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Searched defs:MIER (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h10220 …__IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x… member
11201 …__IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x… member
DRV32M1_zero_riscy.h10364 …__IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x… member
11345 …__IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x… member