1 /* 2 * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __DEVICE_CFG_H__ 18 #define __DEVICE_CFG_H__ 19 20 /** 21 * \file device_cfg.h 22 * \brief 23 * This is the device configuration file with only used peripherals 24 * defined and configured via the secure and/or non-secure base address. 25 */ 26 27 /* ARM Memory Protection Controller (MPC) */ 28 #define MPC_VM0_S 29 #define MPC_VM1_S 30 31 /* ARM Peripheral Protection Controllers (PPC) */ 32 #define PPC_RSS_MAIN0_S 33 #define PPC_RSS_MAIN_EXP0_S 34 #define PPC_RSS_MAIN_EXP1_S 35 #define PPC_RSS_MAIN_EXP2_S 36 #define PPC_RSS_MAIN_EXP3_S 37 #define PPC_RSS_PERIPH0_S 38 #define PPC_RSS_PERIPH1_S 39 #define PPC_RSS_PERIPH_EXP0_S 40 #define PPC_RSS_PERIPH_EXP1_S 41 #define PPC_RSS_PERIPH_EXP2_S 42 #define PPC_RSS_PERIPH_EXP3_S 43 44 /* ARM ATU */ 45 #define ATU_S 46 47 /* ARM UART PL011 */ 48 #define DEFAULT_UART_BAUDRATE 115200 49 #define UART0_PL011_S 50 #define UART0_PL011_NS 51 52 /** System Counter Armv8-M */ 53 #define SYSCOUNTER_CNTRL_ARMV8_M_S 54 #define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S 55 56 /** 57 * Arbitrary scaling values for test purposes 58 */ 59 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u 60 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u 61 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u 62 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u 63 64 65 /* System Timer Armv8-M */ 66 #define SYSTIMER0_ARMV8_M_S 67 68 #define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (32000000ul) 69 70 /* MHU */ 71 #define MHU_AP_TO_RSS 72 #define MHU_RSS_TO_AP 73 #define MHU_SCP_TO_RSS 74 #define MHU_RSS_TO_SCP 75 76 /* Arm KMU */ 77 #define KMU_S 78 79 /* Arm LCM */ 80 #define LCM_S 81 82 /* DMA350 defines */ 83 #define DMA350_DMA0_S 84 #define DMA350_DMA0_CHANNEL_COUNT 4 85 #define DMA350_DMA0_CH0_S 86 #define DMA350_DMA0_CH1_S 87 #define DMA350_DMA0_CH2_S 88 #define DMA350_DMA0_CH3_S 89 90 #endif /* __DEVICE_CFG_H__ */ 91
