1 /*! 2 \file gd32a50x_mfcom.h 3 \brief MFCOM driver 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50X 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_MFCOM_H 36 #define GD32A50X_MFCOM_H 37 38 #include "gd32a50x.h" 39 40 /* MFCOM definitions */ 41 #define MFCOM MFCOM_BASE /*!< MFCOM base address */ 42 43 /* registers definitions */ 44 #define MFCOM_CTL REG32(MFCOM + 0x00000000U) /*!< MFCOM control register */ 45 #define MFCOM_PINDATA REG32(MFCOM + 0x00000004U) /*!< MFCOM pin data register */ 46 #define MFCOM_SSTAT REG32(MFCOM + 0x00000008U) /*!< MFCOM shifter status register */ 47 #define MFCOM_SERR REG32(MFCOM + 0x0000000CU) /*!< MFCOM shifter error register */ 48 #define MFCOM_TMSTAT REG32(MFCOM + 0x00000010U) /*!< MFCOM timer status register */ 49 #define MFCOM_SSIEN REG32(MFCOM + 0x00000018U) /*!< MFCOM shifter status interrupt enable register */ 50 #define MFCOM_SEIEN REG32(MFCOM + 0x0000001CU) /*!< MFCOM shifter error interrupt enable register */ 51 #define MFCOM_TMSIEN REG32(MFCOM + 0x00000020U) /*!< MFCOM timer status interrupt enable register */ 52 #define MFCOM_SSDMAEN REG32(MFCOM + 0x00000028U) /*!< MFCOM shifter status dma enable register */ 53 #define MFCOM_SCTL(x) REG32(MFCOM + 0x00000080U + (x)*4U) /*!< MFCOM shifter x control register */ 54 #define MFCOM_SCFG(x) REG32(MFCOM + 0x00000100U + (x)*4U) /*!< MFCOM shifter x configuration register */ 55 #define MFCOM_SBUF(x) REG32(MFCOM + 0x00000200U + (x)*4U) /*!< MFCOM shifter buffer x register */ 56 #define MFCOM_SBUFBIS(x) REG32(MFCOM + 0x00000280U + (x)*4U) /*!< MFCOM shifter buffer x bit swapped register */ 57 #define MFCOM_SBUFBYS(x) REG32(MFCOM + 0x00000300U + (x)*4U) /*!< MFCOM shifter buffer x byte swapped register */ 58 #define MFCOM_SBUFBBS(x) REG32(MFCOM + 0x00000380U + (x)*4U) /*!< MFCOM shifter buffer x bit byte swapped register */ 59 #define MFCOM_TMCTL(x) REG32(MFCOM + 0x00000400U + (x)*4U) /*!< MFCOM timer x control register */ 60 #define MFCOM_TMCFG(x) REG32(MFCOM + 0x00000480U + (x)*4U) /*!< MFCOM timer x configuration register */ 61 #define MFCOM_TMCMP(x) REG32(MFCOM + 0x00000500U + (x)*4U) /*!< MFCOM timer x compare register */ 62 63 /* bits definitions */ 64 /* MFCOM_CTL */ 65 #define MFCOM_CTL_MFCOMEN BIT(0) /*!< MFCOM enable */ 66 #define MFCOM_CTL_SWRSTEN BIT(1) /*!< software reset enable */ 67 68 /* MFCOM_PINDATA */ 69 #define MFCOM_PINDATA_PDATA BITS(0,7) /*!< input data of pins */ 70 71 /* MFCOM_SSTAT */ 72 #define MFCOM_SSTAT_SSTAT BITS(0,3) /*!< shifter x status flag */ 73 74 /* MFCOM_SERR */ 75 #define MFCOM_SERR_SERR BITS(0,3) /*!< shifter x error flags */ 76 77 /* MFCOM_TMSTAT */ 78 #define MFCOM_TMSTAT_TMSTAT BITS(0,3) /*!< timer x status flags */ 79 80 /* MFCOM_SSIEN */ 81 #define MFCOM_SSIEN_SSIEN BITS(0,3) /*!< shifter status interrupt enable */ 82 83 /* MFCOM_TMSIEN */ 84 #define MFCOM_TMSIEN_TMSIEN BITS(0,3) /*!< timer status interrupt enable */ 85 86 /* MFCOM_SSDMAEN */ 87 #define MFCOM_SSDMAEN_SSDMAEN BITS(0,3) /*!< shifter status DMA enable */ 88 89 /* MFCOM_SCTLx */ 90 #define MFCOM_SCTL_SMOD BITS(0,2) /*!< shifter mode */ 91 #define MFCOM_SCTL_SPPL BIT(7) /*!< shifter pin polarity */ 92 #define MFCOM_SCTL_SPSEL BITS(8,10) /*!< shifter pin select */ 93 #define MFCOM_SCTL_SPCFG BITS(16,17) /*!< shifter pin configuration */ 94 #define MFCOM_SCTL_TMPL BIT(23) /*!< timer polarity */ 95 #define MFCOM_SCTL_TMSEL BITS(24,25) /*!< timer select */ 96 97 /* MFCOM_SCFGx */ 98 #define MFCOM_SCFG_SSTART BITS(0,1) /*!< shifter start bit */ 99 #define MFCOM_SCFG_SSTOP BITS(4,5) /*!< shifter stop bit */ 100 #define MFCOM_SCFG_INSRC BIT(8) /*!< input source */ 101 102 /* MFCOM_SBUFx */ 103 #define MFCOM_SBUFx_SBUF BITS(0,31) /*!< shift buffer */ 104 105 /* MFCOM_SBUFBISx */ 106 #define MFCOM_SBUFBISx_SBUFBIS BITS(0,31) /*!< shift buffer bit swapped */ 107 108 /* MFCOM_SBUFBYSx */ 109 #define MFCOM_SBUFBYSx_SBUFBYS BITS(0,31) /*!< shift buffer byte swapped */ 110 111 /* MFCOM_SBUFBBSx */ 112 #define MFCOM_SBUFBBSx_SBUFBBS BITS(0,31) /*!< shift buffer bit byte swapped */ 113 114 /* MFCOM_TMCTLx */ 115 #define MFCOM_TMCTL_TMMOD BITS(0,1) /*!< timer mode */ 116 #define MFCOM_TMCTL_TMPPL BIT(7) /*!< timer pin polarity */ 117 #define MFCOM_TMCTL_TMPSEL BITS(8,10) /*!< timer pin select */ 118 #define MFCOM_TMCTL_TMPCFG BITS(16,17) /*!< timer pin configuration */ 119 #define MFCOM_TMCTL_TRIGSRC BIT(22) /*!< trigger source */ 120 #define MFCOM_TMCTL_TRIGPL BIT(23) /*!< trigger polarity */ 121 #define MFCOM_TMCTL_TRIGSEL BITS(24,27) /*!< trigger select */ 122 123 /* MFCOM_TMCFGx */ 124 #define MFCOM_TMCFG_TMSTART BIT(1) /*!< timer start bit */ 125 #define MFCOM_TMCFG_TMSTOP BITS(4,5) /*!< timer stop bit */ 126 #define MFCOM_TMCFG_TMEN BITS(8,10) /*!< timer enable source */ 127 #define MFCOM_TMCFG_TMDIS BITS(12,14) /*!< timer disable source */ 128 #define MFCOM_TMCFG_TMRST BITS(16,18) /*!< timer reset source */ 129 #define MFCOM_TMCFG_TMDEC BITS(20,21) /*!< timer decrement source */ 130 #define MFCOM_TMCFG_TMOUT BITS(24,25) /*!< timer output select */ 131 132 /* MFCOM_TMCMPx */ 133 #define MFCOM_TMCMPx_TMCVALUE BITS(0,31) /*!< timer compare value */ 134 135 /* constants definitions */ 136 /* MFCOM timer init parameter struct definitions */ 137 typedef struct 138 { 139 /* trigger */ 140 uint32_t trigger_select; /*!< the internal trigger selection */ 141 uint32_t trigger_polarity; /*!< trigger polarity */ 142 /* pin */ 143 uint32_t pin_config; /*!< timer pin configuration */ 144 uint32_t pin_select; /*!< timer pin number select */ 145 uint32_t pin_polarity; /*!< timer pin polarity */ 146 /* timer */ 147 uint32_t mode; /*!< timer work mode */ 148 uint32_t output; /*!< configures the initial state of the timer output and 149 whether it is affected by the timer reset */ 150 uint32_t decrement; /*!< configures the source of the timer decrement and the 151 source of the shift clock */ 152 uint32_t reset; /*!< configures the condition that causes the timer counter 153 (and optionally the timer output) to be reset */ 154 uint32_t disable; /*!< configures the condition that causes the timer to be 155 disabled and stop decrementing */ 156 uint32_t enable; /*!< configures the condition that causes the timer to be 157 enabled and start decrementing */ 158 uint32_t stopbit; /*!< timer stop bit generation */ 159 uint32_t startbit; /*!< timer start bit generation */ 160 uint32_t compare; /*!< value for timer compare x register */ 161 }mfcom_timer_parameter_struct; 162 163 /* MFCOM shifter init parameter struct definitions */ 164 typedef struct 165 { 166 /* timer */ 167 uint32_t timer_select; /*!< selects which timer is used for controlling the 168 logic/shift register and generating the shift clock */ 169 uint32_t timer_polarity; /*!< timer polarity */ 170 /* pin */ 171 uint32_t pin_config; /*!< shifter pin configuration */ 172 uint32_t pin_select; /*!< shifter pin number select */ 173 uint32_t pin_polarity; /*!< shifter pin polarity */ 174 /* shifter */ 175 uint32_t mode; /*!< configures the mode of the shifter */ 176 uint32_t input_source; /*!< selects the input source for the shifter */ 177 uint32_t stopbit; /*!< shifter stop bit */ 178 uint32_t startbit; /*!< shifter start bit */ 179 }mfcom_shifter_parameter_struct; 180 181 /* MFCOM timer trigger source */ 182 #define TMCTL_TRIGSEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) 183 #define MFCOM_TIMER_TRGSEL_PIN0 (TMCTL_TRIGSEL(0)|MFCOM_TMCTL_TRIGSRC) /*!< pin 0 input selected */ 184 #define MFCOM_TIMER_TRGSEL_SHIFTER0 (TMCTL_TRIGSEL(1)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 0 status flag selected */ 185 #define MFCOM_TIMER_TRGSEL_PIN1 (TMCTL_TRIGSEL(2)|MFCOM_TMCTL_TRIGSRC) /*!< pin 1 selected */ 186 #define MFCOM_TIMER_TRGSEL_TIMER0 (TMCTL_TRIGSEL(3)|MFCOM_TMCTL_TRIGSRC) /*!< timer 0 trigger output selected */ 187 #define MFCOM_TIMER_TRGSEL_PIN2 (TMCTL_TRIGSEL(4)|MFCOM_TMCTL_TRIGSRC) /*!< pin 2 selected */ 188 #define MFCOM_TIMER_TRGSEL_SHIFTER1 (TMCTL_TRIGSEL(5)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 1 status flag selected */ 189 #define MFCOM_TIMER_TRGSEL_PIN3 (TMCTL_TRIGSEL(6)|MFCOM_TMCTL_TRIGSRC) /*!< pin 3 selected */ 190 #define MFCOM_TIMER_TRGSEL_TIMER1 (TMCTL_TRIGSEL(7)|MFCOM_TMCTL_TRIGSRC) /*!< timer 1 trigger output selected */ 191 #define MFCOM_TIMER_TRGSEL_PIN4 (TMCTL_TRIGSEL(8)|MFCOM_TMCTL_TRIGSRC) /*!< pin 4 selected */ 192 #define MFCOM_TIMER_TRGSEL_SHIFTER2 (TMCTL_TRIGSEL(9)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 2 status flag selected */ 193 #define MFCOM_TIMER_TRGSEL_PIN5 (TMCTL_TRIGSEL(10)|MFCOM_TMCTL_TRIGSRC) /*!< pin 5 selected */ 194 #define MFCOM_TIMER_TRGSEL_TIMER2 (TMCTL_TRIGSEL(11)|MFCOM_TMCTL_TRIGSRC) /*!< timer 2 trigger output selected */ 195 #define MFCOM_TIMER_TRGSEL_PIN6 (TMCTL_TRIGSEL(12)|MFCOM_TMCTL_TRIGSRC) /*!< pin 6 selected */ 196 #define MFCOM_TIMER_TRGSEL_SHIFTER3 (TMCTL_TRIGSEL(13)|MFCOM_TMCTL_TRIGSRC) /*!< shifter 3 status flag selected */ 197 #define MFCOM_TIMER_TRGSEL_PIN7 (TMCTL_TRIGSEL(14)|MFCOM_TMCTL_TRIGSRC) /*!< pin 7 selected */ 198 #define MFCOM_TIMER_TRGSEL_TIMER3 (TMCTL_TRIGSEL(15)|MFCOM_TMCTL_TRIGSRC) /*!< timer 3 trigger output selected */ 199 #define MFCOM_TIMER_TRGSEL_EXTERNAL0 TMCTL_TRIGSEL(0) /*!< external trigger0 selected */ 200 #define MFCOM_TIMER_TRGSEL_EXTERNAL1 TMCTL_TRIGSEL(1) /*!< external trigger1 selected */ 201 #define MFCOM_TIMER_TRGSEL_EXTERNAL2 TMCTL_TRIGSEL(2) /*!< external trigger2 selected */ 202 #define MFCOM_TIMER_TRGSEL_EXTERNAL3 TMCTL_TRIGSEL(3) /*!< external trigger3 selected */ 203 204 /* MFCOM timer trigger polarity */ 205 #define MFCOM_TIMER_TRGPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< active high */ 206 #define MFCOM_TIMER_TRGPOL_ACTIVE_LOW MFCOM_TMCTL_TRIGPL /*!< active low */ 207 208 /* MFCOM timer pin config */ 209 #define TMCTL_TMPCFG(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) 210 #define MFCOM_TIMER_PINCFG_INPUT TMCTL_TMPCFG(0) /*!< pin input */ 211 #define MFCOM_TIMER_PINCFG_OPENDRAIN TMCTL_TMPCFG(1) /*!< pin open drain */ 212 #define MFCOM_TIMER_PINCFG_BIDI TMCTL_TMPCFG(2) /*!< pin cascade input/output */ 213 #define MFCOM_TIMER_PINCFG_OUTPUT TMCTL_TMPCFG(3) /*!< pin output */ 214 215 /* MFCOM timer pin select */ 216 #define TMCTL_TMPSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) 217 #define MFCOM_TIMER_PINSEL_PIN0 TMCTL_TMPSEL(0) /*!< timer Pin 0 selected */ 218 #define MFCOM_TIMER_PINSEL_PIN1 TMCTL_TMPSEL(1) /*!< timer Pin 1 selected */ 219 #define MFCOM_TIMER_PINSEL_PIN2 TMCTL_TMPSEL(2) /*!< timer Pin 2 selected */ 220 #define MFCOM_TIMER_PINSEL_PIN3 TMCTL_TMPSEL(3) /*!< timer Pin 3 selected */ 221 #define MFCOM_TIMER_PINSEL_PIN4 TMCTL_TMPSEL(4) /*!< timer Pin 4 selected */ 222 #define MFCOM_TIMER_PINSEL_PIN5 TMCTL_TMPSEL(5) /*!< timer Pin 5 selected */ 223 #define MFCOM_TIMER_PINSEL_PIN6 TMCTL_TMPSEL(6) /*!< timer Pin 6 selected */ 224 #define MFCOM_TIMER_PINSEL_PIN7 TMCTL_TMPSEL(7) /*!< timer Pin 7 selected */ 225 226 /* MFCOM timer pin polarity */ 227 #define MFCOM_TIMER_PINPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< active high */ 228 #define MFCOM_TIMER_PINPOL_ACTIVE_LOW MFCOM_TMCTL_TMPPL /*!< active low */ 229 230 /* MFCOM timer mode */ 231 #define TMCTL_TMMOD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) 232 #define MFCOM_TIMER_DISABLE TMCTL_TMMOD(0) /*!< timer disabled. */ 233 #define MFCOM_TIMER_BAUDMODE TMCTL_TMMOD(1) /*!< dual 8-bit counters baud/bit mode */ 234 #define MFCOM_TIMER_PWMMODE TMCTL_TMMOD(2) /*!< dual 8-bit counters PWM mode */ 235 #define MFCOM_TIMER_16BITCOUNTER TMCTL_TMMOD(3) /*!< single 16-bit counter mode */ 236 237 /* MFCOM timer output */ 238 #define TMCFG_TMOUT(regval) (BITS(24,25) & ((uint32_t)(regval) << 24U)) 239 #define MFCOM_TIMER_OUT_HIGH_EN TMCFG_TMOUT(0) /*!< logic one when enabled and is not affected by timer reset */ 240 #define MFCOM_TIMER_OUT_LOW_EN TMCFG_TMOUT(1) /*!< logic zero when enabled and is not affected by timer reset */ 241 #define MFCOM_TIMER_OUT_HIGH_EN_RESET TMCFG_TMOUT(2) /*!< logic one when enabled and on timer reset */ 242 #define MFCOM_TIMER_OUT_LOW_EN_RESET TMCFG_TMOUT(3) /*!< logic zero when enabled and on timer reset */ 243 244 /* MFCOM timer decrement */ 245 #define TMCFG_TMDEC(regval) (BITS(20,21) & ((uint32_t)(regval) << 20U)) 246 #define MFCOM_TIMER_DEC_CLK_SHIFT_OUT TMCFG_TMDEC(0) /*!< decrement counter on MFCOM clock, shift clock equals timer output */ 247 #define MFCOM_TIMER_DEC_TRIG_SHIFT_OUT TMCFG_TMDEC(1) /*!< decrement counter on trigger input (both edges), shift clock equals timer output */ 248 #define MFCOM_TIMER_DEC_PIN_SHIFT_PIN TMCFG_TMDEC(2) /*!< decrement counter on pin input (both edges), shift clock equals Pin input */ 249 #define MFCOM_TIMER_DEC_TRIG_SHIFT_TRIG TMCFG_TMDEC(3) /*!< decrement counter on trigger input (both edges), shift clock equals trigger input */ 250 251 /* MFCOM timer reset */ 252 #define TMCFG_TMRST(regval) (BITS(16,18) & ((uint32_t)(regval) << 16U)) 253 #define MFCOM_TIMER_RESET_NEVER TMCFG_TMRST(0) /*!< timer never reset */ 254 #define MFCOM_TIMER_RESET_PIN_TIMOUT TMCFG_TMRST(2) /*!< timer reset on timer pin equal to timer output */ 255 #define MFCOM_TIMER_RESET_TRIG_TIMOUT TMCFG_TMRST(3) /*!< timer reset on timer trigger equal to timer output */ 256 #define MFCOM_TIMER_RESET_PIN_RISING TMCFG_TMRST(4) /*!< timer reset on timer pin rising edge */ 257 #define MFCOM_TIMER_RESET_TRIG_RISING TMCFG_TMRST(6) /*!< timer reset on trigger rising edge */ 258 #define MFCOM_TIMER_RESET_TRIG_BOTH TMCFG_TMRST(7) /*!< timer reset on trigger rising or falling edge */ 259 260 /* MFCOM timer disable */ 261 #define TMCFG_TMDIS(regval) (BITS(12,14) & ((uint32_t)(regval) << 12U)) 262 #define MFCOM_TIMER_DISMODE_NEVER TMCFG_TMDIS(0) /*!< timer never disabled */ 263 #define MFCOM_TIMER_DISMODE_PRE_TIMDIS TMCFG_TMDIS(1) /*!< timer disabled on timer x-1 disable */ 264 #define MFCOM_TIMER_DISMODE_COMPARE TMCFG_TMDIS(2) /*!< timer disabled on timer compare */ 265 #define MFCOM_TIMER_DISMODE_COMPARE_TRIGLOW TMCFG_TMDIS(3) /*!< timer disabled on timer compare and trigger Low */ 266 #define MFCOM_TIMER_DISMODE_PINBOTH TMCFG_TMDIS(4) /*!< timer disabled on pin rising or falling edge */ 267 #define MFCOM_TIMER_DISMODE_PINBOTH_TRIGHIGH TMCFG_TMDIS(5) /*!< timer disabled on pin rising or falling edge provided trigger is high */ 268 #define MFCOM_TIMER_DISMODE_TRIGFALLING TMCFG_TMDIS(6) /*!< timer disabled on trigger falling edge */ 269 270 /* MFCOM timer enable */ 271 #define TMCFG_TMEN(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) 272 #define MFCOM_TIMER_ENMODE_ALWAYS TMCFG_TMEN(0) /*!< timer always enabled */ 273 #define MFCOM_TIMER_ENMODE_PRE_TIMEN TMCFG_TMEN(1) /*!< timer enabled on timer x-1 enable */ 274 #define MFCOM_TIMER_ENMODE_TRIGHIGH TMCFG_TMEN(2) /*!< timer enabled on trigger high */ 275 #define MFCOM_TIMER_ENMODE_TRIGHIGH_PINHIGH TMCFG_TMEN(3) /*!< timer enabled on trigger high and Pin high */ 276 #define MFCOM_TIMER_ENMODE_PINRISING TMCFG_TMEN(4) /*!< timer enabled on pin rising edge */ 277 #define MFCOM_TIMER_ENMODE_PINRISING_TRIGHIGH TMCFG_TMEN(5) /*!< timer enabled on pin rising edge and trigger high */ 278 #define MFCOM_TIMER_ENMODE_TRIGRISING TMCFG_TMEN(6) /*!< timer enabled on trigger rising edge */ 279 #define MFCOM_TIMER_ENMODE_TRIGBOTH TMCFG_TMEN(7) /*!< timer enabled on trigger rising or falling edge */ 280 281 /* MFCOM timer stopbit */ 282 #define TMCFG_TMSTOP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) 283 #define MFCOM_TIMER_STOPBIT_DISABLE TMCFG_TMSTOP(0) /*!< stop bit disabled */ 284 #define MFCOM_TIMER_STOPBIT_TIMCMP TMCFG_TMSTOP(1) /*!< stop bit is enabled on timer compare */ 285 #define MFCOM_TIMER_STOPBIT_TIMDIS TMCFG_TMSTOP(2) /*!< stop bit is enabled on timer disable */ 286 #define MFCOM_TIMER_STOPBIT_TIMCMP_TIMDIS TMCFG_TMSTOP(3) /*!< stop bit is enabled on timer compare and timer disable */ 287 288 /* MFCOM timer startbit */ 289 #define MFCOM_TIMER_STARTBIT_DISABLE ((uint32_t)0x00000000U) /*!< Start bit disabled */ 290 #define MFCOM_TIMER_STARTBIT_ENABLE MFCOM_TMCFG_TMSTART /*!< Start bit enabled */ 291 292 /* MFCOM shifter timer select */ 293 #define SCTL_TMSEL(regval) (BITS(24,25) & ((uint32_t)(regval) << 24U)) 294 #define MFCOM_SHIFTER_TIMER0 SCTL_TMSEL(0) /*!< timer0 selected */ 295 #define MFCOM_SHIFTER_TIMER1 SCTL_TMSEL(1) /*!< timer1 selected */ 296 #define MFCOM_SHIFTER_TIMER2 SCTL_TMSEL(2) /*!< timer2 selected */ 297 #define MFCOM_SHIFTER_TIMER3 SCTL_TMSEL(3) /*!< timer3 selected */ 298 299 /* type of timer polarity for shifter control */ 300 #define MFCOM_SHIFTER_TIMPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< shift on positive edge of shift clock */ 301 #define MFCOM_SHIFTER_TIMPOL_ACTIVE_LOW MFCOM_SCTL_TMPL /*!< shift on negative edge of shift clock */ 302 303 /* MFCOM shifter pin config */ 304 #define SCTL_SPCFG(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) 305 #define MFCOM_SHIFTER_PINCFG_INPUT SCTL_SPCFG(0) /*!< pin input */ 306 #define MFCOM_SHIFTER_PINCFG_OPENDRAIN SCTL_SPCFG(1) /*!< pin open drain */ 307 #define MFCOM_SHIFTER_PINCFG_BIDI SCTL_SPCFG(2) /*!< pin cascade input/output */ 308 #define MFCOM_SHIFTER_PINCFG_OUTPUT SCTL_SPCFG(3) /*!< pin output */ 309 310 /* MFCOM shifter pin select */ 311 #define SCTL_SPSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) 312 #define MFCOM_SHIFTER_PINSEL_PIN0 SCTL_SPSEL(0) /*!< shifter pin 0 selected */ 313 #define MFCOM_SHIFTER_PINSEL_PIN1 SCTL_SPSEL(1) /*!< shifter pin 1 selected */ 314 #define MFCOM_SHIFTER_PINSEL_PIN2 SCTL_SPSEL(2) /*!< shifter pin 2 selected */ 315 #define MFCOM_SHIFTER_PINSEL_PIN3 SCTL_SPSEL(3) /*!< shifter pin 3 selected */ 316 #define MFCOM_SHIFTER_PINSEL_PIN4 SCTL_SPSEL(4) /*!< shifter pin 4 selected */ 317 #define MFCOM_SHIFTER_PINSEL_PIN5 SCTL_SPSEL(5) /*!< shifter pin 5 selected */ 318 #define MFCOM_SHIFTER_PINSEL_PIN6 SCTL_SPSEL(6) /*!< shifter pin 6 selected */ 319 #define MFCOM_SHIFTER_PINSEL_PIN7 SCTL_SPSEL(7) /*!< shifter pin 7 selected */ 320 321 /* MFCOM shifter pin polarity */ 322 #define MFCOM_SHIFTER_PINPOL_ACTIVE_HIGH ((uint32_t)0x00000000U) /*!< active high */ 323 #define MFCOM_SHIFTER_PINPOL_ACTIVE_LOW MFCOM_SCTL_SPPL /*!< active low */ 324 325 /* MFCOM shifter mode */ 326 #define SCTL_SMOD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) 327 #define MFCOM_SHIFTER_DISABLE SCTL_SMOD(0) /*!< shifter is disabled */ 328 #define MFCOM_SHIFTER_RECEIVE SCTL_SMOD(1) /*!< receive mode */ 329 #define MFCOM_SHIFTER_TRANSMIT SCTL_SMOD(2) /*!< transmit mode */ 330 #define MFCOM_SHIFTER_MATCH_STORE SCTL_SMOD(4) /*!< match store mode */ 331 #define MFCOM_SHIFTER_MATCH_CONTINUOUS SCTL_SMOD(5) /*!< match continuous mode */ 332 333 /* MFCOM shifter input source */ 334 #define MFCOM_SHIFTER_INSRC_PIN ((uint32_t)0x00000000U) /*!< shifter input from pin */ 335 #define MFCOM_SHIFTER_INSRC_NEXTSHIFTER MFCOM_SCFG_INSRC /*!< shifter input from shifter x+1 */ 336 337 /* MFCOM shifter stopbit */ 338 #define SCFG_SSTOP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) 339 #define MFCOM_SHIFTER_STOPBIT_DISABLE SCFG_SSTOP(0) /*!< disable shifter stop bit */ 340 #define MFCOM_SHIFTER_STOPBIT_LOW SCFG_SSTOP(2) /*!< set shifter stop bit to logic low level */ 341 #define MFCOM_SHIFTER_STOPBIT_HIGH SCFG_SSTOP(3) /*!< set shifter stop bit to logic high level */ 342 343 /* MFCOM shifter startbit */ 344 #define SCFG_SSTART(regval) (BITS(0,1) & ((uint32_t)(regval) << 0U)) 345 #define MFCOM_SHIFTER_STARTBIT_DISABLE SCFG_SSTART(0) /*!< disable shifter start bit, transmitter loads data on enable */ 346 #define MFCOM_SHIFTER_STARTBIT_DISABLE_TXEN SCFG_SSTART(1) /*!< disable shifter start bit, transmitter loads data on first shift */ 347 #define MFCOM_SHIFTER_STARTBIT_LOW SCFG_SSTART(2) /*!< set shifter start bit to logic low level */ 348 #define MFCOM_SHIFTER_STARTBIT_HIGH SCFG_SSTART(3) /*!< set shifter start bit to logic high level */ 349 350 /* MFCOM shifter enum */ 351 #define MFCOM_SHIFTER_0 ((uint32_t)0x00000000U) /*!< MFCOM shifter0 */ 352 #define MFCOM_SHIFTER_1 ((uint32_t)0x00000001U) /*!< MFCOM shifter1 */ 353 #define MFCOM_SHIFTER_2 ((uint32_t)0x00000002U) /*!< MFCOM shifter2 */ 354 #define MFCOM_SHIFTER_3 ((uint32_t)0x00000003U) /*!< MFCOM shifter3 */ 355 356 /* MFCOM timer enum */ 357 #define MFCOM_TIMER_0 ((uint32_t)0x00000000U) /*!< MFCOM timer0 */ 358 #define MFCOM_TIMER_1 ((uint32_t)0x00000001U) /*!< MFCOM timer1 */ 359 #define MFCOM_TIMER_2 ((uint32_t)0x00000002U) /*!< MFCOM timer2 */ 360 #define MFCOM_TIMER_3 ((uint32_t)0x00000003U) /*!< MFCOM timer3 */ 361 362 /* MFCOM read write mode enum */ 363 #define MFCOM_RWMODE_NORMAL ((uint32_t)0x00000000U) /*!< read and write in normal mode */ 364 #define MFCOM_RWMODE_BITSWAP ((uint32_t)0x00000001U) /*!< read and write in bit swapped mode */ 365 #define MFCOM_RWMODE_BYTESWAP ((uint32_t)0x00000002U) /*!< read and write in byte swapped mode */ 366 #define MFCOM_RWMODE_BITBYTESWAP ((uint32_t)0x00000003U) /*!< read and write in bit byte swapped mode */ 367 368 /* function declarations */ 369 /* reset MFCOM */ 370 void mfcom_deinit(void); 371 /* software reset */ 372 void mfcom_software_reset(void); 373 /* enable MFCOM function */ 374 void mfcom_enable(void); 375 /* disable MFCOM function */ 376 void mfcom_disable(void); 377 /* initialize mfcom_timer_parameter_struct with the default values */ 378 void mfcom_timer_struct_para_init(mfcom_timer_parameter_struct* init_struct); 379 /* initialize mfcom_shifter_parameter_struct with the default values */ 380 void mfcom_shifter_struct_para_init(mfcom_shifter_parameter_struct* init_struct); 381 382 /* initialize MFCOM timer */ 383 void mfcom_timer_init(uint32_t timer, mfcom_timer_parameter_struct* init_struct); 384 /* initialize MFCOM shifter */ 385 void mfcom_shifter_init(uint32_t shifter, mfcom_shifter_parameter_struct* init_struct); 386 387 /* configure timer pin mode */ 388 void mfcom_timer_pin_config(uint32_t timer, uint32_t mode); 389 /* configure shifter pin mode */ 390 void mfcom_shifter_pin_config(uint32_t shifter, uint32_t mode); 391 /* enable MFCOM timer in specific mode */ 392 void mfcom_timer_enable(uint32_t timer, uint32_t timermode); 393 /* enable MFCOM shifter in specific mode */ 394 void mfcom_shifter_enable(uint32_t shifter, uint32_t shiftermode); 395 /* disable MFCOM timer */ 396 void mfcom_timer_disable(uint32_t timer); 397 /* disable MFCOM shifter */ 398 void mfcom_shifter_disable(uint32_t shifter); 399 400 /* set the timer compare value */ 401 void mfcom_timer_cmpvalue_set(uint32_t timer, uint32_t compare); 402 /* get the timer compare value */ 403 uint32_t mfcom_timer_cmpvalue_get(uint32_t timer); 404 /* set the timer disable source */ 405 void mfcom_timer_dismode_set(uint32_t timer, uint32_t dismode); 406 407 /* set the shifter stopbit */ 408 void mfcom_shifter_stopbit_set(uint32_t shifter, uint32_t stopbit); 409 /* write MFCOM shifter buffer */ 410 void mfcom_buffer_write(uint32_t shifter, uint32_t data, uint32_t rwmode); 411 /* read MFCOM shifter buffer */ 412 uint32_t mfcom_buffer_read(uint32_t shifter, uint32_t rwmode); 413 /* get MFCOM shifter flag */ 414 FlagStatus mfcom_shifter_flag_get(uint32_t shifter); 415 /* get MFCOM shifter error flag */ 416 FlagStatus mfcom_shifter_error_flag_get(uint32_t shifter); 417 /* get MFCOM timer flag */ 418 FlagStatus mfcom_timer_flag_get(uint32_t timer); 419 420 /* get MFCOM shifter interrupt flag */ 421 FlagStatus mfcom_shifter_interrupt_flag_get(uint32_t shifter); 422 /* get MFCOM shifter error interrupt flag */ 423 FlagStatus mfcom_shifter_error_interrupt_flag_get(uint32_t shifter); 424 /* get MFCOM timer interrupt flag */ 425 FlagStatus mfcom_timer_interrupt_flag_get(uint32_t timer); 426 427 /* clear MFCOM shifter flag */ 428 void mfcom_shifter_flag_clear(uint32_t shifter); 429 /* clear MFCOM shifter error flag */ 430 void mfcom_shifter_error_flag_clear(uint32_t shifter); 431 /* clear MFCOM timer flag */ 432 void mfcom_timer_flag_clear(uint32_t timer); 433 434 /* enable MFCOM shifter interrupt */ 435 void mfcom_shifter_interrupt_enable(uint32_t shifter); 436 /* enable MFCOM shifter error interrupt */ 437 void mfcom_shifter_error_interrupt_enable(uint32_t shifter); 438 /* enable MFCOM timer interrupt */ 439 void mfcom_timer_interrupt_enable(uint32_t timer); 440 /* enable MFCOM shifter dma */ 441 void mfcom_shifter_dma_enable(uint32_t shifter); 442 443 /* disable MFCOM shifter interrupt */ 444 void mfcom_shifter_interrupt_disable(uint32_t shifter); 445 /* disable MFCOM shifter error interrupt */ 446 void mfcom_shifter_error_interrupt_disable(uint32_t shifter); 447 /* disable MFCOM timer interrupt */ 448 void mfcom_timer_interrupt_disable(uint32_t timer); 449 /* disable MFCOM shifter dma */ 450 void mfcom_shifter_dma_disable(uint32_t shifter); 451 452 #endif /* GD32A50X_MFCOM_H */ 453
