1 /*! 2 \file gd32a50x.h 3 \brief general definitions for GD32A50x 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_H 36 #define GD32A50X_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #if !defined (GD32A50X) 43 #error "Please select the target GD32A50X device used in your application (in gd32a50x.h file)" 44 #endif /* undefine GD32A50X tip */ 45 46 /* define value of high speed crystal oscillator (HXTAL) in Hz */ 47 #if !defined HXTAL_VALUE 48 #define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */ 49 #endif /* high speed crystal oscillator value */ 50 51 /* define startup timeout value of high speed crystal oscillator (HXTAL) */ 52 #if !defined (HXTAL_STARTUP_TIMEOUT) 53 #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF) 54 #endif /* high speed crystal oscillator startup timeout */ 55 56 /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ 57 #if !defined (IRC8M_VALUE) 58 #define IRC8M_VALUE ((uint32_t)8000000) 59 #endif /* internal 8MHz RC oscillator value */ 60 61 /* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ 62 #if !defined (IRC8M_STARTUP_TIMEOUT) 63 #define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) 64 #endif /* internal 8MHz RC oscillator startup timeout */ 65 66 /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ 67 #if !defined (IRC40K_VALUE) 68 #define IRC40K_VALUE ((uint32_t)40000) 69 #endif /* internal 40KHz RC oscillator value */ 70 71 /* define value of low speed crystal oscillator (LXTAL)in Hz */ 72 #if !defined (LXTAL_VALUE) 73 #define LXTAL_VALUE ((uint32_t)32768) 74 #endif /* low speed crystal oscillator value */ 75 76 /* GD32E50x firmware library version number V1.0 */ 77 #define __GD32A50X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ 78 #define __GD32A50X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ 79 #define __GD32A50X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ 80 #define __GD32A50X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 81 #define __GD32A50X_STDPERIPH_VERSION ((__GD32A50X_STDPERIPH_VERSION_MAIN << 24)\ 82 |(__GD32A50X_STDPERIPH_VERSION_SUB1 << 16)\ 83 |(__GD32A50X_STDPERIPH_VERSION_SUB2 << 8)\ 84 |(__GD32A50X_STDPERIPH_VERSION_RC)) 85 86 /* configuration of the Cortex-M33 processor and core peripherals */ 87 #define __CM33_REV 0x0003U /*!< Core revision r0p3 */ 88 #define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */ 89 #define __MPU_PRESENT 1U /*!< MPU is present */ 90 #define __VTOR_PRESENT 1U /*!< VTOR is present */ 91 #define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ 92 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 93 #define __FPU_PRESENT 1U /*!< FPU present */ 94 #define __DSP_PRESENT 1U /*!< DSP present */ 95 96 /* define interrupt number */ 97 typedef enum IRQn 98 { 99 /* Cortex-M33 processor exceptions numbers */ 100 NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */ 101 HardFault_IRQn = -13, /*!< hard-fault interrupt */ 102 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M33 memory management interrupt */ 103 BusFault_IRQn = -11, /*!< 5 Cortex-M33 bus fault interrupt */ 104 UsageFault_IRQn = -10, /*!< 6 Cortex-M33 usage fault interrupt */ 105 SVCall_IRQn = -5, /*!< 11 Cortex-M33 sv call interrupt */ 106 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M33 debug monitor interrupt */ 107 PendSV_IRQn = -2, /*!< 14 Cortex-M33 pend sv interrupt */ 108 SysTick_IRQn = -1, /*!< 15 Cortex-M33 system tick interrupt */ 109 /* interrupt numbers */ 110 WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ 111 LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ 112 RTC_IRQn = 3, /*!< RTC Wakeup interrupt */ 113 FMC_IRQn = 4, /*!< FMC interrupt */ 114 RCU_IRQn = 5, /*!< RCU and CTC interrupt */ 115 EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ 116 EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ 117 EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ 118 EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ 119 EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ 120 DMA0_Channel0_IRQn = 11, /*!< DMA0 channel 0 interrupt */ 121 DMA0_Channel1_IRQn = 12, /*!< DMA0 channel 1 interrupt */ 122 DMA0_Channel2_IRQn = 13, /*!< DMA0 channel 2 interrupt */ 123 DMA0_Channel3_IRQn = 14, /*!< DMA0 channel 3 interrupt */ 124 DMA0_Channel4_IRQn = 15, /*!< DMA0 channel 4 interrupt */ 125 DMA0_Channel5_IRQn = 16, /*!< DMA0 channel 5 interrupt */ 126 DMA0_Channel6_IRQn = 17, /*!< DMA0 channel 6 interrupt */ 127 ADC0_1_IRQn = 18, /*!< ADC0_1 interrupts */ 128 CAN0_Message_IRQn = 19, /*!< CAN0 message buffer interrupt */ 129 CAN0_Busoff_IRQn = 20, /*!< CAN0 bus off interrupt */ 130 CAN0_Error_IRQn = 21, /*!< CAN0 error interrupt */ 131 CAN0_FastError_IRQn = 22, /*!< CAN0 fast transmission error interrupt */ 132 CAN0_TEC_IRQn = 23, /*!< CAN0 transmit warning interrupt */ 133 CAN0_REC_IRQn = 24, /*!< CAN0 receive warning interrupt */ 134 CAN0_WKUP_IRQn = 25, /*!< CAN0 wakeup through EXTI Line detection interrupt */ 135 TIMER0_BRK_UP_TRG_CMT_IRQn = 26, /*!< TIMER0 break, update, trigger and commutation interrupt */ 136 TIMER0_Channel_IRQn = 27, /*!< TIMER0 capture compare interrupt */ 137 TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ 138 TIMER19_BRK_UP_TRG_CMT_IRQn = 29, /*!< TIMER19 break, update, trigger and commutation interrupt */ 139 TIMER19_Channel_IRQn = 30, /*!< TIMER19 capture compare interrupt */ 140 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 141 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 142 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 143 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 144 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 145 SPI1_IRQn = 36, /*!< SPI1 interrupt */ 146 USART0_IRQn = 37, /*!< USART0 interrupt */ 147 USART1_IRQn = 38, /*!< USART1 interrupt */ 148 USART2_IRQn = 39, /*!< USART2 interrupt */ 149 EXTI10_15_IRQn = 40, /*!< EXTI line 10 to 15 interrupts */ 150 EXTI5_9_IRQn = 41, /*!< EXTI line 5 to 9 interrupts */ 151 TAMPER_IRQn = 42, /*!< BKP Tamper interrupt */ 152 TIMER20_BRK_UP_TRG_CMT_IRQn = 43, /*!< TIMER20 break, update, trigger and commutation interrupt */ 153 TIMER20_Channel_IRQn = 44, /*!< TIMER20 capture compare interrupt */ 154 TIMER7_BRK_UP_TRG_CMT_IRQn = 45, /*!< TIMER7 break, update, trigger and commutation interrupt */ 155 TIMER7_Channel_IRQn = 46, /*!< TIMER7 capture compare interrupt */ 156 DMAMUX_IRQn = 47, /*!< DMAMUX interrupt */ 157 SRAMC_ECCSE_IRQn = 48, /*!< SYSCFG SRAM ECC single err interrupt */ 158 CMP_IRQn = 49, /*!< Comparator interrupt */ 159 OVD_IRQn = 51, /*!< Over voltage detector interrupt */ 160 TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC interrupt */ 161 TIMER6_IRQn = 55, /*!< TIMER6 interrupt */ 162 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel 0 interrupt */ 163 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel 1 interrupt */ 164 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel 2 interrupt */ 165 DMA1_Channel3_IRQn = 59, /*!< DMA1 channel 3 interrupt */ 166 DMA1_Channel4_IRQn = 60, /*!< DMA1 channel 4 interrupt */ 167 CAN1_WKUP_IRQn = 62, /*!< CAN1 wakeup through EXTI Line detection interrupt */ 168 CAN1_Message_IRQn = 63, /*!< CAN1 message buffer interrupt */ 169 CAN1_Busoff_IRQn = 64, /*!< CAN1 bus off interrupt */ 170 CAN1_Error_IRQn = 65, /*!< CAN1 error interrupt */ 171 CAN1_FastError_IRQn = 66, /*!< CAN1 fast transmission error interrupt */ 172 CAN1_TEC_IRQn = 67, /*!< CAN1 transmit warning interrupt */ 173 CAN1_REC_IRQn = 68, /*!< CAN1 receive warning interrupt */ 174 FPU_IRQn = 69, /*!< FPU interrupt */ 175 MFCOM_IRQn = 70 /*!< MFCOM interrupt */ 176 } IRQn_Type; 177 178 /* includes */ 179 #include "core_cm33.h" 180 #include "system_gd32a50x.h" 181 #include <stdint.h> 182 183 /* enum definitions */ 184 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; 185 typedef enum {RESET = 0, SET = !RESET} FlagStatus; 186 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; 187 188 /* bit operations */ 189 #define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr)) 190 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) 191 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) 192 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) 193 #ifndef BIT 194 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) 195 #endif /* BIT */ 196 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 197 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) 198 199 /* main flash and SRAM memory map */ 200 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ 201 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ 202 203 /* peripheral memory map */ 204 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ 205 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ 206 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ 207 #define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb3 base address */ 208 209 /* advanced peripheral bus 1 memory map */ 210 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ 211 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ 212 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ 213 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ 214 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ 215 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ 216 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ 217 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ 218 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ 219 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ 220 221 /* advanced peripheral bus 2 memory map */ 222 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ 223 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ 224 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ 225 #define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */ 226 #define TRIGSEL_BASE (APB2_BUS_BASE + 0x00008400U) /*!< TRIGSEL base address */ 227 #define CAN_BASE (APB2_BUS_BASE + 0x0000A000U) /*!< CAN base address */ 228 229 /* advanced high performance bus 1 memory map */ 230 #define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ 231 #define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMAMUX base address */ 232 #define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ 233 #define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ 234 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ 235 #define MFCOM_BASE (AHB1_BUS_BASE + 0x00018400U) /*!< MFCOM base address */ 236 237 /* advanced high performance bus 2 memory map */ 238 #define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ 239 240 /* option byte and debug memory map */ 241 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ 242 243 #define DBG_BASE ((uint32_t)0xE0044000U) /*!< DBG base address */ 244 245 /* define marco USE_STDPERIPH_DRIVER */ 246 #if !defined USE_STDPERIPH_DRIVER 247 #define USE_STDPERIPH_DRIVER 248 #endif 249 #ifdef USE_STDPERIPH_DRIVER 250 #include "gd32a50x_libopt.h" 251 #endif /* USE_STDPERIPH_DRIVER */ 252 253 #ifdef __cplusplus 254 } 255 #endif 256 257 #endif /* GD32A50X_H */ 258
