1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC_WKTIMER_API_H
7 #define _MEC_WKTIMER_API_H
8 
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12 
13 #include "mec_defs.h"
14 #include "mec_retval.h"
15 
16 /* Microchip MEC5 Week timer is powered by the VBAT power rail.
17  * It implements three hardware counters to cover intervals from ~30us to over 8 years.
18  * In addition, the week timer includes VBAT power pin outputs.
19  */
20 
21 /* Interfaces to any C modules */
22 #ifdef __cplusplus
23 extern "C"
24 {
25 #endif
26 
27 #define MEC_WKTIMER_MAIN_CLK_FREQ    32768u
28 
29 enum mec_wktmr_cfg_flags {
30     MEC_WKTMR_CFG_ENABLE_POS = 0,
31     MEC_WKTMR_CFG_VCI_PWR_UP_EV_EN_POS,
32     MEC_WKTMR_CFG_SYS_PWR_PRES_EN_POS,
33     MEC_WKTMR_CFG_SUBWK_RELOAD_POS,
34 };
35 
36 enum mec_wktmr_sub_sec_freq {
37     MEC_WKTMR_SUBSEC_DIS = 0,
38     MEC_WKTMR_SUBSEC_2HZ,
39     MEC_WKTMR_SUBSEC_4HZ,
40     MEC_WKTMR_SUBSEC_8HZ,
41     MEC_WKTMR_SUBSEC_16HZ,
42     MEC_WKTMR_SUBSEC_32HZ,
43     MEC_WKTMR_SUBSEC_64HZ,
44     MEC_WKTMR_SUBSEC_128HZ,
45     MEC_WKTMR_SUBSEC_256HZ,
46     MEC_WKTMR_SUBSEC_1024HZ,
47     MEC_WKTMR_SUBSEC_2048HZ,
48     MEC_WKTMR_SUBSEC_4096HZ,
49     MEC_WKTMR_SUBSEC_8192HZ,
50     MEC_WKTMR_SUBSEC_16384HZ,
51     MEC_WKTMR_SUBSEC_32768HZ,
52     MEC_WKTMR_SUBSEC_MAX,
53 };
54 
55 enum mec_wktmr_subwk_clk_source {
56     MEC_WKTMR_SUBWK_SRC_DIS = 0,
57     MEC_WKTMR_SUBWK_SRC_SUB_SEC, /* sub-second frequency */
58     MEC_WKTMR_SUBWK_SRC_SEC_1, /* week counter always counts at 1Hz (one second) */
59     MEC_WKTMR_SUBWK_SRC_SEC_8,  /* bit[3] every 8 seconds */
60     MEC_WKTMR_SUBWK_SRC_SEC_32,  /* bit[5] every 32 seconds */
61     MEC_WKTMR_SUBWK_SRC_SEC_256,  /* bit[7] every 256 seconds */
62     MEC_WKTMR_SUBWK_SRC_SEC_1024,  /* bit[9] every 1024 seconds */
63     MEC_WKTMR_SUBWK_SRC_MAX,
64 };
65 
66 struct mec_wktmr_config {
67     uint32_t one_sec_count;
68     uint32_t one_sec_alarm_count;
69     uint16_t sub_week_reload;
70     uint8_t sub_week_clk_src;
71     uint8_t sub_sec_freq;
72     uint8_t cfg_flags;
73 };
74 
75 /* forward declaration */
76 struct mec_wktmr_regs;
77 
78 int mec_hal_wktimer_init(struct mec_wktmr_regs *regs, struct mec_wktmr_config *cfg);
79 
80 /* BGPO pins */
81 enum mec_wktmr_bgpo_prop {
82     MEC_WKTMR_BGPO_STATE = 0,
83     MEC_WKTMR_BGPO_ENABLE,
84     MEC_WKTMR_BGPO_RESET_EVENT,
85 };
86 
87 /* Control Week Timer BGPO pins.
88  * API has three functions: Enable pin in BGPO hardware, select pins reset power rail,
89  * and set pins output state.
90  * NOTE: BGPO pins multiplexed with GPIO's require GPIO mux set to BGPO function.
91  *
92  * Output state property: Output state is not changed until pin is enabled.
93  * pin_bm is a bit map of pin states to modify.
94  * val_bm is a bit map of pin states (0=low, 1=high)
95  *
96  * Enable BGPO control of a pin
97  * pin_bm is a bit map of pins to enable in BGPO logic
98  * val_bm is a bit map of pins to enable BGPO connection to VBAT power rail.
99  * (0=not enabled, 1=enable and connect to VBAT power rail).
100  *
101  * Select reset event for BGPO pins. BGPO pins will be reset on the selected event.
102  * pin_bm is a bit map of pin reset events to modify
103  * val_bm is a bit map of pin reset events. Bit value = 0(RESET_SYS), 1(RESET_VBAT)
104  */
105 int mec_hal_bgpo_set(struct mec_wktmr_regs *regs, enum mec_wktmr_bgpo_prop prop,
106                      uint16_t pin_bitmap, uint16_t val_bitmap);
107 
108 #ifdef __cplusplus
109 }
110 #endif
111 
112 #endif /* #ifndef _MEC_WKTIMER_API_H */
113