1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC_PECI_API_H
7 #define _MEC_PECI_API_H
8 
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12 
13 #include <device_mec5.h>
14 #include "mec_defs.h"
15 #include "mec_retval.h"
16 
17 /* Interfaces to any C modules */
18 #ifdef __cplusplus
19 extern "C"
20 {
21 #endif
22 
23 /* PECI controller */
24 
25 #define MEC_PECI_NUM_IRQS 1 /* number of IRQ sources per instance */
26 
27 #define MEC_PECI_CORE_CLOCK_MHZ 48
28 
29 struct mec_peci_regs;
30 
31 enum mec_peci_cfg_flags {
32     MEC_PECI_CFG_ENABLE = MEC_BIT(0),
33     MEC_PECI_CFG_RESET = MEC_BIT(1),
34     MEC_PECI_CFG_DIS_BIT_TIME_CLAMP = MEC_BIT(2),
35     MEC_PECI_CFG_INTR_EN = MEC_BIT(4),
36     MEC_PECI_CFG_CLK_DIV = MEC_BIT(5),
37     MEC_PECI_CFG_OBT = MEC_BIT(6),
38     MEC_PECI_CFG_REQ_TIMER = MEC_BIT(7),
39 };
40 
41 enum mec_peci_interrupt_enables {
42     MEC_PECI_IEN_BOF = MEC_BIT(0),
43     MEC_PECI_IEN_EOF = MEC_BIT(1),
44     MEC_PECI_IEN_ERR = MEC_BIT(2),
45     MEC_PECI_IEN_RDYLO = MEC_BIT(4),
46     MEC_PECI_IEN_RDYHI = MEC_BIT(5),
47     MEC_PECI_IEN_WFE = MEC_BIT(9),
48     MEC_PECI_IEN_RFF = MEC_BIT(10),
49 };
50 
51 enum mec_peci_status {
52     MEC_PECI_STS_BOF = MEC_BIT(0),
53     MEC_PECI_STS_EOF = MEC_BIT(1),
54     MEC_PECI_STS_ERR = MEC_BIT(2),
55     MEC_PECI_STS_RDYLO = MEC_BIT(4),
56     MEC_PECI_STS_RDYHI = MEC_BIT(5),
57     MEC_PECI_STS_WFE = MEC_BIT(9),
58     MEC_PECI_STS_RFF = MEC_BIT(10),
59     MEC_PECI_STS_FERR = MEC_BIT(16),
60     MEC_PECI_STS_BERR = MEC_BIT(17),
61     MEC_PECI_STS_REQ_ERR = MEC_BIT(19),
62     MEC_PECI_STS_WROV = MEC_BIT(20),
63     MEC_PECI_STS_WRUN = MEC_BIT(21),
64     MEC_PECI_STS_RDOV = MEC_BIT(22),
65     MEC_PECI_STS_CLKERR = MEC_BIT(23),
66 };
67 
68 struct mec_peci_config {
69     uint16_t clock_div;
70     uint16_t optimal_bit_time;
71     uint16_t request_timer;
72     uint16_t intr_enables;
73 };
74 
75 int mec_hal_peci_init(struct mec_peci_regs *regs, struct mec_peci_config *cfg, uint32_t flags);
76 
77 int mec_hal_peci_ctrl_reset(struct mec_peci_regs *regs, uint8_t assert_reset);
78 int mec_hal_peci_fifo_reset(struct mec_peci_regs *regs, uint8_t assert_reset);
79 int mec_hal_peci_enable(struct mec_peci_regs *regs, uint8_t enable);
80 
81 int mec_hal_peci_global_ien(struct mec_peci_regs *regs, uint8_t enable);
82 int mec_hal_peci_intr_ctrl(struct mec_peci_regs *regs, uint8_t enable, uint16_t intr_bitmap);
83 
84 int mec_hal_peci_set_opt_bit_time(struct mec_peci_regs *regs, uint16_t opt_bit_time);
85 
86 int mec_hal_peci_tx_enable(struct mec_peci_regs *regs, uint8_t enable);
87 
88 uint32_t mec_hal_peci_status(struct mec_peci_regs *regs);
89 uint32_t mec_hal_peci_status_clear(struct mec_peci_regs *regs, uint32_t sts);
90 
91 void mec_hal_peci_pm_save_disable(void);
92 void mec_hal_peci_pm_save_restore(void);
93 
94 int mec_hal_peci_girq_en(struct mec_peci_regs *regs);
95 int mec_hal_peci_girq_dis(struct mec_peci_regs *regs);
96 int mec_hal_peci_girq_clr(struct mec_peci_regs *regs);
97 uint32_t mec_hal_peci_girq_result(struct mec_peci_regs *regs);
98 
99 #ifdef __cplusplus
100 }
101 #endif
102 
103 #endif /* #ifndef _MEC_PECI_API_H */
104