1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_EEPROM_API_H 7 #define _MEC_EEPROM_API_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 #include "device_mec5.h" 14 #include "mec_defs.h" 15 #include "mec_retval.h" 16 17 /* Microchip MEC5 Controller for accessing the internal EEPROM */ 18 19 /* Interfaces to any C modules */ 20 #ifdef __cplusplus 21 extern "C" 22 { 23 #endif 24 25 /* Maximum transfer size is 32 bytes */ 26 #define MEC_HAL_EEPROM_MAX_XFR_LEN 32u 27 28 #define MEC_HAL_EEPROM_CFG_SRST MEC_BIT(0) 29 #define MEC_HAL_EEPROM_CFG_ENABLE MEC_BIT(1) 30 #define MEC_HAL_EEPROM_CFG_DONE_IEN MEC_BIT(2) 31 #define MEC_HAL_EEPROM_CFG_EXE_ERR_IEN MEC_BIT(3) 32 #define MEC_HAL_EEPROM_CFG_LOAD_PSWD MEC_BIT(4) 33 #define MEC_HAL_EEPROM_CFG_LOCK_ON_PSWD MEC_BIT(5) 34 #define MEC_HAL_EEPROM_CFG_LOCK_ON_JTAG MEC_BIT(6) 35 36 enum mec_hal_eeprom_intr_flags { 37 MEC_HAL_EEPROM_INTR_DONE_POS = 0, 38 MEC_HAL_EEPROM_INTR_ERR_POS, 39 }; 40 41 enum mec_hal_eeprom_status { 42 MEC_HAL_EEPROM_STS_DONE_POS = 0, 43 MEC_HAL_EEPROM_STS_ERR_POS, 44 MEC_HAL_EEPROM_STS_ACTIVE_RO_POS = 8, 45 }; 46 47 enum mec_hal_eeprom_ops { 48 MEC_HAL_EEPROM_OP_READ_DATA = 0, 49 MEC_HAL_EEPROM_OP_WRITE_DATA, 50 MEC_HAL_EEPROM_OP_READ_STATUS, 51 MEC_HAL_EEPROM_OP_WRITE_STATUS, 52 }; 53 54 /* 8-bit status from internal EEPROM device */ 55 #define MEC_HAL_EEPROM_FABRIC_WR_BUSY_POS 0 56 #define MEC_HAL_EEPROM_FABRIC_WR_EN_POS 1 57 #define MEC_HAL_EEPROM_FABRIC_WR_PROT_POS 2 58 #define MEC_HAL_EEPROM_FABRIC_WR_PROT_MSK0 0x3u 59 #define MEC_HAL_EEPROM_FABRIC_WR_PROT_MSK \ 60 (MEC_HAL_EEPROM_FABRIC_WR_PROT_MSK0 << MEC_HAL_EEPROM_FABRIC_WR_PROT_POS) 61 62 int mec_hal_eeprom_init(struct mec_eeprom_ctrl_regs *regs, uint32_t flags, uint32_t password); 63 int mec_hal_eeprom_activate(struct mec_eeprom_ctrl_regs *regs, uint8_t enable); 64 65 int mec_hal_eeprom_girq_ctrl(struct mec_eeprom_ctrl_regs *regs, uint8_t enable); 66 int mec_hal_eeprom_girq_status_clr(struct mec_eeprom_ctrl_regs *regs); 67 68 uint32_t mec_hal_eeprom_status(struct mec_eeprom_ctrl_regs *regs); 69 int mec_hal_eeprom_status_clr(struct mec_eeprom_ctrl_regs *regs, uint32_t clrmsk); 70 bool mec_hal_eeprom_is_busy(struct mec_eeprom_ctrl_regs *regs); 71 72 int mec_hal_eeprom_intr_en(struct mec_eeprom_ctrl_regs *regs, uint8_t enable, uint32_t flags); 73 74 int mec_hal_eeprom_set_password(struct mec_eeprom_ctrl_regs *regs, uint32_t password); 75 int mec_hal_eeprom_lock(struct mec_eeprom_ctrl_regs *regs); 76 int mec_hal_eeprom_unlock(struct mec_eeprom_ctrl_regs *regs, uint32_t password); 77 bool mec_hal_eeprom_is_locked(struct mec_eeprom_ctrl_regs *regs); 78 79 int mec_hal_eeprom_buffer_rd(struct mec_eeprom_ctrl_regs *regs, uint8_t *dest, uint32_t nbytes); 80 int mec_hal_eeprom_buffer_wr(struct mec_eeprom_ctrl_regs *regs, const uint8_t *src, 81 uint32_t nbytes); 82 83 int mec_hal_eeprom_xfr_start(struct mec_eeprom_ctrl_regs *regs, uint8_t op, 84 uint32_t offset, uint32_t nbytes); 85 86 #ifdef __cplusplus 87 } 88 #endif 89 90 #endif /* #ifndef _MEC_EEPROM_API_H */ 91
