1 /*
2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #ifndef _MEC_GPIO_API_H
7 #define _MEC_GPIO_API_H
8
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12
13 #include "mec_defs.h"
14 #include "mec_retval.h"
15
16 #ifdef __cplusplus
17 extern "C"
18 {
19 #endif
20
21 #define MEC_GPIO_PORT_0 0
22 #define MEC_GPIO_PORT_1 1
23 #define MEC_GPIO_PORT_2 2
24 #define MEC_GPIO_PORT_3 3
25 #define MEC_GPIO_PORT_4 4
26 #define MEC_GPIO_PORT_5 5
27 #define MEC_GPIO_PORT_MAX 6
28
29 /* GPIO Pin ID enum (octal nomenclature matching spec.) */
30 enum mec_pin_id {
31 /* Port 0(A) */
32 MEC_PIN_0000 = 0,
33 MEC_PIN_0001, MEC_PIN_0002, MEC_PIN_0003, MEC_PIN_0004, MEC_PIN_0005,
34 MEC_PIN_0006, MEC_PIN_0007,
35 MEC_PIN_0010, MEC_PIN_0011, MEC_PIN_0012, MEC_PIN_0013, MEC_PIN_0014,
36 MEC_PIN_0015, MEC_PIN_0016, MEC_PIN_0017,
37 MEC_PIN_0020, MEC_PIN_0021, MEC_PIN_0022, MEC_PIN_0023, MEC_PIN_0024,
38 MEC_PIN_0025, MEC_PIN_0026, MEC_PIN_0027,
39 MEC_PIN_0030, MEC_PIN_0031, MEC_PIN_0032, MEC_PIN_0033, MEC_PIN_0034,
40 MEC_PIN_0035, MEC_PIN_0036, MEC_PIN_0037,
41 /* Port 1(B) */
42 MEC_PIN_0040 = 32U,
43 MEC_PIN_0041, MEC_PIN_0042, MEC_PIN_0043, MEC_PIN_0044, MEC_PIN_0045,
44 MEC_PIN_0046, MEC_PIN_0047,
45 MEC_PIN_0050, MEC_PIN_0051, MEC_PIN_0052, MEC_PIN_0053, MEC_PIN_0054,
46 MEC_PIN_0055, MEC_PIN_0056, MEC_PIN_0057,
47 MEC_PIN_0060, MEC_PIN_0061, MEC_PIN_0062, MEC_PIN_0063, MEC_PIN_0064,
48 MEC_PIN_0065, MEC_PIN_0066, MEC_PIN_0067,
49 MEC_PIN_0070, MEC_PIN_0071, MEC_PIN_0072, MEC_PIN_0073, MEC_PIN_0074,
50 MEC_PIN_0075, MEC_PIN_0076, MEC_PIN_0077,
51 /* Port 2(C) */
52 MEC_PIN_0100 = 64U,
53 MEC_PIN_0101, MEC_PIN_0102, MEC_PIN_0103, MEC_PIN_0104, MEC_PIN_0105,
54 MEC_PIN_0106, MEC_PIN_0107,
55 MEC_PIN_0110, MEC_PIN_0111, MEC_PIN_0112, MEC_PIN_0113, MEC_PIN_0114,
56 MEC_PIN_0115, MEC_PIN_0116, MEC_PIN_0117,
57 MEC_PIN_0120, MEC_PIN_0121, MEC_PIN_0122, MEC_PIN_0123, MEC_PIN_0124,
58 MEC_PIN_0125, MEC_PIN_0126, MEC_PIN_0127,
59 MEC_PIN_0130, MEC_PIN_0131, MEC_PIN_0132, MEC_PIN_0133, MEC_PIN_0134,
60 MEC_PIN_0135, MEC_PIN_0136, MEC_PIN_0137,
61 /* Port 3(D) */
62 MEC_PIN_0140 = 96U,
63 MEC_PIN_0141, MEC_PIN_0142, MEC_PIN_0143, MEC_PIN_0144, MEC_PIN_0145,
64 MEC_PIN_0146, MEC_PIN_0147,
65 MEC_PIN_0150, MEC_PIN_0151, MEC_PIN_0152, MEC_PIN_0153, MEC_PIN_0154,
66 MEC_PIN_0155, MEC_PIN_0156, MEC_PIN_0157,
67 MEC_PIN_0160, MEC_PIN_0161, MEC_PIN_0162, MEC_PIN_0163, MEC_PIN_0164,
68 MEC_PIN_0165, MEC_PIN_0166, MEC_PIN_0167,
69 MEC_PIN_0170, MEC_PIN_0171, MEC_PIN_0172, MEC_PIN_0173, MEC_PIN_0174,
70 MEC_PIN_0175, MEC_PIN_0176, MEC_PIN_0177,
71 /* Port 4(E) */
72 MEC_PIN_0200 = 128U,
73 MEC_PIN_0201, MEC_PIN_0202, MEC_PIN_0203, MEC_PIN_0204, MEC_PIN_0205,
74 MEC_PIN_0206, MEC_PIN_0207,
75 MEC_PIN_0210, MEC_PIN_0211, MEC_PIN_0212, MEC_PIN_0213, MEC_PIN_0214,
76 MEC_PIN_0215, MEC_PIN_0216, MEC_PIN_0217,
77 MEC_PIN_0220, MEC_PIN_0221, MEC_PIN_0222, MEC_PIN_0223, MEC_PIN_0224,
78 MEC_PIN_0225, MEC_PIN_0226, MEC_PIN_0227,
79 MEC_PIN_0230, MEC_PIN_0231, MEC_PIN_0232, MEC_PIN_0233, MEC_PIN_0234,
80 MEC_PIN_0235, MEC_PIN_0236, MEC_PIN_0237,
81 /* Port 5(F) */
82 MEC_PIN_0240 = 160U,
83 MEC_PIN_0241, MEC_PIN_0242, MEC_PIN_0243, MEC_PIN_0244, MEC_PIN_0245,
84 MEC_PIN_0246, MEC_PIN_0247,
85 MEC_PIN_0250, MEC_PIN_0251, MEC_PIN_0252, MEC_PIN_0253, MEC_PIN_0254,
86 MEC_PIN_0255, MEC_PIN_0256, MEC_PIN_0257,
87 MEC_PIN_0260, MEC_PIN_0261, MEC_PIN_0262, MEC_PIN_0263, MEC_PIN_0264,
88 MEC_PIN_0265, MEC_PIN_0266, MEC_PIN_0267,
89 MEC_PIN_0270, MEC_PIN_0271, MEC_PIN_0272, MEC_PIN_0273, MEC_PIN_0274,
90 MEC_PIN_0275, MEC_PIN_0276, MEC_PIN_0277,
91 MEC_PIN_MAX
92 };
93
94 typedef enum mec_pin_id MEC_GPIO_PIN;
95
96 #define MEC_GPIO_CTRL2_OFS 0x500u
97 #define MEC_GPIO_PARIN_OFS 0x300u
98 #define MEC_GPIO_PAROUT_OFS 0x380u
99 #define MEC_GPIO_LOCK_OFS_HI 0x3fcu
100
101 #define MEC_GPIO_CTRL_BASE_ADDR 0x40081000u
102 #define MEC_GPIO_CTRL2_BASE_ADDR (MEC_GPIO_CTRL_BASE_ADDR + MEC_GPIO_CTRL2_OFS)
103 #define MEC_GPIO_PARIN_BASE_ADDR (MEC_GPIO_CTRL_BASE_ADDR + MEC_GPIO_PARIN_OFS)
104 #define MEC_GPIO_PAROUT_BASE_ADDR (MEC_GPIO_CTRL_BASE_ADDR + MEC_GPIO_PAROUT_OFS)
105 /* NOTE: LOCK0 is at top of range */
106 #define MEC_GPIO_LOCK_TOP_ADDR (MEC_GPIO_CTRL_BASE_ADDR + MEC_GPIO_LOCK_OFS_HI)
107
108 #define MEC_GPIO_CTRL_REG_ADDR(pin_id) (((uint32_t)(pin_id) * 4u) + (MEC_GPIO_CTRL_BASE_ADDR))
109 #define MEC_GPIO_CTRL2_REG_ADDR(pin_id) (MEC_GPIO_CTRL_REG_ADDR(pin_id) + (MEC_GPIO_CTRL2_OFS))
110
111 /*
112 * API
113 */
114
115 /* Place any C interfaces here */
116
117 /* GPIO Pin configuration property ID's and values for use with
118 * mec_gpio_get/set_property
119 */
120
121 #define MEC_GPIO_PUD_PROP_ID 0
122 #define MEC_GPIO_PWRGT_PROP_ID 1
123 #define MEC_GPIO_IDET_PROP_ID 2
124 #define MEC_GPIO_OBUFT_PROP_ID 3
125 #define MEC_GPIO_DIR_PROP_ID 4
126 #define MEC_GPIO_OSEL_PROP_ID 5
127 #define MEC_GPIO_FUNC_POL_PROP_ID 6
128 #define MEC_GPIO_MUX_PROP_ID 7
129 #define MEC_GPIO_INPAD_DIS_PROP_ID 8
130 #define MEC_GPIO_CTRL_OUT_VAL_ID 9
131 #define MEC_GPIO_SLEW_RATE_ID 10
132 #define MEC_GPIO_DRV_STR_ID 11
133 #define MEC_GPIO_MAX_PROP_ID 12
134
135 #define MEC_GPIO_PROP_NO_PUD 0u
136 #define MEC_GPIO_PROP_PULL_UP 0x01u
137 #define MEC_GPIO_PROP_PULL_DN 0x02u
138 #define MEC_GPIO_PROP_REPEATER 0x03u
139
140 #define MEC_GPIO_PROP_PWRGT_VTR 0u
141 #define MEC_GPIO_PROP_PWRGT_VCC 0x01u
142 #define MEC_GPIO_PROP_PWRGT_OFF 0x02u
143
144 #define MEC_GPIO_PROP_IDET_LO_LVL 0u
145 #define MEC_GPIO_PROP_IDET_HI_LVL 0x01u
146 #define MEC_GPIO_PROP_IDET_DIS 0x04u
147 #define MEC_GPIO_PROP_IDET_EDGE_UP 0x0Du
148 #define MEC_GPIO_PROP_IDET_EDGE_DN 0x0Eu
149 #define MEC_GPIO_PROP_IDET_EDGE_BOTH 0x0Fu
150
151 #define MEC_GPIO_PROP_PUSH_PULL 0u
152 #define MEC_GPIO_PROP_OPEN_DRAIN 1u
153
154 #define MEC_GPIO_PROP_DIR_IN 0u
155 #define MEC_GPIO_PROP_DIR_OUT 1u
156
157 #define MEC_GPIO_PROP_OSEL_CTRL 0u
158 #define MEC_GPIO_PROP_OSEL_PAROUT 1u
159
160 #define MEC_GPIO_PROP_FUNC_OUT_NON_INV 0u
161 #define MEC_GPIO_PROP_FUNC_OUT_INV 1u
162
163 #define MEC_GPIO_PROP_MUX_GPIO 0u
164 #define MEC_GPIO_PROP_MUX_FUNC1 1u
165 #define MEC_GPIO_PROP_MUX_FUNC2 2u
166 #define MEC_GPIO_PROP_MUX_FUNC3 3u
167 #define MEC_GPIO_PROP_MUX_FUNC4 4u
168 #define MEC_GPIO_PROP_MUX_FUNC5 5u
169 #define MEC_GPIO_PROP_MUX_FUNC6 6u
170 #define MEC_GPIO_PROP_MUX_FUNC7 7u
171
172 #define MEC_GPIO_PROP_INPAD_EN 0u
173 #define MEC_GPIO_PROP_INPAD_DIS 1u
174
175 enum mec_gpio_drive_str {
176 MEC_GPIO_DRIVE_STR_1X = 0,
177 MEC_GPIO_DRIVE_STR_2X,
178 MEC_GPIO_DRIVE_STR_4X,
179 MEC_GPIO_DRIVE_STR_6X,
180 MEC_GPIO_DRIVE_STR_NUM_ELEM,
181 };
182
183 enum mec_gpio_slew_rate {
184 MEC_GPIO_SLEW_RATE_SLOW = 0,
185 MEC_GPIO_SLEW_RATE_FAST,
186 MEC_GPIO_SLEW_RATE_NUM_ELEM,
187 };
188
189 struct mec_gpio_props {
190 uint8_t prop;
191 uint8_t val;
192 };
193
194 /* Pin configuration using a single 32-bit unsigned word */
195 #define MEC5_GPIO_CFG_PULL_POS 0
196 #define MEC5_GPIO_CFG_PULL_MSK 0x3u
197 #define MEC5_GPIO_CFG_PWR_GATE_POS 2
198 #define MEC5_GPIO_CFG_PWR_GATE_MSK 0xcu
199 #define MEC5_GPIO_CFG_OUT_OPEN_DRAIN_POS 4
200 #define MEC5_GPIO_CFG_OUT_OPEN_DRAIN_MSK 0x10
201 #define MEC5_GPIO_CFG_DIR_OUT_POS 5
202 #define MEC5_GPIO_CFG_DIR_OUT_MSK 0x20u
203 #define MEC5_GPIO_CFG_PAR_OUT_EN_POS 6
204 #define MEC5_GPIO_CFG_PAR_OUT_EN_MSK 0x40
205 #define MEC5_GPIO_CFG_FUNC_INV_POS 7
206 #define MEC5_GPIO_CFG_FUNC_INV_MSK 0x80
207 #define MEC5_GPIO_CFG_FUNC_POS 8
208 #define MEC5_GPIO_CFG_FUNC_MSK 0x700
209 #define MEC5_GPIO_CFG_IDET_POS 12
210 #define MEC5_GPIO_CFG_IDET_MSK 0x7000u
211 #define MEC5_GPIO_CFG_INPAD_DIS_POS 15
212 #define MEC5_GPIO_CFG_INPAD_DIS_MSK 0x8000u
213 #define MEC5_GPIO_CFG_DRV_STR_POS 16
214 #define MEC5_GPIO_CFG_DRV_STR_MSK 0x30000u
215 #define MEC5_GPIO_CFG_SLEW_RATE_POS 18
216 #define MEC5_GPIO_CFG_SLEW_RATE_MSK 0x40000u
217 #define MEC5_GPIO_CFG_SET_OUT_VAL_POS 20
218 #define MEC5_GPIO_CFG_SET_OUT_VAL_MSK 0x100000u
219 #define MEC5_GPIO_CFG_OUT_VAL_POS 21
220 #define MEC5_GPIO_CFG_OUT_VAL_MSK 0x200000u
221
222 /* internal weak pulls */
223 #define MEC5_GPIO_CFG_PULL_NONE 0
224 #define MEC5_GPIO_CFG_PULL_UP 0x1u
225 #define MEC5_GPIO_CFG_PULL_DN 0x2u
226 #define MEC5_GPIO_CFG_PULL_KEEPER 0x3u
227
228 #define MEC5_GPIO_CFG_PWRGT_VTR 0
229 #define MEC5_GPIO_CFG_PWRGT_VCC (1u << MEC5_GPIO_CFG_PWR_GATE_POS)
230 /* turn off HW pin pad logic, etc. */
231 #define MEC5_GPIO_CFG_PWRGT_OFF (2u << MEC5_GPIO_CFG_PWR_GATE_POS)
232
233 #define MEC5_GPIO_CFG_OUT_BUF_PUSH_PULL 0
234 #define MEC5_GPIO_CFG_OUT_BUF_OPEN_DRAIN (1u << MEC5_GPIO_CFG_OUT_OPEN_DRAIN_POS)
235
236 #define MEC5_GPIO_CFG_DIR_INPUT 0
237 #define MEC5_GPIO_CFG_DIR_OUTPUT (1u << MEC5_GPIO_CFG_DIR_OUT_POS)
238
239 /* Enable pin output state to be set by the GPIO parallel output register
240 * containing this pin. Otherwise pin output state set in GPIO pin control
241 * register.
242 */
243 #define MEC5_GPIO_CFG_PAR_OUT_DIS 0
244 #define MEC5_GPIO_CFG_PAR_OUT_EN (1u << MEC5_GPIO_CFG_PAR_OUT_EN_POS)
245
246 /* GPIO HW can invert the input and output of an alternate function.
247 * Does not apply when pin configured as GPIO function.
248 */
249 #define MEC5_GPIO_CFG_FUNC_INV_DIS 0
250 #define MEC5_GPIO_CFG_FUNC_INV_EN (1u << MEC5_GPIO_CFG_FUNC_INV_POS)
251
252 #define MEC5_GPIO_CFG_FUNC_GPIO 0
253 #define MEC5_GPIO_CFG_FUNC_ALT1 (1u << MEC5_GPIO_CFG_FUNC_POS)
254 #define MEC5_GPIO_CFG_FUNC_ALT2 (2u << MEC5_GPIO_CFG_FUNC_POS)
255 #define MEC5_GPIO_CFG_FUNC_ALT3 (3u << MEC5_GPIO_CFG_FUNC_POS)
256 #define MEC5_GPIO_CFG_FUNC_ALT4 (4u << MEC5_GPIO_CFG_FUNC_POS)
257 #define MEC5_GPIO_CFG_FUNC_ALT5 (5u << MEC5_GPIO_CFG_FUNC_POS)
258 #define MEC5_GPIO_CFG_FUNC_ALT6 (6u << MEC5_GPIO_CFG_FUNC_POS)
259 #define MEC5_GPIO_CFG_FUNC_ALT7 (7u << MEC5_GPIO_CFG_FUNC_POS)
260 #define MEC5_GPIO_CFG_FUNC_ALT(n) \
261 (((uint32_t)(n) & 0x7u) << MEC5_GPIO_CFG_FUNC_POS)
262
263 #define MEC5_GPIO_CFG_IDET_DIS 0
264 #define MEC5_GPIO_CFG_IDET_LVL_LO (1u << MEC5_GPIO_CFG_IDET_POS)
265 #define MEC5_GPIO_CFG_IDET_LVL_HI (2u << MEC5_GPIO_CFG_IDET_POS)
266 #define MEC5_GPIO_CFG_IDET_RISING_EDG (3 << MEC5_GPIO_CFG_IDET_POS)
267 #define MEC5_GPIO_CFG_IDET_FALLING_EDG (4u << MEC5_GPIO_CFG_IDET_POS)
268 #define MEC5_GPIO_CFG_IDET_BOTH_EDG (5u << MEC5_GPIO_CFG_IDET_POS)
269
270 /* Set GPIO pad drive strength as a multiple of the base drive strength based
271 * on the pad type.
272 * PIO-12 pads base drive strength is 2mA
273 * PIO-24 pads base drive strength is 4mA
274 */
275 #define MEC5_GPIO_CFG_DRV_STR_1X 0
276 #define MEC5_GPIO_CFG_DRV_STR_2X (1u << MEC5_GPIO_CFG_DRV_STR_POS)
277 #define MEC5_GPIO_CFG_DRV_STR_4X (2u << MEC5_GPIO_CFG_DRV_STR_POS)
278 #define MEC5_GPIO_CFG_DRV_STR_6X (3u << MEC5_GPIO_CFG_DRV_STR_POS)
279
280 /* GPIO pad slew rate. NOTE: eSPI pins do not support slew rate adjustment */
281 #define MEC5_GPIO_CFG_SLEW_RATE_SLOW 0
282 #define MEC5_GPIO_CFG_SLEW_RATE_FAST (1u << MEC5_GPIO_CFG_SLEW_RATE_POS)
283
284 /* Set pin output value before enabling the pin for output.
285 * This property has both an enable flag and output state value.
286 */
287 #define MEC5_GPIO_CFG_SET_OUT_VAL_DIS 0
288 #define MEC5_GPIO_CFG_SET_OUT_VAL_EN (1u << MEC5_GPIO_CFG_SET_OUT_VAL_POS)
289
290 #define MEC5_GPIO_CFG_OUT_VAL_LO 0
291 #define MEC5_GPIO_CFG_OUT_VAL_HI (1u << MEC5_GPIO_CFG_OUT_VAL_POS)
292
293
mec_hal_gpio_pin_num_nc(uint8_t port,uint8_t pin_port_pos)294 static inline uint32_t mec_hal_gpio_pin_num_nc(uint8_t port, uint8_t pin_port_pos)
295 {
296 return ((uint32_t)(port & 0x7u) * 32u) + (pin_port_pos & 0x1fu);
297 }
298
299 int mec_hal_gpio_pin_num(uint8_t port, uint8_t pin_port_pos, uint32_t *pin_num);
300 int mec_hal_gpio_pin_valid(uint32_t pin);
301 int mec_hal_gpio_port_pin_valid(uint8_t port, uint8_t pin_port_pos);
302 int mec_hal_gpio_port_valid_mask(uint8_t port, uint32_t *valid_msk);
303
304 int mec_hal_gpio_pin_config(uint32_t pin, uint32_t config);
305
306 /* Extract property from 32-bit GPIO control value */
307 int mec_hal_gpio_get_ctrl_property(uint32_t ctrl, uint8_t prop_id, uint8_t *prop);
308
309 /* Modify property of 32-bit GPIO control register value passed in ctrl.
310 * Returns modified value. Does not touch HW. If property is out of range,
311 * return unmodified ctrl.
312 */
313 uint32_t mec_hal_gpio_set_ctrl_property(uint32_t ctrl, uint8_t prop_id, uint8_t val);
314
315 /* Get specified property from GPIO Control register */
316 int mec_hal_gpio_get_property(uint32_t pin, uint8_t prop_id, uint8_t *prop);
317 /* Modify specified propertie(s) of GPIO Control register */
318 int mec_hal_gpio_set_property(uint32_t pin, uint8_t prop_id, uint8_t new_val);
319 int mec_hal_gpio_set_props(uint32_t pin, const struct mec_gpio_props *gprops, size_t nprops);
320
321 /* returns 1 if pin direction is configured as output else 0 */
322 int mec_hal_gpio_is_output(uint32_t pin);
323
324 /* disable a pin: turns off input pad */
325 int mec_hal_gpio_disable_input_pad(uint32_t pin);
326 /* enable a pin: turns on input pad */
327 int mec_hal_gpio_enable_input_pad(uint32_t pin);
328
329 /* Check if pin control registers are locked */
330 int mec_hal_gpio_is_locked(uint32_t pin);
331
332 /* Get address of GPIO Control and Control2 registers */
333 uintptr_t mec_hal_gpio_ctrl_addr(uint32_t pin);
334 uintptr_t mec_hal_gpio_ctrl2_addr(uint32_t pin);
335
336 /* Get/Set GPIO Control configuration b[15:0] */
337 int mec_hal_gpio_get_config(uint32_t pin, uint32_t *config);
338 int mec_hal_gpio_set_config(uint32_t pin, uint32_t new_cfg);
339 int mec_hal_gpio_set_config_mask(uint32_t pin, uint32_t new_cfg, uint32_t mask);
340
341 /* Get/Set GPIO Control full register */
342 int mec_hal_gpio_get_ctrl(uint32_t pin, uint32_t *ctrl);
343 int mec_hal_gpio_set_ctrl(uint32_t pin, uint32_t new_ctrl);
344 int mec_hal_gpio_set_ctrl_mask(uint32_t pin, uint32_t val, uint32_t mask);
345
346 uint32_t mec_hal_gpio_get_ctrl_nc(uint32_t pin);
347 void mec_hal_gpio_set_ctrl_nc(uint32_t pin, uint32_t ctrl_val);
348
349 uint32_t mec_hal_gpio_get_ctrl_nc(uint32_t pin);
350 void mec_hal_gpio_set_ctrl_nc(uint32_t pin, uint32_t ctrl_val);
351 uint32_t mec_hal_gpio_port_get_ctrl_nc(uint8_t port, uint8_t port_pin_pos);
352 void mec_hal_gpio_port_set_ctrl_nc(uint8_t port, uint8_t port_pin_pos, uint32_t ctrl_val);
353
354 int mec_hal_gpio_get_ctrl2(uint32_t pin, uint32_t *ctrl2);
355 int mec_hal_gpio_set_ctrl2(uint32_t pin, uint32_t new_ctrl2);
356 int mec_hal_gpio_ctrl2_mask(const uint32_t pin, uint32_t val, uint32_t mask);
357
358 int mec_hal_gpio_get_slew_rate(uint32_t pin);
359 int mec_hal_gpio_set_slew_rate(uint32_t pin, enum mec_gpio_slew_rate slew_rate);
360
361 int mec_hal_gpio_get_drive_strength(uint32_t pin);
362 int mec_hal_gpio_set_drive_strength(uint32_t pin, enum mec_gpio_drive_str drive_str);
363
364 int mec_hal_gpio_alt_out(const uint32_t pin, uint8_t new_val);
365 int mec_hal_gpio_alt_out_toggle(const uint32_t pin);
366
367 int mec_hal_gpio_pad_in(const uint32_t pin, uint8_t *padin);
368
369 int mec_hal_gpio_par_in(const uint32_t pin, uint8_t *pinval);
370 int mec_hal_gpio_par_out(const uint32_t pin, const uint8_t pin_state);
371
372 int mec_hal_gpio_parin_port(const uint8_t port, uint32_t *val);
373 int mec_hal_gpio_parin_by_pin(uint32_t pin, uint32_t *val);
374 int mec_hal_gpio_parout_port_get(const uint8_t port, uint32_t *val);
375 int mec_hal_gpio_parout_port_get_by_pin(uint32_t pin, uint32_t *val);
376 int mec_hal_gpio_parout_port(const uint8_t port, const uint32_t newval);
377 int mec_hal_gpio_parout_port_set_bits(const uint8_t port, const uint32_t mask);
378 int mec_hal_gpio_parout_port_xor(const uint8_t port, const uint32_t xormask);
379 int mec_hal_gpio_parout_port_mask(const uint8_t port, const uint32_t newval,
380 const uint32_t mask);
381
382 int mec_hal_gpio_port_ia_ctrl(uint8_t port, uint8_t enable);
383 int mec_hal_gpio_port_pin_ia_enable(uint8_t port, uint8_t port_pin_pos, uint8_t enable);
384 int mec_hal_gpio_pin_ia_enable(uint8_t pin, uint8_t enable);
385 int mec_hal_gpio_pin_ia_status_clr(uint8_t pin);
386 int mec_hal_gpio_port_pin_ia_status_clr(uint8_t port, uint8_t port_pin_pos);
387 int mec_hal_gpio_port_ia_status(uint8_t port, uint32_t *status);
388 int mec_hal_gpio_port_ia_status_clr_mask(uint8_t port, uint32_t mask);
389 int mec_hal_gpio_port_ia_result(uint8_t port, uint32_t *result);
390
391 /* VCI capable GPIO pins */
392 bool mec_hal_gpio_pin_is_vci_capable(uint16_t pin);
393 int mec_hal_gpio_vci_disable(uint16_t pin);
394 int mec_hal_gpio_vci_get_func(uint16_t pin, uint8_t *func);
395
396 #ifdef __cplusplus
397 }
398 #endif
399
400 #endif /* #ifndef _MEC_GPIO_API_H */
401
