1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_EMI_API_H 7 #define _MEC_EMI_API_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 #include "mec_defs.h" 14 #include "mec_retval.h" 15 16 /* Interfaces to any C modules */ 17 #ifdef __cplusplus 18 extern "C" 19 { 20 #endif 21 22 enum mec_emi_mbox { 23 MEC_EMI_EC_TO_HOST_MBOX = 0, 24 MEC_EMI_HOST_TO_EC_MBOX, 25 }; 26 27 enum mec_emi_flags { 28 MEC_EMI_RESET = MEC_BIT(0), 29 }; 30 31 enum mec_emi_swi { 32 MEC_EMI_SWI_1 = MEC_BIT(1), 33 MEC_EMI_SWI_2 = MEC_BIT(2), 34 MEC_EMI_SWI_3 = MEC_BIT(3), 35 MEC_EMI_SWI_4 = MEC_BIT(4), 36 MEC_EMI_SWI_5 = MEC_BIT(5), 37 MEC_EMI_SWI_6 = MEC_BIT(6), 38 MEC_EMI_SWI_7 = MEC_BIT(7), 39 MEC_EMI_SWI_8 = MEC_BIT(8), 40 MEC_EMI_SWI_9 = MEC_BIT(9), 41 MEC_EMI_SWI_10 = MEC_BIT(10), 42 MEC_EMI_SWI_11 = MEC_BIT(11), 43 MEC_EMI_SWI_12 = MEC_BIT(12), 44 MEC_EMI_SWI_13 = MEC_BIT(13), 45 MEC_EMI_SWI_14 = MEC_BIT(14), 46 MEC_EMI_SWI_15 = MEC_BIT(15), 47 }; 48 49 enum mec_emi_mem_region { 50 MEC_EMI_MEM_REGION_0 = 0, 51 MEC_EMI_MEM_REGION_1, 52 MEC_EMI_MEM_REGION_NUM, 53 }; 54 55 struct mec_emi_regs; /* forward declaration */ 56 57 int mec_hal_emi_girq_ctrl(struct mec_emi_regs *base, uint8_t enable); 58 int mec_hal_emi_girq_clr(struct mec_emi_regs *base); 59 uint32_t mec_hal_emi_girq_result(struct mec_emi_regs *base); 60 61 int mec_hal_emi_init(struct mec_emi_regs *regs, uint32_t flags); 62 63 #define MEC_EMI_MEMR_CFG_RW_MSK 0xfffcu 64 #define MEC_EMI_MEMR_CFG_RDSZ_POS 0 65 #define MEC_EMI_MEMR_CFG_RDSZ_MSK (MEC_EMI_MEMR_CFG_RW_MSK) 66 #define MEC_EMI_MEMR_CFG_WRSZ_POS 16 67 #define MEC_EMI_MEMR_CFG_WRSZ_MSK ((MEC_EMI_MEMR_CFG_RW_MSK) << MEC_EMI_MEMR_CFG_WRSZ_POS) 68 69 #define MEC_EMI_MEMR_CFG_SIZES(rsz, wsz) \ 70 ((((uint32_t)(rsz) & MEC_EMI_MEMR_CFG_RW_MSK) << MEC_EMI_MEMR_CFG_RDSZ_POS) |\ 71 (((uint32_t)(wsz) & MEC_EMI_MEMR_CFG_RW_MSK) << MEC_EMI_MEMR_CFG_WRSZ_POS)) 72 73 /* Configure EMI memory region. 74 * region is MEC_EMI_MEM_REGION_0 or MEC_EMI_MEM_REGION_1 75 * mbase is memory region address in SRAM aligned >= 4 bytes 76 * rwszs b[15:0] = readable sub-region size in bytes. Must be a multiple of 4 bytes. 77 * rwszs b[31:16] = writeable sub-region size in bytes. Must be a multiple of 4 bytes. 78 * rwszs == 0 disables the region 79 * 80 */ 81 int mec_hal_emi_mem_region_config(struct mec_emi_regs *regs, uint8_t region, 82 uint32_t mbase, uint32_t rwszs); 83 84 int mec_hal_emi_mbox_wr(struct mec_emi_regs *regs, uint8_t host_to_ec, uint8_t val); 85 uint8_t mec_hal_emi_mbox_rd(struct mec_emi_regs *regs, uint8_t host_to_ec); 86 87 int mec_hal_emi_swi_set_one(struct mec_emi_regs *regs, uint8_t swi_pos); 88 int mec_hal_emi_swi_set(struct mec_emi_regs *regs, uint16_t swi_bit_map); 89 int mec_hal_emi_swi_host_clear_enable(struct mec_emi_regs *regs, uint16_t mask, uint16_t enable); 90 91 int mec_hal_emi_is_appid(struct mec_emi_regs *regs, uint8_t appid); 92 int mec_hal_emi_clear_appid(struct mec_emi_regs *regs, uint8_t appid); 93 int mec_hal_emi_clear_all_appid(struct mec_emi_regs *regs); 94 95 #ifdef __cplusplus 96 } 97 #endif 98 99 #endif /* #ifndef _MEC_EMI_API_H */ 100
