1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_EEPROM_CTRL_V1_H 7 #define _MEC5_EEPROM_CTRL_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief EEPROM Controller interface to optional internal EEPROM (MEC_EEPROM_CTRL0) 15 */ 16 17 typedef struct mec_eeprom_ctrl_regs { /*!< (@ 0x40002C00) MEC_EEPROM_CTRL0 Structure */ 18 __IOM uint32_t MODE; /*!< (@ 0x00000000) Mode register */ 19 __IOM uint32_t EXE; /*!< (@ 0x00000004) Execute register */ 20 __IOM uint32_t STATUS; /*!< (@ 0x00000008) Controller status register */ 21 __IOM uint32_t INTR_EN; /*!< (@ 0x0000000C) Interrupt enable register */ 22 __OM uint32_t PSWD; /*!< (@ 0x00000010) EEPROM password register is write-once and stores 23 a 31-bit password to lock the controller */ 24 __OM uint32_t UNLOCK; /*!< (@ 0x00000014) EEPROM unlock register. Value written is compared 25 to stored password and access is unlocked 26 on match */ 27 __IOM uint32_t LOCK; /*!< (@ 0x00000018) EEPROM lock enable register. Enable lock feature */ 28 __IM uint32_t RESERVED; 29 __IOM uint32_t DATA[8]; /*!< (@ 0x00000020) EEPROM data buffer register array for the 32-byte 30 data buffer */ 31 } MEC_EEPROM_CTRL_Type; /*!< Size = 64 (0x40) */ 32 33 /** @} */ /* End of group Device_Peripheral_peripherals */ 34 35 /** @addtogroup PosMask_peripherals 36 * @{ 37 */ 38 /* ========================================================= MODE ========================================================== */ 39 #define MEC_EEPROM_CTRL_MODE_ACTV_Pos (0UL) /*!< ACTV (Bit 0) */ 40 #define MEC_EEPROM_CTRL_MODE_ACTV_Msk (0x1UL) /*!< ACTV (Bitfield-Mask: 0x01) */ 41 #define MEC_EEPROM_CTRL_MODE_SRST_Pos (1UL) /*!< SRST (Bit 1) */ 42 #define MEC_EEPROM_CTRL_MODE_SRST_Msk (0x2UL) /*!< SRST (Bitfield-Mask: 0x01) */ 43 /* ========================================================== EXE ========================================================== */ 44 #define MEC_EEPROM_CTRL_EXE_TADDR_Pos (0UL) /*!< TADDR (Bit 0) */ 45 #define MEC_EEPROM_CTRL_EXE_TADDR_Msk (0xffffUL) /*!< TADDR (Bitfield-Mask: 0xffff) */ 46 #define MEC_EEPROM_CTRL_EXE_CMD_Pos (16UL) /*!< CMD (Bit 16) */ 47 #define MEC_EEPROM_CTRL_EXE_CMD_Msk (0x70000UL) /*!< CMD (Bitfield-Mask: 0x07) */ 48 #define MEC_EEPROM_CTRL_EXE_XFRSZ_Pos (24UL) /*!< XFRSZ (Bit 24) */ 49 #define MEC_EEPROM_CTRL_EXE_XFRSZ_Msk (0x1f000000UL) /*!< XFRSZ (Bitfield-Mask: 0x1f) */ 50 /* ======================================================== STATUS ========================================================= */ 51 #define MEC_EEPROM_CTRL_STATUS_XFR_DONE_Pos (0UL) /*!< XFR_DONE (Bit 0) */ 52 #define MEC_EEPROM_CTRL_STATUS_XFR_DONE_Msk (0x1UL) /*!< XFR_DONE (Bitfield-Mask: 0x01) */ 53 #define MEC_EEPROM_CTRL_STATUS_ERROR_Pos (1UL) /*!< ERROR (Bit 1) */ 54 #define MEC_EEPROM_CTRL_STATUS_ERROR_Msk (0x2UL) /*!< ERROR (Bitfield-Mask: 0x01) */ 55 #define MEC_EEPROM_CTRL_STATUS_XFR_ACTIVE_Pos (8UL) /*!< XFR_ACTIVE (Bit 8) */ 56 #define MEC_EEPROM_CTRL_STATUS_XFR_ACTIVE_Msk (0x100UL) /*!< XFR_ACTIVE (Bitfield-Mask: 0x01) */ 57 /* ======================================================== INTR_EN ======================================================== */ 58 #define MEC_EEPROM_CTRL_INTR_EN_XFR_DONE_Pos (0UL) /*!< XFR_DONE (Bit 0) */ 59 #define MEC_EEPROM_CTRL_INTR_EN_XFR_DONE_Msk (0x1UL) /*!< XFR_DONE (Bitfield-Mask: 0x01) */ 60 #define MEC_EEPROM_CTRL_INTR_EN_ERROR_Pos (1UL) /*!< ERROR (Bit 1) */ 61 #define MEC_EEPROM_CTRL_INTR_EN_ERROR_Msk (0x2UL) /*!< ERROR (Bitfield-Mask: 0x01) */ 62 /* ========================================================= PSWD ========================================================== */ 63 /* ======================================================== UNLOCK ========================================================= */ 64 /* ========================================================= LOCK ========================================================== */ 65 #define MEC_EEPROM_CTRL_LOCK_JTAG_LOCK_Pos (0UL) /*!< JTAG_LOCK (Bit 0) */ 66 #define MEC_EEPROM_CTRL_LOCK_JTAG_LOCK_Msk (0x1UL) /*!< JTAG_LOCK (Bitfield-Mask: 0x01) */ 67 #define MEC_EEPROM_CTRL_LOCK_LOCK_Pos (1UL) /*!< LOCK (Bit 1) */ 68 #define MEC_EEPROM_CTRL_LOCK_LOCK_Msk (0x2UL) /*!< LOCK (Bitfield-Mask: 0x01) */ 69 /* ========================================================= DATA ========================================================== */ 70 71 /** @} */ /* End of group PosMask_peripherals */ 72 73 /** @addtogroup EnumValue_peripherals 74 * @{ 75 */ 76 /* =========================================== MEC_EEPROM_CTRL0 EXE CMD [16..18] =========================================== */ 77 typedef enum { /*!< MEC_EEPROM_CTRL0_EXE_CMD */ 78 MEC_EEPROM_CTRL0_EXE_CMD_READ = 0, /*!< READ : Read data from EEPROM */ 79 MEC_EEPROM_CTRL0_EXE_CMD_WRITE = 1, /*!< WRITE : Write data to EEPROM */ 80 MEC_EEPROM_CTRL0_EXE_CMD_RDSTS = 2, /*!< RDSTS : Read status byte from EEPROM */ 81 MEC_EEPROM_CTRL0_EXE_CMD_WRSTS = 3, /*!< WRSTS : Write status byte in EEPROM */ 82 } MEC_EEPROM_CTRL0_EXE_CMD_Enum; 83 84 /* ========================================== MEC_EEPROM_CTRL0 EXE XFRSZ [24..28] ========================================== */ 85 typedef enum { /*!< MEC_EEPROM_CTRL0_EXE_XFRSZ */ 86 MEC_EEPROM_CTRL0_EXE_XFRSZ_MAX_BYTES32 = 0, /*!< MAX_BYTES32 : Transfer maximum size of 32 bytes */ 87 MEC_EEPROM_CTRL0_EXE_XFRSZ_BYTES1 = 1, /*!< BYTES1 : Transfer one byte */ 88 MEC_EEPROM_CTRL0_EXE_XFRSZ_BYTES2 = 2, /*!< BYTES2 : Transfer two bytes */ 89 MEC_EEPROM_CTRL0_EXE_XFRSZ_BYTES3 = 3, /*!< BYTES3 : Transfer three bytes */ 90 MEC_EEPROM_CTRL0_EXE_XFRSZ_BYTES4 = 4, /*!< BYTES4 : Transfer four bytes */ 91 MEC_EEPROM_CTRL0_EXE_XFRSZ_BYTES31 = 31, /*!< BYTES31 : Transfer 31 bytes */ 92 } MEC_EEPROM_CTRL0_EXE_XFRSZ_Enum; 93 94 /** @} */ /* End of group EnumValue_peripherals */ 95 96 #endif /* _MEC5_EEPROM_CTRL_V1_H */ 97
