1 /*
2  * Copyright (c) 2024 Microchip Technology Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC5_ACPI_EC_V1_H
7 #define _MEC5_ACPI_EC_V1_H
8 
9 /** @addtogroup Device_Peripheral_peripherals
10   * @{
11   */
12 
13 /**
14   * @brief ACPI Host to EC command interface (MEC_ACPI_EC0)
15   */
16 
17 typedef struct mec_acpi_ec_regs {               /*!< (@ 0x400F0800) MEC_ACPI_EC0 Structure                                     */
18   __IOM uint32_t  AEC_HDATA;                    /*!< (@ 0x00000000) Host Data                                                  */
19   __OM  uint8_t   AEC_HCMDSTS;                  /*!< (@ 0x00000004) Host Command(WO), Status(RO)                               */
20   __IM  uint8_t   AEC_HBYTE_CTRL;               /*!< (@ 0x00000005) Byte Access Control                                        */
21   __IM  uint16_t  RESERVED;
22   __IM  uint32_t  RESERVED1[62];
23   __IOM uint32_t  AEC_E2H_DATA;                 /*!< (@ 0x00000100) EC to Host data                                            */
24   __IOM uint8_t   AEC_STATUS;                   /*!< (@ 0x00000104) EC only accessible status                                  */
25   __IOM uint8_t   AEC_BYTE_CTRL;                /*!< (@ 0x00000105) EC only accessible byte access control                     */
26   __IM  uint16_t  RESERVED2;
27   __IOM uint32_t  AEC_H2E_DATA;                 /*!< (@ 0x00000108) Host to EC data                                            */
28 } MEC_ACPI_EC_Type;                             /*!< Size = 268 (0x10c)                                                        */
29 
30 /** @} */ /* End of group Device_Peripheral_peripherals */
31 
32 /** @addtogroup PosMask_peripherals
33   * @{
34   */
35 /* =======================================================  AEC_HDATA  ======================================================= */
36 /* ======================================================  AEC_HCMDSTS  ====================================================== */
37 /* ====================================================  AEC_HBYTE_CTRL  ===================================================== */
38 /* =====================================================  AEC_E2H_DATA  ====================================================== */
39 /* ======================================================  AEC_STATUS  ======================================================= */
40 #define MEC_ACPI_EC_AEC_STATUS_OBF_Pos    (0UL)                     /*!< OBF (Bit 0)                                           */
41 #define MEC_ACPI_EC_AEC_STATUS_OBF_Msk    (0x1UL)                   /*!< OBF (Bitfield-Mask: 0x01)                             */
42 #define MEC_ACPI_EC_AEC_STATUS_IBF_Pos    (1UL)                     /*!< IBF (Bit 1)                                           */
43 #define MEC_ACPI_EC_AEC_STATUS_IBF_Msk    (0x2UL)                   /*!< IBF (Bitfield-Mask: 0x01)                             */
44 #define MEC_ACPI_EC_AEC_STATUS_UD1A_Pos   (2UL)                     /*!< UD1A (Bit 2)                                          */
45 #define MEC_ACPI_EC_AEC_STATUS_UD1A_Msk   (0x4UL)                   /*!< UD1A (Bitfield-Mask: 0x01)                            */
46 #define MEC_ACPI_EC_AEC_STATUS_CMD_Pos    (3UL)                     /*!< CMD (Bit 3)                                           */
47 #define MEC_ACPI_EC_AEC_STATUS_CMD_Msk    (0x8UL)                   /*!< CMD (Bitfield-Mask: 0x01)                             */
48 #define MEC_ACPI_EC_AEC_STATUS_BURST_Pos  (4UL)                     /*!< BURST (Bit 4)                                         */
49 #define MEC_ACPI_EC_AEC_STATUS_BURST_Msk  (0x10UL)                  /*!< BURST (Bitfield-Mask: 0x01)                           */
50 #define MEC_ACPI_EC_AEC_STATUS_SCI_EVT_Pos (5UL)                    /*!< SCI_EVT (Bit 5)                                       */
51 #define MEC_ACPI_EC_AEC_STATUS_SCI_EVT_Msk (0x20UL)                 /*!< SCI_EVT (Bitfield-Mask: 0x01)                         */
52 #define MEC_ACPI_EC_AEC_STATUS_SMI_EVT_Pos (6UL)                    /*!< SMI_EVT (Bit 6)                                       */
53 #define MEC_ACPI_EC_AEC_STATUS_SMI_EVT_Msk (0x40UL)                 /*!< SMI_EVT (Bitfield-Mask: 0x01)                         */
54 #define MEC_ACPI_EC_AEC_STATUS_UD0A_Pos   (7UL)                     /*!< UD0A (Bit 7)                                          */
55 #define MEC_ACPI_EC_AEC_STATUS_UD0A_Msk   (0x80UL)                  /*!< UD0A (Bitfield-Mask: 0x01)                            */
56 /* =====================================================  AEC_BYTE_CTRL  ===================================================== */
57 #define MEC_ACPI_EC_AEC_BYTE_CTRL_FOUR_BYTE_MODE_Pos (0UL)          /*!< FOUR_BYTE_MODE (Bit 0)                                */
58 #define MEC_ACPI_EC_AEC_BYTE_CTRL_FOUR_BYTE_MODE_Msk (0x1UL)        /*!< FOUR_BYTE_MODE (Bitfield-Mask: 0x01)                  */
59 /** @} */ /* End of group PosMask_peripherals */
60 
61 #endif /* _MEC5_ACPI_EC_V1_H */
62