1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #define PLAT_PRIMARY_CPU (0x0) 12 13 #define MT_GIC_BASE (0x0C000000) 14 #define MCUCFG_BASE (0x0C530000) 15 #define IO_PHYS (0x10000000) 16 17 /* Aggregate of all devices for MMU mapping */ 18 #define MTK_DEV_RNG0_BASE IO_PHYS 19 #define MTK_DEV_RNG0_SIZE (0x10000000) 20 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 21 #define MTK_DEV_RNG2_SIZE (0x600000) 22 #define MTK_MCDI_SRAM_BASE (0x11B000) 23 #define MTK_MCDI_SRAM_MAP_SIZE (0x1000) 24 25 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 26 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 27 #define SPM_BASE (IO_PHYS + 0x00006000) 28 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 29 #define SSPM_MCDI_SHARE_SRAM (IO_PHYS + 0x00420000) 30 #define SSPM_CFGREG_BASE (IO_PHYS + 0x00440000) /* SSPM view: 0x30040000 */ 31 #define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) 32 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 33 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 34 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 35 #define VDOSYS0_BASE (IO_PHYS + 0x0C01A000) 36 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 37 38 /******************************************************************************* 39 * GPIO related constants 40 ******************************************************************************/ 41 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 42 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 43 #define GPIO_BASE (IO_PHYS + 0x00005000) 44 #define SPM_BASE (IO_PHYS + 0x00006000) 45 #define IOCFG_LT_BASE (IO_PHYS + 0x00002000) 46 #define IOCFG_LM_BASE (IO_PHYS + 0x00002200) 47 #define IOCFG_LB_BASE (IO_PHYS + 0x00002400) 48 #define IOCFG_BL_BASE (IO_PHYS + 0x00002600) 49 #define IOCFG_RB_BASE (IO_PHYS + 0x00002A00) 50 #define IOCFG_RT_BASE (IO_PHYS + 0x00002C00) 51 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 52 #define DVFSRC_BASE (IO_PHYS + 0x00012000) 53 #define MMSYS_BASE (IO_PHYS + 0x04000000) 54 #define MDPSYS_BASE (IO_PHYS + 0x0B000000) 55 56 /******************************************************************************* 57 * UART related constants 58 ******************************************************************************/ 59 #define UART0_BASE (IO_PHYS + 0x01002000) 60 #define UART1_BASE (IO_PHYS + 0x01003000) 61 62 #define UART_BAUDRATE (115200) 63 64 /******************************************************************************* 65 * PWRAP related constants 66 ******************************************************************************/ 67 #define PMIC_WRAP_BASE (IO_PHYS + 0x0000D000) 68 69 /******************************************************************************* 70 * EMI MPU related constants 71 ******************************************************************************/ 72 #define EMI_MPU_BASE (IO_PHYS + 0x0021B000) 73 74 /******************************************************************************* 75 * MSDC related constants 76 ******************************************************************************/ 77 #define MSDC0_BASE (IO_PHYS + 0x01230000) 78 79 /******************************************************************************* 80 * GIC-600 & interrupt handling related constants 81 ******************************************************************************/ 82 /* Base MTK_platform compatible GIC memory map */ 83 #define BASE_GICD_BASE MT_GIC_BASE 84 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 85 86 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 87 #define CIRQ_REG_NUM (11) 88 #define CIRQ_IRQ_NUM (326) 89 #define CIRQ_SPI_START (64) 90 #define MD_WDT_IRQ_BIT_ID (107) 91 /******************************************************************************* 92 * System counter frequency related constants 93 ******************************************************************************/ 94 #define SYS_COUNTER_FREQ_IN_TICKS (13000000) 95 #define SYS_COUNTER_FREQ_IN_MHZ (13) 96 97 /******************************************************************************* 98 * Platform binary types for linking 99 ******************************************************************************/ 100 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 101 #define PLATFORM_LINKER_ARCH aarch64 102 103 /******************************************************************************* 104 * Generic platform constants 105 ******************************************************************************/ 106 #define PLATFORM_STACK_SIZE 0x800 107 108 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 109 110 #define PLAT_MAX_PWR_LVL U(3) 111 #define PLAT_MAX_RET_STATE U(1) 112 #define PLAT_MAX_OFF_STATE U(9) 113 114 #define PLATFORM_SYSTEM_COUNT U(1) 115 #define PLATFORM_MCUSYS_COUNT U(1) 116 #define PLATFORM_CLUSTER_COUNT U(1) 117 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 118 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 119 120 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 121 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 122 123 #define SOC_CHIP_ID U(0x8186) 124 125 /******************************************************************************* 126 * Platform memory map related constants 127 ******************************************************************************/ 128 #define TZRAM_BASE (0x54600000) 129 #define TZRAM_SIZE (0x00030000) 130 131 /******************************************************************************* 132 * BL31 specific defines. 133 ******************************************************************************/ 134 /* 135 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 136 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 137 * little space for growth. 138 */ 139 #define BL31_BASE (TZRAM_BASE + 0x1000) 140 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 141 142 /******************************************************************************* 143 * Platform specific page table and MMU setup constants 144 ******************************************************************************/ 145 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 146 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 147 #define MAX_XLAT_TABLES (16) 148 #define MAX_MMAP_REGIONS (16) 149 150 /******************************************************************************* 151 * Declarations and constants to access the mailboxes safely. Each mailbox is 152 * aligned on the biggest cache line size in the platform. This is known only 153 * to the platform as it might have a combination of integrated and external 154 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 155 * line at any cache level. They could belong to different cpus/clusters & 156 * get written while being protected by different locks causing corruption of 157 * a valid mailbox address. 158 ******************************************************************************/ 159 #define CACHE_WRITEBACK_SHIFT (6) 160 #define CACHE_WRITEBACK_GRANULE BIT(CACHE_WRITEBACK_SHIFT) 161 #endif /* PLATFORM_DEF_H */ 162
