1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef POWER_IP_SPECIFIC_H 8 #define POWER_IP_SPECIFIC_H 9 10 /** 11 * @file Power_Ip_Specific.h 12 * @version 3.0.0 13 * 14 * @brief POWER IP driver header file. 15 * @details POWER IP driver header file. 16 * 17 * @addtogroup POWER_DRIVER Power Ip Driver 18 * @{ 19 */ 20 21 #ifdef __cplusplus 22 extern "C"{ 23 #endif 24 25 /*================================================================================================== 26 INCLUDE FILES 27 1) system and project includes 28 2) needed interfaces from external units 29 3) internal and external interfaces from this unit 30 ==================================================================================================*/ 31 #include "Power_Ip_Cfg_Defines.h" 32 33 /*================================================================================================== 34 SOURCE FILE VERSION INFORMATION 35 ==================================================================================================*/ 36 #define POWER_IP_SPECIFIC_VENDOR_ID 43 37 #define POWER_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION 4 38 #define POWER_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION 7 39 #define POWER_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION 0 40 #define POWER_IP_SPECIFIC_SW_MAJOR_VERSION 3 41 #define POWER_IP_SPECIFIC_SW_MINOR_VERSION 0 42 #define POWER_IP_SPECIFIC_SW_PATCH_VERSION 0 43 44 /*================================================================================================== 45 FILE VERSION CHECKS 46 ==================================================================================================*/ 47 /* Check if Power_Ip_Specific.h file and Power_Ip_Cfg_Defines.h file have same versions */ 48 #if (POWER_IP_SPECIFIC_VENDOR_ID != POWER_IP_CFG_DEFINES_VENDOR_ID) 49 #error "Power_Ip_Specific.h and Power_Ip_Cfg_Defines.h have different vendor IDs" 50 #endif 51 52 /* Check if Power_Ip_Specific.h file and Power_Ip_Cfg_Defines.h file are of the same Autosar version */ 53 #if ((POWER_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != POWER_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ 54 (POWER_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != POWER_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ 55 (POWER_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION != POWER_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) 56 #error "AutoSar Version Numbers of Power_Ip_Specific.h and Power_Ip_Cfg_Defines.h are different" 57 #endif 58 59 /* Check if Power_Ip_Specific.h file and Power_Ip_Cfg_Defines.h file are of the same Software version */ 60 #if ((POWER_IP_SPECIFIC_SW_MAJOR_VERSION != POWER_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ 61 (POWER_IP_SPECIFIC_SW_MINOR_VERSION != POWER_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ 62 (POWER_IP_SPECIFIC_SW_PATCH_VERSION != POWER_IP_CFG_DEFINES_SW_PATCH_VERSION)) 63 #error "Software Version Numbers of Power_Ip_Specific.h and Power_Ip_Cfg_Defines.h are different" 64 #endif 65 66 67 /*================================================================================================== 68 * CONSTANTS 69 ==================================================================================================*/ 70 71 /*================================================================================================== 72 * DEFINES AND MACROS 73 ==================================================================================================*/ 74 #if (defined(POWER_IP_DERIVATIVE_001) || defined(POWER_IP_DERIVATIVE_002) || defined(POWER_IP_DERIVATIVE_004) || defined(POWER_IP_DERIVATIVE_005)) 75 #define MC_RGM_FES_SWT1_RST_MASK32 ((uint32)0x00000080U) 76 #define MC_RGM_FES_SWT1_RST_MASK ((uint32)0x00000000U) 77 #define MC_RGM_FERD_D_SWT1_RST_MASK ((uint32)0x00000000U) 78 #endif 79 80 #if (!(defined(POWER_IP_DERIVATIVE_006) || defined(POWER_IP_DERIVATIVE_008) || defined(POWER_IP_DERIVATIVE_009))) 81 #define MC_RGM_FES_SWT2_RST_MASK32 ((uint32)0x00000100U) 82 #define MC_RGM_FES_SWT2_RST_MASK ((uint32)0x00000000U) 83 #define MC_RGM_FERD_D_SWT2_RST_MASK ((uint32)0x00000000U) 84 #endif 85 86 #if (!(defined(POWER_IP_DERIVATIVE_008))) 87 #define MC_RGM_FES_SWT3_RST_MASK32 ((uint32)0x00000400U) 88 #define MC_RGM_FES_SWT3_RST_MASK ((uint32)0x00000000U) 89 #define MC_RGM_FERD_D_SWT3_RST_MASK ((uint32)0x00000000U) 90 #endif 91 92 #if (!(defined(POWER_IP_DERIVATIVE_008) || defined(POWER_IP_DERIVATIVE_009))) 93 #define MC_RGM_FES_PLL_AUX_MASK32 ((uint32)0x00001000U) 94 #define MC_RGM_FES_PLL_AUX_MASK ((uint32)0x00000000U) 95 #endif 96 97 #if (!(defined(POWER_IP_DERIVATIVE_006) || defined(POWER_IP_DERIVATIVE_008))) 98 #define MC_RGM_DES_CM7_CORE_CLK_FAIL_MASK32 ((uint32)0x00010000U) 99 #define MC_RGM_DES_CM7_CORE_CLK_FAIL_MASK ((uint32)0x00000000U) 100 #endif 101 102 #define MC_RGM_FES_RWBITS_MASK32 ((uint32)(MC_RGM_FES_DEBUG_FUNC_MASK | \ 103 MC_RGM_FES_SW_FUNC_MASK | \ 104 MC_RGM_FES_HSE_BOOT_RST_MASK | \ 105 MC_RGM_FES_HSE_SWT_RST_MASK | \ 106 MC_RGM_FES_JTAG_RST_MASK | \ 107 MC_RGM_FES_PLL_AUX_MASK | \ 108 MC_RGM_FES_SWT3_RST_MASK | \ 109 MC_RGM_FES_SWT2_RST_MASK | \ 110 MC_RGM_FES_SWT1_RST_MASK | \ 111 MC_RGM_FES_SWT0_RST_MASK | \ 112 MC_RGM_FES_ST_DONE_MASK | \ 113 MC_RGM_FES_FCCU_RST_MASK | \ 114 MC_RGM_FES_F_EXR_MASK)) 115 116 #define MC_RGM_DES_RWBITS_MASK32 ((uint32)(MC_RGM_DES_DEBUG_DEST_MASK | \ 117 MC_RGM_DES_SW_DEST_MASK | \ 118 MC_RGM_DES_HSE_SNVS_RST_MASK | \ 119 MC_RGM_DES_HSE_TMPR_RST_MASK | \ 120 MC_RGM_DES_CM7_CORE_CLK_FAIL_MASK | \ 121 MC_RGM_DES_SYS_DIV_FAIL_MASK | \ 122 MC_RGM_DES_HSE_CLK_FAIL_MASK | \ 123 MC_RGM_DES_AIPS_PLAT_CLK_FAIL_MASK | \ 124 MC_RGM_DES_CORE_CLK_FAIL_MASK | \ 125 MC_RGM_DES_PLL_LOL_MASK | \ 126 MC_RGM_DES_FXOSC_FAIL_MASK | \ 127 MC_RGM_DES_MC_RGM_FRE_MASK | \ 128 MC_RGM_DES_STCU_URF_MASK | \ 129 MC_RGM_DES_FCCU_FTR_MASK | \ 130 MC_RGM_DES_F_POR_MASK)) 131 132 #define MC_RGM_FES_IRQ_BITS_MASK ((uint32)(MC_RGM_FES_DEBUG_FUNC_MASK | \ 133 MC_RGM_FES_JTAG_RST_MASK | \ 134 MC_RGM_FES_PLL_AUX_MASK | \ 135 MC_RGM_FES_SWT3_RST_MASK | \ 136 MC_RGM_FES_SWT2_RST_MASK | \ 137 MC_RGM_FES_SWT1_RST_MASK | \ 138 MC_RGM_FES_SWT0_RST_MASK | \ 139 MC_RGM_FES_FCCU_RST_MASK)) 140 141 #define MC_RGM_DES_IRQ_BITS_MASK ((uint32) 0x00000000U) 142 143 #define MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 ((uint32)0U) 144 #define MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 ((uint32)15U) 145 146 #define MC_RGM_FERD_RWBITS_MASK ((uint32)(MC_RGM_FERD_D_FCCU_RST_MASK | \ 147 MC_RGM_FERD_D_SWT0_RST_MASK | \ 148 MC_RGM_FERD_D_SWT1_RST_MASK | \ 149 MC_RGM_FERD_D_SWT2_RST_MASK | \ 150 MC_RGM_FERD_D_SWT3_RST_MASK | \ 151 MC_RGM_FERD_D_JTAG_RST_MASK | \ 152 MC_RGM_FERD_D_DEBUG_FUNC_MASK)) 153 154 /***********************************************************/ 155 /* MC_RGM_RDSS */ 156 /***********************************************************/ 157 #define MC_RGM_FES_RES_OCCURED_DURING_STANDBY_U32 ((uint32)MC_RGM_RDSS_FES_RES_MASK) 158 #define MC_RGM_FES_RES_NOT_OCCURED_DURING_STANDBY_U32 ((uint32)0x00000000U) 159 160 #define MC_RGM_DES_RES_OCCURED_DURING_STANDBY_U32 ((uint32)MC_RGM_RDSS_DES_RES_MASK) 161 #define MC_RGM_DES_RES_NOT_OCCURED_DURING_STANDBY_U32 ((uint32)0x00000000U) 162 163 #define MC_RGM_RDSS_RWBITS_MASK_U32 ((uint32)MC_RGM_RDSS_DES_RES_MASK | (uint32)MC_RGM_RDSS_FES_RES_MASK) 164 165 #define MC_RGM_RDSS_FES_RES_MASK_U32 ((uint32)MC_RGM_RDSS_FES_RES_MASK) 166 #define MC_RGM_RDSS_DES_RES_MASK_U32 ((uint32)MC_RGM_RDSS_DES_RES_MASK) 167 168 /***********************************************************/ 169 /* Power_Ip_MC_RGM_GetResetRawValue Defines */ 170 /***********************************************************/ 171 #define MC_RGM_RAWRESET_FES_F_F_EXR_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x0U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 172 #define MC_RGM_RAWRESET_FES_F_FCCU_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x1U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 173 #define MC_RGM_RAWRESET_FES_F_ST_DONE_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x2U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 174 #define MC_RGM_RAWRESET_FES_F_SWT0_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x3U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 175 #define MC_RGM_RAWRESET_FES_F_SWT1_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x4U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 176 #define MC_RGM_RAWRESET_FES_F_SWT2_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x5U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 177 #define MC_RGM_RAWRESET_FES_F_JTAG_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x6U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 178 #define MC_RGM_RAWRESET_FES_F_SWT3_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x7U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 179 #define MC_RGM_RAWRESET_FES_F_PLL_AUX_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x8U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 180 #define MC_RGM_RAWRESET_FES_F_HSE_SWT_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x9U ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 181 #define MC_RGM_RAWRESET_FES_F_HSE_BOOT_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xAU ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 182 #define MC_RGM_RAWRESET_FES_F_SW_FUNC_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xBU ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 183 #define MC_RGM_RAWRESET_FES_F_DEBUG_FUNC_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xCU ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 184 #define MC_RGM_RAWRESET_WAKEUP_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xDU ) << MC_RGM_RAWRESET_FES_BASE_SHIFT_U32 )) 185 186 #define MC_RGM_RAWRESET_DES_F_POR_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x0U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 187 #define MC_RGM_RAWRESET_DES_F_FCCU_FTR_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x1U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 188 #define MC_RGM_RAWRESET_DES_F_STCU_URF_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x2U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 189 #define MC_RGM_RAWRESET_DES_F_MC_RGM_FRE_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x3U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 190 #define MC_RGM_RAWRESET_DES_F_FXOSC_FAIL_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x4U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 191 #define MC_RGM_RAWRESET_DES_F_PLL_LOL_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x5U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 192 #define MC_RGM_RAWRESET_DES_F_CORE_CLK_FAIL_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x6U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 193 #define MC_RGM_RAWRESET_DES_F_AIPS_PLAT_CLK_FAIL_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x7U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 194 #define MC_RGM_RAWRESET_DES_F_HSE_CLK_FAIL_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x8U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 195 #define MC_RGM_RAWRESET_DES_F_SYS_DIV_FAIL_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0x9U ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 196 #define MC_RGM_RAWRESET_DES_F_CM7_CORE_CLK_FAIL_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xAU ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 197 #define MC_RGM_RAWRESET_DES_F_HSE_TMPR_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xBU ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 198 #define MC_RGM_RAWRESET_DES_F_HSE_SNVS_RST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xCU ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 199 #define MC_RGM_RAWRESET_DES_F_SW_DEST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xDU ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 200 #define MC_RGM_RAWRESET_DES_F_DEBUG_DEST_MASK32 ((uint32)( ( (uint32)0x01U << (uint32)0xEU ) << MC_RGM_RAWRESET_DES_BASE_SHIFT_U32 )) 201 202 /***********************************************************/ 203 /* MC_ME_MAIN_COREID */ 204 /***********************************************************/ 205 206 #define MC_ME_MAIN_COREID_U32(value) ((uint32)( (uint32)(MC_ME_MAIN_COREID_CIDX(value)) | (uint32)(MC_ME_MAIN_COREID_PIDX(value)) )) 207 208 #define MC_ME_MAIN_COREID_NOT_USED_U32 ((uint32)0x1FU) 209 210 #define MC_ME_MAIN_COREID_PIDX_CM7_0_U32 (MC_ME_MAIN_COREID_PIDX((uint32)0U)) 211 #define MC_ME_MAIN_COREID_PIDX_CM7_1_U32 (MC_ME_MAIN_COREID_PIDX((uint32)0U)) 212 #define MC_ME_MAIN_COREID_PIDX_CM7_2_U32 (MC_ME_MAIN_COREID_PIDX((uint32)0U)) 213 214 #define MC_ME_MAIN_COREID_CIDX_CM7_0_U32 (MC_ME_MAIN_COREID_CIDX((uint32)0U)) 215 #define MC_ME_MAIN_COREID_CIDX_CM7_1_U32 (MC_ME_MAIN_COREID_CIDX((uint32)1U)) 216 #define MC_ME_MAIN_COREID_CIDX_CM7_2_U32 (MC_ME_MAIN_COREID_CIDX((uint32)2U)) 217 218 #define MC_ME_PRTN0_PUPD_RWBITS_MASK ((uint32)MC_ME_PRTN0_PUPD_PCUD_MASK) 219 #define MC_ME_PRTN1_PUPD_RWBITS_MASK ((uint32)MC_ME_PRTN0_PUPD_PCUD_MASK) 220 #define MC_ME_PRTN2_PUPD_RWBITS_MASK ((uint32)MC_ME_PRTN0_PUPD_PCUD_MASK) 221 #define MC_ME_PRTN3_PUPD_RWBITS_MASK ((uint32)MC_ME_PRTN0_PUPD_PCUD_MASK) 222 223 #if defined(POWER_IP_DERIVATIVE_001) || defined(POWER_IP_DERIVATIVE_002) || defined(POWER_IP_DERIVATIVE_006) 224 #define PMC_LVSC_RAMP_UP_RESET_FLAGS_RWBITS_MASK (((uint32)PMC_LVSC_PORF_MASK | \ 225 (uint32)PMC_LVSC_LVR11LPF_MASK | \ 226 (uint32)PMC_LVSC_LVR11F_MASK | \ 227 (uint32)PMC_LVSC_LVR25LPF_MASK | \ 228 (uint32)PMC_LVSC_LVR25F_MASK | \ 229 (uint32)PMC_LVSC_LVRALPF_MASK | \ 230 (uint32)PMC_LVSC_LVRAF_MASK)) 231 232 #define PMC_LVSC_RWBITS_MASK (((uint32)PMC_LVSC_PORF_MASK | \ 233 (uint32)PMC_LVSC_GNG11OSCF_MASK | \ 234 (uint32)PMC_LVSC_GNG25OSCF_MASK | \ 235 (uint32)PMC_LVSC_LVR11LPF_MASK | \ 236 (uint32)PMC_LVSC_LVR11F_MASK | \ 237 (uint32)PMC_LVSC_LVR25LPF_MASK | \ 238 (uint32)PMC_LVSC_LVR25F_MASK | \ 239 (uint32)PMC_LVSC_LVRALPF_MASK | \ 240 (uint32)PMC_LVSC_LVRAF_MASK | \ 241 (uint32)PMC_LVSC_LVD5AF_MASK | \ 242 (uint32)PMC_LVSC_HVD11F_MASK | \ 243 (uint32)PMC_LVSC_HVD25F_MASK | \ 244 (uint32)PMC_LVSC_HVDAF_MASK)) 245 #elif defined(POWER_IP_DERIVATIVE_009) || defined(POWER_IP_DERIVATIVE_008) 246 #define PMC_LVSC_RAMP_UP_RESET_FLAGS_RWBITS_MASK (((uint32)PMC_LVSC_PORF_MASK | \ 247 (uint32)PMC_LVSC_LVR11LPF_MASK | \ 248 (uint32)PMC_LVSC_LVR11F_MASK | \ 249 (uint32)PMC_LVSC_LVR25LPF_MASK | \ 250 (uint32)PMC_LVSC_LVR25F_MASK | \ 251 (uint32)PMC_LVSC_LVRBLPF_MASK | \ 252 (uint32)PMC_LVSC_LVRBF_MASK | \ 253 (uint32)PMC_LVSC_LVRALPF_MASK | \ 254 (uint32)PMC_LVSC_LVRAF_MASK)) 255 256 #define PMC_LVSC_RWBITS_MASK (((uint32)PMC_LVSC_PORF_MASK | \ 257 (uint32)PMC_LVSC_GNG11OSCF_MASK | \ 258 (uint32)PMC_LVSC_GNG25OSCF_MASK | \ 259 (uint32)PMC_LVSC_GNG11OSCF_MASK | \ 260 (uint32)PMC_LVSC_GNG25OSCF_MASK | \ 261 (uint32)PMC_LVSC_LVR11LPF_MASK | \ 262 (uint32)PMC_LVSC_LVR11F_MASK | \ 263 (uint32)PMC_LVSC_LVR25LPF_MASK | \ 264 (uint32)PMC_LVSC_LVR25F_MASK | \ 265 (uint32)PMC_LVSC_LVRBLPF_MASK | \ 266 (uint32)PMC_LVSC_LVRBF_MASK | \ 267 (uint32)PMC_LVSC_LVRALPF_MASK | \ 268 (uint32)PMC_LVSC_LVRAF_MASK | \ 269 (uint32)PMC_LVSC_HVD15S_MASK | \ 270 (uint32)PMC_LVSC_LVD5AS_MASK | \ 271 (uint32)PMC_LVSC_HVD11S_MASK | \ 272 (uint32)PMC_LVSC_HVD25S_MASK | \ 273 (uint32)PMC_LVSC_HVDBS_MASK | \ 274 (uint32)PMC_LVSC_HVDAS_MASK | \ 275 (uint32)PMC_LVSC_HVD15F_MASK | \ 276 (uint32)PMC_LVSC_LVD5AF_MASK | \ 277 (uint32)PMC_LVSC_HVD11F_MASK | \ 278 (uint32)PMC_LVSC_HVD25F_MASK | \ 279 (uint32)PMC_LVSC_HVDBF_MASK | \ 280 (uint32)PMC_LVSC_HVDAF_MASK)) 281 #else 282 #define PMC_LVSC_RAMP_UP_RESET_FLAGS_RWBITS_MASK (((uint32)PMC_LVSC_PORF_MASK | \ 283 (uint32)PMC_LVSC_LVR11LPF_MASK | \ 284 (uint32)PMC_LVSC_LVR11F_MASK | \ 285 (uint32)PMC_LVSC_LVR25LPF_MASK | \ 286 (uint32)PMC_LVSC_LVR25F_MASK | \ 287 (uint32)PMC_LVSC_LVRBLPF_MASK | \ 288 (uint32)PMC_LVSC_LVRBF_MASK | \ 289 (uint32)PMC_LVSC_LVRALPF_MASK | \ 290 (uint32)PMC_LVSC_LVRAF_MASK)) 291 292 #define PMC_LVSC_RWBITS_MASK (((uint32)PMC_LVSC_PORF_MASK | \ 293 (uint32)PMC_LVSC_GNG11OSCF_MASK | \ 294 (uint32)PMC_LVSC_GNG25OSCF_MASK | \ 295 (uint32)PMC_LVSC_LVR11LPF_MASK | \ 296 (uint32)PMC_LVSC_LVR11F_MASK | \ 297 (uint32)PMC_LVSC_LVR25LPF_MASK | \ 298 (uint32)PMC_LVSC_LVR25F_MASK | \ 299 (uint32)PMC_LVSC_LVRBLPF_MASK | \ 300 (uint32)PMC_LVSC_LVRBF_MASK | \ 301 (uint32)PMC_LVSC_LVRALPF_MASK | \ 302 (uint32)PMC_LVSC_LVRAF_MASK | \ 303 (uint32)PMC_LVSC_LVD15F_MASK | \ 304 (uint32)PMC_LVSC_LVD5AF_MASK | \ 305 (uint32)PMC_LVSC_HVD11F_MASK | \ 306 (uint32)PMC_LVSC_HVD25F_MASK | \ 307 (uint32)PMC_LVSC_HVDBF_MASK | \ 308 (uint32)PMC_LVSC_HVDAF_MASK)) 309 #endif 310 311 #define MC_ME_MODE_CONF_MASK ( (uint32)(MC_ME_MODE_CONF_DEST_RST_MASK) | (uint32)(MC_ME_MODE_CONF_FUNC_RST_MASK) | (uint32)(MC_ME_MODE_CONF_STANDBY_MASK) ) 312 313 #define MC_ME_MODE_CONF(value) ((uint32)(((uint32)(value)) & ((uint32)(MC_ME_MODE_CONF_MASK)))) 314 315 #define POWER_IP_MC_ME_PRTN_COUNT (3U) 316 #define POWER_IP_MC_ME_CORE_COUNT (3U) 317 #define POWER_IP_MC_ME_COFB_COUNT (4U) 318 319 /** 320 * @brief This macro is used to define the position of the first reset reason. 321 * 322 */ 323 #define POWER_IP_FIRST_RESET_REASON_POS ((uint32)MCU_POWER_ON_RESET) 324 325 #define POWER_IP_SOC_PREPARE_STANDBY_MODE_SUPPORT (STD_ON) 326 327 /*================================================================================================== 328 * ENUMS 329 ==================================================================================================*/ 330 /** 331 * @brief The type Power_Ip_ResetType, represents the different reset that a specified POWER_IP can have. 332 * @details The POWER_IP shall provide at least the values MCU_POWER_ON_RESET and MCU_RESET_UNDEFINED for the enumeration Power_Ip_ResetType. 333 * 334 * @implements Power_Ip_ResetType_Enumeration 335 */ 336 typedef enum 337 { 338 /* 'Destructive' Event Status Register (MC_RGM_DES) */ 339 MCU_POWER_ON_RESET = McuConf_McuResetReasonConf_MCU_POWER_ON_RESET, /**< @brief Power on reset event. RGM_DES[F_DR0]. */ 340 MCU_FCCU_FTR_RESET = McuConf_McuResetReasonConf_MCU_FCCU_FTR_RESET, /**< @brief Non-critical supply presence detector fail. RGM_DES[F_DR1]. */ 341 MCU_STCU_URF_RESET = McuConf_McuResetReasonConf_MCU_STCU_URF_RESET, /**< @brief FCCU failure to react. RGM_DES[F_DR3]. */ 342 MCU_MC_RGM_FRE_RESET = McuConf_McuResetReasonConf_MCU_MC_RGM_FRE_RESET, /**< @brief STCU unrecoverable fault. RGM_DES[F_DR4]. */ 343 MCU_FXOSC_FAIL_RESET = McuConf_McuResetReasonConf_MCU_FXOSC_FAIL_RESET, /**< @brief Functional reset escalation. RGM_DES[F_DR6]. */ 344 MCU_PLL_LOL_RESET = McuConf_McuResetReasonConf_MCU_PLL_LOL_RESET, /**< @brief FXOSC failure. RGM_DES[F_DR8]. */ 345 MCU_CORE_CLK_FAIL_RESET = McuConf_McuResetReasonConf_MCU_CORE_CLK_FAIL_RESET, /**< @brief CORE_PLL and related DFS loss of lock. RGM_DES[F_DR9]. */ 346 MCU_AIPS_PLAT_CLK_FAIL_RESET = McuConf_McuResetReasonConf_MCU_AIPS_PLAT_CLK_FAIL_RESET, /**< @brief PERIPH_PLL and related DFS loss of lock. RGM_DES[F_DR10]. */ 347 MCU_HSE_CLK_FAIL_RESET = McuConf_McuResetReasonConf_MCU_HSE_CLK_FAIL_RESET, /**< @brief DDR_PLL loss of lock. RGM_DES[F_DR11]. */ 348 MCU_SYS_DIV_FAIL_RESET = McuConf_McuResetReasonConf_MCU_SYS_DIV_FAIL_RESET, /**< @brief ACCEL_PLL loss of lock. RGM_DES[F_DR12]. */ 349 MCU_CM7_CORE_CLK_FAIL_RESET = McuConf_McuResetReasonConf_MCU_CM7_CORE_CLK_FAIL_RESET, /**< @brief CM7_CORE_CLK failure. */ 350 MCU_HSE_TMPR_RST_RESET = McuConf_McuResetReasonConf_MCU_HSE_TMPR_RST_RESET, /**< @brief XBAR_DIV3_CLK failure. RGM_DES[F_DR13]. */ 351 MCU_HSE_SNVS_RST_RESET = McuConf_McuResetReasonConf_MCU_HSE_SNVS_RST_RESET, /**< @brief Life-cycle error. RGM_DES[F_DR16]. */ 352 MCU_SW_DEST_RESET = McuConf_McuResetReasonConf_MCU_SW_DEST_RESET, /**< @brief HSE SNVS tamper detected. RGM_DES[F_DR17]. */ 353 MCU_DEBUG_DEST_RESET = McuConf_McuResetReasonConf_MCU_DEBUG_DEST_RESET, /**< @brief HSE SWT timeout. RGM_DES[F_DR18]. */ 354 355 /* 'Functional' Event Status Register (MC_RGM_FES) */ 356 MCU_F_EXR_RESET = McuConf_McuResetReasonConf_MCU_F_EXR_RESET, /**< @brief Software destructive reset. RGM_DES[F_DR30]. */ 357 MCU_FCCU_RST_RESET = McuConf_McuResetReasonConf_MCU_FCCU_RST_RESET, /**< @brief FCCU Reset Reaction. RGM_FES[F_FR3]. */ 358 MCU_ST_DONE_RESET = McuConf_McuResetReasonConf_MCU_ST_DONE_RESET, /**< @brief Self-Test Done. RGM_FES[F_FR4]. */ 359 MCU_SWT0_RST_RESET = McuConf_McuResetReasonConf_MCU_SWT0_RST_RESET, /**< @brief SWT0 Timeout. RGM_FES[F_FR6]. */ 360 MCU_SWT1_RST_RESET = McuConf_McuResetReasonConf_MCU_SWT1_RST_RESET, /**< @brief SWT1 Timeout. RGM_FES[F_FR6]. */ 361 MCU_SWT2_RST_RESET = McuConf_McuResetReasonConf_MCU_SWT2_RST_RESET, /**< @brief SWT2 Timeout. */ 362 MCU_JTAG_RST_RESET = McuConf_McuResetReasonConf_MCU_JTAG_RST_RESET, /**< @brief HSE Memory ECC Error. RGM_FES[F_FR18]. */ 363 MCU_SWT3_RST_RESET = McuConf_McuResetReasonConf_MCU_SWT3_RST_RESET, /**< @brief SWT3 Timeout. */ 364 MCU_PLL_AUX_RESET = McuConf_McuResetReasonConf_MCU_PLL_AUX_RESET, /**< @brief PLL_AUX_CLK failure. */ 365 MCU_HSE_SWT_RST_RESET = McuConf_McuResetReasonConf_MCU_HSE_SWT_RST_RESET, /**< @brief HSE Boot Failure Error. RGM_FES[F_FR20]. */ 366 MCU_HSE_BOOT_RST_RESET = McuConf_McuResetReasonConf_MCU_HSE_BOOT_RST_RESET, /**< @brief HSE M7 Core Lock. RGM_FES[F_FR21]. */ 367 MCU_SW_FUNC_RESET = McuConf_McuResetReasonConf_MCU_SW_FUNC_RESET, /**< @brief Software functional reset. RGM_FES[F_FR30]. */ 368 MCU_DEBUG_FUNC_RESET = McuConf_McuResetReasonConf_MCU_DEBUG_FUNC_RESET, /**< @brief Debug functional reset. RGM_FES[F_FR31]. */ 369 370 MCU_WAKEUP_REASON = McuConf_McuResetReasonConf_MCU_WAKEUP_REASON, /**< @brief Wake-up event detected. */ 371 MCU_NO_RESET_REASON = McuConf_McuResetReasonConf_MCU_NO_RESET_REASON, /**< @brief No reset reason found */ 372 MCU_MULTIPLE_RESET_REASON = McuConf_McuResetReasonConf_MCU_MULTIPLE_RESET_REASON, /**< @brief More than one reset events are logged except "Power on event" */ 373 MCU_RESET_UNDEFINED = McuConf_McuResetReasonConf_MCU_RESET_UNDEFINED /**< @brief Undefined reset source. */ 374 375 } Power_Ip_ResetType; 376 377 /*================================================================================================== 378 * STRUCTURES AND OTHER TYPEDEFS 379 ==================================================================================================*/ 380 typedef struct 381 { 382 volatile uint32 PRTN_CORE_PCONF; /**< Partition 0 Core 0 Process Configuration Register, offset: 0x140 */ 383 volatile uint32 PRTN_CORE_PUPD; /**< Partition 0 Core 0 Process Update Register, offset: 0x144 */ 384 volatile const uint32 PRTN_CORE_STAT; /**< Partition 0 Core 0 Status Register, offset: 0x148 */ 385 volatile uint32 PRTN_CORE_ADDR; /**< Partition 0 Core 0 Address Register, offset: 0x14C */ 386 uint8 RESERVED[16U]; 387 } Power_Ip_MC_ME_Prtn_Core_Type; 388 389 typedef struct { 390 volatile uint32 PRTN_PCONF; /**< Partition 0 Process Configuration Register, offset: 0x100 */ 391 volatile uint32 PRTN_PUPD; /**< Partition 0 Process Update Register, offset: 0x104 */ 392 volatile const uint32 PRTN_STAT; /**< Partition 0 Status Register, offset: 0x108 */ 393 #if (defined(POWER_IP_LOCKSTEP_CTRL_SUPPORT) && (POWER_IP_LOCKSTEP_CTRL_SUPPORT == STD_ON)) 394 volatile uint32 CORE_LOCKSTEP; /**< Partition 0 Core LockStep Control Register, reserved for other partitions, offset: 0x10C */ 395 #else 396 uint8 RESERVED[4U]; 397 #endif 398 volatile const uint32 PRTN_COFB_STAT[POWER_IP_MC_ME_COFB_COUNT]; /**< Partition 0 COFB Set 0 Clock Status Register, offset: 0x110 */ 399 uint8 RESERVED_1[16U]; 400 volatile uint32 PRTN_COFB_CLKEN[POWER_IP_MC_ME_COFB_COUNT]; /**< Partition 0 COFB Set 0 Clock Enable Register, offset: 0x130 */ 401 Power_Ip_MC_ME_Prtn_Core_Type McMePrtnCoreArray[POWER_IP_MC_ME_CORE_COUNT]; 402 uint8 RESERVED_2[352U]; 403 } Power_Ip_MC_ME_Prtn_Type; 404 405 typedef struct{ 406 volatile uint32 CTL_KEY; /**< Control Key Register, offset: 0x0 */ 407 volatile uint32 MODE_CONF; /**< Mode Configuration Register, offset: 0x4 */ 408 volatile uint32 MODE_UPD; /**< Mode Update Register, offset: 0x8 */ 409 volatile const uint32 MODE_STAT; /**< Mode Status Register, offset: 0xC */ 410 volatile uint32 MAIN_COREID; /**< Main Core ID Register, offset: 0x10 */ 411 uint8 RESERVED[236U]; 412 Power_Ip_MC_ME_Prtn_Type McMePrtnArray[POWER_IP_MC_ME_PRTN_COUNT]; 413 } Power_Ip_MC_ME_Type; 414 415 /** MC_RGM - Register Layout Typedef */ 416 typedef MC_RGM_Type Power_Ip_MC_RGM_Type; 417 418 419 /*================================================================================================== 420 * GLOBAL VARIABLE DECLARATIONS 421 ==================================================================================================*/ 422 423 /*================================================================================================== 424 * FUNCTION PROTOTYPES 425 ==================================================================================================*/ 426 427 428 #ifdef __cplusplus 429 } 430 #endif 431 432 /** @} */ 433 #endif /* POWER_IP_SPECIFIC_H */ 434 435
