1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MC_RGM.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_MC_RGM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MC_RGM_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MC_RGM_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MC_RGM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MC_RGM_Peripheral_Access_Layer MC_RGM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MC_RGM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t DES; /**< Destructive Event Status Register, offset: 0x0 */ 74 uint8_t RESERVED_0[4]; 75 __IO uint32_t FES; /**< Functional /External Reset Status Register, offset: 0x8 */ 76 __IO uint32_t FERD; /**< Functional Event Reset Disable Register, offset: 0xC */ 77 __IO uint32_t FBRE; /**< Functional Bidirectional Reset Enable Register, offset: 0x10 */ 78 __IO uint32_t FREC; /**< Functional Reset Escalation Counter Register, offset: 0x14 */ 79 __IO uint32_t FRET; /**< Functional Reset Escalation Threshold Register, offset: 0x18 */ 80 __IO uint32_t DRET; /**< Destructive Reset Escalation Threshold Register, offset: 0x1C */ 81 __IO uint32_t ERCTRL; /**< External Reset Control Register, offset: 0x20 */ 82 __IO uint32_t RDSS; /**< Reset During Standby Status Register, offset: 0x24 */ 83 __IO uint32_t FRENTC; /**< Functional Reset Entry Timeout Control Register, offset: 0x28 */ 84 __I uint32_t LPDEBUG; /**< Low Power Debug Control Register, offset: 0x2C */ 85 } MC_RGM_Type, *MC_RGM_MemMapPtr; 86 87 /** Number of instances of the MC_RGM module. */ 88 #define MC_RGM_INSTANCE_COUNT (1u) 89 90 /* MC_RGM - Peripheral instance base addresses */ 91 /** Peripheral MC_RGM base address */ 92 #define IP_MC_RGM_BASE (0x4028C000u) 93 /** Peripheral MC_RGM base pointer */ 94 #define IP_MC_RGM ((MC_RGM_Type *)IP_MC_RGM_BASE) 95 /** Array initializer of MC_RGM peripheral base addresses */ 96 #define IP_MC_RGM_BASE_ADDRS { IP_MC_RGM_BASE } 97 /** Array initializer of MC_RGM peripheral base pointers */ 98 #define IP_MC_RGM_BASE_PTRS { IP_MC_RGM } 99 100 /* ---------------------------------------------------------------------------- 101 -- MC_RGM Register Masks 102 ---------------------------------------------------------------------------- */ 103 104 /*! 105 * @addtogroup MC_RGM_Register_Masks MC_RGM Register Masks 106 * @{ 107 */ 108 109 /*! @name DES - Destructive Event Status Register */ 110 /*! @{ */ 111 112 #define MC_RGM_DES_F_POR_MASK (0x1U) 113 #define MC_RGM_DES_F_POR_SHIFT (0U) 114 #define MC_RGM_DES_F_POR_WIDTH (1U) 115 #define MC_RGM_DES_F_POR(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_POR_SHIFT)) & MC_RGM_DES_F_POR_MASK) 116 117 #define MC_RGM_DES_FCCU_FTR_MASK (0x8U) 118 #define MC_RGM_DES_FCCU_FTR_SHIFT (3U) 119 #define MC_RGM_DES_FCCU_FTR_WIDTH (1U) 120 #define MC_RGM_DES_FCCU_FTR(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_FCCU_FTR_SHIFT)) & MC_RGM_DES_FCCU_FTR_MASK) 121 122 #define MC_RGM_DES_STCU_URF_MASK (0x10U) 123 #define MC_RGM_DES_STCU_URF_SHIFT (4U) 124 #define MC_RGM_DES_STCU_URF_WIDTH (1U) 125 #define MC_RGM_DES_STCU_URF(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_STCU_URF_SHIFT)) & MC_RGM_DES_STCU_URF_MASK) 126 127 #define MC_RGM_DES_MC_RGM_FRE_MASK (0x40U) 128 #define MC_RGM_DES_MC_RGM_FRE_SHIFT (6U) 129 #define MC_RGM_DES_MC_RGM_FRE_WIDTH (1U) 130 #define MC_RGM_DES_MC_RGM_FRE(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_MC_RGM_FRE_SHIFT)) & MC_RGM_DES_MC_RGM_FRE_MASK) 131 132 #define MC_RGM_DES_FXOSC_FAIL_MASK (0x100U) 133 #define MC_RGM_DES_FXOSC_FAIL_SHIFT (8U) 134 #define MC_RGM_DES_FXOSC_FAIL_WIDTH (1U) 135 #define MC_RGM_DES_FXOSC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_FXOSC_FAIL_SHIFT)) & MC_RGM_DES_FXOSC_FAIL_MASK) 136 137 #define MC_RGM_DES_PLL_LOL_MASK (0x200U) 138 #define MC_RGM_DES_PLL_LOL_SHIFT (9U) 139 #define MC_RGM_DES_PLL_LOL_WIDTH (1U) 140 #define MC_RGM_DES_PLL_LOL(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_PLL_LOL_SHIFT)) & MC_RGM_DES_PLL_LOL_MASK) 141 142 #define MC_RGM_DES_CORE_CLK_FAIL_MASK (0x400U) 143 #define MC_RGM_DES_CORE_CLK_FAIL_SHIFT (10U) 144 #define MC_RGM_DES_CORE_CLK_FAIL_WIDTH (1U) 145 #define MC_RGM_DES_CORE_CLK_FAIL(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_CORE_CLK_FAIL_SHIFT)) & MC_RGM_DES_CORE_CLK_FAIL_MASK) 146 147 #define MC_RGM_DES_AIPS_PLAT_CLK_FAIL_MASK (0x1000U) 148 #define MC_RGM_DES_AIPS_PLAT_CLK_FAIL_SHIFT (12U) 149 #define MC_RGM_DES_AIPS_PLAT_CLK_FAIL_WIDTH (1U) 150 #define MC_RGM_DES_AIPS_PLAT_CLK_FAIL(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_AIPS_PLAT_CLK_FAIL_SHIFT)) & MC_RGM_DES_AIPS_PLAT_CLK_FAIL_MASK) 151 152 #define MC_RGM_DES_HSE_CLK_FAIL_MASK (0x4000U) 153 #define MC_RGM_DES_HSE_CLK_FAIL_SHIFT (14U) 154 #define MC_RGM_DES_HSE_CLK_FAIL_WIDTH (1U) 155 #define MC_RGM_DES_HSE_CLK_FAIL(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_HSE_CLK_FAIL_SHIFT)) & MC_RGM_DES_HSE_CLK_FAIL_MASK) 156 157 #define MC_RGM_DES_SYS_DIV_FAIL_MASK (0x8000U) 158 #define MC_RGM_DES_SYS_DIV_FAIL_SHIFT (15U) 159 #define MC_RGM_DES_SYS_DIV_FAIL_WIDTH (1U) 160 #define MC_RGM_DES_SYS_DIV_FAIL(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_SYS_DIV_FAIL_SHIFT)) & MC_RGM_DES_SYS_DIV_FAIL_MASK) 161 162 #define MC_RGM_DES_HSE_TMPR_RST_MASK (0x20000U) 163 #define MC_RGM_DES_HSE_TMPR_RST_SHIFT (17U) 164 #define MC_RGM_DES_HSE_TMPR_RST_WIDTH (1U) 165 #define MC_RGM_DES_HSE_TMPR_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_HSE_TMPR_RST_SHIFT)) & MC_RGM_DES_HSE_TMPR_RST_MASK) 166 167 #define MC_RGM_DES_HSE_SNVS_RST_MASK (0x40000U) 168 #define MC_RGM_DES_HSE_SNVS_RST_SHIFT (18U) 169 #define MC_RGM_DES_HSE_SNVS_RST_WIDTH (1U) 170 #define MC_RGM_DES_HSE_SNVS_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_HSE_SNVS_RST_SHIFT)) & MC_RGM_DES_HSE_SNVS_RST_MASK) 171 172 #define MC_RGM_DES_SW_DEST_MASK (0x20000000U) 173 #define MC_RGM_DES_SW_DEST_SHIFT (29U) 174 #define MC_RGM_DES_SW_DEST_WIDTH (1U) 175 #define MC_RGM_DES_SW_DEST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_SW_DEST_SHIFT)) & MC_RGM_DES_SW_DEST_MASK) 176 177 #define MC_RGM_DES_DEBUG_DEST_MASK (0x40000000U) 178 #define MC_RGM_DES_DEBUG_DEST_SHIFT (30U) 179 #define MC_RGM_DES_DEBUG_DEST_WIDTH (1U) 180 #define MC_RGM_DES_DEBUG_DEST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_DEBUG_DEST_SHIFT)) & MC_RGM_DES_DEBUG_DEST_MASK) 181 /*! @} */ 182 183 /*! @name FES - Functional /External Reset Status Register */ 184 /*! @{ */ 185 186 #define MC_RGM_FES_F_EXR_MASK (0x1U) 187 #define MC_RGM_FES_F_EXR_SHIFT (0U) 188 #define MC_RGM_FES_F_EXR_WIDTH (1U) 189 #define MC_RGM_FES_F_EXR(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_F_EXR_SHIFT)) & MC_RGM_FES_F_EXR_MASK) 190 191 #define MC_RGM_FES_FCCU_RST_MASK (0x8U) 192 #define MC_RGM_FES_FCCU_RST_SHIFT (3U) 193 #define MC_RGM_FES_FCCU_RST_WIDTH (1U) 194 #define MC_RGM_FES_FCCU_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_FCCU_RST_SHIFT)) & MC_RGM_FES_FCCU_RST_MASK) 195 196 #define MC_RGM_FES_ST_DONE_MASK (0x10U) 197 #define MC_RGM_FES_ST_DONE_SHIFT (4U) 198 #define MC_RGM_FES_ST_DONE_WIDTH (1U) 199 #define MC_RGM_FES_ST_DONE(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_ST_DONE_SHIFT)) & MC_RGM_FES_ST_DONE_MASK) 200 201 #define MC_RGM_FES_SWT0_RST_MASK (0x40U) 202 #define MC_RGM_FES_SWT0_RST_SHIFT (6U) 203 #define MC_RGM_FES_SWT0_RST_WIDTH (1U) 204 #define MC_RGM_FES_SWT0_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_SWT0_RST_SHIFT)) & MC_RGM_FES_SWT0_RST_MASK) 205 206 #define MC_RGM_FES_JTAG_RST_MASK (0x200U) 207 #define MC_RGM_FES_JTAG_RST_SHIFT (9U) 208 #define MC_RGM_FES_JTAG_RST_WIDTH (1U) 209 #define MC_RGM_FES_JTAG_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_JTAG_RST_SHIFT)) & MC_RGM_FES_JTAG_RST_MASK) 210 211 #define MC_RGM_FES_HSE_SWT_RST_MASK (0x10000U) 212 #define MC_RGM_FES_HSE_SWT_RST_SHIFT (16U) 213 #define MC_RGM_FES_HSE_SWT_RST_WIDTH (1U) 214 #define MC_RGM_FES_HSE_SWT_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_HSE_SWT_RST_SHIFT)) & MC_RGM_FES_HSE_SWT_RST_MASK) 215 216 #define MC_RGM_FES_HSE_BOOT_RST_MASK (0x100000U) 217 #define MC_RGM_FES_HSE_BOOT_RST_SHIFT (20U) 218 #define MC_RGM_FES_HSE_BOOT_RST_WIDTH (1U) 219 #define MC_RGM_FES_HSE_BOOT_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_HSE_BOOT_RST_SHIFT)) & MC_RGM_FES_HSE_BOOT_RST_MASK) 220 221 #define MC_RGM_FES_SW_FUNC_MASK (0x20000000U) 222 #define MC_RGM_FES_SW_FUNC_SHIFT (29U) 223 #define MC_RGM_FES_SW_FUNC_WIDTH (1U) 224 #define MC_RGM_FES_SW_FUNC(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_SW_FUNC_SHIFT)) & MC_RGM_FES_SW_FUNC_MASK) 225 226 #define MC_RGM_FES_DEBUG_FUNC_MASK (0x40000000U) 227 #define MC_RGM_FES_DEBUG_FUNC_SHIFT (30U) 228 #define MC_RGM_FES_DEBUG_FUNC_WIDTH (1U) 229 #define MC_RGM_FES_DEBUG_FUNC(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_DEBUG_FUNC_SHIFT)) & MC_RGM_FES_DEBUG_FUNC_MASK) 230 /*! @} */ 231 232 /*! @name FERD - Functional Event Reset Disable Register */ 233 /*! @{ */ 234 235 #define MC_RGM_FERD_D_FCCU_RST_MASK (0x8U) 236 #define MC_RGM_FERD_D_FCCU_RST_SHIFT (3U) 237 #define MC_RGM_FERD_D_FCCU_RST_WIDTH (1U) 238 #define MC_RGM_FERD_D_FCCU_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_FCCU_RST_SHIFT)) & MC_RGM_FERD_D_FCCU_RST_MASK) 239 240 #define MC_RGM_FERD_D_SWT0_RST_MASK (0x40U) 241 #define MC_RGM_FERD_D_SWT0_RST_SHIFT (6U) 242 #define MC_RGM_FERD_D_SWT0_RST_WIDTH (1U) 243 #define MC_RGM_FERD_D_SWT0_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_SWT0_RST_SHIFT)) & MC_RGM_FERD_D_SWT0_RST_MASK) 244 245 #define MC_RGM_FERD_D_JTAG_RST_MASK (0x200U) 246 #define MC_RGM_FERD_D_JTAG_RST_SHIFT (9U) 247 #define MC_RGM_FERD_D_JTAG_RST_WIDTH (1U) 248 #define MC_RGM_FERD_D_JTAG_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_JTAG_RST_SHIFT)) & MC_RGM_FERD_D_JTAG_RST_MASK) 249 250 #define MC_RGM_FERD_D_DEBUG_FUNC_MASK (0x40000000U) 251 #define MC_RGM_FERD_D_DEBUG_FUNC_SHIFT (30U) 252 #define MC_RGM_FERD_D_DEBUG_FUNC_WIDTH (1U) 253 #define MC_RGM_FERD_D_DEBUG_FUNC(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_DEBUG_FUNC_SHIFT)) & MC_RGM_FERD_D_DEBUG_FUNC_MASK) 254 /*! @} */ 255 256 /*! @name FBRE - Functional Bidirectional Reset Enable Register */ 257 /*! @{ */ 258 259 #define MC_RGM_FBRE_BE_FCCU_RST_MASK (0x8U) 260 #define MC_RGM_FBRE_BE_FCCU_RST_SHIFT (3U) 261 #define MC_RGM_FBRE_BE_FCCU_RST_WIDTH (1U) 262 #define MC_RGM_FBRE_BE_FCCU_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_FCCU_RST_SHIFT)) & MC_RGM_FBRE_BE_FCCU_RST_MASK) 263 264 #define MC_RGM_FBRE_BE_ST_DONE_MASK (0x10U) 265 #define MC_RGM_FBRE_BE_ST_DONE_SHIFT (4U) 266 #define MC_RGM_FBRE_BE_ST_DONE_WIDTH (1U) 267 #define MC_RGM_FBRE_BE_ST_DONE(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_ST_DONE_SHIFT)) & MC_RGM_FBRE_BE_ST_DONE_MASK) 268 269 #define MC_RGM_FBRE_BE_SWT0_RST_MASK (0x40U) 270 #define MC_RGM_FBRE_BE_SWT0_RST_SHIFT (6U) 271 #define MC_RGM_FBRE_BE_SWT0_RST_WIDTH (1U) 272 #define MC_RGM_FBRE_BE_SWT0_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_SWT0_RST_SHIFT)) & MC_RGM_FBRE_BE_SWT0_RST_MASK) 273 274 #define MC_RGM_FBRE_BE_JTAG_RST_MASK (0x200U) 275 #define MC_RGM_FBRE_BE_JTAG_RST_SHIFT (9U) 276 #define MC_RGM_FBRE_BE_JTAG_RST_WIDTH (1U) 277 #define MC_RGM_FBRE_BE_JTAG_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_JTAG_RST_SHIFT)) & MC_RGM_FBRE_BE_JTAG_RST_MASK) 278 279 #define MC_RGM_FBRE_BE_HSE_SWT_RST_MASK (0x10000U) 280 #define MC_RGM_FBRE_BE_HSE_SWT_RST_SHIFT (16U) 281 #define MC_RGM_FBRE_BE_HSE_SWT_RST_WIDTH (1U) 282 #define MC_RGM_FBRE_BE_HSE_SWT_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_HSE_SWT_RST_SHIFT)) & MC_RGM_FBRE_BE_HSE_SWT_RST_MASK) 283 284 #define MC_RGM_FBRE_BE_HSE_BOOT_RST_MASK (0x100000U) 285 #define MC_RGM_FBRE_BE_HSE_BOOT_RST_SHIFT (20U) 286 #define MC_RGM_FBRE_BE_HSE_BOOT_RST_WIDTH (1U) 287 #define MC_RGM_FBRE_BE_HSE_BOOT_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_HSE_BOOT_RST_SHIFT)) & MC_RGM_FBRE_BE_HSE_BOOT_RST_MASK) 288 289 #define MC_RGM_FBRE_BE_SW_FUNC_MASK (0x20000000U) 290 #define MC_RGM_FBRE_BE_SW_FUNC_SHIFT (29U) 291 #define MC_RGM_FBRE_BE_SW_FUNC_WIDTH (1U) 292 #define MC_RGM_FBRE_BE_SW_FUNC(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_SW_FUNC_SHIFT)) & MC_RGM_FBRE_BE_SW_FUNC_MASK) 293 294 #define MC_RGM_FBRE_BE_DEBUG_FUNC_MASK (0x40000000U) 295 #define MC_RGM_FBRE_BE_DEBUG_FUNC_SHIFT (30U) 296 #define MC_RGM_FBRE_BE_DEBUG_FUNC_WIDTH (1U) 297 #define MC_RGM_FBRE_BE_DEBUG_FUNC(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_DEBUG_FUNC_SHIFT)) & MC_RGM_FBRE_BE_DEBUG_FUNC_MASK) 298 /*! @} */ 299 300 /*! @name FREC - Functional Reset Escalation Counter Register */ 301 /*! @{ */ 302 303 #define MC_RGM_FREC_FREC_MASK (0xFU) 304 #define MC_RGM_FREC_FREC_SHIFT (0U) 305 #define MC_RGM_FREC_FREC_WIDTH (4U) 306 #define MC_RGM_FREC_FREC(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FREC_FREC_SHIFT)) & MC_RGM_FREC_FREC_MASK) 307 /*! @} */ 308 309 /*! @name FRET - Functional Reset Escalation Threshold Register */ 310 /*! @{ */ 311 312 #define MC_RGM_FRET_FRET_MASK (0xFU) 313 #define MC_RGM_FRET_FRET_SHIFT (0U) 314 #define MC_RGM_FRET_FRET_WIDTH (4U) 315 #define MC_RGM_FRET_FRET(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FRET_FRET_SHIFT)) & MC_RGM_FRET_FRET_MASK) 316 /*! @} */ 317 318 /*! @name DRET - Destructive Reset Escalation Threshold Register */ 319 /*! @{ */ 320 321 #define MC_RGM_DRET_DRET_MASK (0xFU) 322 #define MC_RGM_DRET_DRET_SHIFT (0U) 323 #define MC_RGM_DRET_DRET_WIDTH (4U) 324 #define MC_RGM_DRET_DRET(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DRET_DRET_SHIFT)) & MC_RGM_DRET_DRET_MASK) 325 /*! @} */ 326 327 /*! @name ERCTRL - External Reset Control Register */ 328 /*! @{ */ 329 330 #define MC_RGM_ERCTRL_ERASSERT_MASK (0x1U) 331 #define MC_RGM_ERCTRL_ERASSERT_SHIFT (0U) 332 #define MC_RGM_ERCTRL_ERASSERT_WIDTH (1U) 333 #define MC_RGM_ERCTRL_ERASSERT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_ERCTRL_ERASSERT_SHIFT)) & MC_RGM_ERCTRL_ERASSERT_MASK) 334 /*! @} */ 335 336 /*! @name RDSS - Reset During Standby Status Register */ 337 /*! @{ */ 338 339 #define MC_RGM_RDSS_DES_RES_MASK (0x1U) 340 #define MC_RGM_RDSS_DES_RES_SHIFT (0U) 341 #define MC_RGM_RDSS_DES_RES_WIDTH (1U) 342 #define MC_RGM_RDSS_DES_RES(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_RDSS_DES_RES_SHIFT)) & MC_RGM_RDSS_DES_RES_MASK) 343 344 #define MC_RGM_RDSS_FES_RES_MASK (0x2U) 345 #define MC_RGM_RDSS_FES_RES_SHIFT (1U) 346 #define MC_RGM_RDSS_FES_RES_WIDTH (1U) 347 #define MC_RGM_RDSS_FES_RES(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_RDSS_FES_RES_SHIFT)) & MC_RGM_RDSS_FES_RES_MASK) 348 /*! @} */ 349 350 /*! @name FRENTC - Functional Reset Entry Timeout Control Register */ 351 /*! @{ */ 352 353 #define MC_RGM_FRENTC_FRET_EN_MASK (0x1U) 354 #define MC_RGM_FRENTC_FRET_EN_SHIFT (0U) 355 #define MC_RGM_FRENTC_FRET_EN_WIDTH (1U) 356 #define MC_RGM_FRENTC_FRET_EN(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FRENTC_FRET_EN_SHIFT)) & MC_RGM_FRENTC_FRET_EN_MASK) 357 358 #define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0xFFFFFFFEU) 359 #define MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT (1U) 360 #define MC_RGM_FRENTC_FRET_TIMEOUT_WIDTH (31U) 361 #define MC_RGM_FRENTC_FRET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT)) & MC_RGM_FRENTC_FRET_TIMEOUT_MASK) 362 /*! @} */ 363 364 /*! @name LPDEBUG - Low Power Debug Control Register */ 365 /*! @{ */ 366 367 #define MC_RGM_LPDEBUG_LP_DBG_EN_MASK (0x1U) 368 #define MC_RGM_LPDEBUG_LP_DBG_EN_SHIFT (0U) 369 #define MC_RGM_LPDEBUG_LP_DBG_EN_WIDTH (1U) 370 #define MC_RGM_LPDEBUG_LP_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_LPDEBUG_LP_DBG_EN_SHIFT)) & MC_RGM_LPDEBUG_LP_DBG_EN_MASK) 371 /*! @} */ 372 373 /*! 374 * @} 375 */ /* end of group MC_RGM_Register_Masks */ 376 377 /*! 378 * @} 379 */ /* end of group MC_RGM_Peripheral_Access_Layer */ 380 381 #endif /* #if !defined(S32K344_MC_RGM_H_) */ 382
