1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef POWER_IP_MC_ME_TYPES_H 8 #define POWER_IP_MC_ME_TYPES_H 9 10 /** 11 * @file Power_Ip_MC_ME_Types.h 12 * @version 3.0.0 13 * 14 * @brief POWER IP driver header file. 15 * @details POWER IP driver header file. 16 * 17 * @addtogroup POWER_DRIVER Power Ip Driver 18 * @{ 19 */ 20 21 #ifdef __cplusplus 22 extern "C"{ 23 #endif 24 25 26 /*================================================================================================== 27 INCLUDE FILES 28 1) system and project includes 29 2) needed interfaces from external units 30 3) internal and external interfaces from this unit 31 ==================================================================================================*/ 32 #include "Power_Ip_Specific.h" 33 34 /*================================================================================================== 35 SOURCE FILE VERSION INFORMATION 36 ==================================================================================================*/ 37 #define POWER_IP_MC_ME_TYPES_VENDOR_ID 43 38 #define POWER_IP_MC_ME_TYPES_AR_RELEASE_MAJOR_VERSION 4 39 #define POWER_IP_MC_ME_TYPES_AR_RELEASE_MINOR_VERSION 7 40 #define POWER_IP_MC_ME_TYPES_AR_RELEASE_REVISION_VERSION 0 41 #define POWER_IP_MC_ME_TYPES_SW_MAJOR_VERSION 3 42 #define POWER_IP_MC_ME_TYPES_SW_MINOR_VERSION 0 43 #define POWER_IP_MC_ME_TYPES_SW_PATCH_VERSION 0 44 45 /*================================================================================================== 46 FILE VERSION CHECKS 47 ==================================================================================================*/ 48 49 /* Check if Power_Ip_MC_ME_Types.h file and Power_Ip_Specific.h file have same versions */ 50 #if (POWER_IP_MC_ME_TYPES_VENDOR_ID != POWER_IP_SPECIFIC_VENDOR_ID) 51 #error "Power_Ip_MC_ME_Types.h and Power_Ip_Specific.h have different vendor IDs" 52 #endif 53 54 /* Check if Power_Ip_MC_ME_Types.h file and Power_Ip_Specific.h file are of the same Autosar version */ 55 #if ((POWER_IP_MC_ME_TYPES_AR_RELEASE_MAJOR_VERSION != POWER_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION) || \ 56 (POWER_IP_MC_ME_TYPES_AR_RELEASE_MINOR_VERSION != POWER_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION) || \ 57 (POWER_IP_MC_ME_TYPES_AR_RELEASE_REVISION_VERSION != POWER_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION)) 58 #error "AutoSar Version Numbers of Power_Ip_MC_ME_Types.h and Power_Ip_Specific.h are different" 59 #endif 60 61 /* Check if Power_Ip_MC_ME_Types.h file and Power_Ip_Specific.h file are of the same Software version */ 62 #if ((POWER_IP_MC_ME_TYPES_SW_MAJOR_VERSION != POWER_IP_SPECIFIC_SW_MAJOR_VERSION) || \ 63 (POWER_IP_MC_ME_TYPES_SW_MINOR_VERSION != POWER_IP_SPECIFIC_SW_MINOR_VERSION) || \ 64 (POWER_IP_MC_ME_TYPES_SW_PATCH_VERSION != POWER_IP_SPECIFIC_SW_PATCH_VERSION)) 65 #error "Software Version Numbers of Power_Ip_MC_ME_Types.h and Power_Ip_Specific.h are different" 66 #endif 67 68 /*================================================================================================== 69 * CONSTANTS 70 ==================================================================================================*/ 71 72 /*================================================================================================== 73 DEFINES AND MACROS 74 ==================================================================================================*/ 75 76 /***********************************************************/ 77 /* MC_ME_CTL_KEY */ 78 /***********************************************************/ 79 #define MC_ME_CTL_KEY_DIRECT_KEY_U32 ((uint32)0x00005AF0U) 80 #define MC_ME_CTL_KEY_INVERTED_KEY_U32 ((uint32)0x0000A50FU) 81 82 /***********************************************************/ 83 /* MC_ME_MODE_STAT */ 84 /***********************************************************/ 85 #define MC_ME_MODE_STAT_PREV_MODE_RESET_U32 ((uint32)0x00000000U) 86 #define MC_ME_MODE_STAT_PREV_MODE_STANDBY_U32 (MC_ME_MODE_STAT_PREV_MODE_MASK) 87 88 /***********************************************************/ 89 /* MC_ME_PRTNx_PCONF */ 90 /***********************************************************/ 91 #define MC_ME_PRTNX_PCONF_PCE_EN_U32 (MC_ME_PRTN0_PCONF_PCE_MASK) 92 #define MC_ME_PRTNX_PCONF_PCE_DIS_U32 ((uint32)0x00000000U) 93 94 /***********************************************************/ 95 /* MC_ME_PRTNx_PUPD */ 96 /***********************************************************/ 97 #define MC_ME_PRTNX_PUPD_PCUD_TRIG_U32 (MC_ME_PRTN0_PUPD_PCUD_MASK) 98 #define MC_ME_PRTNX_PUPD_PCUD_NOT_TRIG_U32 ((uint32)0x00000000U) 99 100 /***********************************************************/ 101 /* MC_ME_PRTNx_STAT */ 102 /***********************************************************/ 103 #define MC_ME_PRTNX_STAT_PCS_ACTIVE_U32 (MC_ME_PRTN0_STAT_PCS_MASK) 104 #define MC_ME_PRTNX_STAT_PCS_INACTIVE_U32 ((uint32)0x00000000U) 105 106 /***********************************************************/ 107 /* MC_ME_PRTNn_COREm_PCONF */ 108 /***********************************************************/ 109 #define MC_ME_PRTNX_COREX_PCONF_CCE_EN_U32 (MC_ME_PRTN0_CORE0_PCONF_CCE_MASK) 110 #define MC_ME_PRTNX_COREX_PCONF_CCE_DIS_U32 ((uint32)0x00000000U) 111 112 /***********************************************************/ 113 /* MC_ME_PRTNn_COREm_PUPD */ 114 /***********************************************************/ 115 #define MC_ME_PRTNX_COREX_PUPD_CCUPD_TRIG_U32 (MC_ME_PRTN0_CORE0_PUPD_CCUPD_MASK) 116 #define MC_ME_PRTNX_COREX_PUPD_CCUPD_NOT_TRIG_U32 ((uint32)0x00000000U) 117 118 /***********************************************************/ 119 /* MC_ME_PRTNn_COREm_STAT */ 120 /***********************************************************/ 121 #define MC_ME_PRTNX_COREX_STAT_WFI_EXECUTED_U32 (MC_ME_PRTN0_CORE0_STAT_WFI_MASK) 122 #define MC_ME_PRTNX_COREX_STAT_WFI_NOT_EXECUTED_U32 ((uint32)0x00000000U) 123 124 #define MC_ME_PRTNX_COREX_STAT_CCS_ACTIVE_U32 (MC_ME_PRTN0_CORE0_STAT_CCS_MASK) 125 #define MC_ME_PRTNX_COREX_STAT_CCS_INACTIVE_U32 ((uint32)0x00000000U) 126 127 /*================================================================================================== 128 * ENUMS 129 ==================================================================================================*/ 130 131 132 /*================================================================================================== 133 * STRUCTURES AND OTHER TYPEDEFS 134 ==================================================================================================*/ 135 136 137 /** 138 * @brief MC_ME Core Configuration. 139 * @details This structure contains information for configuring the cores. 140 * The definitions for each Core setting within the structure Power_Ip_MC_ME_CoreConfigType shall contain: 141 * - The index of the Core (within its partition). 142 * - The boot address of the Core. 143 * - Power management information (i.e. start or shutdown the Core). 144 */ 145 typedef struct 146 { 147 /** @brief Specifies whether the given core is under MCU control. */ 148 boolean CoreUnderMcuControl; 149 150 /** @brief The index of the core within the partition. */ 151 uint8 CoreIndex; 152 153 /** @brief The boot address of the core. */ 154 uint32 * CoreBootAddress; 155 156 /** @brief The process configuration register value of the core. */ 157 uint32 CorePconfRegValue; 158 159 } Power_Ip_MC_ME_CoreConfigType; 160 161 /** 162 * @brief MC_ME COFB Configuration. 163 * @details This structure contains information for configuring the COFBs (Collection of Functional Blocks). 164 * The definitions for each COFB setting within the structure Power_Ip_MC_ME_CofbConfigType shall contain: 165 * - The index of the COFB (within its partition). 166 * - The list of peripherals enable/disable (i.e. the value of the PRTNx_COFBx_CLKEN register). 167 */ 168 typedef struct 169 { 170 /** @brief Specifies whether the given COFB set is under MCU control. */ 171 boolean CofbUnderMcuControl; 172 173 /** @brief The index of the COFB set within the partition. */ 174 uint8 CofbIndex; 175 176 /** @brief The clock enable register value of the COFB set. */ 177 uint32 CofbClkenRegValue; 178 179 /** @brief Mask containing the COFB blocks to be updated. */ 180 uint32 CofbBlocksToUpdateMask; 181 182 } Power_Ip_MC_ME_CofbConfigType; 183 184 /** 185 * @brief MC_ME Partition Configuration. 186 * @details This structure contains information for configuring the Partitions. 187 * The definitions for each Partition setting within the structure Power_Ip_MC_ME_PartitionConfigType shall contain: 188 * - The index of the Partition. 189 * - The configuration settings for the COFBs contained within the Partition. 190 * - The configuration settings for the Cores contained within the Partition. 191 */ 192 typedef struct 193 { 194 /** @brief Specifies whether the given partition is under MCU control. */ 195 boolean PartitionUnderMcuControl; 196 197 /** @brief Specifies whether the given partition's power management is under MCU control */ 198 boolean PartitionPowerUnderMcuControl; 199 200 /** @brief The index of the partition. */ 201 uint8 PartitionIndex; 202 203 /** @brief The process configuration register value of the partition. */ 204 uint32 PartitionPconfRegValue; 205 206 /** @brief Mask containing the Partition triggers (PCE/OSSE/etc) to be updated. */ 207 uint32 PartitionTriggerMask; 208 209 /** @brief Number of COFBs within the partition. */ 210 uint8 NumberOfCofbs; 211 /** @brief The configuration of the COFBs. */ 212 const Power_Ip_MC_ME_CofbConfigType (*ArrayPartitionCofbConfigPtr)[]; 213 214 /** @brief Number of cores within the partition. */ 215 uint8 NumberOfCores; 216 /** @brief The configuration of the cores. */ 217 const Power_Ip_MC_ME_CoreConfigType (*ArrayPartitionCoreConfigPtr)[]; 218 219 } Power_Ip_MC_ME_PartitionConfigType; 220 221 /** 222 * @brief MC_ME IP Configuration. 223 * @details This structure contains information for configuring the entire MC_ME IP. 224 */ 225 typedef struct 226 { 227 #if (defined(POWER_IP_ENTER_LOW_POWER_MODE)) 228 #if (POWER_IP_ENTER_LOW_POWER_MODE == STD_ON) 229 /** @brief MC_ME Main Core ID register */ 230 uint32 MainCoreIdRegValue; 231 #endif 232 #endif 233 #if (defined(POWER_IP_LOCKSTEP_CTRL_SUPPORT)) 234 #if (POWER_IP_LOCKSTEP_CTRL_SUPPORT == STD_ON) 235 /** @brief The control for indicating a set of cores for lockstep execution. */ 236 boolean CoreLockStepCtrl; 237 #endif 238 #endif 239 /** @brief MC_ME Mode Partition Settings. */ 240 const Power_Ip_MC_ME_PartitionConfigType (*ArrayPartitionConfigPtr)[POWER_IP_MAX_NUMBER_OF_PARTITIONS]; 241 242 } Power_Ip_MC_ME_ModeConfigType; 243 244 245 /*================================================================================================== 246 * GLOBAL VARIABLE DECLARATIONS 247 ==================================================================================================*/ 248 249 250 /*================================================================================================== 251 * FUNCTION PROTOTYPES 252 ==================================================================================================*/ 253 254 255 #ifdef __cplusplus 256 } 257 #endif 258 259 /** @} */ 260 #endif /* POWER_IP_MC_ME_TYPES_H */ 261 262
