1 /* 2 * Copyright 2021-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CLOCK_IP_SPECIFIC_H 8 #define CLOCK_IP_SPECIFIC_H 9 10 /** 11 * @file Clock_Ip_Specific.h 12 * @version 0.9.0 13 * 14 * @brief CLOCK IP specific header file. 15 * @details CLOCK IP specific header file. 16 * 17 * @addtogroup CLOCK_DRIVER Clock Ip Driver 18 * @{ 19 */ 20 21 #ifdef __cplusplus 22 extern "C"{ 23 #endif 24 25 26 /*================================================================================================== 27 * INCLUDE FILES 28 * 1) system and project includes 29 * 2) needed interfaces from external units 30 * 3) internal and external interfaces from this unit 31 ==================================================================================================*/ 32 #include "Clock_Ip_Cfg_Defines.h" 33 #include "Mcal.h" 34 35 #if defined(CLOCK_IP_DERIVATIVE_001) 36 #include "Clock_Ip_Derivative_001.h" 37 #endif 38 #if defined(CLOCK_IP_DERIVATIVE_002) 39 #include "Clock_Ip_Derivative_002.h" 40 #endif 41 42 43 44 /*================================================================================================== 45 SOURCE FILE VERSION INFORMATION 46 ==================================================================================================*/ 47 #define CLOCK_IP_SPECIFIC_VENDOR_ID 43 48 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION 4 49 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION 7 50 #define CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION 0 51 #define CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION 0 52 #define CLOCK_IP_SPECIFIC_SW_MINOR_VERSION 9 53 #define CLOCK_IP_SPECIFIC_SW_PATCH_VERSION 0 54 55 /*================================================================================================== 56 FILE VERSION CHECKS 57 ==================================================================================================*/ 58 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Cfg_Defines.h file have same versions */ 59 #if (CLOCK_IP_SPECIFIC_VENDOR_ID != CLOCK_IP_CFG_DEFINES_VENDOR_ID) 60 #error "Clock_Ip_Specific.h and Clock_Ip_Cfg_Defines.h have different vendor IDs" 61 #endif 62 63 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Cfg_Defines.h file are of the same Autosar version */ 64 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MAJOR_VERSION) || \ 65 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_MINOR_VERSION) || \ 66 (CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION != CLOCK_IP_CFG_DEFINES_AR_RELEASE_REVISION_VERSION)) 67 #error "AutoSar Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Cfg_Defines.h are different" 68 #endif 69 70 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Cfg_Defines.h file are of the same Software version */ 71 #if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MAJOR_VERSION) || \ 72 (CLOCK_IP_SPECIFIC_SW_MINOR_VERSION != CLOCK_IP_CFG_DEFINES_SW_MINOR_VERSION) || \ 73 (CLOCK_IP_SPECIFIC_SW_PATCH_VERSION != CLOCK_IP_CFG_DEFINES_SW_PATCH_VERSION)) 74 #error "Software Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Cfg_Defines.h are different" 75 #endif 76 77 #if defined(CLOCK_IP_DERIVATIVE_001) 78 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Derivative_001.h file have same versions */ 79 #if (CLOCK_IP_SPECIFIC_VENDOR_ID != CLOCK_IP_DERIVATIVE_001_VENDOR_ID) 80 #error "Clock_Ip_Specific.h and Clock_Ip_Derivative_001.h have different vendor IDs" 81 #endif 82 83 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Derivative_001.h file are of the same Autosar version */ 84 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != CLOCK_IP_DERIVATIVE_001_AR_RELEASE_MAJOR_VERSION) || \ 85 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != CLOCK_IP_DERIVATIVE_001_AR_RELEASE_MINOR_VERSION) || \ 86 (CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION != CLOCK_IP_DERIVATIVE_001_AR_RELEASE_REVISION_VERSION)) 87 #error "AutoSar Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Derivative_001.h are different" 88 #endif 89 90 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Derivative_001.h file are of the same Software version */ 91 #if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION != CLOCK_IP_DERIVATIVE_001_SW_MAJOR_VERSION) || \ 92 (CLOCK_IP_SPECIFIC_SW_MINOR_VERSION != CLOCK_IP_DERIVATIVE_001_SW_MINOR_VERSION) || \ 93 (CLOCK_IP_SPECIFIC_SW_PATCH_VERSION != CLOCK_IP_DERIVATIVE_001_SW_PATCH_VERSION)) 94 #error "Software Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Derivative_001.h are different" 95 #endif 96 #endif 97 98 #if defined(CLOCK_IP_DERIVATIVE_002) 99 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Derivative_002.h file have same versions */ 100 #if (CLOCK_IP_SPECIFIC_VENDOR_ID != CLOCK_IP_DERIVATIVE_002_VENDOR_ID) 101 #error "Clock_Ip_Specific.h and Clock_Ip_Derivative_002.h have different vendor IDs" 102 #endif 103 104 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Derivative_002.h file are of the same Autosar version */ 105 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != CLOCK_IP_DERIVATIVE_002_AR_RELEASE_MAJOR_VERSION) || \ 106 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != CLOCK_IP_DERIVATIVE_002_AR_RELEASE_MINOR_VERSION) || \ 107 (CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION != CLOCK_IP_DERIVATIVE_002_AR_RELEASE_REVISION_VERSION)) 108 #error "AutoSar Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Derivative_002.h are different" 109 #endif 110 111 /* Check if Clock_Ip_Specific.h file and Clock_Ip_Derivative_002.h file are of the same Software version */ 112 #if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION != CLOCK_IP_DERIVATIVE_002_SW_MAJOR_VERSION) || \ 113 (CLOCK_IP_SPECIFIC_SW_MINOR_VERSION != CLOCK_IP_DERIVATIVE_002_SW_MINOR_VERSION) || \ 114 (CLOCK_IP_SPECIFIC_SW_PATCH_VERSION != CLOCK_IP_DERIVATIVE_002_SW_PATCH_VERSION)) 115 #error "Software Version Numbers of Clock_Ip_Specific.h and Clock_Ip_Derivative_002.h are different" 116 #endif 117 #endif 118 119 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK 120 /* Check if Clock_Ip_Specific.h file and Mcal.h file are of the same Autosar version */ 121 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION != MCAL_AR_RELEASE_MAJOR_VERSION) || \ 122 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION != MCAL_AR_RELEASE_MINOR_VERSION)) 123 #error "AutoSar Version Numbers of Clock_Ip_Specific.h and Mcal.h are different" 124 #endif 125 #endif 126 /*================================================================================================== 127 * CONSTANTS 128 ==================================================================================================*/ 129 130 /*================================================================================================== 131 * DEFINES AND MACROS 132 ==================================================================================================*/ 133 134 #define CLOCK_IP_ALL_CALLBACKS_COUNT 10U 135 #define CLOCK_IP_TRIGGER_VALUE 0xFFFFFFFFU /* Trigger value. */ 136 137 #define CLOCK_IP_NUMBER_OF_HARDWARE_DFS 12U 138 #define CLOCK_IP_NUMBER_OF_HARDWARE_PLL 5U 139 140 #define DFS_PORTSR_PORTSTAT_MASK (DFS_PORTSR_PORTSTAT5_MASK | DFS_PORTSR_PORTSTAT4_MASK | DFS_PORTSR_PORTSTAT3_MASK | DFS_PORTSR_PORTSTAT2_MASK | DFS_PORTSR_PORTSTAT1_MASK | DFS_PORTSR_PORTSTAT0_MASK) 141 #define DFS_PORTSR_PORTSTAT_SHIFT (DFS_PORTSR_PORTSTAT0_SHIFT) 142 143 #define MC_ME_AE_TRANSITION_IS_ON_GOING MC_ME_AE_GS_S_MTRANS_MASK 144 145 #define CLOCK_IP_MC_CGM_MUX_MUX_DIV_COUNT 11u 146 #define CLOCK_IP_MC_CGM_PCFS_COUNT 64u 147 #define CLOCK_IP_PERIPHERALS_NO 64u 148 149 #define CLOCK_IP_MC_CGM_INSTANCES_COUNT 10U 150 #define CLOCK_IP_MC_CGM_MUXS_COUNT 15U 151 #define CLOCK_IP_XOSC_INSTANCES_ARRAY_SIZE 1U 152 #define CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE 3U 153 #define CLOCK_IP_LFASTPLL_INSTANCES_ARRAY_SIZE 2U 154 #define CLOCK_IP_DFS_INSTANCES_ARRAY_SIZE 2U 155 #define CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE 27U 156 #define CLOCK_IP_PERIPHERAL_GROUPS_COUNT 7U 157 #define CLOCK_IP_CMU_INFO_SIZE 28U 158 #define CLOCK_IP_GATE_INFO_SIZE 101U 159 #define CLOCK_IP_EXTENSIONS_SIZE 133U 160 #define CLOCK_IP_GPR_INSTANCES_COUNT 6U 161 #define CLOCK_IP_CLKOUTS_COUNT 5U 162 163 #define MC_CGM_MUX_DC_DE_MASK MC_CGM_MUX_0_DC_0_DE_MASK 164 #define MC_CGM_MUX_DC_DE_SHIFT MC_CGM_MUX_0_DC_0_DE_SHIFT 165 #define MC_CGM_MUX_CSC_SAFE_SW_MASK MC_CGM_MUX_0_CSS_SAFE_SW_MASK 166 #define MC_CGM_MUX_CSC_CLK_SW_MASK MC_CGM_MUX_0_CSC_CLK_SW_MASK 167 #define MC_CGM_MUX_CSC_RAMPUP_MASK MC_CGM_MUX_0_CSC_RAMPUP_MASK 168 #define MC_CGM_MUX_CSC_RAMPDOWN_MASK MC_CGM_MUX_0_CSC_RAMPDOWN_MASK 169 #define MC_CGM_MUX_CSS_SWIP_MASK MC_CGM_MUX_0_CSS_SWIP_MASK 170 #define MC_CGM_MUX_CSS_SWIP_IN_PROGRESS MC_CGM_MUX_CSS_SWIP_MASK 171 #define MC_CGM_MUX_CSS_SWTRG_MASK MC_CGM_MUX_0_CSS_SWTRG_MASK 172 #define MC_CGM_MUX_CSS_SWTRG_SHIFT MC_CGM_MUX_0_CSS_SWTRG_SHIFT 173 #define CLOCK_IP_MC_CGM_MUX_CSS_SWTRG_SUCCEEDED 1U 174 #define MC_CGM_MUX_CSS_CLK_SW_MASK MC_CGM_MUX_0_CSS_CLK_SW_MASK 175 #define CLOCK_IP_MC_CGM_MUX_CSS_CLK_SW_NOT_REQUESTED 0U 176 177 #define MC_CGM_MUX_CSC_CG_MASK MC_CGM_MUX_4_CSC_CG_MASK 178 #define MC_CGM_MUX_CSC_FCG_MASK MC_CGM_MUX_4_CSC_FCG_MASK 179 #define MC_CGM_MUX_CSS_CS_MASK MC_CGM_MUX_4_CSS_CS_MASK 180 #define MC_CGM_MUX_CSS_CS_TRANSPARENT MC_CGM_MUX_CSS_CS_MASK 181 182 #define MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK MC_CGM_MUX_0_DIV_UPD_STAT_DIV_STAT_MASK 183 #define MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_PENDING MC_CGM_MUX_DIV_UPD_STAT_DIV_STAT_MASK 184 #define MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL_MASK 185 #define MC_CGM_MUX_DIV_TRIG_TRIGGER(x) MC_CGM_MUX_7_DIV_TRIG_CTRL_TCTL(x) 186 #define MC_CGM_MUX_DIV_TRIG_CTRL_COMMON_TRIGGER_DIVIDER_UPDATE MC_CGM_MUX_DIV_TRIG_CTRL_TCTL_MASK 187 188 189 #define MC_CGM_PCFS_DIVC_INIT(x) MC_CGM_PCFS_DIVC12_INIT(x) 190 #define MC_CGM_PCFS_DIVC_RATE(x) MC_CGM_PCFS_DIVC12_RATE(x) 191 #define MC_CGM_PCFS_DIVE_DIVE(x) MC_CGM_PCFS_DIVE12_DIVE(x) 192 #define MC_CGM_PCFS_DIVS_DIVS(x) MC_CGM_PCFS_DIVS12_DIVS(x) 193 194 #define CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED CMU_FC_GCR_FCE_MASK 195 #define CLOCK_IP_CMU_FREQUENCY_CHECK_STOPPED 0U 196 #define CLOCK_IP_CMU_ISR_MASK 3U 197 198 #define GPR_PCTL_MASK GPR3_PCTL_EDMACEPCTL_PCTL_MASK 199 200 #define CLOCK_IP_DIVIDER_HAVE_DIV_FMT STD_ON 201 /*================================================================================================== 202 * ENUMS 203 ==================================================================================================*/ 204 205 /*================================================================================================== 206 * STRUCTURES AND OTHER TYPEDEFS 207 ==================================================================================================*/ 208 typedef struct { 209 uint32 CSC; /**< Clock Mux Select Control Register */ 210 const uint32 CSS; /**< Clock Mux Select Status Register */ 211 uint32 Divider[CLOCK_IP_MC_CGM_MUX_MUX_DIV_COUNT]; /**< Clock Divider Control Register */ 212 uint32 MUX_DIV_TRIG_CTRL; /**< Clock Divider trigger Control Register */ 213 uint32 MUX_DIV_TRIG; /**< Clock Divider trigger Register */ 214 const uint32 MUX_DIV_UPD_STAT; /**< Clock Divider Update Status Register */ 215 216 }volatile Clock_Ip_CgmMuxType; 217 218 typedef struct { 219 220 uint32 PCFS_SDUR; /**< PCFS Step Duration, offset: 0x0 */ 221 struct { /* offset: 0x4, array step: 0xC */ 222 uint32 DIVC; /**< PCFS Divider Change 12 Register, array offset: 0x4, array step: 0xC */ 223 uint32 DIVE; /**< PCFS Divider End 12 Register, array offset: 0x8, array step: 0xC */ 224 uint32 DIVS; /**< PCFS Divider Start 12 Register, array offset: 0xC, array step: 0xC */ 225 } PCFS[CLOCK_IP_MC_CGM_PCFS_COUNT]; 226 227 }Clock_Ip_CgmPcfsType; 228 229 typedef struct { 230 volatile uint32 PCTL[CLOCK_IP_PERIPHERALS_NO]; 231 }Clock_Ip_GprClockControlEnable_Type; 232 233 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 234 /** MC_ME_AE - Register Layout Typedef */ 235 typedef struct { 236 uint32_t POWER_MODE_CONFIG[3u]; /**< Power Mode Configuration, offset: 0x28, 0x2C and 0x30 */ 237 }volatile Clock_Ip_SystemClockType; 238 #endif 239 240 /** XOSC - Register Layout Typedef */ 241 typedef struct { 242 uint32 CTRL; /**< XOSC Control Register, offset: 0x0 */ 243 const uint32 STAT; /**< Oscillator Status Register, offset: 0x4 */ 244 }volatile Clock_Ip_ExtOSCType; 245 246 /** CMU - Register Layout Typedef */ 247 typedef struct { 248 uint32 GCR; /**< Global Configuration Register, offset: 0x0 */ 249 uint32 RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ 250 uint32 HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ 251 uint32 LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ 252 volatile uint32 SR; /**< Status Register, offset: 0x10 */ 253 uint32 IER; /**< Interrupt Enable Register, offset: 0x14 */ 254 255 }Clock_Ip_ClockMonitorType; 256 257 typedef struct{ 258 259 Clock_Ip_NameType Name; /* Name of the clock that can be monitored/supports cmu (clock monitor) */ 260 Clock_Ip_NameType Reference; /* Name of the reference clock */ 261 Clock_Ip_NameType Bus; /* Name of the bus clock */ 262 263 Clock_Ip_ClockMonitorType* CmuInstance; 264 265 }Clock_Ip_CmuInfoType; 266 267 typedef struct 268 { 269 uint8 GroupIndex; 270 uint8 GateIndex; 271 uint8 GateBitField; 272 273 }Clock_Ip_GateInfoType; 274 275 typedef struct 276 { 277 uint32 SelectorValueMask; 278 uint32 SelectorValueShift; 279 uint32 DividerValueMask; 280 uint32 DividerValueShift; 281 282 }Clock_Ip_ClockExtensionType; 283 284 typedef struct 285 { 286 PLLDIG_Type* PllInstance; 287 uint8 DivsNo; 288 289 }Clock_Ip_PllType; 290 291 typedef struct 292 { 293 LFAST_Type* PllInstance; 294 295 }Clock_Ip_LfastPllType; 296 /*================================================================================================== 297 * GLOBAL VARIABLE DECLARATIONS 298 ==================================================================================================*/ 299 300 /* Clock start constant section data */ 301 #define MCU_START_SEC_CONST_UNSPECIFIED 302 #include "Mcu_MemMap.h" 303 304 extern Clock_Ip_CgmMuxType* const Clock_Ip_apxCgm[CLOCK_IP_MC_CGM_INSTANCES_COUNT][CLOCK_IP_MC_CGM_MUXS_COUNT]; 305 extern volatile Clock_Ip_CgmPcfsType* const Clock_Ip_apxCgmPcfs[CLOCK_IP_MC_CGM_INSTANCES_COUNT]; 306 extern Clock_Ip_ExtOSCType* const Clock_Ip_apxXosc[CLOCK_IP_XOSC_INSTANCES_ARRAY_SIZE]; 307 extern Clock_Ip_PllType const Clock_Ip_apxPll[CLOCK_IP_PLL_INSTANCES_ARRAY_SIZE]; 308 extern Clock_Ip_LfastPllType const Clock_Ip_apxLfastPll[CLOCK_IP_LFASTPLL_INSTANCES_ARRAY_SIZE]; 309 extern DFS_Type* const Clock_Ip_apxDfs[CLOCK_IP_DFS_INSTANCES_ARRAY_SIZE]; 310 extern Clock_Ip_ClockMonitorType * const Clock_Ip_apxCmu[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE]; 311 extern Clock_Ip_NameType const Clock_Ip_aeCmuNames[CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE]; 312 313 extern Clock_Ip_GprClockControlEnable_Type* const Clock_Ip_apxGprClockControlEnable[CLOCK_IP_PERIPHERAL_GROUPS_COUNT]; 314 315 extern const Clock_Ip_CmuInfoType Clock_Ip_axCmuInfo[CLOCK_IP_CMU_INFO_SIZE]; 316 317 extern const Clock_Ip_GateInfoType Clock_Ip_axGateInfo[CLOCK_IP_GATE_INFO_SIZE]; 318 319 extern const Clock_Ip_ClockExtensionType Clock_Ip_axFeatureExtensions[CLOCK_IP_EXTENSIONS_SIZE]; 320 321 #if defined(CLOCK_IP_HAS_SYSTEM_CLK) 322 extern Clock_Ip_SystemClockType* const Clock_Ip_apxSystemClock; 323 #endif 324 325 extern volatile uint32* const Clock_Ip_apxGprClkout[CLOCK_IP_GPR_INSTANCES_COUNT][CLOCK_IP_CLKOUTS_COUNT]; 326 327 /* Clock stop constant section data */ 328 #define MCU_STOP_SEC_CONST_UNSPECIFIED 329 #include "Mcu_MemMap.h" 330 331 /* Clock start constant section data */ 332 #define MCU_START_SEC_CONST_8 333 #include "Mcu_MemMap.h" 334 335 extern const uint8 Clock_Ip_au8SoftwareMuxResetValue[CLOCK_IP_FEATURE_NAMES_NO]; 336 337 /* Clock stop constant section data */ 338 #define MCU_STOP_SEC_CONST_8 339 #include "Mcu_MemMap.h" 340 341 342 /* Clock start constant section data */ 343 #define MCU_START_SEC_CONST_16 344 #include "Mcu_MemMap.h" 345 346 extern const uint16 Clock_Ip_au16SelectorEntryHardwareValue[CLOCK_IP_FEATURE_NAMES_NO]; 347 extern const uint16 Clock_Ip_au16SelectorEntryClkoutHardwareValue[CLOCK_IP_FEATURE_NAMES_NO]; 348 #ifdef CLOCK_IP_MC_ME_AE_GS_S_SYSCLK 349 extern const uint16 Clock_Ip_au16SelectorEntryAeHardwareValue[CLOCK_IP_FEATURE_NAMES_NO]; 350 #endif 351 /* Clock stop constant section data */ 352 #define MCU_STOP_SEC_CONST_16 353 #include "Mcu_MemMap.h" 354 355 356 357 /*================================================================================================== 358 * FUNCTION PROTOTYPES 359 ==================================================================================================*/ 360 361 /* Clock start section code */ 362 #define MCU_START_SEC_CODE 363 364 #include "Mcu_MemMap.h" 365 366 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT)) 367 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT) 368 #if (defined(MCAL_CMU_AE_REG_PROT_AVAILABLE)) 369 #if(STD_ON == MCAL_CMU_AE_REG_PROT_AVAILABLE) 370 void Clock_Ip_SpecificSetUserAccessAllowed(void); 371 #endif 372 #endif /* MCAL_CMU_AE_REG_PROT_AVAILABLE */ 373 #endif 374 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */ 375 void Clock_Ip_McMeEnterKey(void); 376 377 /* Clock stop section code */ 378 #define MCU_STOP_SEC_CODE 379 380 #include "Mcu_MemMap.h" 381 382 #ifdef __cplusplus 383 } 384 #endif 385 386 /** @} */ 387 388 #endif /* CLOCK_IP_SPECIFIC_H */ 389 390
