1 /***************************************************************************//**
2 * \file cy_device.h
3 * \version 2.0
4 *
5 * This file specifies the structure for core and peripheral block HW base
6 * addresses, versions, and parameters.
7 *
8 ********************************************************************************/
9 #ifndef CY_DEVICE_H_
10 #define CY_DEVICE_H_
11 
12 #include <stdint.h>
13 #include <stddef.h>
14 #include "cy_utils.h"
15 #include "cy_device_headers.h"
16 #include "startup_cat1c.h"
17 #include "ip/cyip_cpuss.h"
18 
19 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 1, \
20 'Checked manually. The definition is a part of linker script.')
21 
22 /* Device descriptor type */
23 typedef struct
24 {
25     /* Base HW addresses */
26     uint32_t hsiomBase;
27     uint32_t gpioBase;
28 
29     /* IP block versions: [7:4] major, [3:0] minor */
30     uint8_t  dwVersion;
31 
32     /* Parameters */
33     uint8_t  cpussDw0ChNr;
34     uint8_t  cpussDw1ChNr;
35     uint8_t  epMonitorNr;
36 
37     /* Peripheral register offsets */
38 
39    /* DW registers */
40     uint16_t dwChOffset;
41     uint16_t dwChSize;
42     uint8_t  dwChCtlPrioPos;
43     uint8_t  dwChCtlPreemptablePos;
44     uint8_t  dwStatusChIdxPos;
45     uint32_t dwStatusChIdxMsk;
46 
47     uint8_t  tcpwmCC1Present;
48     uint8_t  tcpwmAMCPresent;
49     uint8_t  tcpwmSMCPrecent;
50 
51 } cy_stc_device_t;
52 
53 void Cy_PDL_Init(const cy_stc_device_t * device);
54 
55 /* Pointer to device configuration structure */
56 #define CY_DEVICE_CFG                   (&cy_deviceIpBlockCfg)
57 
58 /*******************************************************************************
59 *                   Global Variables
60 *******************************************************************************/
61 
62 extern const cy_stc_device_t   cy_deviceIpBlockCfg;
63 extern const cy_stc_device_t* cy_device;
64 
65 /*******************************************************************************
66 *                   Global Extern Functions
67 *******************************************************************************/
68 
69 #if defined(__ARMCC_VERSION)
70 #define interrupt_type __attribute__((interrupt))
71 #elif defined (__GNUC__)
72 #define interrupt_type __attribute__((interrupt))
73 #elif defined (__ICCARM__)
74 #define interrupt_type __irq
75 #else
76     #error "An unsupported toolchain"
77 #endif  /* (__ARMCC_VERSION) */
78 
79 /*******************************************************************************
80 *               Macro Definitions
81 *******************************************************************************/
82 /*******************************************************************************
83 *               Register Access Helper Macros
84 *******************************************************************************/
85 #define CY_DEVICE_CAT1C            /* Device Category */
86 #define CY_CRYPTO_V1                        (0U) /* CAT1C devices have only mxcrypto_v2 IP */
87 
88 /*******************************************************************************
89 *                System Level
90 *******************************************************************************/
91 #define ENABLE_CM7_INSTRUCTION_CACHE
92 //#define ENABLE_CM7_DATA_CACHE
93 
94 /*******************************************************************************
95 *               Generic Macro Definitions
96 *******************************************************************************/
97 #define GET_ALIAS_ADDRESS(addr)             (uint32_t)(addr)
98 
99 /*******************************************************************************
100 *                CRYPTO
101 *******************************************************************************/
102 
103 /* The CRYPTO internal-memory buffer-size in 32-bit words. */
104 #define CY_CRYPTO_MEM_BUFF_SIZE_U32         (2048U)
105 
106 /*******************************************************************************
107 *                SYSLIB
108 *******************************************************************************/
109 #if defined(CORE_NAME_CM7_0) || defined(CORE_NAME_CM7_1)
110 #define CY_SYSLIB_DELAY_CALIBRATION_FACTOR    2U
111 #else
112 #define CY_SYSLIB_DELAY_CALIBRATION_FACTOR    1U
113 #endif
114 
115 /*******************************************************************************
116 *                SRSS
117 *******************************************************************************/
118 
119 #define CY_SRSS_NUM_CLKPATH                 SRSS_NUM_CLKPATH
120 #define CY_SRSS_NUM_PLL                     SRSS_NUM_TOTAL_PLL
121 #define CY_SRSS_NUM_PLL200M                 SRSS_NUM_PLL
122 #define CY_SRSS_NUM_PLL400M                 SRSS_NUM_PLL400M
123 #define CY_SRSS_NUM_HFROOT                  SRSS_NUM_HFROOT
124 #define CY_SRSS_ECO_PRESENT                 SRSS_ECO_PRESENT
125 #define CY_SRSS_FLL_PRESENT                 1
126 #define CY_SRSS_PLL_PRESENT                 SRSS_NUM_PLL
127 #define CY_SRSS_PLL400M_PRESENT             1
128 #define CY_SRSS_ALTHF_PRESENT               SRSS_ALTHF_PRESENT
129 #define CY_SRSS_DPLL_LP_PRESENT             0
130 #define CY_SRSS_IMO_PRESENT                 1
131 
132 #define CY_SRSS_ILO_COUNT                   2
133 
134 /** HF PATH # used for PERI PCLK */
135 #define CY_SYSCLK_CLK_PERI_HF_PATH_NUM     2U
136 
137 /** HF PATH # used for MEM CLK */
138 #define CY_SYSCLK_CLK_MEM_HF_PATH_NUM     0U
139 
140 
141 /** HF PATH # used for Core */
142 #ifdef CORE_NAME_CM0P_0
143 #define CY_SYSCLK_CLK_CORE_HF_PATH_NUM     0U
144 #else
145 #define CY_SYSCLK_CLK_CORE_HF_PATH_NUM     1U
146 #endif
147 
148 /** HF PATH # used for CLOCK FAST */
149 #define CY_SYSCLK_CLK_FAST_HF_NUM          1U
150 
151 /* HF PATH # Max Allowed Frequencies */
152 #define CY_SYSCLK_HF_MAX_FREQ(hfNum)       (350000000U)
153 
154 /** FLL Max Frequency */
155 #define  CY_SYSCLK_FLL_MAX_OUTPUT_FREQ     (100000000UL)
156 
157 /* Technology Independant Register set */
158 #define SRSS_CLK_DSI_SELECT                 (((SRSS_Type *) SRSS)->CLK_DSI_SELECT)
159 #define SRSS_CLK_OUTPUT_FAST                (((SRSS_Type *) SRSS)->CLK_OUTPUT_FAST)
160 #define SRSS_CLK_OUTPUT_SLOW                (((SRSS_Type *) SRSS)->CLK_OUTPUT_SLOW)
161 #define SRSS_CLK_CAL_CNT1                   (((SRSS_Type *) SRSS)->CLK_CAL_CNT1)
162 #define SRSS_CLK_CAL_CNT2                   (((SRSS_Type *) SRSS)->CLK_CAL_CNT2)
163 #define SRSS_SRSS_INTR                      (((SRSS_Type *) SRSS)->SRSS_INTR)
164 #define SRSS_SRSS_INTR_SET                  (((SRSS_Type *) SRSS)->SRSS_INTR_SET)
165 #define SRSS_SRSS_INTR_MASK                 (((SRSS_Type *) SRSS)->SRSS_INTR_MASK)
166 #define SRSS_SRSS_INTR_MASKED               (((SRSS_Type *) SRSS)->SRSS_INTR_MASKED)
167 #define SRSS_PWR_CTL                        (((SRSS_Type *) SRSS)->PWR_CTL)
168 #define SRSS_PWR_CTL2                       (((SRSS_Type *) SRSS)->PWR_CTL2)
169 #define SRSS_PWR_HIBERNATE                  (((SRSS_Type *) SRSS)->PWR_HIBERNATE)
170 #define SRSS_PWR_BUCK_CTL                   (((SRSS_Type *) SRSS)->PWR_BUCK_CTL)
171 #define SRSS_PWR_BUCK_CTL2                  (((SRSS_Type *) SRSS)->PWR_BUCK_CTL2)
172 #define SRSS_PWR_SSV_CTL                    (((SRSS_Type *) SRSS)->PWR_SSV_CTL)
173 #define SRSS_PWR_SSV_STATUS                 (((SRSS_Type *) SRSS)->PWR_SSV_STATUS)
174 #define SRSS_PWR_LVD_CTL                    (((SRSS_Type *) SRSS)->PWR_LVD_CTL)
175 #define SRSS_PWR_LVD_CTL2                   (((SRSS_Type *) SRSS)->PWR_LVD_CTL2)
176 #define SRSS_PWR_REGHC_CTL                  (((SRSS_Type *) SRSS)->PWR_REGHC_CTL)
177 #define SRSS_PWR_REGHC_STATUS               (((SRSS_Type *) SRSS)->PWR_REGHC_STATUS)
178 #define SRSS_PWR_REGHC_CTL2                 (((SRSS_Type *) SRSS)->PWR_REGHC_CTL2)
179 #define SRSS_PWR_REGHC_CTL4                 (((SRSS_Type *) SRSS)->PWR_REGHC_CTL4)
180 #define SRSS_PWR_HIB_DATA                   (((SRSS_Type *) SRSS)->PWR_HIB_DATA)
181 #define SRSS_PWR_PMIC_CTL                   (((SRSS_Type *) SRSS)->PWR_PMIC_CTL)
182 #define SRSS_PWR_PMIC_STATUS                (((SRSS_Type *) SRSS)->PWR_PMIC_STATUS)
183 #define SRSS_PWR_PMIC_CTL2                  (((SRSS_Type *) SRSS)->PWR_PMIC_CTL2)
184 #define SRSS_PWR_PMIC_CTL4                  (((SRSS_Type *) SRSS)->PWR_PMIC_CTL4)
185 #define SRSS_CLK_PATH_SELECT                (((SRSS_Type *) SRSS)->CLK_PATH_SELECT)
186 #define SRSS_CLK_ROOT_SELECT                (((SRSS_Type *) SRSS)->CLK_ROOT_SELECT)
187 #define SRSS_CLK_DIRECT_SELECT              (((SRSS_Type *) SRSS)->CLK_DIRECT_SELECT)
188 #define SRSS_CLK_ECO_STATUS                 (((SRSS_Type *) SRSS)->CLK_ECO_STATUS)
189 #define SRSS_CLK_ILO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG) /* BWC */
190 #define SRSS_CLK_ILO0_CONFIG                (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG)
191 #define SRSS_CLK_ILO1_CONFIG                (((SRSS_Type *) SRSS)->CLK_ILO1_CONFIG)
192 
193 #define SRSS_CLK_ILO_CONFIG_ENABLE_Msk      SRSS_CLK_ILO0_CONFIG_ENABLE_Msk /* BWC */
194 
195 #define SRSS_CLK_TRIM_ILO_CTL               (((SRSS_Type *) SRSS)->CLK_TRIM_ILO_CTL)
196 #define SRSS_CLK_PILO_CONFIG                (((SRSS_Type *) SRSS)->CLK_PILO_CONFIG)
197 #define SRSS_CLK_ECO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG)
198 #define SRSS_CLK_ECO_CONFIG2                 (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG2)
199 #define SRSS_CLK_MFO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_MFO_CONFIG)
200 #define SRSS_CLK_IHO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_IHO_CONFIG)
201 #define SRSS_CLK_ALTHF_CTL                  (((SRSS_Type *) SRSS)->CLK_ALTHF_CTL)
202 
203 #define SRSS_CLK_ILO0_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ILO0_CONFIG)
204 #define SRSS_CLK_ILO1_CONFIG                 (((SRSS_Type *) SRSS)->CLK_ILO1_CONFIG)
205 
206 #define SRSS_CSV_HF                         (((SRSS_Type *) SRSS)->CSV_HF)
207 #define SRSS_CLK_SELECT                     (((SRSS_Type *) SRSS)->CLK_SELECT)
208 #define SRSS_CLK_TIMER_CTL                  (((SRSS_Type *) SRSS)->CLK_TIMER_CTL)
209 #define SRSS_CLK_IMO_CONFIG                 (((SRSS_Type *) SRSS)->CLK_IMO_CONFIG)
210 #define SRSS_CLK_ECO_PRESCALE               (((SRSS_Type *) SRSS)->CLK_ECO_PRESCALE)
211 #define SRSS_CLK_MF_SELECT                  (((SRSS_Type *) SRSS)->CLK_MF_SELECT)
212 #define SRSS_CSV_REF_SEL                    (((SRSS_Type *) SRSS)->CSV_REF_SEL)
213 #define SRSS_CSV_REF                        (((SRSS_Type *) SRSS)->CSV_REF)
214 #define SRSS_CSV_LF                         (((SRSS_Type *) SRSS)->CSV_LF)
215 #define SRSS_CSV_ILO                        (((SRSS_Type *) SRSS)->CSV_ILO)
216 #define SRSS_RES_CAUSE                      (((SRSS_Type *) SRSS)->RES_CAUSE)
217 #define SRSS_RES_CAUSE2                     (((SRSS_Type *) SRSS)->RES_CAUSE2)
218 #define SRSS_RES_CAUSE_EXTEND               (((SRSS_Type *) SRSS)->RES_CAUSE_EXTEND)
219 #define SRSS_CLK_LP_PLL                     (((SRSS_Type *) SRSS)->CLK_LP_PLL)
220 #define SRSS_CLK_IHO                        (((SRSS_Type *) SRSS)->CLK_IHO)
221 #define SRSS_TST_XRES_SECURE                (((SRSS_Type *) SRSS)->TST_XRES_SECURE)
222 #define SRSS_RES_PXRES_CTL                  (((SRSS_Type *) SRSS)->RES_PXRES_CTL)
223 
224 #define SRSS_CLK_FLL_CONFIG                 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG)
225 #define SRSS_CLK_FLL_CONFIG2                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG2)
226 #define SRSS_CLK_FLL_CONFIG3                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3)
227 #define SRSS_CLK_FLL_CONFIG4                (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG4)
228 #define SRSS_CLK_FLL_STATUS                 (((SRSS_Type *) SRSS)->CLK_FLL_STATUS)
229 
230 #define SRSS_PWR_LVD_STATUS                 (((SRSS_Type *) SRSS)->PWR_LVD_STATUS)
231 #define SRSS_PWR_LVD_STATUS2                 (((SRSS_Type *) SRSS)->PWR_LVD_STATUS2)
232 
233 #define SRSS_SRSS_INTR_CFG                  (((SRSS_Type *) SRSS)->SRSS_AINTR_CFG)
234 
235 #define SRSS_PWR_HIB_WAKE_CTL               (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL)
236 #define SRSS_PWR_HIB_WAKE_CTL2              (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL2)
237 #define SRSS_PWR_HIB_WAKE_CAUSE             (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CAUSE)
238 #define SRSS_RES_SOFT_CTL                   (((SRSS_Type *) SRSS)->RES_SOFT_CTL)
239 
240 #define SRSS_CLK_PLL_CONFIG                 (((SRSS_Type *) SRSS)->CLK_PLL_CONFIG)
241 #define SRSS_CLK_PLL_STATUS                 (((SRSS_Type *) SRSS)->CLK_PLL_STATUS)
242 
243 #define SRSS_FLL_PATH_NUM         (0UL)
244 #define SRSS_PLL_400M_0_PATH_NUM  (1UL)
245 #define SRSS_PLL_400M_1_PATH_NUM  (2UL)
246 #define SRSS_PLL_200M_0_PATH_NUM  (3UL)
247 #define SRSS_PLL_200M_1_PATH_NUM  (4UL)
248 
249 #define SRSS_PLL400M_FRAC_BIT_COUNT (24ULL)
250 
251 #if (CY_IP_MXS40SRSS_VERSION >= 3)
252 #define SRSS_CLK_PLL_400M_CONFIG(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG)
253 #define SRSS_CLK_PLL_400M_CONFIG2(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG2)
254 #define SRSS_CLK_PLL_400M_CONFIG3(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG3)
255 #define SRSS_CLK_PLL_400M_STATUS(pllNum)                 (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].STATUS)
256 #endif
257 
258 
259 #define SRSS_WDT_CTL                        (((WDT_Type*) &SRSS->WDT_STRUCT)->CTL)
260 #define SRSS_WDT_LOWER_LIMIT                (((WDT_Type*) &SRSS->WDT_STRUCT)->LOWER_LIMIT)
261 #define SRSS_WDT_UPPER_LIMIT                (((WDT_Type*) &SRSS->WDT_STRUCT)->UPPER_LIMIT)
262 #define SRSS_WDT_WARN_LIMIT                 (((WDT_Type*) &SRSS->WDT_STRUCT)->WARN_LIMIT)
263 #define SRSS_WDT_CONFIG                     (((WDT_Type*) &SRSS->WDT_STRUCT)->CONFIG)
264 #define SRSS_WDT_CNT                        (((WDT_Type*) &SRSS->WDT_STRUCT)->CNT)
265 #define SRSS_WDT_LOCK                       (((WDT_Type*) &SRSS->WDT_STRUCT)->LOCK)
266 #define SRSS_WDT_SERVICE                    (((WDT_Type*) &SRSS->WDT_STRUCT)->SERVICE)
267 #define SRSS_WDT_INTR                       (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR)
268 #define SRSS_WDT_INTR_SET                   (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_SET)
269 #define SRSS_WDT_INTR_MASK                  (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_MASK)
270 #define SRSS_WDT_INTR_MASKED                (((WDT_Type*) &SRSS->WDT_STRUCT)->INTR_MASKED)
271 
272 
273 
274 #define SRSS_TST_DDFT_FAST_CTL_REG          (*(volatile uint32_t *) 0x40261104U)
275 #define SRSS_TST_DDFT_SLOW_CTL_REG          (*(volatile uint32_t *) 0x40261108U)
276 
277 #define SRSS_TST_DDFT_SLOW_CTL_MASK         (0x00001F1EU)
278 #define SRSS_TST_DDFT_FAST_CTL_MASK         (62U)
279 
280 
281 /*******************************************************************************
282 *                BACKUP
283 *******************************************************************************/
284 
285 #define BACKUP_PMIC_CTL                     (((BACKUP_Type *) BACKUP)->PMIC_CTL)
286 #define BACKUP_CTL                          (((BACKUP_Type *) BACKUP)->CTL)
287 #define BACKUP_RTC_TIME                     (((BACKUP_Type *) BACKUP)->RTC_TIME)
288 #define BACKUP_RTC_DATE                     (((BACKUP_Type *) BACKUP)->RTC_DATE)
289 #define BACKUP_RTC_RW                       (((BACKUP_Type *) BACKUP)->RTC_RW)
290 #define BACKUP_CAL_CTL                      (((BACKUP_Type *) BACKUP)->CAL_CTL)
291 #define BACKUP_ALM1_TIME                    (((BACKUP_Type *) BACKUP)->ALM1_TIME)
292 #define BACKUP_ALM1_DATE                    (((BACKUP_Type *) BACKUP)->ALM1_DATE)
293 #define BACKUP_ALM2_TIME                    (((BACKUP_Type *) BACKUP)->ALM2_TIME)
294 #define BACKUP_ALM2_DATE                    (((BACKUP_Type *) BACKUP)->ALM2_DATE)
295 #define BACKUP_STATUS                       (((BACKUP_Type *) BACKUP)->STATUS)
296 #define BACKUP_INTR                         (((BACKUP_Type *) BACKUP)->INTR)
297 #define BACKUP_INTR_SET                     (((BACKUP_Type *) BACKUP)->INTR_SET)
298 #define BACKUP_INTR_MASK                    (((BACKUP_Type *) BACKUP)->INTR_MASK)
299 #define BACKUP_INTR_MASKED                  (((BACKUP_Type *) BACKUP)->INTR_MASKED)
300 #define BACKUP_RESET                        (((BACKUP_Type *) BACKUP)->RESET)
301 #define BACKUP_BREG                         (((BACKUP_Type *) BACKUP)->BREG)
302 
303 
304 #define CY_SRSS_BACKUP_NUM_BREG             SRSS_BACKUP_NUM_BREG
305 
306 
307 /*******************************************************************************
308 *                CANFD
309 *******************************************************************************/
310 
311 #define CANFD_CTL(base)                           (((CANFD_Type *)(base))->CTL)
312 #define CANFD_STATUS(base)                        (((CANFD_Type *)(base))->STATUS)
313 #define CANFD_NBTP(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NBTP)
314 #define CANFD_IR(base, chan)                      (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IR)
315 #define CANFD_IE(base, chan)                      (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IE)
316 #define CANFD_ILS(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILS)
317 #define CANFD_ILE(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILE)
318 #define CANFD_CCCR(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CCCR)
319 #define CANFD_SIDFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.SIDFC)
320 #define CANFD_XIDFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDFC)
321 #define CANFD_XIDAM(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDAM)
322 #define CANFD_RXESC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXESC)
323 #define CANFD_RXF0C(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0C)
324 #define CANFD_RXF1C(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1C)
325 #define CANFD_RXFTOP_CTL(base, chan)              (((CANFD_Type *)(base))->CH[chan].RXFTOP_CTL)
326 #define CANFD_RXBC(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXBC)
327 #define CANFD_TXESC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXESC)
328 #define CANFD_TXEFC(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXEFC)
329 #define CANFD_TXBC(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBC)
330 #define CANFD_DBTP(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.DBTP)
331 #define CANFD_TDCR(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TDCR)
332 #define CANFD_GFC(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.GFC)
333 #define CANFD_TXBRP(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBRP)
334 #define CANFD_TXBAR(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBAR)
335 #define CANFD_TXBCR(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCR)
336 #define CANFD_TXBTO(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTO)
337 #define CANFD_TXBCF(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCF)
338 #define CANFD_TXBTIE(base, chan)                  (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTIE)
339 #define CANFD_TXBCIE(base, chan)                  (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCIE)
340 #define CANFD_NDAT1(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT1)
341 #define CANFD_NDAT2(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT2)
342 #define CANFD_RXF0S(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0S)
343 #define CANFD_RXFTOP0_DATA(base, chan)            (((CANFD_Type *)(base))->CH[chan].RXFTOP0_DATA)
344 #define CANFD_RXFTOP1_DATA(base, chan)            (((CANFD_Type *)(base))->CH[chan].RXFTOP1_DATA)
345 #define CANFD_RXF0A(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0A)
346 #define CANFD_RXF1S(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1S)
347 #define CANFD_RXF1A(base, chan)                   (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1A)
348 #define CANFD_PSR(base, chan)                     (((CANFD_Type *)(base))->CH[chan].M_TTCAN.PSR)
349 #define CANFD_TEST(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TEST)
350 #define CANFD_CREL(base, chan)                    (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CREL)
351 
352 #define CY_CANFD_CHANNELS_NUM                     (0x1UL)
353 
354 
355 /*******************************************************************************
356 *                FLASHC
357 *******************************************************************************/
358 #if ((CPUSS_FLASHC_PRESENT == 1) && (CPUSS_FLASHC_ECT == 1))
359 #define CY_IP_MXFLASHC_VERSION_ECT
360 #endif
361 
362 #define FLASHC_FLASH_CTL             (((FLASHC_Type *)(FLASHC))->FLASH_CTL)
363 #define FLASHC_FLASH_PWR_CTL         (((FLASHC_Type *)(FLASHC))->FLASH_PWR_CTL)
364 #define FLASHC_FLASH_CMD             (((FLASHC_Type *)(FLASHC))->FLASH_CMD)
365 #define FLASHC_ECC_CTL               (((FLASHC_Type *)(FLASHC))->ECC_CTL)
366 #define FLASHC_FM_SRAM_ECC_CTL0      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL0)
367 #define FLASHC_FM_SRAM_ECC_CTL1      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL1)
368 #define FLASHC_FM_SRAM_ECC_CTL2      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL2)
369 #define FLASHC_FM_SRAM_ECC_CTL3      (((FLASHC_Type *)(FLASHC))->FM_SRAM_ECC_CTL3)
370 #define FLASHC_CM0_CA_CTL0           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL0)
371 #define FLASHC_CM0_CA_CTL1           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL1)
372 #define FLASHC_CM0_CA_CTL2           (((FLASHC_Type *)(FLASHC))->CM0_CA_CTL2)
373 #define FLASHC_CM0_CA_STATUS0        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS0)
374 #define FLASHC_CM0_CA_STATUS1        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS1)
375 #define FLASHC_CM0_CA_STATUS2        (((FLASHC_Type *)(FLASHC))->CM0_CA_STATUS2)
376 #define FLASHC_CM0_STATUS            (((FLASHC_Type *)(FLASHC))->CM0_STATUS)
377 #define FLASHC_CM7_0_STATUS          (((FLASHC_Type *)(FLASHC))->CM7_0_STATUS)
378 #define FLASHC_CM7_1_STATUS          (((FLASHC_Type *)(FLASHC))->CM7_1_STATUS)
379 #define FLASHC_CRYPTO_BUFF_CTL       (((FLASHC_Type *)(FLASHC))->CRYPTO_BUFF_CTL)
380 #define FLASHC_DW0_BUFF_CTL          (((FLASHC_Type *)(FLASHC))->DW0_BUFF_CTL)
381 #define FLASHC_DW1_BUFF_CTL          (((FLASHC_Type *)(FLASHC))->DW1_BUFF_CTL)
382 #define FLASHC_DMAC_BUFF_CTL         (((FLASHC_Type *)(FLASHC))->DMAC_BUFF_CTL)
383 #define FLASHC_SLOW0_MS_BUFF_CTL     (((FLASHC_Type *)(FLASHC))->SLOW0_MS_BUFF_CTL)
384 #define FLASHC_SLOW1_MS_BUFF_CTL     (((FLASHC_Type *)(FLASHC))->SLOW1_MS_BUFF_CTL)
385 
386 /* FLASH Memory  */
387 #define FLASHC_FM_CTL_ECT_WORK_FLASH_SAFETY (((FLASHC_FM_CTL_ECT_Type *)(FLASHC_FM_CTL_ECT))->WORK_FLASH_SAFETY)
388 #define FLASHC_FM_CTL_ECT_MAIN_FLASH_SAFETY (((FLASHC_FM_CTL_ECT_Type *)(FLASHC_FM_CTL_ECT))->MAIN_FLASH_SAFETY)
389 #define FLASHC_FM_CTL_ECT_FLASH_STATUS (((FLASHC_FM_CTL_ECT_Type *)(FLASHC_FM_CTL_ECT))->STATUS)
390 
391 /*******************************************************************************
392 *                SFLASH
393 *******************************************************************************/
394 
395 #define SFLASH_DIE_YEAR                     (((SFLASH_V1_Type *) SFLASH)->DIE_YEAR)
396 #define SFLASH_DIE_MINOR                    (((SFLASH_V1_Type *) SFLASH)->DIE_MINOR)
397 #define SFLASH_DIE_SORT                     (((SFLASH_V1_Type *) SFLASH)->DIE_SORT)
398 #define SFLASH_DIE_Y                        (((SFLASH_V1_Type *) SFLASH)->DIE_Y)
399 #define SFLASH_DIE_X                        (((SFLASH_V1_Type *) SFLASH)->DIE_X)
400 #define SFLASH_DIE_WAFER                    (((SFLASH_V1_Type *) SFLASH)->DIE_WAFER)
401 #define SFLASH_DIE_LOT(val)                 (((SFLASH_V1_Type *) SFLASH)->DIE_LOT[(val)])
402 #define SFLASH_FAMILY_ID                    (((SFLASH_V1_Type *) SFLASH)->FAMILY_ID)
403 #define SFLASH_SI_REVISION_ID               (((SFLASH_V1_Type *) SFLASH)->SI_REVISION_ID)
404 #define SFLASH_PWR_TRIM_WAKE_CTL            (((SFLASH_V1_Type *) SFLASH)->PWR_TRIM_WAKE_CTL)
405 #define SFLASH_LDO_0P9V_TRIM                (((SFLASH_V1_Type *) SFLASH)->LDO_0P9V_TRIM)
406 #define SFLASH_LDO_1P1V_TRIM                (((SFLASH_V1_Type *) SFLASH)->LDO_1P1V_TRIM)
407 #define SFLASH_BLE_DEVICE_ADDRESS           (((SFLASH_V1_Type *) SFLASH)->BLE_DEVICE_ADDRESS)
408 #define SFLASH_SILICON_ID                   (((SFLASH_V1_Type *) SFLASH)->SILICON_ID)
409 #define SFLASH_SINGLE_CORE                  (*(volatile uint8_t *) (SFLASH_BASE + 0xBU))
410 
411 
412 #define SFLASH_CPUSS_TRIM_ROM_CTL_LP        (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_LP)
413 #define SFLASH_CPUSS_TRIM_RAM_CTL_LP        (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_LP)
414 #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP       (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_ULP)
415 #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP       (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_ULP)
416 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP   (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP)
417 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP   (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_LP)
418 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP  (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_ULP)
419 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP  (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP)
420 
421 
422 #define SFLASH_CSD0_ADC_VREF0_TRIM          (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF0)
423 #define SFLASH_CSD0_ADC_VREF1_TRIM          (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF1)
424 #define SFLASH_CSD0_ADC_VREF2_TRIM          (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF2)
425 
426 
427 /*******************************************************************************
428 *                CPUSS
429 *******************************************************************************/
430 
431 /* ARM core registers */
432 #define SYSTICK_CTRL                        (((SysTick_Type *)SysTick)->CTRL)
433 #define SYSTICK_LOAD                        (((SysTick_Type *)SysTick)->LOAD)
434 #define SYSTICK_VAL                         (((SysTick_Type *)SysTick)->VAL)
435 #define SCB_SCR                             (((SCB_Type *)SCB)->SCR)
436 
437 #define CPUSS_SYSTICK_CTL                (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_CTL)
438 
439 #define UDB_UDBIF_BANK_CTL                  (((UDB_V1_Type *) cy_device->udbBase)->UDBIF.BANK_CTL)
440 #define UDB_BCTL_MDCLK_EN                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MDCLK_EN)
441 #define UDB_BCTL_MBCLK_EN                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MBCLK_EN)
442 #define UDB_BCTL_BOTSEL_L                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_L)
443 #define UDB_BCTL_BOTSEL_U                   (((UDB_V1_Type *) cy_device->udbBase)->BCTL.BOTSEL_U)
444 #define UDB_BCTL_QCLK_EN_0                  (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[0U])
445 #define UDB_BCTL_QCLK_EN_1                  (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[1U])
446 #define UDB_BCTL_QCLK_EN_2                  (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[2U])
447 
448 #define CPUSS_FAST_0_CLOCK_CTL              (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL)
449 #define CPUSS_FAST_1_CLOCK_CTL              (((CPUSS_Type*) CPUSS_BASE)->FAST_1_CLOCK_CTL)
450 #define CPUSS_SLOW_CLOCK_CTL                (((CPUSS_Type*) CPUSS_BASE)->SLOW_CLOCK_CTL)
451 #define CPUSS_MEM_CLOCK_CTL                (((CPUSS_Type*) CPUSS_BASE)->MEM_CLOCK_CTL)
452 #define CPUSS_PERI_CLOCK_CTL                (((CPUSS_Type*) CPUSS_BASE)->PERI_CLOCK_CTL)
453 
454 #define CPUSS_CM0_NMI_CTL(nmi)               (((volatile uint32_t *) (CPUSS->CM0_NMI_CTL))[(nmi)])
455 #define CPUSS_CM7_0_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_0_NMI_CTL))[(nmi)])
456 #define CPUSS_CM7_1_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_1_NMI_CTL))[(nmi)])
457 
458 
459 #define CY_CPUSS_NOT_CONNECTED_IRQN          ((uint32_t)disconnected_IRQn)
460 #define CY_CPUSS_DISCONNECTED_IRQN           ((cy_en_intr_t)CY_CPUSS_NOT_CONNECTED_IRQN)
461 
462 #define CPUSS_CM0_INT_STATUS_BASE            ((volatile const uint32_t *) &(((CPUSS_Type *)(CPUSS))->CM0_INT0_STATUS))
463 #define CY_IS_CM0_CORE   ((_FLD2VAL(CPUSS_IDENTITY_MS, CPUSS_IDENTITY) == ((uint32_t)(CPUSS_MS_ID_CM0))) ? true : false)
464 #define CY_IS_CM7_CORE_0 ((_FLD2VAL(CPUSS_IDENTITY_MS, CPUSS_IDENTITY) == ((uint32_t)(CPUSS_MS_ID_CM7_0))) ? true : false)
465 #define CY_IS_CM7_CORE_1 ((_FLD2VAL(CPUSS_IDENTITY_MS, CPUSS_IDENTITY) == ((uint32_t)(CPUSS_MS_ID_CM7_1))) ? true : false)
466 
467 #define CPUSS_IDENTITY                       ((((CPUSS_Type *)(CPUSS_BASE))->IDENTITY))
468 #define CPUSS_CM7_0_STATUS                   ((((CPUSS_Type *)(CPUSS_BASE))->CM7_0_STATUS))
469 #define CPUSS_FAST_0_CLOCK_CTL               (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL)
470 #define CPUSS_CM7_0_CTL                      (((CPUSS_Type*) CPUSS_BASE)->CM7_0_CTL)
471 #define CPUSS_CM7_0_INT_STATUS               (((CPUSS_Type*) CPUSS_BASE)->CM7_0_INT_STATUS)
472 #define CPUSS_CM7_0_VECTOR_TABLE_BASE        (((CPUSS_Type*) CPUSS_BASE)->CM7_0_VECTOR_TABLE_BASE)
473 #define CPUSS_CM7_0_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_0_NMI_CTL))[(nmi)])
474 #define CPUSS_CM7_1_STATUS                   ((((CPUSS_Type *)(CPUSS_BASE))->CM7_1_STATUS))
475 #define CPUSS_FAST_1_CLOCK_CTL               (((CPUSS_Type*) CPUSS_BASE)->FAST_1_CLOCK_CTL)
476 #define CPUSS_CM7_1_CTL                      (((CPUSS_Type*) CPUSS_BASE)->CM7_1_CTL)
477 #define CPUSS_CM7_1_INT_STATUS               ((((CPUSS_Type *)(CPUSS_BASE))->CM7_1_INT_STATUS))
478 #define CPUSS_CM7_1_VECTOR_TABLE_BASE        (((CPUSS_Type*) CPUSS_BASE)->CM7_1_VECTOR_TABLE_BASE)
479 #define CPUSS_CM7_1_NMI_CTL(nmi)             (((volatile uint32_t *) (CPUSS->CM7_1_NMI_CTL))[(nmi)])
480 #define CPUSS_CM0_CTL                        (((CPUSS_Type*) CPUSS_BASE)->CM0_CTL)
481 #define CPUSS_CM0_STATUS                     (((CPUSS_Type*) CPUSS_BASE)->CM0_STATUS)
482 #define CPUSS_SLOW_CLOCK_CTL                 (((CPUSS_Type*) CPUSS_BASE)->SLOW_CLOCK_CTL)
483 #define CPUSS_PERI_CLOCK_CTL                 (((CPUSS_Type*) CPUSS_BASE)->PERI_CLOCK_CTL)
484 #define CPUSS_MEM_CLOCK_CTL                  (((CPUSS_Type*) CPUSS_BASE)->MEM_CLOCK_CTL)
485 #define CPUSS_CM0_INT0_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT0_STATUS))
486 #define CPUSS_CM0_INT1_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT1_STATUS))
487 #define CPUSS_CM0_INT2_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT2_STATUS))
488 #define CPUSS_CM0_INT3_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT3_STATUS))
489 #define CPUSS_CM0_INT4_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT4_STATUS))
490 #define CPUSS_CM0_INT5_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT5_STATUS))
491 #define CPUSS_CM0_INT6_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT6_STATUS))
492 #define CPUSS_CM0_INT7_STATUS                ((((CPUSS_Type *)(CPUSS_BASE))->CM0_INT7_STATUS))
493 #define CPUSS_CM0_NMI_CTL(nmi)               (((volatile uint32_t *) (CPUSS->CM0_NMI_CTL))[(nmi)])
494 #define CPUSS_CM0_VECTOR_TABLE_BASE          ((((CPUSS_Type *)(CPUSS_BASE))->CM0_VECTOR_TABLE_BASE))
495 #define CPUSS_CM7_0_PWR_CTL                  ((((CPUSS_Type *)(CPUSS_BASE))->CM7_0_PWR_CTL))
496 #define CPUSS_CM7_1_PWR_DELAY_CTL            ((((CPUSS_Type *)(CPUSS_BASE))->CM7_1_PWR_DELAY_CTL))
497 #define CPUSS_RAM0_CTL0                      ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_CTL0))
498 #define CPUSS_RAM0_STATUS                    ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_STATUS))
499 #define CPUSS_RAM0_PWR_MACRO_CTL(macroIdx)   ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_PWR_MACRO_CTL[(macroIdx)]))
500 #define CPUSS_RAM1_CTL0                      ((((CPUSS_Type *)(CPUSS_BASE))->RAM1_STATUS))
501 #define CPUSS_RAM1_STATUS                    ((((CPUSS_Type *)(CPUSS_BASE))->RAM0_CTL0))
502 #define CPUSS_RAM1_PWR_CTL                   ((((CPUSS_Type *)(CPUSS_BASE))->RAM1_PWR_CTL))
503 #define CPUSS_RAM2_CTL0                      ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_CTL0))
504 #define CPUSS_RAM2_STATUS                    ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_STATUS))
505 #define CPUSS_RAM2_PWR_CTL                   ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_PWR_CTL))
506 #define CPUSS_RAM_PWR_DELAY_CTL              ((((CPUSS_Type *)(CPUSS_BASE))->RAM_PWR_DELAY_CTL))
507 #define CPUSS_ROM_CTL                        ((((CPUSS_Type *)(CPUSS_BASE))->ROM_CTL))
508 #define CPUSS_ECC_CTL                        ((((CPUSS_Type *)(CPUSS_BASE))->ECC_CTL))
509 #define CPUSS_PRODUCT_ID                     ((((CPUSS_Type*) CPUSS_BASE)->PRODUCT_ID))
510 #define CPUSS_CM0_SYSTEM_INT_CTL             (((CPUSS_Type *)(CPUSS_BASE))->CM0_SYSTEM_INT_CTL)
511 #define CPUSS_CM7_0_SYSTEM_INT_CTL           (((CPUSS_Type *)(CPUSS_BASE))->CM7_0_SYSTEM_INT_CTL)
512 #define CPUSS_CM7_1_SYSTEM_INT_CTL           (((CPUSS_Type *)(CPUSS_BASE))->CM7_1_SYSTEM_INT_CTL)
513 
514 #define CPUSS_SRAM_COUNT                    (1u + CPUSS_RAMC1_PRESENT + CPUSS_RAMC2_PRESENT)
515 
516 
517 /*******************************************************************************
518 *                LPCOMP
519 *******************************************************************************/
520 
521 #define LPCOMP_CMP0_CTRL(base)              (((LPCOMP_V1_Type *)(base))->CMP0_CTRL)
522 #define LPCOMP_CMP1_CTRL(base)              (((LPCOMP_V1_Type *)(base))->CMP1_CTRL)
523 #define LPCOMP_CMP0_SW_CLEAR(base)          (((LPCOMP_V1_Type *)(base))->CMP0_SW_CLEAR)
524 #define LPCOMP_CMP1_SW_CLEAR(base)          (((LPCOMP_V1_Type *)(base))->CMP1_SW_CLEAR)
525 #define LPCOMP_CMP0_SW(base)                (((LPCOMP_V1_Type *)(base))->CMP0_SW)
526 #define LPCOMP_CMP1_SW(base)                (((LPCOMP_V1_Type *)(base))->CMP1_SW)
527 #define LPCOMP_STATUS(base)                 (((LPCOMP_V1_Type *)(base))->STATUS)
528 #define LPCOMP_CONFIG(base)                 (((LPCOMP_V1_Type *)(base))->CONFIG)
529 #define LPCOMP_INTR(base)                   (((LPCOMP_V1_Type *)(base))->INTR)
530 #define LPCOMP_INTR_SET(base)               (((LPCOMP_V1_Type *)(base))->INTR_SET)
531 #define LPCOMP_INTR_MASK(base)              (((LPCOMP_V1_Type *)(base))->INTR_MASK)
532 #define LPCOMP_INTR_MASKED(base)            (((LPCOMP_V1_Type *)(base))->INTR_MASKED)
533 
534 
535 /*******************************************************************************
536 *                MCWDT
537 *******************************************************************************/
538 #define MCWDT_CTR_CTL(base, counter)            (((MCWDT_Type *)(base))->CTR[counter].CTL)
539 #define MCWDT_CTR_LOWER_LIMIT(base, counter)    (((MCWDT_Type *)(base))->CTR[counter].LOWER_LIMIT)
540 #define MCWDT_CTR_UPPER_LIMIT(base, counter)    (((MCWDT_Type *)(base))->CTR[counter].UPPER_LIMIT)
541 #define MCWDT_CTR_WARN_LIMIT(base, counter)     (((MCWDT_Type *)(base))->CTR[counter].WARN_LIMIT)
542 #define MCWDT_CTR_CONFIG(base, counter)         (((MCWDT_Type *)(base))->CTR[counter].CONFIG)
543 #define MCWDT_CTR_CNT(base, counter)            (((MCWDT_Type *)(base))->CTR[counter].CNT)
544 
545 #define MCWDT_CPU_SELECT(base)                  (((MCWDT_Type *)(base))->CPU_SELECT)
546 #define MCWDT_CTR2_CTL(base)                    (((MCWDT_Type *)(base))->CTR2_CTL)
547 #define MCWDT_CTR2_CONFIG(base)                 (((MCWDT_Type *)(base))->CTR2_CONFIG)
548 #define MCWDT_CTR2_CNT(base)                    (((MCWDT_Type *)(base))->CTR2_CNT)
549 #define MCWDT_LOCK(base)                        (((MCWDT_Type *)(base))->LOCK)
550 #define MCWDT_SERVICE(base)                     (((MCWDT_Type *)(base))->SERVICE)
551 #define MCWDT_INTR(base)                        (((MCWDT_Type *)(base))->INTR)
552 #define MCWDT_INTR_SET(base)                    (((MCWDT_Type *)(base))->INTR_SET)
553 #define MCWDT_INTR_MASK(base)                   (((MCWDT_Type *)(base))->INTR_MASK)
554 #define MCWDT_INTR_MASKED(base)                 (((MCWDT_Type *)(base))->INTR_MASKED)
555 
556 
557 /*******************************************************************************
558 *                TCPWM
559 *******************************************************************************/
560 
561 #define TCPWM_CTRL_SET(base)                (((TCPWM_Type *)(base))->CTRL_SET)
562 #define TCPWM_CTRL_CLR(base)                (((TCPWM_Type *)(base))->CTRL_CLR)
563 #define TCPWM_CMD_START(base)               (((TCPWM_Type *)(base))->CMD_START)
564 #define TCPWM_CMD_RELOAD(base)              (((TCPWM_Type *)(base))->CMD_RELOAD)
565 #define TCPWM_CMD_STOP(base)                (((TCPWM_Type *)(base))->CMD_STOP)
566 #define TCPWM_CMD_CAPTURE(base)             (((TCPWM_Type *)(base))->CMD_CAPTURE)
567 
568 #define TCPWM_CNT_CTRL(base, cntNum)         (((TCPWM_Type *)(base))->CNT[cntNum].CTRL)
569 #define TCPWM_CNT_CC(base, cntNum)           (((TCPWM_Type *)(base))->CNT[cntNum].CC)
570 #define TCPWM_CNT_CC_BUFF(base, cntNum)      (((TCPWM_Type *)(base))->CNT[cntNum].CC_BUFF)
571 #define TCPWM_CNT_COUNTER(base, cntNum)      (((TCPWM_Type *)(base))->CNT[cntNum].COUNTER)
572 #define TCPWM_CNT_PERIOD(base, cntNum)       (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD)
573 #define TCPWM_CNT_PERIOD_BUFF(base, cntNum)  (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD_BUFF)
574 #define TCPWM_CNT_STATUS(base, cntNum)       (((TCPWM_Type *)(base))->CNT[cntNum].STATUS)
575 #define TCPWM_CNT_INTR(base, cntNum)         (((TCPWM_Type *)(base))->CNT[cntNum].INTR)
576 #define TCPWM_CNT_INTR_SET(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].INTR_SET)
577 #define TCPWM_CNT_INTR_MASK(base, cntNum)    (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASK)
578 #define TCPWM_CNT_INTR_MASKED(base, cntNum)  (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASKED)
579 #define TCPWM_CNT_TR_CTRL0(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL0)
580 #define TCPWM_CNT_TR_CTRL1(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL1)
581 #define TCPWM_CNT_TR_CTRL2(base, cntNum)     (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL2)
582 
583 #if (CY_IP_MXTCPWM_INSTANCES == 1UL)
584 #define TCPWM_GRP_CC1_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))
585 #define TCPWM_GRP_AMC_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))
586 #define TCPWM_GRP_SMC_PRESENT_STATUS(base) (TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2))
587 #endif
588 
589 #if (CY_IP_MXTCPWM_INSTANCES == 2UL)
590 #define TCPWM_GRP_CC1_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_CC1_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_CC1_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)))
591 #define TCPWM_GRP_AMC_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_AMC_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_AMC_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)))
592 #define TCPWM_GRP_SMC_PRESENT_STATUS(base) (((base) == (TCPWM_Type *) TCPWM0_BASE) ? (TCPWM0_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM0_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM0_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)) : (TCPWM1_GRP_NR0_CNT_GRP_SMC_PRESENT | (TCPWM1_GRP_NR1_CNT_GRP_SMC_PRESENT << 1) | (TCPWM1_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)))
593 #endif
594 
595 #define TCPWM_GRP_CC1(base, grp) ((bool)(((TCPWM_GRP_CC1_PRESENT_STATUS(base)) >> (grp)) & 0x01U))
596 #define TCPWM_GRP_AMC(base, grp) ((bool)(((TCPWM_GRP_AMC_PRESENT_STATUS(base)) >> (grp)) & 0x01U))
597 #define TCPWM_GRP_SMC(base, grp) ((bool)(((TCPWM_GRP_SMC_PRESENT_STATUS(base)) >> (grp)) & 0x01U))
598 
599 #define TCPWM_GRP_CNT_GET_GRP(cntNum)        ((cntNum )/ 256U)
600 
601 #define TCPWM_GRP_CNT_CTRL(base, grp, cntNum)           (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CTRL)
602 #define TCPWM_GRP_CNT_STATUS(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].STATUS)
603 #define TCPWM_GRP_CNT_COUNTER(base, grp, cntNum)        (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].COUNTER)
604 #define TCPWM_GRP_CNT_CC0(base, grp, cntNum)            (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0)
605 #define TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0_BUFF)
606 #define TCPWM_GRP_CNT_CC1(base, grp, cntNum)            (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1)
607 #define TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1_BUFF)
608 #define TCPWM_GRP_CNT_PERIOD(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD)
609 #define TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD_BUFF)
610 #define TCPWM_GRP_CNT_LINE_SEL(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL)
611 #define TCPWM_GRP_CNT_LINE_SEL_BUFF(base, grp, cntNum)  (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL_BUFF)
612 #define TCPWM_GRP_CNT_DT(base, grp, cntNum)             (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].DT)
613 #define TCPWM_GRP_CNT_TR_CMD(base, grp, cntNum)         (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_CMD)
614 #define TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL0)
615 #define TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL1)
616 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_EDGE_SEL)
617 #define TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_PWM_CTRL)
618 #define TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum)     (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_OUT_SEL)
619 #define TCPWM_GRP_CNT_INTR(base, grp, cntNum)           (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR)
620 #define TCPWM_GRP_CNT_INTR_SET(base, grp, cntNum)       (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_SET)
621 #define TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum)      (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASK)
622 #define TCPWM_GRP_CNT_INTR_MASKED(base, grp, cntNum)    (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASKED)
623 
624 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos
625 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk
626 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos
627 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk
628 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos
629 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk
630 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos
631 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk
632 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos
633 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk
634 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos
635 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk
636 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos
637 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk
638 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos
639 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk
640 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos  TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos
641 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk  TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk
642 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos
643 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk
644 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos
645 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk
646 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos
647 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk
648 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos  TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos
649 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk  TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk
650 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos      TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos
651 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk      TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk
652 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos
653 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk
654 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos          TCPWM_GRP_CNT_CTRL_MODE_Pos
655 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk          TCPWM_GRP_CNT_CTRL_MODE_Msk
656 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos
657 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk
658 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos       TCPWM_GRP_CNT_CTRL_ENABLED_Pos
659 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk       TCPWM_GRP_CNT_CTRL_ENABLED_Msk
660 /* TCPWM_GRP_CNT.STATUS */
661 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos        TCPWM_GRP_CNT_STATUS_DOWN_Pos
662 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk        TCPWM_GRP_CNT_STATUS_DOWN_Msk
663 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos
664 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk
665 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos    TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos
666 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk    TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk
667 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos   TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos
668 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk   TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk
669 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos     TCPWM_GRP_CNT_STATUS_TR_STOP_Pos
670 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk     TCPWM_GRP_CNT_STATUS_TR_STOP_Msk
671 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos    TCPWM_GRP_CNT_STATUS_TR_START_Pos
672 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk    TCPWM_GRP_CNT_STATUS_TR_START_Msk
673 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos
674 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk
675 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos    TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos
676 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk    TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk
677 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos
678 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk
679 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos     TCPWM_GRP_CNT_STATUS_RUNNING_Pos
680 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk     TCPWM_GRP_CNT_STATUS_RUNNING_Msk
681 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos    TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos
682 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk    TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk
683 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos    TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos
684 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk    TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk
685 /* TCPWM_GRP_CNT.COUNTER */
686 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos    TCPWM_GRP_CNT_COUNTER_COUNTER_Pos
687 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk    TCPWM_GRP_CNT_COUNTER_COUNTER_Msk
688 /* TCPWM_GRP_CNT.CC0 */
689 #define TCPWM_GRP_CNT_V2_CC0_CC_Pos             TCPWM_GRP_CNT_CC0_CC_Pos
690 #define TCPWM_GRP_CNT_V2_CC0_CC_Msk             TCPWM_GRP_CNT_CC0_CC_Msk
691 /* TCPWM_GRP_CNT.CC0_BUFF */
692 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos        TCPWM_GRP_CNT_CC0_BUFF_CC_Pos
693 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk        TCPWM_GRP_CNT_CC0_BUFF_CC_Msk
694 /* TCPWM_GRP_CNT.CC1 */
695 #define TCPWM_GRP_CNT_V2_CC1_CC_Pos             TCPWM_GRP_CNT_CC1_CC_Pos
696 #define TCPWM_GRP_CNT_V2_CC1_CC_Msk             TCPWM_GRP_CNT_CC1_CC_Msk
697 /* TCPWM_GRP_CNT.CC1_BUFF */
698 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos        TCPWM_GRP_CNT_CC1_BUFF_CC_Pos
699 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk        TCPWM_GRP_CNT_CC1_BUFF_CC_Msk
700 /* TCPWM_GRP_CNT.PERIOD */
701 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos      TCPWM_GRP_CNT_PERIOD_PERIOD_Pos
702 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk      TCPWM_GRP_CNT_PERIOD_PERIOD_Msk
703 /* TCPWM_GRP_CNT.PERIOD_BUFF */
704 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos
705 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk
706 /* TCPWM_GRP_CNT.LINE_SEL */
707 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos   TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos
708 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk   TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk
709 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos
710 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk
711 /* TCPWM_GRP_CNT.LINE_SEL_BUFF */
712 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos
713 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk
714 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos
715 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk
716 /* TCPWM_GRP_CNT.DT */
717 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos   TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos
718 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk   TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk
719 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos   TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos
720 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk   TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk
721 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos
722 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk
723 /* TCPWM_GRP_CNT.TR_CMD */
724 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos    TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos
725 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk    TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk
726 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos      TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos
727 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk      TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk
728 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos        TCPWM_GRP_CNT_TR_CMD_STOP_Pos
729 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk        TCPWM_GRP_CNT_TR_CMD_STOP_Msk
730 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos       TCPWM_GRP_CNT_TR_CMD_START_Pos
731 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk       TCPWM_GRP_CNT_TR_CMD_START_Msk
732 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos    TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos
733 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk    TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk
734 /* TCPWM_GRP_CNT.TR_IN_SEL0 */
735 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos
736 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk
737 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos
738 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk
739 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos
740 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk
741 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos
742 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk
743 /* TCPWM_GRP_CNT.TR_IN_SEL1 */
744 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos
745 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk
746 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos
747 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk
748 /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */
749 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos
750 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk
751 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos
752 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk
753 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos
754 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk
755 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos
756 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk
757 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos
758 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk
759 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos
760 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk
761 /* TCPWM_GRP_CNT.TR_PWM_CTRL */
762 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos
763 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk
764 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos
765 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk
766 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos
767 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk
768 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos
769 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk
770 /* TCPWM_GRP_CNT.TR_OUT_SEL */
771 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos    TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos
772 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk    TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk
773 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos    TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos
774 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk    TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk
775 /* TCPWM_GRP_CNT.INTR */
776 #define TCPWM_GRP_CNT_V2_INTR_TC_Pos            TCPWM_GRP_CNT_INTR_TC_Pos
777 #define TCPWM_GRP_CNT_V2_INTR_TC_Msk            TCPWM_GRP_CNT_INTR_TC_Msk
778 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos     TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos
779 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk     TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk
780 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos     TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos
781 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk     TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk
782 /* TCPWM_GRP_CNT.INTR_SET */
783 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos        TCPWM_GRP_CNT_INTR_SET_TC_Pos
784 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk        TCPWM_GRP_CNT_INTR_SET_TC_Msk
785 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos
786 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk
787 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos
788 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk
789 /* TCPWM_GRP_CNT.INTR_MASK */
790 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos       TCPWM_GRP_CNT_INTR_MASK_TC_Pos
791 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk       TCPWM_GRP_CNT_INTR_MASK_TC_Msk
792 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos
793 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk
794 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos
795 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk
796 /* TCPWM_GRP_CNT.INTR_MASKED */
797 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos     TCPWM_GRP_CNT_INTR_MASKED_TC_Pos
798 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk     TCPWM_GRP_CNT_INTR_MASKED_TC_Msk
799 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos
800 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk
801 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos
802 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk
803 
804 /* For backward compatibility, we set TCPWM_CNT_STATUS_RUNNING_Pos with TCPWM_GRP_CNT_V2_STATUS_RUNNING
805 we need to define this for version 2 only. */
806 #define TCPWM_CNT_STATUS_RUNNING_Pos 31UL
807 
808 
809 /*******************************************************************************
810 *                SAR
811 *******************************************************************************/
812 
813 #define CY_SAR_INSTANCES                    (2UL)
814 #define CY_SAR0_BASE                        ((SAR_Type*)(cy_device->sar0Base))
815 #define CY_SAR_INSTANCE(base)               ((CY_SAR0_BASE == (base)) ? 0UL : 1UL)
816 
817 #define SAR_SAMPLE_CTRL(base)               (((SAR_V1_Type *)(base))->SAMPLE_CTRL)
818 #define SAR_SAMPLE_TIME01(base)             (((SAR_V1_Type *)(base))->SAMPLE_TIME01)
819 #define SAR_SAMPLE_TIME23(base)             (((SAR_V1_Type *)(base))->SAMPLE_TIME23)
820 
821 #define SAR_RANGE_THRES(base)               (((SAR_V1_Type *)(base))->RANGE_THRES)
822 #define SAR_RANGE_COND(base)                (((SAR_V1_Type *)(base))->RANGE_COND)
823 #define SAR_RANGE_INTR(base)                (((SAR_V1_Type *)(base))->RANGE_INTR)
824 #define SAR_RANGE_INTR_SET(base)            (((SAR_V1_Type *)(base))->RANGE_INTR_SET)
825 
826 #define SAR_RANGE_INTR_MASK(base)           (((SAR_V1_Type *)(base))->RANGE_INTR_MASK)
827 #define SAR_RANGE_INTR_MASKED(base)         (((SAR_V1_Type *)(base))->RANGE_INTR_MASKED)
828 
829 #define SAR_CHAN_EN(base)                   (((SAR_V1_Type *)(base))->CHAN_EN)
830 #define SAR_CHAN_CONFIG(base, chan)         (((SAR_V1_Type *)(base))->CHAN_CONFIG[(chan)])
831 #define SAR_CHAN_RESULT(base, chan )        (((SAR_V1_Type *)(base))->CHAN_RESULT[(chan)])
832 #define SAR_CHAN_RESULT_UPDATED(base)       (((SAR_V1_Type *)(base))->CHAN_RESULT_UPDATED)
833 
834 #define SAR_INTR(base)                      (((SAR_V1_Type *)(base))->INTR)
835 #define SAR_INTR_MASK(base)                 (((SAR_V1_Type *)(base))->INTR_MASK)
836 #define SAR_INTR_MASKED(base)               (((SAR_V1_Type *)(base))->INTR_MASKED)
837 #define SAR_INTR_SET(base)                  (((SAR_V1_Type *)(base))->INTR_SET)
838 #define SAR_INTR_CAUSE(base)                (((SAR_V1_Type *)(base))->INTR_CAUSE)
839 
840 #define SAR_MUX_SWITCH_CLEAR0(base)         (((SAR_V1_Type *)(base))->MUX_SWITCH_CLEAR0)
841 #define SAR_MUX_SWITCH0(base)               (((SAR_V1_Type *)(base))->MUX_SWITCH0)
842 #define SAR_MUX_SWITCH_SQ_CTRL(base)        (((SAR_V1_Type *)(base))->MUX_SWITCH_SQ_CTRL)
843 #define SAR_MUX_SWITCH_DS_CTRL(base)        (((SAR_V1_Type *)(base))->MUX_SWITCH_DS_CTRL)
844 
845 #define SAR_ANA_TRIM0(base)                 (((SAR_V1_Type *)(base))->ANA_TRIM0)
846 #define SAR_CTRL(base)                      (((SAR_V1_Type *)(base))->CTRL)
847 #define SAR_STATUS(base)                    (((SAR_V1_Type *)(base))->STATUS)
848 #define SAR_START_CTRL(base)                (((SAR_V1_Type *)(base))->START_CTRL)
849 
850 #define SAR_SATURATE_INTR(base)             (((SAR_V1_Type *)(base))->SATURATE_INTR)
851 #define SAR_SATURATE_INTR_MASK(base)        (((SAR_V1_Type *)(base))->SATURATE_INTR_MASK)
852 #define SAR_SATURATE_INTR_MASKED(base)      (((SAR_V1_Type *)(base))->SATURATE_INTR_MASKED)
853 #define SAR_SATURATE_INTR_SET(base)         (((SAR_V1_Type *)(base))->SATURATE_INTR_SET)
854 
855 #define SAR_INJ_CHAN_CONFIG(base)           (((SAR_V1_Type *)(base))->INJ_CHAN_CONFIG)
856 #define SAR_INJ_RESULT(base)                (((SAR_V1_Type *)(base))->INJ_RESULT)
857 
858 /*******************************************************************************
859 *                FAULT
860 *******************************************************************************/
861 
862 #define FAULT_CTL(base)                         (((FAULT_STRUCT_Type *)(base))->CTL)
863 #define FAULT_STATUS(base)                      (((FAULT_STRUCT_Type *)(base))->STATUS)
864 #define FAULT_DATA(base)                        (((FAULT_STRUCT_Type *)(base))->DATA)
865 #define FAULT_PENDING0(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING0)
866 #define FAULT_PENDING1(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING1)
867 #define FAULT_PENDING2(base)                    (((FAULT_STRUCT_Type *)(base))->PENDING2)
868 #define FAULT_MASK0(base)                       (((FAULT_STRUCT_Type *)(base))->MASK0)
869 #define FAULT_MASK1(base)                       (((FAULT_STRUCT_Type *)(base))->MASK1)
870 #define FAULT_MASK2(base)                       (((FAULT_STRUCT_Type *)(base))->MASK2)
871 #define FAULT_INTR(base)                        (((FAULT_STRUCT_Type *)(base))->INTR)
872 #define FAULT_INTR_SET(base)                    (((FAULT_STRUCT_Type *)(base))->INTR_SET)
873 #define FAULT_INTR_MASK(base)                   (((FAULT_STRUCT_Type *)(base))->INTR_MASK)
874 #define FAULT_INTR_MASKED(base)                 (((FAULT_STRUCT_Type *)(base))->INTR_MASKED)
875 
876 /*******************************************************************************
877 *                SDHC
878 *******************************************************************************/
879 
880 #define SDHC_WRAP_CTL(base)                     (((SDHC_Type *)(base))->WRAP.CTL)
881 #define SDHC_CORE_SDMASA_R(base)                (((SDHC_Type *)(base))->CORE.SDMASA_R)
882 #define SDHC_CORE_BLOCKSIZE_R(base)             (((SDHC_Type *)(base))->CORE.BLOCKSIZE_R)
883 #define SDHC_CORE_BLOCKCOUNT_R(base)            (((SDHC_Type *)(base))->CORE.BLOCKCOUNT_R)
884 #define SDHC_CORE_ARGUMENT_R(base)              (((SDHC_Type *)(base))->CORE.ARGUMENT_R)
885 #define SDHC_CORE_XFER_MODE_R(base)             (((SDHC_Type *)(base))->CORE.XFER_MODE_R)
886 #define SDHC_CORE_CMD_R(base)                   (((SDHC_Type *)(base))->CORE.CMD_R)
887 #define SDHC_CORE_RESP01_R(base)                (((SDHC_Type *)(base))->CORE.RESP01_R)
888 #define SDHC_CORE_RESP23_R(base)                (((SDHC_Type *)(base))->CORE.RESP23_R)
889 #define SDHC_CORE_RESP45_R(base)                (((SDHC_Type *)(base))->CORE.RESP45_R)
890 #define SDHC_CORE_RESP67_R(base)                (((SDHC_Type *)(base))->CORE.RESP67_R)
891 #define SDHC_CORE_BUF_DATA_R(base)              (((SDHC_Type *)(base))->CORE.BUF_DATA_R)
892 #define SDHC_CORE_PSTATE_REG(base)              (((SDHC_Type *)(base))->CORE.PSTATE_REG)
893 #define SDHC_CORE_HOST_CTRL1_R(base)            (((SDHC_Type *)(base))->CORE.HOST_CTRL1_R)
894 #define SDHC_CORE_PWR_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.PWR_CTRL_R)
895 #define SDHC_CORE_BGAP_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.BGAP_CTRL_R)
896 #define SDHC_CORE_WUP_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.WUP_CTRL_R)
897 #define SDHC_CORE_CLK_CTRL_R(base)              (((SDHC_Type *)(base))->CORE.CLK_CTRL_R)
898 #define SDHC_CORE_TOUT_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.TOUT_CTRL_R)
899 #define SDHC_CORE_SW_RST_R(base)                (((SDHC_Type *)(base))->CORE.SW_RST_R)
900 #define SDHC_CORE_NORMAL_INT_STAT_R(base)       (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_R)
901 #define SDHC_CORE_ERROR_INT_STAT_R(base)        (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_R)
902 #define SDHC_CORE_NORMAL_INT_STAT_EN_R(base)    (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_EN_R)
903 #define SDHC_CORE_ERROR_INT_STAT_EN_R(base)     (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_EN_R)
904 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base)  (((SDHC_Type *)(base))->CORE.NORMAL_INT_SIGNAL_EN_R)
905 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base)   (((SDHC_Type *)(base))->CORE.ERROR_INT_SIGNAL_EN_R)
906 #define SDHC_CORE_AUTO_CMD_STAT_R(base)         (((SDHC_Type *)(base))->CORE.AUTO_CMD_STAT_R)
907 #define SDHC_CORE_HOST_CTRL2_R(base)            (((SDHC_Type *)(base))->CORE.HOST_CTRL2_R)
908 #define SDHC_CORE_CAPABILITIES1_R(base)         (((SDHC_Type *)(base))->CORE.CAPABILITIES1_R)
909 #define SDHC_CORE_CAPABILITIES2_R(base)         (((SDHC_Type *)(base))->CORE.CAPABILITIES2_R)
910 #define SDHC_CORE_CURR_CAPABILITIES1_R(base)    (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES1_R)
911 #define SDHC_CORE_CURR_CAPABILITIES2_R(base)    (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES2_R)
912 #define SDHC_CORE_ADMA_ERR_STAT_R(base)         (((SDHC_Type *)(base))->CORE.ADMA_ERR_STAT_R)
913 #define SDHC_CORE_ADMA_SA_LOW_R(base)           (((SDHC_Type *)(base))->CORE.ADMA_SA_LOW_R)
914 #define SDHC_CORE_ADMA_ID_LOW_R(base)           (((SDHC_Type *)(base))->CORE.ADMA_ID_LOW_R)
915 #define SDHC_CORE_EMMC_CTRL_R(base)             (((SDHC_Type *)(base))->CORE.EMMC_CTRL_R)
916 #define SDHC_CORE_GP_OUT_R(base)                (((SDHC_Type *)(base))->CORE.GP_OUT_R)
917 
918 /*******************************************************************************
919 *                SMARTIO
920 *******************************************************************************/
921 
922 #define SMARTIO_PRT_CTL(base)               (((SMARTIO_PRT_Type *)(base))->CTL)
923 #define SMARTIO_PRT_SYNC_CTL(base)          (((SMARTIO_PRT_Type *)(base))->SYNC_CTL)
924 #define SMARTIO_PRT_LUT_SEL(base, idx)      (((SMARTIO_PRT_Type *)(base))->LUT_SEL[idx])
925 #define SMARTIO_PRT_LUT_CTL(base, idx)      (((SMARTIO_PRT_Type *)(base))->LUT_CTL[idx])
926 #define SMARTIO_PRT_DU_SEL(base)            (((SMARTIO_PRT_Type *)(base))->DU_SEL)
927 #define SMARTIO_PRT_DU_CTL(base)            (((SMARTIO_PRT_Type *)(base))->DU_CTL)
928 #define SMARTIO_PRT_DATA(base)              (((SMARTIO_PRT_Type *)(base))->DATA)
929 
930 
931 /*******************************************************************************
932 *                SMIF
933 *******************************************************************************/
934 
935 /* Feature Flags - Start
936  * Few products have very less memory available in BOOT ROM and they do not require
937  * SFDP enumeration of Octal parts. Hence, we introduce feature flags to enable
938  * specific features only where Octal SFDP enumeration and Hyperbus devices are supported
939  * using below feature flags
940  */
941 #define SMIF_OCTAL_SFDP_SUPPORT
942 #define SMIF_HYPERBUS_DEVICE_SUPPORT
943 /* Feature Flags - End */
944 
945 #define SMIF_DEVICE_CTL(base)               (((SMIF_DEVICE_Type *)(base))->CTL)
946 #define SMIF_DEVICE_ADDR(base)              (((SMIF_DEVICE_Type *)(base))->ADDR)
947 #define SMIF_DEVICE_ADDR_CTL(base)          (((SMIF_DEVICE_Type *)(base))->ADDR_CTL)
948 #define SMIF_DEVICE_MASK(base)              (((SMIF_DEVICE_Type *)(base))->MASK)
949 #define SMIF_DEVICE_RD_CMD_CTL(base)        (((SMIF_DEVICE_Type *)(base))->RD_CMD_CTL)
950 #define SMIF_DEVICE_RD_ADDR_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_ADDR_CTL)
951 #define SMIF_DEVICE_RD_MODE_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_MODE_CTL)
952 #define SMIF_DEVICE_RD_DUMMY_CTL(base)      (((SMIF_DEVICE_Type *)(base))->RD_DUMMY_CTL)
953 #define SMIF_DEVICE_RD_DATA_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_DATA_CTL)
954 #define SMIF_DEVICE_RD_BOUND_CTL(base)       (((SMIF_DEVICE_Type *)(base))->RD_BOUND_CTL)
955 #define SMIF_DEVICE_WR_CMD_CTL(base)        (((SMIF_DEVICE_Type *)(base))->WR_CMD_CTL)
956 #define SMIF_DEVICE_WR_ADDR_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_ADDR_CTL)
957 #define SMIF_DEVICE_WR_MODE_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_MODE_CTL)
958 #define SMIF_DEVICE_WR_DUMMY_CTL(base)      (((SMIF_DEVICE_Type *)(base))->WR_DUMMY_CTL)
959 #define SMIF_DEVICE_WR_DATA_CTL(base)       (((SMIF_DEVICE_Type *)(base))->WR_DATA_CTL)
960 
961 #define SMIF_DEVICE_IDX(base, deviceIndex)                 (((SMIF_Type *)(base))->DEVICE[deviceIndex])
962 
963 #define SMIF_DEVICE_IDX_CTL(base, deviceIndex)             (SMIF_DEVICE_IDX(base, deviceIndex).CTL)
964 #define SMIF_DEVICE_IDX_ADDR(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).ADDR)
965 #define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex)        (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL)
966 #define SMIF_DEVICE_IDX_MASK(base, deviceIndex)            (SMIF_DEVICE_IDX(base, deviceIndex).MASK)
967 #define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL)
968 #define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL)
969 #define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL)
970 #define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL)
971 #define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL)
972 #define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex)      (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL)
973 #define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL)
974 #define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL)
975 #define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex)    (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL)
976 #define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex)     (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL)
977 
978 #define SMIF_CTL(base)                      (((SMIF_Type *)(base))->CTL)
979 #define SMIF_DELAY_TAP_SEL(base)            (((SMIF_Type *)(base))->DELAY_TAP_SEL)
980 #define SMIF_STATUS(base)                   (((SMIF_Type *)(base))->STATUS)
981 #define SMIF_TX_DATA_FIFO_CTL(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_CTL)
982 #define SMIF_RX_DATA_MMIO_FIFO_CTL(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_CTL)
983 #define SMIF_TX_DATA_FIFO_WR1(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_WR1)
984 #define SMIF_TX_DATA_FIFO_WR2(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_WR2)
985 #define SMIF_TX_DATA_FIFO_WR4(base)         (((SMIF_Type *)(base))->TX_DATA_FIFO_WR4)
986 #define SMIF_TX_DATA_FIFO_WR1ODD(base)      (((SMIF_Type *)(base))->TX_DATA_FIFO_WR1ODD)
987 #define SMIF_RX_DATA_FIFO_STATUS(base)        (((SMIF_Type *)(base))->RX_DATA_FIFO_STATUS)
988 #define SMIF_RX_DATA_MMIO_FIFO_STATUS(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_STATUS)
989 #define SMIF_RX_DATA_MMIO_FIFO_RD1(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1)
990 #define SMIF_RX_DATA_MMIO_FIFO_RD2(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD2)
991 #define SMIF_RX_DATA_MMIO_FIFO_RD4(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD4)
992 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT(base)    (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1_SILENT)
993 #define SMIF_TX_CMD_FIFO_WR(base)           (((SMIF_Type *)(base))->TX_CMD_FIFO_WR)
994 #define SMIF_TX_CMD_FIFO_STATUS(base)       (((SMIF_Type *)(base))->TX_CMD_FIFO_STATUS)
995 #define SMIF_TX_DATA_FIFO_STATUS(base)      (((SMIF_Type *)(base))->TX_DATA_FIFO_STATUS)
996 #define SMIF_INTR(base)                     (((SMIF_Type *)(base))->INTR)
997 #define SMIF_INTR_SET(base)                 (((SMIF_Type *)(base))->INTR_SET)
998 #define SMIF_INTR_MASK(base)                (((SMIF_Type *)(base))->INTR_MASK)
999 #define SMIF_INTR_MASKED(base)              (((SMIF_Type *)(base))->INTR_MASKED)
1000 #define SMIF_CRYPTO_INPUT0(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT0)
1001 #define SMIF_CRYPTO_INPUT1(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT1)
1002 #define SMIF_CRYPTO_INPUT2(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT2)
1003 #define SMIF_CRYPTO_INPUT3(base)            (((SMIF_Type *)(base))->CRYPTO_INPUT3)
1004 #define SMIF_CRYPTO_KEY0(base)              (((SMIF_Type *)(base))->CRYPTO_KEY0)
1005 #define SMIF_CRYPTO_KEY1(base)              (((SMIF_Type *)(base))->CRYPTO_KEY1)
1006 #define SMIF_CRYPTO_KEY2(base)              (((SMIF_Type *)(base))->CRYPTO_KEY2)
1007 #define SMIF_CRYPTO_KEY3(base)              (((SMIF_Type *)(base))->CRYPTO_KEY3)
1008 #define SMIF_CRYPTO_OUTPUT0(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT0)
1009 #define SMIF_CRYPTO_OUTPUT1(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT1)
1010 #define SMIF_CRYPTO_OUTPUT2(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT2)
1011 #define SMIF_CRYPTO_OUTPUT3(base)           (((SMIF_Type *)(base))->CRYPTO_OUTPUT3)
1012 #define SMIF_CRYPTO_CMD(base)               (((SMIF_Type *)(base))->CRYPTO_CMD)
1013 #define SMIF_SLOW_CA_CTL(base)              (((SMIF_Type *)(base))->SLOW_CA_CTL)
1014 #define SMIF_FAST_CA_CTL(base)              (((SMIF_Type *)(base))->FAST_CA_CTL)
1015 #define SMIF_SLOW_CA_CMD(base)              (((SMIF_Type *)(base))->SLOW_CA_CMD)
1016 #define SMIF_FAST_CA_CMD(base)              (((SMIF_Type *)(base))->FAST_CA_CMD)
1017 
1018 
1019 /*******************************************************************************
1020 *                DW
1021 *******************************************************************************/
1022 
1023 #define CY_DW                               (0UL)
1024 #define CY_DW_CRC                           (1UL)
1025 #define CY_DW0_BASE                         DW0
1026 #define CY_DW1_BASE                         DW1
1027 #define CY_DW0_CH_NR                        CPUSS_DW0_CH_NR
1028 #define CY_DW1_CH_NR                        CPUSS_DW1_CH_NR
1029 
1030 #define CY_DW_CH_CTL_PRIO_Pos               ((uint32_t)(DW_CH_STRUCT_CH_CTL_PRIO_Pos))
1031 #define CY_DW_CH_CTL_PRIO_Msk               ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos))
1032 #define CY_DW_CH_CTL_PREEMPTABLE_Pos        ((uint32_t)(DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos))
1033 #define CY_DW_CH_CTL_PREEMPTABLE_Msk        ((uint32_t)(0x1UL << CY_DW_CH_CTL_PREEMPTABLE_Pos))
1034 #define CY_DW_STATUS_CH_IDX_Pos             ((uint32_t)(DW_STATUS_CH_IDX_Pos))
1035 #define CY_DW_STATUS_CH_IDX_Msk             (DW_STATUS_CH_IDX_Msk)
1036 
1037 #define DW_CTL(base)                        (((DW_Type*)(base))->CTL)
1038 #define DW_STATUS(base)                     (((DW_Type const*)(base))->STATUS)
1039 #define DW_DESCR_SRC(base)                  (((DW_Type*)(base))->ACT_DESCR_SRC)
1040 #define DW_DESCR_DST(base)                  (((DW_Type*)(base))->ACT_DESCR_DST)
1041 
1042 #define DW_CRC_CTL(base)                    (((DW_Type*)(base))->CRC_CTL)
1043 #define DW_CRC_DATA_CTL(base)               (((DW_Type*)(base))->CRC_DATA_CTL)
1044 #define DW_CRC_REM_CTL(base)                (((DW_Type*)(base))->CRC_REM_CTL)
1045 #define DW_CRC_POL_CTL(base)                (((DW_Type*)(base))->CRC_POL_CTL)
1046 #define DW_CRC_LFSR_CTL(base)               (((DW_Type*)(base))->CRC_LFSR_CTL)
1047 
1048 #define DW_CH_OFFSET                        (uint32_t)(offsetof(DW_Type, CH_STRUCT))
1049 #define DW_CH_SIZE                            (uint32_t)(sizeof(DW_CH_STRUCT_Type))
1050 
1051 #define DW_CH(base, chan)                    ((DW_CH_STRUCT_Type*)((uint32_t)(base) + DW_CH_OFFSET + (chan * DW_CH_SIZE)))
1052 #define DW_CH_CTL(base, chan)               (DW_CH((base), (chan))->CH_CTL)
1053 #define DW_CH_STATUS(base, chan)            (DW_CH((base), (chan))->CH_STATUS)
1054 #define DW_CH_IDX(base, chan)               (DW_CH((base), (chan))->CH_IDX)
1055 #define DW_CH_CURR_PTR(base, chan)          (DW_CH((base), (chan))->CH_CURR_PTR)
1056 
1057 #define DW_CH_INTR(base, chan)              (DW_CH((base), (chan))->INTR)
1058 #define DW_CH_INTR_SET(base, chan)          (DW_CH((base), (chan))->INTR_SET)
1059 #define DW_CH_INTR_MASK(base, chan)         (DW_CH((base), (chan))->INTR_MASK)
1060 #define DW_CH_INTR_MASKED(base, chan)       (DW_CH((base), (chan))->INTR_MASKED)
1061 
1062 #define DW_V2_CRC_CTL_DATA_REVERSE_Msk DW_CRC_CTL_DATA_REVERSE_Msk
1063 #define DW_V2_CRC_CTL_REM_REVERSE_Msk DW_CRC_CTL_REM_REVERSE_Msk
1064 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Msk DW_CRC_DATA_CTL_DATA_XOR_Msk
1065 #define DW_V2_CRC_REM_CTL_REM_XOR_Msk DW_CRC_REM_CTL_REM_XOR_Msk
1066 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk DW_CRC_POL_CTL_POLYNOMIAL_Msk
1067 #define DW_V2_CRC_LFSR_CTL_LFSR32_Msk DW_CRC_LFSR_CTL_LFSR32_Msk
1068 #define DW_V2_CRC_CTL_DATA_REVERSE_Pos DW_CRC_CTL_DATA_REVERSE_Pos
1069 #define DW_V2_CRC_CTL_REM_REVERSE_Pos DW_CRC_CTL_REM_REVERSE_Pos
1070 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Pos DW_CRC_DATA_CTL_DATA_XOR_Pos
1071 #define DW_V2_CRC_REM_CTL_REM_XOR_Pos DW_CRC_REM_CTL_REM_XOR_Pos
1072 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos DW_CRC_POL_CTL_POLYNOMIAL_Pos
1073 #define DW_V2_CRC_LFSR_CTL_LFSR32_Pos DW_CRC_LFSR_CTL_LFSR32_Pos
1074 
1075 
1076 /*******************************************************************************
1077 *                DMAC
1078 *******************************************************************************/
1079 
1080 #define CY_DMAC_CH_NR                       CPUSS_DMAC_CH_NR
1081 #define DMAC_CTL(base)                      (((DMAC_Type*)(base))->CTL)
1082 #define DMAC_ACTIVE(base)                   (((DMAC_Type const*)(base))->ACTIVE)
1083 #define DMAC_CH(base, chan)                 (&(((DMAC_Type*)(base))->CH[(chan)]))
1084 #define DMAC_CH_CTL(base, chan)             (DMAC_CH(base, chan)->CTL)
1085 #define DMAC_CH_IDX(base, chan)             (DMAC_CH(base, chan)->IDX)
1086 #define DMAC_CH_CURR(base, chan)            (DMAC_CH(base, chan)->CURR)
1087 #define DMAC_CH_DESCR_SRC(base, chan)       (DMAC_CH(base, chan)->DESCR_SRC)
1088 #define DMAC_CH_DESCR_DST(base, chan)       (DMAC_CH(base, chan)->DESCR_DST)
1089 #define DMAC_CH_INTR(base, chan)            (DMAC_CH(base, chan)->INTR)
1090 #define DMAC_CH_INTR_SET(base, chan)        (DMAC_CH(base, chan)->INTR_SET)
1091 #define DMAC_CH_INTR_MASK(base, chan)       (DMAC_CH(base, chan)->INTR_MASK)
1092 #define DMAC_CH_INTR_MASKED(base, chan)     (DMAC_CH(base, chan)->INTR_MASKED)
1093 
1094 #define DMAC_CH_V2_INTR_COMPLETION_Msk DMAC_CH_INTR_COMPLETION_Msk
1095 #define DMAC_CH_V2_INTR_COMPLETION_Pos DMAC_CH_INTR_COMPLETION_Pos
1096 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk DMAC_CH_INTR_SRC_BUS_ERROR_Msk
1097 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Pos DMAC_CH_INTR_SRC_BUS_ERROR_Pos
1098 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk DMAC_CH_INTR_DST_BUS_ERROR_Msk
1099 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Pos DMAC_CH_INTR_DST_BUS_ERROR_Pos
1100 #define DMAC_CH_V2_INTR_SRC_MISAL_Msk DMAC_CH_INTR_SRC_MISAL_Msk
1101 #define DMAC_CH_V2_INTR_SRC_MISAL_Pos DMAC_CH_INTR_SRC_MISAL_Pos
1102 #define DMAC_CH_V2_INTR_DST_MISAL_Msk DMAC_CH_INTR_DST_MISAL_Msk
1103 #define DMAC_CH_V2_INTR_DST_MISAL_Pos DMAC_CH_INTR_DST_MISAL_Pos
1104 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk DMAC_CH_INTR_CURR_PTR_NULL_Msk
1105 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Pos DMAC_CH_INTR_CURR_PTR_NULL_Pos
1106 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk
1107 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Pos DMAC_CH_INTR_ACTIVE_CH_DISABLED_Pos
1108 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk DMAC_CH_INTR_DESCR_BUS_ERROR_Msk
1109 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Pos DMAC_CH_INTR_DESCR_BUS_ERROR_Pos
1110 #define DMAC_V2_CTL_ENABLED_Msk DMAC_CTL_ENABLED_Msk
1111 #define DMAC_V2_CTL_ENABLED_Pos DMAC_CTL_ENABLED_Pos
1112 #define DMAC_V2_ACTIVE_ACTIVE_Msk DMAC_ACTIVE_ACTIVE_Msk
1113 #define DMAC_V2_ACTIVE_ACTIVE_Pos DMAC_ACTIVE_ACTIVE_Pos
1114 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Msk DMAC_CH_DESCR_CTL_INTR_TYPE_Msk
1115 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Pos DMAC_CH_DESCR_CTL_INTR_TYPE_Pos
1116 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk DMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk
1117 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Pos DMAC_CH_DESCR_CTL_TR_IN_TYPE_Pos
1118 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk
1119 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Pos DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Pos
1120 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Msk DMAC_CH_DESCR_CTL_DATA_SIZE_Msk
1121 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Pos DMAC_CH_DESCR_CTL_DATA_SIZE_Pos
1122 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Msk DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Msk
1123 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Pos DMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Pos
1124 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Msk DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Msk
1125 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Pos DMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Pos
1126 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Msk DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Msk
1127 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Pos DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Pos
1128 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Msk DMAC_CH_DESCR_CTL_DESCR_TYPE_Msk
1129 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Pos DMAC_CH_DESCR_CTL_DESCR_TYPE_Pos
1130 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Msk DMAC_CH_DESCR_CTL_CH_DISABLE_Msk
1131 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Pos DMAC_CH_DESCR_CTL_CH_DISABLE_Pos
1132 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Msk DMAC_CH_DESCR_X_INCR_SRC_X_Msk
1133 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Pos DMAC_CH_DESCR_X_INCR_SRC_X_Pos
1134 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Msk DMAC_CH_DESCR_X_INCR_DST_X_Msk
1135 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Pos DMAC_CH_DESCR_X_INCR_DST_X_Pos
1136 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Msk DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Msk
1137 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Pos DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Pos
1138 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Msk DMAC_CH_DESCR_Y_INCR_SRC_Y_Msk
1139 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Pos DMAC_CH_DESCR_Y_INCR_SRC_Y_Pos
1140 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Msk DMAC_CH_DESCR_Y_INCR_DST_Y_Msk
1141 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Pos DMAC_CH_DESCR_Y_INCR_DST_Y_Pos
1142 #define DMAC_CH_V2_CTL_ENABLED_Msk DMAC_CH_CTL_ENABLED_Msk
1143 #define DMAC_CH_V2_CTL_ENABLED_Pos DMAC_CH_CTL_ENABLED_Pos
1144 #define DMAC_CH_V2_CTL_PRIO_Msk DMAC_CH_CTL_PRIO_Msk
1145 #define DMAC_CH_V2_CTL_PRIO_Pos DMAC_CH_CTL_PRIO_Pos
1146 #define DMAC_CH_V2_IDX_X_Msk DMAC_CH_IDX_X_Msk
1147 #define DMAC_CH_V2_IDX_X_Pos DMAC_CH_IDX_X_Pos
1148 #define DMAC_CH_V2_IDX_Y_Msk DMAC_CH_IDX_Y_Msk
1149 #define DMAC_CH_V2_IDX_Y_Pos DMAC_CH_IDX_Y_Pos
1150 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Msk DMAC_CH_DESCR_CTL_DATA_PREFETCH_Msk
1151 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Pos DMAC_CH_DESCR_CTL_DATA_PREFETCH_Pos
1152 #define DMAC_CH_V2_CTL_B_Msk DMAC_CH_CTL_B_Msk
1153 #define DMAC_CH_V2_CTL_B_Pos DMAC_CH_CTL_B_Pos
1154 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Msk DMAC_CH_DESCR_X_SIZE_X_COUNT_Msk
1155 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Pos DMAC_CH_DESCR_X_SIZE_X_COUNT_Pos
1156 
1157 
1158 /*******************************************************************************
1159 *                PERI
1160 *******************************************************************************/
1161 /*******************************************************************************
1162 *                PERI PCLK
1163 *******************************************************************************/
1164 
1165 #define PERI_INSTANCE_COUNT                    (1U)
1166 
1167 #ifndef PERI0_PCLK_GROUP_NR
1168 #define PERI0_PCLK_GROUP_NR     PERI_PCLK_GROUP_NR
1169 #endif
1170 
1171 #ifndef PERI1_PCLK_GROUP_NR
1172 #define PERI1_PCLK_GROUP_NR     (0U)
1173 #endif
1174 
1175 
1176 #ifndef PERI_PCLK0_BASE
1177 #define PERI_PCLK0_BASE     PERI_PCLK_BASE
1178 #endif
1179 
1180 #ifndef PERI_PCLK1_BASE
1181 #define PERI_PCLK1_BASE     0U
1182 #endif
1183 
1184 #if (PERI_INSTANCE_COUNT == 1U)
1185 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT
1186 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT
1187 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0U
1188 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0U
1189 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0U
1190 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0U
1191 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0U
1192 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1193 
1194 
1195 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT
1196 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT
1197 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0U
1198 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0U
1199 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0U
1200 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0U
1201 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0U
1202 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1203 
1204 
1205 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT
1206 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT
1207 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0U
1208 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 0U
1209 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0U
1210 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0U
1211 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0U
1212 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1213 
1214 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT
1215 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT
1216 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0U
1217 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0U
1218 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0U
1219 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0U
1220 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0U
1221 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1222 
1223 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 0U
1224 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 0U
1225 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0U
1226 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0U
1227 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0U
1228 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0U
1229 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0U
1230 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1231 
1232 
1233 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 0U
1234 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 0U
1235 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0U
1236 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0U
1237 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0U
1238 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0U
1239 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0U
1240 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1241 
1242 
1243 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0U
1244 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 0U
1245 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0U
1246 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 0U
1247 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0U
1248 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0U
1249 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0U
1250 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1251 
1252 
1253 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 0U
1254 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 0U
1255 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0U
1256 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0U
1257 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0U
1258 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0U
1259 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0U
1260 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1261 
1262 #endif
1263 
1264 #define PERI_PCLK_PERI_NUM_Msk                 (0x000000FFU)
1265 #define PERI_PCLK_GR_NUM_Msk                   (0x0000FF00U)
1266 #define PERI_PCLK_GR_NUM_Pos                   (8U)
1267 #define PERI_PCLK_PERIPHERAL_GROUP_NUM         (1UL << PERI_PCLK_GR_NUM_Pos)
1268 #define PERI_PCLK_INST_NUM_Msk                 (0x00FF0000U)
1269 #define PERI_PCLK_INST_NUM_Pos                 (16U)
1270 
1271 #define PERI_PCLK_GR_NUM(instNum)              (((instNum) == 0U)? PERI0_PCLK_GROUP_NR : PERI1_PCLK_GROUP_NR)
1272 
1273 #define PERI_PCLK1_OFFSET                      (PERI_PCLK1_BASE - PERI_PCLK0_BASE)
1274 #define PERI_PCLK_REG_BASE(instNum)            ((PERI_PCLK_Type*)(PERI_PCLK0_BASE + ((instNum) * PERI_PCLK1_OFFSET)))
1275 
1276 #define PERI_DIV_8_CTL(instNum, grNum, divNum)                   ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_8_CTL[divNum]
1277 #define PERI_DIV_16_CTL(instNum, grNum, divNum)                  ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_CTL[divNum]
1278 #define PERI_DIV_16_5_CTL(instNum, grNum, divNum)                ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_5_CTL[divNum]
1279 #define PERI_DIV_24_5_CTL(instNum, grNum, divNum)                ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_24_5_CTL[divNum]
1280 #define PERI_CLOCK_CTL(instNum, grNum, periNum)                  ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL[periNum]
1281 #define PERI_DIV_CMD(instNum, grNum)                             ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_CMD
1282 
1283 #define PERI_DIV_8_NR(instNum, grNum)           (((instNum) == 0U) ? \
1284                                                   (((grNum) <= 3U) ? \
1285                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) |      \
1286                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U)         |    \
1287                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U)        |    \
1288                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1289                                                   : \
1290                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) |        \
1291                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U)    |    \
1292                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U)   |    \
1293                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1294                                                   : \
1295                                                   (((grNum) <= 3U) ? \
1296                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) |      \
1297                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U)          |    \
1298                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U)         |    \
1299                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1300                                                   : \
1301                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) |         \
1302                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U)    |    \
1303                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U)   |    \
1304                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1305 
1306 #define PERI_DIV_16_NR(instNum, grNum)           (((instNum) == 0U) ? \
1307                                                   (((grNum) <= 3U) ? \
1308                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) |      \
1309                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U)         |    \
1310                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U)        |    \
1311                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1312                                                   : \
1313                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) |         \
1314                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U)    |    \
1315                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U)   |    \
1316                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1317                                                   : \
1318                                                   (((grNum) <= 3U) ? \
1319                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) |       \
1320                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U)          |    \
1321                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U)         |    \
1322                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1323                                                   : \
1324                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) |         \
1325                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U)    |    \
1326                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U)   |    \
1327                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1328 
1329 #define PERI_DIV_16_5_NR(instNum, grNum)         (((instNum) == 0U) ? \
1330                                                   (((grNum) <= 3U) ? \
1331                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) |          \
1332                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U)    |    \
1333                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U)    |    \
1334                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1335                                                   : \
1336                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) |         \
1337                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U)    |    \
1338                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U)   |    \
1339                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1340                                                   : \
1341                                                   (((grNum) <= 3U) ? \
1342                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) |       \
1343                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U)          |    \
1344                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U)         |    \
1345                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1346                                                   : \
1347                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) |         \
1348                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U)    |    \
1349                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U)   |    \
1350                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1351 
1352 #define PERI_DIV_24_5_NR(instNum, grNum)         (((instNum) == 0U) ? \
1353                                                   (((grNum) <= 3U) ? \
1354                                                   ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT) |      \
1355                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U)         |    \
1356                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U)        |    \
1357                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1358                                                   : \
1359                                                   ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) |         \
1360                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U)    |    \
1361                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U)   |    \
1362                                                   (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1363                                                   : \
1364                                                   (((grNum) <= 3U) ? \
1365                                                   ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT) |       \
1366                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U)          |    \
1367                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U)         |    \
1368                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1369                                                   : \
1370                                                   ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) |         \
1371                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U)    |    \
1372                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U)   |    \
1373                                                   (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1374 
1375 /* PERI_PCLK_GR.DIV_CMD */
1376 #define CY_PERI_DIV_CMD_DIV_SEL_Pos             PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1377 #define CY_PERI_DIV_CMD_DIV_SEL_Msk             PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1378 #define CY_PERI_DIV_CMD_TYPE_SEL_Pos            PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1379 #define CY_PERI_DIV_CMD_TYPE_SEL_Msk            PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1380 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Pos          PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1381 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Msk          PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1382 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos         PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1383 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk         PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1384 #define CY_PERI_DIV_CMD_DISABLE_Pos             PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1385 #define CY_PERI_DIV_CMD_DISABLE_Msk             PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1386 #define CY_PERI_DIV_CMD_ENABLE_Pos              PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1387 #define CY_PERI_DIV_CMD_ENABLE_Msk              PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1388 
1389 
1390 #define PERI_DIV_CMD_DIV_SEL_Pos                PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1391 #define PERI_DIV_CMD_DIV_SEL_Msk                PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1392 #define PERI_DIV_CMD_TYPE_SEL_Pos               PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1393 #define PERI_DIV_CMD_TYPE_SEL_Msk               PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1394 #define PERI_DIV_CMD_PA_DIV_SEL_Pos             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1395 #define PERI_DIV_CMD_PA_DIV_SEL_Msk             PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1396 #define PERI_DIV_CMD_PA_TYPE_SEL_Pos            PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1397 #define PERI_DIV_CMD_PA_TYPE_SEL_Msk            PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1398 #define PERI_DIV_CMD_DISABLE_Pos                PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1399 #define PERI_DIV_CMD_DISABLE_Msk                PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1400 #define PERI_DIV_CMD_ENABLE_Pos                 PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1401 #define PERI_DIV_CMD_ENABLE_Msk                 PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1402 
1403 /* PERI_PCLK_GR.CLOCK_CTL */
1404 #define CY_PERI_CLOCK_CTL_DIV_SEL_Pos           PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Pos
1405 #define CY_PERI_CLOCK_CTL_DIV_SEL_Msk           PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Msk
1406 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Pos          PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos
1407 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Msk          PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Msk
1408 /* PERI.DIV_8_CTL */
1409 #define PERI_DIV_8_CTL_EN_Pos                   PERI_PCLK_GR_DIV_8_CTL_EN_Pos
1410 #define PERI_DIV_8_CTL_EN_Msk                   PERI_PCLK_GR_DIV_8_CTL_EN_Msk
1411 #define PERI_DIV_8_CTL_INT8_DIV_Pos             PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Pos
1412 #define PERI_DIV_8_CTL_INT8_DIV_Msk             PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Msk
1413 /* PERI.DIV_16_CTL */
1414 #define PERI_DIV_16_CTL_EN_Pos                  PERI_PCLK_GR_DIV_16_CTL_EN_Pos
1415 #define PERI_DIV_16_CTL_EN_Msk                  PERI_PCLK_GR_DIV_16_CTL_EN_Msk
1416 #define PERI_DIV_16_CTL_INT16_DIV_Pos           PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Pos
1417 #define PERI_DIV_16_CTL_INT16_DIV_Msk           PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Msk
1418 /* PERI.DIV_16_5_CTL */
1419 #define PERI_DIV_16_5_CTL_EN_Pos                PERI_PCLK_GR_DIV_16_5_CTL_EN_Pos
1420 #define PERI_DIV_16_5_CTL_EN_Msk                PERI_PCLK_GR_DIV_16_5_CTL_EN_Msk
1421 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos         PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Pos
1422 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk         PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Msk
1423 #define PERI_DIV_16_5_CTL_INT16_DIV_Pos         PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Pos
1424 #define PERI_DIV_16_5_CTL_INT16_DIV_Msk         PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Msk
1425 /* PERI.DIV_24_5_CTL */
1426 #define PERI_DIV_24_5_CTL_EN_Pos                PERI_PCLK_GR_DIV_24_5_CTL_EN_Pos
1427 #define PERI_DIV_24_5_CTL_EN_Msk                PERI_PCLK_GR_DIV_24_5_CTL_EN_Msk
1428 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos         PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos
1429 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk         PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Msk
1430 #define PERI_DIV_24_5_CTL_INT24_DIV_Pos         PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos
1431 #define PERI_DIV_24_5_CTL_INT24_DIV_Msk         PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Msk
1432 
1433 /*******************************************************************************
1434 *                PERI-GROUP
1435 *******************************************************************************/
1436 #define CY_PERI_GROUP_NR                        10
1437 
1438 #ifndef PERI0_BASE
1439 #define PERI0_BASE PERI_BASE
1440 #endif
1441 
1442 #ifndef PERI1_BASE
1443 #define PERI1_BASE 0U
1444 #endif
1445 
1446 
1447 #define PERI_GR_OFFSET                      (PERI1_BASE - PERI0_BASE)
1448 #define PERI_GR_REG_BASE(instNum)           ((PERI_Type*)(PERI0_BASE + ((instNum) * PERI_GR_OFFSET)))
1449 
1450 #define PERI_GR_INST_NUM_Msk                 (0x0000FF00U)
1451 #define PERI_GR_INST_NUM_Pos                 (8U)
1452 
1453 
1454 #define PERI_GR_CLOCK_CTL(instNum, grNum)   ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL
1455 #define PERI_GR_SL_CTL(instNum, grNum)      ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL
1456 #define PERI_GR_SL_CTL2(instNum, grNum)     ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL2
1457 #define PERI_GR_SL_CTL3(instNum, grNum)     ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL3
1458 
1459 
1460 /* CLK_HF* to PERI PCLK Group Mapping */
1461 #define PERI0_PCLK_GR_NUM_0_CLK_HF_NUM              (0U)
1462 #define PERI0_PCLK_GR_NUM_1_CLK_HF_NUM              (2U)
1463 
1464 /*******************************************************************************
1465 *                PERI-TR
1466 *******************************************************************************/
1467 #define PERI_TR_CMD                         (((PERI_Type*) (PERI_BASE))->TR_CMD)
1468 #define PERI_TR_GR_TR_CTL(group, trCtl)     (*(volatile uint32_t*) ((uint32_t)PERI_BASE+ (uint32_t)offsetof(PERI_Type,TR_GR) + \
1469                                             ((group) * (uint32_t)sizeof(PERI_TR_GR_Type)) + \
1470                                             ((trCtl) * (uint32_t)sizeof(uint32_t))))
1471 
1472 #if defined (CY_IP_MXPERI)
1473 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1474 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1475 #define CY_PERI_TR_CTL_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1476 #define CY_PERI_TR_CTL_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1477 #define PERI_V2_TR_CMD_OUT_SEL_Msk PERI_TR_CMD_OUT_SEL_Msk
1478 #define PERI_V2_TR_CMD_OUT_SEL_Pos PERI_TR_CMD_OUT_SEL_Pos
1479 #define PERI_V2_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1480 #define PERI_V2_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1481 #define CY_PERI_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1482 #define CY_PERI_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1483 #define CY_PERI_TR_CTL_SEL PERI_TR_GR_TR_CTL_TR_SEL
1484 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk PERI_TR_GR_TR_CTL_TR_INV_Msk
1485 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos PERI_TR_GR_TR_CTL_TR_INV_Pos
1486 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk PERI_TR_GR_TR_CTL_TR_EDGE_Msk
1487 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos PERI_TR_GR_TR_CTL_TR_EDGE_Pos
1488 #define PERI_V2_TR_CMD_TR_EDGE_Msk PERI_TR_CMD_TR_EDGE_Msk
1489 #define PERI_V2_TR_CMD_TR_EDGE_Pos PERI_TR_CMD_TR_EDGE_Pos
1490 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk
1491 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos
1492 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk
1493 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos
1494 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk
1495 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos
1496 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk
1497 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos
1498 #define CY_PERI_V1 0U
1499 #define PERI_TR_CMD_COUNT_Pos 0UL
1500 #define PERI_TR_CMD_COUNT_Msk 0UL
1501 #endif /* CY_IP_MXPERI */
1502 
1503 #define PERI_MS_PPU_PR_SL_ADDR(base)        (((PERI_MS_PPU_PR_Type *) (base))->SL_ADDR)
1504 #define PERI_MS_PPU_PR_SL_SIZE(base)        (((PERI_MS_PPU_PR_Type *) (base))->SL_SIZE)
1505 #define PERI_MS_PPU_PR_MS_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_PR_Type *)(base))->MS_ATT0))
1506 #define PERI_MS_PPU_PR_SL_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_PR_Type *)(base))->SL_ATT0))
1507 #define PERI_MS_PPU_FX_MS_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_FX_Type *)(base))->MS_ATT0))
1508 #define PERI_MS_PPU_FX_SL_ATT(base)         ((volatile uint32_t *) &(((PERI_MS_PPU_FX_Type *)(base))->SL_ATT0))
1509 
1510 
1511 /*******************************************************************************
1512 *                PROT
1513 *******************************************************************************/
1514 #define CY_PROT_BASE                        ((uint32_t)PROT_BASE)
1515 #define CY_PROT_PC_MAX                      (8UL)
1516 #define CY_PROT_BUS_MASTER_MASK             (0xFE7FUL)
1517 #define PROT_MPU_MS_CTL(mpu)                (((PROT_Type*)CY_PROT_BASE)->CYMPU[(mpu)].MS_CTL)
1518 #define PROT_MPU_MPU_STRUCT_ADDR(base)      (((PROT_MPU_MPU_STRUCT_Type *) (base))->ADDR)
1519 #define PROT_MPU_MPU_STRUCT_ATT(base)       (((PROT_MPU_MPU_STRUCT_Type *) (base))->ATT)
1520 #define PROT_SMPU_SMPU_STRUCT_ADDR0(base)   (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR0)
1521 #define PROT_SMPU_SMPU_STRUCT_ADDR1(base)   (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ADDR1)
1522 #define PROT_SMPU_SMPU_STRUCT_ATT0(base)    (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT0)
1523 #define PROT_SMPU_SMPU_STRUCT_ATT1(base)    (((PROT_SMPU_SMPU_STRUCT_Type *) (base))->ATT1)
1524 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT0(stcIdx)    (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT0)
1525 #define PROT_SMPU_SMPU_STRUCT_IDX_ATT1(stcIdx)    (((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)].ATT1)
1526 #define PROT_SMPU_SMPU_STRUCT_IDX(stcIdx)         (((PROT_SMPU_SMPU_STRUCT_Type *) &((PROT_SMPU_Type *) CY_PROT_BASE)->SMPU_STRUCT[(stcIdx)]))
1527 
1528 
1529 /*******************************************************************************
1530 *                IOSS
1531 *******************************************************************************/
1532 
1533 #define CY_GPIO_BASE                       ((uint32_t)GPIO_BASE)
1534 
1535 #define GPIO_INTR_CAUSE0                   ((GPIO)->INTR_CAUSE0)
1536 #define GPIO_INTR_CAUSE1                   ((GPIO)->INTR_CAUSE1)
1537 #define GPIO_INTR_CAUSE2                   ((GPIO)->INTR_CAUSE2)
1538 #define GPIO_INTR_CAUSE3                   ((GPIO)->INTR_CAUSE3)
1539 
1540 #define GPIO_PRT_OUT(base)                 (((GPIO_PRT_Type*)(base))->OUT)
1541 #define GPIO_PRT_OUT_CLR(base)             (((GPIO_PRT_Type*)(base))->OUT_CLR)
1542 #define GPIO_PRT_OUT_SET(base)             (((GPIO_PRT_Type*)(base))->OUT_SET)
1543 #define GPIO_PRT_OUT_INV(base)             (((GPIO_PRT_Type*)(base))->OUT_INV)
1544 #define GPIO_PRT_IN(base)                  (((GPIO_PRT_Type*)(base))->IN)
1545 #define GPIO_PRT_INTR(base)                (((GPIO_PRT_Type*)(base))->INTR)
1546 #define GPIO_PRT_INTR_MASK(base)           (((GPIO_PRT_Type*)(base))->INTR_MASK)
1547 #define GPIO_PRT_INTR_MASKED(base)         (((GPIO_PRT_Type*)(base))->INTR_MASKED)
1548 #define GPIO_PRT_INTR_SET(base)            (((GPIO_PRT_Type*)(base))->INTR_SET)
1549 #define GPIO_PRT_INTR_CFG(base)            (((GPIO_PRT_Type*)(base))->INTR_CFG)
1550 #define GPIO_PRT_CFG(base)                 (((GPIO_PRT_Type*)(base))->CFG)
1551 #define GPIO_PRT_CFG_IN(base)              (((GPIO_PRT_Type*)(base))->CFG_IN)
1552 #define GPIO_PRT_CFG_OUT(base)             (((GPIO_PRT_Type*)(base))->CFG_OUT)
1553 #define GPIO_PRT_CFG_SIO(base)             (((GPIO_PRT_Type*)(base))->CFG_SIO)
1554 #define GPIO_PRT_CFG_IN_AUTOLVL(base)      (((GPIO_PRT_Type*)(base))->CFG_IN_AUTOLVL)
1555 
1556 #define CY_HSIOM_BASE                      ((uint32_t)HSIOM_BASE)
1557 
1558 #define HSIOM_PRT_PORT_SEL0(base)          (((HSIOM_PRT_Type *)(base))->PORT_SEL0)
1559 #define HSIOM_PRT_PORT_SEL1(base)          (((HSIOM_PRT_Type *)(base))->PORT_SEL1)
1560 
1561 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl)    (((HSIOM_Type *)HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl])
1562 
1563 #define ioss_interrupts_gpio_0_IRQn         ioss_interrupts_gpio_dpslp_0_IRQn
1564 #define ioss_interrupts_gpio_1_IRQn         ioss_interrupts_gpio_dpslp_1_IRQn
1565 #define ioss_interrupts_gpio_2_IRQn         ioss_interrupts_gpio_dpslp_2_IRQn
1566 #define ioss_interrupts_gpio_3_IRQn         ioss_interrupts_gpio_dpslp_3_IRQn
1567 #define ioss_interrupts_gpio_4_IRQn         ioss_interrupts_gpio_dpslp_4_IRQn
1568 #define ioss_interrupts_gpio_5_IRQn         ioss_interrupts_gpio_dpslp_5_IRQn
1569 #define ioss_interrupts_gpio_6_IRQn         ioss_interrupts_gpio_dpslp_6_IRQn
1570 #define ioss_interrupts_gpio_7_IRQn         ioss_interrupts_gpio_dpslp_7_IRQn
1571 #define ioss_interrupts_gpio_8_IRQn         ioss_interrupts_gpio_dpslp_8_IRQn
1572 #define ioss_interrupts_gpio_9_IRQn         ioss_interrupts_gpio_dpslp_9_IRQn
1573 #define ioss_interrupts_gpio_10_IRQn        ioss_interrupts_gpio_dpslp_10_IRQn
1574 #define ioss_interrupts_gpio_11_IRQn        ioss_interrupts_gpio_dpslp_11_IRQn
1575 #define ioss_interrupts_gpio_12_IRQn        ioss_interrupts_gpio_dpslp_12_IRQn
1576 #define ioss_interrupts_gpio_13_IRQn        ioss_interrupts_gpio_dpslp_13_IRQn
1577 #define ioss_interrupts_gpio_14_IRQn        ioss_interrupts_gpio_dpslp_14_IRQn
1578 #define ioss_interrupts_gpio_15_IRQn        ioss_interrupts_gpio_dpslp_15_IRQn
1579 #define ioss_interrupts_gpio_16_IRQn        ioss_interrupts_gpio_dpslp_16_IRQn
1580 #define ioss_interrupts_gpio_17_IRQn        ioss_interrupts_gpio_dpslp_17_IRQn
1581 #define ioss_interrupts_gpio_18_IRQn        ioss_interrupts_gpio_dpslp_18_IRQn
1582 #define ioss_interrupts_gpio_19_IRQn        ioss_interrupts_gpio_dpslp_19_IRQn
1583 #define ioss_interrupts_gpio_20_IRQn        ioss_interrupts_gpio_dpslp_20_IRQn
1584 #define ioss_interrupts_gpio_21_IRQn        ioss_interrupts_gpio_dpslp_21_IRQn
1585 #define ioss_interrupts_gpio_22_IRQn        ioss_interrupts_gpio_dpslp_22_IRQn
1586 #define ioss_interrupts_gpio_23_IRQn        ioss_interrupts_gpio_dpslp_23_IRQn
1587 #define ioss_interrupts_gpio_28_IRQn        ioss_interrupts_gpio_dpslp_28_IRQn
1588 #define ioss_interrupts_gpio_29_IRQn        ioss_interrupts_gpio_dpslp_29_IRQn
1589 #define ioss_interrupts_gpio_30_IRQn        ioss_interrupts_gpio_dpslp_30_IRQn
1590 #define ioss_interrupts_gpio_31_IRQn        ioss_interrupts_gpio_dpslp_31_IRQn
1591 #define ioss_interrupts_gpio_32_IRQn        ioss_interrupts_gpio_dpslp_32_IRQn
1592 #define ioss_interrupts_gpio_24_IRQn        ioss_interrupts_gpio_act_24_IRQn
1593 #define ioss_interrupts_gpio_25_IRQn        ioss_interrupts_gpio_act_25_IRQn
1594 #define ioss_interrupts_gpio_26_IRQn        ioss_interrupts_gpio_act_26_IRQn
1595 #define ioss_interrupts_gpio_27_IRQn        ioss_interrupts_gpio_act_27_IRQn
1596 #define ioss_interrupts_gpio_33_IRQn        ioss_interrupts_gpio_act_33_IRQn
1597 #define ioss_interrupts_gpio_34_IRQn        ioss_interrupts_gpio_act_34_IRQn
1598 
1599 /*******************************************************************************
1600 *                I2S
1601 *******************************************************************************/
1602 #if (defined(AUDIOSS_I2S) || defined(AUDIOSS0_I2S_I2S))
1603 #define AUDIOSS_I2S_PRESENT
1604 #endif
1605 
1606 #define REG_I2S_CTL(base)                   (((I2S_Type*)(base))->CTL)
1607 #define REG_I2S_CMD(base)                   (((I2S_Type*)(base))->CMD)
1608 #define REG_I2S_CLOCK_CTL(base)             (((I2S_Type*)(base))->CLOCK_CTL)
1609 #define REG_I2S_TR_CTL(base)                (((I2S_Type*)(base))->TR_CTL)
1610 #define REG_I2S_TX_CTL(base)                (((I2S_Type*)(base))->TX_CTL)
1611 #define REG_I2S_TX_FIFO_CTL(base)           (((I2S_Type*)(base))->TX_FIFO_CTL)
1612 #define REG_I2S_TX_FIFO_STATUS(base)        (((I2S_Type*)(base))->TX_FIFO_STATUS)
1613 #define REG_I2S_TX_FIFO_WR(base)            (((I2S_Type*)(base))->TX_FIFO_WR)
1614 #define REG_I2S_TX_WATCHDOG(base)           (((I2S_Type*)(base))->TX_WATCHDOG)
1615 #define REG_I2S_RX_CTL(base)                (((I2S_Type*)(base))->RX_CTL)
1616 #define REG_I2S_RX_FIFO_CTL(base)           (((I2S_Type*)(base))->RX_FIFO_CTL)
1617 #define REG_I2S_RX_FIFO_STATUS(base)        (((I2S_Type*)(base))->RX_FIFO_STATUS)
1618 #define REG_I2S_RX_FIFO_RD(base)            (((I2S_Type*)(base))->RX_FIFO_RD)
1619 #define REG_I2S_RX_FIFO_RD_SILENT(base)     (((I2S_Type*)(base))->RX_FIFO_RD_SILENT)
1620 #define REG_I2S_RX_WATCHDOG(base)           (((I2S_Type*)(base))->RX_WATCHDOG)
1621 #define REG_I2S_INTR(base)                  (((I2S_Type*)(base))->INTR)
1622 #define REG_I2S_INTR_SET(base)              (((I2S_Type*)(base))->INTR_SET)
1623 #define REG_I2S_INTR_MASK(base)             (((I2S_Type*)(base))->INTR_MASK)
1624 #define REG_I2S_INTR_MASKED(base)           (((I2S_Type*)(base))->INTR_MASKED)
1625 
1626 
1627 
1628 /*******************************************************************************
1629 *                LCD
1630 *******************************************************************************/
1631 
1632 #define LCD_OCTET_NUM                       (8U) /* LCD_NUMPORTS - number of octets supporting up to 4 COMs */
1633 #define LCD_OCTET_NUM_8                     (8U) /* LCD_NUMPORTS8 - number of octets supporting up to 8 COMs */
1634 #define LCD_OCTET_NUM_16                    (0U) /* LCD_NUMPORTS16 - number of octets supporting up to 16 COMs */
1635 #define LCD_COM_NUM                         (8U) /* LCD_CHIP_TOP_COM_NR - maximum number of commons */
1636 
1637 #define LCD_ID(base)                        (((LCD_V1_Type*)(base))->ID)
1638 #define LCD_CONTROL(base)                   (((LCD_V1_Type*)(base))->CONTROL)
1639 #define LCD_DIVIDER(base)                   (((LCD_V1_Type*)(base))->DIVIDER)
1640 #define LCD_DATA0(base)                     (((LCD_V1_Type*)(base))->DATA0)
1641 #define LCD_DATA1(base)                     (((LCD_V1_Type*)(base))->DATA1)
1642 #define LCD_DATA2(base)                     (((LCD_V1_Type*)(base))->DATA2)
1643 #define LCD_DATA3(base)                     (((LCD_V1_Type*)(base))->DATA3)
1644 
1645 
1646 /*******************************************************************************
1647 *                IPC
1648 *******************************************************************************/
1649 
1650 #define CY_IPC_V1                              (0x20u > cy_device->ipcVersion) /* true if the IPC version is 1.x */
1651 
1652 #define REG_IPC_STRUCT_ACQUIRE(base)           (((IPC_STRUCT_Type*)(base))->ACQUIRE)
1653 #define REG_IPC_STRUCT_RELEASE(base)           (((IPC_STRUCT_Type*)(base))->RELEASE)
1654 #define REG_IPC_STRUCT_NOTIFY(base)            (((IPC_STRUCT_Type*)(base))->NOTIFY)
1655 #define REG_IPC_STRUCT_DATA(base)              (((IPC_STRUCT_Type*)(base))->DATA0)
1656 #define REG_IPC_STRUCT_DATA1(base)             (((IPC_STRUCT_Type*)(base))->DATA1)
1657 #define REG_IPC_STRUCT_LOCK_STATUS(base)       (*(volatile uint32_t*)((uint32_t)(base) + (uint32_t)offsetof(IPC_STRUCT_Type, LOCK_STATUS)))
1658 
1659 #define REG_IPC_INTR_STRUCT_INTR(base)         (((IPC_INTR_STRUCT_Type*)(base))->INTR)
1660 #define REG_IPC_INTR_STRUCT_INTR_SET(base)     (((IPC_INTR_STRUCT_Type*)(base))->INTR_SET)
1661 #define REG_IPC_INTR_STRUCT_INTR_MASK(base)    (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASK)
1662 #define REG_IPC_INTR_STRUCT_INTR_MASKED(base)  (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASKED)
1663 
1664 #define CY_IPC_STRUCT_PTR_FOR_IP(ipcIndex, base)            ((IPC_STRUCT_Type*)((uint32_t)(base) + (sizeof(IPC_STRUCT_Type) * (ipcIndex))))
1665 #define CY_IPC_INTR_STRUCT_PTR_FOR_IP(ipcIntrIndex, base)   (&(((IPC_Type *)(base))->INTR_STRUCT[ipcIntrIndex]))
1666 
1667 #define CY_IPC_INSTANCES                       (1U)
1668 #define CY_IPC_CHANNELS                        CPUSS_IPC_IPC_NR
1669 #define CY_IPC_CHANNELS_PER_INSTANCE           CPUSS_IPC_IPC_NR
1670 #define CY_IPC_INTERRUPTS                      CPUSS_IPC_IPC_IRQ_NR
1671 #define CY_IPC_INTERRUPTS_PER_INSTANCE         CPUSS_IPC_IPC_IRQ_NR
1672 #define CY_IPC_IP0_CH                          CPUSS_IPC_IPC_NR
1673 #define CY_IPC_IP0_INT                         CPUSS_IPC_IPC_IRQ_NR
1674 
1675 extern const uint32_t IPC_CHANNELS_NR[CY_IPC_INSTANCES];
1676 extern const uint32_t IPC_IRQ_NR[CY_IPC_INSTANCES];
1677 extern const uint32_t IPC_BASE_PTR[CY_IPC_INSTANCES];
1678 
1679 #define CY_IPC_STRUCT_PTR(ipcIndex)                            CY_IPC_STRUCT_PTR_FOR_IP(((ipcIndex)%CY_IPC_CHANNELS_PER_INSTANCE), IPC_BASE_PTR[(ipcIndex-((ipcIndex)%CY_IPC_CHANNELS_PER_INSTANCE))/CY_IPC_CHANNELS_PER_INSTANCE])
1680 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex)                   CY_IPC_INTR_STRUCT_PTR_FOR_IP(((ipcIntrIndex)%CY_IPC_INTERRUPTS_PER_INSTANCE), IPC_BASE_PTR[(ipcIntrIndex-((ipcIntrIndex)%CY_IPC_INTERRUPTS_PER_INSTANCE))/CY_IPC_INTERRUPTS_PER_INSTANCE])
1681 /* ipcChannel comprises of total number of channels present in all IPC IP instances */
1682 #define CY_IPC_PIPE_CHANNEL_NUMBER_WITHIN_INSTANCE(ipcChannel) (((ipcChannel)%CY_IPC_CHANNELS_PER_INSTANCE))
1683 #define CY_IPC_PIPE_INTR_NUMBER_WITHIN_INSTANCE(ipcIntr)       (((ipcIntr)%CY_IPC_INTERRUPTS_PER_INSTANCE))
1684 
1685 /* IPC channel definitions  */
1686 #define CY_IPC_CHAN_SYSCALL_CM0             (0UL)  /* System calls for the CM0 processor */
1687 #define CY_IPC_CHAN_SYSCALL_CM7_0           (1UL)  /* System calls for the CM7_0 processor */
1688 #if (CPUSS_CM7_1_PRESENT == 1)
1689 #define CY_IPC_CHAN_SYSCALL_CM7_1           (2UL)  /* System calls for the CM7_1 processor */
1690 #define CY_IPC_CHAN_SYSCALL_DAP             (3UL) /* System calls for the DAP */
1691 #define CY_IPC_CHAN_SEMA                    (4UL) /* IPC data channel for the Semaphores */
1692 #else
1693 #define CY_IPC_CHAN_SYSCALL_CM7_1           (CY_IPC_CHANNELS)  /* This macro should not be used. This is defined only for compilation purpose */
1694 #define CY_IPC_CHAN_SYSCALL_DAP             (2UL) /* System calls for the DAP */
1695 #define CY_IPC_CHAN_SEMA                    (3UL) /* IPC data channel for the Semaphores */
1696 #endif
1697 #define CY_IPC_CHAN_USER                    (CY_IPC_CHAN_SEMA + 1UL)
1698 
1699 /* IPC Notify interrupts definitions */
1700 #define CY_IPC_INTR_SYSCALL1                (0UL)
1701 #define CY_IPC_INTR_USER                    (CY_IPC_INTR_SYSCALL1 + 1UL)
1702 
1703 
1704 /*******************************************************************************
1705 *                CTB
1706 *******************************************************************************/
1707 
1708 #define CTBM_CTB_CTRL(base)                 (((CTBM_V1_Type *) (base))->CTB_CTRL)
1709 #define CTBM_CTB_SW_DS_CTRL(base)           (((CTBM_V1_Type *) (base))->CTB_SW_DS_CTRL)
1710 #define CTBM_CTB_SW_SQ_CTRL(base)           (((CTBM_V1_Type *) (base))->CTB_SW_SQ_CTRL)
1711 #define CTBM_CTD_SW(base)                   (((CTBM_V1_Type *) (base))->CTD_SW)
1712 #define CTBM_CTD_SW_CLEAR(base)             (((CTBM_V1_Type *) (base))->CTD_SW_CLEAR)
1713 #define CTBM_COMP_STAT(base)                (((CTBM_V1_Type *) (base))->COMP_STAT)
1714 #define CTBM_OA0_SW_CLEAR(base)             (((CTBM_V1_Type *) (base))->OA0_SW_CLEAR)
1715 #define CTBM_OA1_SW_CLEAR(base)             (((CTBM_V1_Type *) (base))->OA1_SW_CLEAR)
1716 #define CTBM_OA0_SW(base)                   (((CTBM_V1_Type *) (base))->OA0_SW)
1717 #define CTBM_OA1_SW(base)                   (((CTBM_V1_Type *) (base))->OA1_SW)
1718 #define CTBM_OA_RES0_CTRL(base)             (((CTBM_V1_Type *) (base))->OA_RES0_CTRL)
1719 #define CTBM_OA_RES1_CTRL(base)             (((CTBM_V1_Type *) (base))->OA_RES1_CTRL)
1720 #define CTBM_OA0_COMP_TRIM(base)            (((CTBM_V1_Type *) (base))->OA0_COMP_TRIM)
1721 #define CTBM_OA1_COMP_TRIM(base)            (((CTBM_V1_Type *) (base))->OA1_COMP_TRIM)
1722 #define CTBM_OA0_OFFSET_TRIM(base)          (((CTBM_V1_Type *) (base))->OA0_OFFSET_TRIM)
1723 #define CTBM_OA1_OFFSET_TRIM(base)          (((CTBM_V1_Type *) (base))->OA1_OFFSET_TRIM)
1724 #define CTBM_OA0_SLOPE_OFFSET_TRIM(base)    (((CTBM_V1_Type *) (base))->OA0_SLOPE_OFFSET_TRIM)
1725 #define CTBM_OA1_SLOPE_OFFSET_TRIM(base)    (((CTBM_V1_Type *) (base))->OA1_SLOPE_OFFSET_TRIM)
1726 #define CTBM_INTR(base)                     (((CTBM_V1_Type *) (base))->INTR)
1727 #define CTBM_INTR_SET(base)                 (((CTBM_V1_Type *) (base))->INTR_SET)
1728 #define CTBM_INTR_MASK(base)                (((CTBM_V1_Type *) (base))->INTR_MASK)
1729 #define CTBM_INTR_MASKED(base)              (((CTBM_V1_Type *) (base))->INTR_MASKED)
1730 
1731 
1732 /*******************************************************************************
1733 *                CTDAC
1734 *******************************************************************************/
1735 
1736 #define CTDAC_CTDAC_CTRL(base)              (((CTDAC_V1_Type *) (base))->CTDAC_CTRL)
1737 #define CTDAC_CTDAC_SW(base)                (((CTDAC_V1_Type *) (base))->CTDAC_SW)
1738 #define CTDAC_CTDAC_SW_CLEAR(base)          (((CTDAC_V1_Type *) (base))->CTDAC_SW_CLEAR)
1739 #define CTDAC_CTDAC_VAL(base)               (((CTDAC_V1_Type *) (base))->CTDAC_VAL)
1740 #define CTDAC_CTDAC_VAL_NXT(base)           (((CTDAC_V1_Type *) (base))->CTDAC_VAL_NXT)
1741 #define CTDAC_INTR(base)                    (((CTDAC_V1_Type *) (base))->INTR)
1742 #define CTDAC_INTR_SET(base)                (((CTDAC_V1_Type *) (base))->INTR_SET)
1743 #define CTDAC_INTR_MASK(base)               (((CTDAC_V1_Type *) (base))->INTR_MASK)
1744 #define CTDAC_INTR_MASKED(base)             (((CTDAC_V1_Type *) (base))->INTR_MASKED)
1745 
1746 
1747 /*******************************************************************************
1748 *                SYSANALOG
1749 *******************************************************************************/
1750 
1751 #define CY_PASS_V1                          (0x20U > cy_device->passVersion)
1752 #define CY_PASS_ADDR                        ((PASS_Type*)cy_device->passBase)
1753 #define CY_PASS_V2_ADDR                     ((PASS_V2_Type*)cy_device->passBase)
1754 #define CY_PASS_BASE(sarBase)               ((NULL != (sarBase)) ? ((PASS_V2_Type*) cy_device->passBase) : NULL) /* temporary solution for single pass instance */
1755 
1756 #define PASS_AREF_AREF_CTRL                 (((PASS_V1_Type*) CY_PASS_ADDR)->AREF.AREF_CTRL)
1757 #define PASS_INTR_CAUSE(passBase)           (((PASS_V1_Type*) (passBase))->INTR_CAUSE)
1758 #define PASS_CTBM_CLOCK_SEL(passBase)       (((PASS_V2_Type*) (passBase))->CTBM_CLOCK_SEL)
1759 #define PASS_DPSLP_CLOCK_SEL(passBase)      (((PASS_V2_Type*) (passBase))->DPSLP_CLOCK_SEL)
1760 #define PASS_LPOSC_CTRL(passBase)           (((PASS_V2_Type*) (passBase))->LPOSC.CTRL)
1761 #define PASS_LPOSC_CONFIG(passBase)         (((PASS_V2_Type*) (passBase))->LPOSC.CONFIG)
1762 #define PASS_TIMER_CTRL(passBase)           (((PASS_V2_Type*) (passBase))->TIMER.CTRL)
1763 #define PASS_TIMER_CONFIG(passBase)         (((PASS_V2_Type*) (passBase))->TIMER.CONFIG)
1764 #define PASS_TIMER_PERIOD(passBase)         (((PASS_V2_Type*) (passBase))->TIMER.PERIOD)
1765 
1766 #define PASS_SAR_SIMULT_CTRL(passBase)      (((PASS_V2_Type*) (passBase))->SAR_SIMULT_CTRL)
1767 #define PASS_SAR_TR_SCAN_CNT(passBase)      (((PASS_V2_Type*) (passBase))->SAR_TR_SCAN_CNT)
1768 #define PASS_SAR_OVR_CTRL(passBase)         (((PASS_V2_Type*) (passBase))->SAR_OVR_CTRL)
1769 #define PASS_SAR_SIMULT_FW_START_CTRL(passBase) (((PASS_V2_Type*) (passBase))->SAR_SIMULT_FW_START_CTRL)
1770 #define PASS_ANA_PWR_CFG(passBase)          (((PASS_V2_Type*) (passBase))->ANA_PWR_CFG)
1771 #define PASS_SAR_TR_OUT_CTRL(passBase)      (((PASS_V2_Type*) (passBase))->SAR_TR_OUT_CTRL)
1772 
1773 #define PASS_SAR_DPSLP_CTRL(sarBase)        (((PASS_V2_Type*) cy_device->passBase)->SAR_DPSLP_CTRL[CY_SAR_INSTANCE(sarBase)])
1774 #define PASS_SAR_CLOCK_SEL(sarBase)         (((PASS_V2_Type*) cy_device->passBase)->SAR_CLOCK_SEL[CY_SAR_INSTANCE(sarBase)])
1775 
1776 #define PASS_FIFO_BASE(sarBase)             ((PASS_FIFO_V2_Type*)&(((PASS_V2_Type*)cy_device->passBase)->FIFO[CY_SAR_INSTANCE(sarBase)]))
1777 #define PASS_FIFO_CTRL(sarBase)             (PASS_FIFO_BASE(sarBase)->CTRL)
1778 #define PASS_FIFO_CONFIG(sarBase)           (PASS_FIFO_BASE(sarBase)->CONFIG)
1779 #define PASS_FIFO_LEVEL(sarBase)            (PASS_FIFO_BASE(sarBase)->LEVEL)
1780 #define PASS_FIFO_USED(sarBase)             (PASS_FIFO_BASE(sarBase)->USED)
1781 #define PASS_FIFO_RD_DATA(sarBase)          (PASS_FIFO_BASE(sarBase)->RD_DATA)
1782 #define PASS_FIFO_INTR(sarBase)             (PASS_FIFO_BASE(sarBase)->INTR)
1783 #define PASS_FIFO_INTR_SET(sarBase)         (PASS_FIFO_BASE(sarBase)->INTR_SET)
1784 #define PASS_FIFO_INTR_MASK(sarBase)        (PASS_FIFO_BASE(sarBase)->INTR_MASK)
1785 #define PASS_FIFO_INTR_MASKED(sarBase)      (PASS_FIFO_BASE(sarBase)->INTR_MASKED)
1786 
1787 /*******************************************************************************
1788 *                SCB
1789 *******************************************************************************/
1790 
1791 #define SCB_CTRL(base)                      (((CySCB_Type*) (base))->CTRL)
1792 #define SCB_SPI_CTRL(base)                  (((CySCB_Type*) (base))->SPI_CTRL)
1793 #define SCB_SPI_STATUS(base)                (((CySCB_Type*) (base))->SPI_STATUS)
1794 #define SCB_SPI_TX_CTRL(base)               (((CySCB_Type*) (base))->SPI_TX_CTRL)
1795 #define SCB_SPI_RX_CTRL(base)               (((CySCB_Type*) (base))->SPI_RX_CTRL)
1796 #define SCB_UART_CTRL(base)                 (((CySCB_Type*) (base))->UART_CTRL)
1797 #define SCB_UART_TX_CTRL(base)              (((CySCB_Type*) (base))->UART_TX_CTRL)
1798 #define SCB_UART_RX_CTRL(base)              (((CySCB_Type*) (base))->UART_RX_CTRL)
1799 #define SCB_UART_FLOW_CTRL(base)            (((CySCB_Type*) (base))->UART_FLOW_CTRL)
1800 #define SCB_I2C_CTRL(base)                  (((CySCB_Type*) (base))->I2C_CTRL)
1801 #define SCB_I2C_STATUS(base)                (((CySCB_Type*) (base))->I2C_STATUS)
1802 #define SCB_I2C_M_CMD(base)                 (((CySCB_Type*) (base))->I2C_M_CMD)
1803 #define SCB_I2C_S_CMD(base)                 (((CySCB_Type*) (base))->I2C_S_CMD)
1804 #define SCB_I2C_CFG(base)                   (((CySCB_Type*) (base))->I2C_CFG)
1805 #define SCB_TX_CTRL(base)                   (((CySCB_Type*) (base))->TX_CTRL)
1806 #define SCB_TX_FIFO_CTRL(base)              (((CySCB_Type*) (base))->TX_FIFO_CTRL)
1807 #define SCB_TX_FIFO_STATUS(base)            (((CySCB_Type*) (base))->TX_FIFO_STATUS)
1808 #define SCB_TX_FIFO_WR(base)                (((CySCB_Type*) (base))->TX_FIFO_WR)
1809 #define SCB_RX_CTRL(base)                   (((CySCB_Type*) (base))->RX_CTRL)
1810 #define SCB_RX_FIFO_CTRL(base)              (((CySCB_Type*) (base))->RX_FIFO_CTRL)
1811 #define SCB_RX_FIFO_STATUS(base)            (((CySCB_Type*) (base))->RX_FIFO_STATUS)
1812 #define SCB_RX_MATCH(base)                  (((CySCB_Type*) (base))->RX_MATCH)
1813 #define SCB_RX_FIFO_RD(base)                (((CySCB_Type*) (base))->RX_FIFO_RD)
1814 #define SCB_INTR_CAUSE(base)                (((CySCB_Type*) (base))->INTR_CAUSE)
1815 #define SCB_INTR_I2C_EC(base)               (((CySCB_Type*) (base))->INTR_I2C_EC)
1816 #define SCB_INTR_I2C_EC_MASK(base)          (((CySCB_Type*) (base))->INTR_I2C_EC_MASK)
1817 #define SCB_INTR_I2C_EC_MASKED(base)        (((CySCB_Type*) (base))->INTR_I2C_EC_MASKED)
1818 #define SCB_INTR_SPI_EC(base)               (((CySCB_Type*) (base))->INTR_SPI_EC)
1819 #define SCB_INTR_SPI_EC_MASK(base)          (((CySCB_Type*) (base))->INTR_SPI_EC_MASK)
1820 #define SCB_INTR_SPI_EC_MASKED(base)        (((CySCB_Type*) (base))->INTR_SPI_EC_MASKED)
1821 #define SCB_INTR_M(base)                    (((CySCB_Type*) (base))->INTR_M)
1822 #define SCB_INTR_M_SET(base)                (((CySCB_Type*) (base))->INTR_M_SET)
1823 #define SCB_INTR_M_MASK(base)               (((CySCB_Type*) (base))->INTR_M_MASK)
1824 #define SCB_INTR_M_MASKED(base)             (((CySCB_Type*) (base))->INTR_M_MASKED)
1825 #define SCB_INTR_S(base)                    (((CySCB_Type*) (base))->INTR_S)
1826 #define SCB_INTR_S_SET(base)                (((CySCB_Type*) (base))->INTR_S_SET)
1827 #define SCB_INTR_S_MASK(base)               (((CySCB_Type*) (base))->INTR_S_MASK)
1828 #define SCB_INTR_S_MASKED(base)             (((CySCB_Type*) (base))->INTR_S_MASKED)
1829 #define SCB_INTR_TX(base)                   (((CySCB_Type*) (base))->INTR_TX)
1830 #define SCB_INTR_TX_SET(base)               (((CySCB_Type*) (base))->INTR_TX_SET)
1831 #define SCB_INTR_TX_MASK(base)              (((CySCB_Type*) (base))->INTR_TX_MASK)
1832 #define SCB_INTR_TX_MASKED(base)            (((CySCB_Type*) (base))->INTR_TX_MASKED)
1833 #define SCB_INTR_RX(base)                   (((CySCB_Type*) (base))->INTR_RX)
1834 #define SCB_INTR_RX_SET(base)               (((CySCB_Type*) (base))->INTR_RX_SET)
1835 #define SCB_INTR_RX_MASK(base)              (((CySCB_Type*) (base))->INTR_RX_MASK)
1836 #define SCB_INTR_RX_MASKED(base)            (((CySCB_Type*) (base))->INTR_RX_MASKED)
1837 
1838 
1839 /*******************************************************************************
1840 *                PROFILE
1841 *******************************************************************************/
1842 
1843 #define CY_EP_MONITOR_COUNT                 ((uint32_t)(cy_device->epMonitorNr))
1844 #define CY_EP_CNT_NR                        (8UL)
1845 #define PROFILE_CTL                         (((PROFILE_V1_Type*) PROFILE_BASE)->CTL)
1846 #define PROFILE_STATUS                      (((PROFILE_V1_Type*) PROFILE_BASE)->STATUS)
1847 #define PROFILE_CMD                         (((PROFILE_V1_Type*) PROFILE_BASE)->CMD)
1848 #define PROFILE_INTR                        (((PROFILE_V1_Type*) PROFILE_BASE)->INTR)
1849 #define PROFILE_INTR_MASK                   (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASK)
1850 #define PROFILE_INTR_MASKED                 (((PROFILE_V1_Type*) PROFILE_BASE)->INTR_MASKED)
1851 #define PROFILE_CNT_STRUCT                  (((PROFILE_V1_Type*) PROFILE_BASE)->CNT_STRUCT)
1852 
1853 /******************************************************************************
1854 *                MXETH
1855 *******************************************************************************/
1856 #define ETH_CTL(base)                       (((ETH_Type*)(base))->CTL)
1857 #define ETH_TX_Q_PTR(base)                  (((ETH_Type*)(base))->TRANSMIT_Q_PTR)
1858 #define ETH_TX_Q1_PTR(base)                 (((ETH_Type*)(base))->TRANSMIT_Q1_PTR)
1859 #define ETH_TX_Q2_PTR(base)                 (((ETH_Type*)(base))->TRANSMIT_Q2_PTR)
1860 #define ETH_RX_Q_PTR(base)                  (((ETH_Type*)(base))->RECEIVE_Q_PTR)
1861 #define ETH_RX_Q1_PTR(base)                 (((ETH_Type*)(base))->RECEIVE_Q1_PTR)
1862 #define ETH_RX_Q2_PTR(base)                 (((ETH_Type*)(base))->RECEIVE_Q2_PTR)
1863 
1864 /*******************************************************************************
1865 *                BLE
1866 *******************************************************************************/
1867 
1868 #define BLE_RCB_INTR                        (((BLE_V1_Type *) BLE_BASE)->RCB.INTR)
1869 #define BLE_RCB_TX_FIFO_WR                  (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR)
1870 #define BLE_RCB_RX_FIFO_RD                  (((BLE_V1_Type *) BLE_BASE)->RCB.RX_FIFO_RD)
1871 #define BLE_RCB_CTRL                        (((BLE_V1_Type *) BLE_BASE)->RCB.CTRL)
1872 #define BLE_RCB_RCBLL_CTRL                  (((BLE_V1_Type *) BLE_BASE)->RCB.RCBLL.CTRL)
1873 #define BLE_BLESS_XTAL_CLK_DIV_CONFIG       (((BLE_V1_Type *) BLE_BASE)->BLESS.XTAL_CLK_DIV_CONFIG)
1874 #define BLE_BLESS_MT_CFG                    (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_CFG)
1875 #define BLE_BLESS_MT_STATUS                 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_STATUS)
1876 #define BLE_BLESS_MT_DELAY_CFG              (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG)
1877 #define BLE_BLESS_MT_DELAY_CFG2             (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG2)
1878 #define BLE_BLESS_MT_DELAY_CFG3             (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG3)
1879 #define BLE_BLESS_MT_VIO_CTRL               (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_VIO_CTRL)
1880 #define BLE_BLESS_LL_CLK_EN                 (((BLE_V1_Type *) BLE_BASE)->BLESS.LL_CLK_EN)
1881 #define BLE_BLESS_MISC_EN_CTRL              (((BLE_V1_Type *) BLE_BASE)->BLESS.MISC_EN_CTRL)
1882 #define BLE_BLESS_INTR_STAT                 (((BLE_V1_Type *) BLE_BASE)->BLESS.INTR_STAT)
1883 #define BLE_BLELL_EVENT_INTR                (((BLE_V1_Type *) BLE_BASE)->BLELL.EVENT_INTR)
1884 #define BLE_BLELL_CONN_INTR                 (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_INTR)
1885 #define BLE_BLELL_CONN_EXT_INTR             (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_EXT_INTR)
1886 #define BLE_BLELL_SCAN_INTR                 (((BLE_V1_Type *) BLE_BASE)->BLELL.SCAN_INTR)
1887 #define BLE_BLELL_ADV_INTR                  (((BLE_V1_Type *) BLE_BASE)->BLELL.ADV_INTR)
1888 
1889 
1890 /*******************************************************************************
1891 *                USBFS Device
1892 *******************************************************************************/
1893 
1894 #define USBFS_DEV_CR0(base)             (((USBFS_V1_Type *)(base))->USBDEV.CR0)
1895 #define USBFS_DEV_CR1(base)             (((USBFS_V1_Type *)(base))->USBDEV.CR1)
1896 #define USBFS_DEV_USBIO_CR0(base)       (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR0)
1897 #define USBFS_DEV_USBIO_CR2(base)       (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR2)
1898 #define USBFS_DEV_USBIO_CR1(base)       (((USBFS_V1_Type *)(base))->USBDEV.USBIO_CR1)
1899 #define USBFS_DEV_USB_CLK_EN(base)      (((USBFS_V1_Type *)(base))->USBDEV.USB_CLK_EN)
1900 #define USBFS_DEV_BUS_RST_CNT(base)     (((USBFS_V1_Type *)(base))->USBDEV.BUS_RST_CNT)
1901 #define USBFS_DEV_OSCLK_DR0(base)       (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE)
1902 #define USBFS_DEV_OSCLK_DR1(base)       (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR0)
1903 #define USBFS_DEV_SOF0(base)            (((USBFS_V1_Type *)(base))->USBDEV.SOF0)
1904 #define USBFS_DEV_SOF1(base)            (((USBFS_V1_Type *)(base))->USBDEV.SOF1)
1905 #define USBFS_DEV_SOF16(base)           (((USBFS_V1_Type *)(base))->USBDEV.OSCLK_DR1)
1906 #define USBFS_DEV_OSCLK_DR16(base)      (((USBFS_V1_Type *)(base))->USBDEV.SOF16)
1907 #define USBFS_DEV_ARB_CFG(base)         (((USBFS_V1_Type *)(base))->USBDEV.ARB_CFG)
1908 #define USBFS_DEV_DYN_RECONFIG(base)    (((USBFS_V1_Type *)(base))->USBDEV.DYN_RECONFIG)
1909 #define USBFS_DEV_BUF_SIZE(base)        (((USBFS_V1_Type *)(base))->USBDEV.BUF_SIZE)
1910 #define USBFS_DEV_EP_ACTIVE(base)       (((USBFS_V1_Type *)(base))->USBDEV.EP_ACTIVE)
1911 #define USBFS_DEV_EP_TYPE(base)         (((USBFS_V1_Type *)(base))->USBDEV.EP_TYPE)
1912 #define USBFS_DEV_CWA16(base)           (((USBFS_V1_Type *)(base))->USBDEV.CWA16)
1913 #define USBFS_DEV_CWA(base)             (((USBFS_V1_Type *)(base))->USBDEV.CWA)
1914 #define USBFS_DEV_CWA_MSB(base)         (((USBFS_V1_Type *)(base))->USBDEV.CWA_MSB)
1915 #define USBFS_DEV_DMA_THRES16(base)     (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES16)
1916 #define USBFS_DEV_DMA_THRES(base)       (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES)
1917 #define USBFS_DEV_DMA_THRES_MSB(base)   (((USBFS_V1_Type *)(base))->USBDEV.DMA_THRES_MSB)
1918 
1919 #define USBFS_DEV_SIE_EP_INT_EN(base)   (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_EN)
1920 #define USBFS_DEV_SIE_EP_INT_SR(base)   (((USBFS_V1_Type *)(base))->USBDEV.SIE_EP_INT_SR)
1921 #define USBFS_DEV_ARB_INT_EN(base)      (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_EN)
1922 #define USBFS_DEV_ARB_INT_SR(base)      (((USBFS_V1_Type *)(base))->USBDEV.ARB_INT_SR)
1923 
1924 #define USBFS_DEV_EP0_CR(base)          (((USBFS_V1_Type *)(base))->USBDEV.EP0_CR)
1925 #define USBFS_DEV_EP0_CNT(base)         (((USBFS_V1_Type *)(base))->USBDEV.EP0_CNT)
1926 #define USBFS_DEV_EP0_DR(base, idx)     (((USBFS_V1_Type *)(base))->USBDEV.EP0_DR[idx])
1927 
1928 #define USBFS_DEV_MEM_DATA(base, idx)   (((USBFS_V1_Type *)(base))->USBDEV.MEM[idx])
1929 
1930 #define USBFS_DEV_SIE_REGS_BASE        (0x30U)
1931 #define USBFS_DEV_SIE_REGS_SIZE        (0x40U)
1932 #define USBFS_DEV_SIE_EP_CNT0_OFFSET   (0x00U)
1933 #define USBFS_DEV_SIE_EP_CNT1_OFFSET   (0x04U)
1934 #define USBFS_DEV_SIE_EP_CR0_OFFSET    (0x08U)
1935 #define USBFS_DEV_SIE_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_SIE_REGS_BASE + ((endpoint) * USBFS_DEV_SIE_REGS_SIZE))
1936 
1937 #define USBFS_DEV_SIE_EP_CNT0(base, endpoint)  (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
1938                                                                         USBFS_DEV_SIE_EP_CNT0_OFFSET))
1939 #define USBFS_DEV_SIE_EP_CNT1(base, endpoint)  (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
1940                                                                         USBFS_DEV_SIE_EP_CNT1_OFFSET))
1941 #define USBFS_DEV_SIE_EP_CR0(base, endpoint)   (*(volatile uint32_t *) (USBFS_DEV_SIE_REGS(base, endpoint) + \
1942                                                                         USBFS_DEV_SIE_EP_CR0_OFFSET))
1943 
1944 #define USBFS_DEV_ARB_REGS_BASE         (0x200U)
1945 #define USBFS_DEV_ARB_REGS_SIZE         (0x40U)
1946 #define USBFS_DEV_ARB_EP_CFG_OFFSET     (0x00U)
1947 #define USBFS_DEV_ARB_EP_INT_EN_OFFSET  (0x04U)
1948 #define USBFS_DEV_ARB_EP_SR_OFFSET      (0x08U)
1949 #define USBFS_DEV_ARB_RW_WA_OFFSET      (0x10U)
1950 #define USBFS_DEV_ARB_RW_WA_MSB_OFFSET  (0x14U)
1951 #define USBFS_DEV_ARB_RW_RA_OFFSET      (0x18U)
1952 #define USBFS_DEV_ARB_RW_RA_MSB_OFFSET  (0x1CU)
1953 #define USBFS_DEV_ARB_RW_DR_OFFSET      (0x20U)
1954 #define USBFS_DEV_ARB_REGS(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS_BASE + ((endpoint) * USBFS_DEV_ARB_REGS_SIZE))
1955 
1956 #define USBFS_DEV_ARB_EP_CFG(base, endpoint)       (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1957                                                                             USBFS_DEV_ARB_EP_CFG_OFFSET))
1958 #define USBFS_DEV_ARB_EP_INT_EN(base, endpoint)    (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1959                                                                             USBFS_DEV_ARB_EP_INT_EN_OFFSET))
1960 #define USBFS_DEV_ARB_EP_SR(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1961                                                                             USBFS_DEV_ARB_EP_SR_OFFSET))
1962 #define USBFS_DEV_ARB_RW_WA(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1963                                                                             USBFS_DEV_ARB_RW_WA_OFFSET))
1964 #define USBFS_DEV_ARB_RW_WA_MSB(base, endpoint)    (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1965                                                                             USBFS_DEV_ARB_RW_WA_MSB_OFFSET))
1966 #define USBFS_DEV_ARB_RW_RA(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1967                                                                             USBFS_DEV_ARB_RW_RA_OFFSET))
1968 #define USBFS_DEV_ARB_RW_RA_MSB(base, endpoint)    (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1969                                                                             USBFS_DEV_ARB_RW_RA_MSB_OFFSET))
1970 #define USBFS_DEV_ARB_RW_DR(base, endpoint)        (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS(base, endpoint) + \
1971                                                                             USBFS_DEV_ARB_RW_DR_OFFSET))
1972 
1973 #define USBFS_DEV_ARB_REGS16_BASE       (0x1210U)
1974 #define USBFS_DEV_ARB_REGS16_SIZE       (0x40U)
1975 #define USBFS_DEV_ARB_RW_WA16_OFFSET    (0x00U)
1976 #define USBFS_DEV_ARB_RW_RA16_OFFSET    (0x08U)
1977 #define USBFS_DEV_ARB_RW_DR16_OFFSET    (0x10U)
1978 #define USBFS_DEV_ARB_REGS_16(base, endpoint) ((uint32_t)(base) + USBFS_DEV_ARB_REGS16_BASE + ((endpoint) * USBFS_DEV_ARB_REGS16_SIZE))
1979 
1980 #define USBFS_DEV_ARB_RW_WA16(base, endpoint)      (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
1981                                                                             USBFS_DEV_ARB_RW_WA16_OFFSET))
1982 #define USBFS_DEV_ARB_RW_RA16(base, endpoint)      (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
1983                                                                             USBFS_DEV_ARB_RW_RA16_OFFSET))
1984 #define USBFS_DEV_ARB_RW_DR16(base, endpoint)      (*(volatile uint32_t *) (USBFS_DEV_ARB_REGS_16(base, endpoint) + \
1985                                                                             USBFS_DEV_ARB_RW_DR16_OFFSET))
1986 
1987 #define USBFS_DEV_LPM_POWER_CTL(base)       (((USBFS_V1_Type *)(base))->USBLPM.POWER_CTL)
1988 #define USBFS_DEV_LPM_USBIO_CTL(base)       (((USBFS_V1_Type *)(base))->USBLPM.USBIO_CTL)
1989 #define USBFS_DEV_LPM_FLOW_CTL(base)        (((USBFS_V1_Type *)(base))->USBLPM.FLOW_CTL)
1990 #define USBFS_DEV_LPM_LPM_CTL(base)         (((USBFS_V1_Type *)(base))->USBLPM.LPM_CTL)
1991 #define USBFS_DEV_LPM_LPM_STAT(base)        (((USBFS_V1_Type const *)(base))->USBLPM.LPM_STAT)
1992 #define USBFS_DEV_LPM_INTR_SIE(base)        (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE)
1993 #define USBFS_DEV_LPM_INTR_SIE_SET(base)    (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_SET)
1994 #define USBFS_DEV_LPM_INTR_SIE_MASK(base)   (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASK)
1995 #define USBFS_DEV_LPM_INTR_SIE_MASKED(base) (((USBFS_V1_Type *)(base))->USBLPM.INTR_SIE_MASKED)
1996 #define USBFS_DEV_LPM_INTR_LVL_SEL(base)    (((USBFS_V1_Type *)(base))->USBLPM.INTR_LVL_SEL)
1997 #define USBFS_DEV_LPM_INTR_CAUSE_HI(base)   (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_HI)
1998 #define USBFS_DEV_LPM_INTR_CAUSE_MED(base)  (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_MED)
1999 #define USBFS_DEV_LPM_INTR_CAUSE_LO(base)   (((USBFS_V1_Type const *)(base))->USBLPM.INTR_CAUSE_LO)
2000 #define USBFS_DEV_LPM_DFT_CTL(base)         (((USBFS_V1_Type *)(base))->USBLPM.DFT_CTL)
2001 
2002 #define USBFS_HOST_CTL0(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL0)
2003 #define USBFS_HOST_CTL1(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL1)
2004 #define USBFS_HOST_CTL2(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_CTL2)
2005 #define USBFS_HOST_ERR(base)                (((USBFS_V1_Type *)(base))->USBHOST.HOST_ERR)
2006 #define USBFS_HOST_STATUS(base)             (((USBFS_V1_Type *)(base))->USBHOST.HOST_STATUS)
2007 #define USBFS_HOST_FCOMP(base)              (((USBFS_V1_Type *)(base))->USBHOST.HOST_FCOMP)
2008 #define USBFS_HOST_RTIMER(base)             (((USBFS_V1_Type *)(base))->USBHOST.HOST_RTIMER)
2009 #define USBFS_HOST_ADDR(base)               (((USBFS_V1_Type *)(base))->USBHOST.HOST_ADDR)
2010 #define USBFS_HOST_EOF(base)                (((USBFS_V1_Type *)(base))->USBHOST.HOST_EOF)
2011 #define USBFS_HOST_FRAME(base)              (((USBFS_V1_Type *)(base))->USBHOST.HOST_FRAME)
2012 #define USBFS_HOST_TOKEN(base)              (((USBFS_V1_Type *)(base))->USBHOST.HOST_TOKEN)
2013 #define USBFS_HOST_EP1_CTL(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_CTL)
2014 #define USBFS_HOST_EP1_STATUS(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_STATUS)
2015 #define USBFS_HOST_EP1_RW1_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW1_DR)
2016 #define USBFS_HOST_EP1_RW2_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_RW2_DR)
2017 #define USBFS_HOST_EP2_CTL(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_CTL)
2018 #define USBFS_HOST_EP2_STATUS(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_STATUS)
2019 #define USBFS_HOST_EP2_RW1_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW1_DR)
2020 #define USBFS_HOST_EP2_RW2_DR(base)         (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_RW2_DR)
2021 #define USBFS_HOST_LVL1_SEL(base)           (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL1_SEL)
2022 #define USBFS_HOST_LVL2_SEL(base)           (((USBFS_V1_Type *)(base))->USBHOST.HOST_LVL2_SEL)
2023 #define USBFS_INTR_USBHOST_CAUSE_HI(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_HI)
2024 #define USBFS_INTR_USBHOST_CAUSE_MED(base)  (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_MED)
2025 #define USBFS_INTR_USBHOST_CAUSE_LO(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_CAUSE_LO)
2026 #define USBFS_INTR_HOST_EP_CAUSE_HI(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_HI)
2027 #define USBFS_INTR_HOST_EP_CAUSE_MED(base)  (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_MED)
2028 #define USBFS_INTR_HOST_EP_CAUSE_LO(base)   (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_CAUSE_LO)
2029 #define USBFS_INTR_USBHOST(base)            (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST)
2030 #define USBFS_INTR_USBHOST_SET(base)        (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_SET)
2031 #define USBFS_INTR_USBHOST_MASK(base)       (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASK)
2032 #define USBFS_INTR_USBHOST_MASKED(base)     (((USBFS_V1_Type *)(base))->USBHOST.INTR_USBHOST_MASKED)
2033 #define USBFS_INTR_HOST_EP(base)            (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP)
2034 #define USBFS_INTR_HOST_EP_SET(base)        (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_SET)
2035 #define USBFS_INTR_HOST_EP_MASK(base)       (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASK)
2036 #define USBFS_INTR_HOST_EP_MASKED(base)     (((USBFS_V1_Type *)(base))->USBHOST.INTR_HOST_EP_MASKED)
2037 #define USBFS_HOST_DMA_ENBL(base)           (((USBFS_V1_Type *)(base))->USBHOST.HOST_DMA_ENBL)
2038 #define USBFS_HOST_EP1_BLK(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP1_BLK)
2039 #define USBFS_HOST_EP2_BLK(base)            (((USBFS_V1_Type *)(base))->USBHOST.HOST_EP2_BLK)
2040 
2041 
2042 /*******************************************************************************
2043 *                LIN
2044 *******************************************************************************/
2045 #if defined (CY_IP_MXLIN)
2046 #define LIN0_CH1                                ((LIN_CH_Type*) &LIN0->CH[1])
2047 #define LIN0_CH2                                ((LIN_CH_Type*) &LIN0->CH[2])
2048 #define LIN0_CH3                                ((LIN_CH_Type*) &LIN0->CH[3])
2049 #define LIN0_CH4                                ((LIN_CH_Type*) &LIN0->CH[4])
2050 #define LIN0_CH5                                ((LIN_CH_Type*) &LIN0->CH[5])
2051 #define LIN0_CH6                                ((LIN_CH_Type*) &LIN0->CH[6])
2052 #define LIN0_CH7                                ((LIN_CH_Type*) &LIN0->CH[7])
2053 #define LIN0_CH8                                ((LIN_CH_Type*) &LIN0->CH[8])
2054 #define LIN0_CH9                                ((LIN_CH_Type*) &LIN0->CH[9])
2055 #define LIN0_CH10                               ((LIN_CH_Type*) &LIN0->CH[10])
2056 #define LIN0_CH11                               ((LIN_CH_Type*) &LIN0->CH[11])
2057 #define LIN0_CH12                               ((LIN_CH_Type*) &LIN0->CH[12])
2058 #define LIN0_CH13                               ((LIN_CH_Type*) &LIN0->CH[13])
2059 #define LIN0_CH14                               ((LIN_CH_Type*) &LIN0->CH[14])
2060 #define LIN0_CH15                               ((LIN_CH_Type*) &LIN0->CH[15])
2061 #define LIN0_CH16                               ((LIN_CH_Type*) &LIN0->CH[16])
2062 #define LIN0_CH17                               ((LIN_CH_Type*) &LIN0->CH[17])
2063 #define LIN0_CH18                               ((LIN_CH_Type*) &LIN0->CH[18])
2064 #define LIN0_CH19                               ((LIN_CH_Type*) &LIN0->CH[19])
2065 #define LIN0_CH20                               ((LIN_CH_Type*) &LIN0->CH[20])
2066 #define LIN0_CH21                               ((LIN_CH_Type*) &LIN0->CH[21])
2067 #define LIN0_CH22                               ((LIN_CH_Type*) &LIN0->CH[22])
2068 #define LIN0_CH23                               ((LIN_CH_Type*) &LIN0->CH[23])
2069 #define LIN0_CH24                               ((LIN_CH_Type*) &LIN0->CH[24])
2070 #define LIN0_CH25                               ((LIN_CH_Type*) &LIN0->CH[25])
2071 #define LIN0_CH26                               ((LIN_CH_Type*) &LIN0->CH[26])
2072 #define LIN0_CH27                               ((LIN_CH_Type*) &LIN0->CH[27])
2073 #define LIN0_CH28                               ((LIN_CH_Type*) &LIN0->CH[28])
2074 #define LIN0_CH29                               ((LIN_CH_Type*) &LIN0->CH[29])
2075 #define LIN0_CH30                               ((LIN_CH_Type*) &LIN0->CH[30])
2076 #define LIN0_CH31                               ((LIN_CH_Type*) &LIN0->CH[31])
2077 
2078 #define LIN_CH_CTL0(base)                       (((LIN_CH_Type *)(base))->CTL0)
2079 #define LIN_CH_CTL1(base)                       (((LIN_CH_Type *)(base))->CTL1)
2080 #define LIN_CH_STATUS(base)                     (((LIN_CH_Type *)(base))->STATUS)
2081 #define LIN_CH_CMD(base)                        (((LIN_CH_Type *)(base))->CMD)
2082 #define LIN_CH_TX_RX_STATUS(base)               (((LIN_CH_Type *)(base))->TX_RX_STATUS)
2083 #define LIN_CH_PID_CHECKSUM(base)               (((LIN_CH_Type *)(base))->PID_CHECKSUM)
2084 #define LIN_CH_DATA0(base)                      (((LIN_CH_Type *)(base))->DATA0)
2085 #define LIN_CH_DATA1(base)                      (((LIN_CH_Type *)(base))->DATA1)
2086 #define LIN_CH_INTR(base)                       (((LIN_CH_Type *)(base))->INTR)
2087 #define LIN_CH_INTR_SET(base)                   (((LIN_CH_Type *)(base))->INTR_SET)
2088 #define LIN_CH_INTR_MASK(base)                  (((LIN_CH_Type *)(base))->INTR_MASK)
2089 #define LIN_CH_INTR_MASKED(base)                (((LIN_CH_Type *)(base))->INTR_MASKED)
2090 
2091 #define LIN_ERROR_CTL(base)                     (((LIN_Type *)(base))->ERROR_CTL)
2092 #define LIN_TEST_CTL(base)                      (((LIN_Type *)(base))->TEST_CTL)
2093 #endif /* CY_IP_MXLIN */
2094 
2095 /*******************************************************************************
2096 *                SAR ADC
2097 *******************************************************************************/
2098 /** Channel TR_CTL register access macro. */
2099 #define SAR2_CH_TR_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].TR_CTL)
2100 
2101 /** Channel SAMPLE_CTL register access macro. */
2102 #define SAR2_CH_SAMPLE_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].SAMPLE_CTL)
2103 
2104 /** Channel POST_CTL register access macro. */
2105 #define SAR2_CH_POST_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].POST_CTL)
2106 
2107 /** Channel RANGE_CTL register access macro. */
2108 #define SAR2_CH_RANGE_CTL(base, channel) (((PASS_SAR_Type *)base)->CH[channel].RANGE_CTL)
2109 
2110 /** Channel INTR register access macro. */
2111 #define SAR2_CH_INTR(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR)
2112 
2113 /** Channel INTR_SET register access macro. */
2114 #define SAR2_CH_INTR_SET(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_SET)
2115 
2116 /** Channel INTR_MASK register access macro. */
2117 #define SAR2_CH_INTR_MASK(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_MASK)
2118 
2119 /** Channel INTR_MASKED register access macro. */
2120 #define SAR2_CH_INTR_MASKED(base, channel) (((PASS_SAR_Type *)base)->CH[channel].INTR_MASKED)
2121 
2122 /** Channel WORK register access macro. */
2123 #define SAR2_CH_WORK(base, channel) (((PASS_SAR_Type *)base)->CH[channel].WORK)
2124 
2125 /** Channel WORK register access macro. */
2126 #define SAR2_CH_RESULT(base, channel) (((PASS_SAR_Type *)base)->CH[channel].WORK)
2127 
2128 /** Channel GRP_STAT register access macro. */
2129 #define SAR2_CH_GRP_STAT(base, channel) (((PASS_SAR_Type *)base)->CH[channel].GRP_STAT)
2130 
2131 /** Channel ENABLE register access macro. */
2132 #define SAR2_CH_ENABLE(base, channel) (((PASS_SAR_Type *)base)->CH[channel].ENABLE)
2133 
2134 /** Channel TR_CMD register access macro. */
2135 #define SAR2_CH_TR_CMD(base, channel) (((PASS_SAR_Type *)base)->CH[channel].TR_CMD)
2136 
2137 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
2138 #endif /* CY_DEVICE_H_ */
2139 
2140 /* [] END OF FILE */
2141