1 /* 2 * Copyright 2020-2023, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ 9 10 #define MCUX_FLEXCOMM0_CLK 0 11 #define MCUX_FLEXCOMM1_CLK 1 12 #define MCUX_FLEXCOMM2_CLK 2 13 #define MCUX_FLEXCOMM3_CLK 3 14 #define MCUX_FLEXCOMM4_CLK 4 15 #define MCUX_FLEXCOMM5_CLK 5 16 #define MCUX_FLEXCOMM6_CLK 6 17 #define MCUX_FLEXCOMM7_CLK 7 18 #define MCUX_FLEXCOMM8_CLK 8 19 #define MCUX_FLEXCOMM9_CLK 9 20 #define MCUX_FLEXCOMM10_CLK 10 21 #define MCUX_FLEXCOMM11_CLK 11 22 #define MCUX_FLEXCOMM12_CLK 12 23 #define MCUX_FLEXCOMM13_CLK 13 24 #define MCUX_HS_SPI_CLK 14 25 #define MCUX_PMIC_I2C_CLK 15 26 #define MCUX_HS_SPI1_CLK 16 27 28 #define MCUX_USDHC1_CLK 20 29 #define MCUX_USDHC2_CLK 21 30 31 #define MCUX_CTIMER_CLK_OFFSET 22 32 33 #define MCUX_CTIMER0_CLK 0 34 #define MCUX_CTIMER1_CLK 1 35 #define MCUX_CTIMER2_CLK 2 36 #define MCUX_CTIMER3_CLK 3 37 #define MCUX_CTIMER4_CLK 4 38 39 #define MCUX_MCAN_CLK 27 40 41 #define MCUX_BUS_CLK 28 42 43 #define MCUX_SDIF_CLK 29 44 45 #define MCUX_I3C_CLK 30 46 47 #define MCUX_MIPI_DSI_DPHY_CLK 31 48 #define MCUX_MIPI_DSI_ESC_CLK 32 49 50 #define MCUX_LCDIF_PIXEL_CLK 33 51 52 #define MCUX_SCTIMER_CLK 34 53 54 #define MCUX_DMIC_CLK 35 55 56 #define MCUX_FLEXSPI_CLK 36 57 #define MCUX_FLEXSPI2_CLK 37 58 59 #define MCUX_MRT_CLK 40 60 61 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ 62
