1 /* 2 * Copyright 2020-2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ 9 10 /* Note- clock identifiers in this file must be unique, 11 * as the driver uses them in a switch case 12 */ 13 14 #define MCUX_LPC_CLK_ID(high, low) ((high << 8) | (low)) 15 16 /* These IDs are used within SOC macros, and thus cannot be defined 17 * using the standard MCUX_LPC_CLK_ID form 18 */ 19 #define MCUX_CTIMER0_CLK 0 20 #define MCUX_CTIMER1_CLK 1 21 #define MCUX_CTIMER2_CLK 2 22 #define MCUX_CTIMER3_CLK 3 23 #define MCUX_CTIMER4_CLK 4 24 #define MCUX_CTIMER5_CLK 5 25 #define MCUX_CTIMER6_CLK 6 26 #define MCUX_CTIMER7_CLK 7 27 28 #define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00) 29 #define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01) 30 #define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02) 31 #define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03) 32 #define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04) 33 #define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05) 34 #define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06) 35 #define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07) 36 #define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08) 37 #define MCUX_FLEXCOMM9_CLK MCUX_LPC_CLK_ID(0x01, 0x09) 38 #define MCUX_FLEXCOMM10_CLK MCUX_LPC_CLK_ID(0x01, 0x0A) 39 #define MCUX_FLEXCOMM11_CLK MCUX_LPC_CLK_ID(0x01, 0x0B) 40 #define MCUX_FLEXCOMM12_CLK MCUX_LPC_CLK_ID(0x01, 0x0C) 41 #define MCUX_FLEXCOMM13_CLK MCUX_LPC_CLK_ID(0x01, 0x0D) 42 #define MCUX_HS_SPI_CLK MCUX_LPC_CLK_ID(0x01, 0x0E) 43 #define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK 44 #define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F) 45 #define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10) 46 #define MCUX_FLEXCOMM17_CLK MCUX_LPC_CLK_ID(0x01, 0x11) 47 #define MCUX_FLEXCOMM18_CLK MCUX_LPC_CLK_ID(0x01, 0x12) 48 #define MCUX_FLEXCOMM19_CLK MCUX_LPC_CLK_ID(0x01, 0x13) 49 #define MCUX_FLEXCOMM20_CLK MCUX_LPC_CLK_ID(0x01, 0x14) 50 /* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */ 51 #define MCUX_LPSPI14_CLK MCUX_LPC_CLK_ID(0x01, 0x24) 52 #define MCUX_LPI2C15_CLK MCUX_LPC_CLK_ID(0x01, 0x25) 53 #define MCUX_LPSPI16_CLK MCUX_LPC_CLK_ID(0x01, 0x26) 54 #define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) 55 #define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) 56 57 #define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00) 58 59 #define MCUX_BUS_CLK MCUX_LPC_CLK_ID(0x04, 0x00) 60 61 #define MCUX_SDIF_CLK MCUX_LPC_CLK_ID(0x05, 0x00) 62 63 #define MCUX_I3C_CLK MCUX_LPC_CLK_ID(0x06, 0x00) 64 #define MCUX_I3C2_CLK MCUX_LPC_CLK_ID(0x06, 0x01) 65 66 #define MCUX_MIPI_DSI_DPHY_CLK MCUX_LPC_CLK_ID(0x07, 0x00) 67 #define MCUX_MIPI_DSI_ESC_CLK MCUX_LPC_CLK_ID(0x07, 0x01) 68 69 #define MCUX_LCDIF_PIXEL_CLK MCUX_LPC_CLK_ID(0x08, 0x00) 70 71 #define MCUX_SCTIMER_CLK MCUX_LPC_CLK_ID(0x09, 0x00) 72 73 #define MCUX_DMIC_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) 74 75 #define MCUX_FLEXSPI_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) 76 #define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01) 77 78 #define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00) 79 #define MCUX_FREEMRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x01) 80 81 #define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00) 82 #define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01) 83 #define MCUX_PORT2_CLK MCUX_LPC_CLK_ID(0x0C, 0x02) 84 #define MCUX_PORT3_CLK MCUX_LPC_CLK_ID(0x0C, 0x03) 85 #define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04) 86 #define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05) 87 88 #define MCUX_ENET_QOS_CLK MCUX_LPC_CLK_ID(0x0D, 0x00) 89 90 #define MCUX_ENET_CLK MCUX_LPC_CLK_ID(0x0D, 0x80) 91 #define MCUX_ENET_PLL MCUX_LPC_CLK_ID(0x0D, 0x81) 92 93 #define MCUX_LCDIC_CLK MCUX_LPC_CLK_ID(0x0E, 0x00) 94 95 #define MCUX_LPADC1_CLK MCUX_LPC_CLK_ID(0x0F, 0x00) 96 #define MCUX_LPADC2_CLK MCUX_LPC_CLK_ID(0x0F, 0x01) 97 98 #define MCUX_FLEXCAN0_CLK MCUX_LPC_CLK_ID(0x10, 0x00) 99 #define MCUX_FLEXCAN1_CLK MCUX_LPC_CLK_ID(0x10, 0x01) 100 101 #define MCUX_FLEXIO0_CLK MCUX_LPC_CLK_ID(0x11, 0x00) 102 103 #define MCUX_AUDIO_MCLK MCUX_LPC_CLK_ID(0x12, 0x00) 104 105 #define MCUX_LPUART0_CLK MCUX_LPC_CLK_ID(0x13, 0x00) 106 #define MCUX_LPUART1_CLK MCUX_LPC_CLK_ID(0x13, 0x01) 107 #define MCUX_LPUART2_CLK MCUX_LPC_CLK_ID(0x13, 0x02) 108 #define MCUX_LPUART3_CLK MCUX_LPC_CLK_ID(0x13, 0x03) 109 #define MCUX_LPUART4_CLK MCUX_LPC_CLK_ID(0x13, 0x04) 110 111 #define MCUX_LPI2C0_CLK MCUX_LPC_CLK_ID(0x14, 0x00) 112 #define MCUX_LPI2C1_CLK MCUX_LPC_CLK_ID(0x14, 0x01) 113 #define MCUX_LPI2C2_CLK MCUX_LPC_CLK_ID(0x14, 0x02) 114 #define MCUX_LPI2C3_CLK MCUX_LPC_CLK_ID(0x14, 0x03) 115 116 #define MCUX_XSPI_CLK MCUX_LPC_CLK_ID(0x15, 0x00) 117 #define MCUX_XSPI0_CLK MCUX_LPC_CLK_ID(0x15, 0x00) 118 #define MCUX_XSPI1_CLK MCUX_LPC_CLK_ID(0x15, 0x01) 119 #define MCUX_XSPI2_CLK MCUX_LPC_CLK_ID(0x15, 0x02) 120 121 #define MCUX_SAI0_CLK MCUX_LPC_CLK_ID(0x16, 0x00) 122 #define MCUX_SAI1_CLK MCUX_LPC_CLK_ID(0x16, 0x01) 123 124 #define MCUX_LPSPI0_CLK MCUX_LPC_CLK_ID(0x17, 0x00) 125 #define MCUX_LPSPI1_CLK MCUX_LPC_CLK_ID(0x17, 0x01) 126 127 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ 128
