1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_ESPI_SAF_H_ 8 #define _MEC172X_ESPI_SAF_H_ 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #define MCHP_ESPI_SAF_BASE_ADDR 0x40008000u 14 #define MCHP_ESPI_SAF_COMM_BASE_ADDR 0x40071000u 15 16 /* SAF hardware supports up to 2 external SPI flash devices */ 17 #define MCHP_ESPI_SAF_CS_MAX 2 18 19 /* Three TAG Map registers */ 20 #define MCHP_ESPI_SAF_TAGMAP_MAX 3 21 /* 17 protection regions */ 22 #define MCHP_ESPI_SAF_PR_MAX 17 23 24 #define MCHP_SAF_FL_CM_PRF_CS0_OFS 0x1b0u 25 #define MCHP_SAF_FL_CM_PRF_CS1_OFS 0x1b2u 26 27 #define MCHP_ESPI_SAF_BASE 0x40008000u 28 #define MCHP_ESPI_SAF_COMM_BASE 0x40071000u 29 #define MCHP_ESPI_SAF_COMM_MODE_OFS 0x2b8u 30 #define MCHP_ESPI_SAF_COMM_MODE_ADDR (MCHP_ESPI_SAF_COMM_BASE_ADDR + \ 31 MCHP_ESPI_SAF_COMM_MODE_OFS) 32 33 /* SAF Protection region described by 4 32-bit registers. 17 regions */ 34 #define MCHP_ESPI_SAF_PROT_MAX 17u 35 36 /* Register bit definitions */ 37 38 /* SAF EC Portal Command register */ 39 #define MCHP_SAF_ECP_CMD_OFS 0x18u 40 #define MCHP_SAF_ECP_CMD_MASK 0xff00ffffu 41 #define MCHP_SAF_ECP_CMD_PUT_POS 0 42 #define MCHP_SAF_ECP_CMD_PUT_MASK 0xffu 43 #define MCHP_SAF_ECP_CMD_PUT_FLASH_NP 0x0au 44 #define MCHP_SAF_ECP_CMD_CTYPE_POS 8 45 #define MCHP_SAF_ECP_CMD_CTYPE_MSK0 0xffu 46 #define MCHP_SAF_ECP_CMD_CTYPE_MASK 0xff00u 47 #define MCHP_SAF_ECP_CMD_CTYPE_READ 0x0000u 48 #define MCHP_SAF_ECP_CMD_CTYPE_WRITE 0x0100u 49 #define MCHP_SAF_ECP_CMD_CTYPE_ERASE 0x0200u 50 #define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP1_CS0 0x0300u 51 #define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP2_CS0 0x0400u 52 #define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP1_CS1 0x8300u 53 #define MCHP_SAF_ECP_CMD_CTYPE_RPMC_OP2_CS1 0x8400u 54 #define MCHP_SAF_ECP_CMD_LEN_POS 24 55 #define MCHP_SAF_ECP_CMD_LEN_MASK0 0xffu 56 #define MCHP_SAF_ECP_CMD_LEN_MASK 0xff000000ul 57 /* Read/Write request size (1 <= reqlen <= 64) bytes */ 58 #define MCHP_SAF_ECP_CMD_RW_LEN_MIN 1u 59 #define MCHP_SAF_ECP_CMD_RW_LEN_MAX 64u 60 /* Only three erase sizes are supported encoded as */ 61 #define MCHP_SAF_ECP_CMD_ERASE_4K 0u 62 #define MCHP_SAF_ECP_CMD_ERASE_32K BIT(24) 63 #define MCHP_SAF_ECP_CMD_ERASE_64K BIT(25) 64 65 /* Zero based command values */ 66 #define MCHP_SAF_ECP_CMD_READ 0x00u 67 #define MCHP_SAF_ECP_CMD_WRITE 0x01u 68 #define MCHP_SAF_ECP_CMD_ERASE 0x02u 69 #define MCHP_SAF_ECP_CMD_RPMC_OP1_CS0 0x03u 70 #define MCHP_SAF_ECP_CMD_RPMC_OP2_CS0 0x04u 71 #define MCHP_SAF_ECP_CMD_RPMC_OP1_CS1 0x83u 72 #define MCHP_SAF_ECP_CMD_RPMC_OP2_CS1 0x84u 73 74 /* SAF EC Portal Flash Address register */ 75 #define MCHP_SAF_ECP_FLAR_OFS 0x1cu 76 #define MCHP_SAF_ECP_FLAR_MASK 0xffffffffu 77 78 /* SAF EC Portal Start register */ 79 #define MCHP_SAF_ECP_START_OFS 0x20u 80 #define MCHP_SAF_ECP_START_MASK 0x01u 81 #define MCHP_SAF_ECP_START_POS 0 82 #define MCHP_SAF_ECP_START BIT(0) 83 84 /* SAF EC Portal Buffer Address register */ 85 #define MCHP_SAF_ECP_BFAR_OFS 0x24u 86 #define MCHP_SAF_ECP_BFAR_MASK 0xfffffffcu 87 88 /* SAF EC Portal Status register */ 89 #define MCHP_SAF_ECP_STS_OFS 0x28u 90 #define MCHP_SAF_ECP_STS_MASK 0x1ffu 91 #define MCHP_SAF_ECP_STS_ERR_MASK 0x1fcu 92 #define MCHP_SAF_ECP_STS_DONE_POS 0 93 #define MCHP_SAF_ECP_STS_DONE_TST_POS 1 94 #define MCHP_SAF_ECP_STS_TMOUT_POS 2 95 #define MCHP_SAF_ECP_STS_OOR_POS 3 96 #define MCHP_SAF_ECP_STS_AV_POS 4 97 #define MCHP_SAF_ECP_STS_BND_4K_POS 5 98 #define MCHP_SAF_ECP_STS_ERSZ_POS 6 99 #define MCHP_SAF_ECP_STS_ST_OVFL_POS 7 100 #define MCHP_SAF_ECP_STS_BAD_REQ_POS 8 101 #define MCHP_SAF_ECP_STS_DONE BIT(0) 102 #define MCHP_SAF_ECP_STS_DONE_TST BIT(1) 103 #define MCHP_SAF_ECP_STS_TMOUT BIT(2) 104 #define MCHP_SAF_ECP_STS_OOR BIT(3) 105 #define MCHP_SAF_ECP_STS_AV BIT(4) 106 #define MCHP_SAF_ECP_STS_BND_4K BIT(5) 107 #define MCHP_SAF_ECP_STS_ERSZ BIT(6) 108 #define MCHP_SAF_ECP_STS_ST_OVFL BIT(7) 109 #define MCHP_SAF_ECP_STS_BAD_REQ BIT(8) 110 111 /* SAF EC Portal Interrupt Enable register */ 112 #define MCHP_SAF_ECP_INTEN_OFS 0x2cu 113 #define MCHP_SAF_ECP_INTEN_MASK 0x01u 114 #define MCHP_SAF_ECP_INTEN_DONE_POS 0 115 #define MCHP_SAF_ECP_INTEN_DONE BIT(0) 116 117 /* SAF Flash Configuration Size Limit register */ 118 #define MCHP_SAF_FL_CFG_SIZE_LIM_OFS 0x30u 119 #define MCHP_SAF_FL_CFG_SIZE_LIM_MASK 0xffffffffu 120 121 /* SAF Flash Configuration Threshold register */ 122 #define MCHP_SAF_FL_CFG_THRH_OFS 0x34u 123 #define MCHP_SAF_FL_CFG_THRH_MASK 0xffffffffu 124 125 /* SAF Flash Configuration Miscellaneous register */ 126 #define MCHP_SAF_FL_CFG_MISC_OFS 0x38u 127 #define MCHP_SAF_FL_CFG_MISC_MASK 0x000030f3u 128 #define MCHP_SAF_FL_CFG_MISC_PFOE_MASK 0x3u 129 #define MCHP_SAF_FL_CFG_MISC_PFOE_DFLT 0u 130 #define MCHP_SAF_FL_CFG_MISC_PFOE_EXP 0x3u 131 #define MCHP_SAF_FL_CFG_MISC_CS0_4BM_POS 4 132 #define MCHP_SAF_FL_CFG_MISC_CS1_4BM_POS 5 133 #define MCHP_SAF_FL_CFG_MISC_CS0_CPE_POS 6 134 #define MCHP_SAF_FL_CFG_MISC_CS1_CPE_POS 7 135 #define MCHP_SAF_FL_CFG_MISC_SAF_EN_POS 12 136 #define MCHP_SAF_FL_CFG_MISC_SAF_LOCK_POS 13 137 #define MCHP_SAF_FL_CFG_MISC_CS0_4BM BIT(4) 138 #define MCHP_SAF_FL_CFG_MISC_CS1_4BM BIT(5) 139 #define MCHP_SAF_FL_CFG_MISC_CS0_CPE BIT(6) 140 #define MCHP_SAF_FL_CFG_MISC_CS1_CPE BIT(7) 141 #define MCHP_SAF_FL_CFG_MISC_SAF_EN BIT(12) 142 #define MCHP_SAF_FL_CFG_MISC_SAF_LOCK BIT(13) 143 144 /* SAF eSPI Monitor Status and Interrupt enable registers */ 145 #define MCHP_SAF_ESPI_MON_STATUS_OFS 0x3cu 146 #define MCHP_SAF_ESPI_MON_INTEN_OFS 0x40u 147 #define MCHP_SAF_ESPI_MON_STS_IEN_MSK 0x1fu 148 #define MCHP_SAF_ESPI_MON_STS_IEN_TMOUT_POS 0 149 #define MCHP_SAF_ESPI_MON_STS_IEN_OOR_POS 1 150 #define MCHP_SAF_ESPI_MON_STS_IEN_AV_POS 2 151 #define MCHP_SAF_ESPI_MON_STS_IEN_BND_4K_POS 3 152 #define MCHP_SAF_ESPI_MON_STS_IEN_ERSZ_POS 4 153 #define MCHP_SAF_ESPI_MON_STS_IEN_TMOUT BIT(0) 154 #define MCHP_SAF_ESPI_MON_STS_IEN_OOR BIT(1) 155 #define MCHP_SAF_ESPI_MON_STS_IEN_AV BIT(2) 156 #define MCHP_SAF_ESPI_MON_STS_IEN_BND_4K BIT(3) 157 #define MCHP_SAF_ESPI_MON_STS_IEN_ERSZ BIT(4) 158 159 /* SAF EC Portal Busy register */ 160 #define MCHP_SAF_ECP_BUSY_OFS 0x44u 161 #define MCHP_SAF_ECP_BUSY_MASK 0x01u 162 #define MCHP_SAF_ECP_EC0_BUSY_POS 0 163 #define MCHP_SAF_ECP_EC1_BUSY_POS 1 164 #define MCHP_SAF_ECP_EC0_BUSY BIT(0) 165 #define MCHP_SAF_ECP_EC1_BUSY BIT(1) 166 167 /* SAF CS0/CS1 Opcode A registers */ 168 #define MCHP_SAF_CS0_OPA_OFS 0x4cu 169 #define MCHP_SAF_CS1_OPA_OFS 0x5cu 170 #define MCHP_SAF_CS_OPA_MASK 0xffffffffu 171 #define MCHP_SAF_CS_OPA_WE_POS 0 172 #define MCHP_SAF_CS_OPA_WE_MASK 0xfful 173 #define MCHP_SAF_CS_OPA_SUS_POS 8 174 #define MCHP_SAF_CS_OPA_SUS_MASK 0xff00ul 175 #define MCHP_SAF_CS_OPA_RSM_POS 16 176 #define MCHP_SAF_CS_OPA_RSM_MASK 0xff0000ul 177 #define MCHP_SAF_CS_OPA_POLL1_POS 24 178 #define MCHP_SAF_CS_OPA_POLL1_MASK 0xff000000ul 179 180 /* SAF CS0/CS1 Opcode B registers */ 181 #define MCHP_SAF_CS0_OPB_OFS 0x50u 182 #define MCHP_SAF_CS1_OPB_OFS 0x60u 183 #define MCHP_SAF_CS_OPB_OFS 0xffffffffu 184 #define MCHP_SAF_CS_OPB_ER0_POS 0 185 #define MCHP_SAF_CS_OPB_ER0_MASK 0xffu 186 #define MCHP_SAF_CS_OPB_ER1_POS 8 187 #define MCHP_SAF_CS_OPB_ER1_MASK 0xff00ul 188 #define MCHP_SAF_CS_OPB_ER2_POS 16 189 #define MCHP_SAF_CS_OPB_ER2_MASK 0xff0000ul 190 #define MCHP_SAF_CS_OPB_PGM_POS 24 191 #define MCHP_SAF_CS_OPB_PGM_MASK 0xff000000ul 192 193 /* SAF CS0/CS1 Opcode C registers */ 194 #define MCHP_SAF_CS0_OPC_OFS 0x54u 195 #define MCHP_SAF_CS1_OPC_OFS 0x64u 196 #define MCHP_SAF_CS_OPC_MASK 0xffffffffu 197 #define MCHP_SAF_CS_OPC_RD_POS 0 198 #define MCHP_SAF_CS_OPC_RD_MASK 0xffu 199 #define MCHP_SAF_CS_OPC_MNC_POS 8 200 #define MCHP_SAF_CS_OPC_MNC_MASK 0xff00ul 201 #define MCHP_SAF_CS_OPC_MC_POS 16 202 #define MCHP_SAF_CS_OPC_MC_MASK 0xff0000ul 203 #define MCHP_SAF_CS_OPC_POLL2_POS 24 204 #define MCHP_SAF_CS_OPC_POLL2_MASK 0xff000000ul 205 206 /* SAF CS0/CS1 registers */ 207 #define MCHP_SAF_CS0_DESCR_OFS 0x58u 208 #define MCHP_SAF_CS1_DESCR_OFS 0x68u 209 #define MCHP_SAF_CS_DESCR_MASK 0x0000ff0fu 210 #define MCHP_SAF_CS_DESCR_ENTC_POS 0 211 #define MCHP_SAF_CS_DESCR_ENTC_MASK 0x0fu 212 #define MCHP_SAF_CS_DESCR_RDC_POS 8 213 #define MCHP_SAF_CS_DESCR_RDC_MASK 0x0f00ul 214 #define MCHP_SAF_CS_DESCR_SZC_POS 12 215 #define MCHP_SAF_CS_DESCR_SZC_MASK 0xf000ul 216 217 /* SAF Flash Configuration General Descriptors register */ 218 #define MCHP_SAF_FL_CFG_GEN_DESCR_OFS 0x6cu 219 #define MCHP_SAF_FL_CFG_GEN_DESCR_MASK 0x0000ff0fu 220 /* value for standard 16 descriptor programming */ 221 #define MCHP_SAF_FL_CFG_GEN_DESCR_STD 0x0000ee0cu 222 #define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_POS 0 223 #define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_MASK 0x0fu 224 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS 8 225 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_MASK \ 226 SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS) 227 228 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS 12 229 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_MASK \ 230 SHLU32(0x0Fu, MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS) 231 232 /* SAF Protection Lock register */ 233 #define MCHP_SAF_PROT_LOCK_OFS 0x70u 234 #define MCHP_SAF_PROT_LOCK_MASK 0x1ffffu 235 #define MCHP_SAF_PROT_LOCK0 BIT(0) 236 #define MCHP_SAF_PROT_LOCK1 BIT(1) 237 #define MCHP_SAF_PROT_LOCK2 BIT(2) 238 #define MCHP_SAF_PROT_LOCK3 BIT(3) 239 #define MCHP_SAF_PROT_LOCK4 BIT(4) 240 #define MCHP_SAF_PROT_LOCK5 BIT(5) 241 #define MCHP_SAF_PROT_LOCK6 BIT(6) 242 #define MCHP_SAF_PROT_LOCK7 BIT(7) 243 #define MCHP_SAF_PROT_LOCK8 BIT(8) 244 #define MCHP_SAF_PROT_LOCK9 BIT(9) 245 #define MCHP_SAF_PROT_LOCK10 BIT(10) 246 #define MCHP_SAF_PROT_LOCK11 BIT(11) 247 #define MCHP_SAF_PROT_LOCK12 BIT(12) 248 #define MCHP_SAF_PROT_LOCK13 BIT(13) 249 #define MCHP_SAF_PROT_LOCK14 BIT(14) 250 #define MCHP_SAF_PROT_LOCK15 BIT(15) 251 #define MCHP_SAF_PROT_LOCK16 BIT(16) 252 253 /* SAF Protection Dirty register */ 254 #define MCHP_SAF_PROT_DIRTY_OFS 0x74u 255 #define MCHP_SAF_PROT_DIRTY_MASK 0xfffu 256 #define MCHP_SAF_PROT_DIRTY0 BIT(0) 257 #define MCHP_SAF_PROT_DIRTY1 BIT(1) 258 #define MCHP_SAF_PROT_DIRTY2 BIT(2) 259 #define MCHP_SAF_PROT_DIRTY3 BIT(3) 260 #define MCHP_SAF_PROT_DIRTY4 BIT(4) 261 #define MCHP_SAF_PROT_DIRTY5 BIT(5) 262 #define MCHP_SAF_PROT_DIRTY6 BIT(6) 263 #define MCHP_SAF_PROT_DIRTY7 BIT(7) 264 #define MCHP_SAF_PROT_DIRTY8 BIT(8) 265 #define MCHP_SAF_PROT_DIRTY9 BIT(9) 266 #define MCHP_SAF_PROT_DIRTY10 BIT(10) 267 #define MCHP_SAF_PROT_DIRTY11 BIT(11) 268 269 /* SAF Tag Map 0 register */ 270 #define MCHP_SAF_TAG_MAP0_OFS 0x78u 271 #define MCHP_SAF_TAG_MAP0_MASK 0x77777777u 272 #define MCHP_SAF_TAG_MAP0_DFLT_VAL 0x23221100u 273 #define MCHP_SAF_TAG_MAP0_STM0_POS 0 274 #define MCHP_SAF_TAG_MAP0_STM0_MASK 0x07u 275 #define MCHP_SAF_TAG_MAP0_STM1_POS 4 276 #define MCHP_SAF_TAG_MAP0_STM1_MASK \ 277 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP0_STM1_POS) 278 #define MCHP_SAF_TAG_MAP0_STM2_POS 8 279 #define MCHP_SAF_TAG_MAP0_STM2_MASK \ 280 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM2_POS) 281 #define MCHP_SAF_TAG_MAP0_STM3_POS 12 282 #define MCHP_SAF_TAG_MAP0_STM3_MASK \ 283 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM3_POS) 284 #define MCHP_SAF_TAG_MAP0_STM4_POS 16 285 #define MCHP_SAF_TAG_MAP0_STM4_MASK \ 286 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM4_POS) 287 #define MCHP_SAF_TAG_MAP0_STM5_POS 20 288 #define MCHP_SAF_TAG_MAP0_STM5_MASK \ 289 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM5_POS) 290 #define MCHP_SAF_TAG_MAP0_STM6_POS 24 291 #define MCHP_SAF_TAG_MAP0_STM6_MASK \ 292 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM6_POS) 293 #define MCHP_SAF_TAG_MAP0_STM7_POS 28 294 #define MCHP_SAF_TAG_MAP0_STM7_MASK \ 295 SHLU32(MCHP_SAF_TAG_MAP0_STM0_MASK, MCHP_SAF_TAG_MAP1_STM7_POS) 296 297 /* SAF Tag Map 1 register */ 298 #define MCHP_SAF_TAG_MAP1_OFS 0x7Cu 299 #define MCHP_SAF_TAG_MAP1_MASK 0x77777777u 300 #define MCHP_SAF_TAG_MAP1_DFLT_VAL 0x77677767u 301 #define MCHP_SAF_TAG_MAP1_STM8_POS 0 302 #define MCHP_SAF_TAG_MAP1_STM8_MASK 0x07u 303 #define MCHP_SAF_TAG_MAP1_STM9_POS 4 304 #define MCHP_SAF_TAG_MAP1_STM9_MASK \ 305 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STM9_POS) 306 #define MCHP_SAF_TAG_MAP1_STMA_POS 8 307 #define MCHP_SAF_TAG_MAP1_STMA_MASK \ 308 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMA_POS) 309 #define MCHP_SAF_TAG_MAP1_STMB_POS 12 310 #define MCHP_SAF_TAG_MAP1_STMB_MASK \ 311 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMB_POS) 312 #define MCHP_SAF_TAG_MAP1_STMC_POS 16 313 #define MCHP_SAF_TAG_MAP1_STMC_MASK \ 314 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMC_POS) 315 #define MCHP_SAF_TAG_MAP1_STMD_POS 20 316 #define MCHP_SAF_TAG_MAP1_STMD_MASK \ 317 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMD_POS) 318 #define MCHP_SAF_TAG_MAP1_STME_POS 24 319 #define MCHP_SAF_TAG_MAP1_STME_MASK \ 320 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STME_POS) 321 #define MCHP_SAF_TAG_MAP1_STMF_POS 28 322 #define MCHP_SAF_TAG_MAP1_STMF_MASK \ 323 SHLU32(MCHP_SAF_TAG_MAP1_STM8_MASK, MCHP_SAF_TAG_MAP1_STMF_POS) 324 325 /* SAF Tag Map 2 register */ 326 #define MCHP_SAF_TAG_MAP2_OFS 0x80u 327 #define MCHP_SAF_TAG_MAP2_MASK 0x80000007u 328 #define MCHP_SAF_TAG_MAP2_DFLT_VAL 0x00000005u 329 #define MCHP_SAF_TAG_MAP2_SM_EC_POS 0 330 #define MCHP_SAF_TAG_MAP2_SM_EC_MASK 0x07u 331 #define MCHP_SAF_TAG_MAP2_LOCK_POS 31 332 #define MCHP_SAF_TAG_MAP2_LOCK BIT(MCHP_SAF_TAG_MAP2_LOCK_POS) 333 334 /* SAF Protection Region Start registers */ 335 #define MCHP_SAF_PROT_RG0_START_OFS 0x84u 336 #define MCHP_SAF_PROT_RG1_START_OFS 0x94u 337 #define MCHP_SAF_PROT_RG2_START_OFS 0xA4u 338 #define MCHP_SAF_PROT_RG3_START_OFS 0xB4u 339 #define MCHP_SAF_PROT_RG4_START_OFS 0xC4u 340 #define MCHP_SAF_PROT_RG5_START_OFS 0xD4u 341 #define MCHP_SAF_PROT_RG6_START_OFS 0xE4u 342 #define MCHP_SAF_PROT_RG7_START_OFS 0xF4u 343 #define MCHP_SAF_PROT_RG8_START_OFS 0x104u 344 #define MCHP_SAF_PROT_RG9_START_OFS 0x114u 345 #define MCHP_SAF_PROT_RG10_START_OFS 0x124u 346 #define MCHP_SAF_PROT_RG11_START_OFS 0x134u 347 #define MCHP_SAF_PROT_RG12_START_OFS 0x144u 348 #define MCHP_SAF_PROT_RG13_START_OFS 0x154u 349 #define MCHP_SAF_PROT_RG14_START_OFS 0x164u 350 #define MCHP_SAF_PROT_RG15_START_OFS 0x174u 351 #define MCHP_SAF_PROT_RG16_START_OFS 0x184u 352 #define MCHP_SAF_PROT_RG_START_MASK 0xfffffu 353 #define MCHP_SAF_PROT_RG_START_DFLT 0x07fffu 354 355 /* SAF Protection Region Limit registers */ 356 #define MCHP_SAF_PROT_RG0_LIMIT_OFS 0x88u 357 #define MCHP_SAF_PROT_RG1_LIMIT_OFS 0x98u 358 #define MCHP_SAF_PROT_RG2_LIMIT_OFS 0xa8u 359 #define MCHP_SAF_PROT_RG3_LIMIT_OFS 0xb8u 360 #define MCHP_SAF_PROT_RG4_LIMIT_OFS 0xc8u 361 #define MCHP_SAF_PROT_RG5_LIMIT_OFS 0xd8u 362 #define MCHP_SAF_PROT_RG6_LIMIT_OFS 0xe8u 363 #define MCHP_SAF_PROT_RG7_LIMIT_OFS 0xf8u 364 #define MCHP_SAF_PROT_RG8_LIMIT_OFS 0x108u 365 #define MCHP_SAF_PROT_RG9_LIMIT_OFS 0x118u 366 #define MCHP_SAF_PROT_RG10_LIMIT_OFS 0x128u 367 #define MCHP_SAF_PROT_RG11_LIMIT_OFS 0x138u 368 #define MCHP_SAF_PROT_RG12_LIMIT_OFS 0x148u 369 #define MCHP_SAF_PROT_RG13_LIMIT_OFS 0x158u 370 #define MCHP_SAF_PROT_RG14_LIMIT_OFS 0x168u 371 #define MCHP_SAF_PROT_RG15_LIMIT_OFS 0x178u 372 #define MCHP_SAF_PROT_RG16_LIMIT_OFS 0x188u 373 #define MCHP_SAF_PROT_RG_LIMIT_MASK 0xfffffu 374 #define MCHP_SAF_PROT_RG_LIMIT_DFLT 0 375 376 /* SAF Protection Region Write Bitmap registers */ 377 #define MCHP_SAF_PROT_RG0_WBM_OFS 0x8cu 378 #define MCHP_SAF_PROT_RG1_WBM_OFS 0x9cu 379 #define MCHP_SAF_PROT_RG2_WBM_OFS 0xacu 380 #define MCHP_SAF_PROT_RG3_WBM_OFS 0xbcu 381 #define MCHP_SAF_PROT_RG4_WBM_OFS 0xccu 382 #define MCHP_SAF_PROT_RG5_WBM_OFS 0xdcu 383 #define MCHP_SAF_PROT_RG6_WBM_OFS 0xefu 384 #define MCHP_SAF_PROT_RG7_WBM_OFS 0xfcu 385 #define MCHP_SAF_PROT_RG8_WBM_OFS 0x10cu 386 #define MCHP_SAF_PROT_RG9_WBM_OFS 0x11cu 387 #define MCHP_SAF_PROT_RG10_WBM_OFS 0x12cu 388 #define MCHP_SAF_PROT_RG11_WBM_OFS 0x13cu 389 #define MCHP_SAF_PROT_RG12_WBM_OFS 0x14cu 390 #define MCHP_SAF_PROT_RG13_WBM_OFS 0x15cu 391 #define MCHP_SAF_PROT_RG14_WBM_OFS 0x16cu 392 #define MCHP_SAF_PROT_RG15_WBM_OFS 0x17cu 393 #define MCHP_SAF_PROT_RG16_WBM_OFS 0x18cu 394 #define MCHP_SAF_PROT_RG_WBM_MASK 0xffu 395 #define MCHP_SAF_PROT_RG_WBM0 BIT(0) 396 #define MCHP_SAF_PROT_RG_WBM1 BIT(1) 397 #define MCHP_SAF_PROT_RG_WBM2 BIT(2) 398 #define MCHP_SAF_PROT_RG_WBM3 BIT(3) 399 #define MCHP_SAF_PROT_RG_WBM4 BIT(4) 400 #define MCHP_SAF_PROT_RG_WBM5 BIT(5) 401 #define MCHP_SAF_PROT_RG_WBM6 BIT(6) 402 #define MCHP_SAF_PROT_RG_WBM7 BIT(7) 403 404 /* SAF Protection Region Read Bitmap registers */ 405 #define MCHP_SAF_PROT_RG0_RBM_OFS 0x90u 406 #define MCHP_SAF_PROT_RG1_RBM_OFS 0xa0u 407 #define MCHP_SAF_PROT_RG2_RBM_OFS 0xb0u 408 #define MCHP_SAF_PROT_RG3_RBM_OFS 0xc0u 409 #define MCHP_SAF_PROT_RG4_RBM_OFS 0xd0u 410 #define MCHP_SAF_PROT_RG5_RBM_OFS 0xe0u 411 #define MCHP_SAF_PROT_RG6_RBM_OFS 0xf0u 412 #define MCHP_SAF_PROT_RG7_RBM_OFS 0x100u 413 #define MCHP_SAF_PROT_RG8_RBM_OFS 0x110u 414 #define MCHP_SAF_PROT_RG9_RBM_OFS 0x120u 415 #define MCHP_SAF_PROT_RG10_RBM_OFS 0x130u 416 #define MCHP_SAF_PROT_RG11_RBM_OFS 0x140u 417 #define MCHP_SAF_PROT_RG12_RBM_OFS 0x150u 418 #define MCHP_SAF_PROT_RG13_RBM_OFS 0x160u 419 #define MCHP_SAF_PROT_RG14_RBM_OFS 0x170u 420 #define MCHP_SAF_PROT_RG15_RBM_OFS 0x180u 421 #define MCHP_SAF_PROT_RG16_RBM_OFS 0x190u 422 #define MCHP_SAF_PROT_RG_RBM_MASK 0xffu 423 #define MCHP_SAF_PROT_RG_RBM0 BIT(0) 424 #define MCHP_SAF_PROT_RG_RBM1 BIT(1) 425 #define MCHP_SAF_PROT_RG_RBM2 BIT(2) 426 #define MCHP_SAF_PROT_RG_RBM3 BIT(3) 427 #define MCHP_SAF_PROT_RG_RBM4 BIT(4) 428 #define MCHP_SAF_PROT_RG_RBM5 BIT(5) 429 #define MCHP_SAF_PROT_RG_RBM6 BIT(6) 430 #define MCHP_SAF_PROT_RG_RBM7 BIT(7) 431 432 /* SAF Poll Timeout register */ 433 #define MCHP_SAF_POLL_TMOUT_OFS 0x194u 434 #define MCHP_SAF_POLL_TMOUT_MASK 0x3ffffu 435 #define MCHP_SAF_POLL_TMOUT_5S 0x28000u 436 437 /* SAF Poll Interval register */ 438 #define MCHP_SAF_POLL_INTRVL_OFS 0x198u 439 #define MCHP_SAF_POLL_INTRVL_MASK 0xffffu 440 441 /* SAF Suspend Resume Interval register */ 442 #define MCHP_SAF_SUS_RSM_INTRVL_OFS 0x19Cu 443 #define MCHP_SAF_SUS_RSM_INTRVL_MASK 0xffffu 444 445 /* SAF Consecutive Read Timeout register */ 446 #define MCHP_SAF_CRD_TMOUT_OFS 0x1a0u 447 #define MCHP_SAF_CRD_TMOUT_MASK 0xfffffu 448 449 /* SAF Flash CS0/CS1 Configuration Poll2 Mask registers */ 450 #define MCHP_SAF_FL0_CFG_P2M_OFS 0x1a4u 451 #define MCHP_SAF_FL1_CFG_P2M_OFS 0x1a6u 452 #define MCHP_SAF_FL_CFG_P2M_MASK 0xffffu 453 454 /* SAF Flash Configuration Special Mode register */ 455 #define MCHP_SAF_FL_CFG_SPM_OFS 0x1a8u 456 #define MCHP_SAF_FL_CFG_SPM_MASK 0x01u 457 #define MCHP_SAF_FL_CFG_SPM_DIS_SUSP BIT(0) 458 459 /* SAF Suspend Check Delay register */ 460 #define MCHP_SAF_SUS_CHK_DLY_OFS 0x1acu 461 #define MCHP_SAF_SUS_CHK_DLY_MASK 0xfffffu 462 463 /* SAF Flash 0/1 Continuous Mode Prefix registers */ 464 #define MCHP_SAF_FL_CM_PRF_OFS 0x1b0u 465 #define MCHP_SAF_FL_CM_PRF_MASK 0xffffu 466 #define MCHP_SAF_FL_CM_PRF_CS_OP_POS 0 467 #define MCHP_SAF_FL_CM_PRF_CS_OP_MASK 0xffu 468 #define MCHP_SAF_FL_CM_PRF_CS_DAT_POS 8 469 #define MCHP_SAF_FL_CM_PRF_CS_DAT_MASK \ 470 SHLU32(MCHP_SAF_FL_CM_PRF_CS_OP_MASK, MCHP_SAF_FL_CM_PRF_CS_DAT_POS) 471 472 /* SAF DnX Protection Bypass register */ 473 #define MCHP_SAF_DNX_PROT_BYP_OFS 0x1b4u 474 #define MCHP_SAF_DNX_PROT_BYP_MASK 0x1110ffffu 475 #define MCHP_SAF_DNX_PB_TAG_POS(n) ((uint32_t)(n) & 0xfu) 476 #define MCHP_SAF_DNX_PB_TAG(n) BIT(((n) & 0xfu)) 477 #define MCHP_SAF_DNX_DS_RO_POS 20 478 #define MCHP_SAF_DNX_DS_RO BIT(20) 479 #define MCHP_SAF_DNX_DM_POS 24 480 #define MCHP_SAF_DNX_DM BIT(24) 481 #define MCHP_SAF_DNX_LK_POS 28 482 #define MCHP_SAF_DNX_LK BIT(28) 483 484 /* SAF Activity Count Reload Valud register */ 485 #define MCHP_SAF_AC_RELOAD_OFS 0x1b8u 486 #define MCHP_SAF_AC_RELOAD_REG_MSK 0xffffu 487 488 /* SAF Power Down Control register */ 489 #define SAF_PWRDN_CTRL_OFS 0x1bcu 490 #define SAF_PWRDN_CTRL_REG_MSK 0x0fu 491 #define SAF_PWRDN_CTRL_CS0_PD_EN_POS 0 492 #define SAF_PWRDN_CTRL_CS1_PD_EN_POS 1 493 #define SAF_PWRDN_CTRL_CS0_WPA_EN_POS 2 494 #define SAF_PWRDN_CTRL_CS1_WPA_EN_POS 3 495 496 /* SAF Memory Power Status register (RO) */ 497 #define SAF_MEM_PWR_STS_OFS 0x1c0u 498 #define SAF_MEM_PWR_STS_REG_MSK 0x03u 499 500 /* SAF Config CS0 and CS1 Opcode registers */ 501 #define SAF_CFG_CS0_OPC_OFS 0x1c4u 502 #define SAF_CFG_CS1_OPC_OFS 0x1c8u 503 #define SAF_CFG_CS_OPC_REG_MSK 0x00ffffffu 504 #define SAF_CFG_CS_OPC_ENTER_PD_POS 0 505 #define SAF_CFG_CS_OPC_ENTER_PD_MSK0 0xffu 506 #define SAF_CFG_CS_OPC_ENTER_PD_MSK 0xffu 507 #define SAF_CFG_CS_OPC_EXIT_PD_POS 8 508 #define SAF_CFG_CS_OPC_EXIT_PD_MSK0 0xffu 509 #define SAF_CFG_CS_OPC_EXIT_PD_MSK 0xff00u 510 #define SAF_CFG_CS_OPC_RPMC_OP2_POS 16 511 #define SAF_CFG_CS_OPC_RPMC_OP2_MSK0 0xffu 512 #define SAF_CFG_CS_OPC_RPMC_OP2_MSK 0xff0000u 513 514 515 /* SAF Flash Power Down/Up Timerout register */ 516 #define SAF_FL_PWR_TMOUT_OFS 0x1ccu 517 #define SAF_FL_PWR_TMOUT_REG_MSK 0xffffu 518 519 /* SAF Clock Divider CS0 and CS1 registers */ 520 #define SAF_CLKDIV_CS0_OFS 0x200u 521 #define SAF_CLKDIV_CS1_OFS 0x204u 522 #define SAF_CLKDIV_CS_REG_MSK 0xffffffffu 523 #define SAF_CLKDIV_CS_READ_POS 0 524 #define SAF_CLKDIV_CS_REST_POS 16 525 #define SAF_CLKDIV_CS_MSK0 0xffffu 526 527 /* SAF RPMC OP2 eSPI, EC0, and EC1 Result Address register */ 528 #define SAF_RPMC_OP2_ESPI_RES_OFS 0x208u 529 #define SAF_RPMC_OP2_EC0_RES_OFS 0x20cu 530 #define SAF_RPMC_OP2_EC1_RES_OFS 0x210u 531 #define SAF_RPMC_OP2_RES_REG_MSK 0xffffffffu 532 533 /* SAF Communication Mode */ 534 #define MCHP_SAF_COMM_MODE_MASK 0x01u 535 /* Allow pre-fetch from flash devices */ 536 #define MCHP_SAF_COMM_MODE_PF_EN BIT(0) 537 538 /* SAF TAG numbers[0:0xF] */ 539 #define MCHP_SAF_TAG_M0T0 0u 540 #define MCHP_SAF_TAG_M0T1 1u 541 #define MCHP_SAF_TAG_M1T0 2u 542 #define MCHP_SAF_TAG_M1T1 3u 543 #define MCHP_SAF_TAG_M2T0 4u 544 #define MCHP_SAF_TAG_M2T1 5u 545 #define MCHP_SAF_TAG_M3T0 6u 546 #define MCHP_SAF_TAG_M2T2 7u 547 #define MCHP_SAF_TAG_M6T0 9u 548 #define MCHP_SAF_TAG_M6T1 0x0du 549 #define MCHP_SAF_TAG_MAX 0x10u 550 551 /* SAF Master numbers */ 552 #define MCHP_SAF_MSTR_CS_INIT 0u 553 #define MCHP_SAF_MSTR_CPU 1u 554 #define MCHP_SAF_MSTR_CS_ME 2u 555 #define MCHP_SAF_MSTR_CS_LAN 3u 556 #define MCHP_SAF_MSTR_UNUSED4 4u 557 #define MCHP_SAF_MSTR_EC_FW 5u 558 #define MCHP_SAF_MSTR_CS_IE 6u 559 #define MCHP_SAF_MSTR_UNUSED7 7u 560 #define MCHP_SAF_MSTR_MAX 8u 561 #define MCHP_SAF_MSTR_ALL 0xffu 562 563 /* eSPI SAF */ 564 /** @brief SAF SPI Opcodes and descriptor indices */ 565 struct mchp_espi_saf_op { 566 volatile uint32_t OPA; 567 volatile uint32_t OPB; 568 volatile uint32_t OPC; 569 volatile uint32_t OP_DESCR; 570 }; 571 572 /** @brief SAF protection regions contain 4 32-bit registers. */ 573 struct mchp_espi_saf_pr { 574 volatile uint32_t START; 575 volatile uint32_t LIMIT; 576 volatile uint32_t WEBM; 577 volatile uint32_t RDBM; 578 }; 579 580 /** @brief eSPI SAF configuration and control registers at 0x40008000 */ 581 struct mchp_espi_saf { 582 uint32_t RSVD1[6]; 583 volatile uint32_t SAF_ECP_CMD; /* 0x18 */ 584 volatile uint32_t SAF_ECP_FLAR; /* 0x1c */ 585 volatile uint32_t SAF_ECP_START; /* 0x20 */ 586 volatile uint32_t SAF_ECP_BFAR; /* 0x24 */ 587 volatile uint32_t SAF_ECP_STATUS; /* 0x28 */ 588 volatile uint32_t SAF_ECP_INTEN; /* 0x2c */ 589 volatile uint32_t SAF_FL_CFG_SIZE_LIM; /* 0x30 */ 590 volatile uint32_t SAF_FL_CFG_THRH; /* 0x34 */ 591 volatile uint32_t SAF_FL_CFG_MISC; /* 0x38 */ 592 volatile uint32_t SAF_ESPI_MON_STATUS; /* 0x3c */ 593 volatile uint32_t SAF_ESPI_MON_INTEN; /* 0x40 */ 594 volatile uint32_t SAF_ECP_BUSY; /* 0x44 */ 595 uint32_t RSVD2[1]; 596 struct mchp_espi_saf_op SAF_CS_OP[2]; /* 0x4c - 0x6b */ 597 volatile uint32_t SAF_FL_CFG_GEN_DESCR; /* 0x6c */ 598 volatile uint32_t SAF_PROT_LOCK; /* 0x70 */ 599 volatile uint32_t SAF_PROT_DIRTY; /* 0x74 */ 600 volatile uint32_t SAF_TAG_MAP[3]; /* 0x78 - 0x83 */ 601 struct mchp_espi_saf_pr SAF_PROT_RG[17]; /* 0x84 - 0x193 */ 602 volatile uint32_t SAF_POLL_TMOUT; /* 0x194 */ 603 volatile uint32_t SAF_POLL_INTRVL; /* 0x198 */ 604 volatile uint32_t SAF_SUS_RSM_INTRVL; /* 0x19c */ 605 volatile uint32_t SAF_CONSEC_RD_TMOUT; /* 0x1a0 */ 606 volatile uint16_t SAF_CS0_CFG_P2M; /* 0x1a4 */ 607 volatile uint16_t SAF_CS1_CFG_P2M; /* 0x1a6 */ 608 volatile uint32_t SAF_FL_CFG_SPM; /* 0x1a8 */ 609 volatile uint32_t SAF_SUS_CHK_DLY; /* 0x1ac */ 610 volatile uint16_t SAF_CS0_CM_PRF; /* 0x1b0 */ 611 volatile uint16_t SAF_CS1_CM_PRF; /* 0x1b2 */ 612 volatile uint32_t SAF_DNX_PROT_BYP; /* 0x1b4 */ 613 volatile uint32_t SAF_AC_RELOAD; /* 0x1b8 */ 614 volatile uint32_t SAF_PWRDN_CTRL; /* 0x1bc */ 615 volatile uint32_t SAF_MEM_PWR_STS; /* 0x1c0 */ 616 volatile uint32_t SAF_CFG_CS0_OPD; /* 0x1c4 */ 617 volatile uint32_t SAF_CFG_CS1_OPD; /* 0x1c8 */ 618 volatile uint32_t SAF_FL_PWR_TMOUT; /* 0x1cc */ 619 uint32_t RSVD[12]; 620 volatile uint32_t SAF_CLKDIV_CS0; /* 0x200 */ 621 volatile uint32_t SAF_CLKDIV_CS1; /* 0x204 */ 622 volatile uint32_t SAF_RPMC_OP2_ESPI_RES; /* 0x208 */ 623 volatile uint32_t SAF_RPMC_OP2_EC0_RES; /* 0x20c */ 624 volatile uint32_t SAF_RPMC_OP2_EC1_RES; /* 0x210 */ 625 }; 626 627 struct mchp_espi_saf_comm { /* @ 0x40071000 */ 628 uint32_t TEST0; 629 uint32_t TEST1; 630 uint32_t TEST2; 631 uint32_t TEST3; 632 uint32_t TEST4; 633 uint32_t TEST5; 634 uint32_t TEST6; 635 uint32_t RSVD1[(0x2b8 - 0x01c) / 4]; 636 uint32_t SAF_COMM_MODE; /* @ 0x400712b8 */ 637 uint32_t TEST7; 638 }; 639 640 #endif /* _MEC172X_ESPI_SAF_H_ */ 641
