1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_I2C_SMB_H 8 #define _MEC172X_I2C_SMB_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* Version 3.7 MCHP I2C/SMBus Controller specification */ 14 15 #define MCHP_I2C_BAUD_CLK_HZ 16000000u 16 17 #define MCHP_I2C_SMB_INST_SPACING 0x400u 18 #define MCHP_I2C_SMB_INST_SPACING_P2 10u 19 20 #define MCHP_I2C_SMB0_BASE_ADDR 0x40004000u 21 #define MCHP_I2C_SMB1_BASE_ADDR 0x40004400u 22 #define MCHP_I2C_SMB2_BASE_ADDR 0x40004800u 23 #define MCHP_I2C_SMB3_BASE_ADDR 0x40004c00u 24 #define MCHP_I2C_SMB4_BASE_ADDR 0x40005000u 25 26 /* 0 <= n < MCHP_I2C_SMB_MAX_INSTANCES */ 27 #define MCHP_I2C_SMB_BASE_ADDR(n) \ 28 ((MCHP_I2C_SMB0_BASE_ADDR) + \ 29 ((uint32_t)(n) * (MCHP_I2C_SMB_INST_SPACING))) 30 31 /* 32 * Offset 0x00 33 * Control and Status register 34 * Write to Control 35 * Read from Status 36 * Size 8-bit 37 */ 38 #define MCHP_I2C_SMB_CTRL_OFS 0x00u 39 #define MCHP_I2C_SMB_CTRL_MASK 0xcfu 40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0) 41 #define MCHP_I2C_SMB_CTRL_STO BIT(1) 42 #define MCHP_I2C_SMB_CTRL_STA BIT(2) 43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3) 44 /* bits [5:4] reserved */ 45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6) 46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7) 47 /* Status Read-only */ 48 #define MCHP_I2C_SMB_STS_OFS 0x00u 49 #define MCHP_I2C_SMB_STS_NBB BIT(0) 50 #define MCHP_I2C_SMB_STS_LAB BIT(1) 51 #define MCHP_I2C_SMB_STS_AAS BIT(2) 52 #define MCHP_I2C_SMB_STS_LRB_AD0 BIT(3) 53 #define MCHP_I2C_SMB_STS_BER BIT(4) 54 #define MCHP_I2C_SMB_STS_EXT_STOP BIT(5) 55 #define MCHP_I2C_SMB_STS_SAD BIT(6) 56 #define MCHP_I2C_SMB_STS_PIN BIT(7) 57 58 /* 59 * Offset 0x04 60 * Own Address b[7:0] = Slave address 1 61 * b[14:8] = Slave address 2 62 */ 63 #define MCHP_I2C_SMB_OWN_ADDR_OFS 0x04u 64 #define MCHP_I2C_SMB_OWN_ADDR2_OFS 0x05u 65 #define MCHP_I2C_SMB_OWN_ADDR_MASK 0x7f7fu 66 67 /* 68 * Offset 0x08 69 * Data register, 8-bit 70 * Data to be shifted out or shifted in. 71 */ 72 #define MCHP_I2C_SMB_DATA_OFS 0x08u 73 74 /* Offset 0x0C Leader Command register 75 */ 76 #define MCHP_I2C_SMB_MSTR_CMD_OFS 0x0cu 77 #define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_OFS 0x0fu /* byte 3 */ 78 #define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_OFS 0x0eu /* byte 2 */ 79 #define MCHP_I2C_SMB_MSTR_CMD_OP_OFS 0x0du /* byte 1 */ 80 #define MCHP_I2C_SMB_MSTR_CMD_M_OFS 0x0cu /* byte 0 */ 81 #define MCHP_I2C_SMB_MSTR_CMD_MASK 0xffff3ff3u 82 /* 32-bit definitions */ 83 #define MCHP_I2C_SMB_MSTR_CMD_MRUN BIT(0) 84 #define MCHP_I2C_SMB_MSTR_CMD_MPROCEED BIT(1) 85 #define MCHP_I2C_SMB_MSTR_CMD_START0 BIT(8) 86 #define MCHP_I2C_SMB_MSTR_CMD_STARTN BIT(9) 87 #define MCHP_I2C_SMB_MSTR_CMD_STOP BIT(10) 88 #define MCHP_I2C_SMB_MSTR_CMD_PEC_TERM BIT(11) 89 #define MCHP_I2C_SMB_MSTR_CMD_READM BIT(12) 90 #define MCHP_I2C_SMB_MSTR_CMD_READ_PEC BIT(13) 91 #define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_POS 24u 92 #define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_POS 16u 93 /* byte 0 definitions */ 94 #define MCHP_I2C_SMB_MSTR_CMD_B0_MRUN BIT(0) 95 #define MCHP_I2C_SMB_MSTR_CMD_B0_MPROCEED BIT(1) 96 /* byte 1 definitions */ 97 #define MCHP_I2C_SMB_MSTR_CMD_B1_START0 BIT((8 - 8)) 98 #define MCHP_I2C_SMB_MSTR_CMD_B1_STARTN BIT((9 - 8)) 99 #define MCHP_I2C_SMB_MSTR_CMD_B1_STOP BIT((10 - 8)) 100 #define MCHP_I2C_SMB_MSTR_CMD_B1_PEC_TERM BIT((11 - 8)) 101 #define MCHP_I2C_SMB_MSTR_CMD_B1_READM BIT((12 - 8)) 102 #define MCHP_I2C_SMB_MSTR_CMD_B1_READ_PEC BIT((13 - 8)) 103 104 /* Offset 0x10 Follower Command register */ 105 #define MCHP_I2C_SMB_SLV_CMD_OFS 0x10u 106 #define MCHP_I2C_SMB_SLV_CMD_MASK 0x00ffff07u 107 #define MCHP_I2C_SMB_SLV_CMD_SRUN BIT(0) 108 #define MCHP_I2C_SMB_SLV_CMD_SPROCEED BIT(1) 109 #define MCHP_I2C_SMB_SLV_CMD_SEND_PEC BIT(2) 110 #define MCHP_I2C_SMB_SLV_WR_CNT_POS 8u 111 #define MCHP_I2C_SMB_SLV_RD_CNT_POS 16u 112 113 /* Offset 0x14 PEC CRC register, 8-bit read-write */ 114 #define MCHP_I2C_SMB_PEC_CRC_OFS 0x14u 115 116 /* Offset 0x18 Repeated Start Hold Time register, 8-bit read-write */ 117 #define MCHP_I2C_SMB_RSHT_OFS 0x18u 118 119 /* Offset 0x20 Completion register, 32-bit */ 120 #define MCHP_I2C_SMB_CMPL_OFS 0x20u 121 #define MCHP_I2C_SMB_CMPL_MASK 0xe33b7f7Cu 122 #define MCHP_I2C_SMB_CMPL_RW1C_MASK 0xe1397f00u 123 #define MCHP_I2C_SMB_CMPL_DTEN BIT(2) 124 #define MCHP_I2C_SMB_CMPL_MCEN BIT(3) 125 #define MCHP_I2C_SMB_CMPL_SCEN BIT(4) 126 #define MCHP_I2C_SMB_CMPL_BIDEN BIT(5) 127 #define MCHP_I2C_SMB_CMPL_TIMERR BIT(6) 128 #define MCHP_I2C_SMB_CMPL_DTO_RWC BIT(8) 129 #define MCHP_I2C_SMB_CMPL_MCTO_RWC BIT(9) 130 #define MCHP_I2C_SMB_CMPL_SCTO_RWC BIT(10) 131 #define MCHP_I2C_SMB_CMPL_CHDL_RWC BIT(11) 132 #define MCHP_I2C_SMB_CMPL_CHDH_RWC BIT(12) 133 #define MCHP_I2C_SMB_CMPL_BER_RWC BIT(13) 134 #define MCHP_I2C_SMB_CMPL_LAB_RWC BIT(14) 135 #define MCHP_I2C_SMB_CMPL_SNAKR_RWC BIT(16) 136 #define MCHP_I2C_SMB_CMPL_STR_RO BIT(17) 137 #define MCHP_I2C_SMB_CMPL_SPROT_RWC BIT(19) 138 #define MCHP_I2C_SMB_CMPL_RPT_RD_RWC BIT(20) 139 #define MCHP_I2C_SMB_CMPL_RPT_WR_RWC BIT(21) 140 #define MCHP_I2C_SMB_CMPL_MNAKX_RWC BIT(24) 141 #define MCHP_I2C_SMB_CMPL_MTR_RO BIT(25) 142 #define MCHP_I2C_SMB_CMPL_IDLE_RWC BIT(29) 143 #define MCHP_I2C_SMB_CMPL_MDONE_RWC BIT(30) 144 #define MCHP_I2C_SMB_CMPL_SDONE_RWC BIT(31) 145 146 /* Offset 0x24 Idle Scaling register */ 147 #define MCHP_I2C_SMB_IDLSC_OFS 0x24u 148 #define MCHP_I2C_SMB_IDLSC_DLY_OFS 0x24u 149 #define MCHP_I2C_SMB_IDLSC_BUS_OFS 0x26u 150 #define MCHP_I2C_SMB_IDLSC_MASK 0x0fff0fffu 151 #define MCHP_I2C_SMB_IDLSC_BUS_MIN_POS 0u 152 #define MCHP_I2C_SMB_IDLSC_DLY_POS 16u 153 154 /* Offset 0x28 Configuration register */ 155 #define MCHP_I2C_SMB_CFG_OFS 0x28u 156 #define MCHP_I2C_SMB_CFG_MASK 0xf00f5Fbfu 157 #define MCHP_I2C_SMB_CFG_PORT_SEL_POS 0 158 #define MCHP_I2C_SMB_CFG_PORT_SEL_MASK 0x0fu 159 #define MCHP_I2C_SMB_CFG_TCEN BIT(4) 160 #define MCHP_I2C_SMB_CFG_SLOW_CLK BIT(5) 161 #define MCHP_I2C_SMB_CFG_PCEN BIT(7) 162 #define MCHP_I2C_SMB_CFG_FEN BIT(8) 163 #define MCHP_I2C_SMB_CFG_RESET BIT(9) 164 #define MCHP_I2C_SMB_CFG_ENAB BIT(10) 165 #define MCHP_I2C_SMB_CFG_DSA BIT(11) 166 #define MCHP_I2C_SMB_CFG_FAIR BIT(12) 167 #define MCHP_I2C_SMB_CFG_GC_DIS BIT(14) 168 #define MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO BIT(16) 169 #define MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO BIT(17) 170 #define MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO BIT(18) 171 #define MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO BIT(19) 172 #define MCHP_I2C_SMB_CFG_EN_AAS BIT(28) 173 #define MCHP_I2C_SMB_CFG_ENIDI BIT(29) 174 #define MCHP_I2C_SMB_CFG_ENMI BIT(30) 175 #define MCHP_I2C_SMB_CFG_ENSI BIT(31) 176 177 /* Offset 0x2C Bus Clock register */ 178 #define MCHP_I2C_SMB_BUS_CLK_OFS 0x2cu 179 #define MCHP_I2C_SMB_BUS_CLK_MASK 0x0000ffffu 180 #define MCHP_I2C_SMB_BUS_CLK_LO_POS 0u 181 #define MCHP_I2C_SMB_BUS_CLK_HI_POS 8u 182 183 /* Offset 0x30 Block ID register, 8-bit read-only */ 184 #define MCHP_I2C_SMB_BLOCK_ID_OFS 0x30u 185 #define MCHP_I2C_SMB_BLOCK_ID_MASK 0xffu 186 187 /* Offset 0x34 Block Revision register, 8-bit read-only */ 188 #define MCHP_I2C_SMB_BLOCK_REV_OFS 0x34u 189 #define MCHP_I2C_SMB_BLOCK_REV_MASK 0xffu 190 191 /* Offset 0x38 Bit-Bang Control register, 8-bit read-write */ 192 #define MCHP_I2C_SMB_BB_OFS 0x38u 193 #define MCHP_I2C_SMB_BB_MASK 0x7fu 194 #define MCHP_I2C_SMB_BB_EN BIT(0) 195 #define MCHP_I2C_SMB_BB_SCL_DIR_IN 0 196 #define MCHP_I2C_SMB_BB_SCL_DIR_OUT BIT(1) 197 #define MCHP_I2C_SMB_BB_SDA_DIR_IN 0 198 #define MCHP_I2C_SMB_BB_SDA_DIR_OUT BIT(2) 199 #define MCHP_I2C_SMB_BB_CL BIT(3) 200 #define MCHP_I2C_SMB_BB_DAT BIT(4) 201 #define MCHP_I2C_SMB_BB_IN_POS 5u 202 #define MCHP_I2C_SMB_BB_IN_MASK0 0x03u 203 #define MCHP_I2C_SMB_BB_IN_MASK SHLU32(0x03, 5) 204 #define MCHP_I2C_SMB_BB_CLKI_RO BIT(5) 205 #define MCHP_I2C_SMB_BB_DATI_RO BIT(6) 206 207 /* Offset 0x40 Data Timing register */ 208 #define MCHP_I2C_SMB_DATA_TM_OFS 0x40u 209 #define MCHP_I2C_SMB_DATA_TM_MASK GENMASK(31, 0) 210 #define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_POS 0u 211 #define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK 0xffu 212 #define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK0 0xffu 213 #define MCHP_I2C_SMB_DATA_TM_RESTART_POS 8u 214 #define MCHP_I2C_SMB_DATA_TM_RESTART_MASK 0xff00u 215 #define MCHP_I2C_SMB_DATA_TM_RESTART_MASK0 0xffu 216 #define MCHP_I2C_SMB_DATA_TM_STOP_POS 16u 217 #define MCHP_I2C_SMB_DATA_TM_STOP_MASK 0xff0000u 218 #define MCHP_I2C_SMB_DATA_TM_STOP_MASK0 0xffu 219 #define MCHP_I2C_SMB_DATA_TM_FSTART_POS 24u 220 #define MCHP_I2C_SMB_DATA_TM_FSTART_MASK 0xff000000u 221 #define MCHP_I2C_SMB_DATA_TM_FSTART_MASK0 0xffu 222 223 /* Offset 0x44 Time-out Scaling register */ 224 #define MCHP_I2C_SMB_TMTSC_OFS 0x44u 225 #define MCHP_I2C_SMB_TMTSC_MASK GENMASK(31, 0) 226 #define MCHP_I2C_SMB_TMTSC_CLK_HI_POS 0u 227 #define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK 0xffu 228 #define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK0 0xffu 229 #define MCHP_I2C_SMB_TMTSC_SLV_POS 8u 230 #define MCHP_I2C_SMB_TMTSC_SLV_MASK 0xff00u 231 #define MCHP_I2C_SMB_TMTSC_SLV_MASK0 0xffu 232 #define MCHP_I2C_SMB_TMTSC_MSTR_POS 16u 233 #define MCHP_I2C_SMB_TMTSC_MSTR_MASK 0xff0000u 234 #define MCHP_I2C_SMB_TMTSC_MSTR_MASK0 0xffu 235 #define MCHP_I2C_SMB_TMTSC_BUS_POS 24u 236 #define MCHP_I2C_SMB_TMTSC_BUS_MASK 0xff000000u 237 #define MCHP_I2C_SMB_TMTSC_BUS_MASK0 0xffu 238 239 /* Offset 0x48 Follower Transmit Buffer register 8-bit read-write */ 240 #define MCHP_I2C_SMB_SLV_TX_BUF_OFS 0x48u 241 242 /* Offset 0x4C Follower Receive Buffer register 8-bit read-write */ 243 #define MCHP_I2C_SMB_SLV_RX_BUF_OFS 0x4cu 244 245 /* Offset 0x50 Leader Transmit Buffer register 8-bit read-write */ 246 #define MCHP_I2C_SMB_MTR_TX_BUF_OFS 0x50u 247 248 /* Offset 0x54 Leader Receive Buffer register 8-bit read-write */ 249 #define MCHP_I2C_SMB_MTR_RX_BUF_OFS 0x54u 250 251 /* Offset 0x58 I2C FSM read-only */ 252 #define MCHP_I2C_SMB_I2C_FSM_OFS 0x58u 253 254 /* Offset 0x5C SMB Network layer FSM read-only */ 255 #define MCHP_I2C_SMB_FSM_OFS 0x5cu 256 257 /* Offset 0x60 Wake Status register */ 258 #define MCHP_I2C_SMB_WAKE_STS_OFS 0x60u 259 #define MCHP_I2C_SMB_WAKE_STS_START_RWC BIT(0) 260 261 /* Offset 0x64 Wake Enable register */ 262 #define MCHP_I2C_SMB_WAKE_EN_OFS 0x64u 263 #define MCHP_I2C_SMB_WAKE_EN BIT(0) 264 265 /* Offset 0x68 */ 266 #define MCHP_I2C_SMB_WAKE_SYNC_OFS 0x68u 267 #define MCHP_I2C_SMB_WAKE_FAST_RESYNC_EN BIT(0) 268 269 /** @brief I2C-SMBus with network layer registers. */ 270 struct i2c_smb_regs { 271 volatile uint8_t CTRLSTS; 272 uint8_t RSVD1[3]; 273 volatile uint32_t OWN_ADDR; 274 volatile uint8_t I2CDATA; 275 uint8_t RSVD2[3]; 276 volatile uint32_t MCMD; 277 volatile uint32_t SCMD; 278 volatile uint8_t PEC; 279 uint8_t RSVD3[3]; 280 volatile uint32_t RSHTM; 281 volatile uint32_t EXTLEN; 282 volatile uint32_t COMPL; 283 volatile uint32_t IDLSC; 284 volatile uint32_t CFG; 285 volatile uint32_t BUSCLK; 286 volatile uint32_t BLKID; 287 volatile uint32_t BLKREV; 288 volatile uint8_t BBCTRL; 289 uint8_t RSVD7[3]; 290 volatile uint32_t CLKSYNC; 291 volatile uint32_t DATATM; 292 volatile uint32_t TMOUTSC; 293 volatile uint8_t SLV_TXB; 294 uint8_t RSVD8[3]; 295 volatile uint8_t SLV_RXB; 296 uint8_t RSVD9[3]; 297 volatile uint8_t MTR_TXB; 298 uint8_t RSVD10[3]; 299 volatile uint8_t MTR_RXB; 300 uint8_t RSVD11[3]; 301 volatile uint32_t FSM; 302 volatile uint32_t FSM_SMB; 303 volatile uint8_t WAKE_STS; 304 uint8_t RSVD12[3]; 305 volatile uint8_t WAKE_EN; 306 uint32_t RSVD13[2]; 307 volatile uint32_t PROM_ISTS; 308 volatile uint32_t PROM_IEN; 309 volatile uint32_t PROM_CTRL; 310 volatile uint32_t SHADOW_DATA; 311 }; /* Size = 128(0x80) */ 312 313 #endif /* #ifndef _MEC172X_I2C_SMB_H */ 314
