1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC172X_GPIO_H 8 #define _MEC172X_GPIO_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 #if defined(CONFIG_SOC_MEC172X_NSZ) 14 #include "gpio_pkg_sz.h" 15 #elif defined(CONFIG_SOC_MEC172X_NLJ) 16 #include "gpio_pkg_lj.h" 17 #endif 18 19 #define NUM_MCHP_GPIO_PORTS 6u 20 #define MAX_NUM_MCHP_GPIO (NUM_MCHP_GPIO_PORTS * 32u) 21 22 /* GPIO Control register field definitions. */ 23 24 /* bits[1:0] internal pull up/down selection */ 25 #define MCHP_GPIO_CTRL_PUD_POS 0 26 #define MCHP_GPIO_CTRL_PUD_MASK0 0x03u 27 #define MCHP_GPIO_CTRL_PUD_MASK 0x03u 28 #define MCHP_GPIO_CTRL_PUD_NONE 0x00u 29 #define MCHP_GPIO_CTRL_PUD_PU 0x01u 30 #define MCHP_GPIO_CTRL_PUD_PD 0x02u 31 /* Repeater(keeper) mode */ 32 #define MCHP_GPIO_CTRL_PUD_RPT 0x03u 33 34 /* bits[3:2] power gating */ 35 #define MCHP_GPIO_CTRL_PWRG_POS 2 36 #define MCHP_GPIO_CTRL_PWRG_MASK0 0x03u 37 #define MCHP_GPIO_CTRL_PWRG_VTR_IO 0 38 #define MCHP_GPIO_CTRL_PWRG_VCC_IO SHLU32(1, MCHP_GPIO_CTRL_PWRG_POS) 39 #define MCHP_GPIO_CTRL_PWRG_OFF SHLU32(2, MCHP_GPIO_CTRL_PWRG_POS) 40 #define MCHP_GPIO_CTRL_PWRG_RSVD SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS) 41 #define MCHP_GPIO_CTRL_PWRG_MASK SHLU32(3, MCHP_GPIO_CTRL_PWRG_POS) 42 43 /* bits[7:4] interrupt detection mode */ 44 #define MCHP_GPIO_CTRL_IDET_POS 4 45 #define MCHP_GPIO_CTRL_IDET_MASK0 0x0fu 46 #define MCHP_GPIO_CTRL_IDET_LVL_LO 0 47 #define MCHP_GPIO_CTRL_IDET_LVL_HI SHLU32(1, MCHP_GPIO_CTRL_IDET_POS) 48 #define MCHP_GPIO_CTRL_IDET_DISABLE SHLU32(4, MCHP_GPIO_CTRL_IDET_POS) 49 #define MCHP_GPIO_CTRL_IDET_REDGE SHLU32(0xd, MCHP_GPIO_CTRL_IDET_POS) 50 #define MCHP_GPIO_CTRL_IDET_FEDGE SHLU32(0xe, MCHP_GPIO_CTRL_IDET_POS) 51 #define MCHP_GPIO_CTRL_IDET_BEDGE SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS) 52 #define MCHP_GPIO_CTRL_IDET_MASK SHLU32(0xf, MCHP_GPIO_CTRL_IDET_POS) 53 54 /* bit[8] output buffer type: push-pull or open-drain */ 55 #define MCHP_GPIO_CTRL_BUFT_POS 8 56 #define MCHP_GPIO_CTRL_BUFT_MASK BIT(MCHP_GPIO_CTRL_BUFT_POS) 57 #define MCHP_GPIO_CTRL_BUFT_OPENDRAIN BIT(MCHP_GPIO_CTRL_BUFT_POS) 58 #define MCHP_GPIO_CTRL_BUFT_PUSHPULL 0 59 60 /* bit[9] direction */ 61 #define MCHP_GPIO_CTRL_DIR_POS 9 62 #define MCHP_GPIO_CTRL_DIR_MASK BIT(MCHP_GPIO_CTRL_DIR_POS) 63 #define MCHP_GPIO_CTRL_DIR_OUTPUT BIT(MCHP_GPIO_CTRL_DIR_POS) 64 #define MCHP_GPIO_CTRL_DIR_INPUT 0 65 66 /* 67 * bit[10] Alternate output disable. Default==0(alternate output enabled) 68 * GPIO output value is controlled by bit[16] of this register. 69 * Set bit[10]=1 if you wish to control pin output using the parallel 70 * GPIO output register bit for this pin. 71 */ 72 #define MCHP_GPIO_CTRL_AOD_POS 10 73 #define MCHP_GPIO_CTRL_AOD_MASK BIT(MCHP_GPIO_CTRL_AOD_POS) 74 #define MCHP_GPIO_CTRL_AOD_DIS BIT(MCHP_GPIO_CTRL_AOD_POS) 75 76 /* bit[11] GPIO function output polarity */ 77 #define MCHP_GPIO_CTRL_POL_POS 11 78 #define MCHP_GPIO_CTRL_POL_INVERT BIT(MCHP_GPIO_CTRL_POL_POS) 79 80 /* bits[14:12] pin mux (function) */ 81 #define MCHP_GPIO_CTRL_MUX_POS 12 82 #define MCHP_GPIO_CTRL_MUX_MASK0 0x07u 83 #define MCHP_GPIO_CTRL_MUX_MASK SHLU32(7, MCHP_GPIO_CTRL_MUX_POS) 84 #define MCHP_GPIO_CTRL_MUX_F0 0 85 #define MCHP_GPIO_CTRL_MUX_GPIO MCHP_GPIO_CTRL_MUX_F0 86 #define MCHP_GPIO_CTRL_MUX_F1 SHLU32(1, MCHP_GPIO_CTRL_MUX_POS) 87 #define MCHP_GPIO_CTRL_MUX_F2 SHLU32(2, MCHP_GPIO_CTRL_MUX_POS) 88 #define MCHP_GPIO_CTRL_MUX_F3 SHLU32(3, MCHP_GPIO_CTRL_MUX_POS) 89 #define MCHP_GPIO_CTRL_MUX_F4 SHLU32(4, MCHP_GPIO_CTRL_MUX_POS) 90 #define MCHP_GPIO_CTRL_MUX_F5 SHLU32(5, MCHP_GPIO_CTRL_MUX_POS) 91 #define MCHP_GPIO_CTRL_MUX_F6 SHLU32(6, MCHP_GPIO_CTRL_MUX_POS) 92 #define MCHP_GPIO_CTRL_MUX_F7 SHLU32(7, MCHP_GPIO_CTRL_MUX_POS) 93 #define MCHP_GPIO_CTRL_MUX(n) SHLU32(((n) & 0x7u), MCHP_GPIO_CTRL_MUX_POS) 94 95 #define MCHP_GPIO_CTRL_MUX_GET(x) (((uint32_t)(x) >> MCHP_GPIO_CTRL_MUX_POS)\ 96 & MCHP_GPIO_CTRL_MUX_MASK0) 97 98 /* 99 * bit[15] Disables input pad leaving output pad enabled 100 * Useful for reducing power consumption of output only pins. 101 */ 102 #define MCHP_GPIO_CTRL_INPAD_DIS_POS 15 103 #define MCHP_GPIO_CTRL_INPAD_DIS_MASK BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) 104 #define MCHP_GPIO_CTRL_INPAD_DIS BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS) 105 106 /* bit[16]: Alternate output pin value. Enabled when bit[10]==0(default) */ 107 #define MCHP_GPIO_CTRL_OUTVAL_POS 16 108 #define MCHP_GPIO_CTRL_OUTV_HI BIT(MCHP_GPIO_CTRL_OUTVAL_POS) 109 110 /* bit[24] Input pad value. Always live unless input pad is powered down */ 111 #define MCHP_GPIO_CTRL_INPAD_VAL_POS 24 112 #define MCHP_GPIO_CTRL_INPAD_VAL_HI BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS) 113 114 #define MCHP_GPIO_CTRL_DRIVE_OD_HI \ 115 (MCHP_GPIO_CTRL_BUFT_OPENDRAIN + MCHP_GPIO_CTRL_DIR_OUTPUT + \ 116 MCHP_GPIO_CTRL_MUX_GPIO + MCHP_GPIO_CTRL_OUTV_HI) 117 118 /* 119 * Each GPIO pin implements a second control register. 120 * GPIO Control 2 register selects pin drive strength and slew rate. 121 * bit[0] = slew rate: 0=slow, 1=fast 122 * bits[5:4] = drive strength 123 * 00b = 2mA (default) 124 * 01b = 4mA 125 * 10b = 8mA 126 * 11b = 12mA 127 */ 128 #define MCHP_GPIO_CTRL2_SLEW_POS 0 129 #define MCHP_GPIO_CTRL2_SLEW_MASK 0x01u 130 #define MCHP_GPIO_CTRL2_SLEW_SLOW 0 131 #define MCHP_GPIO_CTRL2_SLEW_FAST BIT(MCHP_GPIO_CTRL2_SLEW_POS) 132 #define MCHP_GPIO_CTRL2_DRV_STR_POS 4 133 #define MCHP_GPIO_CTRL2_DRV_STR_MASK 0x30u 134 #define MCHP_GPIO_CTRL2_DRV_STR_2MA 0 135 #define MCHP_GPIO_CTRL2_DRV_STR_4MA 0x10u 136 #define MCHP_GPIO_CTRL2_DRV_STR_8MA 0x20u 137 #define MCHP_GPIO_CTRL2_DRV_STR_12MA 0x30u 138 139 /* Interfaces to any C modules */ 140 #ifdef __cplusplus 141 extern "C" { 142 #endif 143 144 #define MCHP_GPIO_PIN2PORT(pin_id) ((uint32_t)(pin_id) >> 5) 145 146 /* Helper functions */ 147 enum mchp_gpio_pud { 148 MCHP_GPIO_NO_PUD = 0, 149 MCHP_GPIO_PU_EN, 150 MCHP_GPIO_PD_EN, 151 MCHP_GPIO_RPT_EN, 152 }; 153 154 enum mchp_gpio_pwrgate { 155 MCHP_GPIO_PWRGT_VTR = 0, 156 MCHP_GPIO_PWRGT_VCC, 157 MCHP_GPIO_PWRGD_OFF, 158 }; 159 160 enum mchp_gpio_idet { 161 MCHP_GPIO_IDET_LO_LVL = 0u, 162 MCHP_GPIO_IDET_HI_LVL = 0x01u, 163 MCHP_GPIO_IDET_DIS = 0x04u, 164 MCHP_GPIO_IDET_RISING_EDGE = 0x0du, 165 MCHP_GPIO_IDET_FALLING_EDGE = 0x0eu, 166 MCHP_GPIO_IDET_BOTH_EDGES = 0x0fu 167 }; 168 169 enum mchp_gpio_outbuf { 170 MCHP_GPIO_PUSH_PULL = 0, 171 MCHP_GPIO_OPEN_DRAIN, 172 }; 173 174 enum mchp_gpio_dir { 175 MCHP_GPIO_DIR_IN = 0, 176 MCHP_GPIO_DIR_OUT, 177 }; 178 179 enum mchp_gpio_parout_en { 180 MCHP_GPIO_PAROUT_DIS = 0, 181 MCHP_GPIO_PAROUT_EN, 182 }; 183 184 enum mchp_gpio_pol { 185 MCHP_GPIO_POL_NORM = 0, 186 MCHP_GPIO_POL_INV, 187 }; 188 189 enum mchp_gpio_mux { 190 MCHP_GPIO_MUX_GPIO = 0u, 191 MCHP_GPIO_MUX_FUNC1, 192 MCHP_GPIO_MUX_FUNC2, 193 MCHP_GPIO_MUX_FUNC3, 194 MCHP_GPIO_MUX_FUNC4, 195 MCHP_GPIO_MUX_FUNC5, 196 MCHP_GPIO_MUX_FUNC6, 197 MCHP_GPIO_MUX_FUNC7, 198 MCHP_GPIO_MUX_MAX 199 }; 200 201 enum mchp_gpio_inpad_ctrl { 202 MCHP_GPIO_INPAD_CTRL_EN = 0, 203 MCHP_GPIO_INPAD_CTRL_DIS, 204 }; 205 206 enum mchp_gpio_alt_out { 207 MCHP_GPIO_ALT_OUT_LO = 0, 208 MCHP_GPIO_ALT_OUT_HI, 209 }; 210 211 enum mchp_gpio_slew { 212 MCHP_GPIO_SLEW_SLOW = 0, 213 MCHP_GPIO_SLEW_FAST, 214 }; 215 216 enum mchp_gpio_drv_str { 217 MCHP_GPIO_DRV_STR_2MA = 0, 218 MCHP_GPIO_DRV_STR_4MA, 219 MCHP_GPIO_DRV_STR_8MA, 220 MCHP_GPIO_DRV_STR_12MA, 221 }; 222 223 #ifdef __cplusplus 224 } 225 #endif 226 227 #endif /* #ifndef _MEC172X_GPIO_H */ 228
