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Searched defs:MCFGR0 (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h10222 …__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x2… member
DRV32M1_zero_riscy.h10366 …__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x2… member