1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_MCASP_H__ 35 #define __HW_MCASP_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the MCASP register offsets. 40 // 41 //***************************************************************************** 42 #define MCASP_O_PID 0x00000000 43 #define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register. 44 #define MCASP_O_PFUNC 0x00000010 45 #define MCASP_O_PDIR 0x00000014 46 #define MCASP_O_PDOUT 0x00000018 47 #define MCASP_O_PDSET 0x0000001C // The pin data set register 48 // (PDSET) is an alias of the pin 49 // data output register (PDOUT) for 50 // writes only. Writing a 1 to the 51 // PDSET bit sets the corresponding 52 // bit in PDOUT and if PFUNC = 1 53 // (GPIO function) and PDIR = 1 54 // (output) drives a logic high on 55 // the pin. 56 #define MCASP_O_PDIN 0x0000001C // The pin data input register 57 // (PDIN) holds the I/O pin state of 58 // each of the McASP pins. PDIN 59 // allows the actual value of the 60 // pin to be read regardless of the 61 // state of PFUNC and PDIR. 62 #define MCASP_O_PDCLR 0x00000020 // The pin data clear register 63 // (PDCLR) is an alias of the pin 64 // data output register (PDOUT) for 65 // writes only. Writing a 1 to the 66 // PDCLR bit clears the 67 // corresponding bit in PDOUT and if 68 // PFUNC = 1 (GPIO function) and 69 // PDIR = 1 (output) drives a logic 70 // low on the pin. 71 #define MCASP_O_TLGC 0x00000030 // for IODFT 72 #define MCASP_O_TLMR 0x00000034 // for IODFT 73 #define MCASP_O_TLEC 0x00000038 // for IODFT 74 #define MCASP_O_GBLCTL 0x00000044 75 #define MCASP_O_AMUTE 0x00000048 76 #define MCASP_O_LBCTL 0x0000004C 77 #define MCASP_O_TXDITCTL 0x00000050 78 #define MCASP_O_GBLCTLR 0x00000060 79 #define MCASP_O_RXMASK 0x00000064 80 #define MCASP_O_RXFMT 0x00000068 81 #define MCASP_O_RXFMCTL 0x0000006C 82 #define MCASP_O_ACLKRCTL 0x00000070 83 #define MCASP_O_AHCLKRCTL 0x00000074 84 #define MCASP_O_RXTDM 0x00000078 85 #define MCASP_O_EVTCTLR 0x0000007C 86 #define MCASP_O_RXSTAT 0x00000080 87 #define MCASP_O_RXTDMSLOT 0x00000084 88 #define MCASP_O_RXCLKCHK 0x00000088 89 #define MCASP_O_REVTCTL 0x0000008C 90 #define MCASP_O_GBLCTLX 0x000000A0 91 #define MCASP_O_TXMASK 0x000000A4 92 #define MCASP_O_TXFMT 0x000000A8 93 #define MCASP_O_TXFMCTL 0x000000AC 94 #define MCASP_O_ACLKXCTL 0x000000B0 95 #define MCASP_O_AHCLKXCTL 0x000000B4 96 #define MCASP_O_TXTDM 0x000000B8 97 #define MCASP_O_EVTCTLX 0x000000BC 98 #define MCASP_O_TXSTAT 0x000000C0 99 #define MCASP_O_TXTDMSLOT 0x000000C4 100 #define MCASP_O_TXCLKCHK 0x000000C8 101 #define MCASP_O_XEVTCTL 0x000000CC 102 #define MCASP_O_CLKADJEN 0x000000D0 103 #define MCASP_O_DITCSRA0 0x00000100 104 #define MCASP_O_DITCSRA1 0x00000104 105 #define MCASP_O_DITCSRA2 0x00000108 106 #define MCASP_O_DITCSRA3 0x0000010C 107 #define MCASP_O_DITCSRA4 0x00000110 108 #define MCASP_O_DITCSRA5 0x00000114 109 #define MCASP_O_DITCSRB0 0x00000118 110 #define MCASP_O_DITCSRB1 0x0000011C 111 #define MCASP_O_DITCSRB2 0x00000120 112 #define MCASP_O_DITCSRB3 0x00000124 113 #define MCASP_O_DITCSRB4 0x00000128 114 #define MCASP_O_DITCSRB5 0x0000012C 115 #define MCASP_O_DITUDRA0 0x00000130 116 #define MCASP_O_DITUDRA1 0x00000134 117 #define MCASP_O_DITUDRA2 0x00000138 118 #define MCASP_O_DITUDRA3 0x0000013C 119 #define MCASP_O_DITUDRA4 0x00000140 120 #define MCASP_O_DITUDRA5 0x00000144 121 #define MCASP_O_DITUDRB0 0x00000148 122 #define MCASP_O_DITUDRB1 0x0000014C 123 #define MCASP_O_DITUDRB2 0x00000150 124 #define MCASP_O_DITUDRB3 0x00000154 125 #define MCASP_O_DITUDRB4 0x00000158 126 #define MCASP_O_DITUDRB5 0x0000015C 127 #define MCASP_O_XRSRCTL0 0x00000180 128 #define MCASP_O_XRSRCTL1 0x00000184 129 #define MCASP_O_XRSRCTL2 0x00000188 130 #define MCASP_O_XRSRCTL3 0x0000018C 131 #define MCASP_O_XRSRCTL4 0x00000190 132 #define MCASP_O_XRSRCTL5 0x00000194 133 #define MCASP_O_XRSRCTL6 0x00000198 134 #define MCASP_O_XRSRCTL7 0x0000019C 135 #define MCASP_O_XRSRCTL8 0x000001A0 136 #define MCASP_O_XRSRCTL9 0x000001A4 137 #define MCASP_O_XRSRCTL10 0x000001A8 138 #define MCASP_O_XRSRCTL11 0x000001AC 139 #define MCASP_O_XRSRCTL12 0x000001B0 140 #define MCASP_O_XRSRCTL13 0x000001B4 141 #define MCASP_O_XRSRCTL14 0x000001B8 142 #define MCASP_O_XRSRCTL15 0x000001BC 143 #define MCASP_O_TXBUF0 0x00000200 144 #define MCASP_O_TXBUF1 0x00000204 145 #define MCASP_O_TXBUF2 0x00000208 146 #define MCASP_O_TXBUF3 0x0000020C 147 #define MCASP_O_TXBUF4 0x00000210 148 #define MCASP_O_TXBUF5 0x00000214 149 #define MCASP_O_TXBUF6 0x00000218 150 #define MCASP_O_TXBUF7 0x0000021C 151 #define MCASP_O_TXBUF8 0x00000220 152 #define MCASP_O_TXBUF9 0x00000224 153 #define MCASP_O_TXBUF10 0x00000228 154 #define MCASP_O_TXBUF11 0x0000022C 155 #define MCASP_O_TXBUF12 0x00000230 156 #define MCASP_O_TXBUF13 0x00000234 157 #define MCASP_O_TXBUF14 0x00000238 158 #define MCASP_O_TXBUF15 0x0000023C 159 #define MCASP_O_RXBUF0 0x00000280 160 #define MCASP_O_RXBUF1 0x00000284 161 #define MCASP_O_RXBUF2 0x00000288 162 #define MCASP_O_RXBUF3 0x0000028C 163 #define MCASP_O_RXBUF4 0x00000290 164 #define MCASP_O_RXBUF5 0x00000294 165 #define MCASP_O_RXBUF6 0x00000298 166 #define MCASP_O_RXBUF7 0x0000029C 167 #define MCASP_O_RXBUF8 0x000002A0 168 #define MCASP_O_RXBUF9 0x000002A4 169 #define MCASP_O_RXBUF10 0x000002A8 170 #define MCASP_O_RXBUF11 0x000002AC 171 #define MCASP_O_RXBUF12 0x000002B0 172 #define MCASP_O_RXBUF13 0x000002B4 173 #define MCASP_O_RXBUF14 0x000002B8 174 #define MCASP_O_RXBUF15 0x000002BC 175 #define MCASP_0_WFIFOCTL 0x00001000 176 #define MCASP_0_WFIFOSTS 0x00001004 177 #define MCASP_0_RFIFOCTL 0x00001008 178 #define MCASP_0_RFIFOSTS 0x0000100C 179 180 181 //****************************************************************************** 182 // 183 // The following are defines for the bit fields in the MCASP_O_PID register. 184 // 185 //****************************************************************************** 186 #define MCASP_PID_SCHEME_M 0xC0000000 187 #define MCASP_PID_SCHEME_S 30 188 #define MCASP_PID_RESV_M 0x30000000 189 #define MCASP_PID_RESV_S 28 190 #define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP 191 #define MCASP_PID_FUNCTION_S 16 192 #define MCASP_PID_RTL_M 0x0000F800 193 #define MCASP_PID_RTL_S 11 194 #define MCASP_PID_REVMAJOR_M 0x00000700 195 #define MCASP_PID_REVMAJOR_S 8 196 #define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom 197 #define MCASP_PID_CUSTOM_S 6 198 #define MCASP_PID_REVMINOR_M 0x0000003F 199 #define MCASP_PID_REVMINOR_S 0 200 //****************************************************************************** 201 // 202 // The following are defines for the bit fields in the 203 // MCASP_O_ESYSCONFIG register. 204 // 205 //****************************************************************************** 206 #define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5 207 #define MCASP_ESYSCONFIG_RSV_S 6 208 #define MCASP_ESYSCONFIG_OTHER_M \ 209 0x0000003C // Reserved for future expansion 210 211 #define MCASP_ESYSCONFIG_OTHER_S 2 212 #define MCASP_ESYSCONFIG_IDLE_MODE_M \ 213 0x00000003 // Idle Mode 214 215 #define MCASP_ESYSCONFIG_IDLE_MODE_S 0 216 //****************************************************************************** 217 // 218 // The following are defines for the bit fields in the MCASP_O_PFUNC register. 219 // 220 //****************************************************************************** 221 #define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1 222 #define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1 223 #define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1 224 #define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1 225 #define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1 226 #define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1 227 #define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1 228 #define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved 229 #define MCASP_PFUNC_RESV1_S 16 230 #define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1 231 #define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1 232 #define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1 233 #define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1 234 #define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1 235 #define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1 236 #define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1 237 #define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1 238 #define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1 239 #define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1 240 #define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1 241 #define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1 242 #define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1 243 #define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1 244 #define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1 245 #define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1 246 //****************************************************************************** 247 // 248 // The following are defines for the bit fields in the MCASP_O_PDIR register. 249 // 250 //****************************************************************************** 251 #define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1 252 #define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1 253 #define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1 254 #define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1 255 #define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1 256 #define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1 257 #define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1 258 #define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved 259 #define MCASP_PDIR_RESV_S 16 260 #define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1 261 #define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1 262 #define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1 263 #define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1 264 #define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1 265 #define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1 266 #define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1 267 #define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1 268 #define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1 269 #define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1 270 #define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1 271 #define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1 272 #define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1 273 #define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1 274 #define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1 275 #define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1 276 //****************************************************************************** 277 // 278 // The following are defines for the bit fields in the MCASP_O_PDOUT register. 279 // 280 //****************************************************************************** 281 #define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1 282 #define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1 283 #define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1 284 #define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1 285 #define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1 286 #define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1 287 #define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1 288 #define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved 289 #define MCASP_PDOUT_RESV_S 16 290 #define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1 291 #define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1 292 #define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1 293 #define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1 294 #define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1 295 #define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1 296 #define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1 297 #define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1 298 #define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1 299 #define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1 300 #define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1 301 #define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1 302 #define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1 303 #define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1 304 #define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1 305 #define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1 306 //****************************************************************************** 307 // 308 // The following are defines for the bit fields in the MCASP_O_PDSET register. 309 // 310 //****************************************************************************** 311 #define MCASP_PDSET_AFSR 0x80000000 312 #define MCASP_PDSET_AHCLKR 0x40000000 313 #define MCASP_PDSET_ACLKR 0x20000000 314 #define MCASP_PDSET_AFSX 0x10000000 315 #define MCASP_PDSET_AHCLKX 0x08000000 316 #define MCASP_PDSET_ACLKX 0x04000000 317 #define MCASP_PDSET_AMUTE 0x02000000 318 #define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved 319 #define MCASP_PDSET_RESV_S 16 320 #define MCASP_PDSET_AXR15 0x00008000 321 #define MCASP_PDSET_AXR14 0x00004000 322 #define MCASP_PDSET_AXR13 0x00002000 323 #define MCASP_PDSET_AXR12 0x00001000 324 #define MCASP_PDSET_AXR11 0x00000800 325 #define MCASP_PDSET_AXR10 0x00000400 326 #define MCASP_PDSET_AXR9 0x00000200 327 #define MCASP_PDSET_AXR8 0x00000100 328 #define MCASP_PDSET_AXR7 0x00000080 329 #define MCASP_PDSET_AXR6 0x00000040 330 #define MCASP_PDSET_AXR5 0x00000020 331 #define MCASP_PDSET_AXR4 0x00000010 332 #define MCASP_PDSET_AXR3 0x00000008 333 #define MCASP_PDSET_AXR2 0x00000004 334 #define MCASP_PDSET_AXR1 0x00000002 335 #define MCASP_PDSET_AXR0 0x00000001 336 //****************************************************************************** 337 // 338 // The following are defines for the bit fields in the MCASP_O_PDIN register. 339 // 340 //****************************************************************************** 341 #define MCASP_PDIN_AFSR 0x80000000 342 #define MCASP_PDIN_AHCLKR 0x40000000 343 #define MCASP_PDIN_ACLKR 0x20000000 344 #define MCASP_PDIN_AFSX 0x10000000 345 #define MCASP_PDIN_AHCLKX 0x08000000 346 #define MCASP_PDIN_ACLKX 0x04000000 347 #define MCASP_PDIN_AMUTE 0x02000000 348 #define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved 349 #define MCASP_PDIN_RESV_S 16 350 #define MCASP_PDIN_AXR15 0x00008000 351 #define MCASP_PDIN_AXR14 0x00004000 352 #define MCASP_PDIN_AXR13 0x00002000 353 #define MCASP_PDIN_AXR12 0x00001000 354 #define MCASP_PDIN_AXR11 0x00000800 355 #define MCASP_PDIN_AXR10 0x00000400 356 #define MCASP_PDIN_AXR9 0x00000200 357 #define MCASP_PDIN_AXR8 0x00000100 358 #define MCASP_PDIN_AXR7 0x00000080 359 #define MCASP_PDIN_AXR6 0x00000040 360 #define MCASP_PDIN_AXR5 0x00000020 361 #define MCASP_PDIN_AXR4 0x00000010 362 #define MCASP_PDIN_AXR3 0x00000008 363 #define MCASP_PDIN_AXR2 0x00000004 364 #define MCASP_PDIN_AXR1 0x00000002 365 #define MCASP_PDIN_AXR0 0x00000001 366 //****************************************************************************** 367 // 368 // The following are defines for the bit fields in the MCASP_O_PDCLR register. 369 // 370 //****************************************************************************** 371 #define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1 372 #define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1 373 #define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1 374 #define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1 375 #define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1 376 #define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1 377 #define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1 378 #define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved 379 #define MCASP_PDCLR_RESV_S 16 380 #define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1 381 #define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1 382 #define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1 383 #define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1 384 #define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1 385 #define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1 386 #define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1 387 #define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1 388 #define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1 389 #define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1 390 #define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1 391 #define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1 392 #define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1 393 #define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1 394 #define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1 395 #define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1 396 //****************************************************************************** 397 // 398 // The following are defines for the bit fields in the MCASP_O_TLGC register. 399 // 400 //****************************************************************************** 401 #define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved 402 #define MCASP_TLGC_RESV_S 16 403 #define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0 404 // 0x1 0x2 0x3 405 #define MCASP_TLGC_MT_S 14 406 #define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved 407 #define MCASP_TLGC_RESV1_S 9 408 #define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1 409 #define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1 410 #define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1 411 #define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3 412 #define MCASP_TLGC_MC_S 4 413 #define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4 414 // 0x5 0x6 0x7 415 #define MCASP_TLGC_PC_S 1 416 #define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this 417 // bit 0 1 418 //****************************************************************************** 419 // 420 // The following are defines for the bit fields in the MCASP_O_TLMR register. 421 // 422 //****************************************************************************** 423 #define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature. 424 #define MCASP_TLMR_TLMR_S 0 425 //****************************************************************************** 426 // 427 // The following are defines for the bit fields in the MCASP_O_TLEC register. 428 // 429 //****************************************************************************** 430 #define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during 431 // which MISR sig will be 432 // accumulated. 433 #define MCASP_TLEC_TLEC_S 0 434 //****************************************************************************** 435 // 436 // The following are defines for the bit fields in the MCASP_O_GBLCTL register. 437 // 438 //****************************************************************************** 439 #define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1 440 #define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1 441 #define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1 442 #define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 443 #define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1 444 #define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1 445 #define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1 446 #define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1 447 #define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 448 #define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1 449 //****************************************************************************** 450 // 451 // The following are defines for the bit fields in the MCASP_O_AMUTE register. 452 // 453 //****************************************************************************** 454 #define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1 455 #define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1 456 #define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1 457 #define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1 458 #define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1 459 #define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1 460 #define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1 461 #define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1 462 #define MCASP_AMUTE_INSTAT 0x00000010 463 #define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in 464 // active 0 1 465 #define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1 466 #define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2 467 #define MCASP_AMUTE_MUTEN_S 0 468 //****************************************************************************** 469 // 470 // The following are defines for the bit fields in the MCASP_O_LBCTL register. 471 // 472 //****************************************************************************** 473 #define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1 474 #define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator 475 // 0x0 0x1 0x2 0x3 476 #define MCASP_LBCTL_MODE_S 2 477 #define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1 478 #define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1 479 //****************************************************************************** 480 // 481 // The following are defines for the bit fields in the MCASP_O_TXDITCTL register. 482 // 483 //****************************************************************************** 484 #define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1 485 #define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1 486 #define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1 487 //****************************************************************************** 488 // 489 // The following are defines for the bit fields in the MCASP_O_GBLCTLR register. 490 // 491 //****************************************************************************** 492 #define MCASP_GBLCTLR_XFRST 0x00001000 493 #define MCASP_GBLCTLR_XSMRST 0x00000800 494 #define MCASP_GBLCTLR_XSRCLR 0x00000400 495 #define MCASP_GBLCTLR_XHCLKRST 0x00000200 496 #define MCASP_GBLCTLR_XCLKRST 0x00000100 497 #define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1 498 #define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1 499 #define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1 500 #define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 501 #define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1 502 //****************************************************************************** 503 // 504 // The following are defines for the bit fields in the MCASP_O_RXMASK register. 505 // 506 //****************************************************************************** 507 #define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1 508 #define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1 509 #define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1 510 #define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1 511 #define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1 512 #define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1 513 #define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1 514 #define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1 515 #define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1 516 #define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1 517 #define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1 518 #define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1 519 #define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1 520 #define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1 521 #define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1 522 #define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1 523 #define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1 524 #define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1 525 #define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1 526 #define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1 527 #define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1 528 #define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1 529 #define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1 530 #define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1 531 #define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1 532 #define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1 533 #define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1 534 #define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1 535 #define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1 536 #define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1 537 #define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1 538 #define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1 539 //****************************************************************************** 540 // 541 // The following are defines for the bit fields in the MCASP_O_RXFMT register. 542 // 543 //****************************************************************************** 544 #define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit 545 // delay 0x1 1 Bit delay 0x2 2 Bit 546 // delay 547 #define MCASP_RXFMT_RDATDLY_S 16 548 #define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1 549 #define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 550 #define MCASP_RXFMT_RPAD_S 13 551 #define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position 552 #define MCASP_RXFMT_RPBIT_S 8 553 #define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3 554 // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 555 // 0xC 0xD 0xE 0xF 556 #define MCASP_RXFMT_RSSZ_S 4 557 #define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0 558 // DMA port access 1 CPU port Access 559 #define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 560 // 0x3 0x4 0x5 0x6 0x7 561 #define MCASP_RXFMT_RROT_S 0 562 //****************************************************************************** 563 // 564 // The following are defines for the bit fields in the MCASP_O_RXFMCTL register. 565 // 566 //****************************************************************************** 567 #define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode 568 #define MCASP_RXFMCTL_RMOD_S 7 569 #define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1 570 #define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1 571 #define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1 572 //****************************************************************************** 573 // 574 // The following are defines for the bit fields in the MCASP_O_ACLKRCTL register. 575 // 576 //****************************************************************************** 577 #define MCASP_ACLKRCTL_BUSY 0x00100000 578 #define MCASP_ACLKRCTL_DIVBUSY 0x00080000 579 #define MCASP_ACLKRCTL_ADJBUSY 0x00040000 580 #define MCASP_ACLKRCTL_CLKRADJ_M \ 581 0x00030000 582 583 #define MCASP_ACLKRCTL_CLKRADJ_S 16 584 #define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1 585 #define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1 586 #define MCASP_ACLKRCTL_CLKRDIV_M \ 587 0x0000001F // RCV clock devide ratio 588 589 #define MCASP_ACLKRCTL_CLKRDIV_S 0 590 //****************************************************************************** 591 // 592 // The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register. 593 // 594 //****************************************************************************** 595 #define MCASP_AHCLKRCTL_BUSY 0x00100000 596 #define MCASP_AHCLKRCTL_DIVBUSY 0x00080000 597 #define MCASP_AHCLKRCTL_ADJBUSY 0x00040000 598 #define MCASP_AHCLKRCTL_HCLKRADJ_M \ 599 0x00030000 600 601 #define MCASP_AHCLKRCTL_HCLKRADJ_S 16 602 #define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1 603 #define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before 604 // diviser 0 1 605 #define MCASP_AHCLKRCTL_HCLKRDIV_M \ 606 0x00000FFF // RCV clock Divide Ratio 607 608 #define MCASP_AHCLKRCTL_HCLKRDIV_S 0 609 //****************************************************************************** 610 // 611 // The following are defines for the bit fields in the MCASP_O_RXTDM register. 612 // 613 //****************************************************************************** 614 #define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31 615 // 0 1 616 #define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30 617 // 0 1 618 #define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29 619 // 0 1 620 #define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28 621 // 0 1 622 #define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27 623 // 0 1 624 #define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26 625 // 0 1 626 #define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25 627 // 0 1 628 #define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24 629 // 0 1 630 #define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23 631 // 0 1 632 #define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22 633 // 0 1 634 #define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21 635 // 0 1 636 #define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20 637 // 0 1 638 #define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19 639 // 0 1 640 #define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18 641 // 0 1 642 #define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17 643 // 0 1 644 #define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16 645 // 0 1 646 #define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15 647 // 0 1 648 #define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14 649 // 0 1 650 #define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13 651 // 0 1 652 #define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12 653 // 0 1 654 #define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11 655 // 0 1 656 #define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10 657 // 0 1 658 #define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9 659 // 0 1 660 #define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8 661 // 0 1 662 #define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7 663 // 0 1 664 #define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6 665 // 0 1 666 #define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5 667 // 0 1 668 #define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4 669 // 0 1 670 #define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3 671 // 0 1 672 #define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2 673 // 0 1 674 #define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1 675 // 0 1 676 #define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0 677 // 0 1 678 //****************************************************************************** 679 // 680 // The following are defines for the bit fields in the MCASP_O_EVTCTLR register. 681 // 682 //****************************************************************************** 683 #define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1 684 #define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1 685 #define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1 686 #define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1 687 #define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 688 #define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1 689 #define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1 690 //****************************************************************************** 691 // 692 // The following are defines for the bit fields in the MCASP_O_RXSTAT register. 693 // 694 //****************************************************************************** 695 #define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1 696 #define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1 697 #define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1 698 #define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1 699 #define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1 700 #define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1 701 #define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1 702 #define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0 703 // 1 704 #define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1 705 //****************************************************************************** 706 // 707 // The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register. 708 // 709 //****************************************************************************** 710 #define MCASP_RXTDMSLOT_RSLOTCNT_M \ 711 0x000003FF // Current RCV time slot count 712 713 #define MCASP_RXTDMSLOT_RSLOTCNT_S 0 714 //****************************************************************************** 715 // 716 // The following are defines for the bit fields in the MCASP_O_RXCLKCHK register. 717 // 718 //****************************************************************************** 719 #define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value 720 #define MCASP_RXCLKCHK_RCNT_S 24 721 #define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary 722 #define MCASP_RXCLKCHK_RMAX_S 16 723 #define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary 724 #define MCASP_RXCLKCHK_RMIN_S 8 725 #define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0 726 // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 727 #define MCASP_RXCLKCHK_RPS_S 0 728 //****************************************************************************** 729 // 730 // The following are defines for the bit fields in the MCASP_O_REVTCTL register. 731 // 732 //****************************************************************************** 733 #define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable 734 // DMA Transfer 1 Disable DMA 735 // Transfer 736 //****************************************************************************** 737 // 738 // The following are defines for the bit fields in the MCASP_O_GBLCTLX register. 739 // 740 //****************************************************************************** 741 #define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1 742 #define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1 743 #define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1 744 #define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 745 #define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1 746 #define MCASP_GBLCTLX_RFRST 0x00000010 747 #define MCASP_GBLCTLX_RSMRST 0x00000008 748 #define MCASP_GBLCTLX_RSRCLKR 0x00000004 749 #define MCASP_GBLCTLX_RHCLKRST 0x00000002 750 #define MCASP_GBLCTLX_RCLKRST 0x00000001 751 //****************************************************************************** 752 // 753 // The following are defines for the bit fields in the MCASP_O_TXMASK register. 754 // 755 //****************************************************************************** 756 #define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1 757 #define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1 758 #define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1 759 #define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1 760 #define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1 761 #define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1 762 #define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1 763 #define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1 764 #define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1 765 #define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1 766 #define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1 767 #define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1 768 #define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1 769 #define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1 770 #define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1 771 #define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1 772 #define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1 773 #define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1 774 #define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1 775 #define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1 776 #define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1 777 #define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1 778 #define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1 779 #define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1 780 #define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1 781 #define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1 782 #define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1 783 #define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1 784 #define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1 785 #define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1 786 #define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1 787 #define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1 788 //****************************************************************************** 789 // 790 // The following are defines for the bit fields in the MCASP_O_TXFMT register. 791 // 792 //****************************************************************************** 793 #define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit 794 // delay 0x1 1 Bit delay 0x2 2 Bit 795 // delay 796 #define MCASP_TXFMT_XDATDLY_S 16 797 #define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1 798 #define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 799 #define MCASP_TXFMT_XPAD_S 13 800 #define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position 801 #define MCASP_TXFMT_XPBIT_S 8 802 #define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3 803 // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 804 // 0xC 0xD 0xE 0xF 805 #define MCASP_TXFMT_XSSZ_S 4 806 #define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0 807 // DMA port access 1 CPU port Access 808 #define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 809 // 0x3 0x4 0x5 0x6 0x7 810 #define MCASP_TXFMT_XROT_S 0 811 //****************************************************************************** 812 // 813 // The following are defines for the bit fields in the MCASP_O_TXFMCTL register. 814 // 815 //****************************************************************************** 816 #define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode 817 #define MCASP_TXFMCTL_XMOD_S 7 818 #define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1 819 #define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1 820 #define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1 821 //****************************************************************************** 822 // 823 // The following are defines for the bit fields in the MCASP_O_ACLKXCTL register. 824 // 825 //****************************************************************************** 826 #define MCASP_ACLKXCTL_BUSY 0x00100000 827 #define MCASP_ACLKXCTL_DIVBUSY 0x00080000 828 #define MCASP_ACLKXCTL_ADJBUSY 0x00040000 829 #define MCASP_ACLKXCTL_CLKXADJ_M \ 830 0x00030000 831 832 #define MCASP_ACLKXCTL_CLKXADJ_S 16 833 #define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1 834 #define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0 835 // 1 836 #define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1 837 #define MCASP_ACLKXCTL_CLKXDIV_M \ 838 0x0000001F // XMT clock devide ratio 839 840 #define MCASP_ACLKXCTL_CLKXDIV_S 0 841 //****************************************************************************** 842 // 843 // The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register. 844 // 845 //****************************************************************************** 846 #define MCASP_AHCLKXCTL_BUSY 0x00100000 847 #define MCASP_AHCLKXCTL_DIVBUSY 0x00080000 848 #define MCASP_AHCLKXCTL_ADJBUSY 0x00040000 849 #define MCASP_AHCLKXCTL_HCLKXADJ_M \ 850 0x00030000 851 852 #define MCASP_AHCLKXCTL_HCLKXADJ_S 16 853 #define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1 854 #define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before 855 // diviser 0 1 856 #define MCASP_AHCLKXCTL_HCLKXDIV_M \ 857 0x00000FFF // XMT clock Divide Ratio 858 859 #define MCASP_AHCLKXCTL_HCLKXDIV_S 0 860 //****************************************************************************** 861 // 862 // The following are defines for the bit fields in the MCASP_O_TXTDM register. 863 // 864 //****************************************************************************** 865 #define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31 866 // 0 1 867 #define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30 868 // 0 1 869 #define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29 870 // 0 1 871 #define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28 872 // 0 1 873 #define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27 874 // 0 1 875 #define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26 876 // 0 1 877 #define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25 878 // 0 1 879 #define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24 880 // 0 1 881 #define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23 882 // 0 1 883 #define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22 884 // 0 1 885 #define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21 886 // 0 1 887 #define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20 888 // 0 1 889 #define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19 890 // 0 1 891 #define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18 892 // 0 1 893 #define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17 894 // 0 1 895 #define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16 896 // 0 1 897 #define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15 898 // 0 1 899 #define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14 900 // 0 1 901 #define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13 902 // 0 1 903 #define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12 904 // 0 1 905 #define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11 906 // 0 1 907 #define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10 908 // 0 1 909 #define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9 910 // 0 1 911 #define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8 912 // 0 1 913 #define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7 914 // 0 1 915 #define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6 916 // 0 1 917 #define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5 918 // 0 1 919 #define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4 920 // 0 1 921 #define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3 922 // 0 1 923 #define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2 924 // 0 1 925 #define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1 926 // 0 1 927 #define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0 928 // 0 1 929 //****************************************************************************** 930 // 931 // The following are defines for the bit fields in the MCASP_O_EVTCTLX register. 932 // 933 //****************************************************************************** 934 #define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1 935 #define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1 936 #define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1 937 #define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1 938 #define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 939 #define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1 940 #define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1 941 //****************************************************************************** 942 // 943 // The following are defines for the bit fields in the MCASP_O_TXSTAT register. 944 // 945 //****************************************************************************** 946 #define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1 947 #define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1 948 #define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1 949 #define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1 950 #define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1 951 #define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1 952 #define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1 953 #define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0 954 // 1 955 #define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1 956 //****************************************************************************** 957 // 958 // The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register. 959 // 960 //****************************************************************************** 961 #define MCASP_TXTDMSLOT_XSLOTCNT_M \ 962 0x000003FF // Current XMT time slot count 963 // during reset the value of this 964 // register is 0b0101111111 (0x17f) 965 // and after reset 0 966 967 #define MCASP_TXTDMSLOT_XSLOTCNT_S 0 968 //****************************************************************************** 969 // 970 // The following are defines for the bit fields in the MCASP_O_TXCLKCHK register. 971 // 972 //****************************************************************************** 973 #define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value 974 #define MCASP_TXCLKCHK_XCNT_S 24 975 #define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary 976 #define MCASP_TXCLKCHK_XMAX_S 16 977 #define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary 978 #define MCASP_TXCLKCHK_XMIN_S 8 979 #define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved 980 #define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0 981 // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 982 #define MCASP_TXCLKCHK_XPS_S 0 983 //****************************************************************************** 984 // 985 // The following are defines for the bit fields in the MCASP_O_XEVTCTL register. 986 // 987 //****************************************************************************** 988 #define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable 989 // DMA Transfer 1 Disable DMA 990 // Transfer 991 //****************************************************************************** 992 // 993 // The following are defines for the bit fields in the MCASP_O_CLKADJEN register. 994 // 995 //****************************************************************************** 996 #define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1 997 //****************************************************************************** 998 // 999 // The following are defines for the bit fields in the MCASP_O_DITCSRA0 register. 1000 // 1001 //****************************************************************************** 1002 #define MCASP_DITCSRA0_DITCSRA0_M \ 1003 0xFFFFFFFF // Left (Even TDM slot ) Channel 1004 // status 1005 1006 #define MCASP_DITCSRA0_DITCSRA0_S 0 1007 //****************************************************************************** 1008 // 1009 // The following are defines for the bit fields in the MCASP_O_DITCSRA1 register. 1010 // 1011 //****************************************************************************** 1012 #define MCASP_DITCSRA1_DITCSRA1_M \ 1013 0xFFFFFFFF // Left (Even TDM slot ) Channel 1014 // status 1015 1016 #define MCASP_DITCSRA1_DITCSRA1_S 0 1017 //****************************************************************************** 1018 // 1019 // The following are defines for the bit fields in the MCASP_O_DITCSRA2 register. 1020 // 1021 //****************************************************************************** 1022 #define MCASP_DITCSRA2_DITCSRA2_M \ 1023 0xFFFFFFFF // Left (Even TDM slot ) Channel 1024 // status Register 1025 1026 #define MCASP_DITCSRA2_DITCSRA2_S 0 1027 //****************************************************************************** 1028 // 1029 // The following are defines for the bit fields in the MCASP_O_DITCSRA3 register. 1030 // 1031 //****************************************************************************** 1032 #define MCASP_DITCSRA3_DITCSRA3_M \ 1033 0xFFFFFFFF // Left (Even TDM slot ) Channel 1034 // status Register 1035 1036 #define MCASP_DITCSRA3_DITCSRA3_S 0 1037 //****************************************************************************** 1038 // 1039 // The following are defines for the bit fields in the MCASP_O_DITCSRA4 register. 1040 // 1041 //****************************************************************************** 1042 #define MCASP_DITCSRA4_DITCSRA4_M \ 1043 0xFFFFFFFF // Left (Even TDM slot ) Channel 1044 // status 1045 1046 #define MCASP_DITCSRA4_DITCSRA4_S 0 1047 //****************************************************************************** 1048 // 1049 // The following are defines for the bit fields in the MCASP_O_DITCSRA5 register. 1050 // 1051 //****************************************************************************** 1052 #define MCASP_DITCSRA5_DITCSRA5_M \ 1053 0xFFFFFFFF // Left (Even TDM slot ) Channel 1054 // status 1055 1056 #define MCASP_DITCSRA5_DITCSRA5_S 0 1057 //****************************************************************************** 1058 // 1059 // The following are defines for the bit fields in the MCASP_O_DITCSRB0 register. 1060 // 1061 //****************************************************************************** 1062 #define MCASP_DITCSRB0_DITCSRB0_M \ 1063 0xFFFFFFFF // Right (odd TDM slot ) Channel 1064 // status 1065 1066 #define MCASP_DITCSRB0_DITCSRB0_S 0 1067 //****************************************************************************** 1068 // 1069 // The following are defines for the bit fields in the MCASP_O_DITCSRB1 register. 1070 // 1071 //****************************************************************************** 1072 #define MCASP_DITCSRB1_DITCSRB1_M \ 1073 0xFFFFFFFF // Right (odd TDM slot ) Channel 1074 // status 1075 1076 #define MCASP_DITCSRB1_DITCSRB1_S 0 1077 //****************************************************************************** 1078 // 1079 // The following are defines for the bit fields in the MCASP_O_DITCSRB2 register. 1080 // 1081 //****************************************************************************** 1082 #define MCASP_DITCSRB2_DITCSRB2_M \ 1083 0xFFFFFFFF // Right (odd TDM slot ) Channel 1084 // status 1085 1086 #define MCASP_DITCSRB2_DITCSRB2_S 0 1087 //****************************************************************************** 1088 // 1089 // The following are defines for the bit fields in the MCASP_O_DITCSRB3 register. 1090 // 1091 //****************************************************************************** 1092 #define MCASP_DITCSRB3_DITCSRB3_M \ 1093 0xFFFFFFFF // Right (odd TDM slot ) Channel 1094 // status 1095 1096 #define MCASP_DITCSRB3_DITCSRB3_S 0 1097 //****************************************************************************** 1098 // 1099 // The following are defines for the bit fields in the MCASP_O_DITCSRB4 register. 1100 // 1101 //****************************************************************************** 1102 #define MCASP_DITCSRB4_DITCSRB4_M \ 1103 0xFFFFFFFF // Right (odd TDM slot ) Channel 1104 // status 1105 1106 #define MCASP_DITCSRB4_DITCSRB4_S 0 1107 //****************************************************************************** 1108 // 1109 // The following are defines for the bit fields in the MCASP_O_DITCSRB5 register. 1110 // 1111 //****************************************************************************** 1112 #define MCASP_DITCSRB5_DITCSRB5_M \ 1113 0xFFFFFFFF // Right (odd TDM slot ) Channel 1114 // status 1115 1116 #define MCASP_DITCSRB5_DITCSRB5_S 0 1117 //****************************************************************************** 1118 // 1119 // The following are defines for the bit fields in the MCASP_O_DITUDRA0 register. 1120 // 1121 //****************************************************************************** 1122 #define MCASP_DITUDRA0_DITUDRA0_M \ 1123 0xFFFFFFFF // Left (Even TDM slot ) User Data 1124 1125 #define MCASP_DITUDRA0_DITUDRA0_S 0 1126 //****************************************************************************** 1127 // 1128 // The following are defines for the bit fields in the MCASP_O_DITUDRA1 register. 1129 // 1130 //****************************************************************************** 1131 #define MCASP_DITUDRA1_DITUDRA1_M \ 1132 0xFFFFFFFF // Left (Even TDM slot ) User Data 1133 1134 #define MCASP_DITUDRA1_DITUDRA1_S 0 1135 //****************************************************************************** 1136 // 1137 // The following are defines for the bit fields in the MCASP_O_DITUDRA2 register. 1138 // 1139 //****************************************************************************** 1140 #define MCASP_DITUDRA2_DITUDRA2_M \ 1141 0xFFFFFFFF // Left (Even TDM slot ) User Data 1142 1143 #define MCASP_DITUDRA2_DITUDRA2_S 0 1144 //****************************************************************************** 1145 // 1146 // The following are defines for the bit fields in the MCASP_O_DITUDRA3 register. 1147 // 1148 //****************************************************************************** 1149 #define MCASP_DITUDRA3_DITUDRA3_M \ 1150 0xFFFFFFFF // Left (Even TDM slot ) User Data 1151 1152 #define MCASP_DITUDRA3_DITUDRA3_S 0 1153 //****************************************************************************** 1154 // 1155 // The following are defines for the bit fields in the MCASP_O_DITUDRA4 register. 1156 // 1157 //****************************************************************************** 1158 #define MCASP_DITUDRA4_DITUDRA4_M \ 1159 0xFFFFFFFF // Left (Even TDM slot ) User Data 1160 1161 #define MCASP_DITUDRA4_DITUDRA4_S 0 1162 //****************************************************************************** 1163 // 1164 // The following are defines for the bit fields in the MCASP_O_DITUDRA5 register. 1165 // 1166 //****************************************************************************** 1167 #define MCASP_DITUDRA5_DITUDRA5_M \ 1168 0xFFFFFFFF // Left (Even TDM slot ) User Data 1169 1170 #define MCASP_DITUDRA5_DITUDRA5_S 0 1171 //****************************************************************************** 1172 // 1173 // The following are defines for the bit fields in the MCASP_O_DITUDRB0 register. 1174 // 1175 //****************************************************************************** 1176 #define MCASP_DITUDRB0_DITUDRB0_M \ 1177 0xFFFFFFFF // Right (odd TDM slot ) User Data 1178 1179 #define MCASP_DITUDRB0_DITUDRB0_S 0 1180 //****************************************************************************** 1181 // 1182 // The following are defines for the bit fields in the MCASP_O_DITUDRB1 register. 1183 // 1184 //****************************************************************************** 1185 #define MCASP_DITUDRB1_DITUDRB1_M \ 1186 0xFFFFFFFF // Right (odd TDM slot ) User Data 1187 1188 #define MCASP_DITUDRB1_DITUDRB1_S 0 1189 //****************************************************************************** 1190 // 1191 // The following are defines for the bit fields in the MCASP_O_DITUDRB2 register. 1192 // 1193 //****************************************************************************** 1194 #define MCASP_DITUDRB2_DITUDRB2_M \ 1195 0xFFFFFFFF // Right (odd TDM slot ) User Data 1196 1197 #define MCASP_DITUDRB2_DITUDRB2_S 0 1198 //****************************************************************************** 1199 // 1200 // The following are defines for the bit fields in the MCASP_O_DITUDRB3 register. 1201 // 1202 //****************************************************************************** 1203 #define MCASP_DITUDRB3_DITUDRB3_M \ 1204 0xFFFFFFFF // Right (odd TDM slot ) User Data 1205 1206 #define MCASP_DITUDRB3_DITUDRB3_S 0 1207 //****************************************************************************** 1208 // 1209 // The following are defines for the bit fields in the MCASP_O_DITUDRB4 register. 1210 // 1211 //****************************************************************************** 1212 #define MCASP_DITUDRB4_DITUDRB4_M \ 1213 0xFFFFFFFF // Right (odd TDM slot ) User Data 1214 1215 #define MCASP_DITUDRB4_DITUDRB4_S 0 1216 //****************************************************************************** 1217 // 1218 // The following are defines for the bit fields in the MCASP_O_DITUDRB5 register. 1219 // 1220 //****************************************************************************** 1221 #define MCASP_DITUDRB5_DITUDRB5_M \ 1222 0xFFFFFFFF // Right (odd TDM slot ) User Data 1223 1224 #define MCASP_DITUDRB5_DITUDRB5_S 0 1225 //****************************************************************************** 1226 // 1227 // The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register. 1228 // 1229 //****************************************************************************** 1230 #define MCASP_XRSRCTL0_RRDY 0x00000020 1231 #define MCASP_XRSRCTL0_XRDY 0x00000010 1232 #define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1233 // state 0x1 Reserved 0x2 Drive pin 1234 // low 0x3 Drive pin high 1235 #define MCASP_XRSRCTL0_DISMOD_S 2 1236 #define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1237 // mode 0x1 Transmit mode 0x2 1238 // Receive mode 1239 #define MCASP_XRSRCTL0_SRMOD_S 0 1240 //****************************************************************************** 1241 // 1242 // The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register. 1243 // 1244 //****************************************************************************** 1245 #define MCASP_XRSRCTL1_RRDY 0x00000020 1246 #define MCASP_XRSRCTL1_XRDY 0x00000010 1247 #define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1248 // state 0x1 Reserved 0x2 Drive pin 1249 // low 0x3 Drive pin high 1250 #define MCASP_XRSRCTL1_DISMOD_S 2 1251 #define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1252 // mode 0x1 Transmit mode 0x2 1253 // Receive mode 1254 #define MCASP_XRSRCTL1_SRMOD_S 0 1255 //****************************************************************************** 1256 // 1257 // The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register. 1258 // 1259 //****************************************************************************** 1260 #define MCASP_XRSRCTL2_RRDY 0x00000020 1261 #define MCASP_XRSRCTL2_XRDY 0x00000010 1262 #define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1263 // state 0x1 Reserved 0x2 Drive pin 1264 // low 0x3 Drive pin high 1265 #define MCASP_XRSRCTL2_DISMOD_S 2 1266 #define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1267 // mode 0x1 Transmit mode 0x2 1268 // Receive mode 1269 #define MCASP_XRSRCTL2_SRMOD_S 0 1270 //****************************************************************************** 1271 // 1272 // The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register. 1273 // 1274 //****************************************************************************** 1275 #define MCASP_XRSRCTL3_RRDY 0x00000020 1276 #define MCASP_XRSRCTL3_XRDY 0x00000010 1277 #define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1278 // state 0x1 Reserved 0x2 Drive pin 1279 // low 0x3 Drive pin high 1280 #define MCASP_XRSRCTL3_DISMOD_S 2 1281 #define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1282 // mode 0x1 Transmit mode 0x2 1283 // Receive mode 1284 #define MCASP_XRSRCTL3_SRMOD_S 0 1285 //****************************************************************************** 1286 // 1287 // The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register. 1288 // 1289 //****************************************************************************** 1290 #define MCASP_XRSRCTL4_RRDY 0x00000020 1291 #define MCASP_XRSRCTL4_XRDY 0x00000010 1292 #define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1293 // state 0x1 Reserved 0x2 Drive pin 1294 // low 0x3 Drive pin high 1295 #define MCASP_XRSRCTL4_DISMOD_S 2 1296 #define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1297 // mode 0x1 Transmit mode 0x2 1298 // Receive mode 1299 #define MCASP_XRSRCTL4_SRMOD_S 0 1300 //****************************************************************************** 1301 // 1302 // The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register. 1303 // 1304 //****************************************************************************** 1305 #define MCASP_XRSRCTL5_RRDY 0x00000020 1306 #define MCASP_XRSRCTL5_XRDY 0x00000010 1307 #define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1308 // state 0x1 Reserved 0x2 Drive pin 1309 // low 0x3 Drive pin high 1310 #define MCASP_XRSRCTL5_DISMOD_S 2 1311 #define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1312 // mode 0x1 Transmit mode 0x2 1313 // Receive mode 1314 #define MCASP_XRSRCTL5_SRMOD_S 0 1315 //****************************************************************************** 1316 // 1317 // The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register. 1318 // 1319 //****************************************************************************** 1320 #define MCASP_XRSRCTL6_RRDY 0x00000020 1321 #define MCASP_XRSRCTL6_XRDY 0x00000010 1322 #define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1323 // state 0x1 Reserved 0x2 Drive pin 1324 // low 0x3 Drive pin high 1325 #define MCASP_XRSRCTL6_DISMOD_S 2 1326 #define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1327 // mode 0x1 Transmit mode 0x2 1328 // Receive mode 1329 #define MCASP_XRSRCTL6_SRMOD_S 0 1330 //****************************************************************************** 1331 // 1332 // The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register. 1333 // 1334 //****************************************************************************** 1335 #define MCASP_XRSRCTL7_RRDY 0x00000020 1336 #define MCASP_XRSRCTL7_XRDY 0x00000010 1337 #define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1338 // state 0x1 Reserved 0x2 Drive pin 1339 // low 0x3 Drive pin high 1340 #define MCASP_XRSRCTL7_DISMOD_S 2 1341 #define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1342 // mode 0x1 Transmit mode 0x2 1343 // Receive mode 1344 #define MCASP_XRSRCTL7_SRMOD_S 0 1345 //****************************************************************************** 1346 // 1347 // The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register. 1348 // 1349 //****************************************************************************** 1350 #define MCASP_XRSRCTL8_RRDY 0x00000020 1351 #define MCASP_XRSRCTL8_XRDY 0x00000010 1352 #define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1353 // state 0x1 Reserved 0x2 Drive pin 1354 // low 0x3 Drive pin high 1355 #define MCASP_XRSRCTL8_DISMOD_S 2 1356 #define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1357 // mode 0x1 Transmit mode 0x2 1358 // Receive mode 1359 #define MCASP_XRSRCTL8_SRMOD_S 0 1360 //****************************************************************************** 1361 // 1362 // The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register. 1363 // 1364 //****************************************************************************** 1365 #define MCASP_XRSRCTL9_RRDY 0x00000020 1366 #define MCASP_XRSRCTL9_XRDY 0x00000010 1367 #define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri 1368 // state 0x1 Reserved 0x2 Drive pin 1369 // low 0x3 Drive pin high 1370 #define MCASP_XRSRCTL9_DISMOD_S 2 1371 #define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1372 // mode 0x1 Transmit mode 0x2 1373 // Receive mode 1374 #define MCASP_XRSRCTL9_SRMOD_S 0 1375 //****************************************************************************** 1376 // 1377 // The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register. 1378 // 1379 //****************************************************************************** 1380 #define MCASP_XRSRCTL10_RRDY 0x00000020 1381 #define MCASP_XRSRCTL10_XRDY 0x00000010 1382 #define MCASP_XRSRCTL10_DISMOD_M \ 1383 0x0000000C // Serializer drive state 0x0 Tri 1384 // state 0x1 Reserved 0x2 Drive pin 1385 // low 0x3 Drive pin high 1386 1387 #define MCASP_XRSRCTL10_DISMOD_S 2 1388 #define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1389 // mode 0x1 Transmit mode 0x2 1390 // Receive mode 1391 #define MCASP_XRSRCTL10_SRMOD_S 0 1392 //****************************************************************************** 1393 // 1394 // The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register. 1395 // 1396 //****************************************************************************** 1397 #define MCASP_XRSRCTL11_RRDY 0x00000020 1398 #define MCASP_XRSRCTL11_XRDY 0x00000010 1399 #define MCASP_XRSRCTL11_DISMOD_M \ 1400 0x0000000C // Serializer drive state 0x0 Tri 1401 // state 0x1 Reserved 0x2 Drive pin 1402 // low 0x3 Drive pin high 1403 1404 #define MCASP_XRSRCTL11_DISMOD_S 2 1405 #define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1406 // mode 0x1 Transmit mode 0x2 1407 // Receive mode 1408 #define MCASP_XRSRCTL11_SRMOD_S 0 1409 //****************************************************************************** 1410 // 1411 // The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register. 1412 // 1413 //****************************************************************************** 1414 #define MCASP_XRSRCTL12_RRDY 0x00000020 1415 #define MCASP_XRSRCTL12_XRDY 0x00000010 1416 #define MCASP_XRSRCTL12_DISMOD_M \ 1417 0x0000000C // Serializer drive state 0x0 Tri 1418 // state 0x1 Reserved 0x2 Drive pin 1419 // low 0x3 Drive pin high 1420 1421 #define MCASP_XRSRCTL12_DISMOD_S 2 1422 #define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1423 // mode 0x1 Transmit mode 0x2 1424 // Receive mode 1425 #define MCASP_XRSRCTL12_SRMOD_S 0 1426 //****************************************************************************** 1427 // 1428 // The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register. 1429 // 1430 //****************************************************************************** 1431 #define MCASP_XRSRCTL13_RRDY 0x00000020 1432 #define MCASP_XRSRCTL13_XRDY 0x00000010 1433 #define MCASP_XRSRCTL13_DISMOD_M \ 1434 0x0000000C // Serializer drive state 0x0 Tri 1435 // state 0x1 Reserved 0x2 Drive pin 1436 // low 0x3 Drive pin high 1437 1438 #define MCASP_XRSRCTL13_DISMOD_S 2 1439 #define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1440 // mode 0x1 Transmit mode 0x2 1441 // Receive mode 1442 #define MCASP_XRSRCTL13_SRMOD_S 0 1443 //****************************************************************************** 1444 // 1445 // The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register. 1446 // 1447 //****************************************************************************** 1448 #define MCASP_XRSRCTL14_RRDY 0x00000020 1449 #define MCASP_XRSRCTL14_XRDY 0x00000010 1450 #define MCASP_XRSRCTL14_DISMOD_M \ 1451 0x0000000C // Serializer drive state 0x0 Tri 1452 // state 0x1 Reserved 0x2 Drive pin 1453 // low 0x3 Drive pin high 1454 1455 #define MCASP_XRSRCTL14_DISMOD_S 2 1456 #define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1457 // mode 0x1 Transmit mode 0x2 1458 // Receive mode 1459 #define MCASP_XRSRCTL14_SRMOD_S 0 1460 //****************************************************************************** 1461 // 1462 // The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register. 1463 // 1464 //****************************************************************************** 1465 #define MCASP_XRSRCTL15_RRDY 0x00000020 1466 #define MCASP_XRSRCTL15_XRDY 0x00000010 1467 #define MCASP_XRSRCTL15_DISMOD_M \ 1468 0x0000000C // Serializer drive state 0x0 Tri 1469 // state 0x1 Reserved 0x2 Drive pin 1470 // low 0x3 Drive pin high 1471 1472 #define MCASP_XRSRCTL15_DISMOD_S 2 1473 #define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive 1474 // mode 0x1 Transmit mode 0x2 1475 // Receive mode 1476 #define MCASP_XRSRCTL15_SRMOD_S 0 1477 //****************************************************************************** 1478 // 1479 // The following are defines for the bit fields in the MCASP_O_TXBUF0 register. 1480 // 1481 //****************************************************************************** 1482 #define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0 1483 #define MCASP_TXBUF0_XBUF0_S 0 1484 //****************************************************************************** 1485 // 1486 // The following are defines for the bit fields in the MCASP_O_TXBUF1 register. 1487 // 1488 //****************************************************************************** 1489 #define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1 1490 #define MCASP_TXBUF1_XBUF1_S 0 1491 //****************************************************************************** 1492 // 1493 // The following are defines for the bit fields in the MCASP_O_TXBUF2 register. 1494 // 1495 //****************************************************************************** 1496 #define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2 1497 #define MCASP_TXBUF2_XBUF2_S 0 1498 //****************************************************************************** 1499 // 1500 // The following are defines for the bit fields in the MCASP_O_TXBUF3 register. 1501 // 1502 //****************************************************************************** 1503 #define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3 1504 #define MCASP_TXBUF3_XBUF3_S 0 1505 //****************************************************************************** 1506 // 1507 // The following are defines for the bit fields in the MCASP_O_TXBUF4 register. 1508 // 1509 //****************************************************************************** 1510 #define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4 1511 #define MCASP_TXBUF4_XBUF4_S 0 1512 //****************************************************************************** 1513 // 1514 // The following are defines for the bit fields in the MCASP_O_TXBUF5 register. 1515 // 1516 //****************************************************************************** 1517 #define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5 1518 #define MCASP_TXBUF5_XBUF5_S 0 1519 //****************************************************************************** 1520 // 1521 // The following are defines for the bit fields in the MCASP_O_TXBUF6 register. 1522 // 1523 //****************************************************************************** 1524 #define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6 1525 #define MCASP_TXBUF6_XBUF6_S 0 1526 //****************************************************************************** 1527 // 1528 // The following are defines for the bit fields in the MCASP_O_TXBUF7 register. 1529 // 1530 //****************************************************************************** 1531 #define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7 1532 #define MCASP_TXBUF7_XBUF7_S 0 1533 //****************************************************************************** 1534 // 1535 // The following are defines for the bit fields in the MCASP_O_TXBUF8 register. 1536 // 1537 //****************************************************************************** 1538 #define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8 1539 #define MCASP_TXBUF8_XBUF8_S 0 1540 //****************************************************************************** 1541 // 1542 // The following are defines for the bit fields in the MCASP_O_TXBUF9 register. 1543 // 1544 //****************************************************************************** 1545 #define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9 1546 #define MCASP_TXBUF9_XBUF9_S 0 1547 //****************************************************************************** 1548 // 1549 // The following are defines for the bit fields in the MCASP_O_TXBUF10 register. 1550 // 1551 //****************************************************************************** 1552 #define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10 1553 #define MCASP_TXBUF10_XBUF10_S 0 1554 //****************************************************************************** 1555 // 1556 // The following are defines for the bit fields in the MCASP_O_TXBUF11 register. 1557 // 1558 //****************************************************************************** 1559 #define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11 1560 #define MCASP_TXBUF11_XBUF11_S 0 1561 //****************************************************************************** 1562 // 1563 // The following are defines for the bit fields in the MCASP_O_TXBUF12 register. 1564 // 1565 //****************************************************************************** 1566 #define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12 1567 #define MCASP_TXBUF12_XBUF12_S 0 1568 //****************************************************************************** 1569 // 1570 // The following are defines for the bit fields in the MCASP_O_TXBUF13 register. 1571 // 1572 //****************************************************************************** 1573 #define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13 1574 #define MCASP_TXBUF13_XBUF13_S 0 1575 //****************************************************************************** 1576 // 1577 // The following are defines for the bit fields in the MCASP_O_TXBUF14 register. 1578 // 1579 //****************************************************************************** 1580 #define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14 1581 #define MCASP_TXBUF14_XBUF14_S 0 1582 //****************************************************************************** 1583 // 1584 // The following are defines for the bit fields in the MCASP_O_TXBUF15 register. 1585 // 1586 //****************************************************************************** 1587 #define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15 1588 #define MCASP_TXBUF15_XBUF15_S 0 1589 //****************************************************************************** 1590 // 1591 // The following are defines for the bit fields in the MCASP_O_RXBUF0 register. 1592 // 1593 //****************************************************************************** 1594 #define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0 1595 #define MCASP_RXBUF0_RBUF0_S 0 1596 //****************************************************************************** 1597 // 1598 // The following are defines for the bit fields in the MCASP_O_RXBUF1 register. 1599 // 1600 //****************************************************************************** 1601 #define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1 1602 #define MCASP_RXBUF1_RBUF1_S 0 1603 //****************************************************************************** 1604 // 1605 // The following are defines for the bit fields in the MCASP_O_RXBUF2 register. 1606 // 1607 //****************************************************************************** 1608 #define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2 1609 #define MCASP_RXBUF2_RBUF2_S 0 1610 //****************************************************************************** 1611 // 1612 // The following are defines for the bit fields in the MCASP_O_RXBUF3 register. 1613 // 1614 //****************************************************************************** 1615 #define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3 1616 #define MCASP_RXBUF3_RBUF3_S 0 1617 //****************************************************************************** 1618 // 1619 // The following are defines for the bit fields in the MCASP_O_RXBUF4 register. 1620 // 1621 //****************************************************************************** 1622 #define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4 1623 #define MCASP_RXBUF4_RBUF4_S 0 1624 //****************************************************************************** 1625 // 1626 // The following are defines for the bit fields in the MCASP_O_RXBUF5 register. 1627 // 1628 //****************************************************************************** 1629 #define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5 1630 #define MCASP_RXBUF5_RBUF5_S 0 1631 //****************************************************************************** 1632 // 1633 // The following are defines for the bit fields in the MCASP_O_RXBUF6 register. 1634 // 1635 //****************************************************************************** 1636 #define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6 1637 #define MCASP_RXBUF6_RBUF6_S 0 1638 //****************************************************************************** 1639 // 1640 // The following are defines for the bit fields in the MCASP_O_RXBUF7 register. 1641 // 1642 //****************************************************************************** 1643 #define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7 1644 #define MCASP_RXBUF7_RBUF7_S 0 1645 //****************************************************************************** 1646 // 1647 // The following are defines for the bit fields in the MCASP_O_RXBUF8 register. 1648 // 1649 //****************************************************************************** 1650 #define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8 1651 #define MCASP_RXBUF8_RBUF8_S 0 1652 //****************************************************************************** 1653 // 1654 // The following are defines for the bit fields in the MCASP_O_RXBUF9 register. 1655 // 1656 //****************************************************************************** 1657 #define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9 1658 #define MCASP_RXBUF9_RBUF9_S 0 1659 //****************************************************************************** 1660 // 1661 // The following are defines for the bit fields in the MCASP_O_RXBUF10 register. 1662 // 1663 //****************************************************************************** 1664 #define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10 1665 #define MCASP_RXBUF10_RBUF10_S 0 1666 //****************************************************************************** 1667 // 1668 // The following are defines for the bit fields in the MCASP_O_RXBUF11 register. 1669 // 1670 //****************************************************************************** 1671 #define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11 1672 #define MCASP_RXBUF11_RBUF11_S 0 1673 //****************************************************************************** 1674 // 1675 // The following are defines for the bit fields in the MCASP_O_RXBUF12 register. 1676 // 1677 //****************************************************************************** 1678 #define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12 1679 #define MCASP_RXBUF12_RBUF12_S 0 1680 //****************************************************************************** 1681 // 1682 // The following are defines for the bit fields in the MCASP_O_RXBUF13 register. 1683 // 1684 //****************************************************************************** 1685 #define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13 1686 #define MCASP_RXBUF13_RBUF13_S 0 1687 //****************************************************************************** 1688 // 1689 // The following are defines for the bit fields in the MCASP_O_RXBUF14 register. 1690 // 1691 //****************************************************************************** 1692 #define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14 1693 #define MCASP_RXBUF14_RBUF14_S 0 1694 //****************************************************************************** 1695 // 1696 // The following are defines for the bit fields in the MCASP_O_RXBUF15 register. 1697 // 1698 //****************************************************************************** 1699 #define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15 1700 #define MCASP_RXBUF15_RBUF15_S 0 1701 1702 1703 1704 #endif // __HW_MCASP_H__ 1705
