1 /*
2  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOCFPGA_MBOX_H
8 #define SOCFPGA_MBOX_H
9 
10 #include <lib/utils_def.h>
11 
12 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
13 #define MBOX_OFFSET					0x10a30000
14 #else
15 #define MBOX_OFFSET					0xffa30000
16 #endif
17 
18 #define MBOX_ATF_CLIENT_ID				0x1U
19 #define MBOX_MAX_JOB_ID					0xFU
20 #define MBOX_MAX_IND_JOB_ID				(MBOX_MAX_JOB_ID - 1U)
21 #define MBOX_JOB_ID					MBOX_MAX_JOB_ID
22 #define MBOX_TEST_BIT					BIT(31)
23 
24 /* Mailbox Shared Memory Register Map */
25 #define MBOX_CIN					0x00
26 #define MBOX_ROUT					0x04
27 #define MBOX_URG					0x08
28 #define MBOX_INT					0x0C
29 #define MBOX_COUT					0x20
30 #define MBOX_RIN					0x24
31 #define MBOX_STATUS					0x2C
32 #define MBOX_CMD_BUFFER					0x40
33 #define MBOX_RESP_BUFFER				0xC0
34 
35 /* Mailbox SDM doorbell */
36 #define MBOX_DOORBELL_TO_SDM				0x400
37 #define MBOX_DOORBELL_FROM_SDM				0x480
38 
39 
40 /* Mailbox commands */
41 
42 #define MBOX_CMD_NOOP					0x00
43 #define MBOX_CMD_SYNC					0x01
44 #define MBOX_CMD_RESTART				0x02
45 #define MBOX_CMD_CANCEL					0x03
46 #define MBOX_CMD_VAB_SRC_CERT				0x0B
47 #define MBOX_CMD_GET_IDCODE				0x10
48 #define MBOX_CMD_GET_USERCODE				0x13
49 #define MBOX_CMD_GET_CHIPID				0x12
50 #define MBOX_CMD_REBOOT_HPS				0x47
51 
52 /* Reconfiguration Commands */
53 #define MBOX_CONFIG_STATUS				0x04
54 #define MBOX_RECONFIG					0x06
55 #define MBOX_RECONFIG_DATA				0x08
56 #define MBOX_RECONFIG_STATUS				0x09
57 
58 /* HWMON Commands */
59 #define MBOX_HWMON_READVOLT				0x18
60 #define MBOX_HWMON_READTEMP				0x19
61 
62 
63 /* QSPI Commands */
64 #define MBOX_CMD_QSPI_OPEN				0x32
65 #define MBOX_CMD_QSPI_CLOSE				0x33
66 #define MBOX_CMD_QSPI_SET_CS				0x34
67 #define MBOX_CMD_QSPI_DIRECT				0x3B
68 
69 /* SEU Commands */
70 #define MBOX_CMD_SEU_ERR_READ				0x3C
71 
72 /* RSU Commands */
73 #define MBOX_GET_SUBPARTITION_TABLE			0x5A
74 #define MBOX_RSU_STATUS					0x5B
75 #define MBOX_RSU_UPDATE					0x5C
76 #define MBOX_HPS_STAGE_NOTIFY				0x5D
77 
78 /* FCS Command */
79 #define MBOX_FCS_GET_PROVISION				0x7B
80 #define MBOX_FCS_CNTR_SET_PREAUTH			0x7C
81 #define MBOX_FCS_ENCRYPT_REQ				0x7E
82 #define MBOX_FCS_DECRYPT_REQ				0x7F
83 #define MBOX_FCS_RANDOM_GEN				0x80
84 #define MBOX_FCS_AES_CRYPT_REQ				0x81
85 #define MBOX_FCS_GET_DIGEST_REQ				0x82
86 #define MBOX_FCS_MAC_VERIFY_REQ				0x83
87 #define MBOX_FCS_ECDSA_HASH_SIGN_REQ			0x84
88 #define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ		0x85
89 #define MBOX_FCS_ECDSA_HASH_SIG_VERIFY			0x86
90 #define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY		0x87
91 #define MBOX_FCS_ECDSA_GET_PUBKEY			0x88
92 #define MBOX_FCS_ECDH_REQUEST				0x89
93 #define MBOX_FCS_OPEN_CS_SESSION			0xA0
94 #define MBOX_FCS_CLOSE_CS_SESSION			0xA1
95 #define MBOX_FCS_IMPORT_CS_KEY				0xA5
96 #define MBOX_FCS_EXPORT_CS_KEY				0xA6
97 #define MBOX_FCS_REMOVE_CS_KEY				0xA7
98 #define MBOX_FCS_GET_CS_KEY_INFO			0xA8
99 
100 /* PSG SIGMA Commands */
101 #define MBOX_PSG_SIGMA_TEARDOWN				0xD5
102 
103 /* Attestation Commands */
104 #define MBOX_CREATE_CERT_ON_RELOAD			0x180
105 #define MBOX_GET_ATTESTATION_CERT			0x181
106 #define MBOX_ATTESTATION_SUBKEY				0x182
107 #define MBOX_GET_MEASUREMENT				0x183
108 
109 /* Miscellaneous commands */
110 #define MBOX_GET_ROM_PATCH_SHA384	0x1B0
111 
112 /* Mailbox Definitions */
113 
114 #define CMD_DIRECT					0
115 #define CMD_INDIRECT					1
116 #define CMD_CASUAL					0
117 #define CMD_URGENT					1
118 
119 #define MBOX_WORD_BYTE					4U
120 #define MBOX_RESP_BUFFER_SIZE				16
121 #define MBOX_CMD_BUFFER_SIZE				32
122 #define MBOX_INC_HEADER_MAX_WORD_SIZE			1024U
123 
124 /* Execution states for HPS_STAGE_NOTIFY */
125 #define HPS_EXECUTION_STATE_FSBL			0
126 #define HPS_EXECUTION_STATE_SSBL			1
127 #define HPS_EXECUTION_STATE_OS				2
128 
129 /* Status Response */
130 #define MBOX_RET_OK					0
131 #define MBOX_RET_ERROR					-1
132 #define MBOX_NO_RESPONSE				-2
133 #define MBOX_WRONG_ID					-3
134 #define MBOX_BUFFER_FULL				-4
135 #define MBOX_BUSY					-5
136 #define MBOX_TIMEOUT					-2047
137 
138 /* Key Status */
139 #define MBOX_RET_SDOS_DECRYPTION_ERROR_102		-258
140 #define MBOX_RET_SDOS_DECRYPTION_ERROR_103		-259
141 
142 /* Reconfig Status Response */
143 #define RECONFIG_STATUS_STATE				0
144 #define RECONFIG_STATUS_PIN_STATUS			2
145 #define RECONFIG_STATUS_SOFTFUNC_STATUS			3
146 #define PIN_STATUS_NSTATUS				(U(1) << 31)
147 #define SOFTFUNC_STATUS_SEU_ERROR			(1 << 3)
148 #define SOFTFUNC_STATUS_INIT_DONE			(1 << 1)
149 #define SOFTFUNC_STATUS_CONF_DONE			(1 << 0)
150 #define MBOX_CFGSTAT_STATE_IDLE				0x00000000
151 #define MBOX_CFGSTAT_STATE_CONFIG			0x10000000
152 #define MBOX_CFGSTAT_VAB_BS_PREAUTH			0x20000000
153 #define MBOX_CFGSTAT_STATE_FAILACK			0x08000000
154 #define MBOX_CFGSTAT_STATE_ERROR_INVALID		0xf0000001
155 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT		0xf0000002
156 #define MBOX_CFGSTAT_STATE_ERROR_AUTH			0xf0000003
157 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO		0xf0000004
158 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE		0xf0000005
159 #define MBOX_CFGSTAT_STATE_ERROR_FAKE			0xf0000006
160 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO		0xf0000007
161 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR		0xf0000008
162 
163 
164 /* Mailbox Macros */
165 
166 #define MBOX_ENTRY_TO_ADDR(_buf, ptr)			(MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \
167 								+ MBOX_WORD_BYTE * (ptr))
168 
169 /* Mailbox interrupt flags and masks */
170 #define MBOX_INT_FLAG_COE				0x1
171 #define MBOX_INT_FLAG_RIE				0x2
172 #define MBOX_INT_FLAG_UAE				0x100
173 #define MBOX_COE_BIT(INTERRUPT)				((INTERRUPT) & 0x3)
174 #define MBOX_UAE_BIT(INTERRUPT)				(((INTERRUPT) & (1<<8)))
175 
176 /* Mailbox response and status */
177 #define MBOX_RESP_ERR(BUFFER)				((BUFFER) & 0x000007ff)
178 #define MBOX_RESP_LEN(BUFFER)				(((BUFFER) & 0x007ff000) >> 12)
179 #define MBOX_RESP_CLIENT_ID(BUFFER)			(((BUFFER) & 0xf0000000) >> 28)
180 #define MBOX_RESP_JOB_ID(BUFFER)			(((BUFFER) & 0x0f000000) >> 24)
181 #define MBOX_STATUS_UA_MASK				(1<<8)
182 
183 /* Mailbox command and response */
184 #define MBOX_CLIENT_ID_CMD(CLIENT_ID)			((CLIENT_ID) << 28)
185 #define MBOX_JOB_ID_CMD(JOB_ID)				(JOB_ID<<24)
186 #define MBOX_CMD_LEN_CMD(CMD_LEN)			((CMD_LEN) << 12)
187 #define MBOX_INDIRECT(val)				((val) << 11)
188 #define MBOX_CMD_MASK(header)				((header) & 0x7ff)
189 
190 /* Mailbox payload */
191 #define MBOX_DATA_MAX_LEN				0x3ff
192 #define MBOX_PAYLOAD_FLAG_BUSY				BIT(0)
193 
194 /* RSU Macros */
195 #define RSU_VERSION_ACMF				BIT(8)
196 #define RSU_VERSION_ACMF_MASK				0xff00
197 
198 /* Config Status Macros */
199 #define CONFIG_STATUS_WORD_SIZE			16U
200 #define CONFIG_STATUS_FW_VER_OFFSET		1
201 #define CONFIG_STATUS_FW_VER_MASK		0x00FFFFFF
202 
203 /* Data structure */
204 
205 typedef struct mailbox_payload {
206 	uint32_t header;
207 	uint32_t data[MBOX_DATA_MAX_LEN];
208 } mailbox_payload_t;
209 
210 typedef struct mailbox_container {
211 	uint32_t flag;
212 	uint32_t index;
213 	mailbox_payload_t *payload;
214 } mailbox_container_t;
215 
216 /* Mailbox Function Definitions */
217 
218 void mailbox_set_int(uint32_t interrupt_input);
219 int mailbox_init(void);
220 void mailbox_set_qspi_close(void);
221 void mailbox_hps_qspi_enable(void);
222 
223 int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
224 			unsigned int len, uint32_t urgent, uint32_t *response,
225 			unsigned int *resp_len);
226 int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
227 			unsigned int len, unsigned int indirect);
228 int mailbox_send_cmd_async_ext(uint32_t header_cmd, uint32_t *args,
229 			unsigned int len);
230 int mailbox_read_response(uint32_t *job_id, uint32_t *response,
231 			unsigned int *resp_len);
232 int mailbox_read_response_async(uint32_t *job_id, uint32_t *header,
233 			uint32_t *response, unsigned int *resp_len,
234 			uint8_t ignore_client_id);
235 int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
236 			unsigned int *resp_len);
237 
238 void mailbox_reset_cold(void);
239 void mailbox_reset_warm(uint32_t reset_type);
240 void mailbox_clear_response(void);
241 
242 int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
243 int intel_mailbox_is_fpga_not_ready(void);
244 
245 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
246 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
247 int mailbox_rsu_update(uint32_t *flash_offset);
248 int mailbox_hps_stage_notify(uint32_t execution_stage);
249 int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
250 int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
251 int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
252 
253 #endif /* SOCFPGA_MBOX_H */
254