1 /* 2 * Copyright (c) 2023-2024 Analog Devices, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_ 9 10 /** 11 * @brief Pin modes 12 */ 13 #define MAX32_MODE_GPIO 0x00 14 #define MAX32_MODE_AF1 0x01 15 #define MAX32_MODE_AF2 0x02 16 #define MAX32_MODE_AF3 0x03 17 #define MAX32_MODE_AF4 0x04 18 #define MAX32_MODE_AF5 0x05 19 20 /** 21 * @brief Mode, port, pin shift number 22 */ 23 #define MAX32_MODE_SHIFT 0U 24 #define MAX32_MODE_MASK 0x0FU 25 #define MAX32_PORT_SHIFT 4U 26 #define MAX32_PORT_MASK 0x0FU 27 #define MAX32_PIN_SHIFT 8U 28 #define MAX32_PIN_MASK 0xFFU 29 30 /** 31 * @brief Pin configuration bit field. 32 * 33 * Fields: 34 * 35 * - mode [ 0 : 3 ] 36 * - port [ 4 : 7 ] 37 * - pin [ 8 : 15 ] 38 * 39 * @param port Port (0 .. 15) 40 * @param pin Pin (0..31) 41 * @param mode Mode (GPIO, AF1, AF2...). 42 */ 43 #define MAX32_PINMUX(port, pin, mode) \ 44 ((((port)&MAX32_PORT_MASK) << MAX32_PORT_SHIFT) | \ 45 (((pin)&MAX32_PIN_MASK) << MAX32_PIN_SHIFT) | \ 46 (((MAX32_MODE_##mode) & MAX32_MODE_MASK) << MAX32_MODE_SHIFT)) 47 48 #define MAX32_PINMUX_PORT(pinmux) (((pinmux) >> MAX32_PORT_SHIFT) & MAX32_PORT_MASK) 49 #define MAX32_PINMUX_PIN(pinmux) (((pinmux) >> MAX32_PIN_SHIFT) & MAX32_PIN_MASK) 50 #define MAX32_PINMUX_MODE(pinmux) (((pinmux) >> MAX32_MODE_SHIFT) & MAX32_MODE_MASK) 51 52 /* Selects the voltage rail used for the pin */ 53 #define MAX32_VSEL_VDDIO 0 54 #define MAX32_VSEL_VDDIOH 1 55 56 /** 57 * @brief Pin configuration 58 */ 59 #define MAX32_INPUT_ENABLE_SHIFT 0x00 60 #define MAX32_BIAS_PULL_UP_SHIFT 0x01 61 #define MAX32_BIAS_PULL_DOWN_SHIFT 0x02 62 #define MAX32_OUTPUT_ENABLE_SHIFT 0x03 63 #define MAX32_POWER_SOURCE_SHIFT 0x04 64 #define MAX32_OUTPUT_HIGH_SHIFT 0x05 65 #define MAX32_DRV_STRENGTH_SHIFT 0x06 /* 2 bits */ 66 #define MAX32_DRV_STRENGTH_MASK 0x03 67 68 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_ */ 69
