1 /* 2 * Copyright (c) 2017, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/drivers/sensor.h> 8 #include <zephyr/drivers/i2c.h> 9 #include <zephyr/drivers/gpio.h> 10 11 #define MAX30101_REG_INT_STS1 0x00 12 #define MAX30101_REG_INT_STS2 0x01 13 #define MAX30101_REG_INT_EN1 0x02 14 #define MAX30101_REG_INT_EN2 0x03 15 #define MAX30101_REG_FIFO_WR 0x04 16 #define MAX30101_REG_FIFO_OVF 0x05 17 #define MAX30101_REG_FIFO_RD 0x06 18 #define MAX30101_REG_FIFO_DATA 0x07 19 #define MAX30101_REG_FIFO_CFG 0x08 20 #define MAX30101_REG_MODE_CFG 0x09 21 #define MAX30101_REG_SPO2_CFG 0x0a 22 #define MAX30101_REG_LED1_PA 0x0c 23 #define MAX30101_REG_LED2_PA 0x0d 24 #define MAX30101_REG_LED3_PA 0x0e 25 #define MAX30101_REG_PILOT_PA 0x10 26 #define MAX30101_REG_MULTI_LED 0x11 27 #define MAX30101_REG_TINT 0x1f 28 #define MAX30101_REG_TFRAC 0x20 29 #define MAX30101_REG_TEMP_CFG 0x21 30 #define MAX30101_REG_PROX_INT 0x30 31 #define MAX30101_REG_REV_ID 0xfe 32 #define MAX30101_REG_PART_ID 0xff 33 34 #define MAX30101_INT_PPG_MASK (1 << 6) 35 36 #define MAX30101_FIFO_CFG_SMP_AVE_SHIFT 5 37 #define MAX30101_FIFO_CFG_FIFO_FULL_SHIFT 0 38 #define MAX30101_FIFO_CFG_ROLLOVER_EN_MASK (1 << 4) 39 40 #define MAX30101_MODE_CFG_SHDN_MASK (1 << 7) 41 #define MAX30101_MODE_CFG_RESET_MASK (1 << 6) 42 43 #define MAX30101_SPO2_ADC_RGE_SHIFT 5 44 #define MAX30101_SPO2_SR_SHIFT 2 45 #define MAX30101_SPO2_PW_SHIFT 0 46 47 #define MAX30101_PART_ID 0x15 48 49 #define MAX30101_BYTES_PER_CHANNEL 3 50 #define MAX30101_MAX_NUM_CHANNELS 3 51 #define MAX30101_MAX_BYTES_PER_SAMPLE (MAX30101_MAX_NUM_CHANNELS * \ 52 MAX30101_BYTES_PER_CHANNEL) 53 54 #define MAX30101_SLOT_LED_MASK 0x03 55 56 #define MAX30101_FIFO_DATA_BITS 18 57 #define MAX30101_FIFO_DATA_MASK ((1 << MAX30101_FIFO_DATA_BITS) - 1) 58 59 enum max30101_mode { 60 MAX30101_MODE_HEART_RATE = 2, 61 MAX30101_MODE_SPO2 = 3, 62 MAX30101_MODE_MULTI_LED = 7, 63 }; 64 65 enum max30101_slot { 66 MAX30101_SLOT_DISABLED = 0, 67 MAX30101_SLOT_RED_LED1_PA, 68 MAX30101_SLOT_IR_LED2_PA, 69 MAX30101_SLOT_GREEN_LED3_PA, 70 MAX30101_SLOT_RED_PILOT_PA, 71 MAX30101_SLOT_IR_PILOT_PA, 72 MAX30101_SLOT_GREEN_PILOT_PA, 73 }; 74 75 enum max30101_led_channel { 76 MAX30101_LED_CHANNEL_RED = 0, 77 MAX30101_LED_CHANNEL_IR, 78 MAX30101_LED_CHANNEL_GREEN, 79 }; 80 81 enum max30101_pw { 82 MAX30101_PW_15BITS = 0, 83 MAX30101_PW_16BITS, 84 MAX30101_PW_17BITS, 85 MAX30101_PW_18BITS, 86 }; 87 88 struct max30101_config { 89 struct i2c_dt_spec i2c; 90 uint8_t fifo; 91 uint8_t spo2; 92 uint8_t led_pa[MAX30101_MAX_NUM_CHANNELS]; 93 enum max30101_mode mode; 94 enum max30101_slot slot[4]; 95 }; 96 97 struct max30101_data { 98 uint32_t raw[MAX30101_MAX_NUM_CHANNELS]; 99 uint8_t map[MAX30101_MAX_NUM_CHANNELS]; 100 uint8_t num_channels; 101 }; 102
