1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 
7 /** @addtogroup Renesas Electronics Corporation
8  * @{
9  */
10 
11 /** @addtogroup R9A07G084
12  * @{
13  */
14 
15 #ifndef R9A07G084_H
16  #define R9A07G084_H
17 
18  #ifdef __cplusplus
19 extern "C" {
20  #endif
21 
22 /** @addtogroup Configuration_of_CMSIS
23  * @{
24  */
25 
26 /* =========================================================================================================================== */
27 /* ================                                Interrupt Number Definition                                ================ */
28 /* =========================================================================================================================== */
29 
30 /* =========================================================================================================================== */
31 /* ================                           Processor and Core Peripheral Section                           ================ */
32 /* =========================================================================================================================== */
33 
34 /* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */
35  #ifdef RENESAS_CORTEX_M4
36   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
37   #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
38   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
39   #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
40   #include "core_cm4.h"                /*!< Cortex-M4 processor and core peripherals                              */
41  #elif defined(RENESAS_CORTEX_M0PLUS)
42   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
43   #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
44   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
45   #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
46   #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
47   #include "core_cm0plus.h"            /*!< Cortex-M0 processor and core peripherals                              */
48  #elif defined(RENESAS_CORTEX_M23)
49   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
50   #define __NVIC_PRIO_BITS          2  /*!< Number of Bits used for Priority Levels                               */
51   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
52   #define __FPU_PRESENT             0  /*!< FPU present or not                                                    */
53   #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
54   #include "core_cm23.h"               /*!< Cortex-M23 processor and core peripherals                             */
55  #elif defined(RENESAS_CORTEX_M33)
56   #define __MPU_PRESENT             1  /*!< MPU present or not                                                    */
57   #define __NVIC_PRIO_BITS          4  /*!< Number of Bits used for Priority Levels                               */
58   #define __Vendor_SysTickConfig    0  /*!< Set to 1 if different SysTick Config is used                          */
59   #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
60   #define __VTOR_PRESENT            1  /*!< Vector table VTOR register available or not                           */
61   #define __DSP_PRESENT             1  /*!< DSP present or not                                                    */
62   #include "core_cm33.h"               /*!< Cortex-M33 processor and core peripherals                             */
63  #elif defined(RENESAS_CORTEX_R52)
64   #define __FPU_PRESENT             1  /*!< FPU present or not                                                    */
65   #include "core_cr52.h"               /*!< Cortex-R52 processor and core peripherals                              */
66  #endif
67 
68  #include "system.h"                   /*!< System                                                                */
69 
70  #ifndef __IM                          /*!< Fallback for older CMSIS versions                                         */
71   #define __IM     __I
72  #endif
73  #ifndef __OM                          /*!< Fallback for older CMSIS versions                                         */
74   #define __OM     __O
75  #endif
76  #ifndef __IOM                         /*!< Fallback for older CMSIS versions                                         */
77   #define __IOM    __IO
78  #endif
79 
80 /* ========================================  Start of section using anonymous unions  ======================================== */
81  #if defined(__CC_ARM)
82   #pragma push
83   #pragma anon_unions
84  #elif defined(__ICCARM__)
85   #pragma language=extended
86  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
87   #pragma clang diagnostic push
88   #pragma clang diagnostic ignored "-Wc11-extensions"
89   #pragma clang diagnostic ignored "-Wreserved-id-macro"
90   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
91   #pragma clang diagnostic ignored "-Wnested-anon-types"
92  #elif defined(__GNUC__)
93 
94 /* anonymous unions are enabled by default */
95  #elif defined(__TMS470__)
96 
97 /* anonymous unions are enabled by default */
98  #elif defined(__TASKING__)
99   #pragma warning 586
100  #elif defined(__CSMC__)
101 
102 /* anonymous unions are enabled by default */
103  #else
104   #warning Not supported compiler type
105  #endif
106 
107 /* =========================================================================================================================== */
108 /* ================                              Device Specific Cluster Section                              ================ */
109 /* =========================================================================================================================== */
110 
111 /** @addtogroup Device_Peripheral_clusters
112  * @{
113  */
114 
115 /**
116  * @brief R_CANFD_CFDC [CFDC] (CANFD Channel [0..1] Registers)
117  */
118 typedef struct
119 {
120     union
121     {
122         __IOM uint32_t NCFG;            /*!< (@ 0x00000000) Channel n Nominal Bit Rate Configuration Register          */
123 
124         struct
125         {
126             __IOM uint32_t NBRP   : 10; /*!< [9..0] Nominal Bit Rate Prescaler                                         */
127             __IOM uint32_t NSJW   : 7;  /*!< [16..10] Nominal Bit Rate Resynchronization Jump Width Control            */
128             __IOM uint32_t NTSEG1 : 8;  /*!< [24..17] Nominal Bit Rate Time Segment 1 Control                          */
129             __IOM uint32_t NTSEG2 : 7;  /*!< [31..25] Nominal Bit Rate Time Segment 2 Control                          */
130         } NCFG_b;
131     };
132 
133     union
134     {
135         __IOM uint32_t CTR;             /*!< (@ 0x00000004) Channel n Control Register                                 */
136 
137         struct
138         {
139             __IOM uint32_t CHMDC   : 2; /*!< [1..0] Mode Select                                                        */
140             __IOM uint32_t CSLPR   : 1; /*!< [2..2] Channel Stop Mode                                                  */
141             __IOM uint32_t RTBO    : 1; /*!< [3..3] Forcible Return from Bus-Off                                       */
142             uint32_t               : 4;
143             __IOM uint32_t BEIE    : 1; /*!< [8..8] Bus Error Interrupt Enable                                         */
144             __IOM uint32_t EWIE    : 1; /*!< [9..9] Error Warning Interrupt Enable                                     */
145             __IOM uint32_t EPIE    : 1; /*!< [10..10] Error Passive Interrupt Enable                                   */
146             __IOM uint32_t BOEIE   : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable                                   */
147             __IOM uint32_t BORIE   : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable                                */
148             __IOM uint32_t OLIE    : 1; /*!< [13..13] Overload Interrupt Enable                                        */
149             __IOM uint32_t BLIE    : 1; /*!< [14..14] Bus Lock Interrupt Enable                                        */
150             __IOM uint32_t ALIE    : 1; /*!< [15..15] Arbitration Lost Interrupt Enable                                */
151             __IOM uint32_t TAIE    : 1; /*!< [16..16] Transmission Abort Interrupt Enable                              */
152             __IOM uint32_t EOCOIE  : 1; /*!< [17..17] Error Occurrence Counter Overflow Interrupt Enable               */
153             __IOM uint32_t SOCOIE  : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt Enable          */
154             __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt
155                                          *   Enable                                                                    */
156             uint32_t            : 1;
157             __IOM uint32_t BOM  : 2;    /*!< [22..21] Bus-Off Recovery Mode Select                                     */
158             __IOM uint32_t ERRD : 1;    /*!< [23..23] Error Display Mode Select                                        */
159             __IOM uint32_t CTME : 1;    /*!< [24..24] Communication Test Mode Enable                                   */
160             __IOM uint32_t CTMS : 2;    /*!< [26..25] Communication Test Mode Select                                   */
161             uint32_t            : 3;
162             __IOM uint32_t CRCT : 1;    /*!< [30..30] CRC Error Test Enable                                            */
163             __IOM uint32_t ROM  : 1;    /*!< [31..31] Restricted Operation Mode Enable                                 */
164         } CTR_b;
165     };
166 
167     union
168     {
169         __IOM uint32_t STS;             /*!< (@ 0x00000008) Channel n Status Register                                  */
170 
171         struct
172         {
173             __IM uint32_t  CRSTSTS : 1; /*!< [0..0] Channel Reset Status Flag                                          */
174             __IM uint32_t  CHLTSTS : 1; /*!< [1..1] Channel Halt Status Flag                                           */
175             __IM uint32_t  CSLPSTS : 1; /*!< [2..2] Channel Stop Status Flag                                           */
176             __IM uint32_t  EPSTS   : 1; /*!< [3..3] Error Passive Status Flag                                          */
177             __IM uint32_t  BOSTS   : 1; /*!< [4..4] Bus-Off Status Flag                                                */
178             __IM uint32_t  TRMSTS  : 1; /*!< [5..5] Transmit Status Flag                                               */
179             __IM uint32_t  RECSTS  : 1; /*!< [6..6] Receive Status Flag                                                */
180             __IM uint32_t  COMSTS  : 1; /*!< [7..7] Communication Status Flag                                          */
181             __IOM uint32_t ESIF    : 1; /*!< [8..8] Error State Indication Flag                                        */
182             uint32_t               : 7;
183             __IM uint32_t REC      : 8; /*!< [23..16] Reception Error Count                                            */
184             __IM uint32_t TEC      : 8; /*!< [31..24] Transmission Error Count                                         */
185         } STS_b;
186     };
187 
188     union
189     {
190         __IOM uint32_t ERFL;           /*!< (@ 0x0000000C) Channel n Error Flag Register                              */
191 
192         struct
193         {
194             __IOM uint32_t BEF   : 1;  /*!< [0..0] Bus Error Flag                                                     */
195             __IOM uint32_t EWF   : 1;  /*!< [1..1] Error Warning Flag                                                 */
196             __IOM uint32_t EPF   : 1;  /*!< [2..2] Error Passive Flag                                                 */
197             __IOM uint32_t BOEF  : 1;  /*!< [3..3] Bus-Off Entry Flag                                                 */
198             __IOM uint32_t BORF  : 1;  /*!< [4..4] Bus-Off Recovery Flag                                              */
199             __IOM uint32_t OVLF  : 1;  /*!< [5..5] Overload Flag                                                      */
200             __IOM uint32_t BLF   : 1;  /*!< [6..6] Bus Lock Flag                                                      */
201             __IOM uint32_t ALF   : 1;  /*!< [7..7] Arbitration Lost Flag                                              */
202             __IOM uint32_t SERR  : 1;  /*!< [8..8] Stuff Error Flag                                                   */
203             __IOM uint32_t FERR  : 1;  /*!< [9..9] Form Error Flag                                                    */
204             __IOM uint32_t AERR  : 1;  /*!< [10..10] Acknowledge Error Flag                                           */
205             __IOM uint32_t CERR  : 1;  /*!< [11..11] CRC Error Flag                                                   */
206             __IOM uint32_t B1ERR : 1;  /*!< [12..12] Recessive Bit Error Flag                                         */
207             __IOM uint32_t B0ERR : 1;  /*!< [13..13] Dominant Bit Error Flag                                          */
208             __IOM uint32_t ADERR : 1;  /*!< [14..14] Acknowledge Delimiter Error Flag                                 */
209             uint32_t             : 1;
210             __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Calculation Data (CRC length: 15 bits)                       */
211             uint32_t             : 1;
212         } ERFL_b;
213     };
214 } R_CANFD_CFDC_Type;                   /*!< Size = 16 (0x10)                                                          */
215 
216 /**
217  * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers)
218  */
219 typedef struct
220 {
221     union
222     {
223         __IOM uint32_t DCFG;           /*!< (@ 0x00000000) Channel Data Bit Rate Configuration Register               */
224 
225         struct
226         {
227             __IOM uint32_t DBRP   : 8; /*!< [7..0] Data Bit Rate Prescaler Division Ratio Setting                     */
228             __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Data Bit Rate Time Segment 1 Control                              */
229             uint32_t              : 3;
230             __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Data Bit Rate Time Segment 2 Control                             */
231             uint32_t              : 4;
232             __IOM uint32_t DSJW   : 4; /*!< [27..24] Data Bit Rate Resynchronization Jump Width Control               */
233             uint32_t              : 4;
234         } DCFG_b;
235     };
236 
237     union
238     {
239         __IOM uint32_t FDCFG;          /*!< (@ 0x00000004) Channel n CAN-FD Configuration Register                    */
240 
241         struct
242         {
243             __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration                             */
244             uint32_t              : 5;
245             __IOM uint32_t TDCOC  : 1; /*!< [8..8] Transmitter Delay Compensation Offset Configuration                */
246             __IOM uint32_t TDCE   : 1; /*!< [9..9] Transceiver Delay Compensation Enable                              */
247             __IOM uint32_t ESIC   : 1; /*!< [10..10] Error State Indication Configuration                             */
248             uint32_t              : 5;
249             __IOM uint32_t TDCO   : 8; /*!< [23..16] Transceiver Delay Compensation Offset                            */
250             __IOM uint32_t GWEN   : 1; /*!< [24..24] CAN2.0, CAN-FD Multi Gateway Enable                              */
251             __IOM uint32_t GWFDF  : 1; /*!< [25..25] Gateway FDF Configuration Bit                                    */
252             __IOM uint32_t GWBRS  : 1; /*!< [26..26] Gateway BRS Configuration Bit                                    */
253             uint32_t              : 1;
254             __IOM uint32_t FDOE   : 1; /*!< [28..28] FD-Only Enable                                                   */
255             __IOM uint32_t REFE   : 1; /*!< [29..29] RX Edge Filter Enable                                            */
256             __IOM uint32_t CLOE   : 1; /*!< [30..30] Classical CAN-Only Enable                                        */
257             __IOM uint32_t CFDTE  : 1; /*!< [31..31] CAN-FD Frame Distinction Enable                                  */
258         } FDCFG_b;
259     };
260 
261     union
262     {
263         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) Channel n CAN-FD Control Register                          */
264 
265         struct
266         {
267             __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear                                     */
268             __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear                                */
269             uint32_t              : 30;
270         } FDCTR_b;
271     };
272 
273     union
274     {
275         __IOM uint32_t FDSTS;          /*!< (@ 0x0000000C) Channel n CAN-FD Status Register                           */
276 
277         struct
278         {
279             __IM uint32_t  TDCR  : 8;  /*!< [7..0] Transceiver Delay Compensation Result                              */
280             __IOM uint32_t EOCO  : 1;  /*!< [8..8] Error Occurrence Counter Overflow Flag                             */
281             __IOM uint32_t SOCO  : 1;  /*!< [9..9] Successful Occurrence Counter Overflow Flag                        */
282             uint32_t             : 5;
283             __IOM uint32_t TDCVF : 1;  /*!< [15..15] Transceiver Delay Compensation Violation Flag                    */
284             __IM uint32_t  EOC   : 8;  /*!< [23..16] Error Occurrence Counter                                         */
285             __IM uint32_t  SOC   : 8;  /*!< [31..24] Successful Occurrence Counter                                    */
286         } FDSTS_b;
287     };
288 
289     union
290     {
291         __IM uint32_t FDCRC;           /*!< (@ 0x00000010) Channel n CAN-FD CRC Register                              */
292 
293         struct
294         {
295             __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register Value                                                */
296             uint32_t             : 4;
297             __IM uint32_t SCNT   : 4;  /*!< [28..25] Stuff Bit Count                                                  */
298             uint32_t             : 3;
299         } FDCRC_b;
300     };
301     __IM uint32_t RESERVED;
302 
303     union
304     {
305         __IOM uint32_t BLCT;           /*!< (@ 0x00000018) Channel n Bus Load Control Register                        */
306 
307         struct
308         {
309             __IOM uint32_t BLCE : 1;   /*!< [0..0] Bus Load Counter Enable                                            */
310             uint32_t            : 7;
311             __OM uint32_t BLCLD : 1;   /*!< [8..8] Bus Load Counter Load                                              */
312             uint32_t            : 23;
313         } BLCT_b;
314     };
315 
316     union
317     {
318         __IM uint32_t BLSTS;           /*!< (@ 0x0000001C) Channel n Bus Load Status Register                         */
319 
320         struct
321         {
322             uint32_t          : 3;
323             __IM uint32_t BLC : 29;    /*!< [31..3] Bus Load Counter Status                                           */
324         } BLSTS_b;
325     };
326 } R_CANFD_CFDC2_Type;                  /*!< Size = 32 (0x20)                                                          */
327 
328 /**
329  * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers)
330  */
331 typedef struct
332 {
333     union
334     {
335         __IOM uint32_t ID;               /*!< (@ 0x00000000) Global Acceptance Filter List ID Register n                */
336 
337         struct
338         {
339             __IOM uint32_t GAFLID  : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field                      */
340             __IOM uint32_t GAFLLB  : 1;  /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration       */
341             __IOM uint32_t GAFLRTR : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Field                    */
342             __IOM uint32_t GAFLIDE : 1;  /*!< [31..31] Global Acceptance Filter List Entry IDE Field                    */
343         } ID_b;
344     };
345 
346     union
347     {
348         __IOM uint32_t M;                 /*!< (@ 0x00000004) Global Acceptance Filter List Mask Register n              */
349 
350         struct
351         {
352             __IOM uint32_t GAFLIDM  : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field                       */
353             __IOM uint32_t GAFLIFL1 : 1;  /*!< [29..29] Global Acceptance Filter List Information Label 1                */
354             __IOM uint32_t GAFLRTRM : 1;  /*!< [30..30] Global Acceptance Filter List Entry RTR Mask                     */
355             __IOM uint32_t GAFLIDEM : 1;  /*!< [31..31] Global Acceptance Filter List IDE Mask                           */
356         } M_b;
357     };
358 
359     union
360     {
361         __IOM uint32_t P0;               /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Register
362                                           *                  n                                                          */
363 
364         struct
365         {
366             __IOM uint32_t GAFLDLC  : 4; /*!< [3..0] Global Acceptance Filter List DLC Field                            */
367             __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing Destination
368                                           *   0                                                                         */
369             __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing Destination
370                                           *   1                                                                         */
371             __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing Destination
372                                           *   2                                                                         */
373             __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0                  */
374             __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction
375                                           *   Pointer                                                                   */
376             uint32_t               : 2;
377             __IOM uint32_t GAFLRMV : 1;  /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid            */
378             __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer                            */
379         } P0_b;
380     };
381 
382     union
383     {
384         __IOM uint32_t P1;               /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Register
385                                           *                  n                                                          */
386 
387         struct
388         {
389             __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer              */
390             uint32_t               : 18;
391         } P1_b;
392     };
393 } R_CANFD_CFDGAFL_Type;                  /*!< Size = 16 (0x10)                                                          */
394 
395 /**
396  * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers)
397  */
398 typedef struct
399 {
400     union
401     {
402         __IM uint32_t ID;              /*!< (@ 0x00000000) RX Message Buffer ID Register                              */
403 
404         struct
405         {
406             __IM uint32_t RMID  : 29;  /*!< [28..0] RX Message Buffer ID Field                                        */
407             uint32_t            : 1;
408             __IM uint32_t RMRTR : 1;   /*!< [30..30] RX Message Buffer RTR Bit                                        */
409             __IM uint32_t RMIDE : 1;   /*!< [31..31] RX Message Buffer IDE Bit                                        */
410         } ID_b;
411     };
412 
413     union
414     {
415         __IOM uint32_t PTR;            /*!< (@ 0x00000004) RX Message Buffer Pointer Register                         */
416 
417         struct
418         {
419             __IOM uint32_t RMTS  : 16; /*!< [15..0] RX Message Buffer Timestamp Field                                 */
420             uint32_t             : 12;
421             __IOM uint32_t RMDLC : 4;  /*!< [31..28] RX Message Buffer DLC Field                                      */
422         } PTR_b;
423     };
424 
425     union
426     {
427         __IOM uint32_t FDSTS;          /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register                   */
428 
429         struct
430         {
431             __IOM uint32_t RMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
432             __IOM uint32_t RMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
433             __IOM uint32_t RMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
434             uint32_t             : 5;
435             __IOM uint32_t RMIFL : 2;  /*!< [9..8] RX Message Buffer Information Label Field                          */
436             uint32_t             : 6;
437             __IOM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field                                  */
438         } FDSTS_b;
439     };
440 
441     union
442     {
443         union
444         {
445             __IM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p
446                                             *                  = 0 to 15, n = 0 to 31)                                    */
447 
448             struct
449             {
450                 __IM uint32_t RMDB_LL : 8; /*!< [7..0] RX Message Buffer Data Byte (4 * p)                               */
451                 __IM uint32_t RMDB_LH : 8; /*!< [15..8] RX Message Buffer Data Byte (4 * p + 1)                          */
452                 __IM uint32_t RMDB_HL : 8; /*!< [23..16] RX Message Buffer Data Byte (4 * p + 2)                         */
453                 __IM uint32_t RMDB_HH : 8; /*!< [31..24] RX Message Buffer Data Byte (4 * p + 3)                         */
454             } DF_WD_b[16];
455         };
456 
457         union
458         {
459             __IM uint8_t DF[64];       /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p
460                                         *                  = 0 to 63, n = 0 to 31)                                    */
461 
462             struct
463             {
464                 __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte                                        */
465             } DF_b[64];
466         };
467     };
468     __IM uint32_t RESERVED[13];
469 } R_CANFD_CFDRM_Type;                  /*!< Size = 128 (0x80)                                                         */
470 
471 /**
472  * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers)
473  */
474 typedef struct
475 {
476     union
477     {
478         __IM uint32_t ID;              /*!< (@ 0x00000000) RX FIFO Access ID Register n                               */
479 
480         struct
481         {
482             __IM uint32_t RFID  : 29;  /*!< [28..0] RX FIFO Buffer ID Field                                           */
483             uint32_t            : 1;
484             __IM uint32_t RFRTR : 1;   /*!< [30..30] RX FIFO Buffer RTR bit                                           */
485             __IM uint32_t RFIDE : 1;   /*!< [31..31] RX FIFO Buffer IDE bit                                           */
486         } ID_b;
487     };
488 
489     union
490     {
491         __IM uint32_t PTR;             /*!< (@ 0x00000004) RX FIFO Access Pointer Register n                          */
492 
493         struct
494         {
495             __IM uint32_t RFTS  : 16;  /*!< [15..0] RX FIFO Timestamp Value                                           */
496             uint32_t            : 12;
497             __IM uint32_t RFDLC : 4;   /*!< [31..28] RX FIFO Buffer DLC Field                                         */
498         } PTR_b;
499     };
500 
501     union
502     {
503         __IM uint32_t FDSTS;             /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register n                    */
504 
505         struct
506         {
507             __IM uint32_t RFESI    : 1;  /*!< [0..0] Error State Indicator bit                                          */
508             __IM uint32_t RFBRS    : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
509             __IM uint32_t RFFDF    : 1;  /*!< [2..2] CAN FD Format bit                                                  */
510             uint32_t               : 5;
511             __IM uint32_t RFIFL    : 2;  /*!< [9..8] RX FIFO Buffer Information Label Field                             */
512             uint32_t               : 6;
513             __IM uint32_t CFDRFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field                                     */
514         } FDSTS_b;
515     };
516 
517     union
518     {
519         union
520         {
521             __IM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0
522                                             *                  to 15, n = 0 to 7)                                         */
523 
524             struct
525             {
526                 __IM uint32_t RFDB_LL : 8; /*!< [7..0] RX FIFO Buffer Data Byte (4 * p)                                  */
527                 __IM uint32_t RFDB_LH : 8; /*!< [15..8] RX FIFO Buffer Data Byte (4 * p + 1)                             */
528                 __IM uint32_t RFDB_HL : 8; /*!< [23..16] RX FIFO Buffer Data Byte (4 * p + 2)                            */
529                 __IM uint32_t RFDB_HH : 8; /*!< [31..24] RX FIFO Buffer Data Byte (4 * p + 3)                            */
530             } DF_WD_b[16];
531         };
532 
533         union
534         {
535             __IM uint8_t DF[64];       /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0
536                                         *                  to 63, n = 0 to 7)                                         */
537 
538             struct
539             {
540                 __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte                                           */
541             } DF_b[64];
542         };
543     };
544     __IM uint32_t RESERVED[13];
545 } R_CANFD_CFDRF_Type;                  /*!< Size = 128 (0x80)                                                         */
546 
547 /**
548  * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers)
549  */
550 typedef struct
551 {
552     union
553     {
554         __IOM uint32_t ID;             /*!< (@ 0x00000000) Common FIFO Access ID Register                             */
555 
556         struct
557         {
558             __IOM uint32_t CFID  : 29; /*!< [28..0] Common FIFO Buffer ID Field                                       */
559             __IOM uint32_t THLEN : 1;  /*!< [29..29] THL Entry Enable                                                 */
560             __IOM uint32_t CFRTR : 1;  /*!< [30..30] Common FIFO Buffer RTR bit                                       */
561             __IOM uint32_t CFIDE : 1;  /*!< [31..31] Common FIFO Buffer IDE bit                                       */
562         } ID_b;
563     };
564 
565     union
566     {
567         __IOM uint32_t PTR;            /*!< (@ 0x00000004) Common FIFO Access Pointer Register n                      */
568 
569         struct
570         {
571             __IOM uint32_t CFTS  : 16; /*!< [15..0] Common FIFO Timestamp Value                                       */
572             uint32_t             : 12;
573             __IOM uint32_t CFDLC : 4;  /*!< [31..28] Common FIFO Buffer DLC Field                                     */
574         } PTR_b;
575     };
576 
577     union
578     {
579         __IOM uint32_t FDCSTS;         /*!< (@ 0x00000008) Common FIFO Access CAN-FD Control/Status Register
580                                         *                  n                                                          */
581 
582         struct
583         {
584             __IOM uint32_t CFESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
585             __IOM uint32_t CFBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
586             __IOM uint32_t CFFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
587             uint32_t             : 5;
588             __IOM uint32_t CFIFL : 2;  /*!< [9..8] COMMON FIFO Buffer Information Label Field                         */
589             uint32_t             : 6;
590             __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field                                 */
591         } FDCSTS_b;
592     };
593 
594     union
595     {
596         union
597         {
598             __IOM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p
599                                              *                  = 0 to 15, n = 0 to 5)                                     */
600 
601             struct
602             {
603                 __IOM uint32_t CFDB_LL : 8; /*!< [7..0] Common FIFO Buffer Data Bytes (4 * p)                             */
604                 __IOM uint32_t CFDB_LH : 8; /*!< [15..8] Common FIFO Buffer Data Bytes (4 * p + 1)                        */
605                 __IOM uint32_t CFDB_HL : 8; /*!< [23..16] Common FIFO Buffer Data Bytes (4 * p + 2)                       */
606                 __IOM uint32_t CFDB_HH : 8; /*!< [31..24] Common FIFO Buffer Data Bytes (4 * p + 3)                       */
607             } DF_WD_b[16];
608         };
609 
610         union
611         {
612             __IOM uint8_t DF[64];       /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p
613                                          *                  = 0 to 63, n = 0 to 5)                                     */
614 
615             struct
616             {
617                 __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Bytes                                      */
618             } DF_b[64];
619         };
620     };
621     __IM uint32_t RESERVED[13];
622 } R_CANFD_CFDCF_Type;                  /*!< Size = 128 (0x80)                                                         */
623 
624 /**
625  * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List)
626  */
627 typedef struct
628 {
629     union
630     {
631         __IM uint32_t ACC0;            /*!< (@ 0x00000000) Channel TX History List Access Registers 0                 */
632 
633         struct
634         {
635             __IM uint32_t BT   : 3;    /*!< [2..0] Buffer Type                                                        */
636             __IM uint32_t BN   : 7;    /*!< [9..3] Buffer Number                                                      */
637             uint32_t           : 5;
638             __IM uint32_t TGW  : 1;    /*!< [15..15] Transmit Gateway Buffer Indication                               */
639             __IM uint32_t TMTS : 16;   /*!< [31..16] Transmit Timestamp                                               */
640         } ACC0_b;
641     };
642 
643     union
644     {
645         __IM uint32_t ACC1;            /*!< (@ 0x00000004) Channel TX History List Access Registers 1                 */
646 
647         struct
648         {
649             __IM uint32_t TID  : 16;   /*!< [15..0] Transmit ID                                                       */
650             __IM uint32_t TIFL : 2;    /*!< [17..16] Transmit Information Label                                       */
651             uint32_t           : 14;
652         } ACC1_b;
653     };
654 } R_CANFD_CFDTHL_Type;                 /*!< Size = 8 (0x8)                                                            */
655 
656 /**
657  * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Registers)
658  */
659 typedef struct
660 {
661     union
662     {
663         __IOM uint32_t ID;             /*!< (@ 0x00000000) TX Message Buffer ID Register n (n = 0 to 127)             */
664 
665         struct
666         {
667             __IOM uint32_t TMID  : 29; /*!< [28..0] TX Message Buffer ID Field                                        */
668             __IOM uint32_t THLEN : 1;  /*!< [29..29] Tx History List Entry                                            */
669             __IOM uint32_t TMRTR : 1;  /*!< [30..30] TX Message Buffer RTR bit                                        */
670             __IOM uint32_t TMIDE : 1;  /*!< [31..31] TX Message Buffer IDE bit                                        */
671         } ID_b;
672     };
673 
674     union
675     {
676         __IOM uint32_t PTR;            /*!< (@ 0x00000004) TX Message Buffer Pointer Register n (n = 0 to
677                                         *                  127)                                                       */
678 
679         struct
680         {
681             uint32_t             : 28;
682             __IOM uint32_t TMDLC : 4;  /*!< [31..28] TX Message Buffer DLC Field                                      */
683         } PTR_b;
684     };
685 
686     union
687     {
688         __IOM uint32_t FDCTR;          /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register n (n
689                                         *                  = 0 to 127)                                                */
690 
691         struct
692         {
693             __IOM uint32_t TMESI : 1;  /*!< [0..0] Error State Indicator bit                                          */
694             __IOM uint32_t TMBRS : 1;  /*!< [1..1] Bit Rate Switch bit                                                */
695             __IOM uint32_t TMFDF : 1;  /*!< [2..2] CAN FD Format bit                                                  */
696             uint32_t             : 5;
697             __IOM uint32_t TMIFL : 2;  /*!< [9..8] TX Message Buffer Information Label Field                          */
698             uint32_t             : 6;
699             __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field                                  */
700         } FDCTR_b;
701     };
702 
703     union
704     {
705         union
706         {
707             __IOM uint32_t DF_WD[16];       /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p
708                                              *                  = 0 to 15, n = 0 to 127)                                   */
709 
710             struct
711             {
712                 __IOM uint32_t TMDB_LL : 8; /*!< [7..0] TX Message Buffer Data Byte (4 * p)                               */
713                 __IOM uint32_t TMDB_LH : 8; /*!< [15..8] TX Message Buffer Data Byte (4 * p + 1)                          */
714                 __IOM uint32_t TMDB_HL : 8; /*!< [23..16] TX Message Buffer Data Byte (4 * p + 2)                         */
715                 __IOM uint32_t TMDB_HH : 8; /*!< [31..24] TX Message Buffer Data Byte (4 * p + 3)                         */
716             } DF_WD_b[16];
717         };
718 
719         union
720         {
721             __IOM uint8_t DF[64];       /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p
722                                          *                  = 0 to 63, n = 0 to 5)                                     */
723 
724             struct
725             {
726                 __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Bytes                                       */
727             } DF_b[64];
728         };
729     };
730     __IM uint32_t RESERVED[13];
731 } R_CANFD_CFDTM_Type;                  /*!< Size = 128 (0x80)                                                         */
732 
733 /**
734  * @brief R_CMT_UNT_CM [CM] (2 Timer Start Register Pairs)
735  */
736 typedef struct
737 {
738     union
739     {
740         __IOM uint16_t CR;             /*!< (@ 0x00000000) Compare Match Timer Control Register                       */
741 
742         struct
743         {
744             __IOM uint16_t CKS  : 2;   /*!< [1..0] Clock Select                                                       */
745             uint16_t            : 4;
746             __IOM uint16_t CMIE : 1;   /*!< [6..6] Compare Match Interrupt Enable                                     */
747             uint16_t            : 9;
748         } CR_b;
749     };
750     __IOM uint16_t CNT;                /*!< (@ 0x00000002) Compare Match Timer Counter Register                       */
751     __IOM uint16_t COR;                /*!< (@ 0x00000004) Compare Match Timer Constant Register                      */
752 } R_CMT_UNT_CM_Type;                   /*!< Size = 6 (0x6)                                                            */
753 
754 /**
755  * @brief R_CMT_UNT [UNT] (3 Timer Start Register Units)
756  */
757 typedef struct
758 {
759     union
760     {
761         __IOM uint16_t CMSTR0;         /*!< (@ 0x00000000) Compare Match Timer Start Register                         */
762 
763         struct
764         {
765             __IOM uint16_t STR0 : 1;   /*!< [0..0] CMT Channel n Count Start                                          */
766             __IOM uint16_t STR1 : 1;   /*!< [1..1] CMT Channel n+1 Count Start                                        */
767             uint16_t            : 14;
768         } CMSTR0_b;
769     };
770     __IOM R_CMT_UNT_CM_Type CM[2];     /*!< (@ 0x00000002) 2 Timer Start Register Pairs                               */
771     __IM uint16_t           RESERVED[505];
772 } R_CMT_UNT_Type;                      /*!< Size = 1024 (0x400)                                                       */
773 
774 /**
775  * @brief R_IIC0_SAR [SAR] (Slave Address Registers)
776  */
777 typedef struct
778 {
779     union
780     {
781         __IOM uint8_t L;               /*!< (@ 0x00000000) Slave Address Register L y (y = 0 to 2)                    */
782 
783         struct
784         {
785             __IOM uint8_t SVA0 : 1;    /*!< [0..0] 10-bit Address LSB                                                 */
786             __IOM uint8_t SVA  : 7;    /*!< [7..1] 7-bit Address/10-bit Address Lower Bits                            */
787         } L_b;
788     };
789 
790     union
791     {
792         __IOM uint8_t U;               /*!< (@ 0x00000001) Slave Address Register U y (y = 0 to 2)                    */
793 
794         struct
795         {
796             __IOM uint8_t FS  : 1;     /*!< [0..0] 7-bit/10-bit Address Format Select                                 */
797             __IOM uint8_t SVA : 2;     /*!< [2..1] 10-bit Address Upper Bits                                          */
798             uint8_t           : 5;
799         } U_b;
800     };
801 } R_IIC0_SAR_Type;                     /*!< Size = 2 (0x2)                                                            */
802 
803 /**
804  * @brief R_DMAC0_GRP_CH_N [N] (DMAC Address Registers [0..1])
805  */
806 typedef struct
807 {
808     __IOM uint32_t SA;                 /*!< (@ 0x00000000) Nextm0 Source Address Register n (m = 0, 1) (n
809                                         *                  = 0 to 7)                                                  */
810     __IOM uint32_t DA;                 /*!< (@ 0x00000004) Nextm0 Destination Address Register n (m = 0,
811                                         *                  1) (n = 0 to 7)                                            */
812     __IOM uint32_t TB;                 /*!< (@ 0x00000008) Nextm0 Transaction Byte Register n (m = 0, 1)
813                                         *                  (n = 0 to 7)                                               */
814 } R_DMAC0_GRP_CH_N_Type;               /*!< Size = 12 (0xc)                                                           */
815 
816 /**
817  * @brief R_DMAC0_GRP_CH [CH] (DMAC channel Control Register [0..7])
818  */
819 typedef struct
820 {
821     __IOM R_DMAC0_GRP_CH_N_Type N[2];  /*!< (@ 0x00000000) DMAC Address Registers [0..1]                              */
822     __IM uint32_t               CRSA;  /*!< (@ 0x00000018) Current Source Address Register n (n = 0 to 7)             */
823     __IM uint32_t               CRDA;  /*!< (@ 0x0000001C) Current Destination Address Register n (n = 0
824                                         *                  to 7)                                                      */
825     __IM uint32_t CRTB;                /*!< (@ 0x00000020) Current Transaction Byte Register n (n = 0 to
826                                         *                  7)                                                         */
827 
828     union
829     {
830         __IM uint32_t CHSTAT;          /*!< (@ 0x00000024) Channel Status Register n (n = 0 to 7)                     */
831 
832         struct
833         {
834             __IM uint32_t EN   : 1;    /*!< [0..0] DMA Activation Enable                                              */
835             __IM uint32_t RQST : 1;    /*!< [1..1] DMA Transfer Request                                               */
836             __IM uint32_t TACT : 1;    /*!< [2..2] DMAC Operating Status                                              */
837             __IM uint32_t SUS  : 1;    /*!< [3..3] Suspend                                                            */
838             __IM uint32_t ER   : 1;    /*!< [4..4] DMA Error                                                          */
839             __IM uint32_t END  : 1;    /*!< [5..5] DMA Transfer Completion Interrupt                                  */
840             __IM uint32_t TC   : 1;    /*!< [6..6] DMA Transfer Completion (total number of data bytes for
841                                         *   transaction)                                                              */
842             __IM uint32_t SR   : 1;    /*!< [7..7] Next Register Select                                               */
843             __IM uint32_t DL   : 1;    /*!< [8..8] Descriptor Load                                                    */
844             __IM uint32_t DW   : 1;    /*!< [9..9] Descriptor Write Back                                              */
845             __IM uint32_t DER  : 1;    /*!< [10..10] Descriptor Error                                                 */
846             __IM uint32_t MODE : 1;    /*!< [11..11] DMA Mode                                                         */
847             uint32_t           : 4;
848             __IM uint32_t INTM : 1;    /*!< [16..16] DMA Transfer Completion Interrupt Request Mask                   */
849             uint32_t           : 15;
850         } CHSTAT_b;
851     };
852 
853     union
854     {
855         __IOM uint32_t CHCTRL;          /*!< (@ 0x00000028) Channel Control Register n (n = 0 to 7)                    */
856 
857         struct
858         {
859             __IOM uint32_t SETEN   : 1; /*!< [0..0] DMA Activation Enable                                              */
860             __IOM uint32_t CLREN   : 1; /*!< [1..1] DMA Activation Enable Clear                                        */
861             __IOM uint32_t STG     : 1; /*!< [2..2] Software Trigger                                                   */
862             __IOM uint32_t SWRST   : 1; /*!< [3..3] Software Reset                                                     */
863             __IOM uint32_t CLRRQ   : 1; /*!< [4..4] DMA Transfer Request Clear                                         */
864             __IOM uint32_t CLREND  : 1; /*!< [5..5] END Clear                                                          */
865             __IOM uint32_t CLRTC   : 1; /*!< [6..6] TC Clear                                                           */
866             uint32_t               : 1;
867             __IOM uint32_t SETSUS  : 1; /*!< [8..8] Suspend Request                                                    */
868             __IOM uint32_t CLRSUS  : 1; /*!< [9..9] Suspend Clear                                                      */
869             uint32_t               : 6;
870             __IOM uint32_t SETINTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask                   */
871             __IOM uint32_t CLRINTM : 1; /*!< [17..17] DMA Transfer Completion Interrupt Request Mask Clear             */
872             uint32_t               : 14;
873         } CHCTRL_b;
874     };
875 
876     union
877     {
878         __IOM uint32_t CHCFG;          /*!< (@ 0x0000002C) Channel Configuration Register n (n = 0 to 7)              */
879 
880         struct
881         {
882             __IOM uint32_t SEL  : 3;   /*!< [2..0] Pin Select                                                         */
883             __IOM uint32_t REQD : 1;   /*!< [3..3] DMA Activation Request Source Select                               */
884             __IOM uint32_t LOEN : 1;   /*!< [4..4] L Detection Enable                                                 */
885             __IOM uint32_t HIEN : 1;   /*!< [5..5] H Detection Enable                                                 */
886             __IOM uint32_t LVL  : 1;   /*!< [6..6] Level Detection Enable                                             */
887             uint32_t            : 1;
888             __IOM uint32_t AM   : 3;   /*!< [10..8] ACK Mode                                                          */
889             uint32_t            : 1;
890             __IOM uint32_t SDS  : 4;   /*!< [15..12] Source Data Size                                                 */
891             __IOM uint32_t DDS  : 4;   /*!< [19..16] Destination Data Size                                            */
892             __IOM uint32_t SAD  : 1;   /*!< [20..20] Source Address Count Direction                                   */
893             __IOM uint32_t DAD  : 1;   /*!< [21..21] Destination Address Count Direction                              */
894             __IOM uint32_t TM   : 1;   /*!< [22..22] Transfer Mode                                                    */
895             uint32_t            : 1;
896             __IOM uint32_t DEM  : 1;   /*!< [24..24] DMA Transfer Completion Interrupt Mask                           */
897             __IOM uint32_t TCM  : 1;   /*!< [25..25] TEND Mask                                                        */
898             uint32_t            : 1;
899             __IOM uint32_t SBE  : 1;   /*!< [27..27] Buffer Flush Enable                                              */
900             __IOM uint32_t RSEL : 1;   /*!< [28..28] Next Register Select                                             */
901             __IOM uint32_t RSW  : 1;   /*!< [29..29] RSEL Reverse                                                     */
902             __IOM uint32_t REN  : 1;   /*!< [30..30] Register Set Enable                                              */
903             __IOM uint32_t DMS  : 1;   /*!< [31..31] DMA Mode Select                                                  */
904         } CHCFG_b;
905     };
906 
907     union
908     {
909         __IOM uint32_t CHITVL;         /*!< (@ 0x00000030) Channel Interval Register n (n = 0 to 7)                   */
910 
911         struct
912         {
913             __IOM uint32_t ITVL : 16;  /*!< [15..0] Interval                                                          */
914             uint32_t            : 16;
915         } CHITVL_b;
916     };
917 
918     union
919     {
920         __IOM uint32_t CHEXT;          /*!< (@ 0x00000034) Channel Extension Register n (n = 0 to 7)                  */
921 
922         struct
923         {
924             __IOM uint32_t SPR : 3;    /*!< [2..0] Source PROT                                                        */
925             uint32_t           : 1;
926             __IOM uint32_t SCA : 4;    /*!< [7..4] Source CACHE                                                       */
927             __IOM uint32_t DPR : 3;    /*!< [10..8] Destination PROT                                                  */
928             uint32_t           : 1;
929             __IOM uint32_t DCA : 4;    /*!< [15..12] Destination CACHE                                                */
930             uint32_t           : 16;
931         } CHEXT_b;
932     };
933     __IOM uint32_t NXLA;               /*!< (@ 0x00000038) Next Link Address Register n (n = 0 to 7)                  */
934     __IM uint32_t  CRLA;               /*!< (@ 0x0000003C) Current Link Address Register n (n = 0 to 7)               */
935 } R_DMAC0_GRP_CH_Type;                 /*!< Size = 64 (0x40)                                                          */
936 
937 /**
938  * @brief R_DMAC0_GRP [GRP] (8 channel Registers)
939  */
940 typedef struct
941 {
942     __IOM R_DMAC0_GRP_CH_Type CH[8];   /*!< (@ 0x00000000) DMAC channel Control Register [0..7]                       */
943     __IM uint32_t             RESERVED[64];
944 
945     union
946     {
947         __IOM uint32_t DCTRL;          /*!< (@ 0x00000300) DMA Control Register A                                     */
948 
949         struct
950         {
951             __IOM uint32_t PR    : 1;  /*!< [0..0] Priority Control Select                                            */
952             __IOM uint32_t LVINT : 1;  /*!< [1..1] Sets the interrupt output mode.                                    */
953             uint32_t             : 30;
954         } DCTRL_b;
955     };
956     __IM uint32_t RESERVED1[3];
957 
958     union
959     {
960         __IM uint32_t DSTAT_EN;        /*!< (@ 0x00000310) DMA Status EN Register A                                   */
961 
962         struct
963         {
964             __IM uint32_t EN00 : 1;    /*!< [0..0] Channel 0 EN                                                       */
965             __IM uint32_t EN01 : 1;    /*!< [1..1] Channel 1 EN                                                       */
966             __IM uint32_t EN02 : 1;    /*!< [2..2] Channel 2 EN                                                       */
967             __IM uint32_t EN03 : 1;    /*!< [3..3] Channel 3 EN                                                       */
968             __IM uint32_t EN04 : 1;    /*!< [4..4] Channel 4 EN                                                       */
969             __IM uint32_t EN05 : 1;    /*!< [5..5] Channel 5 EN                                                       */
970             __IM uint32_t EN06 : 1;    /*!< [6..6] Channel 6 EN                                                       */
971             __IM uint32_t EN07 : 1;    /*!< [7..7] Channel 7 EN                                                       */
972             uint32_t           : 24;
973         } DSTAT_EN_b;
974     };
975 
976     union
977     {
978         __IM uint32_t DSTAT_ER;        /*!< (@ 0x00000314) DMA Status ER Register A                                   */
979 
980         struct
981         {
982             __IM uint32_t ER00 : 1;    /*!< [0..0] Channel 0 ER                                                       */
983             __IM uint32_t ER01 : 1;    /*!< [1..1] Channel 1 ER                                                       */
984             __IM uint32_t ER02 : 1;    /*!< [2..2] Channel 2 ER                                                       */
985             __IM uint32_t ER03 : 1;    /*!< [3..3] Channel 3 ER                                                       */
986             __IM uint32_t ER04 : 1;    /*!< [4..4] Channel 4 ER                                                       */
987             __IM uint32_t ER05 : 1;    /*!< [5..5] Channel 5 ER                                                       */
988             __IM uint32_t ER06 : 1;    /*!< [6..6] Channel 6 ER                                                       */
989             __IM uint32_t ER07 : 1;    /*!< [7..7] Channel 7 ER                                                       */
990             uint32_t           : 24;
991         } DSTAT_ER_b;
992     };
993 
994     union
995     {
996         __IM uint32_t DSTAT_END;       /*!< (@ 0x00000318) DMA Status END Register A                                  */
997 
998         struct
999         {
1000             __IM uint32_t END00 : 1;   /*!< [0..0] Channel 0 END                                                      */
1001             __IM uint32_t END01 : 1;   /*!< [1..1] Channel 1 END                                                      */
1002             __IM uint32_t END02 : 1;   /*!< [2..2] Channel 2 END                                                      */
1003             __IM uint32_t END03 : 1;   /*!< [3..3] Channel 3 END                                                      */
1004             __IM uint32_t END04 : 1;   /*!< [4..4] Channel 4 END                                                      */
1005             __IM uint32_t END05 : 1;   /*!< [5..5] Channel 5 END                                                      */
1006             __IM uint32_t END06 : 1;   /*!< [6..6] Channel 6 END                                                      */
1007             __IM uint32_t END07 : 1;   /*!< [7..7] Channel 7 END                                                      */
1008             uint32_t            : 24;
1009         } DSTAT_END_b;
1010     };
1011     __IM uint32_t RESERVED2;
1012 
1013     union
1014     {
1015         __IM uint32_t DSTAT_SUS;       /*!< (@ 0x00000320) DMA Status SUS Register A                                  */
1016 
1017         struct
1018         {
1019             __IM uint32_t SUS00 : 1;   /*!< [0..0] Channel 0 SUS                                                      */
1020             __IM uint32_t SUS01 : 1;   /*!< [1..1] Channel 1 SUS                                                      */
1021             __IM uint32_t SUS02 : 1;   /*!< [2..2] Channel 2 SUS                                                      */
1022             __IM uint32_t SUS03 : 1;   /*!< [3..3] Channel 3 SUS                                                      */
1023             __IM uint32_t SUS04 : 1;   /*!< [4..4] Channel 4 SUS                                                      */
1024             __IM uint32_t SUS05 : 1;   /*!< [5..5] Channel 5 SUS                                                      */
1025             __IM uint32_t SUS06 : 1;   /*!< [6..6] Channel 6 SUS                                                      */
1026             __IM uint32_t SUS07 : 1;   /*!< [7..7] Channel 7 SUS                                                      */
1027             uint32_t            : 24;
1028         } DSTAT_SUS_b;
1029     };
1030 } R_DMAC0_GRP_Type;                    /*!< Size = 804 (0x324)                                                        */
1031 
1032 /**
1033  * @brief R_PORT_DRCTL [DRCTL] (I/O Buffer [0..24] Function Switching Register)
1034  */
1035 typedef struct
1036 {
1037     union
1038     {
1039         __IOM uint32_t L;              /*!< (@ 0x00000000) I/O Buffer m Function Switching Register 0-3               */
1040 
1041         struct
1042         {
1043             __IOM uint32_t DRV0 : 2;   /*!< [1..0] Pm_0 Driving Ability Control                                       */
1044             __IOM uint32_t PUD0 : 2;   /*!< [3..2] Pm_0 Pull-Up/Down Control                                          */
1045             __IOM uint32_t SMT0 : 1;   /*!< [4..4] Pm_0 Schmitt Trigger Control                                       */
1046             __IOM uint32_t SR0  : 1;   /*!< [5..5] Pm_0 Slew Rate Control                                             */
1047             uint32_t            : 2;
1048             __IOM uint32_t DRV1 : 2;   /*!< [9..8] Pm_1 Driving Ability Control                                       */
1049             __IOM uint32_t PUD1 : 2;   /*!< [11..10] Pm_1 Pull-Up/Down Control                                        */
1050             __IOM uint32_t SMT1 : 1;   /*!< [12..12] Pm_1 Schmitt Trigger Control                                     */
1051             __IOM uint32_t SR1  : 1;   /*!< [13..13] Pm_1 Slew Rate Control                                           */
1052             uint32_t            : 2;
1053             __IOM uint32_t DRV2 : 2;   /*!< [17..16] Pm_2 Driving Ability Control                                     */
1054             __IOM uint32_t PUD2 : 2;   /*!< [19..18] Pm_2 Pull-Up/Down Control                                        */
1055             __IOM uint32_t SMT2 : 1;   /*!< [20..20] Pm_2 Schmitt Trigger Control                                     */
1056             __IOM uint32_t SR2  : 1;   /*!< [21..21] Pm_2 Slew Rate Control                                           */
1057             uint32_t            : 2;
1058             __IOM uint32_t DRV3 : 2;   /*!< [25..24] Pm_3 Driving Ability Control                                     */
1059             __IOM uint32_t PUD3 : 2;   /*!< [27..26] Pm_3 Pull-Up/Down Control                                        */
1060             __IOM uint32_t SMT3 : 1;   /*!< [28..28] Pm_3 Schmitt Trigger Control                                     */
1061             __IOM uint32_t SR3  : 1;   /*!< [29..29] Pm_3 Slew Rate Control                                           */
1062             uint32_t            : 2;
1063         } L_b;
1064     };
1065 
1066     union
1067     {
1068         __IOM uint32_t H;              /*!< (@ 0x00000004) I/O Buffer m Function Switching Register 4-7               */
1069 
1070         struct
1071         {
1072             __IOM uint32_t DRV4 : 2;   /*!< [1..0] Pm_4 Driving Ability Control                                       */
1073             __IOM uint32_t PUD4 : 2;   /*!< [3..2] Pm_4 Pull-Up/Down Control                                          */
1074             __IOM uint32_t SMT4 : 1;   /*!< [4..4] Pm_4 Schmitt Trigger Control                                       */
1075             __IOM uint32_t SR4  : 1;   /*!< [5..5] Pm_4 Slew Rate Control                                             */
1076             uint32_t            : 2;
1077             __IOM uint32_t DRV5 : 2;   /*!< [9..8] Pm_5 Driving Ability Control                                       */
1078             __IOM uint32_t PUD5 : 2;   /*!< [11..10] Pm_5 Pull-Up/Down Control                                        */
1079             __IOM uint32_t SMT5 : 1;   /*!< [12..12] Pm_5 Schmitt Trigger Control                                     */
1080             __IOM uint32_t SR5  : 1;   /*!< [13..13] Pm_5 Slew Rate Control                                           */
1081             uint32_t            : 2;
1082             __IOM uint32_t DRV6 : 2;   /*!< [17..16] Pm_6 Driving Ability Control                                     */
1083             __IOM uint32_t PUD6 : 2;   /*!< [19..18] Pm_6 Pull-Up/Down Control                                        */
1084             __IOM uint32_t SMT6 : 1;   /*!< [20..20] Pm_6 Schmitt Trigger Control                                     */
1085             __IOM uint32_t SR6  : 1;   /*!< [21..21] Pm_6 Slew Rate Control                                           */
1086             uint32_t            : 2;
1087             __IOM uint32_t DRV7 : 2;   /*!< [25..24] Pm_7 Driving Ability Control                                     */
1088             __IOM uint32_t PUD7 : 2;   /*!< [27..26] Pm_7 Pull-Up/Down Control                                        */
1089             __IOM uint32_t SMT7 : 1;   /*!< [28..28] Pm_7 Schmitt Trigger Control                                     */
1090             __IOM uint32_t SR7  : 1;   /*!< [29..29] Pm_7 Slew Rate Control                                           */
1091             uint32_t            : 2;
1092         } H_b;
1093     };
1094 } R_PORT_DRCTL_Type;                   /*!< Size = 8 (0x8)                                                            */
1095 
1096 /**
1097  * @brief R_PORT_NSR_ELC_PDBF [ELC_PDBF] (ELC Port Buffer Register [0..1])
1098  */
1099 typedef struct
1100 {
1101     union
1102     {
1103         __IOM uint8_t BY;              /*!< (@ 0x00000000) ELC Port Buffer Register n                                 */
1104 
1105         struct
1106         {
1107             __IOM uint8_t PB0 : 1;     /*!< [0..0] Port Buffer 0                                                      */
1108             __IOM uint8_t PB1 : 1;     /*!< [1..1] Port Buffer 1                                                      */
1109             __IOM uint8_t PB2 : 1;     /*!< [2..2] Port Buffer 2                                                      */
1110             __IOM uint8_t PB3 : 1;     /*!< [3..3] Port Buffer 3                                                      */
1111             __IOM uint8_t PB4 : 1;     /*!< [4..4] Port Buffer 4                                                      */
1112             __IOM uint8_t PB5 : 1;     /*!< [5..5] Port Buffer 5                                                      */
1113             __IOM uint8_t PB6 : 1;     /*!< [6..6] Port Buffer 6                                                      */
1114             __IOM uint8_t PB7 : 1;     /*!< [7..7] Port Buffer 7                                                      */
1115         } BY_b;
1116     };
1117     __IM uint8_t RESERVED[3];
1118 } R_PORT_NSR_ELC_PDBF_Type;            /*!< Size = 4 (0x4)                                                            */
1119 
1120 /**
1121  * @brief R_ETHSW_PTP_SWTM [SWTM] (Ethernet Switch Timer output pins 0-3 Registers)
1122  */
1123 typedef struct
1124 {
1125     union
1126     {
1127         __IOM uint32_t EN;             /*!< (@ 0x00000000) PTP Timer Pulse Output Enable n Register                   */
1128 
1129         struct
1130         {
1131             __IOM uint32_t OUTEN : 1;  /*!< [0..0] Enable ETHSW_PTPOUTn Signal Output                                 */
1132             uint32_t             : 31;
1133         } EN_b;
1134     };
1135 
1136     union
1137     {
1138         __IOM uint32_t STSEC;          /*!< (@ 0x00000004) PTP Timer Pulse Start Second n Register                    */
1139 
1140         struct
1141         {
1142             __IOM uint32_t STSEC : 32; /*!< [31..0] STSEC                                                             */
1143         } STSEC_b;
1144     };
1145 
1146     union
1147     {
1148         __IOM uint32_t STNS;           /*!< (@ 0x00000008) PTP Timer Pulse Start Nanosecond n Register                */
1149 
1150         struct
1151         {
1152             __IOM uint32_t STNS : 32;  /*!< [31..0] Start Time by Nanosecond                                          */
1153         } STNS_b;
1154     };
1155 
1156     union
1157     {
1158         __IOM uint32_t PSEC;           /*!< (@ 0x0000000C) PTP Timer Pulse Period Second n Register                   */
1159 
1160         struct
1161         {
1162             __IOM uint32_t PSEC : 32;  /*!< [31..0] PSEC                                                              */
1163         } PSEC_b;
1164     };
1165 
1166     union
1167     {
1168         __IOM uint32_t PNS;            /*!< (@ 0x00000010) PTP Timer Pulse Period Nanosecond n Register               */
1169 
1170         struct
1171         {
1172             __IOM uint32_t PNS : 32;   /*!< [31..0] Period by Nanosecond                                              */
1173         } PNS_b;
1174     };
1175 
1176     union
1177     {
1178         __IOM uint32_t WTH;            /*!< (@ 0x00000014) PTP Timer Pulse Width n Register                           */
1179 
1180         struct
1181         {
1182             __IOM uint32_t WIDTH : 16; /*!< [15..0] Set the Pulse Width of ETHSW_PTPOUTn in the cycle number
1183                                         *   of ts_clk (8 ns).                                                         */
1184             uint32_t : 16;
1185         } WTH_b;
1186     };
1187 
1188     union
1189     {
1190         __IOM uint32_t MAXP;           /*!< (@ 0x00000018) PTP Timer Pulse Max Second n Register                      */
1191 
1192         struct
1193         {
1194             __IOM uint32_t MAXP : 32;  /*!< [31..0] Sets the boundary value in nanoseconds to carry from
1195                                         *   the nanosecond field to the second field. The same value
1196                                         *   as ATIME_EVT_PERIOD register must be set.                                 */
1197         } MAXP_b;
1198     };
1199 
1200     union
1201     {
1202         __IOM uint32_t LATSEC;          /*!< (@ 0x0000001C) PTP Timer Pulse Latch Second n Register                    */
1203 
1204         struct
1205         {
1206             __IOM uint32_t LATSEC : 32; /*!< [31..0] LATSEC                                                            */
1207         } LATSEC_b;
1208     };
1209 
1210     union
1211     {
1212         __IOM uint32_t LATNS;          /*!< (@ 0x00000020) PTP Timer Pulse Latch Nanosecond n Register                */
1213 
1214         struct
1215         {
1216             __IOM uint32_t LATNS : 32; /*!< [31..0] LATNS                                                             */
1217         } LATNS_b;
1218     };
1219     __IM uint32_t RESERVED[55];
1220 } R_ETHSW_PTP_SWTM_Type;               /*!< Size = 256 (0x100)                                                        */
1221 
1222 /**
1223  * @brief R_ETHSW_MGMT_ADDR [MGMT_ADDR] (MAC Address [0..3] for Bridge Protocol Frame Register)
1224  */
1225 typedef struct
1226 {
1227     union
1228     {
1229         __IOM uint32_t lo;                /*!< (@ 0x00000000) Lower MAC Address                                          */
1230 
1231         struct
1232         {
1233             __IOM uint32_t BPDU_DST : 32; /*!< [31..0] Additional MAC address defining a Bridge Protocol Frame
1234                                            *   (BPDU) in addition to the commonly-known addresses                        */
1235         } lo_b;
1236     };
1237 
1238     union
1239     {
1240         __IOM uint32_t hi;                /*!< (@ 0x00000004) Higher MAC Address                                         */
1241 
1242         struct
1243         {
1244             __IOM uint32_t BPDU_DST : 16; /*!< [15..0] Bits [7:0] is 5th byte, bits [15:8] is 6th (last) byte            */
1245             __IOM uint32_t MASK     : 8;  /*!< [23..16] 8-bit mask for comparing the last byte of the MAC address.       */
1246             uint32_t                : 8;
1247         } hi_b;
1248     };
1249 } R_ETHSW_MGMT_ADDR_Type;                 /*!< Size = 8 (0x8)                                                            */
1250 
1251 /**
1252  * @brief R_ESC_FMMU [FMMU] (FMMU [0..7] Registers (n = 0 to 7))
1253  */
1254 typedef struct
1255 {
1256     union
1257     {
1258         __IM uint32_t L_START_ADR;      /*!< (@ 0x00000000) FMMU Logical Start Address n Register (n = 0
1259                                          *                  to 7)                                                      */
1260 
1261         struct
1262         {
1263             __IM uint32_t LSTAADR : 32; /*!< [31..0] Logical Start Address Setting                                     */
1264         } L_START_ADR_b;
1265     };
1266 
1267     union
1268     {
1269         __IM uint16_t LEN;              /*!< (@ 0x00000004) FMMU Length n Register (n = 0 to 7)                        */
1270 
1271         struct
1272         {
1273             __IM uint16_t FMMULEN : 16; /*!< [15..0] Area Size Specification                                           */
1274         } LEN_b;
1275     };
1276 
1277     union
1278     {
1279         __IM uint8_t L_START_BIT;      /*!< (@ 0x00000006) FMMU Logical Start Bit n Register (n = 0 to 7)             */
1280 
1281         struct
1282         {
1283             __IM uint8_t LSTABIT : 3;  /*!< [2..0] Start Bit Setting                                                  */
1284             uint8_t              : 5;
1285         } L_START_BIT_b;
1286     };
1287 
1288     union
1289     {
1290         __IM uint8_t L_STOP_BIT;       /*!< (@ 0x00000007) FMMU Logical Stop Bit n Register (n = 0 to 7)              */
1291 
1292         struct
1293         {
1294             __IM uint8_t LSTPBIT : 3;  /*!< [2..0] Last Bit Setting                                                   */
1295             uint8_t              : 5;
1296         } L_STOP_BIT_b;
1297     };
1298 
1299     union
1300     {
1301         __IM uint16_t P_START_ADR;        /*!< (@ 0x00000008) FMMU Physical Start Address n Register (n = 0
1302                                            *                  to 7)                                                      */
1303 
1304         struct
1305         {
1306             __IM uint16_t PHYSTAADR : 16; /*!< [15..0] Physical Start Address Setting                                    */
1307         } P_START_ADR_b;
1308     };
1309 
1310     union
1311     {
1312         __IM uint8_t P_START_BIT;       /*!< (@ 0x0000000A) FMMU Physical Start Bit n Register (n = 0 to
1313                                          *                  7)                                                         */
1314 
1315         struct
1316         {
1317             __IM uint8_t PHYSTABIT : 3; /*!< [2..0] Physical Start Bit Setting                                         */
1318             uint8_t                : 5;
1319         } P_START_BIT_b;
1320     };
1321 
1322     union
1323     {
1324         __IM uint8_t TYPE;             /*!< (@ 0x0000000B) FMMU Type n Register (n = 0 to 7)                          */
1325 
1326         struct
1327         {
1328             __IM uint8_t READ  : 1;    /*!< [0..0] Read Access Mapping Setting                                        */
1329             __IM uint8_t WRITE : 1;    /*!< [1..1] Write Access Mapping Setting                                       */
1330             uint8_t            : 6;
1331         } TYPE_b;
1332     };
1333 
1334     union
1335     {
1336         __IM uint8_t ACT;              /*!< (@ 0x0000000C) FMMU Activate n Register (n = 0 to 7)                      */
1337 
1338         struct
1339         {
1340             __IM uint8_t ACTIVATE : 1; /*!< [0..0] FMMU Enable/Disable                                                */
1341             uint8_t               : 7;
1342         } ACT_b;
1343     };
1344     __IM uint8_t  RESERVED;
1345     __IM uint16_t RESERVED1;
1346 } R_ESC_FMMU_Type;                     /*!< Size = 16 (0x10)                                                          */
1347 
1348 /**
1349  * @brief R_ESC_SM [SM] (SyncManager [0..7] Registers (n = 0 to 7))
1350  */
1351 typedef struct
1352 {
1353     union
1354     {
1355         __IM uint16_t P_START_ADR;        /*!< (@ 0x00000000) SyncManager Physical Start Address n Register
1356                                            *                  (n = 0 to 7)                                               */
1357 
1358         struct
1359         {
1360             __IM uint16_t SMSTAADDR : 16; /*!< [15..0] Physical Start Address Setting                                    */
1361         } P_START_ADR_b;
1362     };
1363 
1364     union
1365     {
1366         __IM uint16_t LEN;             /*!< (@ 0x00000002) SyncManager Length n Register (n = 0 to 7)                 */
1367 
1368         struct
1369         {
1370             __IM uint16_t SMLEN : 16;  /*!< [15..0] Area Size Setting                                                 */
1371         } LEN_b;
1372     };
1373 
1374     union
1375     {
1376         __IM uint8_t CONTROL;          /*!< (@ 0x00000004) SyncManager Control n Register (n = 0 to 7)                */
1377 
1378         struct
1379         {
1380             __IM uint8_t OPEMODE : 2;  /*!< [1..0] Operating Mode Setting                                             */
1381             __IM uint8_t DIR     : 2;  /*!< [3..2] Transfer Direction Setting                                         */
1382             __IM uint8_t IRQECAT : 1;  /*!< [4..4] ECAT Event Interrupt Setting                                       */
1383             __IM uint8_t IRQPDI  : 1;  /*!< [5..5] AL Event Interrupt Setting                                         */
1384             __IM uint8_t WDTRGEN : 1;  /*!< [6..6] Watchdog Trigger Setting                                           */
1385             uint8_t              : 1;
1386         } CONTROL_b;
1387     };
1388 
1389     union
1390     {
1391         __IM uint8_t STATUS;           /*!< (@ 0x00000005) SyncManager Status n Register (n = 0 to 7)                 */
1392 
1393         struct
1394         {
1395             __IM uint8_t INTWR    : 1; /*!< [0..0] Write Complete Interrupt State Indication                          */
1396             __IM uint8_t INTRD    : 1; /*!< [1..1] Read Complete Interrupt State Indication                           */
1397             uint8_t               : 1;
1398             __IM uint8_t MAILBOX  : 1; /*!< [3..3] Mailbox Status Indication                                          */
1399             __IM uint8_t BUFFERED : 2; /*!< [5..4] Buffer Status Indication                                           */
1400             __IM uint8_t RDBUF    : 1; /*!< [6..6] Read State Indication                                              */
1401             __IM uint8_t WRBUF    : 1; /*!< [7..7] Write State Indication                                             */
1402         } STATUS_b;
1403     };
1404 
1405     union
1406     {
1407         __IM uint8_t ACT;               /*!< (@ 0x00000006) SyncManager Activate n Register (n = 0 to 7)               */
1408 
1409         struct
1410         {
1411             __IM uint8_t SMEN      : 1; /*!< [0..0] SyncManager Enable/Disable                                         */
1412             __IM uint8_t REPEATREQ : 1; /*!< [1..1] Repeat Request                                                     */
1413             uint8_t                : 4;
1414             __IM uint8_t LATCHECAT : 1; /*!< [6..6] ECAT Latch Event Specification                                     */
1415             __IM uint8_t LATCHPDI  : 1; /*!< [7..7] PDI Latch Event Specification                                      */
1416         } ACT_b;
1417     };
1418 
1419     union
1420     {
1421         __IOM uint8_t PDI_CONT;          /*!< (@ 0x00000007) SyncManager PDI Control n Register (n = 0 to
1422                                           *                  7)                                                         */
1423 
1424         struct
1425         {
1426             __IOM uint8_t DEACTIVE  : 1; /*!< [0..0] SyncManager Operation Indication/Setting                           */
1427             __IOM uint8_t REPEATACK : 1; /*!< [1..1] Repeat Acknowledge                                                 */
1428             uint8_t                 : 6;
1429         } PDI_CONT_b;
1430     };
1431 } R_ESC_SM_Type;                         /*!< Size = 8 (0x8)                                                            */
1432 
1433 /**
1434  * @brief R_USBF_PIPE_TR [PIPE_TR] (PIPEn Transaction Counter Registers (n=1-5))
1435  */
1436 typedef struct
1437 {
1438     union
1439     {
1440         __IOM uint16_t E;              /*!< (@ 0x00000000) PIPEn Transaction Counter Enable Register                  */
1441 
1442         struct
1443         {
1444             uint16_t             : 8;
1445             __IOM uint16_t TRCLR : 1;  /*!< [8..8] Transaction Counter Clear                                          */
1446             __IOM uint16_t TRENB : 1;  /*!< [9..9] Transaction Counter Enable                                         */
1447             uint16_t             : 6;
1448         } E_b;
1449     };
1450 
1451     union
1452     {
1453         __IOM uint16_t N;               /*!< (@ 0x00000002) PIPEn Transaction Counter Register                         */
1454 
1455         struct
1456         {
1457             __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter                                               */
1458         } N_b;
1459     };
1460 } R_USBF_PIPE_TR_Type;                  /*!< Size = 4 (0x4)                                                            */
1461 
1462 /**
1463  * @brief R_USBF_CHa_N [N] (Address Registers n (n=0-1))
1464  */
1465 typedef struct
1466 {
1467     union
1468     {
1469         __IOM uint32_t SA;             /*!< (@ 0x00000000) Next Source Address Register                               */
1470 
1471         struct
1472         {
1473             __IOM uint32_t SAWD : 32;  /*!< [31..0] Source Address or Write Data                                      */
1474         } SA_b;
1475     };
1476 
1477     union
1478     {
1479         __IOM uint32_t DA;             /*!< (@ 0x00000004) Next Destination Address Register                          */
1480 
1481         struct
1482         {
1483             __IOM uint32_t DA : 32;    /*!< [31..0] Destination Address                                               */
1484         } DA_b;
1485     };
1486 
1487     union
1488     {
1489         __IOM uint32_t TB;             /*!< (@ 0x00000008) Next Transaction Byte Register                             */
1490 
1491         struct
1492         {
1493             __IOM uint32_t TB : 32;    /*!< [31..0] Transaction Byte                                                  */
1494         } TB_b;
1495     };
1496 } R_USBF_CHa_N_Type;                   /*!< Size = 12 (0xc)                                                           */
1497 
1498 /**
1499  * @brief R_USBF_CHa [CHa] (Next Register Set)
1500  */
1501 typedef struct
1502 {
1503     __IOM R_USBF_CHa_N_Type N[2];      /*!< (@ 0x00000000) Address Registers n (n=0-1)                                */
1504 
1505     union
1506     {
1507         __IM uint32_t CRSA;            /*!< (@ 0x00000018) Current Source Address Register                            */
1508 
1509         struct
1510         {
1511             __IM uint32_t CRSA : 32;   /*!< [31..0] Source Address                                                    */
1512         } CRSA_b;
1513     };
1514 
1515     union
1516     {
1517         __IM uint32_t CRDA;            /*!< (@ 0x0000001C) Current Destination Address Register                       */
1518 
1519         struct
1520         {
1521             __IM uint32_t CRDA : 32;   /*!< [31..0] Destination Address                                               */
1522         } CRDA_b;
1523     };
1524 
1525     union
1526     {
1527         __IM uint32_t CRTB;            /*!< (@ 0x00000020) Current Transaction Byte Register                          */
1528 
1529         struct
1530         {
1531             __IM uint32_t CRTB : 32;   /*!< [31..0] Transaction Byte                                                  */
1532         } CRTB_b;
1533     };
1534 
1535     union
1536     {
1537         __IM uint32_t CHSTAT;          /*!< (@ 0x00000024) Channel Status Register                                    */
1538 
1539         struct
1540         {
1541             __IM uint32_t EN     : 1;  /*!< [0..0] Enable                                                             */
1542             __IM uint32_t RQST   : 1;  /*!< [1..1] Request                                                            */
1543             __IM uint32_t TACT   : 1;  /*!< [2..2] Transaction Active                                                 */
1544             __IM uint32_t SUS    : 1;  /*!< [3..3] Suspend                                                            */
1545             __IM uint32_t ER     : 1;  /*!< [4..4] Error                                                              */
1546             __IM uint32_t END    : 1;  /*!< [5..5] USB_FDMAn Interrupted                                              */
1547             __IM uint32_t TC     : 1;  /*!< [6..6] Terminal Count                                                     */
1548             __IM uint32_t SR     : 1;  /*!< [7..7] Selected Register Set                                              */
1549             __IM uint32_t DL     : 1;  /*!< [8..8] Descriptor Load                                                    */
1550             __IM uint32_t DW     : 1;  /*!< [9..9] Descriptor WriteBack                                               */
1551             __IM uint32_t DER    : 1;  /*!< [10..10] Descriptor Error                                                 */
1552             __IM uint32_t MODE   : 1;  /*!< [11..11] DMA Mode                                                         */
1553             uint32_t             : 4;
1554             __IM uint32_t INTM   : 1;  /*!< [16..16] Interrupt Mask                                                   */
1555             __IM uint32_t DMARQM : 1;  /*!< [17..17] DMAREQ Mask                                                      */
1556             __IM uint32_t SWPRQ  : 1;  /*!< [18..18] Sweep Request                                                    */
1557             uint32_t             : 5;
1558             __IM uint32_t DNUM   : 8;  /*!< [31..24] Data Number                                                      */
1559         } CHSTAT_b;
1560     };
1561 
1562     union
1563     {
1564         __OM uint32_t CHCTRL;            /*!< (@ 0x00000028) Channel Control Register                                   */
1565 
1566         struct
1567         {
1568             __OM uint32_t SETEN     : 1; /*!< [0..0] Set Enable                                                         */
1569             __OM uint32_t CLREN     : 1; /*!< [1..1] Clear Enable                                                       */
1570             __OM uint32_t STG       : 1; /*!< [2..2] Software Trigger                                                   */
1571             __OM uint32_t SWRST     : 1; /*!< [3..3] Software Reset                                                     */
1572             __OM uint32_t CLRRQ     : 1; /*!< [4..4] Clear Request                                                      */
1573             __OM uint32_t CLREND    : 1; /*!< [5..5] Clear End                                                          */
1574             __OM uint32_t CLRTC     : 1; /*!< [6..6] Clear TC                                                           */
1575             __OM uint32_t CLRDER    : 1; /*!< [7..7] Clear DER                                                          */
1576             __OM uint32_t SETSUS    : 1; /*!< [8..8] Set Suspend                                                        */
1577             __OM uint32_t CLRSUS    : 1; /*!< [9..9] Clear Suspend                                                      */
1578             uint32_t                : 2;
1579             __OM uint32_t SETREN    : 1; /*!< [12..12] Set Register Set Enable                                          */
1580             uint32_t                : 1;
1581             __OM uint32_t SETSSWPRQ : 1; /*!< [14..14] Set Software Sweep Request                                       */
1582             uint32_t                : 1;
1583             __OM uint32_t SETINTM   : 1; /*!< [16..16] Set Interrupt Mask                                               */
1584             __OM uint32_t CLRINTM   : 1; /*!< [17..17] Clear Interrupt Mask                                             */
1585             __OM uint32_t SETDMARQM : 1; /*!< [18..18] SET DMAREQ Mask                                                  */
1586             __OM uint32_t CLRDMARQM : 1; /*!< [19..19] Clear DMAREQ Mask                                                */
1587             uint32_t                : 12;
1588         } CHCTRL_b;
1589     };
1590 
1591     union
1592     {
1593         __IOM uint32_t CHCFG;          /*!< (@ 0x0000002C) Channel Configuration Register                             */
1594 
1595         struct
1596         {
1597             __IOM uint32_t SEL  : 1;   /*!< [0..0] Terminal Select                                                    */
1598             uint32_t            : 2;
1599             __IOM uint32_t REQD : 1;   /*!< [3..3] Request Direction                                                  */
1600             __IOM uint32_t LOEN : 1;   /*!< [4..4] Sets the transfer request signal between the USB control
1601                                         *   and the DMAC.                                                             */
1602             __IOM uint32_t HIEN : 1;   /*!< [5..5] Sets the transfer request signal between the USB control
1603                                         *   and the DMAC.                                                             */
1604             __IOM uint32_t LVL : 1;    /*!< [6..6] Sets the transfer request signal between the USB control
1605                                         *   and the DMAC.                                                             */
1606             uint32_t          : 1;
1607             __IOM uint32_t AM : 3;     /*!< [10..8] These bits set the transfer request signal between the
1608                                         *   USB control and the DMAC.                                                 */
1609             __IOM uint32_t DRRP : 1;   /*!< [11..11] Descriptor Read Repeat                                           */
1610             __IOM uint32_t SDS  : 4;   /*!< [15..12] Source Data Size                                                 */
1611             __IOM uint32_t DDS  : 4;   /*!< [19..16] Destination Data Size                                            */
1612             __IOM uint32_t SAD  : 1;   /*!< [20..20] Source Address Direction                                         */
1613             __IOM uint32_t DAD  : 1;   /*!< [21..21] Destination Address Direction                                    */
1614             __IOM uint32_t TM   : 1;   /*!< [22..22] Sets the transfer request signal between the USB control
1615                                         *   and the DMAC.                                                             */
1616             __IOM uint32_t WONLY : 1;  /*!< [23..23] Write Only Mode                                                  */
1617             __IOM uint32_t DEM   : 1;  /*!< [24..24] USB_FDMAn Mask                                                   */
1618             uint32_t             : 1;
1619             __IOM uint32_t DIM   : 1;  /*!< [26..26] Descriptor Interrupt Mask                                        */
1620             __IOM uint32_t SBE   : 1;  /*!< [27..27] Sweep Buffer Enable                                              */
1621             __IOM uint32_t RSEL  : 1;  /*!< [28..28] Register Set Select                                              */
1622             __IOM uint32_t RSW   : 1;  /*!< [29..29] Register Select Switch                                           */
1623             __IOM uint32_t REN   : 1;  /*!< [30..30] Register Set Enable                                              */
1624             __IOM uint32_t DMS   : 1;  /*!< [31..31] DMA Mode Select                                                  */
1625         } CHCFG_b;
1626     };
1627 
1628     union
1629     {
1630         __IOM uint32_t CHITVL;         /*!< (@ 0x00000030) Channel Interval Register                                  */
1631 
1632         struct
1633         {
1634             __IOM uint32_t ITVL : 16;  /*!< [15..0] Interval                                                          */
1635             uint32_t            : 16;
1636         } CHITVL_b;
1637     };
1638 
1639     union
1640     {
1641         __IOM uint32_t CHEXT;          /*!< (@ 0x00000034) Channel Extension Register                                 */
1642 
1643         struct
1644         {
1645             __IOM uint32_t SPR : 4;    /*!< [3..0] Source PROT                                                        */
1646             uint32_t           : 4;
1647             __IOM uint32_t DPR : 4;    /*!< [11..8] Destination PROT                                                  */
1648             uint32_t           : 20;
1649         } CHEXT_b;
1650     };
1651 
1652     union
1653     {
1654         __IOM uint32_t NXLA;           /*!< (@ 0x00000038) Next Link Address Register                                 */
1655 
1656         struct
1657         {
1658             __IOM uint32_t NXLA : 32;  /*!< [31..0] Next Link Address                                                 */
1659         } NXLA_b;
1660     };
1661 
1662     union
1663     {
1664         __IM uint32_t CRLA;            /*!< (@ 0x0000003C) Current Link Address Register                              */
1665 
1666         struct
1667         {
1668             __IM uint32_t CRLA : 32;   /*!< [31..0] Current Link Address                                              */
1669         } CRLA_b;
1670     };
1671 } R_USBF_CHa_Type;                     /*!< Size = 64 (0x40)                                                          */
1672 
1673 /**
1674  * @brief R_USBF_CHb [CHb] (Skip Register Set)
1675  */
1676 typedef struct
1677 {
1678     union
1679     {
1680         __IOM uint32_t SCNT;           /*!< (@ 0x00000000) Source Continuous Register                                 */
1681 
1682         struct
1683         {
1684             __IOM uint32_t SCNT : 32;  /*!< [31..0] Source Continuous                                                 */
1685         } SCNT_b;
1686     };
1687 
1688     union
1689     {
1690         __IOM uint32_t SSKP;           /*!< (@ 0x00000004) Source Skip Register                                       */
1691 
1692         struct
1693         {
1694             __IOM uint32_t SSKP : 32;  /*!< [31..0] Source Skip                                                       */
1695         } SSKP_b;
1696     };
1697 
1698     union
1699     {
1700         __IOM uint32_t DCNT;           /*!< (@ 0x00000008) Destination Continuous Register                            */
1701 
1702         struct
1703         {
1704             __IOM uint32_t DCNT : 32;  /*!< [31..0] Destination Continuous                                            */
1705         } DCNT_b;
1706     };
1707 
1708     union
1709     {
1710         __IOM uint32_t DSKP;           /*!< (@ 0x0000000C) Destination Skip Register                                  */
1711 
1712         struct
1713         {
1714             __IOM uint32_t DSKP : 32;  /*!< [31..0] Destination Skip                                                  */
1715         } DSKP_b;
1716     };
1717     __IM uint32_t RESERVED[4];
1718 } R_USBF_CHb_Type;                     /*!< Size = 32 (0x20)                                                          */
1719 
1720 /**
1721  * @brief R_XSPI0_CSa [CSa] (xSPI Command Map Configuration Register [0..1])
1722  */
1723 typedef struct
1724 {
1725     union
1726     {
1727         __IOM uint32_t CMCFG0;          /*!< (@ 0x00000000) xSPI Command Map Configuration Register 0 CSn              */
1728 
1729         struct
1730         {
1731             __IOM uint32_t FFMT    : 2; /*!< [1..0] Frame format                                                       */
1732             __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size                                                       */
1733             uint32_t               : 12;
1734             __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable                                           */
1735             __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code                                             */
1736         } CMCFG0_b;
1737     };
1738 
1739     union
1740     {
1741         __IOM uint32_t CMCFG1;          /*!< (@ 0x00000004) xSPI Command Map Configuration Register 1 CSn              */
1742 
1743         struct
1744         {
1745             __IOM uint32_t RDCMD  : 16; /*!< [15..0] Read command                                                      */
1746             __IOM uint32_t RDLATE : 5;  /*!< [20..16] Read latency cycle                                               */
1747             uint32_t              : 11;
1748         } CMCFG1_b;
1749     };
1750 
1751     union
1752     {
1753         __IOM uint32_t CMCFG2;          /*!< (@ 0x00000008) xSPI Command Map Configuration Register 2 CSn              */
1754 
1755         struct
1756         {
1757             __IOM uint32_t WRCMD  : 16; /*!< [15..0] Write command                                                     */
1758             __IOM uint32_t WRLATE : 5;  /*!< [20..16] Write latency cycle                                              */
1759             uint32_t              : 11;
1760         } CMCFG2_b;
1761     };
1762     __IM uint32_t RESERVED;
1763 } R_XSPI0_CSa_Type;                    /*!< Size = 16 (0x10)                                                          */
1764 
1765 /**
1766  * @brief R_XSPI0_BUF [BUF] (xSPI Command Manual Buf [0..3])
1767  */
1768 typedef struct
1769 {
1770     union
1771     {
1772         __IOM uint32_t CDT;               /*!< (@ 0x00000000) xSPI Command Manual Type Buf                               */
1773 
1774         struct
1775         {
1776             __IOM uint32_t CMDSIZE  : 2;  /*!< [1..0] Command Size                                                       */
1777             __IOM uint32_t ADDSIZE  : 3;  /*!< [4..2] Address size                                                       */
1778             __IOM uint32_t DATASIZE : 4;  /*!< [8..5] Write/Read Data Size                                               */
1779             __IOM uint32_t LATE     : 5;  /*!< [13..9] Latency cycle                                                     */
1780             uint32_t                : 1;
1781             __IOM uint32_t TRTYPE   : 1;  /*!< [15..15] Transaction Type                                                 */
1782             __IOM uint32_t CMD      : 16; /*!< [31..16] Command (1-2 bytes)                                              */
1783         } CDT_b;
1784     };
1785 
1786     union
1787     {
1788         __IOM uint32_t CDA;            /*!< (@ 0x00000004) xSPI Command Manual Address Buf                            */
1789 
1790         struct
1791         {
1792             __IOM uint32_t ADD : 32;   /*!< [31..0] Address                                                           */
1793         } CDA_b;
1794     };
1795 
1796     union
1797     {
1798         __IOM uint32_t CDD0;           /*!< (@ 0x00000008) xSPI Command Manual Data 0 Buf                             */
1799 
1800         struct
1801         {
1802             __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
1803         } CDD0_b;
1804     };
1805 
1806     union
1807     {
1808         __IOM uint32_t CDD1;           /*!< (@ 0x0000000C) xSPI Command Manual Data 1 Buf                             */
1809 
1810         struct
1811         {
1812             __IOM uint32_t DATA : 32;  /*!< [31..0] Write/Read Data                                                   */
1813         } CDD1_b;
1814     };
1815 } R_XSPI0_BUF_Type;                    /*!< Size = 16 (0x10)                                                          */
1816 
1817 /**
1818  * @brief R_XSPI0_CSb [CSb] (xSPI Command Calibration Control register [0..1])
1819  */
1820 typedef struct
1821 {
1822     union
1823     {
1824         __IOM uint32_t CCCTL0;           /*!< (@ 0x00000000) xSPI Command Calibration Control Register 0 CSn            */
1825 
1826         struct
1827         {
1828             __IOM uint32_t CAEN     : 1; /*!< [0..0] Automatic Calibration Enable                                       */
1829             __IOM uint32_t CANOWR   : 1; /*!< [1..1] Calibration no write mode                                          */
1830             uint32_t                : 6;
1831             __IOM uint32_t CAITV    : 5; /*!< [12..8] Calibration interval                                              */
1832             uint32_t                : 3;
1833             __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value                                 */
1834             uint32_t                : 3;
1835             __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value                                   */
1836             uint32_t                : 3;
1837         } CCCTL0_b;
1838     };
1839 
1840     union
1841     {
1842         __IOM uint32_t CCCTL1;             /*!< (@ 0x00000004) xSPI Command Calibration Control Register 1 CSn            */
1843 
1844         struct
1845         {
1846             __IOM uint32_t CACMDSIZE  : 2; /*!< [1..0] Command Size                                                       */
1847             __IOM uint32_t CAADDSIZE  : 3; /*!< [4..2] Address size                                                       */
1848             __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size                                               */
1849             uint32_t                  : 7;
1850             __IOM uint32_t CAWRLATE   : 5; /*!< [20..16] Write Latency cycle                                              */
1851             uint32_t                  : 3;
1852             __IOM uint32_t CARDLATE   : 5; /*!< [28..24] Read Latency cycle                                               */
1853             uint32_t                  : 3;
1854         } CCCTL1_b;
1855     };
1856 
1857     union
1858     {
1859         __IOM uint32_t CCCTL2;           /*!< (@ 0x00000008) xSPI Command Calibration Control Register 2 CSn            */
1860 
1861         struct
1862         {
1863             __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command                                 */
1864             __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command                                 */
1865         } CCCTL2_b;
1866     };
1867 
1868     union
1869     {
1870         __IOM uint32_t CCCTL3;         /*!< (@ 0x0000000C) xSPI Command Calibration Control Register 3 CSn            */
1871 
1872         struct
1873         {
1874             __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address                                       */
1875         } CCCTL3_b;
1876     };
1877 
1878     union
1879     {
1880         __IOM uint32_t CCCTL4;          /*!< (@ 0x00000010) xSPI Command Calibration Control Register 4 CSn            */
1881 
1882         struct
1883         {
1884             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
1885         } CCCTL4_b;
1886     };
1887 
1888     union
1889     {
1890         __IOM uint32_t CCCTL5;          /*!< (@ 0x00000014) xSPI Command Calibration Control Register 5 CSn            */
1891 
1892         struct
1893         {
1894             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
1895         } CCCTL5_b;
1896     };
1897 
1898     union
1899     {
1900         __IOM uint32_t CCCTL6;          /*!< (@ 0x00000018) xSPI Command Calibration Control Register 6 CSn            */
1901 
1902         struct
1903         {
1904             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
1905         } CCCTL6_b;
1906     };
1907 
1908     union
1909     {
1910         __IOM uint32_t CCCTL7;          /*!< (@ 0x0000001C) xSPI Command Calibration Control Register 7 CSn            */
1911 
1912         struct
1913         {
1914             __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data                                          */
1915         } CCCTL7_b;
1916     };
1917 } R_XSPI0_CSb_Type;                     /*!< Size = 32 (0x20)                                                          */
1918 
1919 /**
1920  * @brief R_SYSRAM0_W [W] (System SRAM Wn Registers (n = 0 to 3))
1921  */
1922 typedef struct
1923 {
1924     union
1925     {
1926         __IOM uint32_t EC710CTL;        /*!< (@ 0x00000000) ECC Control Register                                       */
1927 
1928         struct
1929         {
1930             __IM uint32_t  ECEMF   : 1; /*!< [0..0] ECC Error Indicate Flag                                            */
1931             __IM uint32_t  ECER1F  : 1; /*!< [1..1] 1-Bit ECC Error Detection/Correction Flag                          */
1932             __IM uint32_t  ECER2F  : 1; /*!< [2..2] 2-Bit ECC Error Detection Flag                                     */
1933             __IOM uint32_t EC1EDIC : 1; /*!< [3..3] 1-Bit ECC Error Detection Interrupt Control                        */
1934             __IOM uint32_t EC2EDIC : 1; /*!< [4..4] 2-Bit ECC Error Detection Interrupt Control                        */
1935             __IOM uint32_t EC1ECP  : 1; /*!< [5..5] 1-Bit ECC Error Correction Enable                                  */
1936             __IOM uint32_t ECERVF  : 1; /*!< [6..6] ECC Error Determination Enable                                     */
1937             __IOM uint32_t ECTHM   : 1; /*!< [7..7] ECC Function Through Mode Enable                                   */
1938             uint32_t               : 1;
1939             __IOM uint32_t ECER1C  : 1; /*!< [9..9] 1-Bit ECC Error Detection Clear                                    */
1940             __IOM uint32_t ECER2C  : 1; /*!< [10..10] 2-Bit ECC Error Detection Clear                                  */
1941             __IM uint32_t  ECOVFF  : 1; /*!< [11..11] ECC Error Address Capture Overflow Flag                          */
1942             uint32_t               : 2;
1943             __IOM uint32_t EMCA    : 2; /*!< [15..14] Access Control to ECC Mode Selection                             */
1944             __IM uint32_t  ECEDF0  : 2; /*!< [17..16] ECC Error Address Capture Flag m (m = 0)                         */
1945             __IM uint32_t  ECEDF1  : 2; /*!< [19..18] ECC Error Address Capture Flag m (m = 1)                         */
1946             __IM uint32_t  ECEDF2  : 2; /*!< [21..20] ECC Error Address Capture Flag m (m = 2)                         */
1947             __IM uint32_t  ECEDF3  : 2; /*!< [23..22] ECC Error Address Capture Flag m (m = 3)                         */
1948             __IM uint32_t  ECEDF4  : 2; /*!< [25..24] ECC Error Address Capture Flag m (m = 4)                         */
1949             __IM uint32_t  ECEDF5  : 2; /*!< [27..26] ECC Error Address Capture Flag m (m = 5)                         */
1950             __IM uint32_t  ECEDF6  : 2; /*!< [29..28] ECC Error Address Capture Flag m (m = 6)                         */
1951             __IM uint32_t  ECEDF7  : 2; /*!< [31..30] ECC Error Address Capture Flag m (m = 7)                         */
1952         } EC710CTL_b;
1953     };
1954 
1955     union
1956     {
1957         __IOM uint32_t EC710TMC;       /*!< (@ 0x00000004) ECC Test Mode Control Register                             */
1958 
1959         struct
1960         {
1961             __IOM uint32_t ECREIS : 1; /*!< [0..0] ECC Redundancy Bit Input Data Select                               */
1962             __IOM uint32_t ECDCS  : 1; /*!< [1..1] ECC Decode Input Select                                            */
1963             __IOM uint32_t ECENS  : 1; /*!< [2..2] ECC Encode Input Select                                            */
1964             __IOM uint32_t ECREOS : 1; /*!< [3..3] ECC Redundancy Bit Output Data Select                              */
1965             __IOM uint32_t ECTRRS : 1; /*!< [4..4] RAM Read Test Mode Select                                          */
1966             uint32_t              : 2;
1967             __IOM uint32_t ECTMCE : 1; /*!< [7..7] Test Mode Enable                                                   */
1968             uint32_t              : 6;
1969             __IOM uint32_t ETMA   : 2; /*!< [15..14] ECTMCE Write Enable                                              */
1970             uint32_t              : 16;
1971         } EC710TMC_b;
1972     };
1973 
1974     union
1975     {
1976         __IOM uint32_t EC710TRC;       /*!< (@ 0x00000008) ECC Redundancy Bit Data Control Test Register              */
1977 
1978         struct
1979         {
1980             __IOM uint32_t ECERDB : 7; /*!< [6..0] ECC Redundancy Bit Input/Output Substitute Buffer Register         */
1981             uint32_t              : 1;
1982             __IM uint32_t ECECRD  : 7; /*!< [14..8] ECC Encode Test Register                                          */
1983             uint32_t              : 1;
1984             __IM uint32_t ECHORD  : 7; /*!< [22..16] ECC 7-Redundancy-Bit Data Retain Test Register                   */
1985             uint32_t              : 1;
1986             __IM uint32_t ECSYND  : 7; /*!< [30..24] ECC Decode Syndrome Register                                     */
1987             uint32_t              : 1;
1988         } EC710TRC_b;
1989     };
1990 
1991     union
1992     {
1993         __IOM uint32_t EC710TED;       /*!< (@ 0x0000000C) ECC Encode/Decode Input/Output Switchover Test
1994                                         *                  Register                                                   */
1995 
1996         struct
1997         {
1998             __IOM uint32_t ECEDB : 32; /*!< [31..0] 32-Bit Data Test Register for ECC Encode/Decode                   */
1999         } EC710TED_b;
2000     };
2001 
2002     union
2003     {
2004         __IM uint32_t EC710EAD[8];     /*!< (@ 0x00000010) ECC Error Address [0..7] Register 0                        */
2005 
2006         struct
2007         {
2008             __IM uint32_t ECEAD : 15;  /*!< [14..0] Bit Error Address                                                 */
2009             uint32_t            : 17;
2010         } EC710EAD_b[8];
2011     };
2012     __IM uint32_t RESERVED[4];
2013 } R_SYSRAM0_W_Type;                    /*!< Size = 64 (0x40)                                                          */
2014 
2015 /**
2016  * @brief R_MPU0_RGN [RGN] (Master MPU Safety Region Start Address Register [0..7])
2017  */
2018 typedef struct
2019 {
2020     union
2021     {
2022         __IOM uint32_t STADD;           /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register            */
2023 
2024         struct
2025         {
2026             __IOM uint32_t RDPR   : 1;  /*!< [0..0] Enable read protection for region m of master MPU                  */
2027             __IOM uint32_t WRPR   : 1;  /*!< [1..1] Enable write protection for region m of master MPU                 */
2028             uint32_t              : 8;
2029             __IOM uint32_t STADDR : 22; /*!< [31..10] Start address for MPU region                                     */
2030         } STADD_b;
2031     };
2032 
2033     union
2034     {
2035         __IOM uint32_t ENDADD;         /*!< (@ 0x00000004) Master MPU Safety Region End Address Register              */
2036 
2037         struct
2038         {
2039             uint32_t               : 10;
2040             __IOM uint32_t ENDADDR : 22; /*!< [31..10] End address for MPU region                                       */
2041         } ENDADD_b;
2042     };
2043     __IM uint32_t RESERVED[2];
2044 } R_MPU0_RGN_Type;                       /*!< Size = 16 (0x10)                                                          */
2045 
2046 /**
2047  * @brief R_DSMIF0_CH [CH] (Channel Registers [0..2])
2048  */
2049 typedef struct
2050 {
2051     union
2052     {
2053         __IOM uint32_t DSICR;          /*!< (@ 0x00000000) Interrupt Control Register                                 */
2054 
2055         struct
2056         {
2057             __IOM uint32_t IOEL : 1;   /*!< [0..0] Overcurrent lower limit detection interrupt enable                 */
2058             __IOM uint32_t IOEH : 1;   /*!< [1..1] Overcurrent upper limit exceeded output interrupt enable           */
2059             __IOM uint32_t ISE  : 1;   /*!< [2..2] Short circuit detection error interrupt enable                     */
2060             __IOM uint32_t IUE  : 1;   /*!< [3..3] Current data register update interrupt enable                      */
2061             uint32_t            : 28;
2062         } DSICR_b;
2063     };
2064 
2065     union
2066     {
2067         __IOM uint32_t DSCMCCR;        /*!< (@ 0x00000004) Current Measurement Clock Control Register                 */
2068 
2069         struct
2070         {
2071             __IOM uint32_t CKDIR : 1;  /*!< [0..0] A/D conversion clock master/slave switching                        */
2072             uint32_t             : 6;
2073             __IOM uint32_t SEDGE : 1;  /*!< [7..7] Sampling edge selection                                            */
2074             __IOM uint32_t CKDIV : 6;  /*!< [13..8] A/D conversion clock division ratio                               */
2075             uint32_t             : 18;
2076         } DSCMCCR_b;
2077     };
2078 
2079     union
2080     {
2081         __IOM uint32_t DSCMFCR;        /*!< (@ 0x00000008) Current Measurement Filter Control Register                */
2082 
2083         struct
2084         {
2085             __IOM uint32_t CMSINC : 2; /*!< [1..0] Current measurement filter order setting                           */
2086             uint32_t              : 6;
2087             __IOM uint32_t CMDEC  : 8; /*!< [15..8] Decimation ratio selection for current measurement                */
2088             __IOM uint32_t CMSH   : 5; /*!< [20..16] Data shift setting for current measurement                       */
2089             uint32_t              : 11;
2090         } DSCMFCR_b;
2091     };
2092 
2093     union
2094     {
2095         __IOM uint32_t DSCMCTCR;       /*!< (@ 0x0000000C) Current Measurement Capture Trigger Control Register       */
2096 
2097         struct
2098         {
2099             __IOM uint32_t CTSELA : 3; /*!< [2..0] Current capture trigger A selection bit                            */
2100             uint32_t              : 5;
2101             __IOM uint32_t CTSELB : 3; /*!< [10..8] Current capture trigger B selection bit                           */
2102             uint32_t              : 5;
2103             __IOM uint32_t DITSEL : 2; /*!< [17..16] Current measurement filter initialization trigger selection
2104                                         *   bit for frequency division counter for decimation.                        */
2105             uint32_t             : 5;
2106             __IOM uint32_t DEDGE : 1;  /*!< [23..23] Current measurement filter initialization trigger for
2107                                         *   division counter for decimation edge selection bit. The
2108                                         *   trigger from ELC is usually used positive edge. Change
2109                                         *   from the initial value if necessary.                                      */
2110             uint32_t : 8;
2111         } DSCMCTCR_b;
2112     };
2113 
2114     union
2115     {
2116         __IOM uint32_t DSEDCR;         /*!< (@ 0x00000010) Error Detect Control Register                              */
2117 
2118         struct
2119         {
2120             __IOM uint32_t SDE : 1;    /*!< [0..0] Short circuit detection enable bit                                 */
2121             uint32_t           : 31;
2122         } DSEDCR_b;
2123     };
2124 
2125     union
2126     {
2127         __IOM uint32_t DSOCFCR;        /*!< (@ 0x00000014) Overcurrent Detect Filter Control Register                 */
2128 
2129         struct
2130         {
2131             __IOM uint32_t OCSINC : 2; /*!< [1..0] Overcurrent detection filter order setting                         */
2132             uint32_t              : 6;
2133             __IOM uint32_t OCDEC  : 8; /*!< [15..8] Decimation ratio selection for overcurrent detection              */
2134             __IOM uint32_t OCSH   : 5; /*!< [20..16] Data shift setting for overcurrent detection                     */
2135             uint32_t              : 11;
2136         } DSOCFCR_b;
2137     };
2138 
2139     union
2140     {
2141         __IOM uint32_t DSOCLTR;          /*!< (@ 0x00000018) Overcurrent Low Threshold Register                         */
2142 
2143         struct
2144         {
2145             __IOM uint32_t OCMPTBL : 16; /*!< [15..0] Overcurrent detection lower limit                                 */
2146             uint32_t               : 16;
2147         } DSOCLTR_b;
2148     };
2149 
2150     union
2151     {
2152         __IOM uint32_t DSOCHTR;          /*!< (@ 0x0000001C) Overcurrent High Threshold Register                        */
2153 
2154         struct
2155         {
2156             __IOM uint32_t OCMPTBH : 16; /*!< [15..0] Overcurrent detection upper limit                                 */
2157             uint32_t               : 16;
2158         } DSOCHTR_b;
2159     };
2160 
2161     union
2162     {
2163         __IOM uint32_t DSSCTSR;        /*!< (@ 0x00000020) Short Circuit Threshold Setting Register                   */
2164 
2165         struct
2166         {
2167             __IOM uint32_t SCNTL : 13; /*!< [12..0] Short circuit detection low continuous detection count            */
2168             uint32_t             : 3;
2169             __IOM uint32_t SCNTH : 13; /*!< [28..16] Short circuit detection high continuous detection count          */
2170             uint32_t             : 3;
2171         } DSSCTSR_b;
2172     };
2173 
2174     union
2175     {
2176         __IOM uint32_t DSODCR;         /*!< (@ 0x00000024) Overcurrent Detect Control Register                        */
2177 
2178         struct
2179         {
2180             __IOM uint32_t ODEL : 1;   /*!< [0..0] Overcurrent lower limit detection enable bit                       */
2181             __IOM uint32_t ODEH : 1;   /*!< [1..1] Overcurrent upper limit exceeded detection enable bit              */
2182             uint32_t            : 30;
2183         } DSODCR_b;
2184     };
2185     __IM uint32_t RESERVED[6];
2186 
2187     union
2188     {
2189         __IOM uint32_t DSCSTRTR;       /*!< (@ 0x00000040) Software Start Trigger Register                            */
2190 
2191         struct
2192         {
2193             __IOM uint32_t STRTRG : 1; /*!< [0..0] Channel start trigger                                              */
2194             uint32_t              : 31;
2195         } DSCSTRTR_b;
2196     };
2197 
2198     union
2199     {
2200         __IOM uint32_t DSCSTPTR;       /*!< (@ 0x00000044) Software Stop Trigger Register                             */
2201 
2202         struct
2203         {
2204             __IOM uint32_t STPTRG : 1; /*!< [0..0] Channel stop trigger                                               */
2205             uint32_t              : 31;
2206         } DSCSTPTR_b;
2207     };
2208     __IM uint32_t RESERVED1[2];
2209 
2210     union
2211     {
2212         __IM uint32_t DSCDR;           /*!< (@ 0x00000050) Current Data Register                                      */
2213 
2214         struct
2215         {
2216             __IM uint32_t ADDR : 16;   /*!< [15..0] Current data                                                      */
2217             uint32_t           : 16;
2218         } DSCDR_b;
2219     };
2220 
2221     union
2222     {
2223         __IM uint32_t DSCCDRA;         /*!< (@ 0x00000054) Capture Current Data Register A                            */
2224 
2225         struct
2226         {
2227             __IM uint32_t CDRA : 16;   /*!< [15..0] Capture current data A                                            */
2228             uint32_t           : 16;
2229         } DSCCDRA_b;
2230     };
2231 
2232     union
2233     {
2234         __IM uint32_t DSCCDRB;         /*!< (@ 0x00000058) Capture Current Data Register B                            */
2235 
2236         struct
2237         {
2238             __IM uint32_t CDRB : 16;   /*!< [15..0] Capture current data B                                            */
2239             uint32_t           : 16;
2240         } DSCCDRB_b;
2241     };
2242 
2243     union
2244     {
2245         __IM uint32_t DSOCDR;          /*!< (@ 0x0000005C) Overcurrent Data Register                                  */
2246 
2247         struct
2248         {
2249             __IM uint32_t ODR : 16;    /*!< [15..0] Overcurrent data                                                  */
2250             uint32_t          : 16;
2251         } DSOCDR_b;
2252     };
2253 
2254     union
2255     {
2256         __IM uint32_t DSCOCDR;         /*!< (@ 0x00000060) Capture Overcurrent Data Register                          */
2257 
2258         struct
2259         {
2260             __IM uint32_t CODR : 16;   /*!< [15..0] Capture Overcurrent data when overcurrent detected                */
2261             uint32_t           : 16;
2262         } DSCOCDR_b;
2263     };
2264     __IM uint32_t RESERVED2[7];
2265 
2266     union
2267     {
2268         __IM uint32_t DSCSR;           /*!< (@ 0x00000080) Status Register                                            */
2269 
2270         struct
2271         {
2272             __IM uint32_t DUF     : 1; /*!< [0..0] Channel n data update flag                                         */
2273             __IM uint32_t OCFL    : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag                   */
2274             __IM uint32_t OCFH    : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag                    */
2275             __IM uint32_t SCF     : 1; /*!< [3..3] Channel n short circuit detection flag                             */
2276             uint32_t              : 12;
2277             __IM uint32_t CHSTATE : 1; /*!< [16..16] Channel n state                                                  */
2278             uint32_t              : 15;
2279         } DSCSR_b;
2280     };
2281 
2282     union
2283     {
2284         __IOM uint32_t DSCSCR;          /*!< (@ 0x00000084) Status Clear Register                                      */
2285 
2286         struct
2287         {
2288             __IOM uint32_t CLRDUF  : 1; /*!< [0..0] Channel n data update flag clear                                   */
2289             __IOM uint32_t CLROCFL : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag clear             */
2290             __IOM uint32_t CLROCFH : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag clear              */
2291             __IOM uint32_t CLRSCF  : 1; /*!< [3..3] Channel n short circuit detection flag clear                       */
2292             uint32_t               : 28;
2293         } DSCSCR_b;
2294     };
2295     __IM uint32_t RESERVED3[2];
2296 } R_DSMIF0_CH_Type;                    /*!< Size = 144 (0x90)                                                         */
2297 
2298 /** @} */ /* End of group Device_Peripheral_clusters */
2299 
2300 /* =========================================================================================================================== */
2301 /* ================                            Device Specific Peripheral Section                             ================ */
2302 /* =========================================================================================================================== */
2303 
2304 /** @addtogroup Device_Peripheral_peripherals
2305  * @{
2306  */
2307 
2308 /* =========================================================================================================================== */
2309 /* ================                                          R_GPT7                                           ================ */
2310 /* =========================================================================================================================== */
2311 
2312 /**
2313  * @brief General PWM Timer 7 (R_GPT7)
2314  */
2315 
2316 typedef struct                         /*!< (@ 0x80000000) R_GPT7 Structure                                           */
2317 {
2318     union
2319     {
2320         __IOM uint32_t GTWP;           /*!< (@ 0x00000000) General PWM Timer Write-Protection Register                */
2321 
2322         struct
2323         {
2324             __IOM uint32_t WP    : 1;  /*!< [0..0] Register Write Disabled                                            */
2325             __IOM uint32_t STRWP : 1;  /*!< [1..1] GTSTR.CSTRT Bit Write Disabled                                     */
2326             __IOM uint32_t STPWP : 1;  /*!< [2..2] GTSTP.CSTOP Bit Write Disabled                                     */
2327             __IOM uint32_t CLRWP : 1;  /*!< [3..3] GTCLR.CCLR Bit Write Disabled                                      */
2328             __IOM uint32_t CMNWP : 1;  /*!< [4..4] Common Register Write Disabled                                     */
2329             uint32_t             : 3;
2330             __OM uint32_t PRKEY  : 8;  /*!< [15..8] GTWP Key Code                                                     */
2331             uint32_t             : 16;
2332         } GTWP_b;
2333     };
2334 
2335     union
2336     {
2337         __IOM uint32_t GTSTR;          /*!< (@ 0x00000004) General PWM Timer Software Start Register                  */
2338 
2339         struct
2340         {
2341             __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel 0 Count Start                                              */
2342             __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel 1 Count Start                                              */
2343             __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel 2 Count Start                                              */
2344             __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel 3 Count Start                                              */
2345             __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel 4 Count Start                                              */
2346             __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel 5 Count Start                                              */
2347             __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel 6 Count Start                                              */
2348             uint32_t              : 25;
2349         } GTSTR_b;
2350     };
2351 
2352     union
2353     {
2354         __IOM uint32_t GTSTP;          /*!< (@ 0x00000008) General PWM Timer Software Stop Register                   */
2355 
2356         struct
2357         {
2358             __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel 0 Count Stop                                               */
2359             __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel 1 Count Stop                                               */
2360             __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel 2 Count Stop                                               */
2361             __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel 3 Count Stop                                               */
2362             __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel 4 Count Stop                                               */
2363             __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel 5 Count Stop                                               */
2364             __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel 6 Count Stop                                               */
2365             uint32_t              : 25;
2366         } GTSTP_b;
2367     };
2368 
2369     union
2370     {
2371         __OM uint32_t GTCLR;           /*!< (@ 0x0000000C) General PWM Timer Software Clear Register                  */
2372 
2373         struct
2374         {
2375             __OM uint32_t CCLR0 : 1;   /*!< [0..0] Channel 0 Count Clear                                              */
2376             __OM uint32_t CCLR1 : 1;   /*!< [1..1] Channel 1 Count Clear                                              */
2377             __OM uint32_t CCLR2 : 1;   /*!< [2..2] Channel 2 Count Clear                                              */
2378             __OM uint32_t CCLR3 : 1;   /*!< [3..3] Channel 3 Count Clear                                              */
2379             __OM uint32_t CCLR4 : 1;   /*!< [4..4] Channel 4 Count Clear                                              */
2380             __OM uint32_t CCLR5 : 1;   /*!< [5..5] Channel 5 Count Clear                                              */
2381             __OM uint32_t CCLR6 : 1;   /*!< [6..6] Channel 6 Count Clear                                              */
2382             uint32_t            : 25;
2383         } GTCLR_b;
2384     };
2385 
2386     union
2387     {
2388         __IOM uint32_t GTSSR;             /*!< (@ 0x00000010) General PWM Timer Start Source Select Register             */
2389 
2390         struct
2391         {
2392             __IOM uint32_t SSGTRGAFR : 2; /*!< [1..0] SSGTRGAFR                                                          */
2393             __IOM uint32_t SSGTRGBFR : 2; /*!< [3..2] SSGTRGBFR                                                          */
2394             __IOM uint32_t SSGTRGCFR : 2; /*!< [5..4] SSGTRGCFR                                                          */
2395             __IOM uint32_t SSGTRGDFR : 2; /*!< [7..6] SSGTRGDFR                                                          */
2396             __IOM uint32_t SSCARBHL  : 2; /*!< [9..8] SSCARBHL                                                           */
2397             __IOM uint32_t SSCAFBHL  : 2; /*!< [11..10] SSCAFBHL                                                         */
2398             __IOM uint32_t SSCBRAHL  : 2; /*!< [13..12] SSCBRAHL                                                         */
2399             __IOM uint32_t SSCBFAHL  : 2; /*!< [15..14] SSCBFAHL                                                         */
2400             __IOM uint32_t SSELCA    : 1; /*!< [16..16] SSELCA                                                           */
2401             __IOM uint32_t SSELCB    : 1; /*!< [17..17] SSELCB                                                           */
2402             __IOM uint32_t SSELCC    : 1; /*!< [18..18] SSELCC                                                           */
2403             __IOM uint32_t SSELCD    : 1; /*!< [19..19] SSELCD                                                           */
2404             __IOM uint32_t SSELCE    : 1; /*!< [20..20] SSELCE                                                           */
2405             __IOM uint32_t SSELCF    : 1; /*!< [21..21] SSELCF                                                           */
2406             __IOM uint32_t SSELCG    : 1; /*!< [22..22] SSELCG                                                           */
2407             __IOM uint32_t SSELCH    : 1; /*!< [23..23] SSELCH                                                           */
2408             uint32_t                 : 7;
2409             __IOM uint32_t CSTRT     : 1; /*!< [31..31] Software Source Count Start Enable                               */
2410         } GTSSR_b;
2411     };
2412 
2413     union
2414     {
2415         __IOM uint32_t GTPSR;             /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register              */
2416 
2417         struct
2418         {
2419             __IOM uint32_t PSGTRGAFR : 2; /*!< [1..0] PSGTRGAFR                                                          */
2420             __IOM uint32_t PSGTRGBFR : 2; /*!< [3..2] PSGTRGBFR                                                          */
2421             __IOM uint32_t PSGTRGCFR : 2; /*!< [5..4] PSGTRGCFR                                                          */
2422             __IOM uint32_t PSGTRGDFR : 2; /*!< [7..6] PSGTRGDFR                                                          */
2423             __IOM uint32_t PSCARBHL  : 2; /*!< [9..8] PSCARBHL                                                           */
2424             __IOM uint32_t PSCAFBHL  : 2; /*!< [11..10] PSCAFBHL                                                         */
2425             __IOM uint32_t PSCBRAHL  : 2; /*!< [13..12] PSCBRAHL                                                         */
2426             __IOM uint32_t PSCBFAHL  : 2; /*!< [15..14] PSCBFAHL                                                         */
2427             __IOM uint32_t PSELCA    : 1; /*!< [16..16] PSELCA                                                           */
2428             __IOM uint32_t PSELCB    : 1; /*!< [17..17] PSELCB                                                           */
2429             __IOM uint32_t PSELCC    : 1; /*!< [18..18] PSELCC                                                           */
2430             __IOM uint32_t PSELCD    : 1; /*!< [19..19] PSELCD                                                           */
2431             __IOM uint32_t PSELCE    : 1; /*!< [20..20] PSELCE                                                           */
2432             __IOM uint32_t PSELCF    : 1; /*!< [21..21] PSELCF                                                           */
2433             __IOM uint32_t PSELCG    : 1; /*!< [22..22] PSELCG                                                           */
2434             __IOM uint32_t PSELCH    : 1; /*!< [23..23] PSELCH                                                           */
2435             uint32_t                 : 7;
2436             __IOM uint32_t CSTOP     : 1; /*!< [31..31] CSTOP                                                            */
2437         } GTPSR_b;
2438     };
2439 
2440     union
2441     {
2442         __IOM uint32_t GTCSR;             /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register             */
2443 
2444         struct
2445         {
2446             __IOM uint32_t CSGTRGAFR : 2; /*!< [1..0] CSGTRGAFR                                                          */
2447             __IOM uint32_t CSGTRGBFR : 2; /*!< [3..2] CSGTRGBFR                                                          */
2448             __IOM uint32_t CSGTRGCFR : 2; /*!< [5..4] CSGTRGCFR                                                          */
2449             __IOM uint32_t CSGTRGDFR : 2; /*!< [7..6] CSGTRGDFR                                                          */
2450             __IOM uint32_t CSCARBHL  : 2; /*!< [9..8] CSCARBHL                                                           */
2451             __IOM uint32_t CSCAFBHL  : 2; /*!< [11..10] CSCAFBHL                                                         */
2452             __IOM uint32_t CSCBRAHL  : 2; /*!< [13..12] CSCBRAHL                                                         */
2453             __IOM uint32_t CSCBFAHL  : 2; /*!< [15..14] CSCBFAHL                                                         */
2454             __IOM uint32_t CSELCA    : 1; /*!< [16..16] CSELCA                                                           */
2455             __IOM uint32_t CSELCB    : 1; /*!< [17..17] CSELCB                                                           */
2456             __IOM uint32_t CSELCC    : 1; /*!< [18..18] CSELCC                                                           */
2457             __IOM uint32_t CSELCD    : 1; /*!< [19..19] CSELCD                                                           */
2458             __IOM uint32_t CSELCE    : 1; /*!< [20..20] CSELCE                                                           */
2459             __IOM uint32_t CSELCF    : 1; /*!< [21..21] CSELCF                                                           */
2460             __IOM uint32_t CSELCG    : 1; /*!< [22..22] CSELCG                                                           */
2461             __IOM uint32_t CSELCH    : 1; /*!< [23..23] CSELCH                                                           */
2462             uint32_t                 : 7;
2463             __IOM uint32_t CCLR      : 1; /*!< [31..31] CCLR                                                             */
2464         } GTCSR_b;
2465     };
2466 
2467     union
2468     {
2469         __IOM uint32_t GTUPSR;            /*!< (@ 0x0000001C) General PWM Timer Count-Up Source Select Register          */
2470 
2471         struct
2472         {
2473             __IOM uint32_t USGTRGAFR : 2; /*!< [1..0] USGTRGAFR                                                          */
2474             __IOM uint32_t USGTRGBFR : 2; /*!< [3..2] USGTRGBFR                                                          */
2475             __IOM uint32_t USGTRGCFR : 2; /*!< [5..4] USGTRGCFR                                                          */
2476             __IOM uint32_t USGTRGDFR : 2; /*!< [7..6] USGTRGDFR                                                          */
2477             __IOM uint32_t USCARBHL  : 2; /*!< [9..8] USCARBHL                                                           */
2478             __IOM uint32_t USCAFBHL  : 2; /*!< [11..10] USCAFBHL                                                         */
2479             __IOM uint32_t USCBRAHL  : 2; /*!< [13..12] USCBRAHL                                                         */
2480             __IOM uint32_t USCBFAHL  : 2; /*!< [15..14] USCBFAHL                                                         */
2481             __IOM uint32_t USELCA    : 1; /*!< [16..16] USELCA                                                           */
2482             __IOM uint32_t USELCB    : 1; /*!< [17..17] USELCB                                                           */
2483             __IOM uint32_t USELCC    : 1; /*!< [18..18] USELCC                                                           */
2484             __IOM uint32_t USELCD    : 1; /*!< [19..19] USELCD                                                           */
2485             __IOM uint32_t USELCE    : 1; /*!< [20..20] USELCE                                                           */
2486             __IOM uint32_t USELCF    : 1; /*!< [21..21] USELCF                                                           */
2487             __IOM uint32_t USELCG    : 1; /*!< [22..22] USELCG                                                           */
2488             __IOM uint32_t USELCH    : 1; /*!< [23..23] USELCH                                                           */
2489             uint32_t                 : 8;
2490         } GTUPSR_b;
2491     };
2492 
2493     union
2494     {
2495         __IOM uint32_t GTDNSR;            /*!< (@ 0x00000020) General PWM Timer Count-Down Source Select Register        */
2496 
2497         struct
2498         {
2499             __IOM uint32_t DSGTRGAFR : 2; /*!< [1..0] DSGTRGAFR                                                          */
2500             __IOM uint32_t DSGTRGBFR : 2; /*!< [3..2] DSGTRGBFR                                                          */
2501             __IOM uint32_t DSGTRGCFR : 2; /*!< [5..4] DSGTRGCFR                                                          */
2502             __IOM uint32_t DSGTRGDFR : 2; /*!< [7..6] DSGTRGDFR                                                          */
2503             __IOM uint32_t DSCARBHL  : 2; /*!< [9..8] DSCARBHL                                                           */
2504             __IOM uint32_t DSCAFBHL  : 2; /*!< [11..10] DSCAFBHL                                                         */
2505             __IOM uint32_t DSCBRAHL  : 2; /*!< [13..12] DSCBRAHL                                                         */
2506             __IOM uint32_t DSCBFAHL  : 2; /*!< [15..14] DSCBFAHL                                                         */
2507             __IOM uint32_t DSELCA    : 1; /*!< [16..16] DSELCA                                                           */
2508             __IOM uint32_t DSELCB    : 1; /*!< [17..17] DSELCB                                                           */
2509             __IOM uint32_t DSELCC    : 1; /*!< [18..18] DSELCC                                                           */
2510             __IOM uint32_t DSELCD    : 1; /*!< [19..19] DSELCD                                                           */
2511             __IOM uint32_t DSELCE    : 1; /*!< [20..20] DSELCE                                                           */
2512             __IOM uint32_t DSELCF    : 1; /*!< [21..21] DSELCF                                                           */
2513             __IOM uint32_t DSELCG    : 1; /*!< [22..22] DSELCG                                                           */
2514             __IOM uint32_t DSELCH    : 1; /*!< [23..23] DSELCH                                                           */
2515             uint32_t                 : 8;
2516         } GTDNSR_b;
2517     };
2518 
2519     union
2520     {
2521         __IOM uint32_t GTICASR;           /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select
2522                                            *                  Register A                                                 */
2523 
2524         struct
2525         {
2526             __IOM uint32_t ASGTRGAFR : 2; /*!< [1..0] ASGTRGAFR                                                          */
2527             __IOM uint32_t ASGTRGBFR : 2; /*!< [3..2] ASGTRGBFR                                                          */
2528             __IOM uint32_t ASGTRGCFR : 2; /*!< [5..4] ASGTRGCFR                                                          */
2529             __IOM uint32_t ASGTRGDFR : 2; /*!< [7..6] ASGTRGDFR                                                          */
2530             __IOM uint32_t ASCARBHL  : 2; /*!< [9..8] ASCARBHL                                                           */
2531             __IOM uint32_t ASCAFBHL  : 2; /*!< [11..10] ASCAFBHL                                                         */
2532             __IOM uint32_t ASCBRAHL  : 2; /*!< [13..12] ASCBRAHL                                                         */
2533             __IOM uint32_t ASCBFAHL  : 2; /*!< [15..14] ASCBFAHL                                                         */
2534             __IOM uint32_t ASELCA    : 1; /*!< [16..16] ASELCA                                                           */
2535             __IOM uint32_t ASELCB    : 1; /*!< [17..17] ASELCB                                                           */
2536             __IOM uint32_t ASELCC    : 1; /*!< [18..18] ASELCC                                                           */
2537             __IOM uint32_t ASELCD    : 1; /*!< [19..19] ASELCD                                                           */
2538             __IOM uint32_t ASELCE    : 1; /*!< [20..20] ASELCE                                                           */
2539             __IOM uint32_t ASELCF    : 1; /*!< [21..21] ASELCF                                                           */
2540             __IOM uint32_t ASELCG    : 1; /*!< [22..22] ASELCG                                                           */
2541             __IOM uint32_t ASELCH    : 1; /*!< [23..23] ASELCH                                                           */
2542             uint32_t                 : 8;
2543         } GTICASR_b;
2544     };
2545 
2546     union
2547     {
2548         __IOM uint32_t GTICBSR;           /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select
2549                                            *                  Register B                                                 */
2550 
2551         struct
2552         {
2553             __IOM uint32_t BSGTRGAFR : 2; /*!< [1..0] BSGTRGAFR                                                          */
2554             __IOM uint32_t BSGTRGBFR : 2; /*!< [3..2] BSGTRGBFR                                                          */
2555             __IOM uint32_t BSGTRGCFR : 2; /*!< [5..4] BSGTRGCFR                                                          */
2556             __IOM uint32_t BSGTRGDFR : 2; /*!< [7..6] BSGTRGDFR                                                          */
2557             __IOM uint32_t BSCARBHL  : 2; /*!< [9..8] BSCARBHL                                                           */
2558             __IOM uint32_t BSCAFBHL  : 2; /*!< [11..10] BSCAFBHL                                                         */
2559             __IOM uint32_t BSCBRAHL  : 2; /*!< [13..12] BSCBRAHL                                                         */
2560             __IOM uint32_t BSCBFAHL  : 2; /*!< [15..14] BSCBFAHL                                                         */
2561             __IOM uint32_t BSELCA    : 1; /*!< [16..16] BSELCA                                                           */
2562             __IOM uint32_t BSELCB    : 1; /*!< [17..17] BSELCB                                                           */
2563             __IOM uint32_t BSELCC    : 1; /*!< [18..18] BSELCC                                                           */
2564             __IOM uint32_t BSELCD    : 1; /*!< [19..19] BSELCD                                                           */
2565             __IOM uint32_t BSELCE    : 1; /*!< [20..20] BSELCE                                                           */
2566             __IOM uint32_t BSELCF    : 1; /*!< [21..21] BSELCF                                                           */
2567             __IOM uint32_t BSELCG    : 1; /*!< [22..22] BSELCG                                                           */
2568             __IOM uint32_t BSELCH    : 1; /*!< [23..23] BSELCH                                                           */
2569             uint32_t                 : 8;
2570         } GTICBSR_b;
2571     };
2572 
2573     union
2574     {
2575         __IOM uint32_t GTCR;           /*!< (@ 0x0000002C) General PWM Timer Control Register                         */
2576 
2577         struct
2578         {
2579             __IOM uint32_t CST  : 1;   /*!< [0..0] Count Start                                                        */
2580             uint32_t            : 7;
2581             __IOM uint32_t ICDS : 1;   /*!< [8..8] Input Capture Operation Select at Count Stop                       */
2582             uint32_t            : 7;
2583             __IOM uint32_t MD   : 3;   /*!< [18..16] Mode Select                                                      */
2584             uint32_t            : 4;
2585             __IOM uint32_t TPCS : 4;   /*!< [26..23] Timer Prescaler Select                                           */
2586             uint32_t            : 2;
2587             __IOM uint32_t SWMD : 3;   /*!< [31..29] Switch Mode Select                                               */
2588         } GTCR_b;
2589     };
2590 
2591     union
2592     {
2593         __IOM uint32_t GTUDDTYC;       /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting
2594                                         *                  Register                                                   */
2595 
2596         struct
2597         {
2598             __IOM uint32_t UD     : 1; /*!< [0..0] Count Direction Setting                                            */
2599             __IOM uint32_t UDF    : 1; /*!< [1..1] Forcible Count Direction Setting                                   */
2600             uint32_t              : 14;
2601             __IOM uint32_t OADTY  : 2; /*!< [17..16] GTIOCnA Pin Output Duty Setting                                  */
2602             __IOM uint32_t OADTYF : 1; /*!< [18..18] GTIOCnA Pin Output Duty Forced Setting                           */
2603             __IOM uint32_t OADTYR : 1; /*!< [19..19] Output after Release of GTIOCnA Pin Output 0%/100%
2604                                         *   Duty Cycle Settings                                                       */
2605             uint32_t              : 4;
2606             __IOM uint32_t OBDTY  : 2; /*!< [25..24] GTIOCnB Pin Output Duty Setting                                  */
2607             __IOM uint32_t OBDTYF : 1; /*!< [26..26] GTIOCnB Pin Output Duty Forced Setting                           */
2608             __IOM uint32_t OBDTYR : 1; /*!< [27..27] Output after Release of GTIOCnB Pin Output 0%/100%
2609                                         *   Duty Cycle Settings                                                       */
2610             uint32_t : 4;
2611         } GTUDDTYC_b;
2612     };
2613 
2614     union
2615     {
2616         __IOM uint32_t GTIOR;          /*!< (@ 0x00000034) General PWM Timer I/O Control Register                     */
2617 
2618         struct
2619         {
2620             __IOM uint32_t GTIOA  : 5; /*!< [4..0] GTIOCnA Pin Function Select                                        */
2621             uint32_t              : 1;
2622             __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCnA Pin Output Value Setting at the Count Stop                 */
2623             __IOM uint32_t OAHLD  : 1; /*!< [7..7] GTIOCnA Pin Output Retention at the Start/Stop Count               */
2624             __IOM uint32_t OAE    : 1; /*!< [8..8] GTIOCnA Pin Output Enable                                          */
2625             __IOM uint32_t OADF   : 2; /*!< [10..9] GTIOCnA Pin Negate Value Setting                                  */
2626             uint32_t              : 2;
2627             __IOM uint32_t NFAEN  : 1; /*!< [13..13] GTIOCnA Pin Input Noise Filter Enable                            */
2628             __IOM uint32_t NFCSA  : 2; /*!< [15..14] GTIOCnA Pin Input Noise Filter Sampling Clock Select             */
2629             __IOM uint32_t GTIOB  : 5; /*!< [20..16] GTIOCnB Pin Function Select                                      */
2630             uint32_t              : 1;
2631             __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCnB Pin Output Value Setting at the Count Stop               */
2632             __IOM uint32_t OBHLD  : 1; /*!< [23..23] GTIOCnB Pin Output Retention at the Start/Stop Count             */
2633             __IOM uint32_t OBE    : 1; /*!< [24..24] GTIOCnB Pin Output Enable                                        */
2634             __IOM uint32_t OBDF   : 2; /*!< [26..25] GTIOCnB Pin Negate Value Setting                                 */
2635             uint32_t              : 2;
2636             __IOM uint32_t NFBEN  : 1; /*!< [29..29] GTIOCnB Pin Input Noise Filter Enable                            */
2637             __IOM uint32_t NFCSB  : 2; /*!< [31..30] GTIOCnB Pin Input Noise Filter Sampling Clock Select             */
2638         } GTIOR_b;
2639     };
2640 
2641     union
2642     {
2643         __IOM uint32_t GTINTAD;          /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register        */
2644 
2645         struct
2646         {
2647             __IOM uint32_t GTINTA   : 1; /*!< [0..0] GTINTA                                                             */
2648             __IOM uint32_t GTINTB   : 1; /*!< [1..1] GTINTB                                                             */
2649             __IOM uint32_t GTINTC   : 1; /*!< [2..2] GTINTC                                                             */
2650             __IOM uint32_t GTINTD   : 1; /*!< [3..3] GTINTD                                                             */
2651             __IOM uint32_t GTINTE   : 1; /*!< [4..4] GTINTE                                                             */
2652             __IOM uint32_t GTINTF   : 1; /*!< [5..5] GTINTF                                                             */
2653             __IOM uint32_t GTINTPR  : 2; /*!< [7..6] GTINTPR                                                            */
2654             uint32_t                : 8;
2655             __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] ADTRAUEN                                                         */
2656             __IOM uint32_t ADTRADEN : 1; /*!< [17..17] ADTRADEN                                                         */
2657             __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] ADTRBUEN                                                         */
2658             __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] ADTRBDEN                                                         */
2659             uint32_t                : 4;
2660             __IOM uint32_t GRP      : 2; /*!< [25..24] Select the group to detect disabling of output (dead-time
2661                                           *   error or simultaneous driving of outputs to the high or
2662                                           *   low level) to POEG and to request of disabling of output
2663                                           *   from POEG.                                                                */
2664             uint32_t              : 2;
2665             __IOM uint32_t GRPDTE : 1;   /*!< [28..28] GRPDTE                                                           */
2666             __IOM uint32_t GRPABH : 1;   /*!< [29..29] (GTIOCnA pin and GTIOCnB output)                                 */
2667             __IOM uint32_t GRPABL : 1;   /*!< [30..30] (GTIOCnA pin and GTIOCnB output)                                 */
2668             uint32_t              : 1;
2669         } GTINTAD_b;
2670     };
2671 
2672     union
2673     {
2674         __IOM uint32_t GTST;           /*!< (@ 0x0000003C) General PWM Timer Status Register                          */
2675 
2676         struct
2677         {
2678             uint32_t               : 8;
2679             __IM uint32_t ITCNT    : 3; /*!< [10..8] GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter                */
2680             uint32_t               : 4;
2681             __IM uint32_t  TUCF    : 1; /*!< [15..15] Count Direction Flag                                             */
2682             __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Register Compare Match (Up-Counting) A/D Converter
2683                                          *   Start Request Flag                                                        */
2684             __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Register Compare Match (Down-Counting) A/D
2685                                          *   Converter Start Request Flag                                              */
2686             __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Register Compare Match (Up-Counting) A/D Converter
2687                                          *   Start Request Flag                                                        */
2688             __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Register Compare Match (Down-Counting) A/D
2689                                          *   Converter Start Request Flag                                              */
2690             uint32_t            : 4;
2691             __IM uint32_t ODF   : 1;    /*!< [24..24] Output Stop Request Flag                                         */
2692             uint32_t            : 3;
2693             __IM uint32_t DTEF  : 1;    /*!< [28..28] Dead Time Error Flag                                             */
2694             __IM uint32_t OABHF : 1;    /*!< [29..29] Simultaneous High Output Flag                                    */
2695             __IM uint32_t OABLF : 1;    /*!< [30..30] Simultaneous Low Output Flag                                     */
2696             uint32_t            : 1;
2697         } GTST_b;
2698     };
2699 
2700     union
2701     {
2702         __IOM uint32_t GTBER;           /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register                   */
2703 
2704         struct
2705         {
2706             __IOM uint32_t BD0     : 1; /*!< [0..0] GTCCRA/GTCCRB Registers Buffer Operation Disable                   */
2707             __IOM uint32_t BD1     : 1; /*!< [1..1] GTPR Register Buffer Operation Disable                             */
2708             __IOM uint32_t BD2     : 1; /*!< [2..2] GTADTRA/GTADTRB Registers Buffer Operation Disable                 */
2709             __IOM uint32_t BD3     : 1; /*!< [3..3] GTDVU/GTDVD Registers Buffer Operation Disable                     */
2710             uint32_t               : 4;
2711             __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRA Register Double Buffer Repeat Operation Enable              */
2712             uint32_t               : 1;
2713             __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRB Register Double Buffer Repeat Operation Enable            */
2714             uint32_t               : 5;
2715             __IOM uint32_t CCRA    : 2; /*!< [17..16] GTCCRA Register Buffer Operation                                 */
2716             __IOM uint32_t CCRB    : 2; /*!< [19..18] GTCCRB Register Buffer Operation                                 */
2717             __IOM uint32_t PR      : 2; /*!< [21..20] GTPR Register Buffer Operation                                   */
2718             __IOM uint32_t CCRSWT  : 1; /*!< [22..22] GTCCRA and GTCCRB Registers Forcible Buffer Operation            */
2719             uint32_t               : 1;
2720             __IOM uint32_t ADTTA   : 2; /*!< [25..24] GTADTRA Register Buffer Transfer Timing Select                   */
2721             __IOM uint32_t ADTDA   : 1; /*!< [26..26] GTADTRA Register Double Buffer Operation                         */
2722             uint32_t               : 1;
2723             __IOM uint32_t ADTTB   : 2; /*!< [29..28] GTADTRB Register Buffer Transfer Timing Select                   */
2724             __IOM uint32_t ADTDB   : 1; /*!< [30..30] GTADTRB Register Double Buffer Operation                         */
2725             uint32_t               : 1;
2726         } GTBER_b;
2727     };
2728 
2729     union
2730     {
2731         __IOM uint32_t GTITC;          /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter
2732                                         *                  Start Request Skipping Setting Register                    */
2733 
2734         struct
2735         {
2736             __IOM uint32_t ITLA  : 1;  /*!< [0..0] ITLA                                                               */
2737             __IOM uint32_t ITLB  : 1;  /*!< [1..1] ITLB                                                               */
2738             __IOM uint32_t ITLC  : 1;  /*!< [2..2] ITLC                                                               */
2739             __IOM uint32_t ITLD  : 1;  /*!< [3..3] ITLD                                                               */
2740             __IOM uint32_t ITLE  : 1;  /*!< [4..4] ITLE                                                               */
2741             __IOM uint32_t ITLF  : 1;  /*!< [5..5] ITLF                                                               */
2742             __IOM uint32_t IVTC  : 2;  /*!< [7..6] IVTC                                                               */
2743             __IOM uint32_t IVTT  : 3;  /*!< [10..8] IVTT                                                              */
2744             uint32_t             : 1;
2745             __IOM uint32_t ADTAL : 1;  /*!< [12..12] ADTAL                                                            */
2746             uint32_t             : 1;
2747             __IOM uint32_t ADTBL : 1;  /*!< [14..14] ADTBL                                                            */
2748             uint32_t             : 17;
2749         } GTITC_b;
2750     };
2751     __IOM uint32_t GTCNT;              /*!< (@ 0x00000048) General PWM Timer Counter                                  */
2752     __IOM uint32_t GTCCR[6];           /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register m
2753                                         *                  (m = A to F)                                               */
2754     __IOM uint32_t GTPR;               /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register                   */
2755     __IOM uint32_t GTPBR;              /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register            */
2756     __IOM uint32_t GTPDBR;             /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer
2757                                         *                  Register                                                   */
2758     __IOM uint32_t GTADTRA;            /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A
2759                                         *                  (m = A, B)                                                 */
2760     __IOM uint32_t GTADTBRA;           /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register
2761                                         *                  A (m = A, B)                                               */
2762     __IOM uint32_t GTADTDBRA;          /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer
2763                                         *                  Register A                                                 */
2764     __IOM uint32_t GTADTRB;            /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B
2765                                         *                  (m = A, B)                                                 */
2766     __IOM uint32_t GTADTBRB;           /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register
2767                                         *                  B (m = A, B)                                               */
2768     __IOM uint32_t GTADTDBRB;          /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer
2769                                         *                  Register B                                                 */
2770 
2771     union
2772     {
2773         __IOM uint32_t GTDTCR;         /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register               */
2774 
2775         struct
2776         {
2777             __IOM uint32_t TDE   : 1;  /*!< [0..0] Negative-Phase Waveform Setting                                    */
2778             uint32_t             : 3;
2779             __IOM uint32_t TDBUE : 1;  /*!< [4..4] GTDVU Register Buffer Operation Enable                             */
2780             __IOM uint32_t TDBDE : 1;  /*!< [5..5] GTDVD Register Buffer Operation Enable                             */
2781             uint32_t             : 2;
2782             __IOM uint32_t TDFER : 1;  /*!< [8..8] GTDVD Register Setting                                             */
2783             uint32_t             : 23;
2784         } GTDTCR_b;
2785     };
2786     __IOM uint32_t GTDVU;              /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U
2787                                         *                  (m = U, D)                                                 */
2788     __IOM uint32_t GTDVD;              /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D
2789                                         *                  (m = U, D)                                                 */
2790     __IOM uint32_t GTDBU;              /*!< (@ 0x00000094) General PWM Timer Dead Time Value Buffer Register
2791                                         *                  U (m = U, D)                                               */
2792     __IOM uint32_t GTDBD;              /*!< (@ 0x00000098) General PWM Timer Dead Time Value Buffer Register
2793                                         *                  D (m = U, D)                                               */
2794 
2795     union
2796     {
2797         __IM uint32_t GTSOS;           /*!< (@ 0x0000009C) General PWM Timer Output Protection Function
2798                                         *                  Status Register                                            */
2799 
2800         struct
2801         {
2802             __IM uint32_t SOS : 2;     /*!< [1..0] Output Protection Function Status                                  */
2803             uint32_t          : 30;
2804         } GTSOS_b;
2805     };
2806 
2807     union
2808     {
2809         __IOM uint32_t GTSOTR;         /*!< (@ 0x000000A0) General PWM Timer Output Protection Function
2810                                         *                  Temporary Release Register                                 */
2811 
2812         struct
2813         {
2814             __IOM uint32_t SOTR : 1;   /*!< [0..0] Output Protection Function Temporary Release                       */
2815             uint32_t            : 31;
2816         } GTSOTR_b;
2817     };
2818 
2819     union
2820     {
2821         __IOM uint32_t GTADSMR;         /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request
2822                                          *                  Signal Monitoring Register                                 */
2823 
2824         struct
2825         {
2826             __IOM uint32_t ADSMS0  : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection            */
2827             uint32_t               : 6;
2828             __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output
2829                                          *   Enabling                                                                  */
2830             uint32_t               : 7;
2831             __IOM uint32_t ADSMS1  : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection          */
2832             uint32_t               : 6;
2833             __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output
2834                                          *   Enabling                                                                  */
2835             uint32_t : 7;
2836         } GTADSMR_b;
2837     };
2838 
2839     union
2840     {
2841         __IOM uint32_t GTEITC;            /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping
2842                                            *                  Counter Control Register                                   */
2843 
2844         struct
2845         {
2846             __IOM uint32_t EIVTC1  : 2;   /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select          */
2847             uint32_t               : 2;
2848             __IOM uint32_t EIVTT1  : 4;   /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting               */
2849             uint32_t               : 4;
2850             __IM uint32_t  EITCNT1 : 4;   /*!< [15..12] Extended Interrupt Skipping Counter 1                            */
2851             __IOM uint32_t EIVTC2  : 2;   /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source
2852                                            *   Select                                                                    */
2853             uint32_t                 : 2;
2854             __IOM uint32_t EIVTT2    : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting             */
2855             __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value              */
2856             __IM uint32_t  EITCNT2   : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2                            */
2857         } GTEITC_b;
2858     };
2859 
2860     union
2861     {
2862         __IOM uint32_t GTEITLI1;       /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping
2863                                         *                  Setting Register 1                                         */
2864 
2865         struct
2866         {
2867             __IOM uint32_t EITLA : 3;  /*!< [2..0] GTCCRA Register Compare Match / Input Capture Interrupt
2868                                         *   Extended Skipping Function Select                                         */
2869             uint32_t             : 1;
2870             __IOM uint32_t EITLB : 3;  /*!< [6..4] GTCCRB Register Compare Match / Input Capture Interrupt
2871                                         *   Extended Skipping Function Select                                         */
2872             uint32_t             : 1;
2873             __IOM uint32_t EITLC : 3;  /*!< [10..8] GTCCRC Register Compare Match / Input Capture Interrupt
2874                                         *   Extended Skipping Function Select                                         */
2875             uint32_t             : 1;
2876             __IOM uint32_t EITLD : 3;  /*!< [14..12] GTCCRD Register Compare Match / Input Capture Interrupt
2877                                         *   Extended Skipping Function Select                                         */
2878             uint32_t             : 1;
2879             __IOM uint32_t EITLE : 3;  /*!< [18..16] GTCCRE Register Compare Match / Input Capture Interrupt
2880                                         *   Extended Skipping Function Select                                         */
2881             uint32_t             : 1;
2882             __IOM uint32_t EITLF : 3;  /*!< [22..20] GTCCRF Register Compare Match / Input Capture Interrupt
2883                                         *   Extended Skipping Function Select                                         */
2884             uint32_t             : 1;
2885             __IOM uint32_t EITLV : 3;  /*!< [26..24] Overflow Interrupt Extended Skipping Function Select             */
2886             uint32_t             : 1;
2887             __IOM uint32_t EITLU : 3;  /*!< [30..28] Underflow Interrupt Extended Skipping Function Select            */
2888             uint32_t             : 1;
2889         } GTEITLI1_b;
2890     };
2891 
2892     union
2893     {
2894         __IOM uint32_t GTEITLI2;       /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping
2895                                         *                  Setting Register 2                                         */
2896 
2897         struct
2898         {
2899             __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA A/D Converter Start Request Extended Skipping
2900                                         *   Function Select                                                           */
2901             uint32_t              : 1;
2902             __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB A/D Converter Start Request Extended Skipping
2903                                         *   Function Select                                                           */
2904             uint32_t : 25;
2905         } GTEITLI2_b;
2906     };
2907 
2908     union
2909     {
2910         __IOM uint32_t GTEITLB;         /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping
2911                                          *                  Setting Register                                           */
2912 
2913         struct
2914         {
2915             __IOM uint32_t EBTLCA : 3;  /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function
2916                                          *   Select                                                                    */
2917             uint32_t              : 1;
2918             __IOM uint32_t EBTLCB : 3;  /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function
2919                                          *   Select                                                                    */
2920             uint32_t              : 1;
2921             __IOM uint32_t EBTLPR : 3;  /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function
2922                                          *   Select                                                                    */
2923             uint32_t               : 5;
2924             __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping
2925                                          *   Function Select                                                           */
2926             uint32_t               : 1;
2927             __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping
2928                                          *   Function Select                                                           */
2929             uint32_t               : 1;
2930             __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function
2931                                          *   Select                                                                    */
2932             uint32_t               : 1;
2933             __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function
2934                                          *   Select                                                                    */
2935             uint32_t : 1;
2936         } GTEITLB_b;
2937     };
2938     __IM uint32_t RESERVED[6];
2939 
2940     union
2941     {
2942         __IOM uint32_t GTSECSR;         /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous
2943                                          *                  Control Channel Select Register                            */
2944 
2945         struct
2946         {
2947             __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel
2948                                          *   Select                                                                    */
2949             __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel
2950                                          *   Select                                                                    */
2951             __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel
2952                                          *   Select                                                                    */
2953             __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel
2954                                          *   Select                                                                    */
2955             __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel
2956                                          *   Select                                                                    */
2957             __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel
2958                                          *   Select                                                                    */
2959             __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel
2960                                          *   Select                                                                    */
2961             uint32_t : 25;
2962         } GTSECSR_b;
2963     };
2964 
2965     union
2966     {
2967         __IOM uint32_t GTSECR;         /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous
2968                                         *                  Control Register                                           */
2969 
2970         struct
2971         {
2972             __IOM uint32_t SBDCE : 1;  /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable                */
2973             __IOM uint32_t SBDPE : 1;  /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable                 */
2974             __IOM uint32_t SBDAE : 1;  /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable               */
2975             __IOM uint32_t SBDDE : 1;  /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable                 */
2976             uint32_t             : 4;
2977             __IOM uint32_t SBDCD : 1;  /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable               */
2978             __IOM uint32_t SBDPD : 1;  /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable                */
2979             __IOM uint32_t SBDAD : 1;  /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable            */
2980             __IOM uint32_t SBDDD : 1;  /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable              */
2981             uint32_t             : 20;
2982         } GTSECR_b;
2983     };
2984 
2985     union
2986     {
2987         __IOM uint32_t GTSWSR;          /*!< (@ 0x000000D8) General PWM Timer Switch Source Select Register            */
2988 
2989         struct
2990         {
2991             __IOM uint32_t WSGTRGA : 2; /*!< [1..0] GTETRGA Signal Edge Select to Switch Counter (GTETRGSA
2992                                          *   Signal for SAFTY)                                                         */
2993             __IOM uint32_t WSGTRGB : 2; /*!< [3..2] GTETRGB Signal Edge Select to Switch Counter (GTETRGSB
2994                                          *   Signal for SAFTY)                                                         */
2995             __IOM uint32_t WSGTRGC : 2; /*!< [5..4] GTETRGC Signal Edge Select to Switch Counter (GTETRGSC
2996                                          *   Signal for SAFTY)                                                         */
2997             __IOM uint32_t WSGTRGD : 2; /*!< [7..6] GTETRGD Signal Edge Select to Switch Counter (GTETRGSD
2998                                          *   Signal for SAFTY)                                                         */
2999             uint32_t              : 8;
3000             __IOM uint32_t WSELCA : 1;  /*!< [16..16] Event Source Counter Switch Enable                               */
3001             __IOM uint32_t WSELCB : 1;  /*!< [17..17] Event Source Counter Switch Enable                               */
3002             __IOM uint32_t WSELCC : 1;  /*!< [18..18] Event Source Counter Switch Enable                               */
3003             __IOM uint32_t WSELCD : 1;  /*!< [19..19] Event Source Counter Switch Enable                               */
3004             __IOM uint32_t WSELCE : 1;  /*!< [20..20] Event Source Counter Switch Enable                               */
3005             __IOM uint32_t WSELCF : 1;  /*!< [21..21] Event Source Counter Switch Enable                               */
3006             __IOM uint32_t WSELCG : 1;  /*!< [22..22] Event Source Counter Switch Enable                               */
3007             __IOM uint32_t CSELCH : 1;  /*!< [23..23] Event Source Counter Switch Enable                               */
3008             uint32_t              : 8;
3009         } GTSWSR_b;
3010     };
3011     __IOM uint32_t GTSWOS;              /*!< (@ 0x000000DC) General PWM Timer Switch Offset Setting Register           */
3012 } R_GPT0_Type;                          /*!< Size = 224 (0xe0)                                                         */
3013 
3014 /* =========================================================================================================================== */
3015 /* ================                                          R_SCI0                                           ================ */
3016 /* =========================================================================================================================== */
3017 
3018 /**
3019  * @brief Serial Communication Interface 0 (R_SCI0)
3020  */
3021 
3022 typedef struct                         /*!< (@ 0x80001000) R_SCI0 Structure                                           */
3023 {
3024     union
3025     {
3026         __IM uint32_t RDR;             /*!< (@ 0x00000000) Receive Data Register                                      */
3027 
3028         struct
3029         {
3030             __IM uint32_t RDAT : 9;    /*!< [8..0] Serial receive data                                                */
3031             __IM uint32_t MPB  : 1;    /*!< [9..9] Multi-processor flag                                               */
3032             __IM uint32_t DR   : 1;    /*!< [10..10] Receive data ready flag                                          */
3033             __IM uint32_t FPER : 1;    /*!< [11..11] FIFO parity error flag                                           */
3034             __IM uint32_t FFER : 1;    /*!< [12..12] FIFO framing error flag                                          */
3035             uint32_t           : 11;
3036             __IM uint32_t ORER : 1;    /*!< [24..24] Overrun Error flag                                               */
3037             uint32_t           : 2;
3038             __IM uint32_t PER  : 1;    /*!< [27..27] Parity error flag                                                */
3039             __IM uint32_t FER  : 1;    /*!< [28..28] Framing error flag                                               */
3040             uint32_t           : 3;
3041         } RDR_b;
3042     };
3043 
3044     union
3045     {
3046         __IOM uint32_t TDR;            /*!< (@ 0x00000004) Transmit Data Register                                     */
3047 
3048         struct
3049         {
3050             __IOM uint32_t TDAT : 9;   /*!< [8..0] Serial transmit data                                               */
3051             __IOM uint32_t MPBT : 1;   /*!< [9..9] Multi-processor transfer bit flag                                  */
3052             uint32_t            : 22;
3053         } TDR_b;
3054     };
3055 
3056     union
3057     {
3058         __IOM uint32_t CCR0;           /*!< (@ 0x00000008) Common Control Register 0                                  */
3059 
3060         struct
3061         {
3062             __IOM uint32_t RE    : 1;  /*!< [0..0] Receive Enable                                                     */
3063             uint32_t             : 3;
3064             __IOM uint32_t TE    : 1;  /*!< [4..4] Transmit Enable                                                    */
3065             uint32_t             : 3;
3066             __IOM uint32_t MPIE  : 1;  /*!< [8..8] Multi-Processor Interrupt Enable                                   */
3067             __IOM uint32_t DCME  : 1;  /*!< [9..9] Data Compare Match Enable                                          */
3068             __IOM uint32_t IDSEL : 1;  /*!< [10..10] ID frame select                                                  */
3069             uint32_t             : 5;
3070             __IOM uint32_t RIE   : 1;  /*!< [16..16] Receive Interrupt Enable                                         */
3071             uint32_t             : 3;
3072             __IOM uint32_t TIE   : 1;  /*!< [20..20] Transmit Interrupt Enable                                        */
3073             __IOM uint32_t TEIE  : 1;  /*!< [21..21] Transmit End Interrupt Enable                                    */
3074             uint32_t             : 2;
3075             __IOM uint32_t SSE   : 1;  /*!< [24..24] SSn# Pin Function Enable                                         */
3076             uint32_t             : 7;
3077         } CCR0_b;
3078     };
3079 
3080     union
3081     {
3082         __IOM uint32_t CCR1;           /*!< (@ 0x0000000C) Common Control Register 1                                  */
3083 
3084         struct
3085         {
3086             __IOM uint32_t CTSE   : 1; /*!< [0..0] CTS Enable                                                         */
3087             __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable                                            */
3088             uint32_t              : 2;
3089             __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select                                      */
3090             __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O                                              */
3091             uint32_t              : 2;
3092             __IOM uint32_t PE     : 1; /*!< [8..8] Parity Enable                                                      */
3093             __IOM uint32_t PM     : 1; /*!< [9..9] Parity Mode                                                        */
3094             uint32_t              : 2;
3095             __IOM uint32_t TINV   : 1; /*!< [12..12] TXD invert                                                       */
3096             __IOM uint32_t RINV   : 1; /*!< [13..13] RXD invert                                                       */
3097             uint32_t              : 2;
3098             __IOM uint32_t SPLP   : 1; /*!< [16..16] Loopback Control                                                 */
3099             uint32_t              : 3;
3100             __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select                                 */
3101             uint32_t              : 3;
3102             __IOM uint32_t NFCS   : 3; /*!< [26..24] Noise Filter Clock Select                                        */
3103             uint32_t              : 1;
3104             __IOM uint32_t NFEN   : 1; /*!< [28..28] Digital Noise Filter Function Enable                             */
3105             uint32_t              : 3;
3106         } CCR1_b;
3107     };
3108 
3109     union
3110     {
3111         __IOM uint32_t CCR2;           /*!< (@ 0x00000010) Common Control Register 2                                  */
3112 
3113         struct
3114         {
3115             __IOM uint32_t BCP   : 3;  /*!< [2..0] Base Clock Pulse                                                   */
3116             uint32_t             : 1;
3117             __IOM uint32_t BGDM  : 1;  /*!< [4..4] Baud Rate Generator Double-Speed Mode Select                       */
3118             __IOM uint32_t ABCS  : 1;  /*!< [5..5] Asynchronous Mode Base Clock Select                                */
3119             __IOM uint32_t ABCSE : 1;  /*!< [6..6] Asynchronous Mode Extended Base Clock Select                       */
3120             uint32_t             : 1;
3121             __IOM uint32_t BRR   : 8;  /*!< [15..8] Bit rate setting                                                  */
3122             __IOM uint32_t BRME  : 1;  /*!< [16..16] BRME                                                             */
3123             uint32_t             : 3;
3124             __IOM uint32_t CKS   : 2;  /*!< [21..20] Clock Select                                                     */
3125             uint32_t             : 2;
3126             __IOM uint32_t MDDR  : 8;  /*!< [31..24] Modulation Duty setting                                          */
3127         } CCR2_b;
3128     };
3129 
3130     union
3131     {
3132         __IOM uint32_t CCR3;            /*!< (@ 0x00000014) Common Control Register 3                                  */
3133 
3134         struct
3135         {
3136             __IOM uint32_t CPHA    : 1; /*!< [0..0] Clock Phase Select                                                 */
3137             __IOM uint32_t CPOL    : 1; /*!< [1..1] Clock Polarity Select                                              */
3138             uint32_t               : 5;
3139             __IOM uint32_t BPEN    : 1; /*!< [7..7] Synchronizer bypass enable                                         */
3140             __IOM uint32_t CHR     : 2; /*!< [9..8] Character Length                                                   */
3141             uint32_t               : 2;
3142             __IOM uint32_t LSBF    : 1; /*!< [12..12] LSB First select                                                 */
3143             __IOM uint32_t SINV    : 1; /*!< [13..13] Transmitted/Received Data Invert                                 */
3144             __IOM uint32_t STP     : 1; /*!< [14..14] Stop Bit Length                                                  */
3145             __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select                     */
3146             __IOM uint32_t MOD     : 3; /*!< [18..16] Communication mode select                                        */
3147             __IOM uint32_t MP      : 1; /*!< [19..19] Multi-Processor Mode                                             */
3148             __IOM uint32_t FM      : 1; /*!< [20..20] FIFO Mode select                                                 */
3149             __IOM uint32_t DEN     : 1; /*!< [21..21] Driver enable                                                    */
3150             uint32_t               : 2;
3151             __IOM uint32_t CKE     : 2; /*!< [25..24] Clock enable                                                     */
3152             uint32_t               : 2;
3153             __IOM uint32_t GM      : 1; /*!< [28..28] GSM Mode                                                         */
3154             __IOM uint32_t BLK     : 1; /*!< [29..29] Block Transfer Mode                                              */
3155             uint32_t               : 2;
3156         } CCR3_b;
3157     };
3158 
3159     union
3160     {
3161         __IOM uint32_t CCR4;           /*!< (@ 0x00000018) Common Control Register 4                                  */
3162 
3163         struct
3164         {
3165             __IOM uint32_t CMPD : 9;   /*!< [8..0] Compare Match Data                                                 */
3166             uint32_t            : 7;
3167             __IOM uint32_t ASEN : 1;   /*!< [16..16] Adjust receive sampling timing enable                            */
3168             __IOM uint32_t ATEN : 1;   /*!< [17..17] Adjust transmit timing enable                                    */
3169             uint32_t            : 6;
3170             __IOM uint32_t AST  : 3;   /*!< [26..24] Adjustment value for receive Sampling Timing                     */
3171             __IOM uint32_t AJD  : 1;   /*!< [27..27] Adjustment Direction for receive sampling timing                 */
3172             __IOM uint32_t ATT  : 3;   /*!< [30..28] Adjustment value for Transmit timing                             */
3173             __IOM uint32_t AET  : 1;   /*!< [31..31] Adjustment edge for transmit timing                              */
3174         } CCR4_b;
3175     };
3176     __IM uint32_t RESERVED;
3177 
3178     union
3179     {
3180         __IOM uint32_t ICR;                /*!< (@ 0x00000020) Simple I2C Control Register                                */
3181 
3182         struct
3183         {
3184             __IOM uint32_t IICDL      : 5; /*!< [4..0] SDA Delay Output Select                                            */
3185             uint32_t                  : 3;
3186             __IOM uint32_t IICINTM    : 1; /*!< [8..8] IICINTM                                                            */
3187             __IOM uint32_t IICCSC     : 1; /*!< [9..9] IICCSC                                                             */
3188             uint32_t                  : 3;
3189             __IOM uint32_t IICACKT    : 1; /*!< [13..13] IICACKT                                                          */
3190             uint32_t                  : 2;
3191             __IOM uint32_t IICSTAREQ  : 1; /*!< [16..16] IICSTAREQ                                                        */
3192             __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] IICRSTAREQ                                                       */
3193             __IOM uint32_t IICSTPREQ  : 1; /*!< [18..18] IICSTPREQ                                                        */
3194             uint32_t                  : 1;
3195             __IOM uint32_t IICSDAS    : 2; /*!< [21..20] IICSDAS                                                          */
3196             __IOM uint32_t IICSCLS    : 2; /*!< [23..22] IICSCLS                                                          */
3197             uint32_t                  : 8;
3198         } ICR_b;
3199     };
3200 
3201     union
3202     {
3203         __IOM uint32_t FCR;            /*!< (@ 0x00000024) FIFO Control Register                                      */
3204 
3205         struct
3206         {
3207             __IOM uint32_t DRES  : 1;  /*!< [0..0] Receive data ready error select                                    */
3208             uint32_t             : 7;
3209             __IOM uint32_t TTRG  : 5;  /*!< [12..8] Transmit FIFO data trigger number                                 */
3210             uint32_t             : 2;
3211             __OM uint32_t  TFRST : 1;  /*!< [15..15] Transmit FIFO Data Register Reset                                */
3212             __IOM uint32_t RTRG  : 5;  /*!< [20..16] Receive FIFO data trigger number                                 */
3213             uint32_t             : 2;
3214             __OM uint32_t  RFRST : 1;  /*!< [23..23] Receive FIFO Data Register Reset                                 */
3215             __IOM uint32_t RSTRG : 5;  /*!< [28..24] RTS# Output Active Trigger Number Select                         */
3216             uint32_t             : 3;
3217         } FCR_b;
3218     };
3219     __IM uint32_t RESERVED1[2];
3220 
3221     union
3222     {
3223         __IOM uint32_t DCR;            /*!< (@ 0x00000030) Driver Control Register                                    */
3224 
3225         struct
3226         {
3227             __IOM uint32_t DEPOL : 1;  /*!< [0..0] Driver effective polarity select                                   */
3228             uint32_t             : 7;
3229             __IOM uint32_t DEAST : 5;  /*!< [12..8] Driver Assertion Time                                             */
3230             uint32_t             : 3;
3231             __IOM uint32_t DENGT : 5;  /*!< [20..16] Driver negate time                                               */
3232             uint32_t             : 11;
3233         } DCR_b;
3234     };
3235     __IM uint32_t RESERVED2[5];
3236 
3237     union
3238     {
3239         __IM uint32_t CSR;             /*!< (@ 0x00000048) Common Status Register                                     */
3240 
3241         struct
3242         {
3243             uint32_t             : 4;
3244             __IM uint32_t ERS    : 1;  /*!< [4..4] Error Signal Status Flag                                           */
3245             uint32_t             : 10;
3246             __IM uint32_t RXDMON : 1;  /*!< [15..15] Serial input data monitor                                        */
3247             __IM uint32_t DCMF   : 1;  /*!< [16..16] Data Compare Match Flag                                          */
3248             __IM uint32_t DPER   : 1;  /*!< [17..17] Data Compare Match Parity Error Flag                             */
3249             __IM uint32_t DFER   : 1;  /*!< [18..18] Data Compare Match Framing Error Flag                            */
3250             uint32_t             : 5;
3251             __IM uint32_t ORER   : 1;  /*!< [24..24] ORER                                                             */
3252             uint32_t             : 1;
3253             __IM uint32_t MFF    : 1;  /*!< [26..26] Mode Fault Error Flag                                            */
3254             __IM uint32_t PER    : 1;  /*!< [27..27] PER                                                              */
3255             __IM uint32_t FER    : 1;  /*!< [28..28] FER                                                              */
3256             __IM uint32_t TDRE   : 1;  /*!< [29..29] Transmit Data Empty Flag                                         */
3257             __IM uint32_t TEND   : 1;  /*!< [30..30] TEND                                                             */
3258             __IM uint32_t RDRF   : 1;  /*!< [31..31] RDRF                                                             */
3259         } CSR_b;
3260     };
3261 
3262     union
3263     {
3264         __IM uint32_t ISR;             /*!< (@ 0x0000004C) Simple I2C Status Register                                 */
3265 
3266         struct
3267         {
3268             __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag                                            */
3269             uint32_t              : 2;
3270             __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed
3271                                         *   Flag                                                                      */
3272             uint32_t : 28;
3273         } ISR_b;
3274     };
3275 
3276     union
3277     {
3278         __IM uint32_t FRSR;            /*!< (@ 0x00000050) FIFO Receive Status Register                               */
3279 
3280         struct
3281         {
3282             __IM uint32_t DR   : 1;    /*!< [0..0] DR                                                                 */
3283             uint32_t           : 7;
3284             __IM uint32_t R    : 6;    /*!< [13..8] Receive FIFO Data Count                                           */
3285             uint32_t           : 2;
3286             __IM uint32_t PNUM : 6;    /*!< [21..16] Parity Error Count                                               */
3287             uint32_t           : 2;
3288             __IM uint32_t FNUM : 6;    /*!< [29..24] Framing Error Count                                              */
3289             uint32_t           : 2;
3290         } FRSR_b;
3291     };
3292 
3293     union
3294     {
3295         __IM uint32_t FTSR;            /*!< (@ 0x00000054) FIFO Transmit Status Register                              */
3296 
3297         struct
3298         {
3299             __IM uint32_t T : 6;       /*!< [5..0] Transmit FIFO Data Count                                           */
3300             uint32_t        : 26;
3301         } FTSR_b;
3302     };
3303     __IM uint32_t RESERVED3[4];
3304 
3305     union
3306     {
3307         __OM uint32_t CFCLR;           /*!< (@ 0x00000068) Common Flag Clear Register                                 */
3308 
3309         struct
3310         {
3311             uint32_t            : 4;
3312             __OM uint32_t ERSC  : 1;   /*!< [4..4] ERSC                                                               */
3313             uint32_t            : 11;
3314             __OM uint32_t DCMFC : 1;   /*!< [16..16] DCMFC                                                            */
3315             __OM uint32_t DPERC : 1;   /*!< [17..17] DPERC                                                            */
3316             __OM uint32_t DFERC : 1;   /*!< [18..18] DFERC                                                            */
3317             uint32_t            : 5;
3318             __OM uint32_t ORERC : 1;   /*!< [24..24] ORERC                                                            */
3319             uint32_t            : 1;
3320             __OM uint32_t MFFC  : 1;   /*!< [26..26] MFFC                                                             */
3321             __OM uint32_t PERC  : 1;   /*!< [27..27] PERC                                                             */
3322             __OM uint32_t FERC  : 1;   /*!< [28..28] FERC                                                             */
3323             __OM uint32_t TDREC : 1;   /*!< [29..29] TDREC                                                            */
3324             uint32_t            : 1;
3325             __OM uint32_t RDRFC : 1;   /*!< [31..31] RDRFC                                                            */
3326         } CFCLR_b;
3327     };
3328 
3329     union
3330     {
3331         __OM uint32_t ICFCLR;          /*!< (@ 0x0000006C) Simple I2C Flag Clear Register                             */
3332 
3333         struct
3334         {
3335             uint32_t               : 3;
3336             __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIFC                                                           */
3337             uint32_t               : 28;
3338         } ICFCLR_b;
3339     };
3340 
3341     union
3342     {
3343         __OM uint32_t FFCLR;           /*!< (@ 0x00000070) FIFO Flag Clear Register                                   */
3344 
3345         struct
3346         {
3347             __OM uint32_t DRC : 1;     /*!< [0..0] DRC                                                                */
3348             uint32_t          : 31;
3349         } FFCLR_b;
3350     };
3351 } R_SCI0_Type;                         /*!< Size = 116 (0x74)                                                         */
3352 
3353 /* =========================================================================================================================== */
3354 /* ================                                          R_SPI0                                           ================ */
3355 /* =========================================================================================================================== */
3356 
3357 /**
3358  * @brief Serial Peripheral Interface 0 (R_SPI0)
3359  */
3360 
3361 typedef struct                         /*!< (@ 0x80003000) R_SPI0 Structure                                           */
3362 {
3363     union
3364     {
3365         union
3366         {
3367             __IOM uint32_t SPDR;         /*!< (@ 0x00000000) SPI Data Register                                          */
3368 
3369             struct
3370             {
3371                 __IOM uint32_t SPD : 32; /*!< [31..0] The SPI data register (SPDR) is used to store SPI's
3372                                           *   transmit data and receive data. Transmit buffers and receive
3373                                           *   buffers independently function.                                           */
3374             } SPDR_b;
3375         };
3376         __IOM uint16_t SPDR_HA;          /*!< (@ 0x00000000) SPI Data Register                                          */
3377         __IOM uint8_t  SPDR_BY;          /*!< (@ 0x00000000) SPI Data Register                                          */
3378     };
3379 
3380     union
3381     {
3382         __IOM uint8_t SPCKD;           /*!< (@ 0x00000004) SPI Clock Delay Register                                   */
3383 
3384         struct
3385         {
3386             __IOM uint8_t SCKDL : 3;   /*!< [2..0] RSPCK Delay Setting                                                */
3387             uint8_t             : 5;
3388         } SPCKD_b;
3389     };
3390 
3391     union
3392     {
3393         __IOM uint8_t SSLND;           /*!< (@ 0x00000005) SPI Slave Select Negation Delay Register                   */
3394 
3395         struct
3396         {
3397             __IOM uint8_t SLNDL : 3;   /*!< [2..0] SSL Negation Delay Bits                                            */
3398             uint8_t             : 5;
3399         } SSLND_b;
3400     };
3401 
3402     union
3403     {
3404         __IOM uint8_t SPND;            /*!< (@ 0x00000006) SPI Next-Access Delay Register                             */
3405 
3406         struct
3407         {
3408             __IOM uint8_t SPNDL : 3;   /*!< [2..0] SPI Next-Access Delay Bits                                         */
3409             uint8_t             : 5;
3410         } SPND_b;
3411     };
3412 
3413     union
3414     {
3415         __IOM uint8_t MRCKD;           /*!< (@ 0x00000007) SPI ClocK Digital control Register for Master
3416                                         *                  Receive                                                    */
3417 
3418         struct
3419         {
3420             __IOM uint8_t ARST : 3;    /*!< [2..0] Receive Sampling Timing Adjustment Bits                            */
3421             uint8_t            : 5;
3422         } MRCKD_b;
3423     };
3424 
3425     union
3426     {
3427         __IOM uint32_t SPCR;             /*!< (@ 0x00000008) SPI Control Register                                       */
3428 
3429         struct
3430         {
3431             __IOM uint32_t SPE      : 1; /*!< [0..0] SPI Function Enable                                                */
3432             uint32_t                : 6;
3433             __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] SPI Master Receive Clock Select                                    */
3434             __IOM uint32_t SPPE     : 1; /*!< [8..8] Parity Enable                                                      */
3435             __IOM uint32_t SPOE     : 1; /*!< [9..9] Parity Mode                                                        */
3436             uint32_t                : 1;
3437             __IOM uint32_t PTE      : 1; /*!< [11..11] Parity Self-Diagnosis Enable                                     */
3438             __IOM uint32_t SCKASE   : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable                                  */
3439             __IOM uint32_t BFDS     : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select                       */
3440             __IOM uint32_t MODFEN   : 1; /*!< [14..14] Mode Fault Error Detection Enable                                */
3441             uint32_t                : 1;
3442             __IOM uint32_t SPEIE    : 1; /*!< [16..16] SPI Error Interrupt Enable                                       */
3443             __IOM uint32_t SPRIE    : 1; /*!< [17..17] SPI Receive Buffer Full Interrupt Enable                         */
3444             __IOM uint32_t SPIIE    : 1; /*!< [18..18] SPI Idle Interrupt Enable                                        */
3445             __IOM uint32_t SPDRES   : 1; /*!< [19..19] SPI Receive Data Ready Error Select                              */
3446             __IOM uint32_t SPTIE    : 1; /*!< [20..20] SPI Transmit Buffer Empty Interrupt Enable                       */
3447             __IOM uint32_t CENDIE   : 1; /*!< [21..21] SPI Communication End Interrupt Enable                           */
3448             uint32_t                : 2;
3449             __IOM uint32_t SPMS     : 1; /*!< [24..24] SPI Function Enable                                              */
3450             __IOM uint32_t SPFRF    : 1; /*!< [25..25] SPI Frame Format Select                                          */
3451             uint32_t                : 2;
3452             __IOM uint32_t TXMD     : 2; /*!< [29..28] Communication Mode Select                                        */
3453             __IOM uint32_t MSTR     : 1; /*!< [30..30] SPI Master/Slave Mode Select                                     */
3454             __IOM uint32_t BPEN     : 1; /*!< [31..31] Synchronization Circuit Bypass Enable                            */
3455         } SPCR_b;
3456     };
3457 
3458     union
3459     {
3460         __IOM uint8_t SPCRRM;          /*!< (@ 0x0000000C) SPI Control Register for Master Receive only               */
3461 
3462         struct
3463         {
3464             __IOM uint8_t RMFM  : 5;   /*!< [4..0] Frame processing count setting in Master Receive only              */
3465             uint8_t             : 1;
3466             __OM uint8_t RMEDTG : 1;   /*!< [6..6] Reading value is always 0.                                         */
3467             __OM uint8_t RMSTTG : 1;   /*!< [7..7] Reading value is always 0.                                         */
3468         } SPCRRM_b;
3469     };
3470 
3471     union
3472     {
3473         __IOM uint8_t SPDRCR;          /*!< (@ 0x0000000D) SPI Control Register for Received Data Ready
3474                                         *                  Detection                                                  */
3475 
3476         struct
3477         {
3478             __IOM uint8_t SPDRC : 8;   /*!< [7..0] SPDRC                                                              */
3479         } SPDRCR_b;
3480     };
3481 
3482     union
3483     {
3484         __IOM uint8_t SPPCR;           /*!< (@ 0x0000000E) SPI Pin Control Register                                   */
3485 
3486         struct
3487         {
3488             __IOM uint8_t SPLP  : 1;   /*!< [0..0] SPI Loopback                                                       */
3489             __IOM uint8_t SPLP2 : 1;   /*!< [1..1] SPI Loopback 2                                                     */
3490             __IOM uint8_t SPOM  : 1;   /*!< [2..2] SPI Output Pin Mode                                                */
3491             uint8_t             : 1;
3492             __IOM uint8_t MOIFV : 1;   /*!< [4..4] MOSI Idle Fixed Value                                              */
3493             __IOM uint8_t MOIFE : 1;   /*!< [5..5] MOSI Idle Value Fixing Enable                                      */
3494             uint8_t             : 2;
3495         } SPPCR_b;
3496     };
3497 
3498     union
3499     {
3500         __IOM uint8_t SPCR2;           /*!< (@ 0x0000000F) SPI Control Register 2                                     */
3501 
3502         struct
3503         {
3504             __IOM uint8_t SPSCKDL : 3; /*!< [2..0] SPI Master Receive Clock Analog Delay                              */
3505             uint8_t               : 5;
3506         } SPCR2_b;
3507     };
3508 
3509     union
3510     {
3511         __IOM uint8_t SSLP;            /*!< (@ 0x00000010) SPI Slave Select Polarity Register                         */
3512 
3513         struct
3514         {
3515             __IOM uint8_t SSL0P : 1;   /*!< [0..0] SSL0 Signal Polarity Setting                                       */
3516             __IOM uint8_t SSL1P : 1;   /*!< [1..1] SSL1 Signal Polarity Setting                                       */
3517             __IOM uint8_t SSL2P : 1;   /*!< [2..2] SSL2 Signal Polarity Setting                                       */
3518             __IOM uint8_t SSL3P : 1;   /*!< [3..3] SSL3 Signal Polarity Setting                                       */
3519             uint8_t             : 4;
3520         } SSLP_b;
3521     };
3522 
3523     union
3524     {
3525         __IOM uint8_t SPBR;            /*!< (@ 0x00000011) SPI Bit Rate Register                                      */
3526 
3527         struct
3528         {
3529             __IOM uint8_t SPR : 8;     /*!< [7..0] The SPBR register is used to set the bit rate in master
3530                                         *   mode. If SPBR is modified while SPCR.MSTR = 1 and SPCR.SPE
3531                                         *   = 1, subsequent operation is not guaranteed.                              */
3532         } SPBR_b;
3533     };
3534     __IM uint8_t RESERVED;
3535 
3536     union
3537     {
3538         __IOM uint8_t SPSCR;           /*!< (@ 0x00000013) SPI Sequence Control Register                              */
3539 
3540         struct
3541         {
3542             __IOM uint8_t SPSLN : 3;   /*!< [2..0] SPI Sequence Length Specification                                  */
3543             uint8_t             : 5;
3544         } SPSCR_b;
3545     };
3546 
3547     union
3548     {
3549         __IOM uint32_t SPCMD[8];       /*!< (@ 0x00000014) SPI Command Register [0..7] (m = 0 to 7)                   */
3550 
3551         struct
3552         {
3553             __IOM uint32_t CPHA   : 1; /*!< [0..0] RSPCK Phase                                                        */
3554             __IOM uint32_t CPOL   : 1; /*!< [1..1] RSPCK Polarity                                                     */
3555             __IOM uint32_t BRDV   : 2; /*!< [3..2] Bit Rate Division                                                  */
3556             uint32_t              : 3;
3557             __IOM uint32_t SSLKP  : 1; /*!< [7..7] SSL Signal Level Hold                                              */
3558             uint32_t              : 4;
3559             __IOM uint32_t LSBF   : 1; /*!< [12..12] SPI LSB First                                                    */
3560             __IOM uint32_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable                                     */
3561             __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable                                */
3562             __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable                                       */
3563             __IOM uint32_t SPB    : 5; /*!< [20..16] SPI Data Length                                                  */
3564             uint32_t              : 3;
3565             __IOM uint32_t SSLA   : 2; /*!< [25..24] SSL Signal Assertion                                             */
3566             uint32_t              : 6;
3567         } SPCMD_b[8];
3568     };
3569     __IM uint32_t RESERVED1[3];
3570 
3571     union
3572     {
3573         __IOM uint16_t SPDCR;          /*!< (@ 0x00000040) SPI Data Control Register                                  */
3574 
3575         struct
3576         {
3577             __IOM uint16_t BYSW   : 1; /*!< [0..0] Byte Swap Operating Mode Select                                    */
3578             __IOM uint16_t SLSEL  : 2; /*!< [2..1] SSL Pin Output Select                                              */
3579             __IOM uint16_t SPRDTD : 1; /*!< [3..3] SPI Receive Data or Transmit Data Selection                        */
3580             __IOM uint16_t SINV   : 1; /*!< [4..4] Serial data invert                                                 */
3581             uint16_t              : 3;
3582             __IOM uint16_t SPFC   : 2; /*!< [9..8] Frame Count                                                        */
3583             uint16_t              : 6;
3584         } SPDCR_b;
3585     };
3586     __IM uint16_t RESERVED2;
3587 
3588     union
3589     {
3590         __IOM uint16_t SPDCR2;         /*!< (@ 0x00000044) SPI Data Control Register 2                                */
3591 
3592         struct
3593         {
3594             __IOM uint16_t RTRG : 2;   /*!< [1..0] Receive FIFO threshold setting                                     */
3595             uint16_t            : 6;
3596             __IOM uint16_t TTRG : 2;   /*!< [9..8] Transmission FIFO threshold setting                                */
3597             uint16_t            : 6;
3598         } SPDCR2_b;
3599     };
3600     __IM uint16_t RESERVED3;
3601     __IM uint32_t RESERVED4[2];
3602     __IM uint8_t  RESERVED5;
3603 
3604     union
3605     {
3606         __IM uint8_t SPSSR;            /*!< (@ 0x00000051) SPI Sequence Status Register                               */
3607 
3608         struct
3609         {
3610             __IM uint8_t SPCP  : 3;    /*!< [2..0] SPI Command Pointer                                                */
3611             uint8_t            : 1;
3612             __IM uint8_t SPECM : 3;    /*!< [6..4] SPI Error Command                                                  */
3613             uint8_t            : 1;
3614         } SPSSR_b;
3615     };
3616 
3617     union
3618     {
3619         __IM uint16_t SPSR;            /*!< (@ 0x00000052) SPI Status Register                                        */
3620 
3621         struct
3622         {
3623             uint16_t            : 7;
3624             __IM uint16_t SPDRF : 1;   /*!< [7..7] SPI Receive Data Ready Flag                                        */
3625             __IM uint16_t OVRF  : 1;   /*!< [8..8] Overrun Error Flag                                                 */
3626             __IM uint16_t IDLNF : 1;   /*!< [9..9] SPI Idle Flag                                                      */
3627             __IM uint16_t MODF  : 1;   /*!< [10..10] Mode Fault Error Flag                                            */
3628             __IM uint16_t PERF  : 1;   /*!< [11..11] Parity Error Flag                                                */
3629             __IM uint16_t UDRF  : 1;   /*!< [12..12] Underrun Error Flag                                              */
3630             __IM uint16_t SPTEF : 1;   /*!< [13..13] SPI Transmit Buffer Empty Flag                                   */
3631             __IM uint16_t CENDF : 1;   /*!< [14..14] Communication End Flag                                           */
3632             __IM uint16_t SPRF  : 1;   /*!< [15..15] SPI Receive Buffer Full Flag                                     */
3633         } SPSR_b;
3634     };
3635     __IM uint32_t RESERVED6;
3636 
3637     union
3638     {
3639         __IM uint8_t SPTFSR;           /*!< (@ 0x00000058) SPI Transfer FIFO Status Register                          */
3640 
3641         struct
3642         {
3643             __IM uint8_t TFDN : 3;     /*!< [2..0] Transmit FIFO data empty stage number                              */
3644             uint8_t           : 5;
3645         } SPTFSR_b;
3646     };
3647     __IM uint8_t  RESERVED7;
3648     __IM uint16_t RESERVED8;
3649 
3650     union
3651     {
3652         __IM uint8_t SPRFSR;           /*!< (@ 0x0000005C) SPI Receive FIFO Status Register                           */
3653 
3654         struct
3655         {
3656             __IM uint8_t RFDN : 3;     /*!< [2..0] Receive FIFO data store stage number                               */
3657             uint8_t           : 5;
3658         } SPRFSR_b;
3659     };
3660     __IM uint8_t  RESERVED9;
3661     __IM uint16_t RESERVED10;
3662 
3663     union
3664     {
3665         __IM uint32_t SPPSR;           /*!< (@ 0x00000060) SPI Poling Register                                        */
3666 
3667         struct
3668         {
3669             __IM uint32_t SPEPS : 1;   /*!< [0..0] SPI Polling Status                                                 */
3670             uint32_t            : 31;
3671         } SPPSR_b;
3672     };
3673     __IM uint32_t RESERVED11;
3674     __IM uint16_t RESERVED12;
3675 
3676     union
3677     {
3678         __IOM uint16_t SPSRC;          /*!< (@ 0x0000006A) SPI Status Clear Register                                  */
3679 
3680         struct
3681         {
3682             uint16_t             : 7;
3683             __OM uint16_t SPDRFC : 1;  /*!< [7..7] SPI Receive Data Ready Flag Clear                                  */
3684             __OM uint16_t OVRFC  : 1;  /*!< [8..8] Overrun Error Flag Clear                                           */
3685             uint16_t             : 1;
3686             __OM uint16_t MODFC  : 1;  /*!< [10..10] Mode Fault Error Flag Clear                                      */
3687             __OM uint16_t PERFC  : 1;  /*!< [11..11] Parity Error Flag Clear                                          */
3688             __OM uint16_t UDRFC  : 1;  /*!< [12..12] Underrun Error Flag Clear                                        */
3689             __OM uint16_t SPTEFC : 1;  /*!< [13..13] SPI Transmit Buffer Empty Flag Clear                             */
3690             __OM uint16_t CENDFC : 1;  /*!< [14..14] Communication End Flag Clear                                     */
3691             __OM uint16_t SPRFC  : 1;  /*!< [15..15] SPI Receive Buffer Full Flag Clear                               */
3692         } SPSRC_b;
3693     };
3694 
3695     union
3696     {
3697         __OM uint8_t SPFCR;            /*!< (@ 0x0000006C) SPI FIFO Clear Register                                    */
3698 
3699         struct
3700         {
3701             __OM uint8_t SPFRST : 1;   /*!< [0..0] SPI FIFO clear                                                     */
3702             uint8_t             : 7;
3703         } SPFCR_b;
3704     };
3705     __IM uint8_t  RESERVED13;
3706     __IM uint16_t RESERVED14;
3707 } R_SPI0_Type;                         /*!< Size = 112 (0x70)                                                         */
3708 
3709 /* =========================================================================================================================== */
3710 /* ================                                          R_CRC0                                           ================ */
3711 /* =========================================================================================================================== */
3712 
3713 /**
3714  * @brief CRC Unit 0 (R_CRC0)
3715  */
3716 
3717 typedef struct                         /*!< (@ 0x80004000) R_CRC0 Structure                                           */
3718 {
3719     union
3720     {
3721         __IOM uint8_t CRCCR0;          /*!< (@ 0x00000000) CRC Control Register 0                                     */
3722 
3723         struct
3724         {
3725             __IOM uint8_t GPS    : 3;  /*!< [2..0] CRC Generating Polynomial Switching                                */
3726             uint8_t              : 3;
3727             __IOM uint8_t LMS    : 1;  /*!< [6..6] CRC Calculation Switching                                          */
3728             __OM uint8_t  DORCLR : 1;  /*!< [7..7] CRCDOR Register Clear                                              */
3729         } CRCCR0_b;
3730     };
3731     __IM uint8_t  RESERVED;
3732     __IM uint16_t RESERVED1;
3733 
3734     union
3735     {
3736         __IOM uint32_t CRCDIR;         /*!< (@ 0x00000004) CRC Data Input Register                                    */
3737         __IOM uint8_t  CRCDIR_BY;      /*!< (@ 0x00000004) CRC Data Input Register                                    */
3738     };
3739 
3740     union
3741     {
3742         __IOM uint32_t CRCDOR;         /*!< (@ 0x00000008) CRC Data Output Register                                   */
3743         __IOM uint16_t CRCDOR_HA;      /*!< (@ 0x00000008) CRC Data Output Register                                   */
3744         __IOM uint8_t  CRCDOR_BY;      /*!< (@ 0x00000008) CRC Data Output Register                                   */
3745     };
3746 } R_CRC0_Type;                         /*!< Size = 12 (0xc)                                                           */
3747 
3748 /* =========================================================================================================================== */
3749 /* ================                                          R_CANFD                                          ================ */
3750 /* =========================================================================================================================== */
3751 
3752 /**
3753  * @brief CAN-FD (R_CANFD)
3754  */
3755 
3756 typedef struct                         /*!< (@ 0x80020000) R_CANFD Structure                                          */
3757 {
3758     __IOM R_CANFD_CFDC_Type CFDC[2];   /*!< (@ 0x00000000) CANFD Channel [0..1] Registers                             */
3759     __IM uint32_t           RESERVED[24];
3760 
3761     union
3762     {
3763         __IM uint32_t CFDGIPV;         /*!< (@ 0x00000080) Global IP Version Register                                 */
3764 
3765         struct
3766         {
3767             __IM uint32_t IPV : 8;     /*!< [7..0] IP Version                                                         */
3768             __IM uint32_t IPT : 2;     /*!< [9..8] IP Type                                                            */
3769             uint32_t          : 6;
3770             __IM uint32_t PSI : 14;    /*!< [29..16] Parameter Status Information                                     */
3771             uint32_t          : 2;
3772         } CFDGIPV_b;
3773     };
3774 
3775     union
3776     {
3777         __IOM uint32_t CFDGCFG;         /*!< (@ 0x00000084) Global Configuration Register                              */
3778 
3779         struct
3780         {
3781             __IOM uint32_t TPRI   : 1;  /*!< [0..0] Transmission Priority                                              */
3782             __IOM uint32_t DCE    : 1;  /*!< [1..1] DLC Check Enable                                                   */
3783             __IOM uint32_t DRE    : 1;  /*!< [2..2] DLC Replacement Enable                                             */
3784             __IOM uint32_t MME    : 1;  /*!< [3..3] Mirror Mode Enable                                                 */
3785             __IOM uint32_t DCS    : 1;  /*!< [4..4] Data Link Controller Clock Select                                  */
3786             __IOM uint32_t CMPOC  : 1;  /*!< [5..5] CAN-FD Message Payload Overflow Configuration                      */
3787             uint32_t              : 2;
3788             __IOM uint32_t TSP    : 4;  /*!< [11..8] Timestamp Prescaler                                               */
3789             __IOM uint32_t TSSS   : 1;  /*!< [12..12] Timestamp Source Select                                          */
3790             __IOM uint32_t TSBTCS : 3;  /*!< [15..13] Timestamp Bit Time Channel Select                                */
3791             __IOM uint32_t ITRCP  : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler                         */
3792         } CFDGCFG_b;
3793     };
3794 
3795     union
3796     {
3797         __IOM uint32_t CFDGCTR;         /*!< (@ 0x00000088) Global Control Register                                    */
3798 
3799         struct
3800         {
3801             __IOM uint32_t GMDC    : 2; /*!< [1..0] Global Mode Control                                                */
3802             __IOM uint32_t GSLPR   : 1; /*!< [2..2] Global Sleep Request                                               */
3803             uint32_t               : 5;
3804             __IOM uint32_t DEIE    : 1; /*!< [8..8] DLC Check Interrupt Enable                                         */
3805             __IOM uint32_t MEIE    : 1; /*!< [9..9] Message Lost Error Interrupt Enable                                */
3806             __IOM uint32_t THLEIE  : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable                      */
3807             __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD Message Payload Overflow Flag Interrupt Enable            */
3808             __IOM uint32_t QOWEIE  : 1; /*!< [12..12] TXQ Message Overwrite Error Interrupt Enable                     */
3809             uint32_t               : 1;
3810             __IOM uint32_t QMEIE   : 1; /*!< [14..14] TXQ Message Lost Error Interrupt Enable                          */
3811             __IOM uint32_t MOWEIE  : 1; /*!< [15..15] Message Lost Error Interrupt Enable                              */
3812             __IOM uint32_t TSRST   : 1; /*!< [16..16] Timestamp Reset                                                  */
3813             uint32_t               : 15;
3814         } CFDGCTR_b;
3815     };
3816 
3817     union
3818     {
3819         __IM uint32_t CFDGSTS;          /*!< (@ 0x0000008C) Global Status Register                                     */
3820 
3821         struct
3822         {
3823             __IM uint32_t GRSTSTS  : 1; /*!< [0..0] Global Reset Status                                                */
3824             __IM uint32_t GHLTSTS  : 1; /*!< [1..1] Global Halt Status                                                 */
3825             __IM uint32_t GSLPSTS  : 1; /*!< [2..2] Global Sleep Status                                                */
3826             __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialization                                          */
3827             uint32_t               : 28;
3828         } CFDGSTS_b;
3829     };
3830 
3831     union
3832     {
3833         __IOM uint32_t CFDGERFL;       /*!< (@ 0x00000090) Global Error Flag Register                                 */
3834 
3835         struct
3836         {
3837             __IOM uint32_t DEF   : 1;  /*!< [0..0] DLC Error Flag                                                     */
3838             __IM uint32_t  MES   : 1;  /*!< [1..1] Message Lost Error Status                                          */
3839             __IM uint32_t  THLES : 1;  /*!< [2..2] TX History List Entry Lost Error Status                            */
3840             __IOM uint32_t CMPOF : 1;  /*!< [3..3] CAN-FD Message Payload Overflow Flag                               */
3841             __IM uint32_t  QOWES : 1;  /*!< [4..4] TXQ Message Overwrite Error Status                                 */
3842             uint32_t             : 1;
3843             __IM uint32_t QMES   : 1;  /*!< [6..6] TXQ Message Lost Error Status                                      */
3844             __IM uint32_t MOWES  : 1;  /*!< [7..7] Message Overwrite Error Status                                     */
3845             uint32_t             : 8;
3846             __IOM uint32_t EEF0  : 1;  /*!< [16..16] ECC Error Flag for Channel 0                                     */
3847             __IOM uint32_t EEF1  : 1;  /*!< [17..17] ECC Error Flag for Channel 1                                     */
3848             uint32_t             : 14;
3849         } CFDGERFL_b;
3850     };
3851 
3852     union
3853     {
3854         __IM uint32_t CFDGTSC;         /*!< (@ 0x00000094) Global Timestamp Counter Register                          */
3855 
3856         struct
3857         {
3858             __IM uint32_t TS : 16;     /*!< [15..0] Timestamp value                                                   */
3859             uint32_t         : 16;
3860         } CFDGTSC_b;
3861     };
3862 
3863     union
3864     {
3865         __IOM uint32_t CFDGAFLECTR;    /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register       */
3866 
3867         struct
3868         {
3869             __IOM uint32_t AFLPN  : 4; /*!< [3..0] Acceptance Filter List Page Number                                 */
3870             uint32_t              : 4;
3871             __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable                          */
3872             uint32_t              : 23;
3873         } CFDGAFLECTR_b;
3874     };
3875 
3876     union
3877     {
3878         __IOM uint32_t CFDGAFLCFG0;    /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register
3879                                         *                  0                                                          */
3880 
3881         struct
3882         {
3883             __IOM uint32_t RNC1 : 9;   /*!< [8..0] Rule Number for Channel 1                                          */
3884             uint32_t            : 7;
3885             __IOM uint32_t RNC0 : 9;   /*!< [24..16] Rule Number for Channel 0                                        */
3886             uint32_t            : 7;
3887         } CFDGAFLCFG0_b;
3888     };
3889     __IM uint32_t RESERVED1[3];
3890 
3891     union
3892     {
3893         __IOM uint32_t CFDRMNB;        /*!< (@ 0x000000AC) RX Message Buffer Number Register                          */
3894 
3895         struct
3896         {
3897             __IOM uint32_t NRXMB : 8;  /*!< [7..0] Number of RX Message Buffers                                       */
3898             __IOM uint32_t RMPLS : 3;  /*!< [10..8] Reception Message Buffer Payload Data Size                        */
3899             uint32_t             : 21;
3900         } CFDRMNB_b;
3901     };
3902 
3903     union
3904     {
3905         __IOM uint32_t CFDRMND0;       /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0                      */
3906 
3907         struct
3908         {
3909             __IOM uint32_t RMNS : 32;  /*!< [31..0] RX Message Buffer New Data Status                                 */
3910         } CFDRMND0_b;
3911     };
3912     __IM uint32_t RESERVED2[3];
3913 
3914     union
3915     {
3916         __IOM uint32_t CFDRFCC[8];     /*!< (@ 0x000000C0) RX FIFO Configuration/Control Register [0..7]              */
3917 
3918         struct
3919         {
3920             __IOM uint32_t RFE    : 1; /*!< [0..0] RX FIFO Enable                                                     */
3921             __IOM uint32_t RFIE   : 1; /*!< [1..1] RX FIFO Interrupt Enable                                           */
3922             uint32_t              : 2;
3923             __IOM uint32_t RFPLS  : 3; /*!< [6..4] Rx FIFO Payload Data Size Configuration                            */
3924             uint32_t              : 1;
3925             __IOM uint32_t RFDC   : 3; /*!< [10..8] RX FIFO Depth Configuration                                       */
3926             uint32_t              : 1;
3927             __IOM uint32_t RFIM   : 1; /*!< [12..12] RX FIFO Interrupt Mode                                           */
3928             __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value                       */
3929             __IOM uint32_t RFFIE  : 1; /*!< [16..16] RX FIFO Full Interrupt Enable                                    */
3930             uint32_t              : 15;
3931         } CFDRFCC_b[8];
3932     };
3933 
3934     union
3935     {
3936         __IOM uint32_t CFDRFSTS[8];    /*!< (@ 0x000000E0) RX FIFO Status Register [0..7]                             */
3937 
3938         struct
3939         {
3940             __IM uint32_t  RFEMP : 1;  /*!< [0..0] RX FIFO Empty                                                      */
3941             __IM uint32_t  RFFLL : 1;  /*!< [1..1] RX FIFO Full                                                       */
3942             __IOM uint32_t RFMLT : 1;  /*!< [2..2] RX FIFO Message Lost                                               */
3943             __IOM uint32_t RFIF  : 1;  /*!< [3..3] RX FIFO Interrupt Flag                                             */
3944             uint32_t             : 4;
3945             __IM uint32_t  RFMC  : 8;  /*!< [15..8] RX FIFO Message Count                                             */
3946             __IOM uint32_t RFFIF : 1;  /*!< [16..16] RX FIFO Full Interrupt Flag                                      */
3947             uint32_t             : 15;
3948         } CFDRFSTS_b[8];
3949     };
3950 
3951     union
3952     {
3953         __IOM uint32_t CFDRFPCTR[8];   /*!< (@ 0x00000100) RX FIFO Pointer Control Register [0..7]                    */
3954 
3955         struct
3956         {
3957             __IOM uint32_t RFPC : 8;   /*!< [7..0] RX FIFO Pointer Control                                            */
3958             uint32_t            : 24;
3959         } CFDRFPCTR_b[8];
3960     };
3961 
3962     union
3963     {
3964         __IOM uint32_t CFDCFCC[6];     /*!< (@ 0x00000120) Common FIFO Configuration/Control Register [0..5]          */
3965 
3966         struct
3967         {
3968             __IOM uint32_t CFE    : 1; /*!< [0..0] Common FIFO Enable                                                 */
3969             __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable                                    */
3970             __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable                                    */
3971             uint32_t              : 1;
3972             __IOM uint32_t CFPLS  : 3; /*!< [6..4] Common FIFO Payload Data Size Configuration                        */
3973             uint32_t              : 1;
3974             __IOM uint32_t CFM    : 2; /*!< [9..8] Common FIFO Mode                                                   */
3975             __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select                         */
3976             __IOM uint32_t CFITR  : 1; /*!< [11..11] Common FIFO Interval Timer Resolution                            */
3977             __IOM uint32_t CFIM   : 1; /*!< [12..12] Common FIFO Interrupt Mode                                       */
3978             __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value                   */
3979             __IOM uint32_t CFTML  : 5; /*!< [20..16] Common FIFO TX Message Buffer Link                               */
3980             __IOM uint32_t CFDC   : 3; /*!< [23..21] Common FIFO Depth Configuration                                  */
3981             __IOM uint32_t CFITT  : 8; /*!< [31..24] Common FIFO Interval Transmission Time                           */
3982         } CFDCFCC_b[6];
3983     };
3984     __IM uint32_t RESERVED3[18];
3985 
3986     union
3987     {
3988         __IOM uint32_t CFDCFCCE[6];      /*!< (@ 0x00000180) Common FIFO Configuration/Control Enhancement
3989                                           *                  Register [0..5]                                            */
3990 
3991         struct
3992         {
3993             __IOM uint32_t CFFIE    : 1; /*!< [0..0] Common FIFO Full Interrupt Enable                                  */
3994             __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable                   */
3995             __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable                */
3996             uint32_t                : 5;
3997             __IOM uint32_t CFMOWM   : 1; /*!< [8..8] Common FIFO Message Overwrite Mode                                 */
3998             uint32_t                : 7;
3999             __IOM uint32_t CFBME    : 1; /*!< [16..16] Common FIFO Buffering Mode Enable                                */
4000             uint32_t                : 15;
4001         } CFDCFCCE_b[6];
4002     };
4003     __IM uint32_t RESERVED4[18];
4004 
4005     union
4006     {
4007         __IOM uint32_t CFDCFSTS[6];      /*!< (@ 0x000001E0) Common FIFO Status Register [0..5]                         */
4008 
4009         struct
4010         {
4011             __IM uint32_t  CFEMP    : 1; /*!< [0..0] Common FIFO Empty                                                  */
4012             __IM uint32_t  CFFLL    : 1; /*!< [1..1] Common FIFO Full                                                   */
4013             __IOM uint32_t CFMLT    : 1; /*!< [2..2] Common FIFO Message Lost                                           */
4014             __IOM uint32_t CFRXIF   : 1; /*!< [3..3] Common RX FIFO Interrupt Flag                                      */
4015             __IOM uint32_t CFTXIF   : 1; /*!< [4..4] Common TX FIFO Interrupt Flag                                      */
4016             uint32_t                : 3;
4017             __IM uint32_t  CFMC     : 8; /*!< [15..8] Common FIFO Message Count                                         */
4018             __IOM uint32_t CFFIF    : 1; /*!< [16..16] Common FIFO Full Interrupt Flag                                  */
4019             __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag                   */
4020             __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag                */
4021             uint32_t                : 5;
4022             __IOM uint32_t CFMOW    : 1; /*!< [24..24] Common FIFO Message Overwrite                                    */
4023             uint32_t                : 7;
4024         } CFDCFSTS_b[6];
4025     };
4026     __IM uint32_t RESERVED5[18];
4027 
4028     union
4029     {
4030         __OM uint32_t CFDCFPCTR[6];    /*!< (@ 0x00000240) Common FIFO Pointer Control Register [0..5]                */
4031 
4032         struct
4033         {
4034             __OM uint32_t CFPC : 8;    /*!< [7..0] Common FIFO Pointer Control                                        */
4035             uint32_t           : 24;
4036         } CFDCFPCTR_b[6];
4037     };
4038     __IM uint32_t RESERVED6[18];
4039 
4040     union
4041     {
4042         __IM uint32_t CFDFESTS;        /*!< (@ 0x000002A0) FIFO Empty Status Register                                 */
4043 
4044         struct
4045         {
4046             __IM uint32_t RFXEMP : 8;  /*!< [7..0] RX FIFO Empty Status                                               */
4047             __IM uint32_t CFXEMP : 6;  /*!< [13..8] Common FIFO Empty Status                                          */
4048             uint32_t             : 18;
4049         } CFDFESTS_b;
4050     };
4051 
4052     union
4053     {
4054         __IM uint32_t CFDFFSTS;        /*!< (@ 0x000002A4) FIFO Full Status Register                                  */
4055 
4056         struct
4057         {
4058             __IM uint32_t RFXFLL : 8;  /*!< [7..0] RX FIFO Full Status                                                */
4059             __IM uint32_t CFXFLL : 6;  /*!< [13..8] Common FIFO Full Status                                           */
4060             uint32_t             : 18;
4061         } CFDFFSTS_b;
4062     };
4063 
4064     union
4065     {
4066         __IM uint32_t CFDFMSTS;        /*!< (@ 0x000002A8) FIFO Message Lost Status Register                          */
4067 
4068         struct
4069         {
4070             __IM uint32_t RFXMLT : 8;  /*!< [7..0] RX FIFO Message Lost Status                                        */
4071             __IM uint32_t CFXMLT : 6;  /*!< [13..8] Common FIFO Message Lost Status                                   */
4072             uint32_t             : 18;
4073         } CFDFMSTS_b;
4074     };
4075 
4076     union
4077     {
4078         __IM uint32_t CFDRFISTS;       /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register                     */
4079 
4080         struct
4081         {
4082             __IM uint32_t RFXIF   : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status                                   */
4083             uint32_t              : 8;
4084             __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status                            */
4085             uint32_t              : 8;
4086         } CFDRFISTS_b;
4087     };
4088 
4089     union
4090     {
4091         __IM uint32_t CFDCFRISTS;      /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register              */
4092 
4093         struct
4094         {
4095             __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO RX Interrupt Flag Status                               */
4096             uint32_t              : 26;
4097         } CFDCFRISTS_b;
4098     };
4099 
4100     union
4101     {
4102         __IM uint32_t CFDCFTISTS;      /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register              */
4103 
4104         struct
4105         {
4106             __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO TX Interrupt Flag Status                               */
4107             uint32_t              : 26;
4108         } CFDCFTISTS_b;
4109     };
4110 
4111     union
4112     {
4113         __IM uint32_t CFDCFOFRISTS;      /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status
4114                                           *                  Register                                                   */
4115 
4116         struct
4117         {
4118             __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO One Frame RX Interrupt Flag Status                     */
4119             uint32_t                : 26;
4120         } CFDCFOFRISTS_b;
4121     };
4122 
4123     union
4124     {
4125         __IM uint32_t CFDCFOFTISTS;      /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status
4126                                           *                  Register                                                   */
4127 
4128         struct
4129         {
4130             __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO One Frame TX Interrupt Flag Status                     */
4131             uint32_t                : 26;
4132         } CFDCFOFTISTS_b;
4133     };
4134 
4135     union
4136     {
4137         __IM uint32_t CFDCFMOWSTS;     /*!< (@ 0x000002C0) Common FIFO Message Overwrite Status Register              */
4138 
4139         struct
4140         {
4141             __IM uint32_t CFXMOW : 6;  /*!< [5..0] Common FIFO Massage Overwrite Status                               */
4142             uint32_t             : 26;
4143         } CFDCFMOWSTS_b;
4144     };
4145 
4146     union
4147     {
4148         __IM uint32_t CFDFFFSTS;       /*!< (@ 0x000002C4) FIFO FDC Full Status Register                              */
4149 
4150         struct
4151         {
4152             __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC Level Full Status                                      */
4153             __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC Level Full Status                                 */
4154             uint32_t              : 18;
4155         } CFDFFFSTS_b;
4156     };
4157     __IM uint32_t RESERVED7[2];
4158 
4159     union
4160     {
4161         __IOM uint8_t CFDTMC[128];     /*!< (@ 0x000002D0) TX Message Buffer Control Register [0..127]                */
4162 
4163         struct
4164         {
4165             __IOM uint8_t TMTR  : 1;   /*!< [0..0] TX Message Buffer Transmission Request                             */
4166             __IOM uint8_t TMTAR : 1;   /*!< [1..1] TX Message Buffer Transmission Abort Request                       */
4167             __IOM uint8_t TMOM  : 1;   /*!< [2..2] TX Message Buffer One-shot Mode                                    */
4168             uint8_t             : 5;
4169         } CFDTMC_b[128];
4170     };
4171     __IM uint32_t RESERVED8[288];
4172 
4173     union
4174     {
4175         __IOM uint8_t CFDTMSTS[128];   /*!< (@ 0x000007D0) TX Message Buffer Status Register [0..127]                 */
4176 
4177         struct
4178         {
4179             __IM uint8_t  TMTSTS : 1;  /*!< [0..0] TX Message Buffer Transmission Status                              */
4180             __IOM uint8_t TMTRF  : 2;  /*!< [2..1] TX Message Buffer Transmission Result Flag                         */
4181             __IM uint8_t  TMTRM  : 1;  /*!< [3..3] TX Message Buffer Transmission Request Mirrored                    */
4182             __IM uint8_t  TMTARM : 1;  /*!< [4..4] TX Message Buffer Transmission Abort Request Mirrored              */
4183             uint8_t              : 3;
4184         } CFDTMSTS_b[128];
4185     };
4186     __IM uint32_t RESERVED9[288];
4187 
4188     union
4189     {
4190         __IM uint32_t CFDTMTRSTS[4];    /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status
4191                                          *                  Register [0..3]                                            */
4192 
4193         struct
4194         {
4195             __IM uint32_t TMTRSTS : 16; /*!< [15..0] TX Message Buffer Transmission Request Status                     */
4196             uint32_t              : 16;
4197         } CFDTMTRSTS_b[4];
4198     };
4199     __IM uint32_t RESERVED10[36];
4200 
4201     union
4202     {
4203         __IM uint32_t CFDTMTARSTS[4];    /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request
4204                                           *                  Status Register [0..3]                                     */
4205 
4206         struct
4207         {
4208             __IM uint32_t TMTARSTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Request Status               */
4209             uint32_t               : 16;
4210         } CFDTMTARSTS_b[4];
4211     };
4212     __IM uint32_t RESERVED11[36];
4213 
4214     union
4215     {
4216         __IM uint32_t CFDTMTCSTS[4];    /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status
4217                                          *                  Register [0..3]                                            */
4218 
4219         struct
4220         {
4221             __IM uint32_t TMTCSTS : 16; /*!< [15..0] TX Message Buffer Transmission Completion Status                  */
4222             uint32_t              : 16;
4223         } CFDTMTCSTS_b[4];
4224     };
4225     __IM uint32_t RESERVED12[36];
4226 
4227     union
4228     {
4229         __IM uint32_t CFDTMTASTS[4];    /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register
4230                                          *                  [0..3]                                                     */
4231 
4232         struct
4233         {
4234             __IM uint32_t TMTASTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Status                       */
4235             uint32_t              : 16;
4236         } CFDTMTASTS_b[4];
4237     };
4238     __IM uint32_t RESERVED13[36];
4239 
4240     union
4241     {
4242         __IOM uint32_t CFDTMIEC[4];    /*!< (@ 0x00000F50) TX Message Buffer Transmission Interrupt Enable
4243                                         *                  Register [0..3]                                            */
4244 
4245         struct
4246         {
4247             __IOM uint32_t TMIE : 16;  /*!< [15..0] TX Message Buffer Interrupt Enable                                */
4248             uint32_t            : 16;
4249         } CFDTMIEC_b[4];
4250     };
4251     __IM uint32_t RESERVED14[40];
4252 
4253     union
4254     {
4255         __IOM uint32_t CFDTXQCC0[2];      /*!< (@ 0x00001000) TX Queue Configuration/Control Register 0[0..1]            */
4256 
4257         struct
4258         {
4259             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4260             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
4261             __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
4262             uint32_t                 : 2;
4263             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4264             uint32_t                 : 1;
4265             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4266             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4267             uint32_t                 : 3;
4268             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
4269             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
4270             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4271             uint32_t                 : 13;
4272         } CFDTXQCC0_b[2];
4273     };
4274     __IM uint32_t RESERVED15[6];
4275 
4276     union
4277     {
4278         __IOM uint32_t CFDTXQSTS0[2];     /*!< (@ 0x00001020) TX Queue Status Register 0[0..1]                           */
4279 
4280         struct
4281         {
4282             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4283             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4284             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4285             uint32_t                 : 5;
4286             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4287             uint32_t                 : 2;
4288             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
4289             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
4290             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4291             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
4292             __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
4293             uint32_t                 : 11;
4294         } CFDTXQSTS0_b[2];
4295     };
4296     __IM uint32_t RESERVED16[6];
4297 
4298     union
4299     {
4300         __OM uint32_t CFDTXQPCTR0[2];  /*!< (@ 0x00001040) TX Queue Pointer Control Register 0[0..1]                  */
4301 
4302         struct
4303         {
4304             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4305             uint32_t            : 24;
4306         } CFDTXQPCTR0_b[2];
4307     };
4308     __IM uint32_t RESERVED17[6];
4309 
4310     union
4311     {
4312         __IOM uint32_t CFDTXQCC1[2];      /*!< (@ 0x00001060) TX Queue Configuration/Control Register 1[0..1]            */
4313 
4314         struct
4315         {
4316             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4317             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
4318             __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
4319             uint32_t                 : 2;
4320             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4321             uint32_t                 : 1;
4322             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4323             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4324             uint32_t                 : 3;
4325             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
4326             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
4327             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4328             uint32_t                 : 13;
4329         } CFDTXQCC1_b[2];
4330     };
4331     __IM uint32_t RESERVED18[6];
4332 
4333     union
4334     {
4335         __IOM uint32_t CFDTXQSTS1[2];     /*!< (@ 0x00001080) TX Queue Status Register 1[0..1]                           */
4336 
4337         struct
4338         {
4339             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4340             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4341             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4342             uint32_t                 : 5;
4343             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4344             uint32_t                 : 2;
4345             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
4346             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
4347             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4348             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
4349             __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
4350             uint32_t                 : 11;
4351         } CFDTXQSTS1_b[2];
4352     };
4353     __IM uint32_t RESERVED19[6];
4354 
4355     union
4356     {
4357         __OM uint32_t CFDTXQPCTR1[2];  /*!< (@ 0x000010A0) TX Queue Pointer Control Register 1[0..1]                  */
4358 
4359         struct
4360         {
4361             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4362             uint32_t            : 24;
4363         } CFDTXQPCTR1_b[2];
4364     };
4365     __IM uint32_t RESERVED20[6];
4366 
4367     union
4368     {
4369         __IOM uint32_t CFDTXQCC2[2];      /*!< (@ 0x000010C0) TX Queue Configuration/Control Register 2[0..1]            */
4370 
4371         struct
4372         {
4373             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4374             __IOM uint32_t TXQGWE    : 1; /*!< [1..1] TX Queue Gateway Mode Enable                                       */
4375             __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
4376             uint32_t                 : 2;
4377             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4378             uint32_t                 : 1;
4379             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4380             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4381             uint32_t                 : 3;
4382             __IOM uint32_t TXQFIE    : 1; /*!< [16..16] TXQ Full Interrupt Enable                                        */
4383             __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable                         */
4384             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4385             uint32_t                 : 13;
4386         } CFDTXQCC2_b[2];
4387     };
4388     __IM uint32_t RESERVED21[6];
4389 
4390     union
4391     {
4392         __IOM uint32_t CFDTXQSTS2[2];     /*!< (@ 0x000010E0) TX Queue Status Register 2[0..1]                           */
4393 
4394         struct
4395         {
4396             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4397             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4398             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4399             uint32_t                 : 5;
4400             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4401             uint32_t                 : 2;
4402             __IOM uint32_t TXQFIF    : 1; /*!< [16..16] TXQ Full Interrupt Flag                                          */
4403             __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag                           */
4404             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4405             __IOM uint32_t TXQMLT    : 1; /*!< [19..19] TXQ Message Lost                                                 */
4406             __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
4407             uint32_t                 : 11;
4408         } CFDTXQSTS2_b[2];
4409     };
4410     __IM uint32_t RESERVED22[6];
4411 
4412     union
4413     {
4414         __OM uint32_t CFDTXQPCTR2[2];  /*!< (@ 0x00001100) TX Queue Pointer Control Register 2[0..1]                  */
4415 
4416         struct
4417         {
4418             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4419             uint32_t            : 24;
4420         } CFDTXQPCTR2_b[2];
4421     };
4422     __IM uint32_t RESERVED23[6];
4423 
4424     union
4425     {
4426         __IOM uint32_t CFDTXQCC3[2];      /*!< (@ 0x00001120) TX Queue Configuration/Control Register 3[0..1]            */
4427 
4428         struct
4429         {
4430             __IOM uint32_t TXQE      : 1; /*!< [0..0] TX Queue Enable                                                    */
4431             uint32_t                 : 1;
4432             __IOM uint32_t TXQOWE    : 1; /*!< [2..2] TX Queue Overwrite Mode Enable                                     */
4433             uint32_t                 : 2;
4434             __IOM uint32_t TXQTXIE   : 1; /*!< [5..5] TX Queue TX Interrupt Enable                                       */
4435             uint32_t                 : 1;
4436             __IOM uint32_t TXQIM     : 1; /*!< [7..7] TX Queue Interrupt Mode                                            */
4437             __IOM uint32_t TXQDC     : 5; /*!< [12..8] TX Queue Depth Configuration                                      */
4438             uint32_t                 : 5;
4439             __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable                      */
4440             uint32_t                 : 13;
4441         } CFDTXQCC3_b[2];
4442     };
4443     __IM uint32_t RESERVED24[6];
4444 
4445     union
4446     {
4447         __IOM uint32_t CFDTXQSTS3[2];     /*!< (@ 0x00001140) TX Queue Status Register 3[0..1]                           */
4448 
4449         struct
4450         {
4451             __IM uint32_t  TXQEMP    : 1; /*!< [0..0] TX Queue Empty                                                     */
4452             __IM uint32_t  TXQFLL    : 1; /*!< [1..1] TX Queue Full                                                      */
4453             __IOM uint32_t TXQTXIF   : 1; /*!< [2..2] TX Queue TX Interrupt Flag                                         */
4454             uint32_t                 : 5;
4455             __IM uint32_t TXQMC      : 6; /*!< [13..8] TX Queue Message Count                                            */
4456             uint32_t                 : 4;
4457             __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag                        */
4458             uint32_t                 : 1;
4459             __IOM uint32_t TXQMOW    : 1; /*!< [20..20] TXQ Message Overwrite                                            */
4460             uint32_t                 : 11;
4461         } CFDTXQSTS3_b[2];
4462     };
4463     __IM uint32_t RESERVED25[6];
4464 
4465     union
4466     {
4467         __OM uint32_t CFDTXQPCTR3[2];  /*!< (@ 0x00001160) TX Queue Pointer Control Register 3[0..1]                  */
4468 
4469         struct
4470         {
4471             __OM uint32_t TXQPC : 8;   /*!< [7..0] TX Queue Pointer Control                                           */
4472             uint32_t            : 24;
4473         } CFDTXQPCTR3_b[2];
4474     };
4475     __IM uint32_t RESERVED26[6];
4476 
4477     union
4478     {
4479         __IM uint32_t CFDTXQESTS;      /*!< (@ 0x00001180) TX Queue Empty Status Register                             */
4480 
4481         struct
4482         {
4483             __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ Empty Status                                                   */
4484             uint32_t              : 24;
4485         } CFDTXQESTS_b;
4486     };
4487 
4488     union
4489     {
4490         __IM uint32_t CFDTXQFISTS;      /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register                    */
4491 
4492         struct
4493         {
4494             __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status Flag for Channel 0                       */
4495             uint32_t               : 1;
4496             __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status Flag for Channel 1                       */
4497             uint32_t               : 25;
4498         } CFDTXQFISTS_b;
4499     };
4500 
4501     union
4502     {
4503         __IM uint32_t CFDTXQMSTS;      /*!< (@ 0x00001188) TX Queue Message Lost Status Register                      */
4504 
4505         struct
4506         {
4507             __IM uint32_t TXQ0ML : 3;  /*!< [2..0] TXQ Message Lost Status Flag for Channel 0                         */
4508             uint32_t             : 1;
4509             __IM uint32_t TXQ1ML : 3;  /*!< [6..4] TXQ Message Lost Status Flag for Channel 1                         */
4510             uint32_t             : 25;
4511         } CFDTXQMSTS_b;
4512     };
4513     __IM uint32_t RESERVED27;
4514 
4515     union
4516     {
4517         __IM uint32_t CFDTXQISTS;      /*!< (@ 0x00001190) TX Queue Interrupt Status Register                         */
4518 
4519         struct
4520         {
4521             __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for Channel 0                            */
4522             __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for Channel 1                            */
4523             uint32_t              : 24;
4524         } CFDTXQISTS_b;
4525     };
4526 
4527     union
4528     {
4529         __IM uint32_t CFDTXQOFTISTS;      /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register            */
4530 
4531         struct
4532         {
4533             __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for Channel 0               */
4534             __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for Channel 1               */
4535             uint32_t                 : 24;
4536         } CFDTXQOFTISTS_b;
4537     };
4538 
4539     union
4540     {
4541         __IM uint32_t CFDTXQOFRISTS;      /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register            */
4542 
4543         struct
4544         {
4545             __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag for Channel 0               */
4546             uint32_t                 : 1;
4547             __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag for Channel 1               */
4548             uint32_t                 : 25;
4549         } CFDTXQOFRISTS_b;
4550     };
4551 
4552     union
4553     {
4554         __IM uint32_t CFDTXQFSTS;      /*!< (@ 0x0000119C) TX Queue Full Status Register                              */
4555 
4556         struct
4557         {
4558             __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for Channel 0                                 */
4559             __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for Channel 1                                 */
4560             uint32_t              : 24;
4561         } CFDTXQFSTS_b;
4562     };
4563     __IM uint32_t RESERVED28[24];
4564 
4565     union
4566     {
4567         __IOM uint32_t CFDTHLCC[2];    /*!< (@ 0x00001200) TX History List Configuration/Control Register
4568                                         *                  [0..1]                                                     */
4569 
4570         struct
4571         {
4572             __IOM uint32_t THLE   : 1; /*!< [0..0] TX History List Enable                                             */
4573             uint32_t              : 7;
4574             __IOM uint32_t THLIE  : 1; /*!< [8..8] TX History List Interrupt Enable                                   */
4575             __IOM uint32_t THLIM  : 1; /*!< [9..9] TX History List Interrupt Mode                                     */
4576             __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable                              */
4577             __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated Gateway Enable                         */
4578             uint32_t              : 20;
4579         } CFDTHLCC_b[2];
4580     };
4581     __IM uint32_t RESERVED29[6];
4582 
4583     union
4584     {
4585         __IOM uint32_t CFDTHLSTS[2];   /*!< (@ 0x00001220) TX History List Status Register [0..1]                     */
4586 
4587         struct
4588         {
4589             __IM uint32_t  THLEMP : 1; /*!< [0..0] TX History List Empty                                              */
4590             __IM uint32_t  THLFLL : 1; /*!< [1..1] TX History List Full                                               */
4591             __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost                                         */
4592             __IOM uint32_t THLIF  : 1; /*!< [3..3] TX History List Interrupt Flag                                     */
4593             uint32_t              : 4;
4594             __IM uint32_t THLMC   : 6; /*!< [13..8] TX History List Message Count                                     */
4595             uint32_t              : 18;
4596         } CFDTHLSTS_b[2];
4597     };
4598     __IM uint32_t RESERVED30[6];
4599 
4600     union
4601     {
4602         __OM uint32_t CFDTHLPCTR[2];   /*!< (@ 0x00001240) TX History List Pointer Control Register [0..1]            */
4603 
4604         struct
4605         {
4606             __OM uint32_t THLPC : 8;   /*!< [7..0] TX History List Pointer Control                                    */
4607             uint32_t            : 24;
4608         } CFDTHLPCTR_b[2];
4609     };
4610     __IM uint32_t RESERVED31[46];
4611 
4612     union
4613     {
4614         __IM uint32_t CFDGTINTSTS0;    /*!< (@ 0x00001300) Global TX Interrupt Status Register 0                      */
4615 
4616         struct
4617         {
4618             __IM uint32_t TSIF0   : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0                             */
4619             __IM uint32_t TAIF0   : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0                                  */
4620             __IM uint32_t TQIF0   : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0                                  */
4621             __IM uint32_t CFTIF0  : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0                       */
4622             __IM uint32_t THIF0   : 1; /*!< [4..4] TX History List Interrupt Channel 0                                */
4623             __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel
4624                                         *   0                                                                         */
4625             __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel
4626                                         *   0                                                                         */
4627             uint32_t              : 1;
4628             __IM uint32_t TSIF1   : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1                             */
4629             __IM uint32_t TAIF1   : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1                                  */
4630             __IM uint32_t TQIF1   : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1                                */
4631             __IM uint32_t CFTIF1  : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1                     */
4632             __IM uint32_t THIF1   : 1; /*!< [12..12] TX History List Interrupt Channel 1                              */
4633             __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel
4634                                         *   1                                                                         */
4635             __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel
4636                                         *   1                                                                         */
4637             uint32_t : 17;
4638         } CFDGTINTSTS0_b;
4639     };
4640     __IM uint32_t RESERVED32;
4641 
4642     union
4643     {
4644         __IOM uint32_t CFDGTSTCFG;       /*!< (@ 0x00001308) Global Test Configuration Register                         */
4645 
4646         struct
4647         {
4648             __IOM uint32_t C0ICBCE : 1;  /*!< [0..0] Channel 0 Internal CAN Bus Communication Test Mode Enable          */
4649             __IOM uint32_t C1ICBCE : 1;  /*!< [1..1] Channel 1 Internal CAN Bus Communication Test Mode Enable          */
4650             uint32_t               : 14;
4651             __IOM uint32_t RTMPS   : 10; /*!< [25..16] RAM Test Mode Page Select                                        */
4652             uint32_t               : 6;
4653         } CFDGTSTCFG_b;
4654     };
4655 
4656     union
4657     {
4658         __IOM uint32_t CFDGTSTCTR;      /*!< (@ 0x0000130C) Global Test Control Register                               */
4659 
4660         struct
4661         {
4662             __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable                    */
4663             uint32_t               : 1;
4664             __IOM uint32_t RTME    : 1; /*!< [2..2] RAM Test Mode Enable                                               */
4665             uint32_t               : 29;
4666         } CFDGTSTCTR_b;
4667     };
4668     __IM uint32_t RESERVED33;
4669 
4670     union
4671     {
4672         __IOM uint32_t CFDGFDCFG;      /*!< (@ 0x00001314) Global FD Configuration Register                           */
4673 
4674         struct
4675         {
4676             __IOM uint32_t RPED   : 1; /*!< [0..0] RES Bit Protocol Exception Disable                                 */
4677             uint32_t              : 7;
4678             __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp Capture Configuration                                    */
4679             uint32_t              : 22;
4680         } CFDGFDCFG_b;
4681     };
4682     __IM uint32_t RESERVED34;
4683 
4684     union
4685     {
4686         __OM uint32_t CFDGLOCKK;       /*!< (@ 0x0000131C) Global Lock Key Register                                   */
4687 
4688         struct
4689         {
4690             __OM uint32_t LOCK : 16;   /*!< [15..0] Lock Key                                                          */
4691             uint32_t           : 16;
4692         } CFDGLOCKK_b;
4693     };
4694     __IM uint32_t RESERVED35[4];
4695 
4696     union
4697     {
4698         __IOM uint32_t CFDCDTCT;        /*!< (@ 0x00001330) DMA Transfer Control Register                              */
4699 
4700         struct
4701         {
4702             __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RX FIFO 0                                  */
4703             __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RX FIFO 1                                  */
4704             __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RX FIFO 2                                  */
4705             __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RX FIFO 3                                  */
4706             __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RX FIFO 4                                  */
4707             __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RX FIFO 5                                  */
4708             __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RX FIFO 6                                  */
4709             __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RX FIFO 7                                  */
4710             __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of Channel 0                 */
4711             __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of Channel 1                 */
4712             uint32_t               : 22;
4713         } CFDCDTCT_b;
4714     };
4715 
4716     union
4717     {
4718         __IM uint32_t CFDCDTSTS;         /*!< (@ 0x00001334) DMA Transfer Status Register                               */
4719 
4720         struct
4721         {
4722             __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0                                  */
4723             __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1                                  */
4724             __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2                                  */
4725             __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3                                  */
4726             __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4                                  */
4727             __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5                                  */
4728             __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6                                  */
4729             __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7                                  */
4730             __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of Channel
4731                                           *   0                                                                         */
4732             __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of Channel
4733                                           *   1                                                                         */
4734             uint32_t : 22;
4735         } CFDCDTSTS_b;
4736     };
4737     __IM uint32_t RESERVED36[2];
4738 
4739     union
4740     {
4741         __IOM uint32_t CFDCDTTCT;        /*!< (@ 0x00001340) DMA TX Transfer Control Register                           */
4742 
4743         struct
4744         {
4745             __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of Channel 0                      */
4746             __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of Channel 1                      */
4747             uint32_t                : 6;
4748             __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of Channel 0                      */
4749             __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of Channel 1                      */
4750             uint32_t                : 6;
4751             __IOM uint32_t CFDMAE0  : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of Channel
4752                                           *   0                                                                         */
4753             __IOM uint32_t CFDMAE1 : 1;  /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of Channel
4754                                           *   1                                                                         */
4755             uint32_t : 14;
4756         } CFDCDTTCT_b;
4757     };
4758 
4759     union
4760     {
4761         __IM uint32_t CFDCDTTSTS;         /*!< (@ 0x00001344) DMA TX Transfer Status Register                            */
4762 
4763         struct
4764         {
4765             __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of Channel 0                       */
4766             __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of Channel 1                       */
4767             uint32_t                 : 6;
4768             __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of Channel 0                       */
4769             __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of Channel 1                       */
4770             uint32_t                 : 6;
4771             __IM uint32_t CFDMASTS0  : 1; /*!< [16..16] DMA TX Transfer Status for Common FIFO 2 of Channel
4772                                            *   0                                                                         */
4773             __IM uint32_t CFDMASTS1 : 1;  /*!< [17..17] DMA TX Transfer Status for Common FIFO 2 of Channel
4774                                            *   1                                                                         */
4775             uint32_t : 14;
4776         } CFDCDTTSTS_b;
4777     };
4778     __IM uint32_t RESERVED37[2];
4779 
4780     union
4781     {
4782         __IM uint32_t CFDGRINTSTS[2];  /*!< (@ 0x00001350) Global RX Interrupt Status Register [0..1]                 */
4783 
4784         struct
4785         {
4786             __IM uint32_t QFIF    : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n (n = 0, 1)                       */
4787             uint32_t              : 1;
4788             __IM uint32_t BQFIF   : 2; /*!< [5..4] Borrowed TXQ Full Interrupt Flag Channel n (n = 0, 1)              */
4789             uint32_t              : 2;
4790             __IM uint32_t QOFRIF  : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n (n = 0, 1)              */
4791             uint32_t              : 1;
4792             __IM uint32_t BQOFRIF : 2; /*!< [13..12] Borrowed TXQ One Frame RX Interrupt Flag Channel n
4793                                         *   (n = 0, 1)                                                                */
4794             uint32_t             : 2;
4795             __IM uint32_t CFRIF  : 3;  /*!< [18..16] Common FIFO RX Interrupt Flag Channel n (n = 0, 1)               */
4796             uint32_t             : 5;
4797             __IM uint32_t CFRFIF : 3;  /*!< [26..24] Common FIFO FDC Level Full Interrupt Flag Channel n
4798                                         *   (n = 0, 1)                                                                */
4799             uint32_t              : 1;
4800             __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n (n
4801                                         *   = 0, 1)                                                                   */
4802             uint32_t : 1;
4803         } CFDGRINTSTS_b[2];
4804     };
4805     __IM uint32_t RESERVED38[10];
4806 
4807     union
4808     {
4809         __IOM uint32_t CFDGRSTC;       /*!< (@ 0x00001380) Global Reset Control Register                              */
4810 
4811         struct
4812         {
4813             __IOM uint32_t SRST : 1;   /*!< [0..0] Software Reset                                                     */
4814             uint32_t            : 7;
4815             __OM uint32_t KEY   : 8;   /*!< [15..8] Key Code                                                          */
4816             uint32_t            : 16;
4817         } CFDGRSTC_b;
4818     };
4819 
4820     union
4821     {
4822         __IOM uint32_t CFDGFCMC;       /*!< (@ 0x00001384) Global Flexible CAN Mode Configuration Register            */
4823 
4824         struct
4825         {
4826             __IOM uint32_t FLXC0 : 1;  /*!< [0..0] Flexible CAN Mode between Channel 0 and Channel 1                  */
4827             uint32_t             : 31;
4828         } CFDGFCMC_b;
4829     };
4830     __IM uint32_t RESERVED39;
4831 
4832     union
4833     {
4834         __IOM uint32_t CFDGFTBAC;      /*!< (@ 0x0000138C) Global Flexible Transmission Buffer Assignment
4835                                         *                  Configuration Register                                     */
4836 
4837         struct
4838         {
4839             __IOM uint32_t FLXMB0 : 4; /*!< [3..0] Flexible Transmission Buffer Assignment between Channel
4840                                         *   0 and Channel 1                                                           */
4841             uint32_t : 28;
4842         } CFDGFTBAC_b;
4843     };
4844     __IM uint32_t              RESERVED40[28];
4845     __IOM R_CANFD_CFDC2_Type   CFDC2[2];    /*!< (@ 0x00001400) Channel Configuration Registers                            */
4846     __IM uint32_t              RESERVED41[240];
4847     __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers                    */
4848     __IM uint32_t              RESERVED42[448];
4849     __IOM R_CANFD_CFDRM_Type   CFDRM[32];   /*!< (@ 0x00002000) RX Message Buffer Access Registers                         */
4850     __IM uint32_t              RESERVED43[3072];
4851     __IOM R_CANFD_CFDRF_Type   CFDRF[8];    /*!< (@ 0x00006000) RX FIFO Access Registers                                   */
4852     __IOM R_CANFD_CFDCF_Type   CFDCF[6];    /*!< (@ 0x00006400) Common FIFO Access Registers                               */
4853     __IM uint32_t              RESERVED44[1600];
4854     __IOM R_CANFD_CFDTHL_Type  CFDTHL[2];   /*!< (@ 0x00008000) Channel TX History List                                    */
4855     __IM uint32_t              RESERVED45[252];
4856 
4857     union
4858     {
4859         __IOM uint32_t CFDRPGACC[64];    /*!< (@ 0x00008400) RAM Test Page Access Register [0..63]                      */
4860 
4861         struct
4862         {
4863             __IOM uint32_t RDTA : 32;    /*!< [31..0] RAM Data Test Access                                              */
4864         } CFDRPGACC_b[64];
4865     };
4866     __IM uint32_t            RESERVED46[7872];
4867     __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Registers                                */
4868 } R_CANFD_Type;                          /*!< Size = 81920 (0x14000)                                                    */
4869 
4870 /* =========================================================================================================================== */
4871 /* ================                                           R_CMT                                           ================ */
4872 /* =========================================================================================================================== */
4873 
4874 /**
4875  * @brief Compare Match Timer Control (R_CMT)
4876  */
4877 
4878 typedef struct                         /*!< (@ 0x80040000) R_CMT Structure                                            */
4879 {
4880     __IOM R_CMT_UNT_Type UNT[3];       /*!< (@ 0x00000000) 3 Timer Start Register Units                               */
4881 } R_CMT_Type;                          /*!< Size = 3072 (0xc00)                                                       */
4882 
4883 /* =========================================================================================================================== */
4884 /* ================                                          R_CMTW0                                          ================ */
4885 /* =========================================================================================================================== */
4886 
4887 /**
4888  * @brief Compare Match Timer W (R_CMTW0)
4889  */
4890 
4891 typedef struct                         /*!< (@ 0x80041000) R_CMTW0 Structure                                          */
4892 {
4893     union
4894     {
4895         __IOM uint16_t CMWSTR;         /*!< (@ 0x00000000) Timer Start Register                                       */
4896 
4897         struct
4898         {
4899             __IOM uint16_t STR : 1;    /*!< [0..0] Counter Start                                                      */
4900             uint16_t           : 15;
4901         } CMWSTR_b;
4902     };
4903     __IM uint16_t RESERVED;
4904 
4905     union
4906     {
4907         __IOM uint16_t CMWCR;          /*!< (@ 0x00000004) Timer Control Register                                     */
4908 
4909         struct
4910         {
4911             __IOM uint16_t CKS   : 2;  /*!< [1..0] Clock Select                                                       */
4912             uint16_t             : 1;
4913             __IOM uint16_t CMWIE : 1;  /*!< [3..3] Compare Match Interrupt Enable                                     */
4914             __IOM uint16_t IC0IE : 1;  /*!< [4..4] Input Capture 0 Interrupt Enable                                   */
4915             __IOM uint16_t IC1IE : 1;  /*!< [5..5] Input Capture 1 Interrupt Enable                                   */
4916             __IOM uint16_t OC0IE : 1;  /*!< [6..6] Output Compare 0 Interrupt Enable                                  */
4917             __IOM uint16_t OC1IE : 1;  /*!< [7..7] Output Compare 1 Interrupt Enable                                  */
4918             uint16_t             : 1;
4919             __IOM uint16_t CMS   : 1;  /*!< [9..9] Timer Counter Size                                                 */
4920             uint16_t             : 3;
4921             __IOM uint16_t CCLR  : 3;  /*!< [15..13] Counter Clear                                                    */
4922         } CMWCR_b;
4923     };
4924     __IM uint16_t RESERVED1;
4925 
4926     union
4927     {
4928         __IOM uint16_t CMWIOR;         /*!< (@ 0x00000008) Timer I/O Control Register                                 */
4929 
4930         struct
4931         {
4932             __IOM uint16_t IC0  : 2;   /*!< [1..0] Input Capture Control 0                                            */
4933             __IOM uint16_t IC1  : 2;   /*!< [3..2] Input Capture Control 1                                            */
4934             __IOM uint16_t IC0E : 1;   /*!< [4..4] Input Capture Enable 0                                             */
4935             __IOM uint16_t IC1E : 1;   /*!< [5..5] Input Capture Enable 1                                             */
4936             uint16_t            : 2;
4937             __IOM uint16_t OC0  : 2;   /*!< [9..8] Output Compare Control 0                                           */
4938             __IOM uint16_t OC1  : 2;   /*!< [11..10] Output Compare Control 1                                         */
4939             __IOM uint16_t OC0E : 1;   /*!< [12..12] Compare Match Enable 0                                           */
4940             __IOM uint16_t OC1E : 1;   /*!< [13..13] Compare Match Enable 1                                           */
4941             uint16_t            : 1;
4942             __IOM uint16_t CMWE : 1;   /*!< [15..15] Compare Match Enable                                             */
4943         } CMWIOR_b;
4944     };
4945     __IM uint16_t  RESERVED2;
4946     __IM uint32_t  RESERVED3;
4947     __IOM uint32_t CMWCNT;             /*!< (@ 0x00000010) Timer Counter                                              */
4948     __IOM uint32_t CMWCOR;             /*!< (@ 0x00000014) Compare Match Constant Register                            */
4949     __IM uint32_t  CMWICR0;            /*!< (@ 0x00000018) Input Capture Registers                                    */
4950     __IM uint32_t  CMWICR1;            /*!< (@ 0x0000001C) Input Capture Registers                                    */
4951     __IOM uint32_t CMWOCR0;            /*!< (@ 0x00000020) Output Compare Registers                                   */
4952     __IOM uint32_t CMWOCR1;            /*!< (@ 0x00000024) Output Compare Registers                                   */
4953 } R_CMTW0_Type;                        /*!< Size = 40 (0x28)                                                          */
4954 
4955 /* =========================================================================================================================== */
4956 /* ================                                          R_WDT0                                           ================ */
4957 /* =========================================================================================================================== */
4958 
4959 /**
4960  * @brief Watchdog Timer 0 (R_WDT0)
4961  */
4962 
4963 typedef struct                         /*!< (@ 0x80042000) R_WDT0 Structure                                           */
4964 {
4965     __IOM uint8_t WDTRR;               /*!< (@ 0x00000000) WDT Refresh Register                                       */
4966     __IM uint8_t  RESERVED;
4967 
4968     union
4969     {
4970         __IOM uint16_t WDTCR;          /*!< (@ 0x00000002) WDT Control Register                                       */
4971 
4972         struct
4973         {
4974             __IOM uint16_t TOPS : 2;   /*!< [1..0] Timeout Period Selection                                           */
4975             uint16_t            : 2;
4976             __IOM uint16_t CKS  : 4;   /*!< [7..4] Clock Division Ratio Selection                                     */
4977             __IOM uint16_t RPES : 2;   /*!< [9..8] Window End Position Selection                                      */
4978             uint16_t            : 2;
4979             __IOM uint16_t RPSS : 2;   /*!< [13..12] Window Start Position Selection                                  */
4980             uint16_t            : 2;
4981         } WDTCR_b;
4982     };
4983 
4984     union
4985     {
4986         __IOM uint16_t WDTSR;           /*!< (@ 0x00000004) WDT Status Register                                        */
4987 
4988         struct
4989         {
4990             __IM uint16_t  CNTVAL : 14; /*!< [13..0] Down-Counter Value                                                */
4991             __IOM uint16_t UNDFF  : 1;  /*!< [14..14] Underflow Flag                                                   */
4992             __IOM uint16_t REFEF  : 1;  /*!< [15..15] Refresh Error Flag                                               */
4993         } WDTSR_b;
4994     };
4995 
4996     union
4997     {
4998         __IOM uint8_t WDTRCR;          /*!< (@ 0x00000006) WDT Reset Control Register                                 */
4999 
5000         struct
5001         {
5002             uint8_t               : 7;
5003             __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection                                  */
5004         } WDTRCR_b;
5005     };
5006     __IM uint8_t  RESERVED1;
5007     __IM uint16_t RESERVED2;
5008 } R_WDT0_Type;                         /*!< Size = 10 (0xa)                                                           */
5009 
5010 /* =========================================================================================================================== */
5011 /* ================                                          R_IIC0                                           ================ */
5012 /* =========================================================================================================================== */
5013 
5014 /**
5015  * @brief I2C Bus Interface 0 (R_IIC0)
5016  */
5017 
5018 typedef struct                         /*!< (@ 0x80043000) R_IIC0 Structure                                           */
5019 {
5020     union
5021     {
5022         __IOM uint8_t ICCR1;           /*!< (@ 0x00000000) I2C Bus Control Register 1                                 */
5023 
5024         struct
5025         {
5026             __IM uint8_t  SDAI   : 1;  /*!< [0..0] SDA Line Monitor                                                   */
5027             __IM uint8_t  SCLI   : 1;  /*!< [1..1] SCL Line Monitor                                                   */
5028             __IOM uint8_t SDAO   : 1;  /*!< [2..2] SDA Output Control/Monitor                                         */
5029             __IOM uint8_t SCLO   : 1;  /*!< [3..3] SCL Output Control/Monitor                                         */
5030             __OM uint8_t  SOWP   : 1;  /*!< [4..4] SCLO/SDAO Write Protect                                            */
5031             __IOM uint8_t CLO    : 1;  /*!< [5..5] Extra SCL Clock Cycle Output                                       */
5032             __IOM uint8_t IICRST : 1;  /*!< [6..6] IIC-Bus Interface Internal Reset                                   */
5033             __IOM uint8_t ICE    : 1;  /*!< [7..7] IIC-Bus Interface Enable                                           */
5034         } ICCR1_b;
5035     };
5036 
5037     union
5038     {
5039         __IOM uint8_t ICCR2;           /*!< (@ 0x00000001) I2C Bus Control Register 2                                 */
5040 
5041         struct
5042         {
5043             uint8_t            : 1;
5044             __IOM uint8_t ST   : 1;    /*!< [1..1] Start Condition Issuance Request                                   */
5045             __IOM uint8_t RS   : 1;    /*!< [2..2] Restart Condition Issuance Request                                 */
5046             __IOM uint8_t SP   : 1;    /*!< [3..3] Stop Condition Issuance Request                                    */
5047             uint8_t            : 1;
5048             __IOM uint8_t TRS  : 1;    /*!< [5..5] Transmit/Receive Mode                                              */
5049             __IOM uint8_t MST  : 1;    /*!< [6..6] Master/Slave Mode                                                  */
5050             __IM uint8_t  BBSY : 1;    /*!< [7..7] Bus Busy Detection Flag                                            */
5051         } ICCR2_b;
5052     };
5053 
5054     union
5055     {
5056         __IOM uint8_t ICMR1;           /*!< (@ 0x00000002) I2C Bus Mode Register 1                                    */
5057 
5058         struct
5059         {
5060             __IOM uint8_t BC   : 3;    /*!< [2..0] Bit Counter                                                        */
5061             __OM uint8_t  BCWP : 1;    /*!< [3..3] BC Write Protect                                                   */
5062             __IOM uint8_t CKS  : 3;    /*!< [6..4] Internal Reference Clock Select                                    */
5063             __IOM uint8_t MTWP : 1;    /*!< [7..7] MST/TRS Write Protect                                              */
5064         } ICMR1_b;
5065     };
5066 
5067     union
5068     {
5069         __IOM uint8_t ICMR2;           /*!< (@ 0x00000003) I2C Bus Mode Register 2                                    */
5070 
5071         struct
5072         {
5073             __IOM uint8_t TMOS : 1;    /*!< [0..0] Timeout Detection Time Select                                      */
5074             __IOM uint8_t TMOL : 1;    /*!< [1..1] Timeout L Count Control                                            */
5075             __IOM uint8_t TMOH : 1;    /*!< [2..2] Timeout H Count Control                                            */
5076             uint8_t            : 1;
5077             __IOM uint8_t SDDL : 3;    /*!< [6..4] SDA Output Delay Counter                                           */
5078             __IOM uint8_t DLCS : 1;    /*!< [7..7] SDA Output Delay Clock Source Select                               */
5079         } ICMR2_b;
5080     };
5081 
5082     union
5083     {
5084         __IOM uint8_t ICMR3;           /*!< (@ 0x00000004) I2C Bus Mode Register 3                                    */
5085 
5086         struct
5087         {
5088             __IOM uint8_t NF    : 2;   /*!< [1..0] Noise Filter Stage Select                                          */
5089             __IM uint8_t  ACKBR : 1;   /*!< [2..2] Receive Acknowledge                                                */
5090             __IOM uint8_t ACKBT : 1;   /*!< [3..3] Transmit Acknowledge                                               */
5091             __IOM uint8_t ACKWP : 1;   /*!< [4..4] ACKBT Write Protect                                                */
5092             __IOM uint8_t RDRFS : 1;   /*!< [5..5] RDRF Flag Set Timing Select                                        */
5093             __IOM uint8_t WAIT  : 1;   /*!< [6..6] WAIT                                                               */
5094             __IOM uint8_t SMBS  : 1;   /*!< [7..7] SMBus/IIC-Bus Select                                               */
5095         } ICMR3_b;
5096     };
5097 
5098     union
5099     {
5100         __IOM uint8_t ICFER;           /*!< (@ 0x00000005) I2C Bus Function Enable Register                           */
5101 
5102         struct
5103         {
5104             __IOM uint8_t TMOE  : 1;   /*!< [0..0] Timeout Function Enable                                            */
5105             __IOM uint8_t MALE  : 1;   /*!< [1..1] Master Arbitration-Lost Detection Enable                           */
5106             __IOM uint8_t NALE  : 1;   /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable                */
5107             __IOM uint8_t SALE  : 1;   /*!< [3..3] Slave Arbitration-Lost Detection Enable                            */
5108             __IOM uint8_t NACKE : 1;   /*!< [4..4] NACK Reception Transfer Suspension Enable                          */
5109             __IOM uint8_t NFE   : 1;   /*!< [5..5] Digital Noise Filter Circuit Enable                                */
5110             __IOM uint8_t SCLE  : 1;   /*!< [6..6] SCL Synchronous Circuit Enable                                     */
5111             uint8_t             : 1;
5112         } ICFER_b;
5113     };
5114 
5115     union
5116     {
5117         __IOM uint8_t ICSER;           /*!< (@ 0x00000006) I2C Bus Status Enable Register                             */
5118 
5119         struct
5120         {
5121             __IOM uint8_t SAR0E : 1;   /*!< [0..0] Slave Address Register 0 Enable                                    */
5122             __IOM uint8_t SAR1E : 1;   /*!< [1..1] Slave Address Register 1 Enable                                    */
5123             __IOM uint8_t SAR2E : 1;   /*!< [2..2] Slave Address Register 2 Enable                                    */
5124             __IOM uint8_t GCAE  : 1;   /*!< [3..3] General Call Address Enable                                        */
5125             uint8_t             : 1;
5126             __IOM uint8_t DIDE  : 1;   /*!< [5..5] Device ID Address Detection Enable                                 */
5127             uint8_t             : 1;
5128             __IOM uint8_t HOAE  : 1;   /*!< [7..7] Host Address Enable                                                */
5129         } ICSER_b;
5130     };
5131 
5132     union
5133     {
5134         __IOM uint8_t ICIER;           /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register                          */
5135 
5136         struct
5137         {
5138             __IOM uint8_t TMOIE : 1;   /*!< [0..0] Timeout Interrupt Request Enable                                   */
5139             __IOM uint8_t ALIE  : 1;   /*!< [1..1] Arbitration-Lost Interrupt Request Enable                          */
5140             __IOM uint8_t STIE  : 1;   /*!< [2..2] Start Condition Detection Interrupt Request Enable                 */
5141             __IOM uint8_t SPIE  : 1;   /*!< [3..3] Stop Condition Detection Interrupt Request Enable                  */
5142             __IOM uint8_t NAKIE : 1;   /*!< [4..4] NACK Reception Interrupt Request Enable                            */
5143             __IOM uint8_t RIE   : 1;   /*!< [5..5] Receive Data Full Interrupt Request Enable                         */
5144             __IOM uint8_t TEIE  : 1;   /*!< [6..6] Transmit End Interrupt Request Enable                              */
5145             __IOM uint8_t TIE   : 1;   /*!< [7..7] Transmit Data Empty Interrupt Request Enable                       */
5146         } ICIER_b;
5147     };
5148 
5149     union
5150     {
5151         __IOM uint8_t ICSR1;           /*!< (@ 0x00000008) I2C Bus Status Register 1                                  */
5152 
5153         struct
5154         {
5155             __IOM uint8_t AAS0 : 1;    /*!< [0..0] Slave Address 0 Detection Flag                                     */
5156             __IOM uint8_t AAS1 : 1;    /*!< [1..1] Slave Address 1 Detection Flag                                     */
5157             __IOM uint8_t AAS2 : 1;    /*!< [2..2] Slave Address 2 Detection Flag                                     */
5158             __IOM uint8_t GCA  : 1;    /*!< [3..3] General Call Address Detection Flag                                */
5159             uint8_t            : 1;
5160             __IOM uint8_t DID  : 1;    /*!< [5..5] Device ID Address Detection Flag                                   */
5161             uint8_t            : 1;
5162             __IOM uint8_t HOA  : 1;    /*!< [7..7] Host Address Detection Flag                                        */
5163         } ICSR1_b;
5164     };
5165 
5166     union
5167     {
5168         __IOM uint8_t ICSR2;           /*!< (@ 0x00000009) I2C Bus Status Register 2                                  */
5169 
5170         struct
5171         {
5172             __IOM uint8_t TMOF  : 1;   /*!< [0..0] Timeout Detection Flag                                             */
5173             __IOM uint8_t AL    : 1;   /*!< [1..1] Arbitration-Lost Flag                                              */
5174             __IOM uint8_t START : 1;   /*!< [2..2] Start Condition Detection Flag                                     */
5175             __IOM uint8_t STOP  : 1;   /*!< [3..3] Stop Condition Detection Flag                                      */
5176             __IOM uint8_t NACKF : 1;   /*!< [4..4] NACK Detection Flag                                                */
5177             __IOM uint8_t RDRF  : 1;   /*!< [5..5] Receive Data Full Flag                                             */
5178             __IOM uint8_t TEND  : 1;   /*!< [6..6] Transmit End Flag                                                  */
5179             __IM uint8_t  TDRE  : 1;   /*!< [7..7] Transmit Data Empty Flag                                           */
5180         } ICSR2_b;
5181     };
5182     __IOM R_IIC0_SAR_Type SAR[3];      /*!< (@ 0x0000000A) Slave Address Registers                                    */
5183 
5184     union
5185     {
5186         __IOM uint8_t ICBRL;           /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register                        */
5187 
5188         struct
5189         {
5190             __IOM uint8_t BRL : 5;     /*!< [4..0] Bit Rate Low-Level Period                                          */
5191             uint8_t           : 3;
5192         } ICBRL_b;
5193     };
5194 
5195     union
5196     {
5197         __IOM uint8_t ICBRH;           /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register                       */
5198 
5199         struct
5200         {
5201             __IOM uint8_t BRH : 5;     /*!< [4..0] Bit Rate High-Level Period                                         */
5202             uint8_t           : 3;
5203         } ICBRH_b;
5204     };
5205     __IOM uint8_t ICDRT;               /*!< (@ 0x00000012) I2C Bus Transmit Data Register                             */
5206     __IM uint8_t  ICDRR;               /*!< (@ 0x00000013) I2C Bus Receive Data Register                              */
5207 } R_IIC0_Type;                         /*!< Size = 20 (0x14)                                                          */
5208 
5209 /* =========================================================================================================================== */
5210 /* ================                                           R_DOC                                           ================ */
5211 /* =========================================================================================================================== */
5212 
5213 /**
5214  * @brief Data Operation Circuit (R_DOC)
5215  */
5216 
5217 typedef struct                         /*!< (@ 0x80044000) R_DOC Structure                                            */
5218 {
5219     union
5220     {
5221         __IOM uint8_t DOCR;            /*!< (@ 0x00000000) DOC Control Register                                       */
5222 
5223         struct
5224         {
5225             __IOM uint8_t OMS     : 2; /*!< [1..0] Operating Mode Select                                              */
5226             __IOM uint8_t DCSEL   : 1; /*!< [2..2] Detection Condition Select                                         */
5227             uint8_t               : 1;
5228             __IOM uint8_t DOPCIE  : 1; /*!< [4..4] Data Operation Circuit Interrupt Enable                            */
5229             __IM uint8_t  DOPCF   : 1; /*!< [5..5] Data Operation Circuit Flag                                        */
5230             __OM uint8_t  DOPCFCL : 1; /*!< [6..6] DOPCF Flag Clear                                                   */
5231             uint8_t               : 1;
5232         } DOCR_b;
5233     };
5234     __IM uint8_t   RESERVED;
5235     __IOM uint16_t DODIR;              /*!< (@ 0x00000002) DOC Data Input Register                                    */
5236     __IOM uint16_t DODSR;              /*!< (@ 0x00000004) DOC Data Setting Register                                  */
5237 } R_DOC_Type;                          /*!< Size = 6 (0x6)                                                            */
5238 
5239 /* =========================================================================================================================== */
5240 /* ================                                         R_ADC121                                          ================ */
5241 /* =========================================================================================================================== */
5242 
5243 /**
5244  * @brief 12-Bit A/D converter (R_ADC121)
5245  */
5246 
5247 typedef struct                         /*!< (@ 0x80045000) R_ADC121 Structure                                         */
5248 {
5249     union
5250     {
5251         __IOM uint16_t ADCSR;          /*!< (@ 0x00000000) A/D Control Register                                       */
5252 
5253         struct
5254         {
5255             __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel Select                                      */
5256             uint16_t              : 1;
5257             __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable                                  */
5258             __IOM uint16_t DBLE   : 1; /*!< [7..7] Double Trigger Mode Select                                         */
5259             __IOM uint16_t EXTRG  : 1; /*!< [8..8] Trigger Select                                                     */
5260             __IOM uint16_t TRGE   : 1; /*!< [9..9] Trigger Start Enable                                               */
5261             uint16_t              : 2;
5262             __IOM uint16_t ADIE   : 1; /*!< [12..12] Scan End Interrupt Enable                                        */
5263             __IOM uint16_t ADCS   : 2; /*!< [14..13] Scan Mode Select                                                 */
5264             __IOM uint16_t ADST   : 1; /*!< [15..15] A/D conversion Start                                             */
5265         } ADCSR_b;
5266     };
5267     __IM uint16_t RESERVED;
5268 
5269     union
5270     {
5271         __IOM uint16_t ADANSA0;        /*!< (@ 0x00000004) A/D Channel Select Register A0                             */
5272 
5273         struct
5274         {
5275             __IOM uint16_t ANSA0 : 8;  /*!< [7..0] A/D conversion Analog input Channel Select                         */
5276             uint16_t             : 8;
5277         } ADANSA0_b;
5278     };
5279     __IM uint16_t RESERVED1;
5280 
5281     union
5282     {
5283         __IOM uint16_t ADADS0;         /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Function
5284                                         *                  Channel Select Register 0                                  */
5285 
5286         struct
5287         {
5288             __IOM uint16_t ADS0 : 8;   /*!< [7..0] A/D-Converted Value Addition/Average Channel Select                */
5289             uint16_t            : 8;
5290         } ADADS0_b;
5291     };
5292     __IM uint16_t RESERVED2;
5293 
5294     union
5295     {
5296         __IOM uint8_t ADADC;           /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select
5297                                         *                  Register                                                   */
5298 
5299         struct
5300         {
5301             __IOM uint8_t ADC  : 3;    /*!< [2..0] Addition Count Select                                              */
5302             uint8_t            : 4;
5303             __IOM uint8_t AVEE : 1;    /*!< [7..7] Average Mode Enable                                                */
5304         } ADADC_b;
5305     };
5306     __IM uint8_t RESERVED3;
5307 
5308     union
5309     {
5310         __IOM uint16_t ADCER;          /*!< (@ 0x0000000E) A/D Control Extended Register                              */
5311 
5312         struct
5313         {
5314             uint16_t              : 1;
5315             __IOM uint16_t ADPRC  : 2; /*!< [2..1] A/D Conversion Accuracy Specify                                    */
5316             uint16_t              : 2;
5317             __IOM uint16_t ACE    : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable                        */
5318             uint16_t              : 9;
5319             __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select                                  */
5320         } ADCER_b;
5321     };
5322 
5323     union
5324     {
5325         __IOM uint16_t ADSTRGR;        /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register               */
5326 
5327         struct
5328         {
5329             __IOM uint16_t TRSB : 6;   /*!< [5..0] A/D Conversion Start Trigger Select for Group B                    */
5330             uint16_t            : 2;
5331             __IOM uint16_t TRSA : 6;   /*!< [13..8] A/D Conversion Start Trigger Select                               */
5332             uint16_t            : 2;
5333         } ADSTRGR_b;
5334     };
5335     __IM uint16_t RESERVED4;
5336 
5337     union
5338     {
5339         __IOM uint16_t ADANSB0;        /*!< (@ 0x00000014) A/D Channel Select Register B0                             */
5340 
5341         struct
5342         {
5343             __IOM uint16_t ANSB0 : 8;  /*!< [7..0] A/D Conversion Analog Input Channel Select                         */
5344             uint16_t             : 8;
5345         } ADANSB0_b;
5346     };
5347     __IM uint16_t RESERVED5;
5348 
5349     union
5350     {
5351         __IM uint16_t ADDBLDR;         /*!< (@ 0x00000018) A/D Data Duplication Register                              */
5352 
5353         struct
5354         {
5355             __IM uint16_t DBLDR : 16;  /*!< [15..0] The result of A/D conversion in response to the second
5356                                         *   trigger in double trigger mode.                                           */
5357         } ADDBLDR_b;
5358     };
5359     __IM uint16_t RESERVED6[3];
5360 
5361     union
5362     {
5363         __IM uint16_t ADDR[8];         /*!< (@ 0x00000020) A/D Data Register n (n = 0 to 3 for unit 0, n
5364                                         *                  = 0 to 7 for unit1)                                        */
5365 
5366         struct
5367         {
5368             __IM uint16_t DR : 16;     /*!< [15..0] The result of A/D conversion (n: Number of channel)               */
5369         } ADDR_b[8];
5370     };
5371     __IM uint16_t RESERVED7[27];
5372 
5373     union
5374     {
5375         __IOM uint16_t ADSHCR;         /*!< (@ 0x00000066) A/D Sample and Hold Control Register                       */
5376 
5377         struct
5378         {
5379             __IOM uint16_t SSTSH : 8;  /*!< [7..0] Sample and hold period setting                                     */
5380             __IOM uint16_t SHANS : 3;  /*!< [10..8] Sample and hold use or bypass select for ch0-2                    */
5381             uint16_t             : 5;
5382         } ADSHCR_b;
5383     };
5384     __IM uint16_t RESERVED8[10];
5385     __IM uint8_t  RESERVED9;
5386 
5387     union
5388     {
5389         __IOM uint8_t ADELCCR;         /*!< (@ 0x0000007D) A/D Event Link Control Register                            */
5390 
5391         struct
5392         {
5393             __IOM uint8_t ELCC  : 2;   /*!< [1..0] Event link control bits                                            */
5394             __IOM uint8_t GCELC : 1;   /*!< [2..2] Event control bit for Group C                                      */
5395             uint8_t             : 5;
5396         } ADELCCR_b;
5397     };
5398     __IM uint16_t RESERVED10;
5399 
5400     union
5401     {
5402         __IOM uint16_t ADGSPCR;        /*!< (@ 0x00000080) A/D Group Scan Priority Control Register                   */
5403 
5404         struct
5405         {
5406             __IOM uint16_t PGS    : 1; /*!< [0..0] Group Priority Control Setting                                     */
5407             __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting                                            */
5408             uint16_t              : 12;
5409             __IOM uint16_t LGRRS  : 1; /*!< [14..14] Restart Channel Select                                           */
5410             __IOM uint16_t GBRP   : 1; /*!< [15..15] Group B Single Scan Continuous Start                             */
5411         } ADGSPCR_b;
5412     };
5413     __IM uint16_t RESERVED11;
5414 
5415     union
5416     {
5417         __IM uint16_t ADDBLDRA;        /*!< (@ 0x00000084) A/D Data Duplication Register A                            */
5418 
5419         struct
5420         {
5421             __IM uint16_t DBLDRA : 16; /*!< [15..0] The result of A/D conversion during extended operation
5422                                         *   in double trigger mode                                                    */
5423         } ADDBLDRA_b;
5424     };
5425 
5426     union
5427     {
5428         __IM uint16_t ADDBLDRB;        /*!< (@ 0x00000086) A/D Data Duplication Register B                            */
5429 
5430         struct
5431         {
5432             __IM uint16_t DBLDRB : 16; /*!< [15..0] The result of A/D conversion during extended operation
5433                                         *   in double trigger mode                                                    */
5434         } ADDBLDRB_b;
5435     };
5436     __IM uint16_t RESERVED12[2];
5437 
5438     union
5439     {
5440         __IM uint8_t ADWINMON;         /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitoring
5441                                         *                  Register                                                   */
5442 
5443         struct
5444         {
5445             __IM uint8_t MONCOMB : 1;  /*!< [0..0] Combination result monitor                                         */
5446             uint8_t              : 3;
5447             __IM uint8_t MONCMPA : 1;  /*!< [4..4] Comparing result monitor for window A                              */
5448             __IM uint8_t MONCMPB : 1;  /*!< [5..5] Comparing result monitor for window B                              */
5449             uint8_t              : 2;
5450         } ADWINMON_b;
5451     };
5452     __IM uint8_t  RESERVED13;
5453     __IM uint16_t RESERVED14;
5454 
5455     union
5456     {
5457         __IOM uint16_t ADCMPCR;        /*!< (@ 0x00000090) A/D Compare Function Control Register                      */
5458 
5459         struct
5460         {
5461             __IOM uint16_t CMPAB  : 2; /*!< [1..0] Window A/B combination condition setting                           */
5462             uint16_t              : 7;
5463             __IOM uint16_t CMPBE  : 1; /*!< [9..9] Window B operation permission                                      */
5464             uint16_t              : 1;
5465             __IOM uint16_t CMPAE  : 1; /*!< [11..11] Window A operation permission                                    */
5466             uint16_t              : 1;
5467             __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare window B Interrupt Enable                                */
5468             __IOM uint16_t WCMPE  : 1; /*!< [14..14] Window Function enable                                           */
5469             __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare window A Interrupt Enable                                */
5470         } ADCMPCR_b;
5471     };
5472     __IM uint16_t RESERVED15;
5473 
5474     union
5475     {
5476         __IOM uint16_t ADCMPANSR0;      /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select
5477                                          *                  Register 0                                                 */
5478 
5479         struct
5480         {
5481             __IOM uint16_t CMPCHA0 : 8; /*!< [7..0] Window A Channel Select                                            */
5482             uint16_t               : 8;
5483         } ADCMPANSR0_b;
5484     };
5485     __IM uint16_t RESERVED16;
5486 
5487     union
5488     {
5489         __IOM uint16_t ADCMPLR0;         /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition
5490                                           *                  Setting Register 0                                         */
5491 
5492         struct
5493         {
5494             __IOM uint16_t CMPLCHA0 : 8; /*!< [7..0] Window A comparison condition for target channel (ch0-7)
5495                                           *   setting                                                                   */
5496             uint16_t : 8;
5497         } ADCMPLR0_b;
5498     };
5499     __IM uint16_t RESERVED17;
5500 
5501     union
5502     {
5503         __IOM uint16_t ADCMPDR0;        /*!< (@ 0x0000009C) A/D Comparison Function Window A Lower Level
5504                                          *                  Setting Register                                           */
5505 
5506         struct
5507         {
5508             __IOM uint16_t CMPLLA : 16; /*!< [15..0] Reference data setting when using the compare function
5509                                          *   window A                                                                  */
5510         } ADCMPDR0_b;
5511     };
5512 
5513     union
5514     {
5515         __IOM uint16_t ADCMPDR1;        /*!< (@ 0x0000009E) AD Comparison Function Window A Upper Level Setting
5516                                          *                  Register                                                   */
5517 
5518         struct
5519         {
5520             __IOM uint16_t CMPULA : 16; /*!< [15..0] Reference data setting when using the compare function
5521                                          *   window A                                                                  */
5522         } ADCMPDR1_b;
5523     };
5524 
5525     union
5526     {
5527         __IOM uint16_t ADCMPSR0;          /*!< (@ 0x000000A0) A/D Comparison Function Window A Channel Status
5528                                            *                  Register 0                                                 */
5529 
5530         struct
5531         {
5532             __IOM uint16_t CMPSTCHA0 : 8; /*!< [7..0] Window A Status Flag                                               */
5533             uint16_t                 : 8;
5534         } ADCMPSR0_b;
5535     };
5536     __IM uint16_t RESERVED18[2];
5537 
5538     union
5539     {
5540         __IOM uint8_t ADCMPBNSR;       /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Select
5541                                         *                  Register                                                   */
5542 
5543         struct
5544         {
5545             __IOM uint8_t CMPCHB : 6;  /*!< [5..0] Window B Channel Select                                            */
5546             uint8_t              : 1;
5547             __IOM uint8_t CMPLB  : 1;  /*!< [7..7] Window B Comparison Condition Setting                              */
5548         } ADCMPBNSR_b;
5549     };
5550     __IM uint8_t RESERVED19;
5551 
5552     union
5553     {
5554         __IOM uint16_t ADWINLLB;        /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level
5555                                          *                  Setting Register                                           */
5556 
5557         struct
5558         {
5559             __IOM uint16_t CMPLLB : 16; /*!< [15..0] Reference lower data setting when using the compare
5560                                          *   function window B                                                         */
5561         } ADWINLLB_b;
5562     };
5563 
5564     union
5565     {
5566         __IOM uint16_t ADWINULB;        /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level
5567                                          *                  Setting Register                                           */
5568 
5569         struct
5570         {
5571             __IOM uint16_t CMPULB : 16; /*!< [15..0] Reference upper data setting when using the compare
5572                                          *   function window B                                                         */
5573         } ADWINULB_b;
5574     };
5575 
5576     union
5577     {
5578         __IOM uint8_t ADCMPBSR;        /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register              */
5579 
5580         struct
5581         {
5582             __IOM uint8_t CMPSTB : 1;  /*!< [0..0] Window B Flag                                                      */
5583             uint8_t              : 7;
5584         } ADCMPBSR_b;
5585     };
5586     __IM uint8_t  RESERVED20;
5587     __IM uint16_t RESERVED21[19];
5588 
5589     union
5590     {
5591         __IOM uint16_t ADANSC0;        /*!< (@ 0x000000D4) A/D Channel Select Register C0                             */
5592 
5593         struct
5594         {
5595             __IOM uint16_t ANSC0 : 8;  /*!< [7..0] A/D-Converted Channel Select for Group C in Group Scan
5596                                         *   Mode                                                                      */
5597             uint16_t : 8;
5598         } ADANSC0_b;
5599     };
5600     __IM uint16_t RESERVED22;
5601     __IM uint8_t  RESERVED23;
5602 
5603     union
5604     {
5605         __IOM uint8_t ADGCTRGR;        /*!< (@ 0x000000D9) A/D Group C Trigger Select Register                        */
5606 
5607         struct
5608         {
5609             __IOM uint8_t TRSC   : 6;  /*!< [5..0] Group C A/D Conversion Start Trigger Select                        */
5610             __IOM uint8_t GCADIE : 1;  /*!< [6..6] Group C Scan Completion Interrupt Enable                           */
5611             __IOM uint8_t GRCE   : 1;  /*!< [7..7] Group C A/D Conversion Enable                                      */
5612         } ADGCTRGR_b;
5613     };
5614     __IM uint16_t RESERVED24[3];
5615 
5616     union
5617     {
5618         __IOM uint8_t ADSSTR[8];       /*!< (@ 0x000000E0) A/D Sampling State Register n (n = 0 to 3 for
5619                                         *                  unit 0, n = 0 to 7 for unit1)                              */
5620 
5621         struct
5622         {
5623             __IOM uint8_t SST : 8;     /*!< [7..0] Sampling Time Setting                                              */
5624         } ADSSTR_b[8];
5625     };
5626 } R_ADC121_Type;                       /*!< Size = 232 (0xe8)                                                         */
5627 
5628 /* =========================================================================================================================== */
5629 /* ================                                           R_TSU                                           ================ */
5630 /* =========================================================================================================================== */
5631 
5632 /**
5633  * @brief Temperature Sensor Unit (R_TSU)
5634  */
5635 
5636 typedef struct                         /*!< (@ 0x80046000) R_TSU Structure                                            */
5637 {
5638     union
5639     {
5640         __IOM uint32_t TSUSM;          /*!< (@ 0x00000000) Sensor Mode Register                                       */
5641 
5642         struct
5643         {
5644             __IOM uint32_t TSEN  : 1;  /*!< [0..0] Temperature Sensor Enable                                          */
5645             __IOM uint32_t ADCEN : 1;  /*!< [1..1] ADC Enable                                                         */
5646             uint32_t             : 30;
5647         } TSUSM_b;
5648     };
5649 
5650     union
5651     {
5652         __IOM uint32_t TSUST;          /*!< (@ 0x00000004) Sensor Trigger Register                                    */
5653 
5654         struct
5655         {
5656             __IOM uint32_t START : 1;  /*!< [0..0] A/D Conversion Control                                             */
5657             uint32_t             : 31;
5658         } TSUST_b;
5659     };
5660 
5661     union
5662     {
5663         __IOM uint32_t TSUSCS;         /*!< (@ 0x00000008) Sensor Configuration Setting Register                      */
5664 
5665         struct
5666         {
5667             uint32_t             : 3;
5668             __IOM uint32_t CKDIV : 1;  /*!< [3..3] Divider Value for PCLKL                                            */
5669             uint32_t             : 28;
5670         } TSUSCS_b;
5671     };
5672 
5673     union
5674     {
5675         __IM uint32_t TSUSAD;          /*!< (@ 0x0000000C) Sensor ADC Data Register                                   */
5676 
5677         struct
5678         {
5679             __IM uint32_t DOUT : 12;   /*!< [11..0] Temperature Sensor Data Output                                    */
5680             uint32_t           : 20;
5681         } TSUSAD_b;
5682     };
5683 
5684     union
5685     {
5686         __IM uint32_t TSUSS;           /*!< (@ 0x00000010) Sensor Status Register                                     */
5687 
5688         struct
5689         {
5690             __IM uint32_t CONV : 1;    /*!< [0..0] A/D Conversion Status                                              */
5691             uint32_t           : 31;
5692         } TSUSS_b;
5693     };
5694 } R_TSU_Type;                          /*!< Size = 20 (0x14)                                                          */
5695 
5696 /* =========================================================================================================================== */
5697 /* ================                                          R_POEG1                                          ================ */
5698 /* =========================================================================================================================== */
5699 
5700 /**
5701  * @brief GPT Port Output Enable 1 (R_POEG1)
5702  */
5703 
5704 typedef struct                         /*!< (@ 0x80047000) R_POEG1 Structure                                          */
5705 {
5706     union
5707     {
5708         __IOM uint32_t POEG1GA;        /*!< (@ 0x00000000) POEG1 Group A Setting Register                             */
5709 
5710         struct
5711         {
5712             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
5713             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
5714             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
5715             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
5716             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
5717             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
5718             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
5719             uint32_t             : 9;
5720             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
5721             uint32_t             : 11;
5722             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
5723             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
5724             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
5725         } POEG1GA_b;
5726     };
5727     __IM uint32_t RESERVED[255];
5728 
5729     union
5730     {
5731         __IOM uint32_t POEG1GB;        /*!< (@ 0x00000400) POEG1 Group B Setting Register                             */
5732 
5733         struct
5734         {
5735             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
5736             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
5737             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
5738             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
5739             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
5740             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
5741             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
5742             uint32_t             : 9;
5743             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
5744             uint32_t             : 11;
5745             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
5746             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
5747             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
5748         } POEG1GB_b;
5749     };
5750     __IM uint32_t RESERVED1[255];
5751 
5752     union
5753     {
5754         __IOM uint32_t POEG1GC;        /*!< (@ 0x00000800) POEG1 Group C Setting Register                             */
5755 
5756         struct
5757         {
5758             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
5759             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
5760             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
5761             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
5762             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
5763             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
5764             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
5765             uint32_t             : 9;
5766             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
5767             uint32_t             : 11;
5768             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
5769             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
5770             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
5771         } POEG1GC_b;
5772     };
5773     __IM uint32_t RESERVED2[255];
5774 
5775     union
5776     {
5777         __IOM uint32_t POEG1GD;        /*!< (@ 0x00000C00) POEG1 Group D Setting Register                             */
5778 
5779         struct
5780         {
5781             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
5782             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
5783             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
5784             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
5785             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
5786             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
5787             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
5788             uint32_t             : 9;
5789             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
5790             uint32_t             : 11;
5791             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
5792             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
5793             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
5794         } POEG1GD_b;
5795     };
5796 } R_POEG1_Type;                        /*!< Size = 3076 (0xc04)                                                       */
5797 
5798 /* =========================================================================================================================== */
5799 /* ================                                          R_DMAC0                                          ================ */
5800 /* =========================================================================================================================== */
5801 
5802 /**
5803  * @brief DMA Controller 0 (R_DMAC0)
5804  */
5805 
5806 typedef struct                         /*!< (@ 0x80080000) R_DMAC0 Structure                                          */
5807 {
5808     __IOM R_DMAC0_GRP_Type GRP[1];     /*!< (@ 0x00000000) 8 channel Registers                                        */
5809 } R_DMAC0_Type;                        /*!< Size = 804 (0x324)                                                        */
5810 
5811 /* =========================================================================================================================== */
5812 /* ================                                         R_ICU_NS                                          ================ */
5813 /* =========================================================================================================================== */
5814 
5815 /**
5816  * @brief Interrupt Controller in Non Safety Domain (R_ICU_NS)
5817  */
5818 
5819 typedef struct                         /*!< (@ 0x80090000) R_ICU_NS Structure                                         */
5820 {
5821     union
5822     {
5823         __OM uint32_t NS_SWINT;        /*!< (@ 0x00000000) Software Interrupt Register                                */
5824 
5825         struct
5826         {
5827             __OM uint32_t IC0 : 1;     /*!< [0..0] Software Interrupt register                                        */
5828             __OM uint32_t IC1 : 1;     /*!< [1..1] Software Interrupt register                                        */
5829             __OM uint32_t IC2 : 1;     /*!< [2..2] Software Interrupt register                                        */
5830             __OM uint32_t IC3 : 1;     /*!< [3..3] Software Interrupt register                                        */
5831             __OM uint32_t IC4 : 1;     /*!< [4..4] Software Interrupt register                                        */
5832             __OM uint32_t IC5 : 1;     /*!< [5..5] Software Interrupt register                                        */
5833             uint32_t          : 26;
5834         } NS_SWINT_b;
5835     };
5836 
5837     union
5838     {
5839         __IOM uint32_t NS_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register                     */
5840 
5841         struct
5842         {
5843             __IOM uint32_t FLT0   : 1;   /*!< [0..0] Noise filter enable for IRQ0                                       */
5844             __IOM uint32_t FLT1   : 1;   /*!< [1..1] Noise filter enable for IRQ1                                       */
5845             __IOM uint32_t FLT2   : 1;   /*!< [2..2] Noise filter enable for IRQ2                                       */
5846             __IOM uint32_t FLT3   : 1;   /*!< [3..3] Noise filter enable for IRQ3                                       */
5847             __IOM uint32_t FLT4   : 1;   /*!< [4..4] Noise filter enable for IRQ4                                       */
5848             __IOM uint32_t FLT5   : 1;   /*!< [5..5] Noise filter enable for IRQ5                                       */
5849             __IOM uint32_t FLT6   : 1;   /*!< [6..6] Noise filter enable for IRQ6                                       */
5850             __IOM uint32_t FLT7   : 1;   /*!< [7..7] Noise filter enable for IRQ7                                       */
5851             __IOM uint32_t FLT8   : 1;   /*!< [8..8] Noise filter enable for IRQ8                                       */
5852             __IOM uint32_t FLT9   : 1;   /*!< [9..9] Noise filter enable for IRQ9                                       */
5853             __IOM uint32_t FLT10  : 1;   /*!< [10..10] Noise filter enable for IRQ10                                    */
5854             __IOM uint32_t FLT11  : 1;   /*!< [11..11] Noise filter enable for IRQ11                                    */
5855             __IOM uint32_t FLT12  : 1;   /*!< [12..12] Noise filter enable for IRQ12                                    */
5856             __IOM uint32_t FLT13  : 1;   /*!< [13..13] Noise filter enable for IRQ13                                    */
5857             __IOM uint32_t FLTDRQ : 1;   /*!< [14..14] Noise filter enable for External DMA request (DREQ)              */
5858             uint32_t              : 17;
5859         } NS_PORTNF_FLTSEL_b;
5860     };
5861 
5862     union
5863     {
5864         __IOM uint32_t NS_PORTNF_CLKSEL;  /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register                    */
5865 
5866         struct
5867         {
5868             __IOM uint32_t CKSEL0    : 2; /*!< [1..0] Noise filter sampling clock selector                               */
5869             __IOM uint32_t CKSEL1    : 2; /*!< [3..2] Noise filter sampling clock selector                               */
5870             __IOM uint32_t CKSEL2    : 2; /*!< [5..4] Noise filter sampling clock selector                               */
5871             __IOM uint32_t CKSEL3    : 2; /*!< [7..6] Noise filter sampling clock selector                               */
5872             __IOM uint32_t CKSEL4    : 2; /*!< [9..8] Noise filter sampling clock selector                               */
5873             __IOM uint32_t CKSEL5    : 2; /*!< [11..10] Noise filter sampling clock selector                             */
5874             __IOM uint32_t CKSEL6    : 2; /*!< [13..12] Noise filter sampling clock selector                             */
5875             __IOM uint32_t CKSEL7    : 2; /*!< [15..14] Noise filter sampling clock selector                             */
5876             __IOM uint32_t CKSEL8    : 2; /*!< [17..16] Noise filter sampling clock selector                             */
5877             __IOM uint32_t CKSEL9    : 2; /*!< [19..18] Noise filter sampling clock selector                             */
5878             __IOM uint32_t CKSEL10   : 2; /*!< [21..20] Noise filter sampling clock selector                             */
5879             __IOM uint32_t CKSEL11   : 2; /*!< [23..22] Noise filter sampling clock selector                             */
5880             __IOM uint32_t CKSEL12   : 2; /*!< [25..24] Noise filter sampling clock selector                             */
5881             __IOM uint32_t CKSEL13   : 2; /*!< [27..26] Noise filter sampling clock selector                             */
5882             __IOM uint32_t CKSELDREQ : 2; /*!< [29..28] Noise filter sampling clock selector                             */
5883             uint32_t                 : 2;
5884         } NS_PORTNF_CLKSEL_b;
5885     };
5886 
5887     union
5888     {
5889         __IOM uint32_t NS_PORTNF_MD;   /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register                  */
5890 
5891         struct
5892         {
5893             __IOM uint32_t MD0   : 2;  /*!< [1..0] Select detection mode for IRQ0                                     */
5894             __IOM uint32_t MD1   : 2;  /*!< [3..2] Select detection mode for IRQ1                                     */
5895             __IOM uint32_t MD2   : 2;  /*!< [5..4] Select detection mode for IRQ2                                     */
5896             __IOM uint32_t MD3   : 2;  /*!< [7..6] Select detection mode for IRQ3                                     */
5897             __IOM uint32_t MD4   : 2;  /*!< [9..8] Select detection mode for IRQ4                                     */
5898             __IOM uint32_t MD5   : 2;  /*!< [11..10] Select detection mode for IRQ5                                   */
5899             __IOM uint32_t MD6   : 2;  /*!< [13..12] Select detection mode for IRQ6                                   */
5900             __IOM uint32_t MD7   : 2;  /*!< [15..14] Select detection mode for IRQ7                                   */
5901             __IOM uint32_t MD8   : 2;  /*!< [17..16] Select detection mode for IRQ8                                   */
5902             __IOM uint32_t MD9   : 2;  /*!< [19..18] Select detection mode for IRQ9                                   */
5903             __IOM uint32_t MD10  : 2;  /*!< [21..20] Select detection mode for IRQ10                                  */
5904             __IOM uint32_t MD11  : 2;  /*!< [23..22] Select detection mode for IRQ11                                  */
5905             __IOM uint32_t MD12  : 2;  /*!< [25..24] Select detection mode for IRQ12                                  */
5906             __IOM uint32_t MD13  : 2;  /*!< [27..26] Select detection mode for IRQ13                                  */
5907             __IOM uint32_t MDDRQ : 2;  /*!< [29..28] Select detection mode for DREQ of DMAC                           */
5908             uint32_t             : 2;
5909         } NS_PORTNF_MD_b;
5910     };
5911 } R_ICU_NS_Type;                       /*!< Size = 16 (0x10)                                                          */
5912 
5913 /* =========================================================================================================================== */
5914 /* ================                                           R_ELC                                           ================ */
5915 /* =========================================================================================================================== */
5916 
5917 /**
5918  * @brief Evnet Link Controller (R_ELC)
5919  */
5920 
5921 typedef struct                            /*!< (@ 0x80090010) R_ELC Structure                                            */
5922 {
5923     union
5924     {
5925         __IOM uint32_t ELC_SSEL[19];      /*!< (@ 0x00000000) ELC Event Source Select Register [0..18]                   */
5926 
5927         struct
5928         {
5929             __IOM uint32_t ELC_SEL0 : 10; /*!< [9..0] Set the number for ELC event source to be linked to the
5930                                            *   ELC destination.                                                          */
5931             __IOM uint32_t ELC_SEL1 : 10; /*!< [19..10] Set the number for ELC event source to be linked to
5932                                            *   the ELC destination.                                                      */
5933             __IOM uint32_t ELC_SEL2 : 10; /*!< [29..20] Set the number for ELC event source to be linked to
5934                                            *   the ELC destination.                                                      */
5935             uint32_t : 2;
5936         } ELC_SSEL_b[19];
5937     };
5938 } R_ELC_Type;                             /*!< Size = 76 (0x4c)                                                          */
5939 
5940 /* =========================================================================================================================== */
5941 /* ================                                           R_DMA                                           ================ */
5942 /* =========================================================================================================================== */
5943 
5944 /**
5945  * @brief DMAC Configuration (R_DMA)
5946  */
5947 
5948 typedef struct                         /*!< (@ 0x80090060) R_DMA Structure                                            */
5949 {
5950     __IM uint32_t RESERVED[3];
5951 
5952     union
5953     {
5954         __IOM uint32_t DMAC0_RSSEL[3];   /*!< (@ 0x0000000C) DMAC Unit 0 Resource Select Register [0..2]                */
5955 
5956         struct
5957         {
5958             __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n                                  */
5959             uint32_t                : 1;
5960             __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1                            */
5961             uint32_t                : 1;
5962             __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2                            */
5963             uint32_t                : 3;
5964         } DMAC0_RSSEL_b[3];
5965     };
5966     __IM uint32_t RESERVED1[3];
5967 
5968     union
5969     {
5970         __IOM uint32_t DMAC1_RSSEL[3];   /*!< (@ 0x00000024) DMAC Unit 1 Resource Select Register [0..2]                */
5971 
5972         struct
5973         {
5974             __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n                                  */
5975             uint32_t                : 1;
5976             __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1                            */
5977             uint32_t                : 1;
5978             __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2                            */
5979             uint32_t                : 3;
5980         } DMAC1_RSSEL_b[3];
5981     };
5982 } R_DMA_Type;                            /*!< Size = 48 (0x30)                                                          */
5983 
5984 /* =========================================================================================================================== */
5985 /* ================                                        R_PORT_NSR                                         ================ */
5986 /* =========================================================================================================================== */
5987 
5988 /**
5989  * @brief I/O Ports (Non safety region) (R_PORT_NSR)
5990  */
5991 
5992 typedef struct                         /*!< (@ 0x800A0000) R_PORT_NSR Structure                                       */
5993 {
5994     union
5995     {
5996         __IOM uint8_t P[25];           /*!< (@ 0x00000000) Port [0..24] Register                                      */
5997 
5998         struct
5999         {
6000             __IOM uint8_t POUT_0 : 1;  /*!< [0..0] Pm_n Output Data Store (n: bit position)                           */
6001             __IOM uint8_t POUT_1 : 1;  /*!< [1..1] Pm_n Output Data Store (n: bit position)                           */
6002             __IOM uint8_t POUT_2 : 1;  /*!< [2..2] Pm_n Output Data Store (n: bit position)                           */
6003             __IOM uint8_t POUT_3 : 1;  /*!< [3..3] Pm_n Output Data Store (n: bit position)                           */
6004             __IOM uint8_t POUT_4 : 1;  /*!< [4..4] Pm_n Output Data Store (n: bit position)                           */
6005             __IOM uint8_t POUT_5 : 1;  /*!< [5..5] Pm_n Output Data Store (n: bit position)                           */
6006             __IOM uint8_t POUT_6 : 1;  /*!< [6..6] Pm_n Output Data Store (n: bit position)                           */
6007             __IOM uint8_t POUT_7 : 1;  /*!< [7..7] Pm_n Output Data Store (n: bit position)                           */
6008         } P_b[25];
6009     };
6010     __IM uint8_t  RESERVED;
6011     __IM uint16_t RESERVED1;
6012     __IM uint32_t RESERVED2[121];
6013 
6014     union
6015     {
6016         __IOM uint16_t PM[25];         /*!< (@ 0x00000200) Port 0 Mode Register                                       */
6017 
6018         struct
6019         {
6020             __IOM uint16_t PM0 : 2;    /*!< [1..0] Pm_0 I/O Select                                                    */
6021             __IOM uint16_t PM1 : 2;    /*!< [3..2] Pm_1 I/O Select                                                    */
6022             __IOM uint16_t PM2 : 2;    /*!< [5..4] Pm_2 I/O Select                                                    */
6023             __IOM uint16_t PM3 : 2;    /*!< [7..6] Pm_3 I/O Select                                                    */
6024             __IOM uint16_t PM4 : 2;    /*!< [9..8] Pm_4 I/O Select                                                    */
6025             __IOM uint16_t PM5 : 2;    /*!< [11..10] Pm_5 I/O Select                                                  */
6026             __IOM uint16_t PM6 : 2;    /*!< [13..12] Pm_6 I/O Select                                                  */
6027             __IOM uint16_t PM7 : 2;    /*!< [15..14] Pm_7 I/O Select                                                  */
6028         } PM_b[25];
6029     };
6030     __IM uint16_t RESERVED3;
6031     __IM uint32_t RESERVED4[115];
6032 
6033     union
6034     {
6035         __IOM uint8_t PMC[25];         /*!< (@ 0x00000400) Port [0..24] Mode Control Register                         */
6036 
6037         struct
6038         {
6039             __IOM uint8_t PMC0 : 1;    /*!< [0..0] Pm_n Pin Mode Control (n: bit position)                            */
6040             __IOM uint8_t PMC1 : 1;    /*!< [1..1] Pm_n Pin Mode Control (n: bit position)                            */
6041             __IOM uint8_t PMC2 : 1;    /*!< [2..2] Pm_n Pin Mode Control (n: bit position)                            */
6042             __IOM uint8_t PMC3 : 1;    /*!< [3..3] Pm_n Pin Mode Control (n: bit position)                            */
6043             __IOM uint8_t PMC4 : 1;    /*!< [4..4] Pm_n Pin Mode Control (n: bit position)                            */
6044             __IOM uint8_t PMC5 : 1;    /*!< [5..5] Pm_n Pin Mode Control (n: bit position)                            */
6045             __IOM uint8_t PMC6 : 1;    /*!< [6..6] Pm_n Pin Mode Control (n: bit position)                            */
6046             __IOM uint8_t PMC7 : 1;    /*!< [7..7] Pm_n Pin Mode Control (n: bit position)                            */
6047         } PMC_b[25];
6048     };
6049     __IM uint8_t  RESERVED5;
6050     __IM uint16_t RESERVED6;
6051     __IM uint32_t RESERVED7[121];
6052 
6053     union
6054     {
6055         __IOM uint32_t PFC[25];        /*!< (@ 0x00000600) Port [0..24] Function Control Register                     */
6056 
6057         struct
6058         {
6059             __IOM uint32_t PFC0 : 4;   /*!< [3..0] Pm_0 Pin function Select                                           */
6060             __IOM uint32_t PFC1 : 4;   /*!< [7..4] Pm_1 Pin function Select                                           */
6061             __IOM uint32_t PFC2 : 4;   /*!< [11..8] Pm_2 Pin function Select                                          */
6062             __IOM uint32_t PFC3 : 4;   /*!< [15..12] Pm_3 Pin function Select                                         */
6063             __IOM uint32_t PFC4 : 4;   /*!< [19..16] Pm_4 Pin function Select                                         */
6064             __IOM uint32_t PFC5 : 4;   /*!< [23..20] Pm_5 Pin function Select                                         */
6065             __IOM uint32_t PFC6 : 4;   /*!< [27..24] Pm_6 Pin function Select                                         */
6066             __IOM uint32_t PFC7 : 4;   /*!< [31..28] Pm_7 Pin function Select                                         */
6067         } PFC_b[25];
6068     };
6069     __IM uint32_t RESERVED8[103];
6070 
6071     union
6072     {
6073         __IM uint8_t PIN[25];          /*!< (@ 0x00000800) Port [0..24] Input Register                                */
6074 
6075         struct
6076         {
6077             __IM uint8_t PIN0 : 1;     /*!< [0..0] Pm_n Pin Input (n: bit position)                                   */
6078             __IM uint8_t PIN1 : 1;     /*!< [1..1] Pm_n Pin Input (n: bit position)                                   */
6079             __IM uint8_t PIN2 : 1;     /*!< [2..2] Pm_n Pin Input (n: bit position)                                   */
6080             __IM uint8_t PIN3 : 1;     /*!< [3..3] Pm_n Pin Input (n: bit position)                                   */
6081             __IM uint8_t PIN4 : 1;     /*!< [4..4] Pm_n Pin Input (n: bit position)                                   */
6082             __IM uint8_t PIN5 : 1;     /*!< [5..5] Pm_n Pin Input (n: bit position)                                   */
6083             __IM uint8_t PIN6 : 1;     /*!< [6..6] Pm_n Pin Input (n: bit position)                                   */
6084             __IM uint8_t PIN7 : 1;     /*!< [7..7] Pm_n Pin Input (n: bit position)                                   */
6085         } PIN_b[25];
6086     };
6087     __IM uint8_t            RESERVED9;
6088     __IM uint16_t           RESERVED10;
6089     __IM uint32_t           RESERVED11[121];
6090     __IOM R_PORT_DRCTL_Type DRCTL[25]; /*!< (@ 0x00000A00) I/O Buffer [0..24] Function Switching Register             */
6091     __IM uint32_t           RESERVED12[206];
6092 
6093     union
6094     {
6095         __IOM uint8_t ELC_PGR[2];      /*!< (@ 0x00000E00) ELC Port Group Setting Register [0..1]                     */
6096 
6097         struct
6098         {
6099             __IOM uint8_t PG0 : 1;     /*!< [0..0] Port Group Setting                                                 */
6100             __IOM uint8_t PG1 : 1;     /*!< [1..1] Port Group Setting                                                 */
6101             __IOM uint8_t PG2 : 1;     /*!< [2..2] Port Group Setting                                                 */
6102             __IOM uint8_t PG3 : 1;     /*!< [3..3] Port Group Setting                                                 */
6103             __IOM uint8_t PG4 : 1;     /*!< [4..4] Port Group Setting                                                 */
6104             __IOM uint8_t PG5 : 1;     /*!< [5..5] Port Group Setting                                                 */
6105             __IOM uint8_t PG6 : 1;     /*!< [6..6] Port Group Setting                                                 */
6106             __IOM uint8_t PG7 : 1;     /*!< [7..7] Port Group Setting                                                 */
6107         } ELC_PGR_b[2];
6108     };
6109 
6110     union
6111     {
6112         __IOM uint8_t ELC_PGC[2];               /*!< (@ 0x00000E02) ELC Port Group Control Register [0..1]                     */
6113 
6114         struct
6115         {
6116             __IOM uint8_t PGCI   : 2;           /*!< [1..0] Event Output Edge Select                                           */
6117             __IOM uint8_t PGCOVE : 1;           /*!< [2..2] PDBF Overwrite                                                     */
6118             uint8_t              : 1;
6119             __IOM uint8_t PGCO   : 3;           /*!< [6..4] Port Group Operation Select                                        */
6120             uint8_t              : 1;
6121         } ELC_PGC_b[2];
6122     };
6123     __IOM R_PORT_NSR_ELC_PDBF_Type ELC_PDBF[2]; /*!< (@ 0x00000E04) ELC Port Buffer Register [0..1]                            */
6124 
6125     union
6126     {
6127         __IOM uint8_t ELC_PEL[4];               /*!< (@ 0x00000E0C) ELC Port Setting Register [0..3]                           */
6128 
6129         struct
6130         {
6131             __IOM uint8_t PSB : 3;              /*!< [2..0] Bit Number Specification                                           */
6132             __IOM uint8_t PSP : 2;              /*!< [4..3] Port Number Specification                                          */
6133             __IOM uint8_t PSM : 2;              /*!< [6..5] Event Link Specification                                           */
6134             uint8_t           : 1;
6135         } ELC_PEL_b[4];
6136     };
6137 
6138     union
6139     {
6140         __IOM uint8_t ELC_DPTC;        /*!< (@ 0x00000E10) ELC Edge Detection Control Register                        */
6141 
6142         struct
6143         {
6144             __IOM uint8_t PTC0 : 1;    /*!< [0..0] Single Input Port n Edge Detection                                 */
6145             __IOM uint8_t PTC1 : 1;    /*!< [1..1] Single Input Port n Edge Detection                                 */
6146             __IOM uint8_t PTC2 : 1;    /*!< [2..2] Single Input Port n Edge Detection                                 */
6147             __IOM uint8_t PTC3 : 1;    /*!< [3..3] Single Input Port n Edge Detection                                 */
6148             uint8_t            : 4;
6149         } ELC_DPTC_b;
6150     };
6151 
6152     union
6153     {
6154         __IOM uint8_t ELC_ELSR2;       /*!< (@ 0x00000E11) ELC Port Event Control Register                            */
6155 
6156         struct
6157         {
6158             uint8_t            : 2;
6159             __IOM uint8_t PEG1 : 1;    /*!< [2..2] ELC Port Buffer Register (ELC_PDBFn) write access control.
6160                                         *   When set to 1, writing to the ELC_PDBFn register via Internal
6161                                         *   peripheral bus is disabled, preventing overwriting.                       */
6162             __IOM uint8_t PEG2 : 1;    /*!< [3..3] ELC Port Buffer Register (ELC_PDBFn) write access control.
6163                                         *   When set to 1, writing to the ELC_PDBFn register via Internal
6164                                         *   peripheral bus is disabled, preventing overwriting.                       */
6165             __IOM uint8_t PES0 : 1;    /*!< [4..4] Single Port n Event Link Function Enable                           */
6166             __IOM uint8_t PES1 : 1;    /*!< [5..5] Single Port n Event Link Function Enable                           */
6167             __IOM uint8_t PES2 : 1;    /*!< [6..6] Single Port n Event Link Function Enable                           */
6168             __IOM uint8_t PES3 : 1;    /*!< [7..7] Single Port n Event Link Function Enable                           */
6169         } ELC_ELSR2_b;
6170     };
6171     __IM uint16_t RESERVED13;
6172 } R_PORT_COMMON_Type;                  /*!< Size = 3604 (0xe14)                                                       */
6173 
6174 /* =========================================================================================================================== */
6175 /* ================                                          R_GMAC                                           ================ */
6176 /* =========================================================================================================================== */
6177 
6178 /**
6179  * @brief Ethernet MAC (R_GMAC)
6180  */
6181 
6182 typedef struct                            /*!< (@ 0x80100000) R_GMAC Structure                                           */
6183 {
6184     union
6185     {
6186         __IOM uint32_t MAC_Configuration; /*!< (@ 0x00000000) MAC Configuration Register                                 */
6187 
6188         struct
6189         {
6190             __IOM uint32_t PRELEN : 2;    /*!< [1..0] Preamble Length for Transmit Frames                                */
6191             __IOM uint32_t RE     : 1;    /*!< [2..2] Receiver Enable                                                    */
6192             __IOM uint32_t TE     : 1;    /*!< [3..3] Transmitter Enable                                                 */
6193             __IOM uint32_t DC     : 1;    /*!< [4..4] Deferral Check                                                     */
6194             __IOM uint32_t BL     : 2;    /*!< [6..5] Back-Off Limit                                                     */
6195             __IOM uint32_t ACS    : 1;    /*!< [7..7] Automatic Pad or CRC Stripping                                     */
6196             uint32_t              : 1;
6197             __IOM uint32_t DR     : 1;    /*!< [9..9] Disable Retry                                                      */
6198             __IOM uint32_t IPC    : 1;    /*!< [10..10] Checksum Offload                                                 */
6199             __IOM uint32_t DM     : 1;    /*!< [11..11] Duplex Mode                                                      */
6200             __IOM uint32_t LM     : 1;    /*!< [12..12] Loopback Mode                                                    */
6201             __IOM uint32_t DO     : 1;    /*!< [13..13] Disable Receive Own                                              */
6202             __IOM uint32_t FES    : 1;    /*!< [14..14] Speed                                                            */
6203             __IOM uint32_t PS     : 1;    /*!< [15..15] Port Select                                                      */
6204             __IOM uint32_t DCRS   : 1;    /*!< [16..16] Disable Carrier Sense During Transmission                        */
6205             __IOM uint32_t IFG    : 3;    /*!< [19..17] Inter-Frame Gap                                                  */
6206             __IOM uint32_t JE     : 1;    /*!< [20..20] Jumbo Frame Enable                                               */
6207             __IOM uint32_t BE     : 1;    /*!< [21..21] Frame Burst Enable                                               */
6208             __IOM uint32_t JD     : 1;    /*!< [22..22] Jabber Disable                                                   */
6209             __IOM uint32_t WD     : 1;    /*!< [23..23] Watchdog Disable                                                 */
6210             uint32_t              : 1;
6211             __IOM uint32_t CST    : 1;    /*!< [25..25] CRC Stripping for Type Frames                                    */
6212             uint32_t              : 1;
6213             __IOM uint32_t TWOKPE : 1;    /*!< [27..27] IEEE 802.3 as Support for 2 K Packets                            */
6214             uint32_t              : 4;
6215         } MAC_Configuration_b;
6216     };
6217 
6218     union
6219     {
6220         __IOM uint32_t MAC_Frame_Filter; /*!< (@ 0x00000004) MAC Frame Filter Register                                  */
6221 
6222         struct
6223         {
6224             __IOM uint32_t PR   : 1;     /*!< [0..0] Promiscuous Mode                                                   */
6225             __IOM uint32_t HUC  : 1;     /*!< [1..1] Hash Unicast                                                       */
6226             __IOM uint32_t HMC  : 1;     /*!< [2..2] Hash Multicast                                                     */
6227             __IOM uint32_t DAIF : 1;     /*!< [3..3] DA Inverse Filtering                                               */
6228             __IOM uint32_t PM   : 1;     /*!< [4..4] Pass All Multicast                                                 */
6229             __IOM uint32_t DBF  : 1;     /*!< [5..5] Disable Broadcast Frames                                           */
6230             __IOM uint32_t PCF  : 2;     /*!< [7..6] Pass Control Frames                                                */
6231             __IOM uint32_t SAIF : 1;     /*!< [8..8] SA Inverse Filtering                                               */
6232             __IOM uint32_t SAF  : 1;     /*!< [9..9] Source Address Filter Enable                                       */
6233             __IOM uint32_t HPF  : 1;     /*!< [10..10] Hash or Perfect Filter                                           */
6234             uint32_t            : 5;
6235             __IOM uint32_t VTFE : 1;     /*!< [16..16] VLAN Tag Filter Enable                                           */
6236             uint32_t            : 14;
6237             __IOM uint32_t RA   : 1;     /*!< [31..31] Receive All                                                      */
6238         } MAC_Frame_Filter_b;
6239     };
6240     __IM uint32_t RESERVED[2];
6241 
6242     union
6243     {
6244         __IOM uint32_t GMII_Address;   /*!< (@ 0x00000010) GMII Address Register                                      */
6245 
6246         struct
6247         {
6248             __IOM uint32_t GB : 1;     /*!< [0..0] GMII Busy                                                          */
6249             __IOM uint32_t GW : 1;     /*!< [1..1] GMII Write                                                         */
6250             __IOM uint32_t CR : 4;     /*!< [5..2] CSR Clock Range                                                    */
6251             __IOM uint32_t GR : 5;     /*!< [10..6] GMII Register                                                     */
6252             __IOM uint32_t PA : 5;     /*!< [15..11] Physical Layer Address                                           */
6253             uint32_t          : 16;
6254         } GMII_Address_b;
6255     };
6256 
6257     union
6258     {
6259         __IOM uint32_t GMII_Data;      /*!< (@ 0x00000014) GMII Data Register                                         */
6260 
6261         struct
6262         {
6263             __IOM uint32_t GD : 16;    /*!< [15..0] GMII Data                                                         */
6264             uint32_t          : 16;
6265         } GMII_Data_b;
6266     };
6267 
6268     union
6269     {
6270         __IOM uint32_t Flow_Control;     /*!< (@ 0x00000018) Flow Control Register                                      */
6271 
6272         struct
6273         {
6274             __IOM uint32_t FCA_BPA : 1;  /*!< [0..0] Flow Control Busy or Backpressure Activate                         */
6275             __IOM uint32_t TFE     : 1;  /*!< [1..1] Transmit Flow Control Enable                                       */
6276             __IOM uint32_t RFE     : 1;  /*!< [2..2] Receive Flow Control Enable                                        */
6277             __IOM uint32_t UP      : 1;  /*!< [3..3] Unicast Pause Frame Detect                                         */
6278             __IOM uint32_t PLT     : 2;  /*!< [5..4] Pause Low Threshold                                                */
6279             uint32_t               : 1;
6280             __IOM uint32_t DZPQ    : 1;  /*!< [7..7] Disable Zero-Quanta Pause                                          */
6281             uint32_t               : 8;
6282             __IOM uint32_t PT      : 16; /*!< [31..16] Pause Time                                                       */
6283         } Flow_Control_b;
6284     };
6285 
6286     union
6287     {
6288         __IOM uint32_t VLAN_Tag;       /*!< (@ 0x0000001C) VLAN Tag Register                                          */
6289 
6290         struct
6291         {
6292             __IOM uint32_t VL   : 16;  /*!< [15..0] VLAN Tag Identifier for Receive Frames                            */
6293             __IOM uint32_t ETV  : 1;   /*!< [16..16] Enable 12-Bit VLAN Tag Comparison                                */
6294             __IOM uint32_t VTIM : 1;   /*!< [17..17] VLAN Tag Inverse Match Enable                                    */
6295             __IOM uint32_t ESVL : 1;   /*!< [18..18] Enable S-VLAN                                                    */
6296             __IOM uint32_t VTHM : 1;   /*!< [19..19] VLAN Tag Hash Table Match Enable                                 */
6297             uint32_t            : 12;
6298         } VLAN_Tag_b;
6299     };
6300 
6301     union
6302     {
6303         __IM uint32_t Version;         /*!< (@ 0x00000020) Version Register                                           */
6304 
6305         struct
6306         {
6307             __IM uint32_t VER : 16;    /*!< [15..0] Version (GMAC: 0x3037)                                            */
6308             uint32_t          : 16;
6309         } Version_b;
6310     };
6311 
6312     union
6313     {
6314         __IM uint32_t Debug;             /*!< (@ 0x00000024) Debug Register                                             */
6315 
6316         struct
6317         {
6318             __IM uint32_t RPESTS    : 1; /*!< [0..0] GMAC GMII or MII Receive Protocol Engine Status                    */
6319             __IM uint32_t RFCFCSTS  : 2; /*!< [2..1] GMAC Receive Frame Controller FIFO Status                          */
6320             uint32_t                : 1;
6321             __IM uint32_t RWCSTS    : 1; /*!< [4..4] MTL RX FIFO Write Controller Active Status                         */
6322             __IM uint32_t RRCSTS    : 2; /*!< [6..5] MTL RX FIFO Read Controller State                                  */
6323             uint32_t                : 1;
6324             __IM uint32_t RXFSTS    : 2; /*!< [9..8] MTL RX FIFO Fill-level Status                                      */
6325             uint32_t                : 6;
6326             __IM uint32_t TPESTS    : 1; /*!< [16..16] GMAC GMII or MII Transmit Protocol Engine Status                 */
6327             __IM uint32_t TFCSTS    : 2; /*!< [18..17] GMAC Transmit Frame Controller Status                            */
6328             __IM uint32_t TXPAUSED  : 1; /*!< [19..19] GMAC transmitter in PAUSE                                        */
6329             __IM uint32_t TRCSTS    : 2; /*!< [21..20] MTL TX FIFO Read Controller Status                               */
6330             __IM uint32_t TWCSTS    : 1; /*!< [22..22] MTL TX FIFO Write Controller Active Status                       */
6331             uint32_t                : 1;
6332             __IM uint32_t TXFSTS    : 1; /*!< [24..24] MTL TX FIFO Not Empty Status                                     */
6333             __IM uint32_t TXSTSFSTS : 1; /*!< [25..25] MTL TX Status FIFO Full Status                                   */
6334             uint32_t                : 6;
6335         } Debug_b;
6336     };
6337 
6338     union
6339     {
6340         __IOM uint32_t Remote_Wake_Up_Frame_Filter; /*!< (@ 0x00000028) Remote Wake-Up Frame Filter Register                       */
6341 
6342         struct
6343         {
6344             __IOM uint32_t WKUPFRMFTR : 32;         /*!< [31..0] Remote Wake-Up Frame Filter                                       */
6345         } Remote_Wake_Up_Frame_Filter_b;
6346     };
6347 
6348     union
6349     {
6350         __IOM uint32_t PMT_Control_Status; /*!< (@ 0x0000002C) PMT Control and Status Register                            */
6351 
6352         struct
6353         {
6354             __IOM uint32_t PWRDWN     : 1; /*!< [0..0] Power Down                                                         */
6355             __IOM uint32_t MGKPKTEN   : 1; /*!< [1..1] Magic Packet Enable                                                */
6356             __IOM uint32_t RWKPKTEN   : 1; /*!< [2..2] Wake-Up Frame Enable                                               */
6357             uint32_t                  : 2;
6358             __IM uint32_t MGKPRCVD    : 1; /*!< [5..5] Magic Packet Received                                              */
6359             __IM uint32_t RWKPRCVD    : 1; /*!< [6..6] Wake-Up Frame Received                                             */
6360             uint32_t                  : 2;
6361             __IOM uint32_t GLBLUCAST  : 1; /*!< [9..9] Global Unicast                                                     */
6362             uint32_t                  : 14;
6363             __IM uint32_t RWKPTR      : 3; /*!< [26..24] Remote Wake-Up FIFO Pointer                                      */
6364             uint32_t                  : 4;
6365             __IOM uint32_t RWKFILTRST : 1; /*!< [31..31] Wake-Up Frame Filter Register Pointer Reset                      */
6366         } PMT_Control_Status_b;
6367     };
6368 
6369     union
6370     {
6371         __IOM uint32_t LPI_Control_Status; /*!< (@ 0x00000030) LPI Control and Status Register                            */
6372 
6373         struct
6374         {
6375             __IM uint32_t TLPIEN  : 1;     /*!< [0..0] Transmit LPI Entry                                                 */
6376             __IM uint32_t TLPIEX  : 1;     /*!< [1..1] Transmit LPI Exit                                                  */
6377             __IM uint32_t RLPIEN  : 1;     /*!< [2..2] Receive LPI Entry                                                  */
6378             __IM uint32_t RLPIEX  : 1;     /*!< [3..3] Receive LPI Exit                                                   */
6379             uint32_t              : 4;
6380             __IM uint32_t TLPIST  : 1;     /*!< [8..8] Transmit LPI State                                                 */
6381             __IM uint32_t RLPIST  : 1;     /*!< [9..9] Receive LPI State                                                  */
6382             uint32_t              : 6;
6383             __IOM uint32_t LPIEN  : 1;     /*!< [16..16] LPI Enable                                                       */
6384             __IOM uint32_t PLS    : 1;     /*!< [17..17] PHY Link Status                                                  */
6385             uint32_t              : 1;
6386             __IOM uint32_t LPITXA : 1;     /*!< [19..19] LPI TX Automate                                                  */
6387             uint32_t              : 12;
6388         } LPI_Control_Status_b;
6389     };
6390 
6391     union
6392     {
6393         __IOM uint32_t LPI_Timers_Control; /*!< (@ 0x00000034) LPI Timers Control Register                                */
6394 
6395         struct
6396         {
6397             __IOM uint32_t TWT : 16;       /*!< [15..0] LPI TW Timer                                                      */
6398             __IOM uint32_t LST : 10;       /*!< [25..16] LPI LS Timer                                                     */
6399             uint32_t           : 6;
6400         } LPI_Timers_Control_b;
6401     };
6402 
6403     union
6404     {
6405         __IM uint32_t Interrupt_Status; /*!< (@ 0x00000038) Interrupt Status Register                                  */
6406 
6407         struct
6408         {
6409             uint32_t                : 3;
6410             __IM uint32_t PMTIS     : 1; /*!< [3..3] PMT Interrupt Status                                               */
6411             __IM uint32_t MMCIS     : 1; /*!< [4..4] MMC Interrupt Status                                               */
6412             __IM uint32_t MMCRXIS   : 1; /*!< [5..5] MMC Receive Interrupt Status                                       */
6413             __IM uint32_t MMCTXIS   : 1; /*!< [6..6] MMC Transmit Interrupt Status                                      */
6414             __IM uint32_t MMCRXIPIS : 1; /*!< [7..7] MMC Receive Checksum Offload Interrupt Status                      */
6415             uint32_t                : 1;
6416             __IM uint32_t TSIS      : 1; /*!< [9..9] Timestamp Interrupt Status                                         */
6417             __IM uint32_t LPIIS     : 1; /*!< [10..10] LPI Interrupt Status                                             */
6418             uint32_t                : 21;
6419         } Interrupt_Status_b;
6420     };
6421 
6422     union
6423     {
6424         __IOM uint32_t Interrupt_Mask; /*!< (@ 0x0000003C) Interrupt Mask Register                                    */
6425 
6426         struct
6427         {
6428             uint32_t             : 3;
6429             __IOM uint32_t PMTIM : 1;  /*!< [3..3] PMT Interrupt Mask                                                 */
6430             uint32_t             : 5;
6431             __IOM uint32_t TSIM  : 1;  /*!< [9..9] Timestamp Interrupt Mask                                           */
6432             __IOM uint32_t LPIIM : 1;  /*!< [10..10] LPI Interrupt Mask                                               */
6433             uint32_t             : 21;
6434         } Interrupt_Mask_b;
6435     };
6436 
6437     union
6438     {
6439         __IOM uint32_t MAR0_H;          /*!< (@ 0x00000040) MAC Address 0 High Register                                */
6440 
6441         struct
6442         {
6443             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address0[47:32]                                               */
6444             uint32_t              : 15;
6445             __IM uint32_t AE      : 1;  /*!< [31..31] Address Enable                                                   */
6446         } MAR0_H_b;
6447     };
6448 
6449     union
6450     {
6451         __IOM uint32_t MAR0_L;          /*!< (@ 0x00000044) MAC Address 0 Low Register                                 */
6452 
6453         struct
6454         {
6455             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address0[31:0]                                                */
6456         } MAR0_L_b;
6457     };
6458 
6459     union
6460     {
6461         __IOM uint32_t MAR1_H;          /*!< (@ 0x00000048) MAC ADDRESS High Register                                  */
6462 
6463         struct
6464         {
6465             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6466             uint32_t              : 8;
6467             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6468             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6469             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6470         } MAR1_H_b;
6471     };
6472 
6473     union
6474     {
6475         __IOM uint32_t MAR1_L;          /*!< (@ 0x0000004C) MAC ADDRESS Low Register                                   */
6476 
6477         struct
6478         {
6479             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6480         } MAR1_L_b;
6481     };
6482 
6483     union
6484     {
6485         __IOM uint32_t MAR2_H;          /*!< (@ 0x00000050) MAC ADDRESS High Register                                  */
6486 
6487         struct
6488         {
6489             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6490             uint32_t              : 8;
6491             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6492             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6493             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6494         } MAR2_H_b;
6495     };
6496 
6497     union
6498     {
6499         __IOM uint32_t MAR2_L;          /*!< (@ 0x00000054) MAC ADDRESS Low Register                                   */
6500 
6501         struct
6502         {
6503             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6504         } MAR2_L_b;
6505     };
6506 
6507     union
6508     {
6509         __IOM uint32_t MAR3_H;          /*!< (@ 0x00000058) MAC ADDRESS High Register                                  */
6510 
6511         struct
6512         {
6513             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6514             uint32_t              : 8;
6515             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6516             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6517             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6518         } MAR3_H_b;
6519     };
6520 
6521     union
6522     {
6523         __IOM uint32_t MAR3_L;          /*!< (@ 0x0000005C) MAC ADDRESS Low Register                                   */
6524 
6525         struct
6526         {
6527             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6528         } MAR3_L_b;
6529     };
6530 
6531     union
6532     {
6533         __IOM uint32_t MAR4_H;          /*!< (@ 0x00000060) MAC ADDRESS High Register                                  */
6534 
6535         struct
6536         {
6537             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6538             uint32_t              : 8;
6539             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6540             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6541             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6542         } MAR4_H_b;
6543     };
6544 
6545     union
6546     {
6547         __IOM uint32_t MAR4_L;          /*!< (@ 0x00000064) MAC ADDRESS Low Register                                   */
6548 
6549         struct
6550         {
6551             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6552         } MAR4_L_b;
6553     };
6554 
6555     union
6556     {
6557         __IOM uint32_t MAR5_H;          /*!< (@ 0x00000068) MAC ADDRESS High Register                                  */
6558 
6559         struct
6560         {
6561             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6562             uint32_t              : 8;
6563             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6564             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6565             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6566         } MAR5_H_b;
6567     };
6568 
6569     union
6570     {
6571         __IOM uint32_t MAR5_L;          /*!< (@ 0x0000006C) MAC ADDRESS Low Register                                   */
6572 
6573         struct
6574         {
6575             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6576         } MAR5_L_b;
6577     };
6578 
6579     union
6580     {
6581         __IOM uint32_t MAR6_H;          /*!< (@ 0x00000070) MAC ADDRESS High Register                                  */
6582 
6583         struct
6584         {
6585             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6586             uint32_t              : 8;
6587             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6588             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6589             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6590         } MAR6_H_b;
6591     };
6592 
6593     union
6594     {
6595         __IOM uint32_t MAR6_L;          /*!< (@ 0x00000074) MAC ADDRESS Low Register                                   */
6596 
6597         struct
6598         {
6599             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6600         } MAR6_L_b;
6601     };
6602 
6603     union
6604     {
6605         __IOM uint32_t MAR7_H;          /*!< (@ 0x00000078) MAC ADDRESS High Register                                  */
6606 
6607         struct
6608         {
6609             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6610             uint32_t              : 8;
6611             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6612             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6613             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6614         } MAR7_H_b;
6615     };
6616 
6617     union
6618     {
6619         __IOM uint32_t MAR7_L;          /*!< (@ 0x0000007C) MAC ADDRESS Low Register                                   */
6620 
6621         struct
6622         {
6623             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6624         } MAR7_L_b;
6625     };
6626 
6627     union
6628     {
6629         __IOM uint32_t MAR8_H;          /*!< (@ 0x00000080) MAC ADDRESS High Register                                  */
6630 
6631         struct
6632         {
6633             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6634             uint32_t              : 8;
6635             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6636             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6637             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6638         } MAR8_H_b;
6639     };
6640 
6641     union
6642     {
6643         __IOM uint32_t MAR8_L;          /*!< (@ 0x00000084) MAC ADDRESS Low Register                                   */
6644 
6645         struct
6646         {
6647             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6648         } MAR8_L_b;
6649     };
6650 
6651     union
6652     {
6653         __IOM uint32_t MAR9_H;          /*!< (@ 0x00000088) MAC ADDRESS High Register                                  */
6654 
6655         struct
6656         {
6657             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6658             uint32_t              : 8;
6659             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6660             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6661             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6662         } MAR9_H_b;
6663     };
6664 
6665     union
6666     {
6667         __IOM uint32_t MAR9_L;          /*!< (@ 0x0000008C) MAC ADDRESS Low Register                                   */
6668 
6669         struct
6670         {
6671             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6672         } MAR9_L_b;
6673     };
6674 
6675     union
6676     {
6677         __IOM uint32_t MAR10_H;         /*!< (@ 0x00000090) MAC ADDRESS High Register                                  */
6678 
6679         struct
6680         {
6681             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6682             uint32_t              : 8;
6683             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6684             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6685             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6686         } MAR10_H_b;
6687     };
6688 
6689     union
6690     {
6691         __IOM uint32_t MAR10_L;         /*!< (@ 0x00000094) MAC ADDRESS Low Register                                   */
6692 
6693         struct
6694         {
6695             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6696         } MAR10_L_b;
6697     };
6698 
6699     union
6700     {
6701         __IOM uint32_t MAR11_H;         /*!< (@ 0x00000098) MAC ADDRESS High Register                                  */
6702 
6703         struct
6704         {
6705             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6706             uint32_t              : 8;
6707             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6708             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6709             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6710         } MAR11_H_b;
6711     };
6712 
6713     union
6714     {
6715         __IOM uint32_t MAR11_L;         /*!< (@ 0x0000009C) MAC ADDRESS Low Register                                   */
6716 
6717         struct
6718         {
6719             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6720         } MAR11_L_b;
6721     };
6722 
6723     union
6724     {
6725         __IOM uint32_t MAR12_H;         /*!< (@ 0x000000A0) MAC ADDRESS High Register                                  */
6726 
6727         struct
6728         {
6729             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6730             uint32_t              : 8;
6731             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6732             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6733             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6734         } MAR12_H_b;
6735     };
6736 
6737     union
6738     {
6739         __IOM uint32_t MAR12_L;         /*!< (@ 0x000000A4) MAC ADDRESS Low Register                                   */
6740 
6741         struct
6742         {
6743             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6744         } MAR12_L_b;
6745     };
6746 
6747     union
6748     {
6749         __IOM uint32_t MAR13_H;         /*!< (@ 0x000000A8) MAC ADDRESS High Register                                  */
6750 
6751         struct
6752         {
6753             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6754             uint32_t              : 8;
6755             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6756             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6757             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6758         } MAR13_H_b;
6759     };
6760 
6761     union
6762     {
6763         __IOM uint32_t MAR13_L;         /*!< (@ 0x000000AC) MAC ADDRESS Low Register                                   */
6764 
6765         struct
6766         {
6767             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6768         } MAR13_L_b;
6769     };
6770 
6771     union
6772     {
6773         __IOM uint32_t MAR14_H;         /*!< (@ 0x000000B0) MAC ADDRESS High Register                                  */
6774 
6775         struct
6776         {
6777             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6778             uint32_t              : 8;
6779             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6780             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6781             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6782         } MAR14_H_b;
6783     };
6784 
6785     union
6786     {
6787         __IOM uint32_t MAR14_L;         /*!< (@ 0x000000B4) MAC ADDRESS Low Register                                   */
6788 
6789         struct
6790         {
6791             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6792         } MAR14_L_b;
6793     };
6794 
6795     union
6796     {
6797         __IOM uint32_t MAR15_H;         /*!< (@ 0x000000B8) MAC ADDRESS High Register                                  */
6798 
6799         struct
6800         {
6801             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
6802             uint32_t              : 8;
6803             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
6804             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
6805             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
6806         } MAR15_H_b;
6807     };
6808 
6809     union
6810     {
6811         __IOM uint32_t MAR15_L;         /*!< (@ 0x000000BC) MAC ADDRESS Low Register                                   */
6812 
6813         struct
6814         {
6815             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
6816         } MAR15_L_b;
6817     };
6818     __IM uint32_t RESERVED1[7];
6819 
6820     union
6821     {
6822         __IOM uint32_t WDog_Timeout;   /*!< (@ 0x000000DC) Watchdog Timeout Register                                  */
6823 
6824         struct
6825         {
6826             __IOM uint32_t WTO : 14;   /*!< [13..0] Watchdog Timeout                                                  */
6827             uint32_t           : 2;
6828             __IOM uint32_t PWE : 1;    /*!< [16..16] Programmable Watchdog Enable                                     */
6829             uint32_t           : 15;
6830         } WDog_Timeout_b;
6831     };
6832     __IM uint32_t RESERVED2[8];
6833 
6834     union
6835     {
6836         __IOM uint32_t MMC_Control;        /*!< (@ 0x00000100) MMC Control Register                                       */
6837 
6838         struct
6839         {
6840             __IOM uint32_t CNTRST     : 1; /*!< [0..0] Counters Reset                                                     */
6841             __IOM uint32_t CNTSTOPRO  : 1; /*!< [1..1] Counters Stop Rollover                                             */
6842             __IOM uint32_t RSTONRD    : 1; /*!< [2..2] Reset on Read                                                      */
6843             __IOM uint32_t CNTFREEZ   : 1; /*!< [3..3] MMC Counter Freeze                                                 */
6844             __IOM uint32_t CNTPRST    : 1; /*!< [4..4] Counters Preset                                                    */
6845             __IOM uint32_t CNTPRSTLVL : 1; /*!< [5..5] Full-Half Preset                                                   */
6846             uint32_t                  : 2;
6847             __IOM uint32_t UCDBC      : 1; /*!< [8..8] Update MMC Counters for Dropped Broadcast Frames                   */
6848             uint32_t                  : 23;
6849         } MMC_Control_b;
6850     };
6851 
6852     union
6853     {
6854         __IM uint32_t MMC_Receive_Interrupt;      /*!< (@ 0x00000104) MMC Receive Interrupt Register                             */
6855 
6856         struct
6857         {
6858             __IM uint32_t RXGBFRMIS    : 1;       /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Status                */
6859             __IM uint32_t RXGBOCTIS    : 1;       /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Status                */
6860             __IM uint32_t RXGOCTIS     : 1;       /*!< [2..2] MMC Receive Good Octet Counter Interrupt Status                    */
6861             __IM uint32_t RXBCGFIS     : 1;       /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Status          */
6862             __IM uint32_t RXMCGFIS     : 1;       /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Status          */
6863             __IM uint32_t RXCRCERFIS   : 1;       /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Status               */
6864             __IM uint32_t RXALGNERFIS  : 1;       /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Status         */
6865             __IM uint32_t RXRUNTFIS    : 1;       /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Status                    */
6866             __IM uint32_t RXJABERFIS   : 1;       /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Status            */
6867             __IM uint32_t RXUSIZEGFIS  : 1;       /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Status          */
6868             __IM uint32_t RXOSIZEGFIS  : 1;       /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Status         */
6869             __IM uint32_t RX64OCTGBFIS : 1;       /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt
6870                                                    *   Status                                                                    */
6871             __IM uint32_t RX65T127OCTGBFIS : 1;   /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter
6872                                                    *   Interrupt Status                                                          */
6873             __IM uint32_t RX128T255OCTGBFIS : 1;  /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter
6874                                                    *   Interrupt Status                                                          */
6875             __IM uint32_t RX256T511OCTGBFIS : 1;  /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter
6876                                                    *   Interrupt Status                                                          */
6877             __IM uint32_t RX512T1023OCTGBFIS : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter
6878                                                    *   Interrupt Status                                                          */
6879             __IM uint32_t RX1024TMAXOCTGBFIS : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter
6880                                                    *   Interrupt Status                                                          */
6881             __IM uint32_t RXUCGFIS    : 1;        /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Status          */
6882             __IM uint32_t RXLENERFIS  : 1;        /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Status          */
6883             __IM uint32_t RXORANGEFIS : 1;        /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt
6884                                                    *   Status                                                                    */
6885             __IM uint32_t RXPAUSFIS   : 1;        /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Status                 */
6886             __IM uint32_t RXFOVFIS    : 1;        /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Status         */
6887             __IM uint32_t RXVLANGBFIS : 1;        /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Status         */
6888             __IM uint32_t RXWDOGFIS   : 1;        /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt
6889                                                    *   Status                                                                    */
6890             __IM uint32_t RXRCVERRFIS : 1;        /*!< [24..24] MMC Receive Error Frame Counter Interrupt Status                 */
6891             __IM uint32_t RXCTRLFIS   : 1;        /*!< [25..25] MMC Receive Control Frame Counter Interrupt Status               */
6892             uint32_t                  : 6;
6893         } MMC_Receive_Interrupt_b;
6894     };
6895 
6896     union
6897     {
6898         __IM uint32_t MMC_Transmit_Interrupt;     /*!< (@ 0x00000108) MMC Transmit Interrupt Register                            */
6899 
6900         struct
6901         {
6902             __IM uint32_t TXGBOCTIS    : 1;       /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Status               */
6903             __IM uint32_t TXGBFRMIS    : 1;       /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Status               */
6904             __IM uint32_t TXBCGFIS     : 1;       /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Status         */
6905             __IM uint32_t TXMCGFIS     : 1;       /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Status         */
6906             __IM uint32_t TX64OCTGBFIS : 1;       /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt
6907                                                    *   Status                                                                    */
6908             __IM uint32_t TX65T127OCTGBFIS : 1;   /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt
6909                                                    *   Status                                                                    */
6910             __IM uint32_t TX128T255OCTGBFIS : 1;  /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter
6911                                                    *   Interrupt Status                                                          */
6912             __IM uint32_t TX256T511OCTGBFIS : 1;  /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter
6913                                                    *   Interrupt Status                                                          */
6914             __IM uint32_t TX512T1023OCTGBFIS : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter
6915                                                    *   Interrupt Status                                                          */
6916             __IM uint32_t TX1024TMAXOCTGBFIS : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter
6917                                                    *   Interrupt Status                                                          */
6918             __IM uint32_t TXUCGBFIS : 1;          /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt
6919                                                    *   Status                                                                    */
6920             __IM uint32_t TXMCGBFIS : 1;          /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt
6921                                                    *   Status                                                                    */
6922             __IM uint32_t TXBCGBFIS : 1;          /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt
6923                                                    *   Status                                                                    */
6924             __IM uint32_t TXUFLOWERFIS : 1;       /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt
6925                                                    *   Status                                                                    */
6926             __IM uint32_t TXSCOLGFIS : 1;         /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt
6927                                                    *   Status                                                                    */
6928             __IM uint32_t TXMCOLGFIS : 1;         /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter
6929                                                    *   Interrupt Status                                                          */
6930             __IM uint32_t TXDEFFIS    : 1;        /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Status             */
6931             __IM uint32_t TXLATCOLFIS : 1;        /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt
6932                                                    *   Status                                                                    */
6933             __IM uint32_t TXEXCOLFIS : 1;         /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt
6934                                                    *   Status                                                                    */
6935             __IM uint32_t TXCARERFIS : 1;         /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt
6936                                                    *   Status                                                                    */
6937             __IM uint32_t TXGOCTIS   : 1;         /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Status                 */
6938             __IM uint32_t TXGFRMIS   : 1;         /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Status                 */
6939             __IM uint32_t TXEXDEFFIS : 1;         /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt
6940                                                    *   Status                                                                    */
6941             __IM uint32_t TXPAUSFIS   : 1;        /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Status                */
6942             __IM uint32_t TXVLANGFIS  : 1;        /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Status            */
6943             __IM uint32_t TXOSIZEGFIS : 1;        /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt
6944                                                    *   Status                                                                    */
6945             uint32_t : 6;
6946         } MMC_Transmit_Interrupt_b;
6947     };
6948 
6949     union
6950     {
6951         __IOM uint32_t MMC_Receive_Interrupt_Mask; /*!< (@ 0x0000010C) MMC Receive Interrupt Mask Register                        */
6952 
6953         struct
6954         {
6955             __IOM uint32_t RXGBFRMIM    : 1;       /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Mask                  */
6956             __IOM uint32_t RXGBOCTIM    : 1;       /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Mask                  */
6957             __IOM uint32_t RXGOCTIM     : 1;       /*!< [2..2] MMC Receive Good Octet Counter Interrupt Mask                      */
6958             __IOM uint32_t RXBCGFIM     : 1;       /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Mask            */
6959             __IOM uint32_t RXMCGFIM     : 1;       /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Mask            */
6960             __IOM uint32_t RXCRCERFIM   : 1;       /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Mask                 */
6961             __IOM uint32_t RXALGNERFIM  : 1;       /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Mask           */
6962             __IOM uint32_t RXRUNTFIM    : 1;       /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Mask                      */
6963             __IOM uint32_t RXJABERFIM   : 1;       /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Mask              */
6964             __IOM uint32_t RXUSIZEGFIM  : 1;       /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Mask            */
6965             __IOM uint32_t RXOSIZEGFIM  : 1;       /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Mask           */
6966             __IOM uint32_t RX64OCTGBFIM : 1;       /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt
6967                                                     *   Mask                                                                      */
6968             __IOM uint32_t RX65T127OCTGBFIM : 1;   /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter
6969                                                     *   Interrupt Mask                                                            */
6970             __IOM uint32_t RX128T255OCTGBFIM : 1;  /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter
6971                                                     *   Interrupt Mask                                                            */
6972             __IOM uint32_t RX256T511OCTGBFIM : 1;  /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter
6973                                                     *   Interrupt Mask                                                            */
6974             __IOM uint32_t RX512T1023OCTGBFIM : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter
6975                                                     *   Interrupt Mask                                                            */
6976             __IOM uint32_t RX1024TMAXOCTGBFIM : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter
6977                                                     *   Interrupt Mask                                                            */
6978             __IOM uint32_t RXUCGFIM    : 1;        /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Mask            */
6979             __IOM uint32_t RXLENERFIM  : 1;        /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Mask            */
6980             __IOM uint32_t RXORANGEFIM : 1;        /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt
6981                                                     *   Mask                                                                      */
6982             __IOM uint32_t RXPAUSFIM   : 1;        /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Mask                   */
6983             __IOM uint32_t RXFOVFIM    : 1;        /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Mask           */
6984             __IOM uint32_t RXVLANGBFIM : 1;        /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Mask           */
6985             __IOM uint32_t RXWDOGFIM   : 1;        /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt
6986                                                     *   Mask                                                                      */
6987             __IOM uint32_t RXRCVERRFIM : 1;        /*!< [24..24] MMC Receive Error Frame Counter Interrupt Mask                   */
6988             __IOM uint32_t RXCTRLFIM   : 1;        /*!< [25..25] MMC Receive Control Frame Counter Interrupt Mask                 */
6989             uint32_t                   : 6;
6990         } MMC_Receive_Interrupt_Mask_b;
6991     };
6992 
6993     union
6994     {
6995         __IOM uint32_t MMC_Transmit_Interrupt_Mask; /*!< (@ 0x00000110) MMC Transmit Interrupt Mask Register                       */
6996 
6997         struct
6998         {
6999             __IOM uint32_t TXGBOCTIM    : 1;        /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Mask                 */
7000             __IOM uint32_t TXGBFRMIM    : 1;        /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Mask                 */
7001             __IOM uint32_t TXBCGFIM     : 1;        /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Mask           */
7002             __IOM uint32_t TXMCGFIM     : 1;        /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Mask           */
7003             __IOM uint32_t TX64OCTGBFIM : 1;        /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt
7004                                                      *   Mask                                                                      */
7005             __IOM uint32_t TX65T127OCTGBFIM : 1;    /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt
7006                                                      *   Mask                                                                      */
7007             __IOM uint32_t TX128T255OCTGBFIM : 1;   /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter
7008                                                      *   Interrupt Mask                                                            */
7009             __IOM uint32_t TX256T511OCTGBFIM : 1;   /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter
7010                                                      *   Interrupt Mask                                                            */
7011             __IOM uint32_t TX512T1023OCTGBFIM : 1;  /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter
7012                                                      *   Interrupt Mask                                                            */
7013             __IOM uint32_t TX1024TMAXOCTGBFIM : 1;  /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter
7014                                                      *   Interrupt Mask                                                            */
7015             __IOM uint32_t TXUCGBFIM : 1;           /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt
7016                                                      *   Mask                                                                      */
7017             __IOM uint32_t TXMCGBFIM : 1;           /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt
7018                                                      *   Mask                                                                      */
7019             __IOM uint32_t TXBCGBFIM : 1;           /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt
7020                                                      *   Mask                                                                      */
7021             __IOM uint32_t TXUFLOWERFIM : 1;        /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt
7022                                                      *   Mask                                                                      */
7023             __IOM uint32_t TXSCOLGFIM : 1;          /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt
7024                                                      *   Mask                                                                      */
7025             __IOM uint32_t TXMCOLGFIM : 1;          /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter
7026                                                      *   Interrupt Mask                                                            */
7027             __IOM uint32_t TXDEFFIM    : 1;         /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Mask               */
7028             __IOM uint32_t TXLATCOLFIM : 1;         /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt
7029                                                      *   Mask                                                                      */
7030             __IOM uint32_t TXEXCOLFIM : 1;          /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt
7031                                                      *   Mask                                                                      */
7032             __IOM uint32_t TXCARERFIM : 1;          /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt
7033                                                      *   Mask                                                                      */
7034             __IOM uint32_t TXGOCTIM   : 1;          /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Mask                   */
7035             __IOM uint32_t TXGFRMIM   : 1;          /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Mask                   */
7036             __IOM uint32_t TXEXDEFFIM : 1;          /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt
7037                                                      *   Mask                                                                      */
7038             __IOM uint32_t TXPAUSFIM   : 1;         /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Mask                  */
7039             __IOM uint32_t TXVLANGFIM  : 1;         /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Mask              */
7040             __IOM uint32_t TXOSIZEGFIM : 1;         /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt
7041                                                      *   Mask                                                                      */
7042             uint32_t : 6;
7043         } MMC_Transmit_Interrupt_Mask_b;
7044     };
7045 
7046     union
7047     {
7048         __IM uint32_t Tx_Octet_Count_Good_Bad; /*!< (@ 0x00000114) Transmit Octet Count for Good and Bad Frames               */
7049 
7050         struct
7051         {
7052             __IM uint32_t TXOCTGB : 32;        /*!< [31..0] This field indicates the number of bytes transmitted
7053                                                 *   in good and bad frames exclusive of preamble and retried
7054                                                 *   bytes.                                                                    */
7055         } Tx_Octet_Count_Good_Bad_b;
7056     };
7057 
7058     union
7059     {
7060         __IM uint32_t Tx_Frame_Count_Good_Bad; /*!< (@ 0x00000118) Transmit Frame Count for Good and Bad Frames               */
7061 
7062         struct
7063         {
7064             __IM uint32_t TXFRMGB : 32;        /*!< [31..0] This field indicates the number of good and bad frames
7065                                                 *   transmitted, exclusive of retried frames.                                 */
7066         } Tx_Frame_Count_Good_Bad_b;
7067     };
7068 
7069     union
7070     {
7071         __IM uint32_t Tx_Broadcast_Frames_Good; /*!< (@ 0x0000011C) Transmit Frame Count for Good Broadcast Frames             */
7072 
7073         struct
7074         {
7075             __IM uint32_t TXBCASTG : 32;        /*!< [31..0] This field indicates the number of transmitted good
7076                                                  *   broadcast frames.                                                         */
7077         } Tx_Broadcast_Frames_Good_b;
7078     };
7079 
7080     union
7081     {
7082         __IM uint32_t Tx_Multicast_Frames_Good; /*!< (@ 0x00000120) Transmit Frame Count for Good Multicast Frames             */
7083 
7084         struct
7085         {
7086             __IM uint32_t TXMCASTG : 32;        /*!< [31..0] This field indicates the number of transmitted good
7087                                                  *   multicast frames.                                                         */
7088         } Tx_Multicast_Frames_Good_b;
7089     };
7090 
7091     union
7092     {
7093         __IM uint32_t Tx_64Octets_Frames_Good_Bad; /*!< (@ 0x00000124) Transmit Octet Count for Good and Bad 64 Byte
7094                                                     *                  Frames                                                     */
7095 
7096         struct
7097         {
7098             __IM uint32_t TX64OCTGB : 32;          /*!< [31..0] This field indicates the number of transmitted good
7099                                                     *   and bad frames with length of 64 bytes, exclusive of preamble
7100                                                     *   and retried frames.                                                       */
7101         } Tx_64Octets_Frames_Good_Bad_b;
7102     };
7103 
7104     union
7105     {
7106         __IM uint32_t Tx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x00000128) Transmit Octet Count for Good and Bad 65 to 127
7107                                                          *              Bytes Frames                                               */
7108 
7109         struct
7110         {
7111             __IM uint32_t TX65_127OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
7112                                                          *   and bad frames with length between 65 and 127 (inclusive)
7113                                                          *   bytes, exclusive of preamble and retried frames.                          */
7114         } Tx_65To127Octets_Frames_Good_Bad_b;
7115     };
7116 
7117     union
7118     {
7119         __IM uint32_t Tx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x0000012C) Transmit Octet Count for Good and Bad 128 to
7120                                                           *             255 Bytes Frames                                           */
7121 
7122         struct
7123         {
7124             __IM uint32_t TX128_255OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
7125                                                           *   and bad frames with length between 128 and 255 (inclusive)
7126                                                           *   bytes, exclusive of preamble and retried frames.                          */
7127         } Tx_128To255Octets_Frames_Good_Bad_b;
7128     };
7129 
7130     union
7131     {
7132         __IM uint32_t Tx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x00000130) Transmit Octet Count for Good and Bad 256 to
7133                                                           *             511 Bytes Frames                                           */
7134 
7135         struct
7136         {
7137             __IM uint32_t TX256_511OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
7138                                                           *   and bad frames with length between 256 and 511 (inclusive)
7139                                                           *   bytes, exclusive of preamble and retried frames.                          */
7140         } Tx_256To511Octets_Frames_Good_Bad_b;
7141     };
7142 
7143     union
7144     {
7145         __IM uint32_t Tx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x00000134) Transmit Octet Count for Good and Bad 512 to
7146                                                            *            1023 Bytes Frames                                          */
7147 
7148         struct
7149         {
7150             __IM uint32_t TX512_1023OCTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
7151                                                            *   and bad frames with length between 512 and 1,023 (inclusive)
7152                                                            *   bytes, exclusive of preamble and retried frames.                          */
7153         } Tx_512To1023Octets_Frames_Good_Bad_b;
7154     };
7155 
7156     union
7157     {
7158         __IM uint32_t Tx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x00000138) Transmit Octet Count for Good and Bad 1024 to
7159                                                            *            Maxsize Bytes Frames                                       */
7160 
7161         struct
7162         {
7163             __IM uint32_t TX1024_MAXOCTGB : 32;           /*!< [31..0] This field indicates the number of good and bad frames
7164                                                            *   transmitted with length between 1,024 and maxsize (inclusive)
7165                                                            *   bytes, exclusive of preamble and retried frames.                          */
7166         } Tx_1024ToMaxOctets_Frames_Good_Bad_b;
7167     };
7168 
7169     union
7170     {
7171         __IM uint32_t Tx_Unicast_Frames_Good_Bad; /*!< (@ 0x0000013C) Transmit Frame Count for Good and Bad Unicast
7172                                                    *                  Frames                                                     */
7173 
7174         struct
7175         {
7176             __IM uint32_t TXUCASTGB : 32;         /*!< [31..0] This field indicates the number of transmitted good
7177                                                    *   and bad unicast frames.                                                   */
7178         } Tx_Unicast_Frames_Good_Bad_b;
7179     };
7180 
7181     union
7182     {
7183         __IM uint32_t Tx_Multicast_Frames_Good_Bad; /*!< (@ 0x00000140) Transmit Frame Count for Good and Bad Multicast
7184                                                      *                  Frames                                                     */
7185 
7186         struct
7187         {
7188             __IM uint32_t TXMCASTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
7189                                                      *   and bad multicast frames.                                                 */
7190         } Tx_Multicast_Frames_Good_Bad_b;
7191     };
7192 
7193     union
7194     {
7195         __IM uint32_t Tx_Broadcast_Frames_Good_Bad; /*!< (@ 0x00000144) Transmit Frame Count for Good and Bad Broadcast
7196                                                      *                  Frames                                                     */
7197 
7198         struct
7199         {
7200             __IM uint32_t TXBCASTGB : 32;           /*!< [31..0] This field indicates the number of transmitted good
7201                                                      *   and bad broadcast frames.                                                 */
7202         } Tx_Broadcast_Frames_Good_Bad_b;
7203     };
7204 
7205     union
7206     {
7207         __IM uint32_t Tx_Underflow_Error_Frames; /*!< (@ 0x00000148) Transmit Frame Count for Underflow Error Frames            */
7208 
7209         struct
7210         {
7211             __IM uint32_t TXUNDRFLW : 16;        /*!< [15..0] This field indicates the number of frames aborted because
7212                                                   *   of frame underflow error.                                                 */
7213             uint32_t : 16;
7214         } Tx_Underflow_Error_Frames_b;
7215     };
7216 
7217     union
7218     {
7219         __IM uint32_t Tx_Single_Collision_Good_Frames; /*!< (@ 0x0000014C) Transmit Frame Count for Frames Transmitted after
7220                                                         *               Single Collision                                           */
7221 
7222         struct
7223         {
7224             __IM uint32_t TXSNGLCOLG : 16;             /*!< [15..0] This field indicates the number of successfully transmitted
7225                                                         *   frames after a single collision in the half-duplex mode.                  */
7226             uint32_t : 16;
7227         } Tx_Single_Collision_Good_Frames_b;
7228     };
7229 
7230     union
7231     {
7232         __IM uint32_t Tx_Multiple_Collision_Good_Frames; /*!< (@ 0x00000150) Transmit Frame Count for Frames Transmitted after
7233                                                           *             Multiple Collision                                         */
7234 
7235         struct
7236         {
7237             __IM uint32_t TXMULTCOLG : 16;               /*!< [15..0] This field indicates the number of successfully transmitted
7238                                                           *   frames after multiple collisions in the half-duplex mode.                 */
7239             uint32_t : 16;
7240         } Tx_Multiple_Collision_Good_Frames_b;
7241     };
7242 
7243     union
7244     {
7245         __IM uint32_t Tx_Deferred_Frames; /*!< (@ 0x00000154) Transmit Frame Count for Deferred Frames                   */
7246 
7247         struct
7248         {
7249             __IM uint32_t TXDEFRD : 16;   /*!< [15..0] This field indicates the number of successfully transmitted
7250                                            *   frames after a deferral in the half-duplex mode.                          */
7251             uint32_t : 16;
7252         } Tx_Deferred_Frames_b;
7253     };
7254 
7255     union
7256     {
7257         __IM uint32_t Tx_Late_Collision_Frames; /*!< (@ 0x00000158) Transmit Frame Count for Late Collision Error
7258                                                  *                  Frames                                                     */
7259 
7260         struct
7261         {
7262             __IM uint32_t TXLATECOL : 16;       /*!< [15..0] This field indicates the number of frames aborted because
7263                                                  *   of late collision error.                                                  */
7264             uint32_t : 16;
7265         } Tx_Late_Collision_Frames_b;
7266     };
7267 
7268     union
7269     {
7270         __IM uint32_t Tx_Excessive_Collision_Frames; /*!< (@ 0x0000015C) Transmit Frame Count for Excessive Collision
7271                                                       *                 Error Frames                                               */
7272 
7273         struct
7274         {
7275             __IM uint32_t TXEXSCOL : 16;             /*!< [15..0] This field indicates the number of frames aborted because
7276                                                       *   of excessive (16) collision error.                                        */
7277             uint32_t : 16;
7278         } Tx_Excessive_Collision_Frames_b;
7279     };
7280 
7281     union
7282     {
7283         __IM uint32_t Tx_Carrier_Error_Frames; /*!< (@ 0x00000160) Transmit Frame Count for Carrier Sense Error
7284                                                 *                  Frames                                                     */
7285 
7286         struct
7287         {
7288             __IM uint32_t TXCARR : 16;         /*!< [15..0] This field indicates the number of frames aborted because
7289                                                 *   of carrier sense error (no carrier or loss of carrier).                   */
7290             uint32_t : 16;
7291         } Tx_Carrier_Error_Frames_b;
7292     };
7293 
7294     union
7295     {
7296         __IM uint32_t Tx_Octet_Count_Good; /*!< (@ 0x00000164) Transmit Octet Count for Good Frames                       */
7297 
7298         struct
7299         {
7300             __IM uint32_t TXOCTG : 32;     /*!< [31..0] TXOCTG                                                            */
7301         } Tx_Octet_Count_Good_b;
7302     };
7303 
7304     union
7305     {
7306         __IM uint32_t Tx_Frame_Count_Good; /*!< (@ 0x00000168) Transmit Frame Count for Good Frames                       */
7307 
7308         struct
7309         {
7310             __IM uint32_t TXFRMG : 32;     /*!< [31..0] This field indicates the number of transmitted good
7311                                             *   frames, exclusive of preamble.                                            */
7312         } Tx_Frame_Count_Good_b;
7313     };
7314 
7315     union
7316     {
7317         __IM uint32_t Tx_Excessive_Deferral_Error; /*!< (@ 0x0000016C) Transmit Frame Count for Excessive Deferral Error
7318                                                     *                  Frames                                                     */
7319 
7320         struct
7321         {
7322             __IM uint32_t TXEXSDEF : 16;           /*!< [15..0] This field indicates the number of frames aborted because
7323                                                     *   of excessive deferral error, that is, frames deferred for
7324                                                     *   more than two max sized frame times.                                      */
7325             uint32_t : 16;
7326         } Tx_Excessive_Deferral_Error_b;
7327     };
7328 
7329     union
7330     {
7331         __IM uint32_t Tx_Pause_Frames;  /*!< (@ 0x00000170) Transmit Frame Count for Good PAUSE Frames                 */
7332 
7333         struct
7334         {
7335             __IM uint32_t TXPAUSE : 16; /*!< [15..0] This field indicates the number of transmitted good
7336                                          *   PAUSE frames.                                                             */
7337             uint32_t : 16;
7338         } Tx_Pause_Frames_b;
7339     };
7340 
7341     union
7342     {
7343         __IM uint32_t Tx_VLAN_Frames_Good; /*!< (@ 0x00000174) Transmit Frame Count for Good VLAN Frames                  */
7344 
7345         struct
7346         {
7347             __IM uint32_t TXVLANG : 32;    /*!< [31..0] This register maintains the number of transmitted good
7348                                             *   VLAN frames, exclusive of retried frames.                                 */
7349         } Tx_VLAN_Frames_Good_b;
7350     };
7351 
7352     union
7353     {
7354         __IM uint32_t Tx_OSize_Frames_Good; /*!< (@ 0x00000178) Transmit Frame Count for Good Oversize Frames              */
7355 
7356         struct
7357         {
7358             __IM uint32_t TXOSIZG : 16;     /*!< [15..0] This field indicates the number of frames transmitted
7359                                              *   without errors and with length greater than the maxsize
7360                                              *   (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes
7361                                              *   if enabled in bit [27] of MAC Configuration Register (MAC_Configuration))
7362                                              */
7363             uint32_t : 16;
7364         } Tx_OSize_Frames_Good_b;
7365     };
7366     __IM uint32_t RESERVED3;
7367 
7368     union
7369     {
7370         __IM uint32_t Rx_Frames_Count_Good_Bad; /*!< (@ 0x00000180) Receive Frame Count for Good and Bad Frames                */
7371 
7372         struct
7373         {
7374             __IM uint32_t RXFRMGB : 32;         /*!< [31..0] This field indicates the number of received good and
7375                                                  *   bad frames.                                                               */
7376         } Rx_Frames_Count_Good_Bad_b;
7377     };
7378 
7379     union
7380     {
7381         __IM uint32_t Rx_Octet_Count_Good_Bad; /*!< (@ 0x00000184) Receive Octet Count for Good and Bad Frames                */
7382 
7383         struct
7384         {
7385             __IM uint32_t RXOCTGB : 32;        /*!< [31..0] This field indicates the number of bytes received, exclusive
7386                                                 *   of preamble, in good and bad frames.                                      */
7387         } Rx_Octet_Count_Good_Bad_b;
7388     };
7389 
7390     union
7391     {
7392         __IM uint32_t Rx_Octet_Count_Good; /*!< (@ 0x00000188) Receive Octet Count for Good Frames                        */
7393 
7394         struct
7395         {
7396             __IM uint32_t RXOCTG : 32;     /*!< [31..0] This field indicates the number of bytes received, exclusive
7397                                             *   of preamble, only in good frames.                                         */
7398         } Rx_Octet_Count_Good_b;
7399     };
7400 
7401     union
7402     {
7403         __IM uint32_t Rx_Broadcast_Frames_Good; /*!< (@ 0x0000018C) Receive Frame Count for Good Broadcast Frames              */
7404 
7405         struct
7406         {
7407             __IM uint32_t RXBCASTG : 32;        /*!< [31..0] This field indicates the number of received good broadcast
7408                                                  *   frames.                                                                   */
7409         } Rx_Broadcast_Frames_Good_b;
7410     };
7411 
7412     union
7413     {
7414         __IM uint32_t Rx_Multicast_Frames_Good; /*!< (@ 0x00000190) Receive Frame Count for Good Multicast Frames              */
7415 
7416         struct
7417         {
7418             __IM uint32_t RXMCASTG : 32;        /*!< [31..0] This field indicates the number of received good multicast
7419                                                  *   frames.                                                                   */
7420         } Rx_Multicast_Frames_Good_b;
7421     };
7422 
7423     union
7424     {
7425         __IM uint32_t Rx_CRC_Error_Frames; /*!< (@ 0x00000194) Receive Frame Count for CRC Error Frames                   */
7426 
7427         struct
7428         {
7429             __IM uint32_t RXCRCERR : 16;   /*!< [15..0] This field indicates the number of frames received with
7430                                             *   CRC error.                                                                */
7431             uint32_t : 16;
7432         } Rx_CRC_Error_Frames_b;
7433     };
7434 
7435     union
7436     {
7437         __IM uint32_t Rx_Alignment_Error_Frames; /*!< (@ 0x00000198) Receive Frame Count for Alignment Error Frames             */
7438 
7439         struct
7440         {
7441             __IM uint32_t RXALGNERR : 16;        /*!< [15..0] This field indicates the number of frames received with
7442                                                   *   alignment (dribble) error. This field is valid only in
7443                                                   *   the 10 or 100 Mbps mode.                                                  */
7444             uint32_t : 16;
7445         } Rx_Alignment_Error_Frames_b;
7446     };
7447 
7448     union
7449     {
7450         __IM uint32_t Rx_Runt_Error_Frames; /*!< (@ 0x0000019C) Receive Frame Count for Runt Error Frames                  */
7451 
7452         struct
7453         {
7454             __IM uint32_t RXRUNTERR : 16;   /*!< [15..0] This field indicates the number of frames received with
7455                                              *   runt error (< 64 bytes and CRC error).                                    */
7456             uint32_t : 16;
7457         } Rx_Runt_Error_Frames_b;
7458     };
7459 
7460     union
7461     {
7462         __IM uint32_t Rx_Jabber_Error_Frames; /*!< (@ 0x000001A0) Receive Frame Count for Jabber Error Frames                */
7463 
7464         struct
7465         {
7466             __IM uint32_t RXJABERR : 16;      /*!< [15..0] This field indicates the number of giant frames received
7467                                                *   with length (including CRC) greater than 1,518 bytes (1,522
7468                                                *   bytes for VLAN tagged) and with CRC error. If Jumbo Frame
7469                                                *   mode is enabled, then frames of length greater than 9,018
7470                                                *   bytes (9,022 for VLAN tagged) are considered as giant frames.             */
7471             uint32_t : 16;
7472         } Rx_Jabber_Error_Frames_b;
7473     };
7474 
7475     union
7476     {
7477         __IM uint32_t Rx_Undersize_Frames_Good; /*!< (@ 0x000001A4) Receive Frame Count for Undersize Frames                   */
7478 
7479         struct
7480         {
7481             __IM uint32_t RXUNDERSZG : 16;      /*!< [15..0] This field indicates the number of frames received with
7482                                                  *   length less than 64 bytes and without errors.                             */
7483             uint32_t : 16;
7484         } Rx_Undersize_Frames_Good_b;
7485     };
7486 
7487     union
7488     {
7489         __IM uint32_t Rx_Oversize_Frames_Good; /*!< (@ 0x000001A8) Receive Frame Count for Oversize Frames                    */
7490 
7491         struct
7492         {
7493             __IM uint32_t RXOVERSZG : 16;      /*!< [15..0] This field indicates the number of frames received without
7494                                                 *   errors, with length greater than the maxsize (1,518 or
7495                                                 *   1,522 for VLAN tagged frames; 2,000 bytes if enabled in
7496                                                 *   bit [27] of MAC Configuration Register (MAC_Configuration)).              */
7497             uint32_t : 16;
7498         } Rx_Oversize_Frames_Good_b;
7499     };
7500 
7501     union
7502     {
7503         __IM uint32_t Rx_64Octets_Frames_Good_Bad; /*!< (@ 0x000001AC) Receive Frame Count for Good and Bad 64 Byte
7504                                                     *                  Frames                                                     */
7505 
7506         struct
7507         {
7508             __IM uint32_t RX64OCTGB : 32;          /*!< [31..0] This field indicates the number of received good and
7509                                                     *   bad frames with length 64 bytes, exclusive of preamble.                   */
7510         } Rx_64Octets_Frames_Good_Bad_b;
7511     };
7512 
7513     union
7514     {
7515         __IM uint32_t Rx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x000001B0) Receive Frame Count for Good and Bad 65 to 127
7516                                                          *              Bytes Frames                                               */
7517 
7518         struct
7519         {
7520             __IM uint32_t RX65_127OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
7521                                                          *   bad frames received with length between 65 and 127 (inclusive)
7522                                                          *   bytes, exclusive of preamble.                                             */
7523         } Rx_65To127Octets_Frames_Good_Bad_b;
7524     };
7525 
7526     union
7527     {
7528         __IM uint32_t Rx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x000001B4) Receive Frame Count for Good and Bad 128 to 255
7529                                                           *             Bytes Frames                                               */
7530 
7531         struct
7532         {
7533             __IM uint32_t RX128_255OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
7534                                                           *   bad frames with length between 128 and 255 (inclusive)
7535                                                           *   bytes, exclusive of preamble.                                             */
7536         } Rx_128To255Octets_Frames_Good_Bad_b;
7537     };
7538 
7539     union
7540     {
7541         __IM uint32_t Rx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x000001B8) Receive Frame Count for Good and Bad 256 to 511
7542                                                           *             Bytes Frames                                               */
7543 
7544         struct
7545         {
7546             __IM uint32_t RX256_511OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
7547                                                           *   bad frames with length between 256 and 511 (inclusive)
7548                                                           *   bytes, exclusive of preamble.                                             */
7549         } Rx_256To511Octets_Frames_Good_Bad_b;
7550     };
7551 
7552     union
7553     {
7554         __IM uint32_t Rx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x000001BC) Receive Frame Count for Good and Bad 512 to 1,023
7555                                                            *            Bytes Frames                                               */
7556 
7557         struct
7558         {
7559             __IM uint32_t RX512_1023OCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
7560                                                            *   bad frames with length between 512 and 1,023 (inclusive)
7561                                                            *   bytes, exclusive of preamble.                                             */
7562         } Rx_512To1023Octets_Frames_Good_Bad_b;
7563     };
7564 
7565     union
7566     {
7567         __IM uint32_t Rx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x000001C0) Receive Frame Count for Good and Bad 1,024 to
7568                                                            *            Maxsize Bytes Frames                                       */
7569 
7570         struct
7571         {
7572             __IM uint32_t RX1024_MAXOCTGB : 32;           /*!< [31..0] This field indicates the number of received good and
7573                                                            *   bad frames with length between 1,024 and maxsize (inclusive)
7574                                                            *   bytes, exclusive of preamble and retried frames.                          */
7575         } Rx_1024ToMaxOctets_Frames_Good_Bad_b;
7576     };
7577 
7578     union
7579     {
7580         __IM uint32_t Rx_Unicast_Frames_Good; /*!< (@ 0x000001C4) Receive Frame Count for Good Unicast Frames                */
7581 
7582         struct
7583         {
7584             __IM uint32_t RXUCASTG : 32;      /*!< [31..0] This field indicates the number of received good unicast
7585                                                *   frames.                                                                   */
7586         } Rx_Unicast_Frames_Good_b;
7587     };
7588 
7589     union
7590     {
7591         __IM uint32_t Rx_Length_Error_Frames; /*!< (@ 0x000001C8) Receive Frame Count for Length Error Frames                */
7592 
7593         struct
7594         {
7595             __IM uint32_t RXLENERR : 16;      /*!< [15..0] RXLENERR                                                          */
7596             uint32_t               : 16;
7597         } Rx_Length_Error_Frames_b;
7598     };
7599 
7600     union
7601     {
7602         __IM uint32_t Rx_Out_Of_Range_Type_Frames; /*!< (@ 0x000001CC) Receive Frame Count for Out of Range Frames                */
7603 
7604         struct
7605         {
7606             __IM uint32_t RXOUTOFRNG : 16;         /*!< [15..0] This field indicates the number of received frames with
7607                                                     *   length field not equal to the valid frame size (greater
7608                                                     *   than 1,500 but less than 1,536).                                          */
7609             uint32_t : 16;
7610         } Rx_Out_Of_Range_Type_Frames_b;
7611     };
7612 
7613     union
7614     {
7615         __IM uint32_t Rx_Pause_Frames;     /*!< (@ 0x000001D0) Receive Frame Count for PAUSE Frames                       */
7616 
7617         struct
7618         {
7619             __IM uint32_t RXPAUSEFRM : 16; /*!< [15..0] This field indicates the number of received good and
7620                                             *   valid PAUSE frames.                                                       */
7621             uint32_t : 16;
7622         } Rx_Pause_Frames_b;
7623     };
7624 
7625     union
7626     {
7627         __IM uint32_t Rx_FIFO_Overflow_Frames; /*!< (@ 0x000001D4) Receive Frame Count for FIFO Overflow Frames               */
7628 
7629         struct
7630         {
7631             __IM uint32_t RXFIFOOVFL : 16;     /*!< [15..0] This field indicates the number of received frames missed
7632                                                 *   because of FIFO overflow.                                                 */
7633             uint32_t : 16;
7634         } Rx_FIFO_Overflow_Frames_b;
7635     };
7636 
7637     union
7638     {
7639         __IM uint32_t Rx_VLAN_Frames_Good_Bad; /*!< (@ 0x000001D8) Receive Frame Count for Good and Bad VLAN Frames           */
7640 
7641         struct
7642         {
7643             __IM uint32_t RXVLANFRGB : 32;     /*!< [31..0] This field indicates the number of received good and
7644                                                 *   bad VLAN frames.                                                          */
7645         } Rx_VLAN_Frames_Good_Bad_b;
7646     };
7647 
7648     union
7649     {
7650         __IM uint32_t Rx_Watchdog_Error_Frames; /*!< (@ 0x000001DC) Receive Frame Count for Watchdog Error Frames              */
7651 
7652         struct
7653         {
7654             __IM uint32_t RXWDGERR : 16;        /*!< [15..0] This field indicates the number of frames received with
7655                                                  *   error because of the watchdog timeout error (frames with
7656                                                  *   more than 2,048 bytes or value programmed in Watchdog Timeout
7657                                                  *   Register (WDog_Timeout)).                                                 */
7658             uint32_t : 16;
7659         } Rx_Watchdog_Error_Frames_b;
7660     };
7661 
7662     union
7663     {
7664         __IM uint32_t Rx_Receive_Error_Frames; /*!< (@ 0x000001E0) Receive Frame Count for Receive Error Frames               */
7665 
7666         struct
7667         {
7668             __IM uint32_t RXRCVERR : 16;       /*!< [15..0] This field indicates the number of frames received with
7669                                                 *   error because of the GMII/MII RXER error or Frame Extension
7670                                                 *   error on GMII.                                                            */
7671             uint32_t : 16;
7672         } Rx_Receive_Error_Frames_b;
7673     };
7674 
7675     union
7676     {
7677         __IM uint32_t Rx_Control_Frames_Good; /*!< (@ 0x000001E4) Receive Frame Count for Good Control Frames                */
7678 
7679         struct
7680         {
7681             __IM uint32_t RXCTRLG : 32;       /*!< [31..0] This field indicates the number of good control frames
7682                                                *   received.                                                                 */
7683         } Rx_Control_Frames_Good_b;
7684     };
7685     __IM uint32_t RESERVED4[134];
7686 
7687     union
7688     {
7689         __IOM uint32_t GMACTRGSEL;     /*!< (@ 0x00000400) GMAC PTP Trigger Select Register                           */
7690 
7691         struct
7692         {
7693             __IOM uint32_t TRGSEL : 2; /*!< [1..0] Select PTP Timestamp Trigger for GMAC IP                           */
7694             uint32_t              : 30;
7695         } GMACTRGSEL_b;
7696     };
7697     __IM uint32_t RESERVED5[63];
7698 
7699     union
7700     {
7701         __IOM uint32_t HASH_TABLE_REG[8]; /*!< (@ 0x00000500) Hash Table Register [0..7] (n = 0 to 7)                    */
7702 
7703         struct
7704         {
7705             __IOM uint32_t HT : 32;       /*!< [31..0] This field contains the nth 32 bits [31:0] of the Hash
7706                                            *   table.                                                                    */
7707         } HASH_TABLE_REG_b[8];
7708     };
7709     __IM uint32_t RESERVED6[26];
7710 
7711     union
7712     {
7713         __IOM uint32_t VLAN_Hash_Table_Reg; /*!< (@ 0x00000588) VLAN Hash Table Register                                   */
7714 
7715         struct
7716         {
7717             __IOM uint32_t VLHT : 16;       /*!< [15..0] VLAN Hash Table                                                   */
7718             uint32_t            : 16;
7719         } VLAN_Hash_Table_Reg_b;
7720     };
7721     __IM uint32_t RESERVED7[93];
7722 
7723     union
7724     {
7725         __IOM uint32_t Timestamp_Control;   /*!< (@ 0x00000700) Timestamp Control Register                                 */
7726 
7727         struct
7728         {
7729             __IOM uint32_t TSENA       : 1; /*!< [0..0] Timestamp Enable                                                   */
7730             uint32_t                   : 7;
7731             __IOM uint32_t TSENALL     : 1; /*!< [8..8] Enable Timestamp for all Frames                                    */
7732             __IOM uint32_t TSCTRLSSR   : 1; /*!< [9..9] Timestamp Digital or Binary Rollover Control                       */
7733             __IOM uint32_t TSVER2ENA   : 1; /*!< [10..10] Enable PTP packet Processing for Version 2 Format                */
7734             __IOM uint32_t TSIPENA     : 1; /*!< [11..11] Enable Processing of PTP over Ethernet Frames                    */
7735             __IOM uint32_t TSIPV6ENA   : 1; /*!< [12..12] Enable Processing of PTP Frames Sent Over IPv6 UDP               */
7736             __IOM uint32_t TSIPV4ENA   : 1; /*!< [13..13] Enable Processing of PTP Frames Sent over IPv4 UDP               */
7737             __IOM uint32_t TSEVNTENA   : 1; /*!< [14..14] Enable Timestamp Snapshot for Event Messages                     */
7738             __IOM uint32_t TSMSTRENA   : 1; /*!< [15..15] Enable Snapshot for Messages Relevant to Master                  */
7739             __IOM uint32_t SNAPTYPSEL  : 2; /*!< [17..16] Select PTP packets for Taking Snapshots                          */
7740             __IOM uint32_t TSENMACADDR : 1; /*!< [18..18] Enable MAC address for PTP Frame Filtering                       */
7741             uint32_t                   : 5;
7742             __IOM uint32_t ATSFC       : 1; /*!< [24..24] Auxiliary Snapshot FIFO Clear                                    */
7743             __IOM uint32_t ATSEN0      : 1; /*!< [25..25] Auxiliary Snapshot 0 Enable                                      */
7744             __IOM uint32_t ATSEN1      : 1; /*!< [26..26] Auxiliary Snapshot 1 Enable                                      */
7745             uint32_t                   : 5;
7746         } Timestamp_Control_b;
7747     };
7748     __IM uint32_t RESERVED8[9];
7749 
7750     union
7751     {
7752         __IM uint32_t Timestamp_Status; /*!< (@ 0x00000728) Timestamp Status Register                                  */
7753 
7754         struct
7755         {
7756             uint32_t                : 2;
7757             __IM uint32_t AUXTSTRIG : 1; /*!< [2..2] Auxiliary Timestamp Trigger Snapshot                               */
7758             uint32_t                : 13;
7759             __IM uint32_t ATSSTN    : 4; /*!< [19..16] Auxiliary Timestamp Snapshot Trigger Identifier                  */
7760             uint32_t                : 4;
7761             __IM uint32_t ATSSTM    : 1; /*!< [24..24] Auxiliary Timestamp Snapshot Trigger Missed                      */
7762             __IM uint32_t ATSNS     : 5; /*!< [29..25] Number of Auxiliary Timestamp Snapshots                          */
7763             uint32_t                : 2;
7764         } Timestamp_Status_b;
7765     };
7766     __IM uint32_t RESERVED9;
7767 
7768     union
7769     {
7770         __IM uint32_t Auxiliary_Timestamp_Nanoseconds; /*!< (@ 0x00000730) Auxiliary Timestamp - Nanoseconds Register            */
7771 
7772         struct
7773         {
7774             __IM uint32_t AUXTSLO : 31;                /*!< [30..0] Contains the lower 32 bits (nanoseconds field) of the
7775                                                         *   auxiliary timestamp.                                                      */
7776             uint32_t : 1;
7777         } Auxiliary_Timestamp_Nanoseconds_b;
7778     };
7779 
7780     union
7781     {
7782         __IM uint32_t Auxiliary_Timestamp_Seconds; /*!< (@ 0x00000734) Auxiliary Timestamp - Seconds Register                     */
7783 
7784         struct
7785         {
7786             __IM uint32_t AUXTSHI : 32;            /*!< [31..0] Contains the upper 32 bits (Seconds field) of the auxiliary
7787                                                     *   timestamp.                                                                */
7788         } Auxiliary_Timestamp_Seconds_b;
7789     };
7790     __IM uint32_t RESERVED10[50];
7791 
7792     union
7793     {
7794         __IOM uint32_t MAR16_H;         /*!< (@ 0x00000800) MAC ADDRESS High Register                                  */
7795 
7796         struct
7797         {
7798             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
7799             uint32_t              : 8;
7800             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
7801             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
7802             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
7803         } MAR16_H_b;
7804     };
7805 
7806     union
7807     {
7808         __IOM uint32_t MAR16_L;         /*!< (@ 0x00000804) MAC ADDRESS Low Register                                   */
7809 
7810         struct
7811         {
7812             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
7813         } MAR16_L_b;
7814     };
7815 
7816     union
7817     {
7818         __IOM uint32_t MAR17_H;         /*!< (@ 0x00000808) MAC ADDRESS High Register                                  */
7819 
7820         struct
7821         {
7822             __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32]                                              */
7823             uint32_t              : 8;
7824             __IOM uint32_t MBC    : 6;  /*!< [29..24] Mask Byte Control                                                */
7825             __IOM uint32_t SA     : 1;  /*!< [30..30] Source Address                                                   */
7826             __IOM uint32_t AE     : 1;  /*!< [31..31] Address Enable                                                   */
7827         } MAR17_H_b;
7828     };
7829 
7830     union
7831     {
7832         __IOM uint32_t MAR17_L;         /*!< (@ 0x0000080C) MAC ADDRESS Low Register                                   */
7833 
7834         struct
7835         {
7836             __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0]                                               */
7837         } MAR17_L_b;
7838     };
7839     __IM uint32_t RESERVED11[508];
7840 
7841     union
7842     {
7843         __IOM uint32_t Bus_Mode;       /*!< (@ 0x00001000) Bus Mode Register                                          */
7844 
7845         struct
7846         {
7847             __IOM uint32_t SWR   : 1;  /*!< [0..0] Software Reset                                                     */
7848             __IM uint32_t  DA    : 1;  /*!< [1..1] DMA Arbitration Scheme                                             */
7849             __IOM uint32_t DSL   : 5;  /*!< [6..2] Descriptor Skip Length                                             */
7850             __IOM uint32_t ATDS  : 1;  /*!< [7..7] Enhanced Descriptor Size                                           */
7851             __IOM uint32_t PBL   : 6;  /*!< [13..8] Programmable Burst Length                                         */
7852             __IM uint32_t  PR    : 2;  /*!< [15..14] Priority Ratio                                                   */
7853             __IOM uint32_t FB    : 1;  /*!< [16..16] Fixed Burst                                                      */
7854             __IOM uint32_t RPBL  : 6;  /*!< [22..17] RX DMA PBL                                                       */
7855             __IOM uint32_t USP   : 1;  /*!< [23..23] Use Separate PBL                                                 */
7856             __IOM uint32_t PBLx8 : 1;  /*!< [24..24] PBLx8 Mode                                                       */
7857             __IOM uint32_t AAL   : 1;  /*!< [25..25] Address Aligned Beats                                            */
7858             __IM uint32_t  MB    : 1;  /*!< [26..26] Mixed Burst                                                      */
7859             __IM uint32_t  TXPR  : 1;  /*!< [27..27] Transmit Priority                                                */
7860             __IM uint32_t  PRWG  : 2;  /*!< [29..28] Channel Priority Weights                                         */
7861             uint32_t             : 1;
7862             __IM uint32_t RIB    : 1;  /*!< [31..31] Rebuild INCRx Burst                                              */
7863         } Bus_Mode_b;
7864     };
7865 
7866     union
7867     {
7868         __IOM uint32_t Transmit_Poll_Demand; /*!< (@ 0x00001004) Transmit Poll Demand Register                              */
7869 
7870         struct
7871         {
7872             __IOM uint32_t TPD : 32;         /*!< [31..0] Transmit Poll Demand                                              */
7873         } Transmit_Poll_Demand_b;
7874     };
7875 
7876     union
7877     {
7878         __IOM uint32_t Receive_Poll_Demand; /*!< (@ 0x00001008) Receive Poll Demand Register                               */
7879 
7880         struct
7881         {
7882             __IOM uint32_t RPD : 32;        /*!< [31..0] Receive Poll Demand                                               */
7883         } Receive_Poll_Demand_b;
7884     };
7885 
7886     union
7887     {
7888         __IOM uint32_t Receive_Descriptor_List_Address; /*!< (@ 0x0000100C) Receive Descriptor List Address Register                */
7889 
7890         struct
7891         {
7892             uint32_t                    : 2;
7893             __IOM uint32_t RDESLA_32bit : 30; /*!< [31..2] Start of Receive List                                             */
7894         } Receive_Descriptor_List_Address_b;
7895     };
7896 
7897     union
7898     {
7899         __IOM uint32_t Transmit_Descriptor_List_Address; /*!< (@ 0x00001010) Transmit Descriptor List Address Register              */
7900 
7901         struct
7902         {
7903             uint32_t                    : 2;
7904             __IOM uint32_t TDESLA_32bit : 30; /*!< [31..2] Start of Transmit List                                            */
7905         } Transmit_Descriptor_List_Address_b;
7906     };
7907 
7908     union
7909     {
7910         __IOM uint32_t Status;         /*!< (@ 0x00001014) Status Register                                            */
7911 
7912         struct
7913         {
7914             __IOM uint32_t TI   : 1;   /*!< [0..0] Transmit Interrupt                                                 */
7915             __IOM uint32_t TPS  : 1;   /*!< [1..1] Transmit Process Stopped                                           */
7916             __IOM uint32_t TU   : 1;   /*!< [2..2] Transmit Buffer Unavailable                                        */
7917             __IOM uint32_t TJT  : 1;   /*!< [3..3] Transmit Jabber Timeout                                            */
7918             __IOM uint32_t OVF  : 1;   /*!< [4..4] Receive Overflow                                                   */
7919             __IOM uint32_t UNF  : 1;   /*!< [5..5] Transmit Underflow                                                 */
7920             __IOM uint32_t RI   : 1;   /*!< [6..6] Receive Interrupt                                                  */
7921             __IOM uint32_t RU   : 1;   /*!< [7..7] Receive Buffer Unavailable                                         */
7922             __IOM uint32_t RPS  : 1;   /*!< [8..8] Receive Process Stopped                                            */
7923             __IOM uint32_t RWT  : 1;   /*!< [9..9] Receive Watchdog Timeout                                           */
7924             __IOM uint32_t ETI  : 1;   /*!< [10..10] Early Transmit Interrupt                                         */
7925             uint32_t            : 2;
7926             __IOM uint32_t FBI  : 1;   /*!< [13..13] Fatal Bus Error Interrupt                                        */
7927             __IOM uint32_t ERI  : 1;   /*!< [14..14] Early Receive Interrupt                                          */
7928             __IOM uint32_t AIS  : 1;   /*!< [15..15] Abnormal Interrupt Summary                                       */
7929             __IOM uint32_t NIS  : 1;   /*!< [16..16] Normal Interrupt Summary                                         */
7930             __IM uint32_t  RS   : 3;   /*!< [19..17] Received Process State                                           */
7931             __IM uint32_t  TS   : 3;   /*!< [22..20] Transmit Process State                                           */
7932             __IM uint32_t  EB   : 3;   /*!< [25..23] Error Bits                                                       */
7933             uint32_t            : 1;
7934             __IM uint32_t GMI   : 1;   /*!< [27..27] GMAC MMC Interrupt                                               */
7935             __IM uint32_t GPI   : 1;   /*!< [28..28] GMAC PMT Interrupt                                               */
7936             __IM uint32_t TTI   : 1;   /*!< [29..29] Timestamp Trigger Interrupt                                      */
7937             __IM uint32_t GLPII : 1;   /*!< [30..30] GMAC LPI Interrupt                                               */
7938             uint32_t            : 1;
7939         } Status_b;
7940     };
7941 
7942     union
7943     {
7944         __IOM uint32_t Operation_Mode; /*!< (@ 0x00001018) Operation Mode Register                                    */
7945 
7946         struct
7947         {
7948             uint32_t           : 1;
7949             __IOM uint32_t SR  : 1;    /*!< [1..1] Start or Stop Receive                                              */
7950             __IOM uint32_t OSF : 1;    /*!< [2..2] Operate on Second Frame                                            */
7951             __IOM uint32_t RTC : 2;    /*!< [4..3] Receive Threshold Control                                          */
7952             __IOM uint32_t DGF : 1;    /*!< [5..5] Drop Giant Frames                                                  */
7953             __IOM uint32_t FUF : 1;    /*!< [6..6] Forward Undersized Good Frames                                     */
7954             __IOM uint32_t FEF : 1;    /*!< [7..7] Forward Error Frames                                               */
7955             __IOM uint32_t EFC : 1;    /*!< [8..8] Enable HW Flow Control                                             */
7956             __IOM uint32_t RFA : 2;    /*!< [10..9] Threshold for Activating Flow Control (in half-duplex
7957                                         *   and full-duplex)                                                          */
7958             __IOM uint32_t RFD : 2;    /*!< [12..11] Threshold for Deactivating Flow Control (in half-duplex
7959                                         *   and full-duplex)                                                          */
7960             __IOM uint32_t ST  : 1;    /*!< [13..13] Start or Stop Transmission Command                               */
7961             __IOM uint32_t TTC : 3;    /*!< [16..14] Transmit Threshold Control                                       */
7962             uint32_t           : 3;
7963             __IOM uint32_t FTF : 1;    /*!< [20..20] Flush Transmit FIFO                                              */
7964             __IOM uint32_t TSF : 1;    /*!< [21..21] Transmit Store and Forward                                       */
7965             uint32_t           : 3;
7966             __IOM uint32_t RSF : 1;    /*!< [25..25] Receive Store and Forward                                        */
7967             __IOM uint32_t DT  : 1;    /*!< [26..26] Disable Dropping of TCP/IP Checksum Error Frames                 */
7968             uint32_t           : 5;
7969         } Operation_Mode_b;
7970     };
7971 
7972     union
7973     {
7974         __IOM uint32_t Interrupt_Enable; /*!< (@ 0x0000101C) Interrupt Enable Register                                  */
7975 
7976         struct
7977         {
7978             __IOM uint32_t TIE : 1;      /*!< [0..0] Transmit Interrupt Enable                                          */
7979             __IOM uint32_t TSE : 1;      /*!< [1..1] Transmit Stopped Enable                                            */
7980             __IOM uint32_t TUE : 1;      /*!< [2..2] Transmit Buffer Unavailable Enable                                 */
7981             __IOM uint32_t TJE : 1;      /*!< [3..3] Transmit Jabber Timeout Enable                                     */
7982             __IOM uint32_t OVE : 1;      /*!< [4..4] Overflow Interrupt Enable                                          */
7983             __IOM uint32_t UNE : 1;      /*!< [5..5] Underflow Interrupt Enable                                         */
7984             __IOM uint32_t RIE : 1;      /*!< [6..6] Receive Interrupt Enable                                           */
7985             __IOM uint32_t RUE : 1;      /*!< [7..7] Receive Buffer Unavailable Enable                                  */
7986             __IOM uint32_t RSE : 1;      /*!< [8..8] Receive Stopped Enable                                             */
7987             __IOM uint32_t RWE : 1;      /*!< [9..9] Receive Watchdog Timeout Enable                                    */
7988             __IOM uint32_t ETE : 1;      /*!< [10..10] Early Transmit Interrupt Enable                                  */
7989             uint32_t           : 2;
7990             __IOM uint32_t FBE : 1;      /*!< [13..13] Fatal Bus Error Enable                                           */
7991             __IOM uint32_t ERE : 1;      /*!< [14..14] Early Receive Interrupt Enable                                   */
7992             __IOM uint32_t AIE : 1;      /*!< [15..15] Abnormal Interrupt Summary Enable                                */
7993             __IOM uint32_t NIE : 1;      /*!< [16..16] Normal Interrupt Summary Enable                                  */
7994             uint32_t           : 15;
7995         } Interrupt_Enable_b;
7996     };
7997 
7998     union
7999     {
8000         __IM uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /*!< (@ 0x00001020) Missed Frame and Buffer Overflow Counter Register */
8001 
8002         struct
8003         {
8004             __IM uint32_t MISFRMCNT : 16;                       /*!< [15..0] Missed Frame Counter                                              */
8005             __IM uint32_t MISCNTOVF : 1;                        /*!< [16..16] Overflow Bit for Missed Frame Counter                            */
8006             __IM uint32_t OVFFRMCNT : 11;                       /*!< [27..17] Overflow Frame Counter                                           */
8007             __IM uint32_t OVFCNTOVF : 1;                        /*!< [28..28] Overflow Bit for FIFO Overflow Counter                           */
8008             uint32_t                : 3;
8009         } Missed_Frame_And_Buffer_Overflow_Counter_b;
8010     };
8011 
8012     union
8013     {
8014         __IOM uint32_t Receive_Interrupt_Watchdog_Timer; /*!< (@ 0x00001024) Receive Interrupt Watchdog Timer Register              */
8015 
8016         struct
8017         {
8018             __IOM uint32_t RIWT : 8;                     /*!< [7..0] RI Watchdog Timer Count                                            */
8019             uint32_t            : 24;
8020         } Receive_Interrupt_Watchdog_Timer_b;
8021     };
8022 
8023     union
8024     {
8025         __IOM uint32_t AXI_Bus_Mode;        /*!< (@ 0x00001028) AXI Bus Mode Register                                      */
8026 
8027         struct
8028         {
8029             __IM uint32_t  UNDEF       : 1; /*!< [0..0] AXI Undefined Burst Length                                         */
8030             __IOM uint32_t BLEN4       : 1; /*!< [1..1] AXI Burst Length 4                                                 */
8031             __IOM uint32_t BLEN8       : 1; /*!< [2..2] AXI Burst Length 8                                                 */
8032             __IOM uint32_t BLEN16      : 1; /*!< [3..3] AXI Burst Length 16                                                */
8033             uint32_t                   : 8;
8034             __IM uint32_t  AXI_AAL     : 1; /*!< [12..12] Address-Aligned Beats                                            */
8035             __IOM uint32_t ONEKBBE     : 1; /*!< [13..13] 1 KB Boundary Crossing Enable for the GMAC-AXI Master            */
8036             uint32_t                   : 2;
8037             __IOM uint32_t RD_OSR_LMT  : 2; /*!< [17..16] AXI Maximum Read OutStanding Request Limit                       */
8038             uint32_t                   : 2;
8039             __IOM uint32_t WR_OSR_LMT  : 2; /*!< [21..20] AXI Maximum Write OutStanding Request Limit                      */
8040             uint32_t                   : 8;
8041             __IOM uint32_t LPI_XIT_FRM : 1; /*!< [30..30] Unlock on Magic Packet or Remote Wake-Up Frame                   */
8042             __IOM uint32_t EN_LPI      : 1; /*!< [31..31] Enable Low Power Interface (LPI)                                 */
8043         } AXI_Bus_Mode_b;
8044     };
8045 
8046     union
8047     {
8048         __IM uint32_t AXI_Status;       /*!< (@ 0x0000102C) AXI Status Register                                        */
8049 
8050         struct
8051         {
8052             __IM uint32_t AXWHSTS  : 1; /*!< [0..0] AXI Master Write Channel                                           */
8053             __IM uint32_t AXIRDSTS : 1; /*!< [1..1] AXI Master Read Channel Status                                     */
8054             uint32_t               : 30;
8055         } AXI_Status_b;
8056     };
8057     __IM uint32_t RESERVED12[6];
8058 
8059     union
8060     {
8061         __IM uint32_t Current_Host_Transmit_Descriptor; /*!< (@ 0x00001048) Current Host Transmit Descriptor Register              */
8062 
8063         struct
8064         {
8065             __IM uint32_t CURTDESAPTR : 32;             /*!< [31..0] Host Transmit Descriptor Address Pointer                          */
8066         } Current_Host_Transmit_Descriptor_b;
8067     };
8068 
8069     union
8070     {
8071         __IM uint32_t Current_Host_Receive_Descriptor; /*!< (@ 0x0000104C) Current Host Receive Descriptor Register                */
8072 
8073         struct
8074         {
8075             __IM uint32_t CURRDESAPTR : 32;            /*!< [31..0] Host Receive Descriptor Address Pointer                           */
8076         } Current_Host_Receive_Descriptor_b;
8077     };
8078 
8079     union
8080     {
8081         __IM uint32_t Current_Host_Transmit_Buffer_Address; /*!< (@ 0x00001050) Current Host Transmit Buffer Address Register      */
8082 
8083         struct
8084         {
8085             __IM uint32_t CURTBUFAPTR : 32;                 /*!< [31..0] Host Transmit Buffer Address Pointer                              */
8086         } Current_Host_Transmit_Buffer_Address_b;
8087     };
8088 
8089     union
8090     {
8091         __IM uint32_t Current_Host_Receive_Buffer_Address; /*!< (@ 0x00001054) Current Host Receive Buffer Address Register        */
8092 
8093         struct
8094         {
8095             __IM uint32_t CURRBUFAPTR : 32;                /*!< [31..0] Host Receive Buffer Address Pointer                               */
8096         } Current_Host_Receive_Buffer_Address_b;
8097     };
8098 
8099     union
8100     {
8101         __IM uint32_t HW_Feature;           /*!< (@ 0x00001058) HW Feature Register                                        */
8102 
8103         struct
8104         {
8105             __IM uint32_t MIISEL       : 1; /*!< [0..0] 10 or 100 Mbps support                                             */
8106             __IM uint32_t GMIISEL      : 1; /*!< [1..1] 1000 Mbps support                                                  */
8107             __IM uint32_t HDSEL        : 1; /*!< [2..2] Half-Duplex support                                                */
8108             __IM uint32_t EXTHASHEN    : 1; /*!< [3..3] Expanded DA Hash Filter                                            */
8109             __IM uint32_t HASHSEL      : 1; /*!< [4..4] HASH Filter                                                        */
8110             __IM uint32_t ADDMACADRSEL : 1; /*!< [5..5] Multiple MAC Address Registers                                     */
8111             uint32_t                   : 1;
8112             __IM uint32_t L3L4FLTREN   : 1; /*!< [7..7] Layer 3 and Layer 4 Filter Feature                                 */
8113             __IM uint32_t SMASEL       : 1; /*!< [8..8] SMA (MDIO) Interface                                               */
8114             __IM uint32_t RWKSEL       : 1; /*!< [9..9] PMT Remote wakeup                                                  */
8115             __IM uint32_t MGKSEL       : 1; /*!< [10..10] PMT Magic Packet                                                 */
8116             __IM uint32_t MMCSEL       : 1; /*!< [11..11] RMON Module                                                      */
8117             __IM uint32_t TSVER1SEL    : 1; /*!< [12..12] Only IEEE 1588-2002 Timestamp                                    */
8118             __IM uint32_t TSVER2SEL    : 1; /*!< [13..13] IEEE 1588-2008 Advanced Timestamp                                */
8119             __IM uint32_t EEESEL       : 1; /*!< [14..14] Energy Efficient Ethernet                                        */
8120             __IM uint32_t AVSEL        : 1; /*!< [15..15] AV Feature                                                       */
8121             __IM uint32_t TXCOESEL     : 1; /*!< [16..16] Checksum Offload in TX                                           */
8122             __IM uint32_t RXTYP1COE    : 1; /*!< [17..17] IP Checksum Offload (Type 1) in RX                               */
8123             __IM uint32_t RXTYP2COE    : 1; /*!< [18..18] IP Checksum Offload (Type 2) in RX                               */
8124             __IM uint32_t RXFIFOSIZE   : 1; /*!< [19..19] RX FIFO > 2,048 Bytes                                            */
8125             __IM uint32_t RXCHCNT      : 2; /*!< [21..20] Number of additional RX channels                                 */
8126             __IM uint32_t TXCHCNT      : 2; /*!< [23..22] Number of additional TX channels                                 */
8127             __IM uint32_t ENHDESSEL    : 1; /*!< [24..24] Enhanced Descriptor                                              */
8128             __IM uint32_t INTTSEN      : 1; /*!< [25..25] Timestamping with Internal System Time                           */
8129             __IM uint32_t FLEXIPPSEN   : 1; /*!< [26..26] Flexible Pulse-Per-Second Output (GMAC: 0)                       */
8130             __IM uint32_t SAVLANINS    : 1; /*!< [27..27] Source Address or VLAN Insertion                                 */
8131             __IM uint32_t ACTPHYIF     : 3; /*!< [30..28] Active or Selected PHY interface                                 */
8132             uint32_t                   : 1;
8133         } HW_Feature_b;
8134     };
8135 } R_GMAC_Type;                              /*!< Size = 4188 (0x105c)                                                      */
8136 
8137 /* =========================================================================================================================== */
8138 /* ================                                          R_ETHSS                                          ================ */
8139 /* =========================================================================================================================== */
8140 
8141 /**
8142  * @brief Ethernet Subsystem (R_ETHSS)
8143  */
8144 
8145 typedef struct                         /*!< (@ 0x80110000) R_ETHSS Structure                                          */
8146 {
8147     __IOM uint32_t PRCMD;              /*!< (@ 0x00000000) Ethernet Protect Register                                  */
8148     __IM uint32_t  RESERVED;
8149 
8150     union
8151     {
8152         __IOM uint32_t MODCTRL;         /*!< (@ 0x00000008) Mode Control Register                                      */
8153 
8154         struct
8155         {
8156             __IOM uint32_t SW_MODE : 3; /*!< [2..0] Media I/F connectionSW_MODE[2:0]Media I/FPort 0Port 1Port
8157                                          *   2000bETHSW Port 0ETHSW Port 1ETHSW Port 2001bESC Port 0ESC
8158                                          *   Port 1GMAC Port010bESC Port 0ESC Port 1ETHSW Port 2011bESC
8159                                          *   Port 0ESC Port 1ESC Port 2100bETHSW Port 0ESC Port 1ESC
8160                                          *   Port 2101bETHSW Port 0ESC Port 1ETHSW Port 2110b-ETHSW
8161                                          *   Port 1ETHSW Port 0111b-ESC Port 1ESC Port 0                             */
8162             uint32_t : 29;
8163         } MODCTRL_b;
8164     };
8165 
8166     union
8167     {
8168         __IOM uint32_t PTPMCTRL;             /*!< (@ 0x0000000C) PTP Mode Control Register                                  */
8169 
8170         struct
8171         {
8172             __IOM uint32_t PTP_MODE : 1;     /*!< [0..0] Select the unit number of PTP Timer for GMAC and Pulse
8173                                               *   Generator (unit 0 - 3)                                                    */
8174             uint32_t                    : 15;
8175             __IOM uint32_t PTP_PLS_RSTn : 1; /*!< [16..16] Reset control for Pulse Generator (unit 0 - 3)                   */
8176             uint32_t                    : 15;
8177         } PTPMCTRL_b;
8178     };
8179     __IM uint32_t RESERVED1;
8180 
8181     union
8182     {
8183         __IOM uint32_t PHYLNK;         /*!< (@ 0x00000014) Ethernet PHY Link Mode Register                            */
8184 
8185         struct
8186         {
8187             __IOM uint32_t SWLINK : 3; /*!< [2..0] Specify the active level of the ETHSW_PHYLINKn signal
8188                                         *   using the Ethernet switch interface                                       */
8189             uint32_t              : 1;
8190             __IOM uint32_t CATLNK : 3; /*!< [6..4] Specify the active level of the ESC_PHYLINKn signal using
8191                                         *   the EtherCAT interface                                                    */
8192             uint32_t : 25;
8193         } PHYLNK_b;
8194     };
8195     __IM uint32_t RESERVED2[58];
8196 
8197     union
8198     {
8199         __IOM uint32_t CONVCTRL[3];           /*!< (@ 0x00000100) RGMII/RMII Converter [0..2] Control Register               */
8200 
8201         struct
8202         {
8203             __IOM uint32_t CONV_MODE     : 5; /*!< [4..0] Converter operation mode                                           */
8204             uint32_t                     : 3;
8205             __IOM uint32_t FULLD         : 1; /*!< [8..8] FULLD                                                              */
8206             __IOM uint32_t RMII_RX_ER_EN : 1; /*!< [9..9] RMII_RX_ER_EN                                                      */
8207             __IOM uint32_t RMII_CRS_MODE : 1; /*!< [10..10] RMII_CRS_MODE                                                    */
8208             uint32_t                     : 1;
8209             __IM uint32_t RGMII_LINK     : 1; /*!< [12..12] RGMII_LINK                                                       */
8210             __IM uint32_t RGMII_DUPLEX   : 1; /*!< [13..13] RGMII_DUPLEX                                                     */
8211             __IM uint32_t RGMII_SPEED    : 2; /*!< [15..14] RGMII_SPEED                                                      */
8212             uint32_t                     : 16;
8213         } CONVCTRL_b[3];
8214     };
8215     __IM uint32_t RESERVED3[2];
8216 
8217     union
8218     {
8219         __IOM uint32_t CONVRST;        /*!< (@ 0x00000114) RGMII/RMII Converter Reset Control Register                */
8220 
8221         struct
8222         {
8223             __IOM uint32_t PHYIR : 3;  /*!< [2..0] PHYIR                                                              */
8224             uint32_t             : 29;
8225         } CONVRST_b;
8226     };
8227     __IM uint32_t RESERVED4[123];
8228 
8229     union
8230     {
8231         __IOM uint32_t SWCTRL;                /*!< (@ 0x00000304) Switch Core Control Register                               */
8232 
8233         struct
8234         {
8235             __IOM uint32_t SET10 : 3;         /*!< [2..0] Port control to select use of 10 Mbps. Bit 0 = port 0,
8236                                                *   bit 1 = port 1, bit 2 = port 2.                                           */
8237             uint32_t               : 1;
8238             __IOM uint32_t SET1000 : 3;       /*!< [6..4] Port control to select use of 1000 Mbps. Bit 0 = port
8239                                                *   0, bit 1 = port 1, bit 2 = port 2.                                        */
8240             uint32_t                    : 9;
8241             __IOM uint32_t STRAP_SX_ENB : 1;  /*!< [16..16] Initialize switch after reset (set during module reset
8242                                                *   of ETHSW)                                                                 */
8243             __IOM uint32_t STRAP_HUB_ENB : 1; /*!< [17..17] Initialize switch port 0 and 1 (set during module reset
8244                                                *   of ETHSW)                                                                 */
8245             uint32_t : 14;
8246         } SWCTRL_b;
8247     };
8248 
8249     union
8250     {
8251         __IOM uint32_t SWDUPC;             /*!< (@ 0x00000308) Switch Core Duplex Mode Register                           */
8252 
8253         struct
8254         {
8255             __IOM uint32_t PHY_DUPLEX : 3; /*!< [2..0] Configure the MAC of each port for full-duplex or half-duplex
8256                                             *   operation. Bit 0 = port 0, bit 1 = port 1, bit 2 = port
8257                                             *   2.                                                                        */
8258             uint32_t : 29;
8259         } SWDUPC_b;
8260     };
8261     __IM uint32_t RESERVED5[573];
8262 
8263     union
8264     {
8265         __IOM uint32_t CDCR;             /*!< (@ 0x00000C00) RGMII Clock Delay Control Register                         */
8266 
8267         struct
8268         {
8269             __IOM uint32_t RXDLYEN  : 1; /*!< [0..0] Enable delay for ETH2_RXCLK                                        */
8270             __IOM uint32_t TXDLYEN  : 1; /*!< [1..1] Enable delay for ETH2_TXCLK                                        */
8271             __IOM uint32_t OSCCLKEN : 1; /*!< [2..2] Enable Oscillation mode for calibration                            */
8272             __IOM uint32_t CLKINEN  : 1; /*!< [3..3] Enable Phase shift mode for normal operation                       */
8273             uint32_t                : 28;
8274         } CDCR_b;
8275     };
8276     __IM uint32_t RESERVED6[3];
8277 
8278     union
8279     {
8280         __IM uint32_t RXFCNT;          /*!< (@ 0x00000C10) RGMII RX OSC Frequency Measurement Counter Register        */
8281 
8282         struct
8283         {
8284             __IM uint32_t RXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_RXCLK
8285                                         *   delay                                                                     */
8286             uint32_t : 16;
8287         } RXFCNT_b;
8288     };
8289 
8290     union
8291     {
8292         __IM uint32_t TXFCNT;          /*!< (@ 0x00000C14) RGMII TX OSC Frequency Measurement Counter Register        */
8293 
8294         struct
8295         {
8296             __IM uint32_t TXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_TXCLK
8297                                         *   delay                                                                     */
8298             uint32_t : 16;
8299         } TXFCNT_b;
8300     };
8301 
8302     union
8303     {
8304         __IOM uint32_t RXTAPSEL;         /*!< (@ 0x00000C18) RGMII RX TAP Selection Register                            */
8305 
8306         struct
8307         {
8308             __IOM uint32_t RXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_RXCLK delay (number of taps for
8309                                           *   90 degree phase shift)                                                    */
8310             uint32_t : 25;
8311         } RXTAPSEL_b;
8312     };
8313 
8314     union
8315     {
8316         __IOM uint32_t TXTAPSEL;         /*!< (@ 0x00000C1C) RGMII TX TAP Selection Register                            */
8317 
8318         struct
8319         {
8320             __IOM uint32_t TXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_TXCLK delay (Number of taps for
8321                                           *   90 degree phase shift)                                                    */
8322             uint32_t : 25;
8323         } TXTAPSEL_b;
8324     };
8325 
8326     union
8327     {
8328         __IOM uint32_t MIIMCR;           /*!< (@ 0x00000C20) MII Mode Control Register                                  */
8329 
8330         struct
8331         {
8332             __IOM uint32_t MIIM2MEN : 1; /*!< [0..0] Enable MAC-to-MAC MII Mode                                         */
8333             uint32_t                : 31;
8334         } MIIMCR_b;
8335     };
8336 } R_ETHSS_Type;                          /*!< Size = 3108 (0xc24)                                                       */
8337 
8338 /* =========================================================================================================================== */
8339 /* ================                                         R_ESC_INI                                         ================ */
8340 /* =========================================================================================================================== */
8341 
8342 /**
8343  * @brief Initial Configuration 1 for EtherCAT Slave Controller (R_ESC_INI)
8344  */
8345 
8346 typedef struct                         /*!< (@ 0x80110200) R_ESC_INI Structure                                        */
8347 {
8348     union
8349     {
8350         __IOM uint32_t ECATOFFADR;     /*!< (@ 0x00000000) EtherCAT PHY Offset Address Setting Register               */
8351 
8352         struct
8353         {
8354             __IOM uint32_t OADD : 5;   /*!< [4..0] PHY Offset Address Setting                                         */
8355             uint32_t            : 27;
8356         } ECATOFFADR_b;
8357     };
8358 
8359     union
8360     {
8361         __IOM uint32_t ECATOPMOD;          /*!< (@ 0x00000004) EtherCAT Operation Mode Register                           */
8362 
8363         struct
8364         {
8365             __IOM uint32_t EEPROMSIZE : 1; /*!< [0..0] EEPROM Memory Size Specification                                   */
8366             uint32_t                  : 31;
8367         } ECATOPMOD_b;
8368     };
8369 
8370     union
8371     {
8372         __IOM uint32_t ECATDBGC;       /*!< (@ 0x00000008) EtherCAT Debug Control Register                            */
8373 
8374         struct
8375         {
8376             __IOM uint32_t TXSFT0 : 2; /*!< [1..0] Set the delay time for ETH0_TXEN and ETH0_TXDn of the
8377                                         *   EtherCAT                                                                  */
8378             __IOM uint32_t TXSFT1 : 2; /*!< [3..2] Set the delay time for ETH1_TXEN and ETH1_TXDn of the
8379                                         *   EtherCAT                                                                  */
8380             __IOM uint32_t TXSFT2 : 2; /*!< [5..4] Set the delay time for ETH2_TXEN and ETH2_TXDn of the
8381                                         *   EtherCAT                                                                  */
8382             uint32_t : 26;
8383         } ECATDBGC_b;
8384     };
8385 
8386     union
8387     {
8388         __IOM uint32_t ECATTRGSEL;      /*!< (@ 0x0000000C) EtherCAT DC Latch Trigger Select Register                  */
8389 
8390         struct
8391         {
8392             __IOM uint32_t TRGSEL0 : 1; /*!< [0..0] Select DC Latch Trigger 0 for ESC                                  */
8393             __IOM uint32_t TRGSEL1 : 1; /*!< [1..1] Select DC Latch Trigger 1 for ESC                                  */
8394             uint32_t               : 30;
8395         } ECATTRGSEL_b;
8396     };
8397 } R_ESC_INI_Type;                       /*!< Size = 16 (0x10)                                                          */
8398 
8399 /* =========================================================================================================================== */
8400 /* ================                                        R_ETHSW_PTP                                        ================ */
8401 /* =========================================================================================================================== */
8402 
8403 /**
8404  * @brief Ethernet Switch for PTP (R_ETHSW_PTP)
8405  */
8406 
8407 typedef struct                         /*!< (@ 0x80110400) R_ETHSW_PTP Structure                                      */
8408 {
8409     __IM uint32_t RESERVED;
8410 
8411     union
8412     {
8413         __IOM uint32_t SWPTPOUTSEL;     /*!< (@ 0x00000004) ETHSW_PTPOUT Select Register                               */
8414 
8415         struct
8416         {
8417             __IOM uint32_t IOSEL0  : 1; /*!< [0..0] Select the source of the ETHSW_PTPOUT0 output signal               */
8418             __IOM uint32_t IOSEL1  : 1; /*!< [1..1] Select the source of the ETHSW_PTPOUT1 output signal               */
8419             __IOM uint32_t IOSEL2  : 1; /*!< [2..2] Select the source of the ETHSW_PTPOUT2 output signal               */
8420             __IOM uint32_t IOSEL3  : 1; /*!< [3..3] Select the source of the ETHSW_PTPOUT3 output signal               */
8421             __IOM uint32_t EVTSEL0 : 1; /*!< [4..4] Select the source of the ETHSW_PTPOUT0 event for GIC,
8422                                          *   DMAC, and ELC                                                             */
8423             __IOM uint32_t EVTSEL1 : 1; /*!< [5..5] Select the source of the ETHSW_PTPOUT1 event for GIC,
8424                                          *   DMAC, and ELC                                                             */
8425             __IOM uint32_t EVTSEL2 : 1; /*!< [6..6] Select the source of the ETHSW_PTPOUT2 event for GIC,
8426                                          *   DMAC, and ELC                                                             */
8427             __IOM uint32_t EVTSEL3 : 1; /*!< [7..7] Select the source of the ETHSW_PTPOUT3 event for GIC,
8428                                          *   DMAC, and ELC                                                             */
8429             uint32_t : 24;
8430         } SWPTPOUTSEL_b;
8431     };
8432     __IM uint32_t               RESERVED1[254];
8433     __IOM R_ETHSW_PTP_SWTM_Type SWTM[4]; /*!< (@ 0x00000400) Ethernet Switch Timer output pins 0-3 Registers            */
8434 } R_ETHSW_PTP_Type;                      /*!< Size = 2048 (0x800)                                                       */
8435 
8436 /* =========================================================================================================================== */
8437 /* ================                                          R_ETHSW                                          ================ */
8438 /* =========================================================================================================================== */
8439 
8440 /**
8441  * @brief Ethernet Switch (R_ETHSW)
8442  */
8443 
8444 typedef struct                         /*!< (@ 0x80120000) R_ETHSW Structure                                          */
8445 {
8446     union
8447     {
8448         __IM uint32_t REVISION;        /*!< (@ 0x00000000) Switch Core Version Register                               */
8449 
8450         struct
8451         {
8452             __IM uint32_t REV : 32;    /*!< [31..0] Revision                                                          */
8453         } REVISION_b;
8454     };
8455 
8456     union
8457     {
8458         __IOM uint32_t SCRATCH;          /*!< (@ 0x00000004) Scratch Register                                           */
8459 
8460         struct
8461         {
8462             __IOM uint32_t SCRATCH : 32; /*!< [31..0] The Scratch Register provides a memory location to test
8463                                           *   the register access.                                                      */
8464         } SCRATCH_b;
8465     };
8466 
8467     union
8468     {
8469         __IOM uint32_t PORT_ENA;       /*!< (@ 0x00000008) Port Enable Register                                       */
8470 
8471         struct
8472         {
8473             __IOM uint32_t TXENA : 4;  /*!< [3..0] Transmit Enable Mask                                               */
8474             uint32_t             : 12;
8475             __IOM uint32_t RXENA : 4;  /*!< [19..16] Receive Enable Mask                                              */
8476             uint32_t             : 12;
8477         } PORT_ENA_b;
8478     };
8479 
8480     union
8481     {
8482         __IOM uint32_t UCAST_DEFAULT_MASK0; /*!< (@ 0x0000000C) Unicast Default Mask Register 0                            */
8483 
8484         struct
8485         {
8486             __IOM uint32_t UCASTDM : 4;     /*!< [3..0] Default Unicast Resolution                                         */
8487             uint32_t               : 28;
8488         } UCAST_DEFAULT_MASK0_b;
8489     };
8490 
8491     union
8492     {
8493         __IOM uint32_t VLAN_VERIFY;      /*!< (@ 0x00000010) Verify VLAN Domain Register                                */
8494 
8495         struct
8496         {
8497             __IOM uint32_t VLANVERI : 4; /*!< [3..0] Verify VLAN Domain                                                 */
8498             uint32_t                : 12;
8499             __IOM uint32_t VLANDISC : 4; /*!< [19..16] Discard Unknown                                                  */
8500             uint32_t                : 12;
8501         } VLAN_VERIFY_b;
8502     };
8503 
8504     union
8505     {
8506         __IOM uint32_t BCAST_DEFAULT_MASK0; /*!< (@ 0x00000014) Broadcast Default Mask Register 0                          */
8507 
8508         struct
8509         {
8510             __IOM uint32_t BCASTDM : 4;     /*!< [3..0] Default Broadcast Resolution                                       */
8511             uint32_t               : 28;
8512         } BCAST_DEFAULT_MASK0_b;
8513     };
8514 
8515     union
8516     {
8517         __IOM uint32_t MCAST_DEFAULT_MASK0; /*!< (@ 0x00000018) Multicast Default Mask Register 0                          */
8518 
8519         struct
8520         {
8521             __IOM uint32_t MCASTDM : 4;     /*!< [3..0] Default Multicast Resolution                                       */
8522             uint32_t               : 28;
8523         } MCAST_DEFAULT_MASK0_b;
8524     };
8525 
8526     union
8527     {
8528         __IOM uint32_t INPUT_LEARN_BLOCK; /*!< (@ 0x0000001C) Input Learning Block Register                              */
8529 
8530         struct
8531         {
8532             __IOM uint32_t BLOCKEN  : 4;  /*!< [3..0] Blocking Enable                                                    */
8533             uint32_t                : 12;
8534             __IOM uint32_t LEARNDIS : 4;  /*!< [19..16] Learning Disable                                                 */
8535             uint32_t                : 12;
8536         } INPUT_LEARN_BLOCK_b;
8537     };
8538 
8539     union
8540     {
8541         __IOM uint32_t MGMT_CONFIG;       /*!< (@ 0x00000020) Management Configuration Register                          */
8542 
8543         struct
8544         {
8545             __IOM uint32_t PORT : 4;      /*!< [3..0] The Port number of the port that should act as a management
8546                                            *   port. Keep the initial value.                                             */
8547             uint32_t                 : 1;
8548             __IOM uint32_t MSG_TRANS : 1; /*!< [5..5] Set (latched) when a BPDU message is transmitted from
8549                                            *   the management port to any output port. This bit can be
8550                                            *   used for handshaking to indicate that the port mask bits
8551                                            *   are used and can now be changed again by setting it to
8552                                            *   0.                                                                        */
8553             __IOM uint32_t ENABLE : 1;    /*!< [6..6] If set, all Bridge Protocol Frames (BPDU) are forwarded
8554                                            *   exclusively to the management port specified in bits [3:0].               */
8555             __IOM uint32_t DISCARD : 1;   /*!< [7..7] If set, BPDU frames are discarded always.                          */
8556             __IOM uint32_t MGMT_EN : 1;   /*!< [8..8] If set, BPDU frames received at the management port are
8557                                            *   forwarded to the ports given in the portmask given in this
8558                                            *   register, bypassing the normal forwarding decisions (except
8559                                            *   forced forwarding).                                                       */
8560             __IOM uint32_t MGMT_DISC : 1; /*!< [9..9] This bit is the same as DISCARD (bit 7) but for the management
8561                                            *   port.                                                                     */
8562             uint32_t                : 3;
8563             __IOM uint32_t PRIORITY : 3;  /*!< [15..13] Priority to use for transmitted BPDU frames if non-zero.         */
8564             __IOM uint32_t PORTMASK : 4;  /*!< [19..16] Portmask for transmission of management frames. When
8565                                            *   the management port transmits a frame to the switch, it
8566                                            *   is forwarded to all ports in this portmask (bit 16 = port
8567                                            *   0, bit 17 = port 1, ..., bit 19 = port 3).                                */
8568             uint32_t : 12;
8569         } MGMT_CONFIG_b;
8570     };
8571 
8572     union
8573     {
8574         __IOM uint32_t MODE_CONFIG;    /*!< (@ 0x00000024) Mode Configuration Register                                */
8575 
8576         struct
8577         {
8578             uint32_t                   : 8;
8579             __IOM uint32_t CUT_THRU_EN : 4; /*!< [11..8] Port Cut through Support Enable                                   */
8580             uint32_t                   : 19;
8581             __IOM uint32_t STATSRESET  : 1; /*!< [31..31] Reset Statistics Counters Command.                               */
8582         } MODE_CONFIG_b;
8583     };
8584 
8585     union
8586     {
8587         __IOM uint32_t VLAN_IN_MODE;       /*!< (@ 0x00000028) VLAN Input Manipulation Mode Register                      */
8588 
8589         struct
8590         {
8591             __IOM uint32_t P0VLANINMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Input Manipulation Function         */
8592             __IOM uint32_t P1VLANINMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Input Manipulation Function         */
8593             __IOM uint32_t P2VLANINMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Input Manipulation Function         */
8594             __IOM uint32_t P3VLANINMD : 2; /*!< [7..6] Port3 Define Behavior of VLAN Input Manipulation Function          */
8595             uint32_t                  : 24;
8596         } VLAN_IN_MODE_b;
8597     };
8598 
8599     union
8600     {
8601         __IOM uint32_t VLAN_OUT_MODE;       /*!< (@ 0x0000002C) VLAN Output Manipulation Mode Register                     */
8602 
8603         struct
8604         {
8605             __IOM uint32_t P0VLANOUTMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Output Manipulation Function        */
8606             __IOM uint32_t P1VLANOUTMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Output Manipulation Function        */
8607             __IOM uint32_t P2VLANOUTMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Output Manipulation Function        */
8608             __IOM uint32_t P3VLANOUTMD : 2; /*!< [7..6] Port 3 Define Behavior of VLAN Output Manipulation Function        */
8609             uint32_t                   : 24;
8610         } VLAN_OUT_MODE_b;
8611     };
8612 
8613     union
8614     {
8615         __IOM uint32_t VLAN_IN_MODE_ENA;   /*!< (@ 0x00000030) VLAN Input Mode Enable Register                            */
8616 
8617         struct
8618         {
8619             __IOM uint32_t VLANINMDEN : 4; /*!< [3..0] Enable the input processing according to the VLAN_IN_MODE
8620                                             *   for a port (1 bit per port).                                              */
8621             uint32_t : 28;
8622         } VLAN_IN_MODE_ENA_b;
8623     };
8624 
8625     union
8626     {
8627         __IOM uint32_t VLAN_TAG_ID;        /*!< (@ 0x00000034) VLAN Tag ID Register                                       */
8628 
8629         struct
8630         {
8631             __IOM uint32_t VLANTAGID : 16; /*!< [15..0] The VLAN type field (TPID) value to expect to identify
8632                                             *   a VLAN tagged frame.                                                      */
8633             uint32_t : 16;
8634         } VLAN_TAG_ID_b;
8635     };
8636 
8637     union
8638     {
8639         __IOM uint32_t BCAST_STORM_LIMIT;   /*!< (@ 0x00000038) Broadcast Storm Protection Register                        */
8640 
8641         struct
8642         {
8643             __IOM uint32_t TMOUT      : 16; /*!< [15..0] Timeout in steps of 65535 switch operating clock cycles.          */
8644             __IOM uint32_t BCASTLIMIT : 16; /*!< [31..16] Number of broadcast frames (-1) that can be accepted
8645                                              *   on a port during a timeout period. If more are received,
8646                                              *   they are discarded. The counter is implemented per port
8647                                              *   independently. However, the limit is used for all ports.                  */
8648         } BCAST_STORM_LIMIT_b;
8649     };
8650 
8651     union
8652     {
8653         __IOM uint32_t MCAST_STORM_LIMIT; /*!< (@ 0x0000003C) Multicast Storm Protection Register                        */
8654 
8655         struct
8656         {
8657             uint32_t                  : 16;
8658             __IOM uint32_t MCASTLIMIT : 16; /*!< [31..16] Number of multicast frames (-1) that can be accepted
8659                                              *   on a port during a timeout period. If more are received,
8660                                              *   they are discarded. The counter is implemented per port
8661                                              *   independently. However, the limit is used for all ports.                  */
8662         } MCAST_STORM_LIMIT_b;
8663     };
8664 
8665     union
8666     {
8667         __IOM uint32_t MIRROR_CONTROL;       /*!< (@ 0x00000040) Port Mirroring Configuration Register                      */
8668 
8669         struct
8670         {
8671             __IOM uint32_t PORT : 2;         /*!< [1..0] The port number of the port that acts as the mirror port
8672                                               *   and receives all mirrored frames. Valid setting range is
8673                                               *   0 to 3.                                                                   */
8674             uint32_t                    : 2;
8675             __IOM uint32_t MIRROR_EN    : 1; /*!< [4..4] MIRROR_EN                                                          */
8676             __IOM uint32_t ING_MAP_EN   : 1; /*!< [5..5] If set, the ingress map is enabled (MIRROR_ING_MAP).               */
8677             __IOM uint32_t EG_MAP_EN    : 1; /*!< [6..6] If set, the egress map is enabled (MIRROR_EG_MAP).                 */
8678             __IOM uint32_t ING_SA_MATCH : 1; /*!< [7..7] If set, only frames received on an ingress port with
8679                                               *   a source address matching the value programmed in MIRROR_ISRC
8680                                               *   registers are mirrored. Other frames are not mirrored.                    */
8681             __IOM uint32_t ING_DA_MATCH : 1; /*!< [8..8] If set, only frames received on an ingress port with
8682                                               *   a destination address matching the value programmed in
8683                                               *   MIRROR_IDST registers are mirrored. Other frames are not
8684                                               *   mirrored.                                                                 */
8685             __IOM uint32_t EG_SA_MATCH : 1;  /*!< [9..9] If set, only frames transmitted on an egress port with
8686                                               *   a source address matching the value programmed in MIRROR_ESRC
8687                                               *   registers are mirrored. Other frames are not mirrored.                    */
8688             __IOM uint32_t EG_DA_MATCH : 1;  /*!< [10..10] If set, only frames transmitted on an egress port with
8689                                               *   a destination address matching the value programmed in
8690                                               *   MIRROR_EDST registers are mirrored. Other frames are not
8691                                               *   mirrored.                                                                 */
8692             uint32_t : 21;
8693         } MIRROR_CONTROL_b;
8694     };
8695 
8696     union
8697     {
8698         __IOM uint32_t MIRROR_EG_MAP;  /*!< (@ 0x00000044) Port Mirroring Egress Port Definition Register             */
8699 
8700         struct
8701         {
8702             __IOM uint32_t EMAP : 4;   /*!< [3..0] Port Mirroring Egress Port Definitions                             */
8703             uint32_t            : 28;
8704         } MIRROR_EG_MAP_b;
8705     };
8706 
8707     union
8708     {
8709         __IOM uint32_t MIRROR_ING_MAP; /*!< (@ 0x00000048) Port Mirroring Ingress Port Definition Register            */
8710 
8711         struct
8712         {
8713             __IOM uint32_t IMAP : 4;   /*!< [3..0] Port Mirroring Ingress Port Definitions                            */
8714             uint32_t            : 28;
8715         } MIRROR_ING_MAP_b;
8716     };
8717 
8718     union
8719     {
8720         __IOM uint32_t MIRROR_ISRC_0;  /*!< (@ 0x0000004C) Ingress Source MAC Address for Mirror Filtering
8721                                         *                  Register 0                                                 */
8722 
8723         struct
8724         {
8725             __IOM uint32_t ISRC : 32;  /*!< [31..0] Ingress Source MAC Address for Mirror Filtering                   */
8726         } MIRROR_ISRC_0_b;
8727     };
8728 
8729     union
8730     {
8731         __IOM uint32_t MIRROR_ISRC_1;  /*!< (@ 0x00000050) Ingress Source MAC Address for Mirror Filtering
8732                                         *                  Register 1                                                 */
8733 
8734         struct
8735         {
8736             __IOM uint32_t ISRC : 16;  /*!< [15..0] Ingress Source MAC Address for Mirror Filtering                   */
8737             uint32_t            : 16;
8738         } MIRROR_ISRC_1_b;
8739     };
8740 
8741     union
8742     {
8743         __IOM uint32_t MIRROR_IDST_0;  /*!< (@ 0x00000054) Ingress Destination MAC Address for Mirror Filtering
8744                                         *                  Register 0                                                 */
8745 
8746         struct
8747         {
8748             __IOM uint32_t IDST : 32;  /*!< [31..0] Ingress Destination MAC Address for Mirror Filtering              */
8749         } MIRROR_IDST_0_b;
8750     };
8751 
8752     union
8753     {
8754         __IOM uint32_t MIRROR_IDST_1;  /*!< (@ 0x00000058) Ingress Destination MAC Address for Mirror Filtering
8755                                         *                  Register 1                                                 */
8756 
8757         struct
8758         {
8759             __IOM uint32_t IDST : 16;  /*!< [15..0] Ingress Destination MAC Address for Mirror Filtering              */
8760             uint32_t            : 16;
8761         } MIRROR_IDST_1_b;
8762     };
8763 
8764     union
8765     {
8766         __IOM uint32_t MIRROR_ESRC_0;  /*!< (@ 0x0000005C) Egress Source MAC Address for Mirror Filtering
8767                                         *                  Register 0                                                 */
8768 
8769         struct
8770         {
8771             __IOM uint32_t ESRC : 32;  /*!< [31..0] Egress Source MAC Address for Mirror Filtering                    */
8772         } MIRROR_ESRC_0_b;
8773     };
8774 
8775     union
8776     {
8777         __IOM uint32_t MIRROR_ESRC_1;  /*!< (@ 0x00000060) Egress Source MAC Address for Mirror Filtering
8778                                         *                  Register 1                                                 */
8779 
8780         struct
8781         {
8782             __IOM uint32_t ESRC : 16;  /*!< [15..0] Egress Source MAC Address for Mirror Filtering                    */
8783             uint32_t            : 16;
8784         } MIRROR_ESRC_1_b;
8785     };
8786 
8787     union
8788     {
8789         __IOM uint32_t MIRROR_EDST_0;  /*!< (@ 0x00000064) Egress Destination MAC Address for Mirror Filtering
8790                                         *                  Register 0                                                 */
8791 
8792         struct
8793         {
8794             __IOM uint32_t EDST : 32;  /*!< [31..0] Egress Destination MAC Address for Mirror Filtering               */
8795         } MIRROR_EDST_0_b;
8796     };
8797 
8798     union
8799     {
8800         __IOM uint32_t MIRROR_EDST_1;  /*!< (@ 0x00000068) Egress Destination MAC Address for Mirror Filtering
8801                                         *                  Register 1                                                 */
8802 
8803         struct
8804         {
8805             __IOM uint32_t EDST : 16;  /*!< [15..0] Egress Destination MAC Address for Mirror Filtering               */
8806             uint32_t            : 16;
8807         } MIRROR_EDST_1_b;
8808     };
8809 
8810     union
8811     {
8812         __IOM uint32_t MIRROR_CNT;     /*!< (@ 0x0000006C) Mirror Filtering Count Value Register                      */
8813 
8814         struct
8815         {
8816             __IOM uint32_t CNT : 8;    /*!< [7..0] Count Value for Mirror Filtering                                   */
8817             uint32_t           : 24;
8818         } MIRROR_CNT_b;
8819     };
8820 
8821     union
8822     {
8823         __IOM uint32_t UCAST_DEFAULT_MASK1; /*!< (@ 0x00000070) Unicast Default Mask Register 1                            */
8824 
8825         struct
8826         {
8827             __IOM uint32_t UCASTDM1 : 4;    /*!< [3..0] Default Unicast Resolution Mask 1                                  */
8828             uint32_t                : 28;
8829         } UCAST_DEFAULT_MASK1_b;
8830     };
8831 
8832     union
8833     {
8834         __IOM uint32_t BCAST_DEFAULT_MASK1; /*!< (@ 0x00000074) Broadcast Default Mask Register 1                          */
8835 
8836         struct
8837         {
8838             __IOM uint32_t BCASTDM1 : 4;    /*!< [3..0] Default Broadcast Resolution Mask 1                                */
8839             uint32_t                : 28;
8840         } BCAST_DEFAULT_MASK1_b;
8841     };
8842 
8843     union
8844     {
8845         __IOM uint32_t MCAST_DEFAULT_MASK1; /*!< (@ 0x00000078) Multicast Default Mask Register 1                          */
8846 
8847         struct
8848         {
8849             __IOM uint32_t MCASTDM1 : 4;    /*!< [3..0] Default Multicast Resolution Mask 1                                */
8850             uint32_t                : 28;
8851         } MCAST_DEFAULT_MASK1_b;
8852     };
8853 
8854     union
8855     {
8856         __IOM uint32_t PORT_XCAST_MASK_SEL; /*!< (@ 0x0000007C) Port Mask Select Register                                  */
8857 
8858         struct
8859         {
8860             __IOM uint32_t MSEL : 4;        /*!< [3..0] Mask Select                                                        */
8861             uint32_t            : 28;
8862         } PORT_XCAST_MASK_SEL_b;
8863     };
8864     __IM uint32_t RESERVED[2];
8865 
8866     union
8867     {
8868         __IOM uint32_t QMGR_ST_MINCELLS;    /*!< (@ 0x00000088) Minimum Memory Cell Statistics Register                    */
8869 
8870         struct
8871         {
8872             __IOM uint32_t STMINCELLS : 11; /*!< [10..0] Minimum Free Cell Indication                                      */
8873             uint32_t                  : 21;
8874         } QMGR_ST_MINCELLS_b;
8875     };
8876     __IM uint32_t RESERVED1[2];
8877 
8878     union
8879     {
8880         __IOM uint32_t QMGR_RED_MIN4;          /*!< (@ 0x00000094) RED Minimum Threshold Register                             */
8881 
8882         struct
8883         {
8884             __IOM uint32_t CFGRED_MINTH4 : 32; /*!< [31..0] Random Early Detection (RED) Minimum Threshold for Queues
8885                                                 *   0 to 3                                                                    */
8886         } QMGR_RED_MIN4_b;
8887     };
8888 
8889     union
8890     {
8891         __IOM uint32_t QMGR_RED_MAX4;          /*!< (@ 0x00000098) RED Maximum Threshold Register                             */
8892 
8893         struct
8894         {
8895             __IOM uint32_t CFGRED_MAXTH4 : 32; /*!< [31..0] Random Early Detection (RED) Maximum Threshold for Queues
8896                                                 *   0 to 3                                                                    */
8897         } QMGR_RED_MAX4_b;
8898     };
8899 
8900     union
8901     {
8902         __IOM uint32_t QMGR_RED_CONFIG;      /*!< (@ 0x0000009C) RED Configuration Register                                 */
8903 
8904         struct
8905         {
8906             __IOM uint32_t QUEUE_RED_EN : 4; /*!< [3..0] Enable Random Early Detection (RED) (when this bit is
8907                                               *   1) or Tail Drop (when this bit is 0) congestion management
8908                                               *   for a queue.                                                              */
8909             uint32_t                    : 4;
8910             __IOM uint32_t GACTIVITY_EN : 1; /*!< [8..8] Enable Averaging on Global Switch Activity (when this
8911                                               *   bit is 1) or on port local activity (when this bit is 0)
8912                                               *   only.                                                                     */
8913             uint32_t : 23;
8914         } QMGR_RED_CONFIG_b;
8915     };
8916 
8917     union
8918     {
8919         __IM uint32_t IMC_STATUS;               /*!< (@ 0x000000A0) Input Memory Controller Status Register                    */
8920 
8921         struct
8922         {
8923             __IM uint32_t CELLS_AVAILABLE : 24; /*!< [23..0] Total number of memory cells (128-byte units) available
8924                                                  *   in the shared memory (real time).                                         */
8925             __IM uint32_t CF_ERR  : 1;          /*!< [24..24] Cell Factory Empty Error                                         */
8926             __IM uint32_t DE_ERR  : 1;          /*!< [25..25] Deallocation Error                                               */
8927             __IM uint32_t DE_INIT : 1;          /*!< [26..26] Asserts during Memory Initialization (deallocation
8928                                                  *   module)                                                                   */
8929             __IM uint32_t MEM_FULL : 1;         /*!< [27..27] Latched Indication that Memory is or was Full                    */
8930             uint32_t               : 4;
8931         } IMC_STATUS_b;
8932     };
8933 
8934     union
8935     {
8936         __IM uint32_t IMC_ERR_FULL;          /*!< (@ 0x000000A4) Input Port Memory Full and Truncation Indicator
8937                                               *                  Register                                                   */
8938 
8939         struct
8940         {
8941             __IM uint32_t IPC_ERR_FULL  : 4; /*!< [3..0] Memory was full at start of a frame reception.                     */
8942             uint32_t                    : 12;
8943             __IM uint32_t IPC_ERR_TRUNC : 4; /*!< [19..16] Memory became full while a frame was received and was
8944                                               *   partly written into memory.                                               */
8945             uint32_t : 12;
8946         } IMC_ERR_FULL_b;
8947     };
8948 
8949     union
8950     {
8951         __IM uint32_t IMC_ERR_IFACE;         /*!< (@ 0x000000A8) Input Port Memory Error Indicator Register                 */
8952 
8953         struct
8954         {
8955             __IM uint32_t IPC_ERR_IFACE : 4; /*!< [3..0] Error indication on memory input (receive from MAC) that
8956                                               *   a frame has been truncated and discarded.                                 */
8957             uint32_t               : 12;
8958             __IM uint32_t WBUF_OVF : 4;      /*!< [19..16] Error indicating an overflow in the input write buffer
8959                                               *   to the memory controller (a small decoupling FIFO at every
8960                                               *   MAC RX).                                                                  */
8961             uint32_t : 12;
8962         } IMC_ERR_IFACE_b;
8963     };
8964 
8965     union
8966     {
8967         __IM uint32_t IMC_ERR_QOFLOW;  /*!< (@ 0x000000AC) Output Port Queue Overflow Indicator Register              */
8968 
8969         struct
8970         {
8971             __IM uint32_t OP_ERR : 4;  /*!< [3..0] A frame cannot be stored in an output queue of the port
8972                                         *   as the queue FIFO overflowed (write occurred into full
8973                                         *   fifo). The frame is ignored but stays stored in memory.
8974                                         *   This should not occur during normal operation. This is
8975                                         *   a fatal error as the memory allocated by that frame is
8976                                         *   not freed, and resulting in memory leakage.                               */
8977             uint32_t : 28;
8978         } IMC_ERR_QOFLOW_b;
8979     };
8980 
8981     union
8982     {
8983         __IOM uint32_t IMC_CONFIG;              /*!< (@ 0x000000B0) Input Memory Controller Configuration Register             */
8984 
8985         struct
8986         {
8987             __IOM uint32_t WFQ_EN : 1;          /*!< [0..0] Enable weighted fair queuing (when this bit is 1) or
8988                                                  *   strict priority (when this bit is 0, default) output queue
8989                                                  *   scheduling.                                                               */
8990             __IOM uint32_t RSV_ENA         : 1; /*!< [1..1] Enable Memory Reservations to Operate                              */
8991             __IOM uint32_t SPEED_HIPRI_THR : 3; /*!< [4..2] High-Priority Speed Threshold                                      */
8992             __IOM uint32_t CTFL_EMPTY_MD   : 1; /*!< [5..5] When this bit is set to 0, a frame received in Cut-Through
8993                                                  *   mode that cannot allocate an entry in the CTFL is forwarded
8994                                                  *   as store and forward.                                                     */
8995             uint32_t : 26;
8996         } IMC_CONFIG_b;
8997     };
8998 
8999     union
9000     {
9001         __IM uint32_t IMC_ERR_ALLOC;     /*!< (@ 0x000000B4) Input Port Error Indicator Register                        */
9002 
9003         struct
9004         {
9005             __IM uint32_t DISC_FULL : 4; /*!< [3..0] Per port discard indication due to memory pool going
9006                                           *   empty. Per port indication that one of the queues was full
9007                                           *   and a frame was discarded.                                                */
9008             uint32_t                : 12;
9009             __IM uint32_t DISC_LATE : 4; /*!< [19..16] Per port discard indication due to lateness in the
9010                                           *   priority resolution. The priority resolution can be delayed
9011                                           *   by the pattern matchers. If it arrives too late (after
9012                                           *   approximately 100 bytes into the frame), the frame is discarded.          */
9013             uint32_t : 12;
9014         } IMC_ERR_ALLOC_b;
9015     };
9016     __IM uint32_t RESERVED2[2];
9017 
9018     union
9019     {
9020         __IOM uint32_t GPARSER0;             /*!< (@ 0x000000C0) [n + 1]th Parser of 1st Block                              */
9021 
9022         struct
9023         {
9024             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9025                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9026                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9027                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9028                                               *   then compared to the compare value. All bits having a 1
9029                                               *   in the mask will be compared with the data in the frame.
9030                                               *   All bits having a 0 will be 0 for the compare, however
9031                                               *   this requires the compare value to have those bits also
9032                                               *   set to 0.                                                                 */
9033             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9034                                               *   offset.                                                                   */
9035             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
9036                                               *   within the frame. The offset value starts at 0 to indicate
9037                                               *   the very first byte after offset start. The offset start
9038                                               *   can be either the type/length field of the frame, that
9039                                               *   is, 0 = first byte of type/length field) or the payload
9040                                               *   following an IP header (see IPDATA). Valid values range
9041                                               *   from 0 to 60.                                                             */
9042             uint32_t                 : 1;
9043             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9044                                               *   byte of the MAC destination address.                                      */
9045             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
9046                                               *   1) and should be used. When this bit is 0, the parser result
9047                                               *   always indicates "no match" and none of the other bits
9048                                               *   are relevant.                                                             */
9049             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9050                                               *   are skipped and the parser starts operating at the first
9051                                               *   byte following any VLAN tags. When cleared, the parser
9052                                               *   starts with the first byte following the source MAC address.              */
9053             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9054                                               *   an IP header if an IP frame is processed. The following
9055                                               *   fields are skipped:                                                       */
9056             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9057                                               *   field found within the IP header for both IPv4 and IPv6
9058                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9059                                               *   VLAN tags if present. The offset setting has no meaning
9060                                               *   and is ignored.                                                           */
9061             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9062                                               *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
9063                                               *   the given offset and MASK_VAL2[7:0] represent the byte
9064                                               *   following at offset + 1 which matches the network byte
9065                                               *   order for 16-bit fields. For example, setting a compare
9066                                               *   value of 0x0800 and offset 0 matches IP frames. No mask
9067                                               *   is available in this mode.                                                */
9068             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9069                                               *   at offset failed.                                                         */
9070             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
9071                                               *   When set, the parser reports a match if the byte at given
9072                                               *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
9073             uint32_t : 1;
9074         } GPARSER0_b;
9075     };
9076 
9077     union
9078     {
9079         __IOM uint32_t GPARSER1;             /*!< (@ 0x000000C4) [n + 1]th Parser of 1st Block                              */
9080 
9081         struct
9082         {
9083             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9084                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9085                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9086                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9087                                               *   then compared to the compare value. All bits having a 1
9088                                               *   in the mask will be compared with the data in the frame.
9089                                               *   All bits having a 0 will be 0 for the compare, however
9090                                               *   this requires the compare value to have those bits also
9091                                               *   set to 0.                                                                 */
9092             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9093                                               *   offset.                                                                   */
9094             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
9095                                               *   within the frame. The offset value starts at 0 to indicate
9096                                               *   the very first byte after offset start. The offset start
9097                                               *   can be either the type/length field of the frame, that
9098                                               *   is, 0 = first byte of type/length field) or the payload
9099                                               *   following an IP header (see IPDATA). Valid values range
9100                                               *   from 0 to 60.                                                             */
9101             uint32_t                 : 1;
9102             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9103                                               *   byte of the MAC destination address.                                      */
9104             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
9105                                               *   1) and should be used. When this bit is 0, the parser result
9106                                               *   always indicates "no match" and none of the other bits
9107                                               *   are relevant.                                                             */
9108             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9109                                               *   are skipped and the parser starts operating at the first
9110                                               *   byte following any VLAN tags. When cleared, the parser
9111                                               *   starts with the first byte following the source MAC address.              */
9112             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9113                                               *   an IP header if an IP frame is processed. The following
9114                                               *   fields are skipped:                                                       */
9115             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9116                                               *   field found within the IP header for both IPv4 and IPv6
9117                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9118                                               *   VLAN tags if present. The offset setting has no meaning
9119                                               *   and is ignored.                                                           */
9120             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9121                                               *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
9122                                               *   the given offset and MASK_VAL2[7:0] represent the byte
9123                                               *   following at offset + 1 which matches the network byte
9124                                               *   order for 16-bit fields. For example, setting a compare
9125                                               *   value of 0x0800 and offset 0 matches IP frames. No mask
9126                                               *   is available in this mode.                                                */
9127             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9128                                               *   at offset failed.                                                         */
9129             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
9130                                               *   When set, the parser reports a match if the byte at given
9131                                               *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
9132             uint32_t : 1;
9133         } GPARSER1_b;
9134     };
9135 
9136     union
9137     {
9138         __IOM uint32_t GPARSER2;             /*!< (@ 0x000000C8) [n + 1]th Parser of 1st Block                              */
9139 
9140         struct
9141         {
9142             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9143                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9144                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9145                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9146                                               *   then compared to the compare value. All bits having a 1
9147                                               *   in the mask will be compared with the data in the frame.
9148                                               *   All bits having a 0 will be 0 for the compare, however
9149                                               *   this requires the compare value to have those bits also
9150                                               *   set to 0.                                                                 */
9151             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9152                                               *   offset.                                                                   */
9153             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
9154                                               *   within the frame. The offset value starts at 0 to indicate
9155                                               *   the very first byte after offset start. The offset start
9156                                               *   can be either the type/length field of the frame, that
9157                                               *   is, 0 = first byte of type/length field) or the payload
9158                                               *   following an IP header (see IPDATA). Valid values range
9159                                               *   from 0 to 60.                                                             */
9160             uint32_t                 : 1;
9161             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9162                                               *   byte of the MAC destination address.                                      */
9163             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
9164                                               *   1) and should be used. When this bit is 0, the parser result
9165                                               *   always indicates "no match" and none of the other bits
9166                                               *   are relevant.                                                             */
9167             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9168                                               *   are skipped and the parser starts operating at the first
9169                                               *   byte following any VLAN tags. When cleared, the parser
9170                                               *   starts with the first byte following the source MAC address.              */
9171             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9172                                               *   an IP header if an IP frame is processed. The following
9173                                               *   fields are skipped:                                                       */
9174             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9175                                               *   field found within the IP header for both IPv4 and IPv6
9176                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9177                                               *   VLAN tags if present. The offset setting has no meaning
9178                                               *   and is ignored.                                                           */
9179             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9180                                               *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
9181                                               *   the given offset and MASK_VAL2[7:0] represent the byte
9182                                               *   following at offset + 1 which matches the network byte
9183                                               *   order for 16-bit fields. For example, setting a compare
9184                                               *   value of 0x0800 and offset 0 matches IP frames. No mask
9185                                               *   is available in this mode.                                                */
9186             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9187                                               *   at offset failed.                                                         */
9188             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
9189                                               *   When set, the parser reports a match if the byte at given
9190                                               *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
9191             uint32_t : 1;
9192         } GPARSER2_b;
9193     };
9194 
9195     union
9196     {
9197         __IOM uint32_t GPARSER3;             /*!< (@ 0x000000CC) [n + 1]th Parser of 1st Block                              */
9198 
9199         struct
9200         {
9201             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9202                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9203                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9204                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9205                                               *   then compared to the compare value. All bits having a 1
9206                                               *   in the mask will be compared with the data in the frame.
9207                                               *   All bits having a 0 will be 0 for the compare, however
9208                                               *   this requires the compare value to have those bits also
9209                                               *   set to 0.                                                                 */
9210             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9211                                               *   offset.                                                                   */
9212             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes where to find the data for comparison
9213                                               *   within the frame. The offset value starts at 0 to indicate
9214                                               *   the very first byte after offset start. The offset start
9215                                               *   can be either the type/length field of the frame, that
9216                                               *   is, 0 = first byte of type/length field) or the payload
9217                                               *   following an IP header (see IPDATA). Valid values range
9218                                               *   from 0 to 60.                                                             */
9219             uint32_t                 : 1;
9220             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9221                                               *   byte of the MAC destination address.                                      */
9222             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicate that this entry is valid (when this bit is
9223                                               *   1) and should be used. When this bit is 0, the parser result
9224                                               *   always indicates "no match" and none of the other bits
9225                                               *   are relevant.                                                             */
9226             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9227                                               *   are skipped and the parser starts operating at the first
9228                                               *   byte following any VLAN tags. When cleared, the parser
9229                                               *   starts with the first byte following the source MAC address.              */
9230             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9231                                               *   an IP header if an IP frame is processed. The following
9232                                               *   fields are skipped:                                                       */
9233             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9234                                               *   field found within the IP header for both IPv4 and IPv6
9235                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9236                                               *   VLAN tags if present. The offset setting has no meaning
9237                                               *   and is ignored.                                                           */
9238             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9239                                               *   a 16-bit compare. COMPARE_VAL[7:0] represent the byte at
9240                                               *   the given offset and MASK_VAL2[7:0] represent the byte
9241                                               *   following at offset + 1 which matches the network byte
9242                                               *   order for 16-bit fields. For example, setting a compare
9243                                               *   value of 0x0800 and offset 0 matches IP frames. No mask
9244                                               *   is available in this mode.                                                */
9245             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9246                                               *   at offset failed.                                                         */
9247             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value.
9248                                               *   When set, the parser reports a match if the byte at given
9249                                               *   offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                        */
9250             uint32_t : 1;
9251         } GPARSER3_b;
9252     };
9253 
9254     union
9255     {
9256         __IOM uint32_t GARITH0;            /*!< (@ 0x000000D0) Snoop Configuration for Arithmetic [n + 1]th
9257                                             *                  Stage of 1st Block                                         */
9258 
9259         struct
9260         {
9261             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9262             uint32_t                  : 4;
9263             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9264             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9265             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9266             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9267             uint32_t                  : 1;
9268             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9269             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9270             uint32_t                  : 2;
9271             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9272             uint32_t                  : 10;
9273         } GARITH0_b;
9274     };
9275 
9276     union
9277     {
9278         __IOM uint32_t GARITH1;            /*!< (@ 0x000000D4) Snoop Configuration for Arithmetic [n + 1]th
9279                                             *                  Stage of 1st Block                                         */
9280 
9281         struct
9282         {
9283             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9284             uint32_t                  : 4;
9285             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9286             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9287             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9288             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9289             uint32_t                  : 1;
9290             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9291             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9292             uint32_t                  : 2;
9293             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9294             uint32_t                  : 10;
9295         } GARITH1_b;
9296     };
9297 
9298     union
9299     {
9300         __IOM uint32_t GARITH2;            /*!< (@ 0x000000D8) Snoop Configuration for Arithmetic [n + 1]th
9301                                             *                  Stage of 1st Block                                         */
9302 
9303         struct
9304         {
9305             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9306             uint32_t                  : 4;
9307             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9308             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9309             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9310             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9311             uint32_t                  : 1;
9312             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9313             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9314             uint32_t                  : 2;
9315             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9316             uint32_t                  : 10;
9317         } GARITH2_b;
9318     };
9319 
9320     union
9321     {
9322         __IOM uint32_t GARITH3;            /*!< (@ 0x000000DC) Snoop Configuration for Arithmetic [n + 1]th
9323                                             *                  Stage of 1st Block                                         */
9324 
9325         struct
9326         {
9327             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9328             uint32_t                  : 4;
9329             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9330             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9331             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9332             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9333             uint32_t                  : 1;
9334             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9335             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9336             uint32_t                  : 2;
9337             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9338             uint32_t                  : 10;
9339         } GARITH3_b;
9340     };
9341 
9342     union
9343     {
9344         __IOM uint32_t GPARSER4;             /*!< (@ 0x000000E0) [n - 3]th Parser of 2nd Block                              */
9345 
9346         struct
9347         {
9348             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9349                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9350                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9351                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9352                                               *   then compared to the compare value. All bits having a 1
9353                                               *   in the mask are compared with the data in the frame. All
9354                                               *   bits having a 0 will be 0 for the compare, however this
9355                                               *   requires the compare value to have those bits also set
9356                                               *   to 0.                                                                     */
9357             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9358                                               *   offset.                                                                   */
9359             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
9360                                               *   within the frame. The offset value starts at 0 to indicate
9361                                               *   the very first byte after offset start. The offset start
9362                                               *   can be either the type or length field of the frame, for
9363                                               *   example 0 = first byte of type/length field) or the payload
9364                                               *   following an IP header (see bit 26). Valid values range
9365                                               *   from 0 to 60.                                                             */
9366             uint32_t                 : 1;
9367             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9368                                               *   byte of the MAC destination address.                                      */
9369             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
9370                                               *   1) and should be used. When this bit is 0, the parser result
9371                                               *   always indicates "no match" and none of the other bits
9372                                               *   are relevant.                                                             */
9373             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9374                                               *   are skipped and the parser starts operating at the first
9375                                               *   byte following any VLAN tags. When cleared, the parser
9376                                               *   starts with the first byte following the source MAC address.              */
9377             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9378                                               *   an IP header if an IP frame is processed. The following
9379                                               *   fields are skipped:                                                       */
9380             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9381                                               *   field located within the IP header for both IPv4 and IPv6
9382                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9383                                               *   VLAN tags if present. The offset setting has no meaning
9384                                               *   and is ignored. If the bit is set, but the frame is not
9385                                               *   an IPv4/v6 frame the parser reports a no match and does
9386                                               *   not continue to inspect the frame. When cleared, the offset
9387                                               *   is used normally on all frames.                                           */
9388             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9389                                               *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
9390                                               *   at the given offset and MASK_VAL2[7:0] represents the byte
9391                                               *   following at offset + 1 which matches the network byte
9392                                               *   order for 16-bit fields, (for example setting a compare
9393                                               *   value of 0x0800 and offset 0 matches IP frames). No mask
9394                                               *   is available in this mode.                                                */
9395             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9396                                               *   at offset failed.                                                         */
9397             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
9398                                               *   set, the parser reports a match if the byte at given offset
9399                                               *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
9400             uint32_t : 1;
9401         } GPARSER4_b;
9402     };
9403 
9404     union
9405     {
9406         __IOM uint32_t GPARSER5;             /*!< (@ 0x000000E4) [n - 3]th Parser of 2nd Block                              */
9407 
9408         struct
9409         {
9410             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9411                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9412                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9413                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9414                                               *   then compared to the compare value. All bits having a 1
9415                                               *   in the mask are compared with the data in the frame. All
9416                                               *   bits having a 0 will be 0 for the compare, however this
9417                                               *   requires the compare value to have those bits also set
9418                                               *   to 0.                                                                     */
9419             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9420                                               *   offset.                                                                   */
9421             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
9422                                               *   within the frame. The offset value starts at 0 to indicate
9423                                               *   the very first byte after offset start. The offset start
9424                                               *   can be either the type or length field of the frame, for
9425                                               *   example 0 = first byte of type/length field) or the payload
9426                                               *   following an IP header (see bit 26). Valid values range
9427                                               *   from 0 to 60.                                                             */
9428             uint32_t                 : 1;
9429             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9430                                               *   byte of the MAC destination address.                                      */
9431             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
9432                                               *   1) and should be used. When this bit is 0, the parser result
9433                                               *   always indicates "no match" and none of the other bits
9434                                               *   are relevant.                                                             */
9435             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9436                                               *   are skipped and the parser starts operating at the first
9437                                               *   byte following any VLAN tags. When cleared, the parser
9438                                               *   starts with the first byte following the source MAC address.              */
9439             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9440                                               *   an IP header if an IP frame is processed. The following
9441                                               *   fields are skipped:                                                       */
9442             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9443                                               *   field located within the IP header for both IPv4 and IPv6
9444                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9445                                               *   VLAN tags if present. The offset setting has no meaning
9446                                               *   and is ignored. If the bit is set, but the frame is not
9447                                               *   an IPv4/v6 frame the parser reports a no match and does
9448                                               *   not continue to inspect the frame. When cleared, the offset
9449                                               *   is used normally on all frames.                                           */
9450             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9451                                               *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
9452                                               *   at the given offset and MASK_VAL2[7:0] represents the byte
9453                                               *   following at offset + 1 which matches the network byte
9454                                               *   order for 16-bit fields, (for example setting a compare
9455                                               *   value of 0x0800 and offset 0 matches IP frames). No mask
9456                                               *   is available in this mode.                                                */
9457             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9458                                               *   at offset failed.                                                         */
9459             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
9460                                               *   set, the parser reports a match if the byte at given offset
9461                                               *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
9462             uint32_t : 1;
9463         } GPARSER5_b;
9464     };
9465 
9466     union
9467     {
9468         __IOM uint32_t GPARSER6;             /*!< (@ 0x000000E8) [n - 3]th Parser of 2nd Block                              */
9469 
9470         struct
9471         {
9472             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9473                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9474                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9475                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9476                                               *   then compared to the compare value. All bits having a 1
9477                                               *   in the mask are compared with the data in the frame. All
9478                                               *   bits having a 0 will be 0 for the compare, however this
9479                                               *   requires the compare value to have those bits also set
9480                                               *   to 0.                                                                     */
9481             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9482                                               *   offset.                                                                   */
9483             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
9484                                               *   within the frame. The offset value starts at 0 to indicate
9485                                               *   the very first byte after offset start. The offset start
9486                                               *   can be either the type or length field of the frame, for
9487                                               *   example 0 = first byte of type/length field) or the payload
9488                                               *   following an IP header (see bit 26). Valid values range
9489                                               *   from 0 to 60.                                                             */
9490             uint32_t                 : 1;
9491             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9492                                               *   byte of the MAC destination address.                                      */
9493             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
9494                                               *   1) and should be used. When this bit is 0, the parser result
9495                                               *   always indicates "no match" and none of the other bits
9496                                               *   are relevant.                                                             */
9497             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9498                                               *   are skipped and the parser starts operating at the first
9499                                               *   byte following any VLAN tags. When cleared, the parser
9500                                               *   starts with the first byte following the source MAC address.              */
9501             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9502                                               *   an IP header if an IP frame is processed. The following
9503                                               *   fields are skipped:                                                       */
9504             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9505                                               *   field located within the IP header for both IPv4 and IPv6
9506                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9507                                               *   VLAN tags if present. The offset setting has no meaning
9508                                               *   and is ignored. If the bit is set, but the frame is not
9509                                               *   an IPv4/v6 frame the parser reports a no match and does
9510                                               *   not continue to inspect the frame. When cleared, the offset
9511                                               *   is used normally on all frames.                                           */
9512             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9513                                               *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
9514                                               *   at the given offset and MASK_VAL2[7:0] represents the byte
9515                                               *   following at offset + 1 which matches the network byte
9516                                               *   order for 16-bit fields, (for example setting a compare
9517                                               *   value of 0x0800 and offset 0 matches IP frames). No mask
9518                                               *   is available in this mode.                                                */
9519             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9520                                               *   at offset failed.                                                         */
9521             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
9522                                               *   set, the parser reports a match if the byte at given offset
9523                                               *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
9524             uint32_t : 1;
9525         } GPARSER6_b;
9526     };
9527 
9528     union
9529     {
9530         __IOM uint32_t GPARSER7;             /*!< (@ 0x000000EC) [n - 3]th Parser of 2nd Block                              */
9531 
9532         struct
9533         {
9534             __IOM uint32_t MASK_VAL2 : 8;    /*!< [7..0] Mask for single byte compares or 2nd compare value (if
9535                                               *   bit 30 = 1) or least significant bits of a 16-bit compare
9536                                               *   value (if bit 28 = 1). When used as a mask (bit 28, 30
9537                                               *   = 0, 0), the data from the frame is ANDed with this mask,
9538                                               *   then compared to the compare value. All bits having a 1
9539                                               *   in the mask are compared with the data in the frame. All
9540                                               *   bits having a 0 will be 0 for the compare, however this
9541                                               *   requires the compare value to have those bits also set
9542                                               *   to 0.                                                                     */
9543             __IOM uint32_t COMPARE_VAL : 8;  /*!< [15..8] The value to compare the frame data with at the given
9544                                               *   offset.                                                                   */
9545             __IOM uint32_t OFFSET : 6;       /*!< [21..16] An offset in bytes to locate the data for comparison
9546                                               *   within the frame. The offset value starts at 0 to indicate
9547                                               *   the very first byte after offset start. The offset start
9548                                               *   can be either the type or length field of the frame, for
9549                                               *   example 0 = first byte of type/length field) or the payload
9550                                               *   following an IP header (see bit 26). Valid values range
9551                                               *   from 0 to 60.                                                             */
9552             uint32_t                 : 1;
9553             __IOM uint32_t OFFSET_DA : 1;    /*!< [23..23] When set, the offset starts counting from the first
9554                                               *   byte of the MAC destination address.                                      */
9555             __IOM uint32_t VALID : 1;        /*!< [24..24] Indicates that this entry is valid (when this bit is
9556                                               *   1) and should be used. When this bit is 0, the parser result
9557                                               *   always indicates "no match" and none of the other bits
9558                                               *   are relevant.                                                             */
9559             __IOM uint32_t SKIPVLAN : 1;     /*!< [25..25] When set, any optional VLAN tags found in the frame
9560                                               *   are skipped and the parser starts operating at the first
9561                                               *   byte following any VLAN tags. When cleared, the parser
9562                                               *   starts with the first byte following the source MAC address.              */
9563             __IOM uint32_t IPDATA : 1;       /*!< [26..26] When set, the offset starts with the first byte following
9564                                               *   an IP header if an IP frame is processed. The following
9565                                               *   fields are skipped:                                                       */
9566             __IOM uint32_t IPPROTOCOL : 1;   /*!< [27..27] When set, the compare value is compared with the protocol
9567                                               *   field located within the IP header for both IPv4 and IPv6
9568                                               *   frames. It implicitly acts as SKIPVLAN = 1 skipping any
9569                                               *   VLAN tags if present. The offset setting has no meaning
9570                                               *   and is ignored. If the bit is set, but the frame is not
9571                                               *   an IPv4/v6 frame the parser reports a no match and does
9572                                               *   not continue to inspect the frame. When cleared, the offset
9573                                               *   is used normally on all frames.                                           */
9574             __IOM uint32_t CMP16 : 1;        /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform
9575                                               *   a 16-bit compare. COMPARE_VAL[7:0] represents the byte
9576                                               *   at the given offset and MASK_VAL2[7:0] represents the byte
9577                                               *   following at offset + 1 which matches the network byte
9578                                               *   order for 16-bit fields, (for example setting a compare
9579                                               *   value of 0x0800 and offset 0 matches IP frames). No mask
9580                                               *   is available in this mode.                                                */
9581             __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison
9582                                               *   at offset failed.                                                         */
9583             __IOM uint32_t CMP_MASK_OR : 1;  /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When
9584                                               *   set, the parser reports a match if the byte at given offset
9585                                               *   matches COMPARE_VAL[7:0] or MASK_VAL2[7:0].                               */
9586             uint32_t : 1;
9587         } GPARSER7_b;
9588     };
9589 
9590     union
9591     {
9592         __IOM uint32_t GARITH4;            /*!< (@ 0x000000F0) Snoop Configuration for Arithmetic [n - 3]th
9593                                             *                  Stage of 2nd Block                                         */
9594 
9595         struct
9596         {
9597             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9598             uint32_t                  : 4;
9599             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9600             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9601             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9602             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9603             uint32_t                  : 1;
9604             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9605             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9606             uint32_t                  : 2;
9607             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9608             uint32_t                  : 10;
9609         } GARITH4_b;
9610     };
9611 
9612     union
9613     {
9614         __IOM uint32_t GARITH5;            /*!< (@ 0x000000F4) Snoop Configuration for Arithmetic [n - 3]th
9615                                             *                  Stage of 2nd Block                                         */
9616 
9617         struct
9618         {
9619             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9620             uint32_t                  : 4;
9621             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9622             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9623             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9624             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9625             uint32_t                  : 1;
9626             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9627             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9628             uint32_t                  : 2;
9629             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9630             uint32_t                  : 10;
9631         } GARITH5_b;
9632     };
9633 
9634     union
9635     {
9636         __IOM uint32_t GARITH6;            /*!< (@ 0x000000F8) Snoop Configuration for Arithmetic [n - 3]th
9637                                             *                  Stage of 2nd Block                                         */
9638 
9639         struct
9640         {
9641             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9642             uint32_t                  : 4;
9643             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9644             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9645             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9646             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9647             uint32_t                  : 1;
9648             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9649             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9650             uint32_t                  : 2;
9651             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9652             uint32_t                  : 10;
9653         } GARITH6_b;
9654     };
9655 
9656     union
9657     {
9658         __IOM uint32_t GARITH7;            /*!< (@ 0x000000FC) Snoop Configuration for Arithmetic [n - 3]th
9659                                             *                  Stage of 2nd Block                                         */
9660 
9661         struct
9662         {
9663             __IOM uint32_t NOT_INP    : 4; /*!< [3..0] Not Input                                                          */
9664             uint32_t                  : 4;
9665             __IOM uint32_t SEL_MATCH  : 4; /*!< [11..8] Select Match                                                      */
9666             __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0                                        */
9667             __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1                                        */
9668             __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2                                        */
9669             uint32_t                  : 1;
9670             __IOM uint32_t OP         : 1; /*!< [16..16] Operation                                                        */
9671             __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert                                                    */
9672             uint32_t                  : 2;
9673             __IOM uint32_t SNP_MD     : 2; /*!< [21..20] Snoop Mode                                                       */
9674             uint32_t                  : 10;
9675         } GARITH7_b;
9676     };
9677 
9678     union
9679     {
9680         __IOM uint32_t VLAN_PRIORITY[4];  /*!< (@ 0x00000100) VLAN Priority Register [0..3]                              */
9681 
9682         struct
9683         {
9684             __IOM uint32_t PRIORITY0 : 3; /*!< [2..0] Priority 0 Setting                                                 */
9685             __IOM uint32_t PRIORITY1 : 3; /*!< [5..3] Priority 1 Setting                                                 */
9686             __IOM uint32_t PRIORITY2 : 3; /*!< [8..6] Priority 2 Setting                                                 */
9687             __IOM uint32_t PRIORITY3 : 3; /*!< [11..9] Priority 3 Setting                                                */
9688             __IOM uint32_t PRIORITY4 : 3; /*!< [14..12] Priority 4 Setting                                               */
9689             __IOM uint32_t PRIORITY5 : 3; /*!< [17..15] Priority 5 Setting                                               */
9690             __IOM uint32_t PRIORITY6 : 3; /*!< [20..18] Priority 6 Setting                                               */
9691             __IOM uint32_t PRIORITY7 : 3; /*!< [23..21] Priority 7 Setting                                               */
9692             uint32_t                 : 8;
9693         } VLAN_PRIORITY_b[4];
9694     };
9695     __IM uint32_t RESERVED3[12];
9696 
9697     union
9698     {
9699         __IOM uint32_t IP_PRIORITY[4];     /*!< (@ 0x00000140) IP Priority Register [0..3]                                */
9700 
9701         struct
9702         {
9703             __IOM uint32_t ADDRESS    : 8; /*!< [7..0] COS Table Address Specifying                                       */
9704             __IOM uint32_t IPV6SELECT : 1; /*!< [8..8] IPv6 COS Table Selection                                           */
9705             __IOM uint32_t PRIORITY   : 3; /*!< [11..9] COS Table Priority                                                */
9706             uint32_t                  : 19;
9707             __IOM uint32_t READ       : 1; /*!< [31..31] COS Table Operation Switching                                    */
9708         } IP_PRIORITY_b[4];
9709     };
9710     __IM uint32_t RESERVED4[12];
9711 
9712     union
9713     {
9714         __IOM uint32_t PRIORITY_CFG[4];        /*!< (@ 0x00000180) Priority Configuration Register [0..3]                     */
9715 
9716         struct
9717         {
9718             __IOM uint32_t VLANEN        : 1;  /*!< [0..0] VLAN Priority Enable                                               */
9719             __IOM uint32_t IPEN          : 1;  /*!< [1..1] IP Priority Enable                                                 */
9720             __IOM uint32_t MACEN         : 1;  /*!< [2..2] MAC Based Priority Enable                                          */
9721             __IOM uint32_t TYPE_EN       : 1;  /*!< [3..3] TYPE Based Priority Enable                                         */
9722             __IOM uint32_t DEFAULTPRI    : 3;  /*!< [6..4] Default Priority Enable Setting                                    */
9723             __IOM uint32_t PCP_REMAP_DIS : 1;  /*!< [7..7] Disables PCP remapping when set to 1.                              */
9724             __IOM uint32_t PCP_REMAP     : 24; /*!< [31..8] PCP Remapping function                                            */
9725         } PRIORITY_CFG_b[4];
9726     };
9727     __IM uint32_t RESERVED5[10];
9728 
9729     union
9730     {
9731         __IOM uint32_t PRIORITY_TYPE1;    /*!< (@ 0x000001B8) Priority Type Register 1                                   */
9732 
9733         struct
9734         {
9735             __IOM uint32_t TYPEVAL  : 16; /*!< [15..0] Type Priority                                                     */
9736             __IOM uint32_t VALID    : 1;  /*!< [16..16] If set indicates, this register contains valid data.             */
9737             __IOM uint32_t PRIORITY : 3;  /*!< [19..17] The priority value to use if a match occurs.                     */
9738             uint32_t                : 12;
9739         } PRIORITY_TYPE1_b;
9740     };
9741 
9742     union
9743     {
9744         __IOM uint32_t PRIORITY_TYPE2;         /*!< (@ 0x000001BC) Priority Type Register 2                                   */
9745 
9746         struct
9747         {
9748             __IOM uint32_t TYPEVAL  : 16;      /*!< [15..0] Type Priority                                                     */
9749             __IOM uint32_t VALID    : 1;       /*!< [16..16] If set indicates, this register contains valid data.             */
9750             __IOM uint32_t PRIORITY : 3;       /*!< [19..17] The priority value to use if a match occurs.                     */
9751             uint32_t                : 12;
9752         } PRIORITY_TYPE2_b;
9753     };
9754     __IOM R_ETHSW_MGMT_ADDR_Type MGMT_ADDR[4]; /*!< (@ 0x000001C0) MAC Address [0..3] for Bridge Protocol Frame
9755                                                 *                  Register                                                   */
9756 
9757     union
9758     {
9759         __IOM uint32_t SRCFLT_ENA;             /*!< (@ 0x000001E0) MAC Source Address Filtering Enable Register               */
9760 
9761         struct
9762         {
9763             __IOM uint32_t SRCENA : 3;         /*!< [2..0] Per-Source Port Enable                                             */
9764             uint32_t              : 13;
9765             __IOM uint32_t DSTENA : 4;         /*!< [19..16] Per-Destination Port Enable                                      */
9766             uint32_t              : 12;
9767         } SRCFLT_ENA_b;
9768     };
9769 
9770     union
9771     {
9772         __IOM uint32_t SRCFLT_CONTROL;         /*!< (@ 0x000001E4) MAC Source Address Filtering Control Register              */
9773 
9774         struct
9775         {
9776             __IOM uint32_t MGMT_FWD      : 1;  /*!< [0..0] Management Forward Enable                                          */
9777             __IOM uint32_t WATCHDOG_ENA  : 1;  /*!< [1..1] When set to 1, a watchdog is enabled.                              */
9778             uint32_t                     : 14;
9779             __IOM uint32_t WATCHDOG_TIME : 16; /*!< [31..16] Defines the watchdog expire time in milliseconds. The
9780                                                 *   default is 2000 milliseconds.                                             */
9781         } SRCFLT_CONTROL_b;
9782     };
9783 
9784     union
9785     {
9786         __IOM uint32_t SRCFLT_MACADDR_LO;       /*!< (@ 0x000001E8) Lower MAC Filtering Address Register                       */
9787 
9788         struct
9789         {
9790             __IOM uint32_t SRCFLT_MACADDR : 32; /*!< [31..0] MAC address to use in source filtering                            */
9791         } SRCFLT_MACADDR_LO_b;
9792     };
9793 
9794     union
9795     {
9796         __IOM uint32_t SRCFLT_MACADDR_HI;       /*!< (@ 0x000001EC) Higher MAC Filtering Address Register                      */
9797 
9798         struct
9799         {
9800             __IOM uint32_t SRCFLT_MACADDR : 16; /*!< [15..0] MAC address to use in source filtering                            */
9801             __IOM uint32_t MASK           : 16; /*!< [31..16] The mask to apply to the last 16 bits of the MAC address         */
9802         } SRCFLT_MACADDR_HI_b;
9803     };
9804     __IM uint32_t RESERVED6[3];
9805 
9806     union
9807     {
9808         __IOM uint32_t PHY_FILTER_CFG;          /*!< (@ 0x000001FC) Debounce Filter Configuration Register                     */
9809 
9810         struct
9811         {
9812             __IOM uint32_t FILTER_DURATION : 9; /*!< [8..0] This is the amount of time to wait after the last phy_link
9813                                                  *   (ETHSW_PHYLINKn: n = port) transition from 0 to 1 to acknowledge
9814                                                  *   the link-up condition.                                                    */
9815             uint32_t              : 7;
9816             __IOM uint32_t FLT_EN : 3;          /*!< [18..16] Per-port Enable Mask                                             */
9817             uint32_t              : 13;
9818         } PHY_FILTER_CFG_b;
9819     };
9820 
9821     union
9822     {
9823         __IOM uint32_t SYSTEM_TAGINFO[4];    /*!< (@ 0x00000200) One VLAN ID Field [0..3] for VLAN Input Manipulation       */
9824 
9825         struct
9826         {
9827             __IOM uint32_t SYSVLANINFO : 16; /*!< [15..0] System VLAN Info (prio/cfi/vid) for Port n                        */
9828             uint32_t                   : 16;
9829         } SYSTEM_TAGINFO_b[4];
9830     };
9831     __IM uint32_t RESERVED7[12];
9832 
9833     union
9834     {
9835         __IOM uint32_t AUTH_PORT[4];        /*!< (@ 0x00000240) Port [0..3] Authentication Control and Configuration       */
9836 
9837         struct
9838         {
9839             __IOM uint32_t AUTH        : 1; /*!< [0..0] Authorized                                                         */
9840             __IOM uint32_t CTRL_BOTH   : 1; /*!< [1..1] Controlled Both                                                    */
9841             __IOM uint32_t EAPOL_EN    : 1; /*!< [2..2] EAPOL Enable                                                       */
9842             __IOM uint32_t GUEST_EN    : 1; /*!< [3..3] Guest Enable                                                       */
9843             __IOM uint32_t BPDU_EN     : 1; /*!< [4..4] BPDU Enable                                                        */
9844             __IOM uint32_t EAPOL_UC_EN : 1; /*!< [5..5] EAPOL Unicast Enable                                               */
9845             uint32_t                   : 5;
9846             __IOM uint32_t ACHG_UNAUTH : 1; /*!< [11..11] Automatic Port Change to Unauthorized                            */
9847             __IOM uint32_t EAPOL_PNUM  : 4; /*!< [15..12] EAPOL Port Number                                                */
9848             __IOM uint32_t GUEST_MASK  : 4; /*!< [19..16] Destination port mask with all ports that are allowed
9849                                              *   to receive non-EAPOL frames from this port while it is
9850                                              *   unauthorized and guest (GUEST_EN) is enabled.                             */
9851             uint32_t : 12;
9852         } AUTH_PORT_b[4];
9853     };
9854     __IM uint32_t RESERVED8[12];
9855 
9856     union
9857     {
9858         __IOM uint32_t VLAN_RES_TABLE[32]; /*!< (@ 0x00000280) 32 VLAN Domain Entries                                     */
9859 
9860         struct
9861         {
9862             __IOM uint32_t PORTMASK : 4;   /*!< [3..0] When this bit is set to 1, it defines a port as a member
9863                                             *   of the VLAN. When bit [28] or bit [29] is set, the tagged
9864                                             *   bit mask is read/written instead of port mask.                            */
9865             __IOM uint32_t VLANID    : 12; /*!< [15..4] The 12-bit VLAN identifier (VLAN ID) of the entry.                */
9866             uint32_t                 : 12;
9867             __IOM uint32_t RD_TAGMSK : 1;  /*!< [28..28] Read TAG Mask                                                    */
9868             __IOM uint32_t WT_TAGMSK : 1;  /*!< [29..29] Write TAG Mask                                                   */
9869             __IOM uint32_t WT_PRTMSK : 1;  /*!< [30..30] Write Port Mask                                                  */
9870             uint32_t                 : 1;
9871         } VLAN_RES_TABLE_b[32];
9872     };
9873 
9874     union
9875     {
9876         __IM uint32_t TOTAL_DISC;          /*!< (@ 0x00000300) Discarded Frame Total Number Register                      */
9877 
9878         struct
9879         {
9880             __IM uint32_t TOTAL_DISC : 32; /*!< [31..0] Total number of incoming frames accepted by MAC RX but
9881                                             *   discarded in the switch                                                   */
9882         } TOTAL_DISC_b;
9883     };
9884 
9885     union
9886     {
9887         __IM uint32_t TOTAL_BYT_DISC;          /*!< (@ 0x00000304) Discarded Frame Total Bytes Register                       */
9888 
9889         struct
9890         {
9891             __IM uint32_t TOTAL_BYT_DISC : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_DISC                      */
9892         } TOTAL_BYT_DISC_b;
9893     };
9894 
9895     union
9896     {
9897         __IM uint32_t TOTAL_FRM;          /*!< (@ 0x00000308) Processed Frame Total Number Register                      */
9898 
9899         struct
9900         {
9901             __IM uint32_t TOTAL_FRM : 32; /*!< [31..0] Total number of incoming frames processed by the switch           */
9902         } TOTAL_FRM_b;
9903     };
9904 
9905     union
9906     {
9907         __IM uint32_t TOTAL_BYT_FRM;          /*!< (@ 0x0000030C) Processed Frame Total Bytes Register                       */
9908 
9909         struct
9910         {
9911             __IM uint32_t TOTAL_BYT_FRM : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_FRM                       */
9912         } TOTAL_BYT_FRM_b;
9913     };
9914     __IM uint32_t RESERVED9[12];
9915 
9916     union
9917     {
9918         __IOM uint32_t IALK_CONTROL;        /*!< (@ 0x00000340) IA Lookup Function Enable Register                         */
9919 
9920         struct
9921         {
9922             __IOM uint32_t IA_LKUP_ENA : 4; /*!< [3..0] Per-port Enable to the IA Lookup Table                             */
9923             uint32_t                   : 12;
9924             __IOM uint32_t CT_ENA      : 4; /*!< [19..16] Per-port Cut-Through Mode Enable                                 */
9925             uint32_t                   : 12;
9926         } IALK_CONTROL_b;
9927     };
9928 
9929     union
9930     {
9931         __IOM uint32_t IALK_OUI;          /*!< (@ 0x00000344) IA Frames MAC Address OUI Register                         */
9932 
9933         struct
9934         {
9935             __IOM uint32_t IALK_OUI : 24; /*!< [23..0] IA Frames MAC Address OUI                                         */
9936             uint32_t                : 8;
9937         } IALK_OUI_b;
9938     };
9939 
9940     union
9941     {
9942         __IOM uint32_t IALK_ID_MIN;          /*!< (@ 0x00000348) Minimum Value ID MAC Address Register                      */
9943 
9944         struct
9945         {
9946             __IOM uint32_t IALK_ID_MIN : 24; /*!< [23..0] Minimum value for the 24-bit ID in the MAC address                */
9947             uint32_t                   : 8;
9948         } IALK_ID_MIN_b;
9949     };
9950 
9951     union
9952     {
9953         __IOM uint32_t IALK_ID_MAX;          /*!< (@ 0x0000034C) Maximum Value ID MAC Address Register                      */
9954 
9955         struct
9956         {
9957             __IOM uint32_t IALK_ID_MAX : 24; /*!< [23..0] Maximum value for the 24-bit ID in the MAC address                */
9958             uint32_t                   : 8;
9959         } IALK_ID_MAX_b;
9960     };
9961 
9962     union
9963     {
9964         __IOM uint32_t IALK_ID_SUB;          /*!< (@ 0x00000350) Offset Value ID MAC Address Register                       */
9965 
9966         struct
9967         {
9968             __IOM uint32_t IALK_ID_SUB : 24; /*!< [23..0] Offset value to subtract from the 24-bit ID in the MAC
9969                                               *   address                                                                   */
9970             uint32_t : 8;
9971         } IALK_ID_SUB_b;
9972     };
9973 
9974     union
9975     {
9976         __IOM uint32_t IALK_ID_CONFIG;              /*!< (@ 0x00000354) Configures Lookup Response Unknown IDs Register            */
9977 
9978         struct
9979         {
9980             __IOM uint32_t INVLD_ID_FLOOD : 1;      /*!< [0..0] Setting this bit to 1 causes the IA table to return a
9981                                                      *   found response for frames whose ID lies outside the ID
9982                                                      *   range defined by [IA_LK_MAX:IA_LK_MIN] using INVLD_ID_FLOOD_MASK[3:0]
9983                                                      *   bits.                                                                     */
9984             __IOM uint32_t INVLD_ID_LRN_ENA : 1;    /*!< [1..1] Setting this bit to 1 allows automatic learning into
9985                                                      *   the L2 FDB for frames with unknown IDs. When 0, learning
9986                                                      *   is inhibited. This bit is only valid when INVLD_ID_FLOOD
9987                                                      *   bit is set to 1.                                                          */
9988             uint32_t                     : 2;
9989             __IOM uint32_t INVLD_ID_PRIO : 3;       /*!< [6..4] Priority to use for found responses of an invalid ID.
9990                                                      *   This bit is only valid when INVLD_ID_FLOOD bit is set to
9991                                                      *   1.                                                                        */
9992             __IOM uint32_t INVLD_ID_PRIO_VLD : 1;   /*!< [7..7] Indicates if the priority in INVLD_ID_PRIO is valid.
9993                                                      *   This bit is valid only when INVLD_ID_FLOOD bit is set to
9994                                                      *   1.                                                                        */
9995             uint32_t                           : 8;
9996             __IOM uint32_t INVLD_ID_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames whose ID is invalid.
9997                                                      *   This bit is only valid when INVLD_ID_FLOOD bit is set to
9998                                                      *   1. Setting this mask to 0 causes the frame to be dropped.                 */
9999             uint32_t : 12;
10000         } IALK_ID_CONFIG_b;
10001     };
10002 
10003     union
10004     {
10005         __IOM uint32_t IALK_VLAN_CONFIG;              /*!< (@ 0x00000358) Configure Lookup Response Unknown VLAN Register            */
10006 
10007         struct
10008         {
10009             __IOM uint32_t UNKWN_VLAN_FLOOD : 1;      /*!< [0..0] When this bit is set to 1, a frame matching the OUI and
10010                                                        *   with a valid ID but having a VLAN ID not matching any of
10011                                                        *   the enabled values in IALK_VLANIDn causes the IA table
10012                                                        *   to return a found response using the forwarding mask in
10013                                                        *   UNKWN_VLAN_FLOOD_MASK[3:0].                                               */
10014             __IOM uint32_t UNKWN_VLAN_LRN_ENA : 1;    /*!< [1..1] Setting this bit to 1 allows automatic learning into
10015                                                        *   the L2 FDB for frames with unknown VLANs. When 0, learning
10016                                                        *   is inhibited. This bit is only valid when UNKWN_VLAN_FLOOD
10017                                                        *   bit is set to 1.                                                          */
10018             uint32_t                       : 2;
10019             __IOM uint32_t UNKWN_VLAN_PRIO : 3;       /*!< [6..4] Priority to use for found responses for an unknown VLAN.
10020                                                        *   This bit is only valid when UNKWN_VLAN_FLOOD bit is set
10021                                                        *   to 1.                                                                     */
10022             __IOM uint32_t UNKWN_VLAN_PRIO_VLD : 1;   /*!< [7..7] Indicates if the priority in UNKWN_VLAN_PRIO[2:0] is
10023                                                        *   valid. This bit is only valid when UNKWN_VLAN_FLOOD bit
10024                                                        *   is set to 1.                                                              */
10025             __IOM uint32_t VLANS_ENABLED : 3;         /*!< [10..8] Configures the logical geometry of the IA table by specifying
10026                                                        *   the number of distinct VLAN IDs enabled. When set to 0,
10027                                                        *   no VLANs are supported and the VLAN ID for the frames is
10028                                                        *   ignored.                                                                  */
10029             uint32_t                             : 5;
10030             __IOM uint32_t UNKWN_VLAN_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames with an unknown VLAN
10031                                                        *   ID.                                                                       */
10032             uint32_t : 12;
10033         } IALK_VLAN_CONFIG_b;
10034     };
10035 
10036     union
10037     {
10038         __IOM uint32_t IALK_TBL_ADDR;  /*!< (@ 0x0000035C) IA Lookup Database Address Register                        */
10039 
10040         struct
10041         {
10042             __IOM uint32_t ADDR : 13;  /*!< [12..0] Defines the address to write to or read from the IA
10043                                         *   Lookup table                                                              */
10044             uint32_t            : 15;
10045             __IOM uint32_t AINC : 4;   /*!< [31..28] Auto-Increment Control                                           */
10046         } IALK_TBL_ADDR_b;
10047     };
10048 
10049     union
10050     {
10051         __IOM uint32_t IALK_TBL_DATA;    /*!< (@ 0x00000360) IA Lookup Database Data Register                           */
10052 
10053         struct
10054         {
10055             __IOM uint32_t VALID : 1;    /*!< [0..0] Indicates whether the entry indicated by ADDR is valid
10056                                           *   or not.                                                                   */
10057             __IOM uint32_t FWD_MASK : 4; /*!< [4..1] Forwarding mask used for lookups that hit the entry and
10058                                           *   when VALID is set to 1.                                                   */
10059             uint32_t : 27;
10060         } IALK_TBL_DATA_b;
10061     };
10062     __IM uint32_t RESERVED10[7];
10063 
10064     union
10065     {
10066         __IOM uint32_t IALK_VLANID[4];            /*!< (@ 0x00000380) IA Lookup VLANIDn Register                                 */
10067 
10068         struct
10069         {
10070             __IOM uint32_t VLANID : 12;           /*!< [11..0] Configure the VLAN ID to be used for VLAN n (n: IALK_VLAN_CONFIG.VLANS
10071                                                    *   ENABLED). This bit is only valid when VLANID_ENA bit is
10072                                                    *   set to 1. A value of 0 matches any VLAN ID.                               */
10073             __IOM uint32_t VLANID_ENA : 1;        /*!< [12..12] Enables this VLAN ID. When set to 1, the VLAN ID of
10074                                                    *   the frame is compared against VLANID[11:0].                               */
10075             __IOM uint32_t VLANID_LRN_ENA : 1;    /*!< [13..13] Configures whether automatic learning in the L2 FDB
10076                                                    *   is allowed for frames matching VLAN ID. This also includes
10077                                                    *   frames that match the VLAN ID and that the entry in the
10078                                                    *   IA table is invalid.                                                      */
10079             uint32_t                         : 2;
10080             __IOM uint32_t VLANID_FLOOD_MASK : 4; /*!< [19..16] Flooding mask to be used for frames matching this VLAN
10081                                                    *   ID but with an invalid entry in the IA table.                             */
10082             uint32_t                       : 8;
10083             __IOM uint32_t VLANID_PRIO     : 3;   /*!< [30..28] Priority to use for found responses.                             */
10084             __IOM uint32_t VLANID_PRIO_VLD : 1;   /*!< [31..31] Indicates if the priority in VLANID_PRIO[2:0] is valid.          */
10085         } IALK_VLANID_b[4];
10086     };
10087     __IM uint32_t RESERVED11[12];
10088 
10089     union
10090     {
10091         __IM uint32_t IMC_QLEVEL_P[4]; /*!< (@ 0x000003C0) Port [0..3] Queued Frame Count Register                    */
10092 
10093         struct
10094         {
10095             __IM uint32_t QUEUE0 : 4;  /*!< [3..0] A 4-bit value per queue indicating the number of frames
10096                                         *   stored in queue 0                                                         */
10097             __IM uint32_t QUEUE1 : 4;  /*!< [7..4] A 4-bit value per queue indicating the number of frames
10098                                         *   stored in queue 1                                                         */
10099             __IM uint32_t QUEUE2 : 4;  /*!< [11..8] A 4-bit value per queue indicating the number of frames
10100                                         *   stored in queue 2                                                         */
10101             __IM uint32_t QUEUE3 : 4;  /*!< [15..12] A 4-bit value per queue indicating the number of frames
10102                                         *   stored in queue 3                                                         */
10103             __IM uint32_t QUEUE4 : 4;  /*!< [19..16] A 4-bit value per queue indicating the number of frames
10104                                         *   stored in queue 4                                                         */
10105             __IM uint32_t QUEUE5 : 4;  /*!< [23..20] A 4-bit value per queue indicating the number of frames
10106                                         *   stored in queue 5                                                         */
10107             __IM uint32_t QUEUE6 : 4;  /*!< [27..24] A 4-bit value per queue indicating the number of frames
10108                                         *   stored in queue 6                                                         */
10109             __IM uint32_t QUEUE7 : 4;  /*!< [31..28] A 4-bit value per queue indicating the number of frames
10110                                         *   stored in queue 7                                                         */
10111         } IMC_QLEVEL_P_b[4];
10112     };
10113     __IM uint32_t RESERVED12[12];
10114 
10115     union
10116     {
10117         __IOM uint32_t LK_CTRL;               /*!< (@ 0x00000400) Learning/Lookup Function Global Configuration
10118                                                *                  Register                                                   */
10119 
10120         struct
10121         {
10122             __IOM uint32_t LKUP_EN       : 1; /*!< [0..0] Lookup Controller Enable                                           */
10123             __IOM uint32_t LEARN_EN      : 1; /*!< [1..1] Learning Enable                                                    */
10124             __IOM uint32_t AGING_EN      : 1; /*!< [2..2] Aging Enable                                                       */
10125             __IOM uint32_t ALW_MGRT      : 1; /*!< [3..3] Allow Migration                                                    */
10126             __IOM uint32_t DISC_UNK_DEST : 1; /*!< [4..4] Discard Unknown Destination                                        */
10127             uint32_t                     : 1;
10128             __IOM uint32_t CLRTBL        : 1; /*!< [6..6] Clear Table                                                        */
10129             __IOM uint32_t IND_VLAN      : 1; /*!< [7..7] Enable Independent VLAN Learning                                   */
10130             uint32_t                     : 8;
10131             __IOM uint32_t DISC_UNK_SRC  : 4; /*!< [19..16] Discard Unknown Source                                           */
10132             uint32_t                     : 12;
10133         } LK_CTRL_b;
10134     };
10135 
10136     union
10137     {
10138         __IOM uint32_t LK_STATUS;       /*!< (@ 0x00000404) Status Bits and Table Overflow Counter Register            */
10139 
10140         struct
10141         {
10142             __IM uint32_t AGEADDR : 16; /*!< [15..0] Address the aging process will inspect when the aging
10143                                          *   timer expires next time.                                                  */
10144             __IOM uint32_t OVRF : 14;   /*!< [29..16] Counts number of table overflows that occurred (a new
10145                                          *   address was learned but the table had no storage and an
10146                                          *   older entry was deleted). The counter is cleared by writing
10147                                          *   into the register and having bit 16 set to 1.                             */
10148             uint32_t               : 1;
10149             __IOM uint32_t LRNEVNT : 1; /*!< [31..31] Learn Event                                                      */
10150         } LK_STATUS_b;
10151     };
10152 
10153     union
10154     {
10155         __IOM uint32_t LK_ADDR_CTRL;        /*!< (@ 0x00000408) Address Table Transaction Control and Read/Write
10156                                              *                  Address                                                    */
10157 
10158         struct
10159         {
10160             __IOM uint32_t ADDR_MSK : 12;   /*!< [11..0] Memory address for read and write transactions. This
10161                                              *   is the address of a 69-bit entry. For the DEL_PORT bit,
10162                                              *   a port mask can be provided in these bits instead of the
10163                                              *   address. Bit 0 represents port 0, bit 1 port 1, and so
10164                                              *   on.                                                                       */
10165             uint32_t                   : 10;
10166             __IOM uint32_t CLR_DYNAMIC : 1; /*!< [22..22] When set to 1, scans the complete table for valid dynamic
10167                                              *   entries and deletes them (writes entry with all 0s). This
10168                                              *   bit is cleared when the function has completed.                           */
10169             __IOM uint32_t CLR_STATIC : 1;  /*!< [23..23] When set to 1, scans the complete table for valid static
10170                                              *   entries and deletes them (writes entry with all 0s). This
10171                                              *   bit is cleared when the function has completed.                           */
10172             __IOM uint32_t GETLASTNEW : 1;  /*!< [24..24] When set to 1, retrieves the last source address that
10173                                              *   was not found in the table and places it into LK_DATA_LO/HI/HI2.
10174                                              *   The valid bit of the entry (bit LK_DATA_HI[16]) indicates
10175                                              *   if the address is new (when valid bit is 1) or not (when
10176                                              *   valid bit is 0) since the command was last issued.                        */
10177             __IOM uint32_t WRITE     : 1;   /*!< [25..25] When set to 1, perform a single write transaction.               */
10178             __IOM uint32_t READ      : 1;   /*!< [26..26] When set to 1, perform a single read transaction.                */
10179             __IOM uint32_t WAIT_COMP : 1;   /*!< [27..27] When set to 1, instructs to stall the processor bus
10180                                              *   until the transaction is completed. This allows performing
10181                                              *   of consecutive writes into this register with varying commands
10182                                              *   without the need for polling the BUSY bit.                                */
10183             __IM uint32_t LOOKUP : 1;       /*!< [28..28] When set to 1, perform a lookup of the MAC address
10184                                              *   given in LK_DATA_LO/HI/HI2.                                               */
10185             __IOM uint32_t CLEAR : 1;       /*!< [29..29] When set to 1, writes all 0s to the entry selected
10186                                              *   by the given address set in ADDR_MSK[11:0]. If this bit
10187                                              *   is set together with the LOOKUP bit, first a lookup is
10188                                              *   performed and if the lookup succeeds, the entry is then
10189                                              *   deleted. The registers LK_DATA_LO/HI/HI2 are also cleared.
10190                                              *   The memory address in this register is set from the lookup
10191                                              *   result. If the lookup failed, the clear command is ignored
10192                                              *   and memory address is arbitrary.                                          */
10193             __IOM uint32_t DEL_PORT : 1;    /*!< [30..30] When set to 1, scans the complete table for valid dynamic
10194                                              *   entries that contain the given ports in their destination
10195                                              *   port mask and deletes the ports or the complete entry.
10196                                              *   The port mask is provided in the ADDR_MSK[3:0] when writing
10197                                              *   this register (1 bit per port, bit 0 = port 0, bit 1 =
10198                                              *   port 1, and so on).                                                       */
10199             __IM uint32_t BUSY : 1;         /*!< [31..31] Transaction Busy Indication                                      */
10200         } LK_ADDR_CTRL_b;
10201     };
10202 
10203     union
10204     {
10205         __IOM uint32_t LK_DATA_LO;       /*!< (@ 0x0000040C) Lower 32-Bit Data of Lookup Memory Entry                   */
10206 
10207         struct
10208         {
10209             __IOM uint32_t MEMDATA : 32; /*!< [31..0] Memory Data [31:0]                                                */
10210         } LK_DATA_LO_b;
10211     };
10212 
10213     union
10214     {
10215         __IOM uint32_t LK_DATA_HI;       /*!< (@ 0x00000410) Higher 25-Bit Data of Lookup Memory Entry                  */
10216 
10217         struct
10218         {
10219             __IOM uint32_t MEMDATA : 25; /*!< [24..0] Memory Data [56:32]                                               */
10220             uint32_t               : 7;
10221         } LK_DATA_HI_b;
10222     };
10223 
10224     union
10225     {
10226         __IOM uint32_t LK_DATA_HI2;    /*!< (@ 0x00000414) Higher2 12-Bit Data of Lookup Memory Entry                 */
10227 
10228         struct
10229         {
10230             uint32_t               : 8;
10231             __IOM uint32_t MEMDATA : 12; /*!< [19..8] Memory Data [68:57]                                               */
10232             uint32_t               : 12;
10233         } LK_DATA_HI2_b;
10234     };
10235 
10236     union
10237     {
10238         __IOM uint32_t LK_LEARNCOUNT;       /*!< (@ 0x00000418) Learned Address Count Register                             */
10239 
10240         struct
10241         {
10242             __IOM uint32_t LEARNCOUNT : 13; /*!< [12..0] Number of Learned Addresses                                       */
10243             uint32_t                  : 17;
10244             __IOM uint32_t WRITE_MD   : 2;  /*!< [31..30] These bits define how the LEARNCOUNT value is modified
10245                                              *   when writing into the register:                                           */
10246         } LK_LEARNCOUNT_b;
10247     };
10248 
10249     union
10250     {
10251         __IOM uint32_t LK_AGETIME;       /*!< (@ 0x0000041C) Period of the Aging Timer                                  */
10252 
10253         struct
10254         {
10255             __IOM uint32_t AGETIME : 24; /*!< [23..0] 24-bit Timer Value                                                */
10256             uint32_t               : 8;
10257         } LK_AGETIME_b;
10258     };
10259     __IM uint32_t RESERVED13[24];
10260 
10261     union
10262     {
10263         __IOM uint32_t MGMT_TAG_CONFIG;   /*!< (@ 0x00000480) Management Tag Configuration Register                      */
10264 
10265         struct
10266         {
10267             __IOM uint32_t ENABLE    : 1; /*!< [0..0] Enable Management Tag Insertion Module                             */
10268             __IOM uint32_t AL_FRAMES : 1; /*!< [1..1] Enable Tag Insertion for All Frames                                */
10269             uint32_t                 : 2;
10270             __IOM uint32_t TYPE1_EN  : 1; /*!< [4..4] When set, frames with a Type field that match the value
10271                                            *   in PRIORITY_TYPE1.TYPEVAL[15:0] have management tag inserted.
10272                                            *   This is in addition to BPDU frames which always have tag
10273                                            *   inserted.                                                                 */
10274             __IOM uint32_t TYPE2_EN : 1;  /*!< [5..5] When set, frames with a Type field that match the value
10275                                            *   in PRIORITY_TYPE2.TYPEVAL[15:0] have management tag inserted.
10276                                            *   This is in addition to BPDU frames which always have tag
10277                                            *   inserted.                                                                 */
10278             uint32_t                : 10;
10279             __IOM uint32_t TAGFIELD : 16; /*!< [31..16] The value of the tag that is found in the first Type/Length
10280                                            *   field of the frame to identify that the control information
10281                                            *   is present within a frame. For example, [31:24] = first
10282                                            *   octet, [23:16] = 2nd octet.                                               */
10283         } MGMT_TAG_CONFIG_b;
10284     };
10285     __IM uint32_t RESERVED14[32];
10286 
10287     union
10288     {
10289         __IOM uint32_t TSM_CONFIG;             /*!< (@ 0x00000504) Timestamping Control Module Configuration Register         */
10290 
10291         struct
10292         {
10293             __IOM uint32_t IRQ_EN         : 1; /*!< [0..0] Final Interrupt enable                                             */
10294             __IOM uint32_t IRQ_TEST       : 1; /*!< [1..1] Software controlled interrupt for testing purposes                 */
10295             __IOM uint32_t IRQ_TSFIFO_OVR : 1; /*!< [2..2] Trigger interrupt enable for Transmit Timestamp Capture
10296                                                 *   Overflow event                                                            */
10297             uint32_t                      : 1;
10298             __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Trigger interrupt enable for the timer offset
10299                                                 *   event                                                                     */
10300             uint32_t                      : 2;
10301             __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Trigger interrupt enable for the timer periodical
10302                                                 *   event                                                                     */
10303             uint32_t                      : 2;
10304             __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Trigger interrupt enable for the timer wrap
10305                                                 *   (reached its maximum)                                                     */
10306             uint32_t                 : 2;
10307             __IOM uint32_t IRQ_TX_EN : 4;      /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt Enable             */
10308             uint32_t                 : 12;
10309         } TSM_CONFIG_b;
10310     };
10311 
10312     union
10313     {
10314         __IOM uint32_t TSM_IRQ_STAT_ACK;       /*!< (@ 0x00000508) Interrupt Status/Acknowledge Register                      */
10315 
10316         struct
10317         {
10318             __IM uint32_t  IRQ_STAT       : 1; /*!< [0..0] Interrupt Pending Status                                           */
10319             __IOM uint32_t IRQ_TEST       : 1; /*!< [1..1] Test Interrupt Pending Status                                      */
10320             __IM uint32_t  IRQ_TSFIFO_OVR : 1; /*!< [2..2] Transmit Timestamp Capture Overflow Interrupt Pending
10321                                                 *   Status                                                                    */
10322             uint32_t                      : 1;
10323             __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Offset Interrupt Pending Status                          */
10324             uint32_t                      : 2;
10325             __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Periodical Interrupt Pending Status                      */
10326             uint32_t                      : 2;
10327             __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Overflow Interrupt Pending Status                      */
10328             uint32_t                      : 2;
10329             __IOM uint32_t IRQ_TX         : 4; /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt                    */
10330             uint32_t                      : 12;
10331         } TSM_IRQ_STAT_ACK_b;
10332     };
10333 
10334     union
10335     {
10336         __IOM uint32_t PTP_DOMAIN;      /*!< (@ 0x0000050C) Domain Number of PTP Frame                                 */
10337 
10338         struct
10339         {
10340             __IOM uint32_t DOMAIN0 : 8; /*!< [7..0] DomainNumber to Match Against for Timer 0                          */
10341             __IOM uint32_t DOMAIN1 : 8; /*!< [15..8] DomainNumber to Match Against for Timer 1                         */
10342             uint32_t               : 16;
10343         } PTP_DOMAIN_b;
10344     };
10345     __IM uint32_t RESERVED15[12];
10346 
10347     union
10348     {
10349         __IOM uint32_t PEERDELAY_P0_T0;    /*!< (@ 0x00000540) Port 0 Peer Delay Value for Timer 0 (n = 0 to
10350                                             *                  3)                                                         */
10351 
10352         struct
10353         {
10354             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10355                                             *   0                                                                         */
10356             uint32_t : 2;
10357         } PEERDELAY_P0_T0_b;
10358     };
10359 
10360     union
10361     {
10362         __IOM uint32_t PEERDELAY_P0_T1;    /*!< (@ 0x00000544) Port 0 Peer Delay Value for Timer 1 (n = 0 to
10363                                             *                  3)                                                         */
10364 
10365         struct
10366         {
10367             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10368                                             *   1                                                                         */
10369             uint32_t : 2;
10370         } PEERDELAY_P0_T1_b;
10371     };
10372     __IM uint32_t RESERVED16[2];
10373 
10374     union
10375     {
10376         __IOM uint32_t PEERDELAY_P1_T0;    /*!< (@ 0x00000550) Port 1 Peer Delay Value for Timer 0 (n = 0 to
10377                                             *                  3)                                                         */
10378 
10379         struct
10380         {
10381             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10382                                             *   0                                                                         */
10383             uint32_t : 2;
10384         } PEERDELAY_P1_T0_b;
10385     };
10386 
10387     union
10388     {
10389         __IOM uint32_t PEERDELAY_P1_T1;    /*!< (@ 0x00000554) Port 1 Peer Delay Value for Timer 1 (n = 0 to
10390                                             *                  3)                                                         */
10391 
10392         struct
10393         {
10394             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10395                                             *   1                                                                         */
10396             uint32_t : 2;
10397         } PEERDELAY_P1_T1_b;
10398     };
10399     __IM uint32_t RESERVED17[2];
10400 
10401     union
10402     {
10403         __IOM uint32_t PEERDELAY_P2_T0;    /*!< (@ 0x00000560) Port 2 Peer Delay Value for Timer 0 (n = 0 to
10404                                             *                  3)                                                         */
10405 
10406         struct
10407         {
10408             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10409                                             *   0                                                                         */
10410             uint32_t : 2;
10411         } PEERDELAY_P2_T0_b;
10412     };
10413 
10414     union
10415     {
10416         __IOM uint32_t PEERDELAY_P2_T1;    /*!< (@ 0x00000564) Port 2 Peer Delay Value for Timer 1 (n = 0 to
10417                                             *                  3)                                                         */
10418 
10419         struct
10420         {
10421             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10422                                             *   1                                                                         */
10423             uint32_t : 2;
10424         } PEERDELAY_P2_T1_b;
10425     };
10426     __IM uint32_t RESERVED18[2];
10427 
10428     union
10429     {
10430         __IOM uint32_t PEERDELAY_P3_T0;    /*!< (@ 0x00000570) Port 3 Peer Delay Value for Timer 0 (n = 0 to
10431                                             *                  3)                                                         */
10432 
10433         struct
10434         {
10435             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10436                                             *   0                                                                         */
10437             uint32_t : 2;
10438         } PEERDELAY_P3_T0_b;
10439     };
10440 
10441     union
10442     {
10443         __IOM uint32_t PEERDELAY_P3_T1;    /*!< (@ 0x00000574) Port 3 Peer Delay Value for Timer 1 (n = 0 to
10444                                             *                  3)                                                         */
10445 
10446         struct
10447         {
10448             __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer
10449                                             *   1                                                                         */
10450             uint32_t : 2;
10451         } PEERDELAY_P3_T1_b;
10452     };
10453     __IM uint32_t RESERVED19[18];
10454 
10455     union
10456     {
10457         __IOM uint32_t TS_FIFO_STATUS;  /*!< (@ 0x000005C0) Transmit Timestamp FIFO Status Register                    */
10458 
10459         struct
10460         {
10461             __IM uint32_t FF_VALID : 4; /*!< [3..0] Per-port indication that a valid timestamp is available
10462                                          *   in the corresponding FIFO of the port                                     */
10463             uint32_t              : 12;
10464             __IOM uint32_t FF_OVR : 4;  /*!< [19..16] Per-port indication that a timestamp cannot be written
10465                                          *   to the FIFO because of the FIFO being full.                               */
10466             uint32_t : 12;
10467         } TS_FIFO_STATUS_b;
10468     };
10469 
10470     union
10471     {
10472         __IOM uint32_t TS_FIFO_READ_CTRL; /*!< (@ 0x000005C4) Transmit Timestamp FIFO Read Control Register              */
10473 
10474         struct
10475         {
10476             __IOM uint32_t PORT_NUM : 2;  /*!< [1..0] Port Number to Read from                                           */
10477             uint32_t                : 2;
10478             __IM uint32_t TS_VALID  : 1;  /*!< [4..4] When reading from this register, this bit is 1 if the
10479                                            *   FIFO indicated by PORT_NUM contained valid data.                          */
10480             uint32_t             : 1;
10481             __IM uint32_t TS_SEL : 1;     /*!< [6..6] When TS_VALID is 1, TS_SEL indicates the timer used for
10482                                            *   the read timestamp.                                                       */
10483             uint32_t            : 1;
10484             __IM uint32_t TS_ID : 7;      /*!< [14..8] When TS_VALID is 1, TS_ID indicates the ID specified
10485                                            *   by the application through the management tag control information,
10486                                            *   if present.                                                               */
10487             uint32_t : 17;
10488         } TS_FIFO_READ_CTRL_b;
10489     };
10490 
10491     union
10492     {
10493         __IM uint32_t TS_FIFO_READ_TIMESTAMP; /*!< (@ 0x000005C8) 32-bit Timestamp Value Read from FIFO                      */
10494 
10495         struct
10496         {
10497             __IM uint32_t TIMESTAMP : 32;     /*!< [31..0] 32-bit timestamp value read from the FIFO                         */
10498         } TS_FIFO_READ_TIMESTAMP_b;
10499     };
10500     __IM uint32_t RESERVED20[13];
10501 
10502     union
10503     {
10504         __IOM uint32_t INT_CONFIG;            /*!< (@ 0x00000600) Interrupt Enable Configuration Register                    */
10505 
10506         struct
10507         {
10508             __IOM uint32_t IRQ_EN     : 1;    /*!< [0..0] Interrupt Global Enable                                            */
10509             __IOM uint32_t MDIO1      : 1;    /*!< [1..1] Enable Interrupt on Transaction Complete from MDIO Controller      */
10510             uint32_t                  : 1;
10511             __IOM uint32_t LK_NEW_SRC : 1;    /*!< [3..3] Enable Interrupt for New Source Address                            */
10512             __IOM uint32_t IRQ_TEST   : 1;    /*!< [4..4] When set, an interrupt is triggered immediately. Can
10513                                                *   be used to cause a software controlled interrupt for testing
10514                                                *   purposes.                                                                 */
10515             __IOM uint32_t DLR_INT       : 1; /*!< [5..5] Enable Interrupt for DLR                                           */
10516             __IOM uint32_t PRP_INT       : 1; /*!< [6..6] Enable Interrupt for PRP                                           */
10517             __IOM uint32_t HUB_INT       : 1; /*!< [7..7] Enable Interrupt for HUB                                           */
10518             __IOM uint32_t IRQ_LINK      : 3; /*!< [10..8] Per Line Port Phy Link Change Interrupt Enable                    */
10519             uint32_t                     : 5;
10520             __IOM uint32_t IRQ_MAC_EEE   : 3; /*!< [18..16] Per Line Port MAC interrupt                                      */
10521             uint32_t                     : 8;
10522             __IOM uint32_t EFP_INT       : 1; /*!< [27..27] Enable Interrupt for Extended Frame Parser                       */
10523             __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] MAC Address Source Filtering Watchdog                            */
10524             __IOM uint32_t TSM_INT       : 1; /*!< [29..29] Enable Interrupt for TSM (Timer, Timestamping)                   */
10525             __IOM uint32_t TDMA_INT      : 1; /*!< [30..30] Enable Interrupt for TDMA scheduler                              */
10526             __IOM uint32_t PATTERN_INT   : 1; /*!< [31..31] Enable Interrupt for RX Pattern Matcher                          */
10527         } INT_CONFIG_b;
10528     };
10529 
10530     union
10531     {
10532         __IOM uint32_t INT_STAT_ACK;          /*!< (@ 0x00000604) Interrupt Status/ACK Register                              */
10533 
10534         struct
10535         {
10536             __IM uint32_t  IRQ_PEND      : 1; /*!< [0..0] Interrupt Pending Status                                           */
10537             __IOM uint32_t MDIO1         : 1; /*!< [1..1] Latched Interrupt Status for MDIO1                                 */
10538             uint32_t                     : 1;
10539             __IOM uint32_t LK_NEW_SRC    : 1; /*!< [3..3] Latched Interrupt Status for LK_NEW_SRC                            */
10540             __IM uint32_t  IRQ_TEST      : 1; /*!< [4..4] Interrupt Status for IRQ_TEST                                      */
10541             __IM uint32_t  DLR_INT       : 1; /*!< [5..5] Interrupt Pending Status from DLR Module                           */
10542             __IM uint32_t  PRP_INT       : 1; /*!< [6..6] Interrupt Pending Status from PRP Module                           */
10543             __IM uint32_t  HUB_INT       : 1; /*!< [7..7] Interrupt Pending Status from Hub Module                           */
10544             __IOM uint32_t IRQ_LINK      : 3; /*!< [10..8] Interrupt Pending per Line Port Phy Link Change Interrupt         */
10545             uint32_t                     : 5;
10546             __IOM uint32_t IRQ_MAC_EEE   : 3; /*!< [18..16] Interrupt Pending Status per Line Port MAC Interrupt             */
10547             uint32_t                     : 8;
10548             __IOM uint32_t EFP_INT       : 1; /*!< [27..27] Interrupt from Extended Frame Parser                             */
10549             __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] Interrupt Pending Status for MAC Source Filtering Watchdog       */
10550             __IM uint32_t  TSM_INT       : 1; /*!< [29..29] Interrupt Pending Interrupt Indication from TSM (Timestamping)
10551                                                *   module                                                                    */
10552             __IM uint32_t TDMA_INT    : 1;    /*!< [30..30] Interrupt Pending Status from TDMA Scheduler                     */
10553             __IM uint32_t PATTERN_INT : 1;    /*!< [31..31] Interrupt Pending Status from RX Pattern Matcher Module          */
10554         } INT_STAT_ACK_b;
10555     };
10556     __IM uint32_t RESERVED21[30];
10557 
10558     union
10559     {
10560         __IOM uint32_t ATIME_CTRL0;            /*!< (@ 0x00000680) Timer 0 Control Register (n = 0, 1)                        */
10561 
10562         struct
10563         {
10564             __IOM uint32_t ENABLE   : 1;       /*!< [0..0] ENABLE                                                             */
10565             __IOM uint32_t ONE_SHOT : 1;       /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum.
10566                                                 *   An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs
10567                                                 *   (if enabled) when the maximum is reached.                                 */
10568             __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event                                                */
10569             uint32_t                      : 1;
10570             __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event                                            */
10571             __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event                                    */
10572             uint32_t                      : 3;
10573             __IOM uint32_t RESTART        : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit)                             */
10574             uint32_t                      : 1;
10575             __IOM uint32_t CAPTURE        : 1; /*!< [11..11] Capture Time Value (Command Bit)                                 */
10576             __IOM uint32_t CAPTURE_ALL    : 1; /*!< [12..12] Capture All Timers Value (Command Bit)                           */
10577             uint32_t                      : 19;
10578         } ATIME_CTRL0_b;
10579     };
10580 
10581     union
10582     {
10583         __IOM uint32_t ATIME0;             /*!< (@ 0x00000684) Timer 0 Count Register (n = 0, 1)                          */
10584 
10585         struct
10586         {
10587             __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value                                                       */
10588         } ATIME0_b;
10589     };
10590 
10591     union
10592     {
10593         __IOM uint32_t ATIME_OFFSET0;   /*!< (@ 0x00000688) Timer 0 Offset Register (n = 0, 1)                         */
10594 
10595         struct
10596         {
10597             __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without
10598                                          *   changing the drift correction                                             */
10599         } ATIME_OFFSET0_b;
10600     };
10601 
10602     union
10603     {
10604         __IOM uint32_t ATIME_EVT_PERIOD0; /*!< (@ 0x0000068C) Timer 0 Periodic Event Register (n = 0, 1)                 */
10605 
10606         struct
10607         {
10608             __IOM uint32_t PERIOD : 32;   /*!< [31..0] Value for generating periodic events                              */
10609         } ATIME_EVT_PERIOD0_b;
10610     };
10611 
10612     union
10613     {
10614         __IOM uint32_t ATIME_CORR0;          /*!< (@ 0x00000690) Timer 0 Correction Period Register (n = 0, 1)              */
10615 
10616         struct
10617         {
10618             __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period                                                 */
10619             uint32_t                   : 1;
10620         } ATIME_CORR0_b;
10621     };
10622 
10623     union
10624     {
10625         __IOM uint32_t ATIME_INC0;            /*!< (@ 0x00000694) Timer 0 Increment Register (n = 0, 1)                      */
10626 
10627         struct
10628         {
10629             __IOM uint32_t CLK_PERIOD    : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds    */
10630             uint32_t                     : 1;
10631             __IOM uint32_t CORR_INC      : 7; /*!< [14..8] Correction Increment Value                                        */
10632             uint32_t                     : 1;
10633             __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value                                */
10634             uint32_t                     : 9;
10635         } ATIME_INC0_b;
10636     };
10637 
10638     union
10639     {
10640         __IOM uint32_t ATIME_SEC0;        /*!< (@ 0x00000698) Timer 0 Seconds Time Register (n = 0, 1)                   */
10641 
10642         struct
10643         {
10644             __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value                                                */
10645         } ATIME_SEC0_b;
10646     };
10647 
10648     union
10649     {
10650         __IOM uint32_t ATIME_OFFS_CORR0;       /*!< (@ 0x0000069C) Timer 0 Offset Correction Counter Register (n
10651                                                 *                  = 0, 1)                                                    */
10652 
10653         struct
10654         {
10655             __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter                                         */
10656         } ATIME_OFFS_CORR0_b;
10657     };
10658 
10659     union
10660     {
10661         __IOM uint32_t ATIME_CTRL1;            /*!< (@ 0x000006A0) Timer 1 Control Register (n = 0, 1)                        */
10662 
10663         struct
10664         {
10665             __IOM uint32_t ENABLE   : 1;       /*!< [0..0] ENABLE                                                             */
10666             __IOM uint32_t ONE_SHOT : 1;       /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum.
10667                                                 *   An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs
10668                                                 *   (if enabled) when the maximum is reached.                                 */
10669             __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event                                                */
10670             uint32_t                      : 1;
10671             __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event                                            */
10672             __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event                                    */
10673             uint32_t                      : 3;
10674             __IOM uint32_t RESTART        : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit)                             */
10675             uint32_t                      : 1;
10676             __IOM uint32_t CAPTURE        : 1; /*!< [11..11] Capture Time Value (Command Bit)                                 */
10677             __IOM uint32_t CAPTURE_ALL    : 1; /*!< [12..12] Capture All Timers Value (Command Bit)                           */
10678             uint32_t                      : 19;
10679         } ATIME_CTRL1_b;
10680     };
10681 
10682     union
10683     {
10684         __IOM uint32_t ATIME1;             /*!< (@ 0x000006A4) Timer 1 Count Register (n = 0, 1)                          */
10685 
10686         struct
10687         {
10688             __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value                                                       */
10689         } ATIME1_b;
10690     };
10691 
10692     union
10693     {
10694         __IOM uint32_t ATIME_OFFSET1;   /*!< (@ 0x000006A8) Timer 1 Offset Register (n = 0, 1)                         */
10695 
10696         struct
10697         {
10698             __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without
10699                                          *   changing the drift correction                                             */
10700         } ATIME_OFFSET1_b;
10701     };
10702 
10703     union
10704     {
10705         __IOM uint32_t ATIME_EVT_PERIOD1; /*!< (@ 0x000006AC) Timer 1 Periodic Event Register (n = 0, 1)                 */
10706 
10707         struct
10708         {
10709             __IOM uint32_t PERIOD : 32;   /*!< [31..0] Value for generating periodic events                              */
10710         } ATIME_EVT_PERIOD1_b;
10711     };
10712 
10713     union
10714     {
10715         __IOM uint32_t ATIME_CORR1;          /*!< (@ 0x000006B0) Timer 1 Correction Period Register (n = 0, 1)              */
10716 
10717         struct
10718         {
10719             __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period                                                 */
10720             uint32_t                   : 1;
10721         } ATIME_CORR1_b;
10722     };
10723 
10724     union
10725     {
10726         __IOM uint32_t ATIME_INC1;            /*!< (@ 0x000006B4) Timer 1 Increment Register (n = 0, 1)                      */
10727 
10728         struct
10729         {
10730             __IOM uint32_t CLK_PERIOD    : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds    */
10731             uint32_t                     : 1;
10732             __IOM uint32_t CORR_INC      : 7; /*!< [14..8] Correction Increment Value                                        */
10733             uint32_t                     : 1;
10734             __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value                                */
10735             uint32_t                     : 9;
10736         } ATIME_INC1_b;
10737     };
10738 
10739     union
10740     {
10741         __IOM uint32_t ATIME_SEC1;        /*!< (@ 0x000006B8) Timer 1 Seconds Time Register (n = 0, 1)                   */
10742 
10743         struct
10744         {
10745             __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value                                                */
10746         } ATIME_SEC1_b;
10747     };
10748 
10749     union
10750     {
10751         __IOM uint32_t ATIME_OFFS_CORR1;       /*!< (@ 0x000006BC) Timer 1 Offset Correction Counter Register (n
10752                                                 *                  = 0, 1)                                                    */
10753 
10754         struct
10755         {
10756             __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter                                         */
10757         } ATIME_OFFS_CORR1_b;
10758     };
10759     __IM uint32_t RESERVED22[16];
10760 
10761     union
10762     {
10763         __IOM uint32_t MDIO_CFG_STATUS;  /*!< (@ 0x00000700) MDIO Configuration and Status Register                     */
10764 
10765         struct
10766         {
10767             __IM uint32_t  BUSY     : 1; /*!< [0..0] MDIO Busy                                                          */
10768             __IM uint32_t  READERR  : 1; /*!< [1..1] MDIO Read Error                                                    */
10769             __IOM uint32_t HOLD     : 3; /*!< [4..2] MDIO Hold Time Setting                                             */
10770             __IOM uint32_t DISPREAM : 1; /*!< [5..5] Disable Preamble                                                   */
10771             uint32_t                : 1;
10772             __IOM uint32_t CLKDIV   : 9; /*!< [15..7] MDIO Clock Divisor                                                */
10773             uint32_t                : 16;
10774         } MDIO_CFG_STATUS_b;
10775     };
10776 
10777     union
10778     {
10779         __IOM uint32_t MDIO_COMMAND;     /*!< (@ 0x00000704) MDIO PHY Command Register                                  */
10780 
10781         struct
10782         {
10783             __IOM uint32_t REGADDR  : 5; /*!< [4..0] Register Address                                                   */
10784             __IOM uint32_t PHYADDR  : 5; /*!< [9..5] PHY Address                                                        */
10785             uint32_t                : 5;
10786             __IOM uint32_t TRANINIT : 1; /*!< [15..15] If set to 1, a read transaction is initiated.                    */
10787             uint32_t                : 16;
10788         } MDIO_COMMAND_b;
10789     };
10790 
10791     union
10792     {
10793         __IOM uint32_t MDIO_DATA;          /*!< (@ 0x00000708) MDIO Data Register                                         */
10794 
10795         struct
10796         {
10797             __IOM uint32_t MDIO_DATA : 16; /*!< [15..0] MDIO_DATA                                                         */
10798             uint32_t                 : 16;
10799         } MDIO_DATA_b;
10800     };
10801     __IM uint32_t RESERVED23[61];
10802 
10803     union
10804     {
10805         __IM uint32_t REV_P0;          /*!< (@ 0x00000800) Port 0 MAC Core Revision (n = 0 to 3)                      */
10806 
10807         struct
10808         {
10809             __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
10810         } REV_P0_b;
10811     };
10812     __IM uint32_t RESERVED24;
10813 
10814     union
10815     {
10816         __IOM uint32_t COMMAND_CONFIG_P0;       /*!< (@ 0x00000808) Port 0 Command Configuration Register (n = 0
10817                                                  *                  to 3)                                                      */
10818 
10819         struct
10820         {
10821             __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
10822             __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
10823             __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
10824                                                  *   the IMC until the current frame is completed. This can
10825                                                  *   cause the IPG between frames to be more than the value
10826                                                  *   in TX_IPG_LENGTH.                                                         */
10827             __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
10828             __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
10829             __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
10830             uint32_t                    : 1;
10831             __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
10832             __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
10833             __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
10834             __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
10835                                                  *   full-duplex only (set to 0).                                              */
10836             __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
10837             uint32_t                     : 1;
10838             __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
10839             uint32_t                     : 9;
10840             __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
10841             __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
10842             __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
10843                                                  *   register.                                                                 */
10844             __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
10845             __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
10846             uint32_t                   : 2;
10847             __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
10848                                                  *   on transmit and on receive. The value is used when not
10849                                                  *   overridden by the PTP auto-response function, pattern matchers
10850                                                  *   or force forwarding information in a management tag.                      */
10851             uint32_t : 1;
10852         } COMMAND_CONFIG_P0_b;
10853     };
10854 
10855     union
10856     {
10857         __IOM uint32_t MAC_ADDR_0_P0;     /*!< (@ 0x0000080C) Port 0 MAC Address Register 0 (n = 0 to 2)                 */
10858 
10859         struct
10860         {
10861             __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
10862                                            *   byte is bits [7:0]. The MAC address is used on locally
10863                                            *   generated frames such as pause frames, peer-delay response.               */
10864         } MAC_ADDR_0_P0_b;
10865     };
10866 
10867     union
10868     {
10869         __IOM uint32_t MAC_ADDR_1_P0;     /*!< (@ 0x00000810) Port 0 MAC Address Register 1 (n = 0 to 2)                 */
10870 
10871         struct
10872         {
10873             __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
10874                                            *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
10875             uint32_t : 16;
10876         } MAC_ADDR_1_P0_b;
10877     };
10878 
10879     union
10880     {
10881         __IOM uint32_t FRM_LENGTH_P0;       /*!< (@ 0x00000814) Port 0 Maximum Frame Length Register (n = 0 to
10882                                              *                  3)                                                         */
10883 
10884         struct
10885         {
10886             __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
10887             uint32_t                  : 18;
10888         } FRM_LENGTH_P0_b;
10889     };
10890 
10891     union
10892     {
10893         __IM uint32_t PAUSE_QUANT_P0;       /*!< (@ 0x00000818) Port 0 MAC Pause Quanta (n = 0 to 3)                       */
10894 
10895         struct
10896         {
10897             __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
10898             uint32_t                  : 16;
10899         } PAUSE_QUANT_P0_b;
10900     };
10901 
10902     union
10903     {
10904         __IOM uint32_t MAC_LINK_QTRIG_P0;  /*!< (@ 0x0000081C) Port 0 Trigger Event Configuration Register (n
10905                                             *                  = 0 to 2)                                                  */
10906 
10907         struct
10908         {
10909             __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
10910             uint32_t                  : 12;
10911             __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
10912                                             *   is transmitted from the ports indicated by PORT_MASK. A
10913                                             *   single frame is transmitted per indicated port in PORT_MASK
10914                                             *   among the queues indicated by QUEUE_MASK.                                 */
10915             uint32_t                 : 4;
10916             __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
10917                                             *   a frame was transmitted. When MODE is set to 0, TRIGGERED
10918                                             *   is always 0. This flag clears when the register is written.               */
10919             __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
10920                                             *   set to 1, the Link Queue Trigger occurs only if the DLR
10921                                             *   state machine is in the NORMAL or FAULT state.                            */
10922             __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
10923                                             *   This is to prevent sending multiple frames due to link
10924                                             *   flapping.                                                                 */
10925             __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
10926                                             *   When the link status (phy_link) transitions from 1 ->
10927                                             *   0, a trigger event is generated to the memory controller
10928                                             *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
10929         } MAC_LINK_QTRIG_P0_b;
10930     };
10931     __IM uint32_t RESERVED25[4];
10932 
10933     union
10934     {
10935         __IOM uint32_t PTPCLOCKIDENTITY1_P0;  /*!< (@ 0x00000830) Port 0 PTP Clock Identity 1 Register (n = 0 to
10936                                                *                  2)                                                         */
10937 
10938         struct
10939         {
10940             __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
10941             __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
10942             __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
10943             __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
10944         } PTPCLOCKIDENTITY1_P0_b;
10945     };
10946 
10947     union
10948     {
10949         __IOM uint32_t PTPCLOCKIDENTITY2_P0;  /*!< (@ 0x00000834) Port 0 PTP Clock Identity 2 Register (n = 0 to
10950                                                *                  2)                                                         */
10951 
10952         struct
10953         {
10954             __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
10955             __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
10956             __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
10957             __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
10958         } PTPCLOCKIDENTITY2_P0_b;
10959     };
10960 
10961     union
10962     {
10963         __IOM uint32_t PTPAUTORESPONSE_P0; /*!< (@ 0x00000838) Port 0 PTP Auto Response Register (n = 0 to 2)             */
10964 
10965         struct
10966         {
10967             __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
10968             __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
10969             uint32_t                : 14;
10970             __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
10971             __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
10972         } PTPAUTORESPONSE_P0_b;
10973     };
10974     __IM uint32_t RESERVED26;
10975 
10976     union
10977     {
10978         __IOM uint32_t STATUS_P0;          /*!< (@ 0x00000840) Port 0 Status Register                                     */
10979 
10980         struct
10981         {
10982             __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
10983             __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
10984             __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
10985             __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
10986                                             *   never occur during normal operation.                                      */
10987             __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
10988                                             *   to complete in time before the next frame was received
10989                                             *   at the port. This should never occur under normal operation.
10990                                             *   The cause could be from IPG violations in the received
10991                                             *   frames.                                                                   */
10992             __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
10993                                             *   to clause 30.14.1.2 of the 802.3br specification                          */
10994             uint32_t : 23;
10995         } STATUS_P0_b;
10996     };
10997 
10998     union
10999     {
11000         __IOM uint32_t TX_IPG_LENGTH_P0;      /*!< (@ 0x00000844) Port 0 Transmit IPG Length Register (n = 0 to
11001                                                *                  3)                                                         */
11002 
11003         struct
11004         {
11005             __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
11006                                                *   are in the range of 8 to 31.                                              */
11007             uint32_t                  : 11;
11008             __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
11009             uint32_t                  : 11;
11010         } TX_IPG_LENGTH_P0_b;
11011     };
11012 
11013     union
11014     {
11015         __IOM uint32_t EEE_CTL_STAT_P0;        /*!< (@ 0x00000848) Port 0 MAC EEE Functions Control and Status (n
11016                                                 *                  = 0 to 2)                                                  */
11017 
11018         struct
11019         {
11020             __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
11021             __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
11022             __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
11023             uint32_t                    : 5;
11024             __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
11025             __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
11026             __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
11027             __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
11028                                                 *   available for transmission.                                               */
11029             __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
11030             uint32_t                      : 3;
11031             __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
11032             __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
11033                                                 *   MAC                                                                       */
11034             __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
11035             uint32_t                   : 1;
11036             __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
11037             uint32_t                   : 11;
11038         } EEE_CTL_STAT_P0_b;
11039     };
11040 
11041     union
11042     {
11043         __IOM uint32_t EEE_IDLE_TIME_P0;       /*!< (@ 0x0000084C) Port 0 EEE Idle Time Register (n = 0 to 2)                 */
11044 
11045         struct
11046         {
11047             __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
11048                                                 *   of LPI begins. A 32-bit value in steps of 32 switch operating
11049                                                 *   clock cycles. A value of 0 disables the timer. The value
11050                                                 *   must be set to 1 less count.                                              */
11051         } EEE_IDLE_TIME_P0_b;
11052     };
11053 
11054     union
11055     {
11056         __IOM uint32_t EEE_TWSYS_TIME_P0;      /*!< (@ 0x00000850) Port 0 EEE Wake Up Time Register (n = 0 to 2)              */
11057 
11058         struct
11059         {
11060             __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
11061                                                 *   to begin transmitting the first frame again. A 32-bit value
11062                                                 *   in steps of switch operating clock cycles. A value of 0
11063                                                 *   disables the timer. The value must be set to 1 less count.                */
11064         } EEE_TWSYS_TIME_P0_b;
11065     };
11066 
11067     union
11068     {
11069         __IOM uint32_t IDLE_SLOPE_P0;       /*!< (@ 0x00000854) Port 0 MAC Traffic Shaper Bandwidth Control                */
11070 
11071         struct
11072         {
11073             __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
11074             uint32_t                  : 21;
11075         } IDLE_SLOPE_P0_b;
11076     };
11077 
11078     union
11079     {
11080         __IOM uint32_t CT_DELAY_P0;      /*!< (@ 0x00000858) Port 0 Cut-Through Delay Indication Register               */
11081 
11082         struct
11083         {
11084             __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
11085                                           *   of the MII PHY interface)                                                 */
11086             uint32_t : 23;
11087         } CT_DELAY_P0_b;
11088     };
11089 
11090     union
11091     {
11092         __IOM uint32_t BR_CONTROL_P0;            /*!< (@ 0x0000085C) Port 0 802.3br Frame Configuration Register                */
11093 
11094         struct
11095         {
11096             __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
11097             __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
11098                                                   *   preemption operation.                                                     */
11099             __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
11100                                                   *   frames.                                                                   */
11101             uint32_t                      : 1;
11102             __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
11103             uint32_t                      : 2;
11104             __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
11105             uint32_t                      : 1;
11106             __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
11107                                                   *   except the SFD are 0x55. When set to 0, only the last 2
11108                                                   *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
11109                                                   *   It is recommended to set this bit to 1 to comply with the
11110                                                   *   802.3br specification. This bit must be set to 0 if only
11111                                                   *   non-802.3br traffic is expected (for example, normal Ethernet
11112                                                   *   traffic) and if custom preamble is used.                                  */
11113             __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
11114                                                   *   SMDs and assumes all frames are express frames. This bit
11115                                                   *   must be set to 0 for correct operation with 802.3br, and
11116                                                   *   can be set to 1 when 802.3br is not enabled to avoid false
11117                                                   *   detection of SMDs.                                                        */
11118             __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
11119                                                   *   frames is enabled. When set to 1, the frame contents and
11120                                                   *   frame length checks are also performed on these frames.
11121                                                   *   The mCRC is always checked regardless of the value of this
11122                                                   *   register. This bit must be set to 0 to be compliant with
11123                                                   *   the functionality described in IEEE 802.3br.                              */
11124             __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
11125                                                   *   the mCRC for transmitted frames is inverted. This bit must
11126                                                   *   always be written to 0 and only used for debugging.                       */
11127             __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
11128                                                   *   the mCRC for received frames is inverted. This bit must
11129                                                   *   always be written to 0 and only used for debugging.                       */
11130             uint32_t : 11;
11131         } BR_CONTROL_P0_b;
11132     };
11133     __IM uint32_t RESERVED27[2];
11134 
11135     union
11136     {
11137         __IM uint32_t AFRAMESTRANSMITTEDOK_P0; /*!< (@ 0x00000868) Port 0 MAC Transmitted Valid Frame Count Register
11138                                                 *                  (n = 0 to 3)                                               */
11139 
11140         struct
11141         {
11142             __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
11143                                                 *   Transmitted, including pause.                                             */
11144         } AFRAMESTRANSMITTEDOK_P0_b;
11145     };
11146 
11147     union
11148     {
11149         __IM uint32_t AFRAMESRECEIVEDOK_P0;  /*!< (@ 0x0000086C) Port 0 MAC Received Valid Frame Count Register
11150                                               *                  (n = 0 to 3)                                               */
11151 
11152         struct
11153         {
11154             __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
11155                                               *   Received, including pause.                                                */
11156         } AFRAMESRECEIVEDOK_P0_b;
11157     };
11158 
11159     union
11160     {
11161         __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P0; /*!< (@ 0x00000870) Port 0 MAC FCS Error Frame Count Register (n
11162                                                      *                  = 0 to 3)                                                  */
11163 
11164         struct
11165         {
11166             __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
11167                                                      *   Length but CRC error.                                                     */
11168         } AFRAMECHECKSEQUENCEERRORS_P0_b;
11169     };
11170 
11171     union
11172     {
11173         __IM uint32_t AALIGNMENTERRORS_P0;   /*!< (@ 0x00000874) Port 0 MAC Alignment Error Frame Count Register
11174                                               *                  (n = 0 to 3)                                               */
11175 
11176         struct
11177         {
11178             __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
11179                                               *   of Nibbles (MII) Received.                                                */
11180         } AALIGNMENTERRORS_P0_b;
11181     };
11182 
11183     union
11184     {
11185         __IM uint32_t AOCTETSTRANSMITTEDOK_P0; /*!< (@ 0x00000878) Port 0 MAC Transmitted Valid Frame Octets Register
11186                                                 *                  (n = 0 to 3)                                               */
11187 
11188         struct
11189         {
11190             __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
11191                                                 *   only) of MAC Valid Transmitted.                                           */
11192         } AOCTETSTRANSMITTEDOK_P0_b;
11193     };
11194 
11195     union
11196     {
11197         __IM uint32_t AOCTETSRECEIVEDOK_P0;   /*!< (@ 0x0000087C) Port 0 MAC Received Valid Frame Octets Register
11198                                                *                  (n = 0 to 3)                                               */
11199 
11200         struct
11201         {
11202             __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
11203                                                *   only) of MAC Valid Received.                                              */
11204         } AOCTETSRECEIVEDOK_P0_b;
11205     };
11206 
11207     union
11208     {
11209         __IM uint32_t ATXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000880) Port 0 MAC Transmitted Pause Frame Count Register
11210                                                  *                  (n = 0 to 3)                                               */
11211 
11212         struct
11213         {
11214             __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
11215                                                  *   Pause Transmitted.                                                        */
11216         } ATXPAUSEMACCTRLFRAMES_P0_b;
11217     };
11218 
11219     union
11220     {
11221         __IM uint32_t ARXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000884) Port 0 MAC Received Pause Frame Count Register
11222                                                  *                  (n = 0 to 3)                                               */
11223 
11224         struct
11225         {
11226             __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
11227                                                  *   Pause Received.                                                           */
11228         } ARXPAUSEMACCTRLFRAMES_P0_b;
11229     };
11230 
11231     union
11232     {
11233         __IM uint32_t IFINERRORS_P0;       /*!< (@ 0x00000888) Port 0 MAC Input Error Count Register (n = 0
11234                                             *                  to 3)                                                      */
11235 
11236         struct
11237         {
11238             __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
11239                                             *   During Reception such as CRC, Length, PHY Error, RX FIFO
11240                                             *   Overflow.                                                                 */
11241         } IFINERRORS_P0_b;
11242     };
11243 
11244     union
11245     {
11246         __IM uint32_t IFOUTERRORS_P0;       /*!< (@ 0x0000088C) Port 0 MAC Output Error Count Register (n = 0
11247                                              *                  to 3)                                                      */
11248 
11249         struct
11250         {
11251             __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
11252                                              *   Transmitted with PHY error.                                               */
11253         } IFOUTERRORS_P0_b;
11254     };
11255 
11256     union
11257     {
11258         __IM uint32_t IFINUCASTPKTS_P0;      /*!< (@ 0x00000890) Port 0 MAC Received Unicast Frame Count Register
11259                                               *                  (n = 0 to 3)                                               */
11260 
11261         struct
11262         {
11263             __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
11264                                               *   Frame Valid Received.                                                     */
11265         } IFINUCASTPKTS_P0_b;
11266     };
11267 
11268     union
11269     {
11270         __IM uint32_t IFINMULTICASTPKTS_P0;  /*!< (@ 0x00000894) Port 0 MAC Received Multicast Frame Count Register
11271                                               *                  (n = 0 to 3)                                               */
11272 
11273         struct
11274         {
11275             __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
11276                                               *   Frame Valid Received.                                                     */
11277         } IFINMULTICASTPKTS_P0_b;
11278     };
11279 
11280     union
11281     {
11282         __IM uint32_t IFINBROADCASTPKTS_P0;  /*!< (@ 0x00000898) Port 0 MAC Received Broadcast Frame Count Register
11283                                               *                  (n = 0 to 3)                                               */
11284 
11285         struct
11286         {
11287             __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
11288                                               *   Frame Valid Received.                                                     */
11289         } IFINBROADCASTPKTS_P0_b;
11290     };
11291 
11292     union
11293     {
11294         __IM uint32_t IFOUTDISCARDS_P0;     /*!< (@ 0x0000089C) Port 0 MAC Discarded Outbound Frame Count Register
11295                                              *                  (n = 0 to 3)                                               */
11296 
11297         struct
11298         {
11299             __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
11300         } IFOUTDISCARDS_P0_b;
11301     };
11302 
11303     union
11304     {
11305         __IM uint32_t IFOUTUCASTPKTS_P0;     /*!< (@ 0x000008A0) Port 0 MAC Transmitted Unicast Frame Count Register
11306                                               *                  (n = 0 to 3)                                               */
11307 
11308         struct
11309         {
11310             __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
11311                                               *   Frame Valid Transmitted.                                                  */
11312         } IFOUTUCASTPKTS_P0_b;
11313     };
11314 
11315     union
11316     {
11317         __IM uint32_t IFOUTMULTICASTPKTS_P0; /*!< (@ 0x000008A4) Port 0 MAC Transmitted Multicast Frame Count
11318                                               *                  Register (n = 0 to 3)                                      */
11319 
11320         struct
11321         {
11322             __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
11323                                               *   Frame Valid Transmitted.                                                  */
11324         } IFOUTMULTICASTPKTS_P0_b;
11325     };
11326 
11327     union
11328     {
11329         __IM uint32_t IFOUTBROADCASTPKTS_P0; /*!< (@ 0x000008A8) Port 0 MAC Transmitted Broadcast Frame Count
11330                                               *                  Register (n = 0 to 3)                                      */
11331 
11332         struct
11333         {
11334             __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
11335                                               *   Frame Valid Transmitted.                                                  */
11336         } IFOUTBROADCASTPKTS_P0_b;
11337     };
11338 
11339     union
11340     {
11341         __IM uint32_t ETHERSTATSDROPEVENTS_P0; /*!< (@ 0x000008AC) Port 0 MAC Dropped Frame Count Register (n =
11342                                                 *                  0 to 3)                                                    */
11343 
11344         struct
11345         {
11346             __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
11347                                                 *   Full at frame start.                                                      */
11348         } ETHERSTATSDROPEVENTS_P0_b;
11349     };
11350 
11351     union
11352     {
11353         __IM uint32_t ETHERSTATSOCTETS_P0; /*!< (@ 0x000008B0) Port 0 MAC All Frame Octets Register (n = 0 to
11354                                             *                  3)                                                         */
11355 
11356         struct
11357         {
11358             __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
11359         } ETHERSTATSOCTETS_P0_b;
11360     };
11361 
11362     union
11363     {
11364         __IM uint32_t ETHERSTATSPKTS_P0; /*!< (@ 0x000008B4) Port 0 MAC All Frame Count Register (n = 0 to
11365                                           *                  3)                                                         */
11366 
11367         struct
11368         {
11369             __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
11370         } ETHERSTATSPKTS_P0_b;
11371     };
11372 
11373     union
11374     {
11375         __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P0; /*!< (@ 0x000008B8) Port 0 MAC Too Short Frame Count Register (n
11376                                                    *                  = 0 to 3)                                                  */
11377 
11378         struct
11379         {
11380             __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
11381                                                    *   Good CRC.                                                                 */
11382         } ETHERSTATSUNDERSIZEPKTS_P0_b;
11383     };
11384 
11385     union
11386     {
11387         __IM uint32_t ETHERSTATSOVERSIZEPKTS_P0; /*!< (@ 0x000008BC) Port 0 MAC Too Long Frame Count Register (n =
11388                                                   *                  0 to 3)                                                    */
11389 
11390         struct
11391         {
11392             __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
11393                                                   *   Good CRC.                                                                 */
11394         } ETHERSTATSOVERSIZEPKTS_P0_b;
11395     };
11396 
11397     union
11398     {
11399         __IM uint32_t ETHERSTATSPKTS64OCTETS_P0; /*!< (@ 0x000008C0) Port 0 MAC 64 Octets Frame Count Register (n
11400                                                   *                  = 0 to 3)                                                  */
11401 
11402         struct
11403         {
11404             __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
11405                                                   *   Good and Bad (Packet Size: 64 bytes).                                     */
11406         } ETHERSTATSPKTS64OCTETS_P0_b;
11407     };
11408 
11409     union
11410     {
11411         __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P0; /*!< (@ 0x000008C4) Port 0 MAC 65 to 127 Octets Frame Count Register
11412                                                        *                (n = 0 to 3)                                               */
11413 
11414         struct
11415         {
11416             __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
11417                                                        *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
11418         } ETHERSTATSPKTS65TO127OCTETS_P0_b;
11419     };
11420 
11421     union
11422     {
11423         __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P0; /*!< (@ 0x000008C8) Port 0 MAC 128 to 255 Octets Frame Count Register
11424                                                         *               (n = 0 to 3)                                               */
11425 
11426         struct
11427         {
11428             __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
11429                                                         *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
11430         } ETHERSTATSPKTS128TO255OCTETS_P0_b;
11431     };
11432 
11433     union
11434     {
11435         __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P0; /*!< (@ 0x000008CC) Port 0 MAC 256 to 511 Octets Frame Count Register
11436                                                         *               (n = 0 to 3)                                               */
11437 
11438         struct
11439         {
11440             __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
11441                                                         *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
11442         } ETHERSTATSPKTS256TO511OCTETS_P0_b;
11443     };
11444 
11445     union
11446     {
11447         __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P0; /*!< (@ 0x000008D0) Port 0 MAC 512 to 1023 Octets Frame Count Register
11448                                                          *              (n = 0 to 3)                                               */
11449 
11450         struct
11451         {
11452             __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
11453                                                          *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
11454         } ETHERSTATSPKTS512TO1023OCTETS_P0_b;
11455     };
11456 
11457     union
11458     {
11459         __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P0; /*!< (@ 0x000008D4) Port 0 MAC 1024 to 1518 Octets Frame Count Register
11460                                                           *             (n = 0 to 3)                                               */
11461 
11462         struct
11463         {
11464             __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
11465                                                           *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
11466         } ETHERSTATSPKTS1024TO1518OCTETS_P0_b;
11467     };
11468 
11469     union
11470     {
11471         __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P0; /*!< (@ 0x000008D8) Port 0 MAC Over 1519 Octets Frame Count Register
11472                                                        *                (n = 0 to 3)                                               */
11473 
11474         struct
11475         {
11476             __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
11477                                                        *   Good and Bad (Packet Size: over 1519 bytes).                              */
11478         } ETHERSTATSPKTS1519TOXOCTETS_P0_b;
11479     };
11480 
11481     union
11482     {
11483         __IM uint32_t ETHERSTATSJABBERS_P0; /*!< (@ 0x000008DC) Port 0 MAC Jabbers Frame Count Register (n =
11484                                              *                  0 to 3)                                                    */
11485 
11486         struct
11487         {
11488             __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
11489                                              *   Bad CRC.                                                                  */
11490         } ETHERSTATSJABBERS_P0_b;
11491     };
11492 
11493     union
11494     {
11495         __IM uint32_t ETHERSTATSFRAGMENTS_P0; /*!< (@ 0x000008E0) Port 0 MAC Fragment Frame Count Register (n =
11496                                                *                  0 to 3)                                                    */
11497 
11498         struct
11499         {
11500             __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
11501                                                *   Bad CRC.                                                                  */
11502         } ETHERSTATSFRAGMENTS_P0_b;
11503     };
11504     __IM uint32_t RESERVED28;
11505 
11506     union
11507     {
11508         __IM uint32_t VLANRECEIVEDOK_P0;     /*!< (@ 0x000008E8) Port 0 MAC Received VLAN Tagged Frame Count Register
11509                                               *                  (n = 0 to 3)                                               */
11510 
11511         struct
11512         {
11513             __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
11514                                               *   with VLAN Tag Received.                                                   */
11515         } VLANRECEIVEDOK_P0_b;
11516     };
11517     __IM uint32_t RESERVED29[2];
11518 
11519     union
11520     {
11521         __IM uint32_t VLANTRANSMITTEDOK_P0;  /*!< (@ 0x000008F4) Port 0 MAC Transmitted VLAN Tagged Frame Count
11522                                               *                  Register (n = 0 to 3)                                      */
11523 
11524         struct
11525         {
11526             __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
11527                                               *   with VLAN Tag Transmitted.                                                */
11528         } VLANTRANSMITTEDOK_P0_b;
11529     };
11530 
11531     union
11532     {
11533         __IM uint32_t FRAMESRETRANSMITTED_P0; /*!< (@ 0x000008F8) Port 0 MAC Retransmitted Frame Count Register
11534                                                *                  (n = 0 to 3)                                               */
11535 
11536         struct
11537         {
11538             __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
11539                                                *   Frames that experienced a collision and were retransmitted.               */
11540         } FRAMESRETRANSMITTED_P0_b;
11541     };
11542     __IM uint32_t RESERVED30;
11543 
11544     union
11545     {
11546         __IM uint32_t STATS_HIWORD_P0;       /*!< (@ 0x00000900) Port 0 MAC Statistics Counter High Word Register
11547                                               *                  (n = 0 to 3)                                               */
11548 
11549         struct
11550         {
11551             __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
11552                                               *   Counter Last Read                                                         */
11553         } STATS_HIWORD_P0_b;
11554     };
11555 
11556     union
11557     {
11558         __IOM uint32_t STATS_CTRL_P0;   /*!< (@ 0x00000904) Port 0 MAC Statistics Control Register (n = 0
11559                                          *                  to 3)                                                      */
11560 
11561         struct
11562         {
11563             __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
11564             __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
11565             uint32_t               : 30;
11566         } STATS_CTRL_P0_b;
11567     };
11568 
11569     union
11570     {
11571         __IOM uint32_t STATS_CLEAR_VALUELO_P0;       /*!< (@ 0x00000908) Port 0 MAC Statistics Clear Value Lower Register
11572                                                       *                  (n = 0 to 3)                                               */
11573 
11574         struct
11575         {
11576             __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
11577                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
11578                                                       *   command for test purposes. These bits should be set to
11579                                                       *   0 normally.                                                               */
11580         } STATS_CLEAR_VALUELO_P0_b;
11581     };
11582 
11583     union
11584     {
11585         __IOM uint32_t STATS_CLEAR_VALUEHI_P0;       /*!< (@ 0x0000090C) Port 0 MAC Statistics Clear Value Higher Register
11586                                                       *                  (n = 0 to 3)                                               */
11587 
11588         struct
11589         {
11590             __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
11591                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
11592                                                       *   command for test purposes. These bits should be set to
11593                                                       *   0 normally.                                                               */
11594         } STATS_CLEAR_VALUEHI_P0_b;
11595     };
11596 
11597     union
11598     {
11599         __IM uint32_t ADEFERRED_P0;        /*!< (@ 0x00000910) Port 0 MAC Deferred Count Register (n = 0 to
11600                                             *                  3)                                                         */
11601 
11602         struct
11603         {
11604             __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
11605                                             *   without collision but was deferred at begin.                              */
11606         } ADEFERRED_P0_b;
11607     };
11608 
11609     union
11610     {
11611         __IM uint32_t AMULTIPLECOLLISIONS_P0;   /*!< (@ 0x00000914) Port 0 MAC Multiple Collision Count Register
11612                                                  *                  (n = 0 to 3)                                               */
11613 
11614         struct
11615         {
11616             __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
11617                                                  *   Transmit after multiple collisions.                                       */
11618         } AMULTIPLECOLLISIONS_P0_b;
11619     };
11620 
11621     union
11622     {
11623         __IM uint32_t ASINGLECOLLISIONS_P0;      /*!< (@ 0x00000918) Port 0 MAC Single Collision Count Register (n
11624                                                   *                  = 0 to 3)                                                  */
11625 
11626         struct
11627         {
11628             __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
11629                                                   *   Transmit after single collision.                                          */
11630         } ASINGLECOLLISIONS_P0_b;
11631     };
11632 
11633     union
11634     {
11635         __IM uint32_t ALATECOLLISIONS_P0;     /*!< (@ 0x0000091C) Port 0 MAC Late Collision Count Register (n =
11636                                                *                  0 to 3)                                                    */
11637 
11638         struct
11639         {
11640             __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
11641                                                *   Collision. Frame was aborted and not retransmitted.                       */
11642         } ALATECOLLISIONS_P0_b;
11643     };
11644 
11645     union
11646     {
11647         __IM uint32_t AEXCESSIVECOLLISIONS_P0; /*!< (@ 0x00000920) Port 0 MAC Excessive Collision Count Register
11648                                                 *                  (n = 0 to 3)                                               */
11649 
11650         struct
11651         {
11652             __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
11653                                                 *   due to 16 consecutive collisions.                                         */
11654         } AEXCESSIVECOLLISIONS_P0_b;
11655     };
11656 
11657     union
11658     {
11659         __IM uint32_t ACARRIERSENSEERRORS_P0; /*!< (@ 0x00000924) Port 0 MAC Carrier Sense Error Count Register
11660                                                *                  (n = 0 to 3)                                               */
11661 
11662         struct
11663         {
11664             __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
11665                                                *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
11666                                                *   asserted.                                                                 */
11667         } ACARRIERSENSEERRORS_P0_b;
11668     };
11669     __IM uint32_t RESERVED31[182];
11670 
11671     union
11672     {
11673         __IM uint32_t REV_P1;          /*!< (@ 0x00000C00) Port 1 MAC Core Revision (n = 0 to 3)                      */
11674 
11675         struct
11676         {
11677             __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
11678         } REV_P1_b;
11679     };
11680     __IM uint32_t RESERVED32;
11681 
11682     union
11683     {
11684         __IOM uint32_t COMMAND_CONFIG_P1;       /*!< (@ 0x00000C08) Port 1 Command Configuration Register (n = 0
11685                                                  *                  to 3)                                                      */
11686 
11687         struct
11688         {
11689             __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
11690             __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
11691             __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
11692                                                  *   the IMC until the current frame is completed. This can
11693                                                  *   cause the IPG between frames to be more than the value
11694                                                  *   in TX_IPG_LENGTH.                                                         */
11695             __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
11696             __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
11697             __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
11698             uint32_t                    : 1;
11699             __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
11700             __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
11701             __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
11702             __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
11703                                                  *   full-duplex only (set to 0).                                              */
11704             __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
11705             uint32_t                     : 1;
11706             __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
11707             uint32_t                     : 9;
11708             __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
11709             __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
11710             __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
11711                                                  *   register.                                                                 */
11712             __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
11713             __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
11714             uint32_t                   : 2;
11715             __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
11716                                                  *   on transmit and on receive. The value is used when not
11717                                                  *   overridden by the PTP auto-response function, pattern matchers
11718                                                  *   or force forwarding information in a management tag.                      */
11719             uint32_t : 1;
11720         } COMMAND_CONFIG_P1_b;
11721     };
11722 
11723     union
11724     {
11725         __IOM uint32_t MAC_ADDR_0_P1;     /*!< (@ 0x00000C0C) Port 1 MAC Address Register 0 (n = 0 to 2)                 */
11726 
11727         struct
11728         {
11729             __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
11730                                            *   byte is bits [7:0]. The MAC address is used on locally
11731                                            *   generated frames such as pause frames, peer-delay response.               */
11732         } MAC_ADDR_0_P1_b;
11733     };
11734 
11735     union
11736     {
11737         __IOM uint32_t MAC_ADDR_1_P1;     /*!< (@ 0x00000C10) Port 1 MAC Address Register 1 (n = 0 to 2)                 */
11738 
11739         struct
11740         {
11741             __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
11742                                            *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
11743             uint32_t : 16;
11744         } MAC_ADDR_1_P1_b;
11745     };
11746 
11747     union
11748     {
11749         __IOM uint32_t FRM_LENGTH_P1;       /*!< (@ 0x00000C14) Port 1 Maximum Frame Length Register (n = 0 to
11750                                              *                  3)                                                         */
11751 
11752         struct
11753         {
11754             __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
11755             uint32_t                  : 18;
11756         } FRM_LENGTH_P1_b;
11757     };
11758 
11759     union
11760     {
11761         __IM uint32_t PAUSE_QUANT_P1;       /*!< (@ 0x00000C18) Port 1 MAC Pause Quanta (n = 0 to 3)                       */
11762 
11763         struct
11764         {
11765             __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
11766             uint32_t                  : 16;
11767         } PAUSE_QUANT_P1_b;
11768     };
11769 
11770     union
11771     {
11772         __IOM uint32_t MAC_LINK_QTRIG_P1;  /*!< (@ 0x00000C1C) Port 1 Trigger Event Configuration Register (n
11773                                             *                  = 0 to 2)                                                  */
11774 
11775         struct
11776         {
11777             __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
11778             uint32_t                  : 12;
11779             __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
11780                                             *   is transmitted from the ports indicated by PORT_MASK. A
11781                                             *   single frame is transmitted per indicated port in PORT_MASK
11782                                             *   among the queues indicated by QUEUE_MASK.                                 */
11783             uint32_t                 : 4;
11784             __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
11785                                             *   a frame was transmitted. When MODE is set to 0, TRIGGERED
11786                                             *   is always 0. This flag clears when the register is written.               */
11787             __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
11788                                             *   set to 1, the Link Queue Trigger occurs only if the DLR
11789                                             *   state machine is in the NORMAL or FAULT state.                            */
11790             __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
11791                                             *   This is to prevent sending multiple frames due to link
11792                                             *   flapping.                                                                 */
11793             __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
11794                                             *   When the link status (phy_link) transitions from 1 ->
11795                                             *   0, a trigger event is generated to the memory controller
11796                                             *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
11797         } MAC_LINK_QTRIG_P1_b;
11798     };
11799     __IM uint32_t RESERVED33[4];
11800 
11801     union
11802     {
11803         __IOM uint32_t PTPCLOCKIDENTITY1_P1;  /*!< (@ 0x00000C30) Port 1 PTP Clock Identity 1 Register (n = 0 to
11804                                                *                  2)                                                         */
11805 
11806         struct
11807         {
11808             __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
11809             __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
11810             __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
11811             __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
11812         } PTPCLOCKIDENTITY1_P1_b;
11813     };
11814 
11815     union
11816     {
11817         __IOM uint32_t PTPCLOCKIDENTITY2_P1;  /*!< (@ 0x00000C34) Port 1 PTP Clock Identity 2 Register (n = 0 to
11818                                                *                  2)                                                         */
11819 
11820         struct
11821         {
11822             __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
11823             __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
11824             __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
11825             __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
11826         } PTPCLOCKIDENTITY2_P1_b;
11827     };
11828 
11829     union
11830     {
11831         __IOM uint32_t PTPAUTORESPONSE_P1; /*!< (@ 0x00000C38) Port 1 PTP Auto Response Register (n = 0 to 2)             */
11832 
11833         struct
11834         {
11835             __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
11836             __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
11837             uint32_t                : 14;
11838             __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
11839             __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
11840         } PTPAUTORESPONSE_P1_b;
11841     };
11842     __IM uint32_t RESERVED34;
11843 
11844     union
11845     {
11846         __IOM uint32_t STATUS_P1;          /*!< (@ 0x00000C40) Port 1 Status Register                                     */
11847 
11848         struct
11849         {
11850             __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
11851             __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
11852             __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
11853             __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
11854                                             *   never occur during normal operation.                                      */
11855             __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
11856                                             *   to complete in time before the next frame was received
11857                                             *   at the port. This should never occur under normal operation.
11858                                             *   The cause could be from IPG violations in the received
11859                                             *   frames.                                                                   */
11860             __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
11861                                             *   to clause 30.14.1.2 of the 802.3br specification                          */
11862             uint32_t : 23;
11863         } STATUS_P1_b;
11864     };
11865 
11866     union
11867     {
11868         __IOM uint32_t TX_IPG_LENGTH_P1;      /*!< (@ 0x00000C44) Port 1 Transmit IPG Length Register (n = 0 to
11869                                                *                  3)                                                         */
11870 
11871         struct
11872         {
11873             __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
11874                                                *   are in the range of 8 to 31.                                              */
11875             uint32_t                  : 11;
11876             __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
11877             uint32_t                  : 11;
11878         } TX_IPG_LENGTH_P1_b;
11879     };
11880 
11881     union
11882     {
11883         __IOM uint32_t EEE_CTL_STAT_P1;        /*!< (@ 0x00000C48) Port 1 MAC EEE Functions Control and Status (n
11884                                                 *                  = 0 to 2)                                                  */
11885 
11886         struct
11887         {
11888             __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
11889             __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
11890             __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
11891             uint32_t                    : 5;
11892             __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
11893             __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
11894             __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
11895             __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
11896                                                 *   available for transmission.                                               */
11897             __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
11898             uint32_t                      : 3;
11899             __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
11900             __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
11901                                                 *   MAC                                                                       */
11902             __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
11903             uint32_t                   : 1;
11904             __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
11905             uint32_t                   : 11;
11906         } EEE_CTL_STAT_P1_b;
11907     };
11908 
11909     union
11910     {
11911         __IOM uint32_t EEE_IDLE_TIME_P1;       /*!< (@ 0x00000C4C) Port 1 EEE Idle Time Register (n = 0 to 2)                 */
11912 
11913         struct
11914         {
11915             __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
11916                                                 *   of LPI begins. A 32-bit value in steps of 32 switch operating
11917                                                 *   clock cycles. A value of 0 disables the timer. The value
11918                                                 *   must be set to 1 less count.                                              */
11919         } EEE_IDLE_TIME_P1_b;
11920     };
11921 
11922     union
11923     {
11924         __IOM uint32_t EEE_TWSYS_TIME_P1;      /*!< (@ 0x00000C50) Port 1 EEE Wake Up Time Register (n = 0 to 2)              */
11925 
11926         struct
11927         {
11928             __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
11929                                                 *   to begin transmitting the first frame again. A 32-bit value
11930                                                 *   in steps of switch operating clock cycles. A value of 0
11931                                                 *   disables the timer. The value must be set to 1 less count.                */
11932         } EEE_TWSYS_TIME_P1_b;
11933     };
11934 
11935     union
11936     {
11937         __IOM uint32_t IDLE_SLOPE_P1;       /*!< (@ 0x00000C54) Port 1 MAC Traffic Shaper Bandwidth Control                */
11938 
11939         struct
11940         {
11941             __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
11942             uint32_t                  : 21;
11943         } IDLE_SLOPE_P1_b;
11944     };
11945 
11946     union
11947     {
11948         __IOM uint32_t CT_DELAY_P1;      /*!< (@ 0x00000C58) Port 1 Cut-Through Delay Indication Register               */
11949 
11950         struct
11951         {
11952             __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
11953                                           *   of the MII PHY interface)                                                 */
11954             uint32_t : 23;
11955         } CT_DELAY_P1_b;
11956     };
11957 
11958     union
11959     {
11960         __IOM uint32_t BR_CONTROL_P1;            /*!< (@ 0x00000C5C) Port 1 802.3br Frame Configuration Register                */
11961 
11962         struct
11963         {
11964             __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
11965             __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
11966                                                   *   preemption operation.                                                     */
11967             __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
11968                                                   *   frames.                                                                   */
11969             uint32_t                      : 1;
11970             __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
11971             uint32_t                      : 2;
11972             __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
11973             uint32_t                      : 1;
11974             __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
11975                                                   *   except the SFD are 0x55. When set to 0, only the last 2
11976                                                   *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
11977                                                   *   It is recommended to set this bit to 1 to comply with the
11978                                                   *   802.3br specification. This bit must be set to 0 if only
11979                                                   *   non-802.3br traffic is expected (for example, normal Ethernet
11980                                                   *   traffic) and if custom preamble is used.                                  */
11981             __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
11982                                                   *   SMDs and assumes all frames are express frames. This bit
11983                                                   *   must be set to 0 for correct operation with 802.3br, and
11984                                                   *   can be set to 1 when 802.3br is not enabled to avoid false
11985                                                   *   detection of SMDs.                                                        */
11986             __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
11987                                                   *   frames is enabled. When set to 1, the frame contents and
11988                                                   *   frame length checks are also performed on these frames.
11989                                                   *   The mCRC is always checked regardless of the value of this
11990                                                   *   register. This bit must be set to 0 to be compliant with
11991                                                   *   the functionality described in IEEE 802.3br.                              */
11992             __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
11993                                                   *   the mCRC for transmitted frames is inverted. This bit must
11994                                                   *   always be written to 0 and only used for debugging.                       */
11995             __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
11996                                                   *   the mCRC for received frames is inverted. This bit must
11997                                                   *   always be written to 0 and only used for debugging.                       */
11998             uint32_t : 11;
11999         } BR_CONTROL_P1_b;
12000     };
12001     __IM uint32_t RESERVED35[2];
12002 
12003     union
12004     {
12005         __IM uint32_t AFRAMESTRANSMITTEDOK_P1; /*!< (@ 0x00000C68) Port 1 MAC Transmitted Valid Frame Count Register
12006                                                 *                  (n = 0 to 3)                                               */
12007 
12008         struct
12009         {
12010             __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12011                                                 *   Transmitted, including pause.                                             */
12012         } AFRAMESTRANSMITTEDOK_P1_b;
12013     };
12014 
12015     union
12016     {
12017         __IM uint32_t AFRAMESRECEIVEDOK_P1;  /*!< (@ 0x00000C6C) Port 1 MAC Received Valid Frame Count Register
12018                                               *                  (n = 0 to 3)                                               */
12019 
12020         struct
12021         {
12022             __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12023                                               *   Received, including pause.                                                */
12024         } AFRAMESRECEIVEDOK_P1_b;
12025     };
12026 
12027     union
12028     {
12029         __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P1; /*!< (@ 0x00000C70) Port 1 MAC FCS Error Frame Count Register (n
12030                                                      *                  = 0 to 3)                                                  */
12031 
12032         struct
12033         {
12034             __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12035                                                      *   Length but CRC error.                                                     */
12036         } AFRAMECHECKSEQUENCEERRORS_P1_b;
12037     };
12038 
12039     union
12040     {
12041         __IM uint32_t AALIGNMENTERRORS_P1;   /*!< (@ 0x00000C74) Port 1 MAC Alignment Error Frame Count Register
12042                                               *                  (n = 0 to 3)                                               */
12043 
12044         struct
12045         {
12046             __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
12047                                               *   of Nibbles (MII) Received.                                                */
12048         } AALIGNMENTERRORS_P1_b;
12049     };
12050 
12051     union
12052     {
12053         __IM uint32_t AOCTETSTRANSMITTEDOK_P1; /*!< (@ 0x00000C78) Port 1 MAC Transmitted Valid Frame Octets Register
12054                                                 *                  (n = 0 to 3)                                               */
12055 
12056         struct
12057         {
12058             __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
12059                                                 *   only) of MAC Valid Transmitted.                                           */
12060         } AOCTETSTRANSMITTEDOK_P1_b;
12061     };
12062 
12063     union
12064     {
12065         __IM uint32_t AOCTETSRECEIVEDOK_P1;   /*!< (@ 0x00000C7C) Port 1 MAC Received Valid Frame Octets Register
12066                                                *                  (n = 0 to 3)                                               */
12067 
12068         struct
12069         {
12070             __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
12071                                                *   only) of MAC Valid Received.                                              */
12072         } AOCTETSRECEIVEDOK_P1_b;
12073     };
12074 
12075     union
12076     {
12077         __IM uint32_t ATXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C80) Port 1 MAC Transmitted Pause Frame Count Register
12078                                                  *                  (n = 0 to 3)                                               */
12079 
12080         struct
12081         {
12082             __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12083                                                  *   Pause Transmitted.                                                        */
12084         } ATXPAUSEMACCTRLFRAMES_P1_b;
12085     };
12086 
12087     union
12088     {
12089         __IM uint32_t ARXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C84) Port 1 MAC Received Pause Frame Count Register
12090                                                  *                  (n = 0 to 3)                                               */
12091 
12092         struct
12093         {
12094             __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12095                                                  *   Pause Received.                                                           */
12096         } ARXPAUSEMACCTRLFRAMES_P1_b;
12097     };
12098 
12099     union
12100     {
12101         __IM uint32_t IFINERRORS_P1;       /*!< (@ 0x00000C88) Port 1 MAC Input Error Count Register (n = 0
12102                                             *                  to 3)                                                      */
12103 
12104         struct
12105         {
12106             __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
12107                                             *   During Reception such as CRC, Length, PHY Error, RX FIFO
12108                                             *   Overflow.                                                                 */
12109         } IFINERRORS_P1_b;
12110     };
12111 
12112     union
12113     {
12114         __IM uint32_t IFOUTERRORS_P1;       /*!< (@ 0x00000C8C) Port 1 MAC Output Error Count Register (n = 0
12115                                              *                  to 3)                                                      */
12116 
12117         struct
12118         {
12119             __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
12120                                              *   Transmitted with PHY error.                                               */
12121         } IFOUTERRORS_P1_b;
12122     };
12123 
12124     union
12125     {
12126         __IM uint32_t IFINUCASTPKTS_P1;      /*!< (@ 0x00000C90) Port 1 MAC Received Unicast Frame Count Register
12127                                               *                  (n = 0 to 3)                                               */
12128 
12129         struct
12130         {
12131             __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
12132                                               *   Frame Valid Received.                                                     */
12133         } IFINUCASTPKTS_P1_b;
12134     };
12135 
12136     union
12137     {
12138         __IM uint32_t IFINMULTICASTPKTS_P1;  /*!< (@ 0x00000C94) Port 1 MAC Received Multicast Frame Count Register
12139                                               *                  (n = 0 to 3)                                               */
12140 
12141         struct
12142         {
12143             __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
12144                                               *   Frame Valid Received.                                                     */
12145         } IFINMULTICASTPKTS_P1_b;
12146     };
12147 
12148     union
12149     {
12150         __IM uint32_t IFINBROADCASTPKTS_P1;  /*!< (@ 0x00000C98) Port 1 MAC Received Broadcast Frame Count Register
12151                                               *                  (n = 0 to 3)                                               */
12152 
12153         struct
12154         {
12155             __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
12156                                               *   Frame Valid Received.                                                     */
12157         } IFINBROADCASTPKTS_P1_b;
12158     };
12159 
12160     union
12161     {
12162         __IM uint32_t IFOUTDISCARDS_P1;     /*!< (@ 0x00000C9C) Port 1 MAC Discarded Outbound Frame Count Register
12163                                              *                  (n = 0 to 3)                                               */
12164 
12165         struct
12166         {
12167             __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
12168         } IFOUTDISCARDS_P1_b;
12169     };
12170 
12171     union
12172     {
12173         __IM uint32_t IFOUTUCASTPKTS_P1;     /*!< (@ 0x00000CA0) Port 1 MAC Transmitted Unicast Frame Count Register
12174                                               *                  (n = 0 to 3)                                               */
12175 
12176         struct
12177         {
12178             __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
12179                                               *   Frame Valid Transmitted.                                                  */
12180         } IFOUTUCASTPKTS_P1_b;
12181     };
12182 
12183     union
12184     {
12185         __IM uint32_t IFOUTMULTICASTPKTS_P1; /*!< (@ 0x00000CA4) Port 1 MAC Transmitted Multicast Frame Count
12186                                               *                  Register (n = 0 to 3)                                      */
12187 
12188         struct
12189         {
12190             __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
12191                                               *   Frame Valid Transmitted.                                                  */
12192         } IFOUTMULTICASTPKTS_P1_b;
12193     };
12194 
12195     union
12196     {
12197         __IM uint32_t IFOUTBROADCASTPKTS_P1; /*!< (@ 0x00000CA8) Port 1 MAC Transmitted Broadcast Frame Count
12198                                               *                  Register (n = 0 to 3)                                      */
12199 
12200         struct
12201         {
12202             __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
12203                                               *   Frame Valid Transmitted.                                                  */
12204         } IFOUTBROADCASTPKTS_P1_b;
12205     };
12206 
12207     union
12208     {
12209         __IM uint32_t ETHERSTATSDROPEVENTS_P1; /*!< (@ 0x00000CAC) Port 1 MAC Dropped Frame Count Register (n =
12210                                                 *                  0 to 3)                                                    */
12211 
12212         struct
12213         {
12214             __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
12215                                                 *   Full at frame start.                                                      */
12216         } ETHERSTATSDROPEVENTS_P1_b;
12217     };
12218 
12219     union
12220     {
12221         __IM uint32_t ETHERSTATSOCTETS_P1; /*!< (@ 0x00000CB0) Port 1 MAC All Frame Octets Register (n = 0 to
12222                                             *                  3)                                                         */
12223 
12224         struct
12225         {
12226             __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
12227         } ETHERSTATSOCTETS_P1_b;
12228     };
12229 
12230     union
12231     {
12232         __IM uint32_t ETHERSTATSPKTS_P1; /*!< (@ 0x00000CB4) Port 1 MAC All Frame Count Register (n = 0 to
12233                                           *                  3)                                                         */
12234 
12235         struct
12236         {
12237             __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
12238         } ETHERSTATSPKTS_P1_b;
12239     };
12240 
12241     union
12242     {
12243         __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P1; /*!< (@ 0x00000CB8) Port 1 MAC Too Short Frame Count Register (n
12244                                                    *                  = 0 to 3)                                                  */
12245 
12246         struct
12247         {
12248             __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
12249                                                    *   Good CRC.                                                                 */
12250         } ETHERSTATSUNDERSIZEPKTS_P1_b;
12251     };
12252 
12253     union
12254     {
12255         __IM uint32_t ETHERSTATSOVERSIZEPKTS_P1; /*!< (@ 0x00000CBC) Port 1 MAC Too Long Frame Count Register (n =
12256                                                   *                  0 to 3)                                                    */
12257 
12258         struct
12259         {
12260             __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
12261                                                   *   Good CRC.                                                                 */
12262         } ETHERSTATSOVERSIZEPKTS_P1_b;
12263     };
12264 
12265     union
12266     {
12267         __IM uint32_t ETHERSTATSPKTS64OCTETS_P1; /*!< (@ 0x00000CC0) Port 1 MAC 64 Octets Frame Count Register (n
12268                                                   *                  = 0 to 3)                                                  */
12269 
12270         struct
12271         {
12272             __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
12273                                                   *   Good and Bad (Packet Size: 64 bytes).                                     */
12274         } ETHERSTATSPKTS64OCTETS_P1_b;
12275     };
12276 
12277     union
12278     {
12279         __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P1; /*!< (@ 0x00000CC4) Port 1 MAC 65 to 127 Octets Frame Count Register
12280                                                        *                (n = 0 to 3)                                               */
12281 
12282         struct
12283         {
12284             __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
12285                                                        *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
12286         } ETHERSTATSPKTS65TO127OCTETS_P1_b;
12287     };
12288 
12289     union
12290     {
12291         __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P1; /*!< (@ 0x00000CC8) Port 1 MAC 128 to 255 Octets Frame Count Register
12292                                                         *               (n = 0 to 3)                                               */
12293 
12294         struct
12295         {
12296             __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
12297                                                         *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
12298         } ETHERSTATSPKTS128TO255OCTETS_P1_b;
12299     };
12300 
12301     union
12302     {
12303         __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P1; /*!< (@ 0x00000CCC) Port 1 MAC 256 to 511 Octets Frame Count Register
12304                                                         *               (n = 0 to 3)                                               */
12305 
12306         struct
12307         {
12308             __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
12309                                                         *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
12310         } ETHERSTATSPKTS256TO511OCTETS_P1_b;
12311     };
12312 
12313     union
12314     {
12315         __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P1; /*!< (@ 0x00000CD0) Port 1 MAC 512 to 1023 Octets Frame Count Register
12316                                                          *              (n = 0 to 3)                                               */
12317 
12318         struct
12319         {
12320             __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
12321                                                          *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
12322         } ETHERSTATSPKTS512TO1023OCTETS_P1_b;
12323     };
12324 
12325     union
12326     {
12327         __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P1; /*!< (@ 0x00000CD4) Port 1 MAC 1024 to 1518 Octets Frame Count Register
12328                                                           *             (n = 0 to 3)                                               */
12329 
12330         struct
12331         {
12332             __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
12333                                                           *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
12334         } ETHERSTATSPKTS1024TO1518OCTETS_P1_b;
12335     };
12336 
12337     union
12338     {
12339         __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P1; /*!< (@ 0x00000CD8) Port 1 MAC Over 1519 Octets Frame Count Register
12340                                                        *                (n = 0 to 3)                                               */
12341 
12342         struct
12343         {
12344             __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
12345                                                        *   Good and Bad (Packet Size: over 1519 bytes).                              */
12346         } ETHERSTATSPKTS1519TOXOCTETS_P1_b;
12347     };
12348 
12349     union
12350     {
12351         __IM uint32_t ETHERSTATSJABBERS_P1; /*!< (@ 0x00000CDC) Port 1 MAC Jabbers Frame Count Register (n =
12352                                              *                  0 to 3)                                                    */
12353 
12354         struct
12355         {
12356             __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
12357                                              *   Bad CRC.                                                                  */
12358         } ETHERSTATSJABBERS_P1_b;
12359     };
12360 
12361     union
12362     {
12363         __IM uint32_t ETHERSTATSFRAGMENTS_P1; /*!< (@ 0x00000CE0) Port 1 MAC Fragment Frame Count Register (n =
12364                                                *                  0 to 3)                                                    */
12365 
12366         struct
12367         {
12368             __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
12369                                                *   Bad CRC.                                                                  */
12370         } ETHERSTATSFRAGMENTS_P1_b;
12371     };
12372     __IM uint32_t RESERVED36;
12373 
12374     union
12375     {
12376         __IM uint32_t VLANRECEIVEDOK_P1;     /*!< (@ 0x00000CE8) Port 1 MAC Received VLAN Tagged Frame Count Register
12377                                               *                  (n = 0 to 3)                                               */
12378 
12379         struct
12380         {
12381             __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
12382                                               *   with VLAN Tag Received.                                                   */
12383         } VLANRECEIVEDOK_P1_b;
12384     };
12385     __IM uint32_t RESERVED37[2];
12386 
12387     union
12388     {
12389         __IM uint32_t VLANTRANSMITTEDOK_P1;  /*!< (@ 0x00000CF4) Port 1 MAC Transmitted VLAN Tagged Frame Count
12390                                               *                  Register (n = 0 to 3)                                      */
12391 
12392         struct
12393         {
12394             __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
12395                                               *   with VLAN Tag Transmitted.                                                */
12396         } VLANTRANSMITTEDOK_P1_b;
12397     };
12398 
12399     union
12400     {
12401         __IM uint32_t FRAMESRETRANSMITTED_P1; /*!< (@ 0x00000CF8) Port 1 MAC Retransmitted Frame Count Register
12402                                                *                  (n = 0 to 3)                                               */
12403 
12404         struct
12405         {
12406             __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
12407                                                *   Frames that experienced a collision and were retransmitted.               */
12408         } FRAMESRETRANSMITTED_P1_b;
12409     };
12410     __IM uint32_t RESERVED38;
12411 
12412     union
12413     {
12414         __IM uint32_t STATS_HIWORD_P1;       /*!< (@ 0x00000D00) Port 1 MAC Statistics Counter High Word Register
12415                                               *                  (n = 0 to 3)                                               */
12416 
12417         struct
12418         {
12419             __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
12420                                               *   Counter Last Read                                                         */
12421         } STATS_HIWORD_P1_b;
12422     };
12423 
12424     union
12425     {
12426         __IOM uint32_t STATS_CTRL_P1;   /*!< (@ 0x00000D04) Port 1 MAC Statistics Control Register (n = 0
12427                                          *                  to 3)                                                      */
12428 
12429         struct
12430         {
12431             __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
12432             __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
12433             uint32_t               : 30;
12434         } STATS_CTRL_P1_b;
12435     };
12436 
12437     union
12438     {
12439         __IOM uint32_t STATS_CLEAR_VALUELO_P1;       /*!< (@ 0x00000D08) Port 1 MAC Statistics Clear Value Lower Register
12440                                                       *                  (n = 0 to 3)                                               */
12441 
12442         struct
12443         {
12444             __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
12445                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
12446                                                       *   command for test purposes. These bits should be set to
12447                                                       *   0 normally.                                                               */
12448         } STATS_CLEAR_VALUELO_P1_b;
12449     };
12450 
12451     union
12452     {
12453         __IOM uint32_t STATS_CLEAR_VALUEHI_P1;       /*!< (@ 0x00000D0C) Port 1 MAC Statistics Clear Value Higher Register
12454                                                       *                  (n = 0 to 3)                                               */
12455 
12456         struct
12457         {
12458             __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
12459                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
12460                                                       *   command for test purposes. These bits should be set to
12461                                                       *   0 normally.                                                               */
12462         } STATS_CLEAR_VALUEHI_P1_b;
12463     };
12464 
12465     union
12466     {
12467         __IM uint32_t ADEFERRED_P1;        /*!< (@ 0x00000D10) Port 1 MAC Deferred Count Register (n = 0 to
12468                                             *                  3)                                                         */
12469 
12470         struct
12471         {
12472             __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
12473                                             *   without collision but was deferred at begin.                              */
12474         } ADEFERRED_P1_b;
12475     };
12476 
12477     union
12478     {
12479         __IM uint32_t AMULTIPLECOLLISIONS_P1;   /*!< (@ 0x00000D14) Port 1 MAC Multiple Collision Count Register
12480                                                  *                  (n = 0 to 3)                                               */
12481 
12482         struct
12483         {
12484             __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
12485                                                  *   Transmit after multiple collisions.                                       */
12486         } AMULTIPLECOLLISIONS_P1_b;
12487     };
12488 
12489     union
12490     {
12491         __IM uint32_t ASINGLECOLLISIONS_P1;      /*!< (@ 0x00000D18) Port 1 MAC Single Collision Count Register (n
12492                                                   *                  = 0 to 3)                                                  */
12493 
12494         struct
12495         {
12496             __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
12497                                                   *   Transmit after single collision.                                          */
12498         } ASINGLECOLLISIONS_P1_b;
12499     };
12500 
12501     union
12502     {
12503         __IM uint32_t ALATECOLLISIONS_P1;     /*!< (@ 0x00000D1C) Port 1 MAC Late Collision Count Register (n =
12504                                                *                  0 to 3)                                                    */
12505 
12506         struct
12507         {
12508             __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
12509                                                *   Collision. Frame was aborted and not retransmitted.                       */
12510         } ALATECOLLISIONS_P1_b;
12511     };
12512 
12513     union
12514     {
12515         __IM uint32_t AEXCESSIVECOLLISIONS_P1; /*!< (@ 0x00000D20) Port 1 MAC Excessive Collision Count Register
12516                                                 *                  (n = 0 to 3)                                               */
12517 
12518         struct
12519         {
12520             __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
12521                                                 *   due to 16 consecutive collisions.                                         */
12522         } AEXCESSIVECOLLISIONS_P1_b;
12523     };
12524 
12525     union
12526     {
12527         __IM uint32_t ACARRIERSENSEERRORS_P1; /*!< (@ 0x00000D24) Port 1 MAC Carrier Sense Error Count Register
12528                                                *                  (n = 0 to 3)                                               */
12529 
12530         struct
12531         {
12532             __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
12533                                                *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
12534                                                *   asserted.                                                                 */
12535         } ACARRIERSENSEERRORS_P1_b;
12536     };
12537     __IM uint32_t RESERVED39[182];
12538 
12539     union
12540     {
12541         __IM uint32_t REV_P2;          /*!< (@ 0x00001000) Port 2 MAC Core Revision (n = 0 to 3)                      */
12542 
12543         struct
12544         {
12545             __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
12546         } REV_P2_b;
12547     };
12548     __IM uint32_t RESERVED40;
12549 
12550     union
12551     {
12552         __IOM uint32_t COMMAND_CONFIG_P2;       /*!< (@ 0x00001008) Port 2 Command Configuration Register (n = 0
12553                                                  *                  to 3)                                                      */
12554 
12555         struct
12556         {
12557             __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
12558             __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
12559             __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
12560                                                  *   the IMC until the current frame is completed. This can
12561                                                  *   cause the IPG between frames to be more than the value
12562                                                  *   in TX_IPG_LENGTH.                                                         */
12563             __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
12564             __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
12565             __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
12566             uint32_t                    : 1;
12567             __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
12568             __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
12569             __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
12570             __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
12571                                                  *   full-duplex only (set to 0).                                              */
12572             __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
12573             uint32_t                     : 1;
12574             __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
12575             uint32_t                     : 9;
12576             __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
12577             __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
12578             __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
12579                                                  *   register.                                                                 */
12580             __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
12581             __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
12582             uint32_t                   : 2;
12583             __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
12584                                                  *   on transmit and on receive. The value is used when not
12585                                                  *   overridden by the PTP auto-response function, pattern matchers
12586                                                  *   or force forwarding information in a management tag.                      */
12587             uint32_t : 1;
12588         } COMMAND_CONFIG_P2_b;
12589     };
12590 
12591     union
12592     {
12593         __IOM uint32_t MAC_ADDR_0_P2;     /*!< (@ 0x0000100C) Port 2 MAC Address Register 0 (n = 0 to 2)                 */
12594 
12595         struct
12596         {
12597             __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First
12598                                            *   byte is bits [7:0]. The MAC address is used on locally
12599                                            *   generated frames such as pause frames, peer-delay response.               */
12600         } MAC_ADDR_0_P2_b;
12601     };
12602 
12603     union
12604     {
12605         __IOM uint32_t MAC_ADDR_1_P2;     /*!< (@ 0x00001010) Port 2 MAC Address Register 1 (n = 0 to 2)                 */
12606 
12607         struct
12608         {
12609             __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits
12610                                            *   [7:0] is the 5th byte and bits [15:8] is the 6th byte.                    */
12611             uint32_t : 16;
12612         } MAC_ADDR_1_P2_b;
12613     };
12614 
12615     union
12616     {
12617         __IOM uint32_t FRM_LENGTH_P2;       /*!< (@ 0x00001014) Port 2 Maximum Frame Length Register (n = 0 to
12618                                              *                  3)                                                         */
12619 
12620         struct
12621         {
12622             __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
12623             uint32_t                  : 18;
12624         } FRM_LENGTH_P2_b;
12625     };
12626 
12627     union
12628     {
12629         __IM uint32_t PAUSE_QUANT_P2;       /*!< (@ 0x00001018) Port 2 MAC Pause Quanta (n = 0 to 3)                       */
12630 
12631         struct
12632         {
12633             __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
12634             uint32_t                  : 16;
12635         } PAUSE_QUANT_P2_b;
12636     };
12637 
12638     union
12639     {
12640         __IOM uint32_t MAC_LINK_QTRIG_P2;  /*!< (@ 0x0000101C) Port 2 Trigger Event Configuration Register (n
12641                                             *                  = 0 to 2)                                                  */
12642 
12643         struct
12644         {
12645             __IOM uint32_t PORT_MASK  : 4; /*!< [3..0] Per-port Bit Mask                                                  */
12646             uint32_t                  : 12;
12647             __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
12648                                             *   is transmitted from the ports indicated by PORT_MASK. A
12649                                             *   single frame is transmitted per indicated port in PORT_MASK
12650                                             *   among the queues indicated by QUEUE_MASK.                                 */
12651             uint32_t                 : 4;
12652             __IOM uint32_t TRIGGERED : 1;  /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether
12653                                             *   a frame was transmitted. When MODE is set to 0, TRIGGERED
12654                                             *   is always 0. This flag clears when the register is written.               */
12655             __IOM uint32_t DLR_MODE : 1;   /*!< [29..29] When set to 0, the DLR state machine is ignored. When
12656                                             *   set to 1, the Link Queue Trigger occurs only if the DLR
12657                                             *   state machine is in the NORMAL or FAULT state.                            */
12658             __IOM uint32_t MODE : 1;       /*!< [30..30] When set to 0, only a single Link_Status frame is generated.
12659                                             *   This is to prevent sending multiple frames due to link
12660                                             *   flapping.                                                                 */
12661             __IOM uint32_t ENABLE : 1;     /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature.
12662                                             *   When the link status (phy_link) transitions from 1 ->
12663                                             *   0, a trigger event is generated to the memory controller
12664                                             *   for the ports and queues indicated in PORT_MASK and QUEUE_MASK.           */
12665         } MAC_LINK_QTRIG_P2_b;
12666     };
12667     __IM uint32_t RESERVED41[4];
12668 
12669     union
12670     {
12671         __IOM uint32_t PTPCLOCKIDENTITY1_P2;  /*!< (@ 0x00001030) Port 2 PTP Clock Identity 1 Register (n = 0 to
12672                                                *                  2)                                                         */
12673 
12674         struct
12675         {
12676             __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0]                                  */
12677             __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1]                                 */
12678             __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2]                                */
12679             __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3]                                */
12680         } PTPCLOCKIDENTITY1_P2_b;
12681     };
12682 
12683     union
12684     {
12685         __IOM uint32_t PTPCLOCKIDENTITY2_P2;  /*!< (@ 0x00001034) Port 2 PTP Clock Identity 2 Register (n = 0 to
12686                                                *                  2)                                                         */
12687 
12688         struct
12689         {
12690             __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4]                                  */
12691             __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5]                                 */
12692             __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6]                                */
12693             __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7]                                */
12694         } PTPCLOCKIDENTITY2_P2_b;
12695     };
12696 
12697     union
12698     {
12699         __IOM uint32_t PTPAUTORESPONSE_P2; /*!< (@ 0x00001038) Port 2 PTP Auto Response Register (n = 0 to 2)             */
12700 
12701         struct
12702         {
12703             __IOM uint32_t ARSP_EN  : 1;   /*!< [0..0] Auto Response Enable                                               */
12704             __IOM uint32_t D_TIMER  : 1;   /*!< [1..1] Default timer to use for auto-response generation                  */
12705             uint32_t                : 14;
12706             __IOM uint32_t PORTNUM1 : 8;   /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb)                             */
12707             __IOM uint32_t PORTNUM0 : 8;   /*!< [31..24] 28, portIdentity.PortNumber[0] (msb)                             */
12708         } PTPAUTORESPONSE_P2_b;
12709     };
12710     __IM uint32_t RESERVED42;
12711 
12712     union
12713     {
12714         __IOM uint32_t STATUS_P2;          /*!< (@ 0x00001040) Port 2 Status Register                                     */
12715 
12716         struct
12717         {
12718             __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
12719             __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
12720             __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
12721             __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
12722                                             *   never occur during normal operation.                                      */
12723             __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
12724                                             *   to complete in time before the next frame was received
12725                                             *   at the port. This should never occur under normal operation.
12726                                             *   The cause could be from IPG violations in the received
12727                                             *   frames.                                                                   */
12728             __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
12729                                             *   to clause 30.14.1.2 of the 802.3br specification                          */
12730             uint32_t : 23;
12731         } STATUS_P2_b;
12732     };
12733 
12734     union
12735     {
12736         __IOM uint32_t TX_IPG_LENGTH_P2;      /*!< (@ 0x00001044) Port 2 Transmit IPG Length Register (n = 0 to
12737                                                *                  3)                                                         */
12738 
12739         struct
12740         {
12741             __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
12742                                                *   are in the range of 8 to 31.                                              */
12743             uint32_t                  : 11;
12744             __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
12745             uint32_t                  : 11;
12746         } TX_IPG_LENGTH_P2_b;
12747     };
12748 
12749     union
12750     {
12751         __IOM uint32_t EEE_CTL_STAT_P2;        /*!< (@ 0x00001048) Port 2 MAC EEE Functions Control and Status (n
12752                                                 *                  = 0 to 2)                                                  */
12753 
12754         struct
12755         {
12756             __IOM uint32_t EEE_AUTO     : 1;   /*!< [0..0] EEE Automatic Mode of Operation                                    */
12757             __IOM uint32_t LPI_REQ      : 1;   /*!< [1..1] Request LPI Transmission when MAC Becomes Idle                     */
12758             __IOM uint32_t LPI_TXHOLD   : 1;   /*!< [2..2] MAC Transmission Hold                                              */
12759             uint32_t                    : 5;
12760             __IM uint32_t ST_LPI_REQ    : 1;   /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC                  */
12761             __IM uint32_t ST_LPI_TXHOLD : 1;   /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC               */
12762             __IM uint32_t ST_TXBUSY     : 1;   /*!< [10..10] Status (real time) if the MAC is currently transmitting.         */
12763             __IM uint32_t ST_TXAVAIL    : 1;   /*!< [11..11] Status (real time) if the MAC transmit FIFO has data
12764                                                 *   available for transmission.                                               */
12765             __IM uint32_t ST_LPI_IND      : 1; /*!< [12..12] Status (real time) of Received LPI                               */
12766             uint32_t                      : 3;
12767             __IM uint32_t STLH_LPI_REQ    : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC             */
12768             __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the
12769                                                 *   MAC                                                                       */
12770             __IM uint32_t STLH_TXBUSY  : 1;    /*!< [18..18] Status (latched high) if the MAC is/was Transmitting             */
12771             uint32_t                   : 1;
12772             __IM uint32_t STLH_LPI_IND : 1;    /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND)               */
12773             uint32_t                   : 11;
12774         } EEE_CTL_STAT_P2_b;
12775     };
12776 
12777     union
12778     {
12779         __IOM uint32_t EEE_IDLE_TIME_P2;       /*!< (@ 0x0000104C) Port 2 EEE Idle Time Register (n = 0 to 2)                 */
12780 
12781         struct
12782         {
12783             __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission
12784                                                 *   of LPI begins. A 32-bit value in steps of 32 switch operating
12785                                                 *   clock cycles. A value of 0 disables the timer. The value
12786                                                 *   must be set to 1 less count.                                              */
12787         } EEE_IDLE_TIME_P2_b;
12788     };
12789 
12790     union
12791     {
12792         __IOM uint32_t EEE_TWSYS_TIME_P2;      /*!< (@ 0x00001050) Port 2 EEE Wake Up Time Register (n = 0 to 2)              */
12793 
12794         struct
12795         {
12796             __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed
12797                                                 *   to begin transmitting the first frame again. A 32-bit value
12798                                                 *   in steps of switch operating clock cycles. A value of 0
12799                                                 *   disables the timer. The value must be set to 1 less count.                */
12800         } EEE_TWSYS_TIME_P2_b;
12801     };
12802 
12803     union
12804     {
12805         __IOM uint32_t IDLE_SLOPE_P2;       /*!< (@ 0x00001054) Port 2 MAC Traffic Shaper Bandwidth Control                */
12806 
12807         struct
12808         {
12809             __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
12810             uint32_t                  : 21;
12811         } IDLE_SLOPE_P2_b;
12812     };
12813 
12814     union
12815     {
12816         __IOM uint32_t CT_DELAY_P2;      /*!< (@ 0x00001058) Port 2 Cut-Through Delay Indication Register               */
12817 
12818         struct
12819         {
12820             __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency
12821                                           *   of the MII PHY interface)                                                 */
12822             uint32_t : 23;
12823         } CT_DELAY_P2_b;
12824     };
12825 
12826     union
12827     {
12828         __IOM uint32_t BR_CONTROL_P2;            /*!< (@ 0x0000105C) Port 2 802.3br Frame Configuration Register                */
12829 
12830         struct
12831         {
12832             __IOM uint32_t PREEMPT_ENA : 1;      /*!< [0..0] When set to 1, enables 802.3br Frame Preemption.                   */
12833             __IOM uint32_t VERIFY_DIS  : 1;      /*!< [1..1] When set to 1, disables the verify process required for
12834                                                   *   preemption operation.                                                     */
12835             __IOM uint32_t RESPONSE_DIS : 1;     /*!< [2..2] When set to 1 prevents the MAC from responding to "verify"
12836                                                   *   frames.                                                                   */
12837             uint32_t                      : 1;
12838             __IOM uint32_t ADDFRAGSIZE    : 2;   /*!< [5..4] Minimum fragment size in increments of 64 bytes.                   */
12839             uint32_t                      : 2;
12840             __IOM uint32_t TX_VERIFY_TIME : 7;   /*!< [14..8] Preemption verification timeout in milliseconds.                  */
12841             uint32_t                      : 1;
12842             __IOM uint32_t RX_STRICT_PRE  : 1;   /*!< [16..16] When set to 1, the preamble is checked so all bytes
12843                                                   *   except the SFD are 0x55. When set to 0, only the last 2
12844                                                   *   bytes of the preamble are checked (SFD/SMD and FRAG_COUNT).
12845                                                   *   It is recommended to set this bit to 1 to comply with the
12846                                                   *   802.3br specification. This bit must be set to 0 if only
12847                                                   *   non-802.3br traffic is expected (for example, normal Ethernet
12848                                                   *   traffic) and if custom preamble is used.                                  */
12849             __IOM uint32_t RX_BR_SMD_DIS : 1;    /*!< [17..17] When set to 1, the receiver does not decode the 802.3br
12850                                                   *   SMDs and assumes all frames are express frames. This bit
12851                                                   *   must be set to 0 for correct operation with 802.3br, and
12852                                                   *   can be set to 1 when 802.3br is not enabled to avoid false
12853                                                   *   detection of SMDs.                                                        */
12854             __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE
12855                                                   *   frames is enabled. When set to 1, the frame contents and
12856                                                   *   frame length checks are also performed on these frames.
12857                                                   *   The mCRC is always checked regardless of the value of this
12858                                                   *   register. This bit must be set to 0 to be compliant with
12859                                                   *   the functionality described in IEEE 802.3br.                              */
12860             __IOM uint32_t TX_MCRC_INV : 1;      /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate
12861                                                   *   the mCRC for transmitted frames is inverted. This bit must
12862                                                   *   always be written to 0 and only used for debugging.                       */
12863             __IOM uint32_t RX_MCRC_INV : 1;      /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate
12864                                                   *   the mCRC for received frames is inverted. This bit must
12865                                                   *   always be written to 0 and only used for debugging.                       */
12866             uint32_t : 11;
12867         } BR_CONTROL_P2_b;
12868     };
12869     __IM uint32_t RESERVED43[2];
12870 
12871     union
12872     {
12873         __IM uint32_t AFRAMESTRANSMITTEDOK_P2; /*!< (@ 0x00001068) Port 2 MAC Transmitted Valid Frame Count Register
12874                                                 *                  (n = 0 to 3)                                               */
12875 
12876         struct
12877         {
12878             __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12879                                                 *   Transmitted, including pause.                                             */
12880         } AFRAMESTRANSMITTEDOK_P2_b;
12881     };
12882 
12883     union
12884     {
12885         __IM uint32_t AFRAMESRECEIVEDOK_P2;  /*!< (@ 0x0000106C) Port 2 MAC Received Valid Frame Count Register
12886                                               *                  (n = 0 to 3)                                               */
12887 
12888         struct
12889         {
12890             __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12891                                               *   Received, including pause.                                                */
12892         } AFRAMESRECEIVEDOK_P2_b;
12893     };
12894 
12895     union
12896     {
12897         __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P2; /*!< (@ 0x00001070) Port 2 MAC FCS Error Frame Count Register (n
12898                                                      *                  = 0 to 3)                                                  */
12899 
12900         struct
12901         {
12902             __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12903                                                      *   Length but CRC error.                                                     */
12904         } AFRAMECHECKSEQUENCEERRORS_P2_b;
12905     };
12906 
12907     union
12908     {
12909         __IM uint32_t AALIGNMENTERRORS_P2;   /*!< (@ 0x00001074) Port 2 MAC Alignment Error Frame Count Register
12910                                               *                  (n = 0 to 3)                                               */
12911 
12912         struct
12913         {
12914             __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
12915                                               *   of Nibbles (MII) Received.                                                */
12916         } AALIGNMENTERRORS_P2_b;
12917     };
12918 
12919     union
12920     {
12921         __IM uint32_t AOCTETSTRANSMITTEDOK_P2; /*!< (@ 0x00001078) Port 2 MAC Transmitted Valid Frame Octets Register
12922                                                 *                  (n = 0 to 3)                                               */
12923 
12924         struct
12925         {
12926             __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
12927                                                 *   only) of MAC Valid Transmitted.                                           */
12928         } AOCTETSTRANSMITTEDOK_P2_b;
12929     };
12930 
12931     union
12932     {
12933         __IM uint32_t AOCTETSRECEIVEDOK_P2;   /*!< (@ 0x0000107C) Port 2 MAC Received Valid Frame Octets Register
12934                                                *                  (n = 0 to 3)                                               */
12935 
12936         struct
12937         {
12938             __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
12939                                                *   only) of MAC Valid Received.                                              */
12940         } AOCTETSRECEIVEDOK_P2_b;
12941     };
12942 
12943     union
12944     {
12945         __IM uint32_t ATXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001080) Port 2 MAC Transmitted Pause Frame Count Register
12946                                                  *                  (n = 0 to 3)                                               */
12947 
12948         struct
12949         {
12950             __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12951                                                  *   Pause Transmitted.                                                        */
12952         } ATXPAUSEMACCTRLFRAMES_P2_b;
12953     };
12954 
12955     union
12956     {
12957         __IM uint32_t ARXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001084) Port 2 MAC Received Pause Frame Count Register
12958                                                  *                  (n = 0 to 3)                                               */
12959 
12960         struct
12961         {
12962             __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
12963                                                  *   Pause Received.                                                           */
12964         } ARXPAUSEMACCTRLFRAMES_P2_b;
12965     };
12966 
12967     union
12968     {
12969         __IM uint32_t IFINERRORS_P2;       /*!< (@ 0x00001088) Port 2 MAC Input Error Count Register (n = 0
12970                                             *                  to 3)                                                      */
12971 
12972         struct
12973         {
12974             __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
12975                                             *   During Reception such as CRC, Length, PHY Error, RX FIFO
12976                                             *   Overflow.                                                                 */
12977         } IFINERRORS_P2_b;
12978     };
12979 
12980     union
12981     {
12982         __IM uint32_t IFOUTERRORS_P2;       /*!< (@ 0x0000108C) Port 2 MAC Output Error Count Register (n = 0
12983                                              *                  to 3)                                                      */
12984 
12985         struct
12986         {
12987             __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
12988                                              *   Transmitted with PHY error.                                               */
12989         } IFOUTERRORS_P2_b;
12990     };
12991 
12992     union
12993     {
12994         __IM uint32_t IFINUCASTPKTS_P2;      /*!< (@ 0x00001090) Port 2 MAC Received Unicast Frame Count Register
12995                                               *                  (n = 0 to 3)                                               */
12996 
12997         struct
12998         {
12999             __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
13000                                               *   Frame Valid Received.                                                     */
13001         } IFINUCASTPKTS_P2_b;
13002     };
13003 
13004     union
13005     {
13006         __IM uint32_t IFINMULTICASTPKTS_P2;  /*!< (@ 0x00001094) Port 2 MAC Received Multicast Frame Count Register
13007                                               *                  (n = 0 to 3)                                               */
13008 
13009         struct
13010         {
13011             __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
13012                                               *   Frame Valid Received.                                                     */
13013         } IFINMULTICASTPKTS_P2_b;
13014     };
13015 
13016     union
13017     {
13018         __IM uint32_t IFINBROADCASTPKTS_P2;  /*!< (@ 0x00001098) Port 2 MAC Received Broadcast Frame Count Register
13019                                               *                  (n = 0 to 3)                                               */
13020 
13021         struct
13022         {
13023             __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
13024                                               *   Frame Valid Received.                                                     */
13025         } IFINBROADCASTPKTS_P2_b;
13026     };
13027 
13028     union
13029     {
13030         __IM uint32_t IFOUTDISCARDS_P2;     /*!< (@ 0x0000109C) Port 2 MAC Discarded Outbound Frame Count Register
13031                                              *                  (n = 0 to 3)                                               */
13032 
13033         struct
13034         {
13035             __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
13036         } IFOUTDISCARDS_P2_b;
13037     };
13038 
13039     union
13040     {
13041         __IM uint32_t IFOUTUCASTPKTS_P2;     /*!< (@ 0x000010A0) Port 2 MAC Transmitted Unicast Frame Count Register
13042                                               *                  (n = 0 to 3)                                               */
13043 
13044         struct
13045         {
13046             __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
13047                                               *   Frame Valid Transmitted.                                                  */
13048         } IFOUTUCASTPKTS_P2_b;
13049     };
13050 
13051     union
13052     {
13053         __IM uint32_t IFOUTMULTICASTPKTS_P2; /*!< (@ 0x000010A4) Port 2 MAC Transmitted Multicast Frame Count
13054                                               *                  Register (n = 0 to 3)                                      */
13055 
13056         struct
13057         {
13058             __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
13059                                               *   Frame Valid Transmitted.                                                  */
13060         } IFOUTMULTICASTPKTS_P2_b;
13061     };
13062 
13063     union
13064     {
13065         __IM uint32_t IFOUTBROADCASTPKTS_P2; /*!< (@ 0x000010A8) Port 2 MAC Transmitted Broadcast Frame Count
13066                                               *                  Register (n = 0 to 3)                                      */
13067 
13068         struct
13069         {
13070             __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
13071                                               *   Frame Valid Transmitted.                                                  */
13072         } IFOUTBROADCASTPKTS_P2_b;
13073     };
13074 
13075     union
13076     {
13077         __IM uint32_t ETHERSTATSDROPEVENTS_P2; /*!< (@ 0x000010AC) Port 2 MAC Dropped Frame Count Register (n =
13078                                                 *                  0 to 3)                                                    */
13079 
13080         struct
13081         {
13082             __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
13083                                                 *   Full at frame start.                                                      */
13084         } ETHERSTATSDROPEVENTS_P2_b;
13085     };
13086 
13087     union
13088     {
13089         __IM uint32_t ETHERSTATSOCTETS_P2; /*!< (@ 0x000010B0) Port 2 MAC All Frame Octets Register (n = 0 to
13090                                             *                  3)                                                         */
13091 
13092         struct
13093         {
13094             __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
13095         } ETHERSTATSOCTETS_P2_b;
13096     };
13097 
13098     union
13099     {
13100         __IM uint32_t ETHERSTATSPKTS_P2; /*!< (@ 0x000010B4) Port 2 MAC All Frame Count Register (n = 0 to
13101                                           *                  3)                                                         */
13102 
13103         struct
13104         {
13105             __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
13106         } ETHERSTATSPKTS_P2_b;
13107     };
13108 
13109     union
13110     {
13111         __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P2; /*!< (@ 0x000010B8) Port 2 MAC Too Short Frame Count Register (n
13112                                                    *                  = 0 to 3)                                                  */
13113 
13114         struct
13115         {
13116             __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
13117                                                    *   Good CRC.                                                                 */
13118         } ETHERSTATSUNDERSIZEPKTS_P2_b;
13119     };
13120 
13121     union
13122     {
13123         __IM uint32_t ETHERSTATSOVERSIZEPKTS_P2; /*!< (@ 0x000010BC) Port 2 MAC Too Long Frame Count Register (n =
13124                                                   *                  0 to 3)                                                    */
13125 
13126         struct
13127         {
13128             __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
13129                                                   *   Good CRC.                                                                 */
13130         } ETHERSTATSOVERSIZEPKTS_P2_b;
13131     };
13132 
13133     union
13134     {
13135         __IM uint32_t ETHERSTATSPKTS64OCTETS_P2; /*!< (@ 0x000010C0) Port 2 MAC 64 Octets Frame Count Register (n
13136                                                   *                  = 0 to 3)                                                  */
13137 
13138         struct
13139         {
13140             __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13141                                                   *   Good and Bad (Packet Size: 64 bytes).                                     */
13142         } ETHERSTATSPKTS64OCTETS_P2_b;
13143     };
13144 
13145     union
13146     {
13147         __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P2; /*!< (@ 0x000010C4) Port 2 MAC 65 to 127 Octets Frame Count Register
13148                                                        *                (n = 0 to 3)                                               */
13149 
13150         struct
13151         {
13152             __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13153                                                        *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
13154         } ETHERSTATSPKTS65TO127OCTETS_P2_b;
13155     };
13156 
13157     union
13158     {
13159         __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P2; /*!< (@ 0x000010C8) Port 2 MAC 128 to 255 Octets Frame Count Register
13160                                                         *               (n = 0 to 3)                                               */
13161 
13162         struct
13163         {
13164             __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13165                                                         *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
13166         } ETHERSTATSPKTS128TO255OCTETS_P2_b;
13167     };
13168 
13169     union
13170     {
13171         __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P2; /*!< (@ 0x000010CC) Port 2 MAC 256 to 511 Octets Frame Count Register
13172                                                         *               (n = 0 to 3)                                               */
13173 
13174         struct
13175         {
13176             __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13177                                                         *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
13178         } ETHERSTATSPKTS256TO511OCTETS_P2_b;
13179     };
13180 
13181     union
13182     {
13183         __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P2; /*!< (@ 0x000010D0) Port 2 MAC 512 to 1023 Octets Frame Count Register
13184                                                          *              (n = 0 to 3)                                               */
13185 
13186         struct
13187         {
13188             __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13189                                                          *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
13190         } ETHERSTATSPKTS512TO1023OCTETS_P2_b;
13191     };
13192 
13193     union
13194     {
13195         __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P2; /*!< (@ 0x000010D4) Port 2 MAC 1024 to 1518 Octets Frame Count Register
13196                                                           *             (n = 0 to 3)                                               */
13197 
13198         struct
13199         {
13200             __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13201                                                           *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
13202         } ETHERSTATSPKTS1024TO1518OCTETS_P2_b;
13203     };
13204 
13205     union
13206     {
13207         __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P2; /*!< (@ 0x000010D8) Port 2 MAC Over 1519 Octets Frame Count Register
13208                                                        *                (n = 0 to 3)                                               */
13209 
13210         struct
13211         {
13212             __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
13213                                                        *   Good and Bad (Packet Size: over 1519 bytes).                              */
13214         } ETHERSTATSPKTS1519TOXOCTETS_P2_b;
13215     };
13216 
13217     union
13218     {
13219         __IM uint32_t ETHERSTATSJABBERS_P2; /*!< (@ 0x000010DC) Port 2 MAC Jabbers Frame Count Register (n =
13220                                              *                  0 to 3)                                                    */
13221 
13222         struct
13223         {
13224             __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
13225                                              *   Bad CRC.                                                                  */
13226         } ETHERSTATSJABBERS_P2_b;
13227     };
13228 
13229     union
13230     {
13231         __IM uint32_t ETHERSTATSFRAGMENTS_P2; /*!< (@ 0x000010E0) Port 2 MAC Fragment Frame Count Register (n =
13232                                                *                  0 to 3)                                                    */
13233 
13234         struct
13235         {
13236             __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
13237                                                *   Bad CRC.                                                                  */
13238         } ETHERSTATSFRAGMENTS_P2_b;
13239     };
13240     __IM uint32_t RESERVED44;
13241 
13242     union
13243     {
13244         __IM uint32_t VLANRECEIVEDOK_P2;     /*!< (@ 0x000010E8) Port 2 MAC Received VLAN Tagged Frame Count Register
13245                                               *                  (n = 0 to 3)                                               */
13246 
13247         struct
13248         {
13249             __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
13250                                               *   with VLAN Tag Received.                                                   */
13251         } VLANRECEIVEDOK_P2_b;
13252     };
13253     __IM uint32_t RESERVED45[2];
13254 
13255     union
13256     {
13257         __IM uint32_t VLANTRANSMITTEDOK_P2;  /*!< (@ 0x000010F4) Port 2 MAC Transmitted VLAN Tagged Frame Count
13258                                               *                  Register (n = 0 to 3)                                      */
13259 
13260         struct
13261         {
13262             __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
13263                                               *   with VLAN Tag Transmitted.                                                */
13264         } VLANTRANSMITTEDOK_P2_b;
13265     };
13266 
13267     union
13268     {
13269         __IM uint32_t FRAMESRETRANSMITTED_P2; /*!< (@ 0x000010F8) Port 2 MAC Retransmitted Frame Count Register
13270                                                *                  (n = 0 to 3)                                               */
13271 
13272         struct
13273         {
13274             __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
13275                                                *   Frames that experienced a collision and were retransmitted.               */
13276         } FRAMESRETRANSMITTED_P2_b;
13277     };
13278     __IM uint32_t RESERVED46;
13279 
13280     union
13281     {
13282         __IM uint32_t STATS_HIWORD_P2;       /*!< (@ 0x00001100) Port 2 MAC Statistics Counter High Word Register
13283                                               *                  (n = 0 to 3)                                               */
13284 
13285         struct
13286         {
13287             __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
13288                                               *   Counter Last Read                                                         */
13289         } STATS_HIWORD_P2_b;
13290     };
13291 
13292     union
13293     {
13294         __IOM uint32_t STATS_CTRL_P2;   /*!< (@ 0x00001104) Port 2 MAC Statistics Control Register (n = 0
13295                                          *                  to 3)                                                      */
13296 
13297         struct
13298         {
13299             __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
13300             __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
13301             uint32_t               : 30;
13302         } STATS_CTRL_P2_b;
13303     };
13304 
13305     union
13306     {
13307         __IOM uint32_t STATS_CLEAR_VALUELO_P2;       /*!< (@ 0x00001108) Port 2 MAC Statistics Clear Value Lower Register
13308                                                       *                  (n = 0 to 3)                                               */
13309 
13310         struct
13311         {
13312             __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
13313                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
13314                                                       *   command for test purposes. These bits should be set to
13315                                                       *   0 normally.                                                               */
13316         } STATS_CLEAR_VALUELO_P2_b;
13317     };
13318 
13319     union
13320     {
13321         __IOM uint32_t STATS_CLEAR_VALUEHI_P2;       /*!< (@ 0x0000110C) Port 2 MAC Statistics Clear Value Higher Register
13322                                                       *                  (n = 0 to 3)                                               */
13323 
13324         struct
13325         {
13326             __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
13327                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
13328                                                       *   command for test purposes. These bits should be set to
13329                                                       *   0 normally.                                                               */
13330         } STATS_CLEAR_VALUEHI_P2_b;
13331     };
13332 
13333     union
13334     {
13335         __IM uint32_t ADEFERRED_P2;        /*!< (@ 0x00001110) Port 2 MAC Deferred Count Register (n = 0 to
13336                                             *                  3)                                                         */
13337 
13338         struct
13339         {
13340             __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
13341                                             *   without collision but was deferred at begin.                              */
13342         } ADEFERRED_P2_b;
13343     };
13344 
13345     union
13346     {
13347         __IM uint32_t AMULTIPLECOLLISIONS_P2;   /*!< (@ 0x00001114) Port 2 MAC Multiple Collision Count Register
13348                                                  *                  (n = 0 to 3)                                               */
13349 
13350         struct
13351         {
13352             __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
13353                                                  *   Transmit after multiple collisions.                                       */
13354         } AMULTIPLECOLLISIONS_P2_b;
13355     };
13356 
13357     union
13358     {
13359         __IM uint32_t ASINGLECOLLISIONS_P2;      /*!< (@ 0x00001118) Port 2 MAC Single Collision Count Register (n
13360                                                   *                  = 0 to 3)                                                  */
13361 
13362         struct
13363         {
13364             __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
13365                                                   *   Transmit after single collision.                                          */
13366         } ASINGLECOLLISIONS_P2_b;
13367     };
13368 
13369     union
13370     {
13371         __IM uint32_t ALATECOLLISIONS_P2;     /*!< (@ 0x0000111C) Port 2 MAC Late Collision Count Register (n =
13372                                                *                  0 to 3)                                                    */
13373 
13374         struct
13375         {
13376             __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
13377                                                *   Collision. Frame was aborted and not retransmitted.                       */
13378         } ALATECOLLISIONS_P2_b;
13379     };
13380 
13381     union
13382     {
13383         __IM uint32_t AEXCESSIVECOLLISIONS_P2; /*!< (@ 0x00001120) Port 2 MAC Excessive Collision Count Register
13384                                                 *                  (n = 0 to 3)                                               */
13385 
13386         struct
13387         {
13388             __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
13389                                                 *   due to 16 consecutive collisions.                                         */
13390         } AEXCESSIVECOLLISIONS_P2_b;
13391     };
13392 
13393     union
13394     {
13395         __IM uint32_t ACARRIERSENSEERRORS_P2; /*!< (@ 0x00001124) Port 2 MAC Carrier Sense Error Count Register
13396                                                *                  (n = 0 to 3)                                               */
13397 
13398         struct
13399         {
13400             __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
13401                                                *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
13402                                                *   asserted.                                                                 */
13403         } ACARRIERSENSEERRORS_P2_b;
13404     };
13405     __IM uint32_t RESERVED47[182];
13406 
13407     union
13408     {
13409         __IM uint32_t REV_P3;          /*!< (@ 0x00001400) Port 3 MAC Core Revision (n = 0 to 3)                      */
13410 
13411         struct
13412         {
13413             __IM uint32_t REV : 32;    /*!< [31..0] MAC Core Revision                                                 */
13414         } REV_P3_b;
13415     };
13416     __IM uint32_t RESERVED48;
13417 
13418     union
13419     {
13420         __IOM uint32_t COMMAND_CONFIG_P3;       /*!< (@ 0x00001408) Port 3 Command Configuration Register (n = 0
13421                                                  *                  to 3)                                                      */
13422 
13423         struct
13424         {
13425             __IOM uint32_t TX_ENA          : 1; /*!< [0..0] Enable/Disable MAC Transmit Path                                   */
13426             __IOM uint32_t RX_ENA          : 1; /*!< [1..1] Enable/Disable MAC Receive Path                                    */
13427             __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from
13428                                                  *   the IMC until the current frame is completed. This can
13429                                                  *   cause the IPG between frames to be more than the value
13430                                                  *   in TX_IPG_LENGTH.                                                         */
13431             __IOM uint32_t ETH_SPEED    : 1;    /*!< [3..3] Operation Mode Definition                                          */
13432             __IM uint32_t  PROMIS_EN    : 1;    /*!< [4..4] Enable/Disable MAC Promiscuous Operation                           */
13433             __IM uint32_t  PAD_EN       : 1;    /*!< [5..5] Enable/Disable Frame Padding Remove on Receive                     */
13434             uint32_t                    : 1;
13435             __IM uint32_t  PAUSE_FWD    : 1;    /*!< [7..7] Terminate/Forward Pause Frames                                     */
13436             __IOM uint32_t PAUSE_IGNORE : 1;    /*!< [8..8] Ignore Pause Frame Quanta                                          */
13437             __IM uint32_t  TX_ADDR_INS  : 1;    /*!< [9..9] Non writable bit, fixed to 0 always.                               */
13438             __IOM uint32_t HD_ENA       : 1;    /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or
13439                                                  *   full-duplex only (set to 0).                                              */
13440             __IOM uint32_t TX_CRC_APPEND : 1;   /*!< [11..11] Enable CRC Append on Transmit                                    */
13441             uint32_t                     : 1;
13442             __IOM uint32_t SW_RESET      : 1;   /*!< [13..13] Self Clearing Reset Command Bit                                  */
13443             uint32_t                     : 9;
13444             __IOM uint32_t CNTL_FRM_ENA  : 1;   /*!< [23..23] MAC Control Frame Enable                                         */
13445             __IOM uint32_t NO_LGTH_CHK   : 1;   /*!< [24..24] Payload Length Check Disable                                     */
13446             __IOM uint32_t ENA_10        : 1;   /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn
13447                                                  *   register.                                                                 */
13448             __IOM uint32_t EFPI_SELECT : 1;     /*!< [26..26] EFPI_SELECT                                                      */
13449             __IOM uint32_t TX_TRUNCATE : 1;     /*!< [27..27] TX_TRUNCATE                                                      */
13450             uint32_t                   : 2;
13451             __IOM uint32_t TIMER_SEL   : 1;     /*!< [30..30] Selects the default timer to use for timestamping operations
13452                                                  *   on transmit and on receive. The value is used when not
13453                                                  *   overridden by the PTP auto-response function, pattern matchers
13454                                                  *   or force forwarding information in a management tag.                      */
13455             uint32_t : 1;
13456         } COMMAND_CONFIG_P3_b;
13457     };
13458     __IM uint32_t RESERVED49[2];
13459 
13460     union
13461     {
13462         __IOM uint32_t FRM_LENGTH_P3;       /*!< (@ 0x00001414) Port 3 Maximum Frame Length Register (n = 0 to
13463                                              *                  3)                                                         */
13464 
13465         struct
13466         {
13467             __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length                                              */
13468             uint32_t                  : 18;
13469         } FRM_LENGTH_P3_b;
13470     };
13471 
13472     union
13473     {
13474         __IM uint32_t PAUSE_QUANT_P3;       /*!< (@ 0x00001418) Port 3 MAC Pause Quanta (n = 0 to 3)                       */
13475 
13476         struct
13477         {
13478             __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta                                                      */
13479             uint32_t                  : 16;
13480         } PAUSE_QUANT_P3_b;
13481     };
13482     __IM uint32_t RESERVED50[9];
13483 
13484     union
13485     {
13486         __IOM uint32_t STATUS_P3;          /*!< (@ 0x00001440) Port 3 Status Register                                     */
13487 
13488         struct
13489         {
13490             __IM uint32_t  PHYSPEED  : 2;  /*!< [1..0] Currently Active PHY Interface Speed                               */
13491             __IM uint32_t  PHYLINK   : 1;  /*!< [2..2] Link status from PHY interface                                     */
13492             __IM uint32_t  PHYDUPLEX : 1;  /*!< [3..3] Duplex status from PHY interface                                   */
13493             __IOM uint32_t TX_UNDFLW : 1;  /*!< [4..4] Indicates that the transmit MAC underflow. This shall
13494                                             *   never occur during normal operation.                                      */
13495             __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed
13496                                             *   to complete in time before the next frame was received
13497                                             *   at the port. This should never occur under normal operation.
13498                                             *   The cause could be from IPG violations in the received
13499                                             *   frames.                                                                   */
13500             __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according
13501                                             *   to clause 30.14.1.2 of the 802.3br specification                          */
13502             uint32_t : 23;
13503         } STATUS_P3_b;
13504     };
13505 
13506     union
13507     {
13508         __IOM uint32_t TX_IPG_LENGTH_P3;      /*!< (@ 0x00001444) Port 3 Transmit IPG Length Register (n = 0 to
13509                                                *                  3)                                                         */
13510 
13511         struct
13512         {
13513             __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values
13514                                                *   are in the range of 8 to 31.                                              */
13515             uint32_t                  : 11;
13516             __IOM uint32_t MINRTC3GAP : 5;    /*!< [20..16] MINRTC3GAP                                                       */
13517             uint32_t                  : 11;
13518         } TX_IPG_LENGTH_P3_b;
13519     };
13520     __IM uint32_t RESERVED51[3];
13521 
13522     union
13523     {
13524         __IOM uint32_t IDLE_SLOPE_P3;       /*!< (@ 0x00001454) Port 3 MAC Traffic Shaper Bandwidth Control                */
13525 
13526         struct
13527         {
13528             __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control                                  */
13529             uint32_t                  : 21;
13530         } IDLE_SLOPE_P3_b;
13531     };
13532     __IM uint32_t RESERVED52[4];
13533 
13534     union
13535     {
13536         __IM uint32_t AFRAMESTRANSMITTEDOK_P3; /*!< (@ 0x00001468) Port 3 MAC Transmitted Valid Frame Count Register
13537                                                 *                  (n = 0 to 3)                                               */
13538 
13539         struct
13540         {
13541             __IM uint32_t TXVALIDCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of MAC Valid
13542                                                 *   Transmitted, including pause.                                             */
13543         } AFRAMESTRANSMITTEDOK_P3_b;
13544     };
13545 
13546     union
13547     {
13548         __IM uint32_t AFRAMESRECEIVEDOK_P3;  /*!< (@ 0x0000146C) Port 3 MAC Received Valid Frame Count Register
13549                                               *                  (n = 0 to 3)                                               */
13550 
13551         struct
13552         {
13553             __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid
13554                                               *   Received, including pause.                                                */
13555         } AFRAMESRECEIVEDOK_P3_b;
13556     };
13557 
13558     union
13559     {
13560         __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P3; /*!< (@ 0x00001470) Port 3 MAC FCS Error Frame Count Register (n
13561                                                      *                  = 0 to 3)                                                  */
13562 
13563         struct
13564         {
13565             __IM uint32_t FCSERRCOUNT : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC Valid
13566                                                      *   Length but CRC error.                                                     */
13567         } AFRAMECHECKSEQUENCEERRORS_P3_b;
13568     };
13569 
13570     union
13571     {
13572         __IM uint32_t AALIGNMENTERRORS_P3;   /*!< (@ 0x00001474) Port 3 MAC Alignment Error Frame Count Register
13573                                               *                  (n = 0 to 3)                                               */
13574 
13575         struct
13576         {
13577             __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number
13578                                               *   of Nibbles (MII) Received.                                                */
13579         } AALIGNMENTERRORS_P3_b;
13580     };
13581 
13582     union
13583     {
13584         __IM uint32_t AOCTETSTRANSMITTEDOK_P3; /*!< (@ 0x00001478) Port 3 MAC Transmitted Valid Frame Octets Register
13585                                                 *                  (n = 0 to 3)                                               */
13586 
13587         struct
13588         {
13589             __IM uint32_t TXVALIDOCTETS : 32;  /*!< [31..0] PORT n, this field indicates the octets (the payload
13590                                                 *   only) of MAC Valid Transmitted.                                           */
13591         } AOCTETSTRANSMITTEDOK_P3_b;
13592     };
13593 
13594     union
13595     {
13596         __IM uint32_t AOCTETSRECEIVEDOK_P3;   /*!< (@ 0x0000147C) Port 3 MAC Received Valid Frame Octets Register
13597                                                *                  (n = 0 to 3)                                               */
13598 
13599         struct
13600         {
13601             __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload
13602                                                *   only) of MAC Valid Received.                                              */
13603         } AOCTETSRECEIVEDOK_P3_b;
13604     };
13605 
13606     union
13607     {
13608         __IM uint32_t ATXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001480) Port 3 MAC Transmitted Pause Frame Count Register
13609                                                  *                  (n = 0 to 3)                                               */
13610 
13611         struct
13612         {
13613             __IM uint32_t TXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
13614                                                  *   Pause Transmitted.                                                        */
13615         } ATXPAUSEMACCTRLFRAMES_P3_b;
13616     };
13617 
13618     union
13619     {
13620         __IM uint32_t ARXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001484) Port 3 MAC Received Pause Frame Count Register
13621                                                  *                  (n = 0 to 3)                                               */
13622 
13623         struct
13624         {
13625             __IM uint32_t RXPAUSECOUNT : 32;    /*!< [31..0] PORT n, this field indicates the number of MAC Valid
13626                                                  *   Pause Received.                                                           */
13627         } ARXPAUSEMACCTRLFRAMES_P3_b;
13628     };
13629 
13630     union
13631     {
13632         __IM uint32_t IFINERRORS_P3;       /*!< (@ 0x00001488) Port 3 MAC Input Error Count Register (n = 0
13633                                             *                  to 3)                                                      */
13634 
13635         struct
13636         {
13637             __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error
13638                                             *   During Reception such as CRC, Length, PHY Error, RX FIFO
13639                                             *   Overflow.                                                                 */
13640         } IFINERRORS_P3_b;
13641     };
13642 
13643     union
13644     {
13645         __IM uint32_t IFOUTERRORS_P3;       /*!< (@ 0x0000148C) Port 3 MAC Output Error Count Register (n = 0
13646                                              *                  to 3)                                                      */
13647 
13648         struct
13649         {
13650             __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame
13651                                              *   Transmitted with PHY error.                                               */
13652         } IFOUTERRORS_P3_b;
13653     };
13654 
13655     union
13656     {
13657         __IM uint32_t IFINUCASTPKTS_P3;      /*!< (@ 0x00001490) Port 3 MAC Received Unicast Frame Count Register
13658                                               *                  (n = 0 to 3)                                               */
13659 
13660         struct
13661         {
13662             __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
13663                                               *   Frame Valid Received.                                                     */
13664         } IFINUCASTPKTS_P3_b;
13665     };
13666 
13667     union
13668     {
13669         __IM uint32_t IFINMULTICASTPKTS_P3;  /*!< (@ 0x00001494) Port 3 MAC Received Multicast Frame Count Register
13670                                               *                  (n = 0 to 3)                                               */
13671 
13672         struct
13673         {
13674             __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
13675                                               *   Frame Valid Received.                                                     */
13676         } IFINMULTICASTPKTS_P3_b;
13677     };
13678 
13679     union
13680     {
13681         __IM uint32_t IFINBROADCASTPKTS_P3;  /*!< (@ 0x00001498) Port 3 MAC Received Broadcast Frame Count Register
13682                                               *                  (n = 0 to 3)                                               */
13683 
13684         struct
13685         {
13686             __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
13687                                               *   Frame Valid Received.                                                     */
13688         } IFINBROADCASTPKTS_P3_b;
13689     };
13690 
13691     union
13692     {
13693         __IM uint32_t IFOUTDISCARDS_P3;     /*!< (@ 0x0000149C) Port 3 MAC Discarded Outbound Frame Count Register
13694                                              *                  (n = 0 to 3)                                               */
13695 
13696         struct
13697         {
13698             __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable                                                    */
13699         } IFOUTDISCARDS_P3_b;
13700     };
13701 
13702     union
13703     {
13704         __IM uint32_t IFOUTUCASTPKTS_P3;     /*!< (@ 0x000014A0) Port 3 MAC Transmitted Unicast Frame Count Register
13705                                               *                  (n = 0 to 3)                                               */
13706 
13707         struct
13708         {
13709             __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast
13710                                               *   Frame Valid Transmitted.                                                  */
13711         } IFOUTUCASTPKTS_P3_b;
13712     };
13713 
13714     union
13715     {
13716         __IM uint32_t IFOUTMULTICASTPKTS_P3; /*!< (@ 0x000014A4) Port 3 MAC Transmitted Multicast Frame Count
13717                                               *                  Register (n = 0 to 3)                                      */
13718 
13719         struct
13720         {
13721             __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast
13722                                               *   Frame Valid Transmitted.                                                  */
13723         } IFOUTMULTICASTPKTS_P3_b;
13724     };
13725 
13726     union
13727     {
13728         __IM uint32_t IFOUTBROADCASTPKTS_P3; /*!< (@ 0x000014A8) Port 3 MAC Transmitted Broadcast Frame Count
13729                                               *                  Register (n = 0 to 3)                                      */
13730 
13731         struct
13732         {
13733             __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast
13734                                               *   Frame Valid Transmitted.                                                  */
13735         } IFOUTBROADCASTPKTS_P3_b;
13736     };
13737 
13738     union
13739     {
13740         __IM uint32_t ETHERSTATSDROPEVENTS_P3; /*!< (@ 0x000014AC) Port 3 MAC Dropped Frame Count Register (n =
13741                                                 *                  0 to 3)                                                    */
13742 
13743         struct
13744         {
13745             __IM uint32_t DROPCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO
13746                                                 *   Full at frame start.                                                      */
13747         } ETHERSTATSDROPEVENTS_P3_b;
13748     };
13749 
13750     union
13751     {
13752         __IM uint32_t ETHERSTATSOCTETS_P3; /*!< (@ 0x000014B0) Port 3 MAC All Frame Octets Register (n = 0 to
13753                                             *                  3)                                                         */
13754 
13755         struct
13756         {
13757             __IM uint32_t ALLOCTETS : 32;  /*!< [31..0] ALLOCTETS                                                         */
13758         } ETHERSTATSOCTETS_P3_b;
13759     };
13760 
13761     union
13762     {
13763         __IM uint32_t ETHERSTATSPKTS_P3; /*!< (@ 0x000014B4) Port 3 MAC All Frame Count Register (n = 0 to
13764                                           *                  3)                                                         */
13765 
13766         struct
13767         {
13768             __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT                                                          */
13769         } ETHERSTATSPKTS_P3_b;
13770     };
13771 
13772     union
13773     {
13774         __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P3; /*!< (@ 0x000014B8) Port 3 MAC Too Short Frame Count Register (n
13775                                                    *                  = 0 to 3)                                                  */
13776 
13777         struct
13778         {
13779             __IM uint32_t TOOSHRTCOUNT : 32;      /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
13780                                                    *   Good CRC.                                                                 */
13781         } ETHERSTATSUNDERSIZEPKTS_P3_b;
13782     };
13783 
13784     union
13785     {
13786         __IM uint32_t ETHERSTATSOVERSIZEPKTS_P3; /*!< (@ 0x000014BC) Port 3 MAC Too Long Frame Count Register (n =
13787                                                   *                  0 to 3)                                                    */
13788 
13789         struct
13790         {
13791             __IM uint32_t TOOLONGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
13792                                                   *   Good CRC.                                                                 */
13793         } ETHERSTATSOVERSIZEPKTS_P3_b;
13794     };
13795 
13796     union
13797     {
13798         __IM uint32_t ETHERSTATSPKTS64OCTETS_P3; /*!< (@ 0x000014C0) Port 3 MAC 64 Octets Frame Count Register (n
13799                                                   *                  = 0 to 3)                                                  */
13800 
13801         struct
13802         {
13803             __IM uint32_t OCTCNT64 : 32;         /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13804                                                   *   Good and Bad (Packet Size: 64 bytes).                                     */
13805         } ETHERSTATSPKTS64OCTETS_P3_b;
13806     };
13807 
13808     union
13809     {
13810         __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P3; /*!< (@ 0x000014C4) Port 3 MAC 65 to 127 Octets Frame Count Register
13811                                                        *                (n = 0 to 3)                                               */
13812 
13813         struct
13814         {
13815             __IM uint32_t OCTCNT65T127 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13816                                                        *   Good and Bad (Packet Size: 65 to 127 bytes).                              */
13817         } ETHERSTATSPKTS65TO127OCTETS_P3_b;
13818     };
13819 
13820     union
13821     {
13822         __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P3; /*!< (@ 0x000014C8) Port 3 MAC 128 to 255 Octets Frame Count Register
13823                                                         *               (n = 0 to 3)                                               */
13824 
13825         struct
13826         {
13827             __IM uint32_t OCTCNT128T255 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13828                                                         *   Good and Bad (Packet Size: 128 to 255 bytes).                             */
13829         } ETHERSTATSPKTS128TO255OCTETS_P3_b;
13830     };
13831 
13832     union
13833     {
13834         __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P3; /*!< (@ 0x000014CC) Port 3 MAC 256 to 511 Octets Frame Count Register
13835                                                         *               (n = 0 to 3)                                               */
13836 
13837         struct
13838         {
13839             __IM uint32_t OCTCNT256T511 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13840                                                         *   Good and Bad (Packet Size: 256 to 511 bytes).                             */
13841         } ETHERSTATSPKTS256TO511OCTETS_P3_b;
13842     };
13843 
13844     union
13845     {
13846         __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P3; /*!< (@ 0x000014D0) Port 3 MAC 512 to 1023 Octets Frame Count Register
13847                                                          *              (n = 0 to 3)                                               */
13848 
13849         struct
13850         {
13851             __IM uint32_t OCTCNT512T1023 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13852                                                          *   Good and Bad (Packet Size: 512 to 1023 bytes).                            */
13853         } ETHERSTATSPKTS512TO1023OCTETS_P3_b;
13854     };
13855 
13856     union
13857     {
13858         __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P3; /*!< (@ 0x000014D4) Port 3 MAC 1024 to 1518 Octets Frame Count Register
13859                                                           *             (n = 0 to 3)                                               */
13860 
13861         struct
13862         {
13863             __IM uint32_t OCTCNT1024T1518 : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC All Frames,
13864                                                           *   Good and Bad (Packet Size: 1024 to 1518 bytes).                           */
13865         } ETHERSTATSPKTS1024TO1518OCTETS_P3_b;
13866     };
13867 
13868     union
13869     {
13870         __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P3; /*!< (@ 0x000014D8) Port 3 MAC Over 1519 Octets Frame Count Register
13871                                                        *                (n = 0 to 3)                                               */
13872 
13873         struct
13874         {
13875             __IM uint32_t OCTCNT1519TX : 32;          /*!< [31..0] PORT n, this field indicates the number of MAC all Frames,
13876                                                        *   Good and Bad (Packet Size: over 1519 bytes).                              */
13877         } ETHERSTATSPKTS1519TOXOCTETS_P3_b;
13878     };
13879 
13880     union
13881     {
13882         __IM uint32_t ETHERSTATSJABBERS_P3; /*!< (@ 0x000014DC) Port 3 MAC Jabbers Frame Count Register (n =
13883                                              *                  0 to 3)                                                    */
13884 
13885         struct
13886         {
13887             __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long,
13888                                              *   Bad CRC.                                                                  */
13889         } ETHERSTATSJABBERS_P3_b;
13890     };
13891 
13892     union
13893     {
13894         __IM uint32_t ETHERSTATSFRAGMENTS_P3; /*!< (@ 0x000014E0) Port 3 MAC Fragment Frame Count Register (n =
13895                                                *                  0 to 3)                                                    */
13896 
13897         struct
13898         {
13899             __IM uint32_t FRAGCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of MAC too Short,
13900                                                *   Bad CRC.                                                                  */
13901         } ETHERSTATSFRAGMENTS_P3_b;
13902     };
13903     __IM uint32_t RESERVED53;
13904 
13905     union
13906     {
13907         __IM uint32_t VLANRECEIVEDOK_P3;     /*!< (@ 0x000014E8) Port 3 MAC Received VLAN Tagged Frame Count Register
13908                                               *                  (n = 0 to 3)                                               */
13909 
13910         struct
13911         {
13912             __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
13913                                               *   with VLAN Tag Received.                                                   */
13914         } VLANRECEIVEDOK_P3_b;
13915     };
13916     __IM uint32_t RESERVED54[2];
13917 
13918     union
13919     {
13920         __IM uint32_t VLANTRANSMITTEDOK_P3;  /*!< (@ 0x000014F4) Port 3 MAC Transmitted VLAN Tagged Frame Count
13921                                               *                  Register (n = 0 to 3)                                      */
13922 
13923         struct
13924         {
13925             __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames
13926                                               *   with VLAN Tag Transmitted.                                                */
13927         } VLANTRANSMITTEDOK_P3_b;
13928     };
13929 
13930     union
13931     {
13932         __IM uint32_t FRAMESRETRANSMITTED_P3; /*!< (@ 0x000014F8) Port 3 MAC Retransmitted Frame Count Register
13933                                                *                  (n = 0 to 3)                                               */
13934 
13935         struct
13936         {
13937             __IM uint32_t RETXCOUNT : 32;     /*!< [31..0] PORT n, this field indicates the number of Transmitted
13938                                                *   Frames that experienced a collision and were retransmitted.               */
13939         } FRAMESRETRANSMITTED_P3_b;
13940     };
13941     __IM uint32_t RESERVED55;
13942 
13943     union
13944     {
13945         __IM uint32_t STATS_HIWORD_P3;       /*!< (@ 0x00001500) Port 3 MAC Statistics Counter High Word Register
13946                                               *                  (n = 0 to 3)                                               */
13947 
13948         struct
13949         {
13950             __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics
13951                                               *   Counter Last Read                                                         */
13952         } STATS_HIWORD_P3_b;
13953     };
13954 
13955     union
13956     {
13957         __IOM uint32_t STATS_CTRL_P3;   /*!< (@ 0x00001504) Port 3 MAC Statistics Control Register (n = 0
13958                                          *                  to 3)                                                      */
13959 
13960         struct
13961         {
13962             __IOM uint32_t CLRALL  : 1; /*!< [0..0] Self Clearing Counter Initialize Command                           */
13963             __IM uint32_t  CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication                                       */
13964             uint32_t               : 30;
13965         } STATS_CTRL_P3_b;
13966     };
13967 
13968     union
13969     {
13970         __IOM uint32_t STATS_CLEAR_VALUELO_P3;       /*!< (@ 0x00001508) Port 3 MAC Statistics Clear Value Lower Register
13971                                                       *                  (n = 0 to 3)                                               */
13972 
13973         struct
13974         {
13975             __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all
13976                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
13977                                                       *   command for test purposes. These bits should be set to
13978                                                       *   0 normally.                                                               */
13979         } STATS_CLEAR_VALUELO_P3_b;
13980     };
13981 
13982     union
13983     {
13984         __IOM uint32_t STATS_CLEAR_VALUEHI_P3;       /*!< (@ 0x0000150C) Port 3 MAC Statistics Clear Value Higher Register
13985                                                       *                  (n = 0 to 3)                                               */
13986 
13987         struct
13988         {
13989             __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all
13990                                                       *   counters when clearing all counters with STATS_CTRL_Pn.CLRALL
13991                                                       *   command for test purposes. These bits should be set to
13992                                                       *   0 normally.                                                               */
13993         } STATS_CLEAR_VALUEHI_P3_b;
13994     };
13995 
13996     union
13997     {
13998         __IM uint32_t ADEFERRED_P3;        /*!< (@ 0x00001510) Port 3 MAC Deferred Count Register (n = 0 to
13999                                             *                  3)                                                         */
14000 
14001         struct
14002         {
14003             __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted
14004                                             *   without collision but was deferred at begin.                              */
14005         } ADEFERRED_P3_b;
14006     };
14007 
14008     union
14009     {
14010         __IM uint32_t AMULTIPLECOLLISIONS_P3;   /*!< (@ 0x00001514) Port 3 MAC Multiple Collision Count Register
14011                                                  *                  (n = 0 to 3)                                               */
14012 
14013         struct
14014         {
14015             __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
14016                                                  *   Transmit after multiple collisions.                                       */
14017         } AMULTIPLECOLLISIONS_P3_b;
14018     };
14019 
14020     union
14021     {
14022         __IM uint32_t ASINGLECOLLISIONS_P3;      /*!< (@ 0x00001518) Port 3 MAC Single Collision Count Register (n
14023                                                   *                  = 0 to 3)                                                  */
14024 
14025         struct
14026         {
14027             __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame
14028                                                   *   Transmit after single collision.                                          */
14029         } ASINGLECOLLISIONS_P3_b;
14030     };
14031 
14032     union
14033     {
14034         __IM uint32_t ALATECOLLISIONS_P3;     /*!< (@ 0x0000151C) Port 3 MAC Late Collision Count Register (n =
14035                                                *                  0 to 3)                                                    */
14036 
14037         struct
14038         {
14039             __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late
14040                                                *   Collision. Frame was aborted and not retransmitted.                       */
14041         } ALATECOLLISIONS_P3_b;
14042     };
14043 
14044     union
14045     {
14046         __IM uint32_t AEXCESSIVECOLLISIONS_P3; /*!< (@ 0x00001520) Port 3 MAC Excessive Collision Count Register
14047                                                 *                  (n = 0 to 3)                                               */
14048 
14049         struct
14050         {
14051             __IM uint32_t EXCCOLLCOUNT : 32;   /*!< [31..0] PORT n, this field indicates the number of Frames Discarded
14052                                                 *   due to 16 consecutive collisions.                                         */
14053         } AEXCESSIVECOLLISIONS_P3_b;
14054     };
14055 
14056     union
14057     {
14058         __IM uint32_t ACARRIERSENSEERRORS_P3; /*!< (@ 0x00001524) Port 3 MAC Carrier Sense Error Count Register
14059                                                *                  (n = 0 to 3)                                               */
14060 
14061         struct
14062         {
14063             __IM uint32_t CSERRCOUNT : 32;    /*!< [31..0] PORT n, increments during Transmission without Collisions
14064                                                *   the PHY Carrier Sense Signal (RX_CRS) dropped or never
14065                                                *   asserted.                                                                 */
14066         } ACARRIERSENSEERRORS_P3_b;
14067     };
14068     __IM uint32_t RESERVED56[694];
14069 
14070     union
14071     {
14072         __IOM uint32_t P0_QSTMACU0;    /*!< (@ 0x00002000) Qci Stream Filter Table MAC Address Upper Part             */
14073 
14074         struct
14075         {
14076             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14077             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14078             uint32_t            : 15;
14079         } P0_QSTMACU0_b;
14080     };
14081 
14082     union
14083     {
14084         __IOM uint32_t P0_QSTMACD0;    /*!< (@ 0x00002004) Qci Stream Filter Table MAC Address Downer Part            */
14085 
14086         struct
14087         {
14088             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14089         } P0_QSTMACD0_b;
14090     };
14091 
14092     union
14093     {
14094         __IOM uint32_t P0_QSTMAMU0;    /*!< (@ 0x00002008) Qci Stream Filter Table MAC Address Mask Upper
14095                                         *                  Part                                                       */
14096 
14097         struct
14098         {
14099             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14100             uint32_t             : 16;
14101         } P0_QSTMAMU0_b;
14102     };
14103 
14104     union
14105     {
14106         __IOM uint32_t P0_QSTMAMD0;    /*!< (@ 0x0000200C) Qci Stream Filter Table MAC Address Mask Downer
14107                                         *                  Part                                                       */
14108 
14109         struct
14110         {
14111             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14112         } P0_QSTMAMD0_b;
14113     };
14114 
14115     union
14116     {
14117         __IOM uint32_t P0_QSFTVL0;      /*!< (@ 0x00002010) Qci Stream Filter Table VLAN                               */
14118 
14119         struct
14120         {
14121             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
14122             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
14123             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
14124             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
14125             uint32_t              : 14;
14126         } P0_QSFTVL0_b;
14127     };
14128 
14129     union
14130     {
14131         __IOM uint32_t P0_QSFTVLM0;      /*!< (@ 0x00002014) Qci Stream Filter Table VLAN Mask                          */
14132 
14133         struct
14134         {
14135             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
14136             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
14137             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
14138             uint32_t               : 16;
14139         } P0_QSFTVLM0_b;
14140     };
14141 
14142     union
14143     {
14144         __IOM uint32_t P0_QSFTBL0;     /*!< (@ 0x00002018) Qci Stream Filter Table SDU/Gate/Meter ID                  */
14145 
14146         struct
14147         {
14148             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
14149             uint32_t             : 3;
14150             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
14151             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
14152             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
14153             uint32_t             : 1;
14154             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
14155             uint32_t             : 3;
14156             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
14157             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
14158             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
14159             uint32_t             : 3;
14160         } P0_QSFTBL0_b;
14161     };
14162 
14163     union
14164     {
14165         __IM uint32_t P0_QSMFC0;       /*!< (@ 0x0000201C) Qci Stream Match Packet Count                              */
14166 
14167         struct
14168         {
14169             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
14170             uint32_t            : 16;
14171         } P0_QSMFC0_b;
14172     };
14173 
14174     union
14175     {
14176         __IM uint32_t P0_QMSPPC0;      /*!< (@ 0x00002020) Qci MSDU Passed Packet Count                               */
14177 
14178         struct
14179         {
14180             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
14181             uint32_t             : 16;
14182         } P0_QMSPPC0_b;
14183     };
14184 
14185     union
14186     {
14187         __IM uint32_t P0_QMSRPC0;      /*!< (@ 0x00002024) Qci MSDU Reject Packet Count                               */
14188 
14189         struct
14190         {
14191             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
14192             uint32_t             : 16;
14193         } P0_QMSRPC0_b;
14194     };
14195 
14196     union
14197     {
14198         __IOM uint32_t P0_QSTMACU1;    /*!< (@ 0x00002028) Qci Stream Filter Table MAC Address Upper Part             */
14199 
14200         struct
14201         {
14202             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14203             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14204             uint32_t            : 15;
14205         } P0_QSTMACU1_b;
14206     };
14207 
14208     union
14209     {
14210         __IOM uint32_t P0_QSTMACD1;    /*!< (@ 0x0000202C) Qci Stream Filter Table MAC Address Downer Part            */
14211 
14212         struct
14213         {
14214             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14215         } P0_QSTMACD1_b;
14216     };
14217 
14218     union
14219     {
14220         __IOM uint32_t P0_QSTMAMU1;    /*!< (@ 0x00002030) Qci Stream Filter Table MAC Address Mask Upper
14221                                         *                  Part                                                       */
14222 
14223         struct
14224         {
14225             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14226             uint32_t             : 16;
14227         } P0_QSTMAMU1_b;
14228     };
14229 
14230     union
14231     {
14232         __IOM uint32_t P0_QSTMAMD1;    /*!< (@ 0x00002034) Qci Stream Filter Table MAC Address Mask Downer
14233                                         *                  Part                                                       */
14234 
14235         struct
14236         {
14237             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14238         } P0_QSTMAMD1_b;
14239     };
14240 
14241     union
14242     {
14243         __IOM uint32_t P0_QSFTVL1;      /*!< (@ 0x00002038) Qci Stream Filter Table VLAN                               */
14244 
14245         struct
14246         {
14247             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
14248             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
14249             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
14250             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
14251             uint32_t              : 14;
14252         } P0_QSFTVL1_b;
14253     };
14254 
14255     union
14256     {
14257         __IOM uint32_t P0_QSFTVLM1;      /*!< (@ 0x0000203C) Qci Stream Filter Table VLAN Mask                          */
14258 
14259         struct
14260         {
14261             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
14262             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
14263             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
14264             uint32_t               : 16;
14265         } P0_QSFTVLM1_b;
14266     };
14267 
14268     union
14269     {
14270         __IOM uint32_t P0_QSFTBL1;     /*!< (@ 0x00002040) Qci Stream Filter Table SDU/Gate/Meter ID                  */
14271 
14272         struct
14273         {
14274             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
14275             uint32_t             : 3;
14276             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
14277             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
14278             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
14279             uint32_t             : 1;
14280             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
14281             uint32_t             : 3;
14282             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
14283             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
14284             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
14285             uint32_t             : 3;
14286         } P0_QSFTBL1_b;
14287     };
14288 
14289     union
14290     {
14291         __IM uint32_t P0_QSMFC1;       /*!< (@ 0x00002044) Qci Stream Match Packet Count                              */
14292 
14293         struct
14294         {
14295             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
14296             uint32_t            : 16;
14297         } P0_QSMFC1_b;
14298     };
14299 
14300     union
14301     {
14302         __IM uint32_t P0_QMSPPC1;      /*!< (@ 0x00002048) Qci MSDU Passed Packet Count                               */
14303 
14304         struct
14305         {
14306             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
14307             uint32_t             : 16;
14308         } P0_QMSPPC1_b;
14309     };
14310 
14311     union
14312     {
14313         __IM uint32_t P0_QMSRPC1;      /*!< (@ 0x0000204C) Qci MSDU Reject Packet Count                               */
14314 
14315         struct
14316         {
14317             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
14318             uint32_t             : 16;
14319         } P0_QMSRPC1_b;
14320     };
14321 
14322     union
14323     {
14324         __IOM uint32_t P0_QSTMACU2;    /*!< (@ 0x00002050) Qci Stream Filter Table MAC Address Upper Part             */
14325 
14326         struct
14327         {
14328             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14329             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14330             uint32_t            : 15;
14331         } P0_QSTMACU2_b;
14332     };
14333 
14334     union
14335     {
14336         __IOM uint32_t P0_QSTMACD2;    /*!< (@ 0x00002054) Qci Stream Filter Table MAC Address Downer Part            */
14337 
14338         struct
14339         {
14340             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14341         } P0_QSTMACD2_b;
14342     };
14343 
14344     union
14345     {
14346         __IOM uint32_t P0_QSTMAMU2;    /*!< (@ 0x00002058) Qci Stream Filter Table MAC Address Mask Upper
14347                                         *                  Part                                                       */
14348 
14349         struct
14350         {
14351             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14352             uint32_t             : 16;
14353         } P0_QSTMAMU2_b;
14354     };
14355 
14356     union
14357     {
14358         __IOM uint32_t P0_QSTMAMD2;    /*!< (@ 0x0000205C) Qci Stream Filter Table MAC Address Mask Downer
14359                                         *                  Part                                                       */
14360 
14361         struct
14362         {
14363             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14364         } P0_QSTMAMD2_b;
14365     };
14366 
14367     union
14368     {
14369         __IOM uint32_t P0_QSFTVL2;      /*!< (@ 0x00002060) Qci Stream Filter Table VLAN                               */
14370 
14371         struct
14372         {
14373             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
14374             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
14375             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
14376             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
14377             uint32_t              : 14;
14378         } P0_QSFTVL2_b;
14379     };
14380 
14381     union
14382     {
14383         __IOM uint32_t P0_QSFTVLM2;      /*!< (@ 0x00002064) Qci Stream Filter Table VLAN Mask                          */
14384 
14385         struct
14386         {
14387             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
14388             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
14389             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
14390             uint32_t               : 16;
14391         } P0_QSFTVLM2_b;
14392     };
14393 
14394     union
14395     {
14396         __IOM uint32_t P0_QSFTBL2;     /*!< (@ 0x00002068) Qci Stream Filter Table SDU/Gate/Meter ID                  */
14397 
14398         struct
14399         {
14400             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
14401             uint32_t             : 3;
14402             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
14403             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
14404             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
14405             uint32_t             : 1;
14406             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
14407             uint32_t             : 3;
14408             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
14409             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
14410             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
14411             uint32_t             : 3;
14412         } P0_QSFTBL2_b;
14413     };
14414 
14415     union
14416     {
14417         __IM uint32_t P0_QSMFC2;       /*!< (@ 0x0000206C) Qci Stream Match Packet Count                              */
14418 
14419         struct
14420         {
14421             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
14422             uint32_t            : 16;
14423         } P0_QSMFC2_b;
14424     };
14425 
14426     union
14427     {
14428         __IM uint32_t P0_QMSPPC2;      /*!< (@ 0x00002070) Qci MSDU Passed Packet Count                               */
14429 
14430         struct
14431         {
14432             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
14433             uint32_t             : 16;
14434         } P0_QMSPPC2_b;
14435     };
14436 
14437     union
14438     {
14439         __IM uint32_t P0_QMSRPC2;      /*!< (@ 0x00002074) Qci MSDU Reject Packet Count                               */
14440 
14441         struct
14442         {
14443             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
14444             uint32_t             : 16;
14445         } P0_QMSRPC2_b;
14446     };
14447 
14448     union
14449     {
14450         __IOM uint32_t P0_QSTMACU3;    /*!< (@ 0x00002078) Qci Stream Filter Table MAC Address Upper Part             */
14451 
14452         struct
14453         {
14454             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14455             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14456             uint32_t            : 15;
14457         } P0_QSTMACU3_b;
14458     };
14459 
14460     union
14461     {
14462         __IOM uint32_t P0_QSTMACD3;    /*!< (@ 0x0000207C) Qci Stream Filter Table MAC Address Downer Part            */
14463 
14464         struct
14465         {
14466             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14467         } P0_QSTMACD3_b;
14468     };
14469 
14470     union
14471     {
14472         __IOM uint32_t P0_QSTMAMU3;    /*!< (@ 0x00002080) Qci Stream Filter Table MAC Address Mask Upper
14473                                         *                  Part                                                       */
14474 
14475         struct
14476         {
14477             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14478             uint32_t             : 16;
14479         } P0_QSTMAMU3_b;
14480     };
14481 
14482     union
14483     {
14484         __IOM uint32_t P0_QSTMAMD3;    /*!< (@ 0x00002084) Qci Stream Filter Table MAC Address Mask Downer
14485                                         *                  Part                                                       */
14486 
14487         struct
14488         {
14489             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14490         } P0_QSTMAMD3_b;
14491     };
14492 
14493     union
14494     {
14495         __IOM uint32_t P0_QSFTVL3;      /*!< (@ 0x00002088) Qci Stream Filter Table VLAN                               */
14496 
14497         struct
14498         {
14499             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
14500             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
14501             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
14502             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
14503             uint32_t              : 14;
14504         } P0_QSFTVL3_b;
14505     };
14506 
14507     union
14508     {
14509         __IOM uint32_t P0_QSFTVLM3;      /*!< (@ 0x0000208C) Qci Stream Filter Table VLAN Mask                          */
14510 
14511         struct
14512         {
14513             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
14514             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
14515             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
14516             uint32_t               : 16;
14517         } P0_QSFTVLM3_b;
14518     };
14519 
14520     union
14521     {
14522         __IOM uint32_t P0_QSFTBL3;     /*!< (@ 0x00002090) Qci Stream Filter Table SDU/Gate/Meter ID                  */
14523 
14524         struct
14525         {
14526             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
14527             uint32_t             : 3;
14528             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
14529             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
14530             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
14531             uint32_t             : 1;
14532             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
14533             uint32_t             : 3;
14534             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
14535             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
14536             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
14537             uint32_t             : 3;
14538         } P0_QSFTBL3_b;
14539     };
14540 
14541     union
14542     {
14543         __IM uint32_t P0_QSMFC3;       /*!< (@ 0x00002094) Qci Stream Match Packet Count                              */
14544 
14545         struct
14546         {
14547             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
14548             uint32_t            : 16;
14549         } P0_QSMFC3_b;
14550     };
14551 
14552     union
14553     {
14554         __IM uint32_t P0_QMSPPC3;      /*!< (@ 0x00002098) Qci MSDU Passed Packet Count                               */
14555 
14556         struct
14557         {
14558             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
14559             uint32_t             : 16;
14560         } P0_QMSPPC3_b;
14561     };
14562 
14563     union
14564     {
14565         __IM uint32_t P0_QMSRPC3;      /*!< (@ 0x0000209C) Qci MSDU Reject Packet Count                               */
14566 
14567         struct
14568         {
14569             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
14570             uint32_t             : 16;
14571         } P0_QMSRPC3_b;
14572     };
14573 
14574     union
14575     {
14576         __IOM uint32_t P0_QSTMACU4;    /*!< (@ 0x000020A0) Qci Stream Filter Table MAC Address Upper Part             */
14577 
14578         struct
14579         {
14580             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14581             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14582             uint32_t            : 15;
14583         } P0_QSTMACU4_b;
14584     };
14585 
14586     union
14587     {
14588         __IOM uint32_t P0_QSTMACD4;    /*!< (@ 0x000020A4) Qci Stream Filter Table MAC Address Downer Part            */
14589 
14590         struct
14591         {
14592             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14593         } P0_QSTMACD4_b;
14594     };
14595 
14596     union
14597     {
14598         __IOM uint32_t P0_QSTMAMU4;    /*!< (@ 0x000020A8) Qci Stream Filter Table MAC Address Mask Upper
14599                                         *                  Part                                                       */
14600 
14601         struct
14602         {
14603             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14604             uint32_t             : 16;
14605         } P0_QSTMAMU4_b;
14606     };
14607 
14608     union
14609     {
14610         __IOM uint32_t P0_QSTMAMD4;    /*!< (@ 0x000020AC) Qci Stream Filter Table MAC Address Mask Downer
14611                                         *                  Part                                                       */
14612 
14613         struct
14614         {
14615             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14616         } P0_QSTMAMD4_b;
14617     };
14618 
14619     union
14620     {
14621         __IOM uint32_t P0_QSFTVL4;      /*!< (@ 0x000020B0) Qci Stream Filter Table VLAN                               */
14622 
14623         struct
14624         {
14625             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
14626             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
14627             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
14628             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
14629             uint32_t              : 14;
14630         } P0_QSFTVL4_b;
14631     };
14632 
14633     union
14634     {
14635         __IOM uint32_t P0_QSFTVLM4;      /*!< (@ 0x000020B4) Qci Stream Filter Table VLAN Mask                          */
14636 
14637         struct
14638         {
14639             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
14640             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
14641             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
14642             uint32_t               : 16;
14643         } P0_QSFTVLM4_b;
14644     };
14645 
14646     union
14647     {
14648         __IOM uint32_t P0_QSFTBL4;     /*!< (@ 0x000020B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
14649 
14650         struct
14651         {
14652             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
14653             uint32_t             : 3;
14654             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
14655             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
14656             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
14657             uint32_t             : 1;
14658             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
14659             uint32_t             : 3;
14660             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
14661             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
14662             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
14663             uint32_t             : 3;
14664         } P0_QSFTBL4_b;
14665     };
14666 
14667     union
14668     {
14669         __IM uint32_t P0_QSMFC4;       /*!< (@ 0x000020BC) Qci Stream Match Packet Count                              */
14670 
14671         struct
14672         {
14673             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
14674             uint32_t            : 16;
14675         } P0_QSMFC4_b;
14676     };
14677 
14678     union
14679     {
14680         __IM uint32_t P0_QMSPPC4;      /*!< (@ 0x000020C0) Qci MSDU Passed Packet Count                               */
14681 
14682         struct
14683         {
14684             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
14685             uint32_t             : 16;
14686         } P0_QMSPPC4_b;
14687     };
14688 
14689     union
14690     {
14691         __IM uint32_t P0_QMSRPC4;      /*!< (@ 0x000020C4) Qci MSDU Reject Packet Count                               */
14692 
14693         struct
14694         {
14695             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
14696             uint32_t             : 16;
14697         } P0_QMSRPC4_b;
14698     };
14699 
14700     union
14701     {
14702         __IOM uint32_t P0_QSTMACU5;    /*!< (@ 0x000020C8) Qci Stream Filter Table MAC Address Upper Part             */
14703 
14704         struct
14705         {
14706             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14707             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14708             uint32_t            : 15;
14709         } P0_QSTMACU5_b;
14710     };
14711 
14712     union
14713     {
14714         __IOM uint32_t P0_QSTMACD5;    /*!< (@ 0x000020CC) Qci Stream Filter Table MAC Address Downer Part            */
14715 
14716         struct
14717         {
14718             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14719         } P0_QSTMACD5_b;
14720     };
14721 
14722     union
14723     {
14724         __IOM uint32_t P0_QSTMAMU5;    /*!< (@ 0x000020D0) Qci Stream Filter Table MAC Address Mask Upper
14725                                         *                  Part                                                       */
14726 
14727         struct
14728         {
14729             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14730             uint32_t             : 16;
14731         } P0_QSTMAMU5_b;
14732     };
14733 
14734     union
14735     {
14736         __IOM uint32_t P0_QSTMAMD5;    /*!< (@ 0x000020D4) Qci Stream Filter Table MAC Address Mask Downer
14737                                         *                  Part                                                       */
14738 
14739         struct
14740         {
14741             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14742         } P0_QSTMAMD5_b;
14743     };
14744 
14745     union
14746     {
14747         __IOM uint32_t P0_QSFTVL5;      /*!< (@ 0x000020D8) Qci Stream Filter Table VLAN                               */
14748 
14749         struct
14750         {
14751             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
14752             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
14753             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
14754             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
14755             uint32_t              : 14;
14756         } P0_QSFTVL5_b;
14757     };
14758 
14759     union
14760     {
14761         __IOM uint32_t P0_QSFTVLM5;      /*!< (@ 0x000020DC) Qci Stream Filter Table VLAN Mask                          */
14762 
14763         struct
14764         {
14765             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
14766             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
14767             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
14768             uint32_t               : 16;
14769         } P0_QSFTVLM5_b;
14770     };
14771 
14772     union
14773     {
14774         __IOM uint32_t P0_QSFTBL5;     /*!< (@ 0x000020E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
14775 
14776         struct
14777         {
14778             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
14779             uint32_t             : 3;
14780             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
14781             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
14782             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
14783             uint32_t             : 1;
14784             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
14785             uint32_t             : 3;
14786             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
14787             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
14788             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
14789             uint32_t             : 3;
14790         } P0_QSFTBL5_b;
14791     };
14792 
14793     union
14794     {
14795         __IM uint32_t P0_QSMFC5;       /*!< (@ 0x000020E4) Qci Stream Match Packet Count                              */
14796 
14797         struct
14798         {
14799             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
14800             uint32_t            : 16;
14801         } P0_QSMFC5_b;
14802     };
14803 
14804     union
14805     {
14806         __IM uint32_t P0_QMSPPC5;      /*!< (@ 0x000020E8) Qci MSDU Passed Packet Count                               */
14807 
14808         struct
14809         {
14810             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
14811             uint32_t             : 16;
14812         } P0_QMSPPC5_b;
14813     };
14814 
14815     union
14816     {
14817         __IM uint32_t P0_QMSRPC5;      /*!< (@ 0x000020EC) Qci MSDU Reject Packet Count                               */
14818 
14819         struct
14820         {
14821             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
14822             uint32_t             : 16;
14823         } P0_QMSRPC5_b;
14824     };
14825 
14826     union
14827     {
14828         __IOM uint32_t P0_QSTMACU6;    /*!< (@ 0x000020F0) Qci Stream Filter Table MAC Address Upper Part             */
14829 
14830         struct
14831         {
14832             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14833             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14834             uint32_t            : 15;
14835         } P0_QSTMACU6_b;
14836     };
14837 
14838     union
14839     {
14840         __IOM uint32_t P0_QSTMACD6;    /*!< (@ 0x000020F4) Qci Stream Filter Table MAC Address Downer Part            */
14841 
14842         struct
14843         {
14844             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14845         } P0_QSTMACD6_b;
14846     };
14847 
14848     union
14849     {
14850         __IOM uint32_t P0_QSTMAMU6;    /*!< (@ 0x000020F8) Qci Stream Filter Table MAC Address Mask Upper
14851                                         *                  Part                                                       */
14852 
14853         struct
14854         {
14855             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14856             uint32_t             : 16;
14857         } P0_QSTMAMU6_b;
14858     };
14859 
14860     union
14861     {
14862         __IOM uint32_t P0_QSTMAMD6;    /*!< (@ 0x000020FC) Qci Stream Filter Table MAC Address Mask Downer
14863                                         *                  Part                                                       */
14864 
14865         struct
14866         {
14867             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14868         } P0_QSTMAMD6_b;
14869     };
14870 
14871     union
14872     {
14873         __IOM uint32_t P0_QSFTVL6;      /*!< (@ 0x00002100) Qci Stream Filter Table VLAN                               */
14874 
14875         struct
14876         {
14877             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
14878             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
14879             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
14880             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
14881             uint32_t              : 14;
14882         } P0_QSFTVL6_b;
14883     };
14884 
14885     union
14886     {
14887         __IOM uint32_t P0_QSFTVLM6;      /*!< (@ 0x00002104) Qci Stream Filter Table VLAN Mask                          */
14888 
14889         struct
14890         {
14891             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
14892             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
14893             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
14894             uint32_t               : 16;
14895         } P0_QSFTVLM6_b;
14896     };
14897 
14898     union
14899     {
14900         __IOM uint32_t P0_QSFTBL6;     /*!< (@ 0x00002108) Qci Stream Filter Table SDU/Gate/Meter ID                  */
14901 
14902         struct
14903         {
14904             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
14905             uint32_t             : 3;
14906             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
14907             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
14908             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
14909             uint32_t             : 1;
14910             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
14911             uint32_t             : 3;
14912             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
14913             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
14914             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
14915             uint32_t             : 3;
14916         } P0_QSFTBL6_b;
14917     };
14918 
14919     union
14920     {
14921         __IM uint32_t P0_QSMFC6;       /*!< (@ 0x0000210C) Qci Stream Match Packet Count                              */
14922 
14923         struct
14924         {
14925             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
14926             uint32_t            : 16;
14927         } P0_QSMFC6_b;
14928     };
14929 
14930     union
14931     {
14932         __IM uint32_t P0_QMSPPC6;      /*!< (@ 0x00002110) Qci MSDU Passed Packet Count                               */
14933 
14934         struct
14935         {
14936             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
14937             uint32_t             : 16;
14938         } P0_QMSPPC6_b;
14939     };
14940 
14941     union
14942     {
14943         __IM uint32_t P0_QMSRPC6;      /*!< (@ 0x00002114) Qci MSDU Reject Packet Count                               */
14944 
14945         struct
14946         {
14947             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
14948             uint32_t             : 16;
14949         } P0_QMSRPC6_b;
14950     };
14951 
14952     union
14953     {
14954         __IOM uint32_t P0_QSTMACU7;    /*!< (@ 0x00002118) Qci Stream Filter Table MAC Address Upper Part             */
14955 
14956         struct
14957         {
14958             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
14959             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
14960             uint32_t            : 15;
14961         } P0_QSTMACU7_b;
14962     };
14963 
14964     union
14965     {
14966         __IOM uint32_t P0_QSTMACD7;    /*!< (@ 0x0000211C) Qci Stream Filter Table MAC Address Downer Part            */
14967 
14968         struct
14969         {
14970             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
14971         } P0_QSTMACD7_b;
14972     };
14973 
14974     union
14975     {
14976         __IOM uint32_t P0_QSTMAMU7;    /*!< (@ 0x00002120) Qci Stream Filter Table MAC Address Mask Upper
14977                                         *                  Part                                                       */
14978 
14979         struct
14980         {
14981             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
14982             uint32_t             : 16;
14983         } P0_QSTMAMU7_b;
14984     };
14985 
14986     union
14987     {
14988         __IOM uint32_t P0_QSTMAMD7;    /*!< (@ 0x00002124) Qci Stream Filter Table MAC Address Mask Downer
14989                                         *                  Part                                                       */
14990 
14991         struct
14992         {
14993             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
14994         } P0_QSTMAMD7_b;
14995     };
14996 
14997     union
14998     {
14999         __IOM uint32_t P0_QSFTVL7;      /*!< (@ 0x00002128) Qci Stream Filter Table VLAN                               */
15000 
15001         struct
15002         {
15003             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
15004             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
15005             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
15006             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
15007             uint32_t              : 14;
15008         } P0_QSFTVL7_b;
15009     };
15010 
15011     union
15012     {
15013         __IOM uint32_t P0_QSFTVLM7;      /*!< (@ 0x0000212C) Qci Stream Filter Table VLAN Mask                          */
15014 
15015         struct
15016         {
15017             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
15018             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
15019             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
15020             uint32_t               : 16;
15021         } P0_QSFTVLM7_b;
15022     };
15023 
15024     union
15025     {
15026         __IOM uint32_t P0_QSFTBL7;     /*!< (@ 0x00002130) Qci Stream Filter Table SDU/Gate/Meter ID                  */
15027 
15028         struct
15029         {
15030             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
15031             uint32_t             : 3;
15032             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
15033             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
15034             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
15035             uint32_t             : 1;
15036             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
15037             uint32_t             : 3;
15038             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
15039             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
15040             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
15041             uint32_t             : 3;
15042         } P0_QSFTBL7_b;
15043     };
15044 
15045     union
15046     {
15047         __IM uint32_t P0_QSMFC7;       /*!< (@ 0x00002134) Qci Stream Match Packet Count                              */
15048 
15049         struct
15050         {
15051             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
15052             uint32_t            : 16;
15053         } P0_QSMFC7_b;
15054     };
15055 
15056     union
15057     {
15058         __IM uint32_t P0_QMSPPC7;      /*!< (@ 0x00002138) Qci MSDU Passed Packet Count                               */
15059 
15060         struct
15061         {
15062             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
15063             uint32_t             : 16;
15064         } P0_QMSPPC7_b;
15065     };
15066 
15067     union
15068     {
15069         __IM uint32_t P0_QMSRPC7;      /*!< (@ 0x0000213C) Qci MSDU Reject Packet Count                               */
15070 
15071         struct
15072         {
15073             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
15074             uint32_t             : 16;
15075         } P0_QMSRPC7_b;
15076     };
15077     __IM uint32_t RESERVED57[42];
15078 
15079     union
15080     {
15081         __IOM uint32_t P0_QSEIS;       /*!< (@ 0x000021E8) Qci Stream Filter Error Interrupt Status (SDU
15082                                         *                  Oversize)                                                  */
15083 
15084         struct
15085         {
15086             __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
15087             uint32_t              : 24;
15088         } P0_QSEIS_b;
15089     };
15090 
15091     union
15092     {
15093         __IOM uint32_t P0_QSEIE;       /*!< (@ 0x000021EC) Qci Stream Filter Error Interrupt Enable                   */
15094 
15095         struct
15096         {
15097             __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
15098             uint32_t              : 24;
15099         } P0_QSEIE_b;
15100     };
15101 
15102     union
15103     {
15104         __OM uint32_t P0_QSEID;        /*!< (@ 0x000021F0) Qci Stream Filter Error Interrupt Disable                  */
15105 
15106         struct
15107         {
15108             __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
15109             uint32_t             : 24;
15110         } P0_QSEID_b;
15111     };
15112     __IM uint32_t RESERVED58[3];
15113 
15114     union
15115     {
15116         __IOM uint32_t P0_QGMOD;       /*!< (@ 0x00002200) Qci Gate Mode Register                                     */
15117 
15118         struct
15119         {
15120             __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
15121             uint32_t             : 24;
15122         } P0_QGMOD_b;
15123     };
15124 
15125     union
15126     {
15127         __IM uint32_t P0_QGPPC;        /*!< (@ 0x00002204) Qci Gate (All) Passed Packet Count Port 0                  */
15128 
15129         struct
15130         {
15131             __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
15132             uint32_t            : 16;
15133         } P0_QGPPC_b;
15134     };
15135 
15136     union
15137     {
15138         __IM uint32_t P0_QGDPC0;       /*!< (@ 0x00002208) Qci Gate 0 Dropped Packet Count Port n                     */
15139 
15140         struct
15141         {
15142             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15143             uint32_t            : 16;
15144         } P0_QGDPC0_b;
15145     };
15146     __IM uint32_t RESERVED59;
15147 
15148     union
15149     {
15150         __IM uint32_t P0_QGDPC1;       /*!< (@ 0x00002210) Qci Gate 1 Dropped Packet Count Port n                     */
15151 
15152         struct
15153         {
15154             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15155             uint32_t            : 16;
15156         } P0_QGDPC1_b;
15157     };
15158     __IM uint32_t RESERVED60;
15159 
15160     union
15161     {
15162         __IM uint32_t P0_QGDPC2;       /*!< (@ 0x00002218) Qci Gate 2 Dropped Packet Count Port n                     */
15163 
15164         struct
15165         {
15166             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15167             uint32_t            : 16;
15168         } P0_QGDPC2_b;
15169     };
15170     __IM uint32_t RESERVED61;
15171 
15172     union
15173     {
15174         __IM uint32_t P0_QGDPC3;       /*!< (@ 0x00002220) Qci Gate 3 Dropped Packet Count Port n                     */
15175 
15176         struct
15177         {
15178             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15179             uint32_t            : 16;
15180         } P0_QGDPC3_b;
15181     };
15182     __IM uint32_t RESERVED62;
15183 
15184     union
15185     {
15186         __IM uint32_t P0_QGDPC4;       /*!< (@ 0x00002228) Qci Gate 4 Dropped Packet Count Port n                     */
15187 
15188         struct
15189         {
15190             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15191             uint32_t            : 16;
15192         } P0_QGDPC4_b;
15193     };
15194     __IM uint32_t RESERVED63;
15195 
15196     union
15197     {
15198         __IM uint32_t P0_QGDPC5;       /*!< (@ 0x00002230) Qci Gate 5 Dropped Packet Count Port n                     */
15199 
15200         struct
15201         {
15202             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15203             uint32_t            : 16;
15204         } P0_QGDPC5_b;
15205     };
15206     __IM uint32_t RESERVED64;
15207 
15208     union
15209     {
15210         __IM uint32_t P0_QGDPC6;       /*!< (@ 0x00002238) Qci Gate 6 Dropped Packet Count Port n                     */
15211 
15212         struct
15213         {
15214             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15215             uint32_t            : 16;
15216         } P0_QGDPC6_b;
15217     };
15218     __IM uint32_t RESERVED65;
15219 
15220     union
15221     {
15222         __IM uint32_t P0_QGDPC7;       /*!< (@ 0x00002240) Qci Gate 7 Dropped Packet Count Port n                     */
15223 
15224         struct
15225         {
15226             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
15227             uint32_t            : 16;
15228         } P0_QGDPC7_b;
15229     };
15230 
15231     union
15232     {
15233         __IOM uint32_t P0_QGEIS;       /*!< (@ 0x00002244) Qci Gate Error Interrupt Status                            */
15234 
15235         struct
15236         {
15237             __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
15238             uint32_t              : 24;
15239         } P0_QGEIS_b;
15240     };
15241 
15242     union
15243     {
15244         __IOM uint32_t P0_QGEIE;       /*!< (@ 0x00002248) Qci Gate Error Interrupt Enable                            */
15245 
15246         struct
15247         {
15248             __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
15249             uint32_t              : 24;
15250         } P0_QGEIE_b;
15251     };
15252 
15253     union
15254     {
15255         __OM uint32_t P0_QGEID;        /*!< (@ 0x0000224C) Qci Gate Error Interrupt Disable                           */
15256 
15257         struct
15258         {
15259             __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
15260             uint32_t             : 24;
15261         } P0_QGEID_b;
15262     };
15263 
15264     union
15265     {
15266         __IOM uint32_t P0_QMDESC0;     /*!< (@ 0x00002250) Qci Port n Flow Meter 0 Descriptor Register                */
15267 
15268         struct
15269         {
15270             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15271             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15272             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15273             uint32_t           : 29;
15274         } P0_QMDESC0_b;
15275     };
15276 
15277     union
15278     {
15279         __IOM uint32_t P0_QMCBSC0;     /*!< (@ 0x00002254) Qci Meter CBS Configuration Port n, Meter 0                */
15280 
15281         struct
15282         {
15283             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15284             uint32_t           : 14;
15285         } P0_QMCBSC0_b;
15286     };
15287 
15288     union
15289     {
15290         __IOM uint32_t P0_QMCIRC0;     /*!< (@ 0x00002258) Qci Meter CIR Configuration n 0                            */
15291 
15292         struct
15293         {
15294             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15295             uint32_t           : 15;
15296         } P0_QMCIRC0_b;
15297     };
15298 
15299     union
15300     {
15301         __IM uint32_t P0_QMGPC0;       /*!< (@ 0x0000225C) Qci Meter Green Packet Count                               */
15302 
15303         struct
15304         {
15305             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15306             uint32_t            : 16;
15307         } P0_QMGPC0_b;
15308     };
15309 
15310     union
15311     {
15312         __IM uint32_t P0_QMRPC0;       /*!< (@ 0x00002260) Qci Meter Red Packet Count                                 */
15313 
15314         struct
15315         {
15316             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15317             uint32_t            : 16;
15318         } P0_QMRPC0_b;
15319     };
15320 
15321     union
15322     {
15323         __IOM uint32_t P0_QMDESC1;     /*!< (@ 0x00002264) Qci Port n Flow Meter 1 Descriptor Register                */
15324 
15325         struct
15326         {
15327             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15328             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15329             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15330             uint32_t           : 29;
15331         } P0_QMDESC1_b;
15332     };
15333 
15334     union
15335     {
15336         __IOM uint32_t P0_QMCBSC1;     /*!< (@ 0x00002268) Qci Meter CBS Configuration Port n, Meter 1                */
15337 
15338         struct
15339         {
15340             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15341             uint32_t           : 14;
15342         } P0_QMCBSC1_b;
15343     };
15344 
15345     union
15346     {
15347         __IOM uint32_t P0_QMCIRC1;     /*!< (@ 0x0000226C) Qci Meter CIR Configuration n 1                            */
15348 
15349         struct
15350         {
15351             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15352             uint32_t           : 15;
15353         } P0_QMCIRC1_b;
15354     };
15355 
15356     union
15357     {
15358         __IM uint32_t P0_QMGPC1;       /*!< (@ 0x00002270) Qci Meter Green Packet Count                               */
15359 
15360         struct
15361         {
15362             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15363             uint32_t            : 16;
15364         } P0_QMGPC1_b;
15365     };
15366 
15367     union
15368     {
15369         __IM uint32_t P0_QMRPC1;       /*!< (@ 0x00002274) Qci Meter Red Packet Count                                 */
15370 
15371         struct
15372         {
15373             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15374             uint32_t            : 16;
15375         } P0_QMRPC1_b;
15376     };
15377 
15378     union
15379     {
15380         __IOM uint32_t P0_QMDESC2;     /*!< (@ 0x00002278) Qci Port n Flow Meter 2 Descriptor Register                */
15381 
15382         struct
15383         {
15384             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15385             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15386             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15387             uint32_t           : 29;
15388         } P0_QMDESC2_b;
15389     };
15390 
15391     union
15392     {
15393         __IOM uint32_t P0_QMCBSC2;     /*!< (@ 0x0000227C) Qci Meter CBS Configuration Port n, Meter 2                */
15394 
15395         struct
15396         {
15397             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15398             uint32_t           : 14;
15399         } P0_QMCBSC2_b;
15400     };
15401 
15402     union
15403     {
15404         __IOM uint32_t P0_QMCIRC2;     /*!< (@ 0x00002280) Qci Meter CIR Configuration n 2                            */
15405 
15406         struct
15407         {
15408             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15409             uint32_t           : 15;
15410         } P0_QMCIRC2_b;
15411     };
15412 
15413     union
15414     {
15415         __IM uint32_t P0_QMGPC2;       /*!< (@ 0x00002284) Qci Meter Green Packet Count                               */
15416 
15417         struct
15418         {
15419             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15420             uint32_t            : 16;
15421         } P0_QMGPC2_b;
15422     };
15423 
15424     union
15425     {
15426         __IM uint32_t P0_QMRPC2;       /*!< (@ 0x00002288) Qci Meter Red Packet Count                                 */
15427 
15428         struct
15429         {
15430             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15431             uint32_t            : 16;
15432         } P0_QMRPC2_b;
15433     };
15434 
15435     union
15436     {
15437         __IOM uint32_t P0_QMDESC3;     /*!< (@ 0x0000228C) Qci Port n Flow Meter 3 Descriptor Register                */
15438 
15439         struct
15440         {
15441             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15442             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15443             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15444             uint32_t           : 29;
15445         } P0_QMDESC3_b;
15446     };
15447 
15448     union
15449     {
15450         __IOM uint32_t P0_QMCBSC3;     /*!< (@ 0x00002290) Qci Meter CBS Configuration Port n, Meter 3                */
15451 
15452         struct
15453         {
15454             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15455             uint32_t           : 14;
15456         } P0_QMCBSC3_b;
15457     };
15458 
15459     union
15460     {
15461         __IOM uint32_t P0_QMCIRC3;     /*!< (@ 0x00002294) Qci Meter CIR Configuration n 3                            */
15462 
15463         struct
15464         {
15465             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15466             uint32_t           : 15;
15467         } P0_QMCIRC3_b;
15468     };
15469 
15470     union
15471     {
15472         __IM uint32_t P0_QMGPC3;       /*!< (@ 0x00002298) Qci Meter Green Packet Count                               */
15473 
15474         struct
15475         {
15476             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15477             uint32_t            : 16;
15478         } P0_QMGPC3_b;
15479     };
15480 
15481     union
15482     {
15483         __IM uint32_t P0_QMRPC3;       /*!< (@ 0x0000229C) Qci Meter Red Packet Count                                 */
15484 
15485         struct
15486         {
15487             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15488             uint32_t            : 16;
15489         } P0_QMRPC3_b;
15490     };
15491 
15492     union
15493     {
15494         __IOM uint32_t P0_QMDESC4;     /*!< (@ 0x000022A0) Qci Port n Flow Meter 4 Descriptor Register                */
15495 
15496         struct
15497         {
15498             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15499             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15500             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15501             uint32_t           : 29;
15502         } P0_QMDESC4_b;
15503     };
15504 
15505     union
15506     {
15507         __IOM uint32_t P0_QMCBSC4;     /*!< (@ 0x000022A4) Qci Meter CBS Configuration Port n, Meter 4                */
15508 
15509         struct
15510         {
15511             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15512             uint32_t           : 14;
15513         } P0_QMCBSC4_b;
15514     };
15515 
15516     union
15517     {
15518         __IOM uint32_t P0_QMCIRC4;     /*!< (@ 0x000022A8) Qci Meter CIR Configuration n 4                            */
15519 
15520         struct
15521         {
15522             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15523             uint32_t           : 15;
15524         } P0_QMCIRC4_b;
15525     };
15526 
15527     union
15528     {
15529         __IM uint32_t P0_QMGPC4;       /*!< (@ 0x000022AC) Qci Meter Green Packet Count                               */
15530 
15531         struct
15532         {
15533             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15534             uint32_t            : 16;
15535         } P0_QMGPC4_b;
15536     };
15537 
15538     union
15539     {
15540         __IM uint32_t P0_QMRPC4;       /*!< (@ 0x000022B0) Qci Meter Red Packet Count                                 */
15541 
15542         struct
15543         {
15544             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15545             uint32_t            : 16;
15546         } P0_QMRPC4_b;
15547     };
15548 
15549     union
15550     {
15551         __IOM uint32_t P0_QMDESC5;     /*!< (@ 0x000022B4) Qci Port n Flow Meter 5 Descriptor Register                */
15552 
15553         struct
15554         {
15555             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15556             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15557             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15558             uint32_t           : 29;
15559         } P0_QMDESC5_b;
15560     };
15561 
15562     union
15563     {
15564         __IOM uint32_t P0_QMCBSC5;     /*!< (@ 0x000022B8) Qci Meter CBS Configuration Port n, Meter 5                */
15565 
15566         struct
15567         {
15568             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15569             uint32_t           : 14;
15570         } P0_QMCBSC5_b;
15571     };
15572 
15573     union
15574     {
15575         __IOM uint32_t P0_QMCIRC5;     /*!< (@ 0x000022BC) Qci Meter CIR Configuration n 5                            */
15576 
15577         struct
15578         {
15579             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15580             uint32_t           : 15;
15581         } P0_QMCIRC5_b;
15582     };
15583 
15584     union
15585     {
15586         __IM uint32_t P0_QMGPC5;       /*!< (@ 0x000022C0) Qci Meter Green Packet Count                               */
15587 
15588         struct
15589         {
15590             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15591             uint32_t            : 16;
15592         } P0_QMGPC5_b;
15593     };
15594 
15595     union
15596     {
15597         __IM uint32_t P0_QMRPC5;       /*!< (@ 0x000022C4) Qci Meter Red Packet Count                                 */
15598 
15599         struct
15600         {
15601             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15602             uint32_t            : 16;
15603         } P0_QMRPC5_b;
15604     };
15605 
15606     union
15607     {
15608         __IOM uint32_t P0_QMDESC6;     /*!< (@ 0x000022C8) Qci Port n Flow Meter 6 Descriptor Register                */
15609 
15610         struct
15611         {
15612             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15613             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15614             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15615             uint32_t           : 29;
15616         } P0_QMDESC6_b;
15617     };
15618 
15619     union
15620     {
15621         __IOM uint32_t P0_QMCBSC6;     /*!< (@ 0x000022CC) Qci Meter CBS Configuration Port n, Meter 6                */
15622 
15623         struct
15624         {
15625             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15626             uint32_t           : 14;
15627         } P0_QMCBSC6_b;
15628     };
15629 
15630     union
15631     {
15632         __IOM uint32_t P0_QMCIRC6;     /*!< (@ 0x000022D0) Qci Meter CIR Configuration n 6                            */
15633 
15634         struct
15635         {
15636             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15637             uint32_t           : 15;
15638         } P0_QMCIRC6_b;
15639     };
15640 
15641     union
15642     {
15643         __IM uint32_t P0_QMGPC6;       /*!< (@ 0x000022D4) Qci Meter Green Packet Count                               */
15644 
15645         struct
15646         {
15647             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15648             uint32_t            : 16;
15649         } P0_QMGPC6_b;
15650     };
15651 
15652     union
15653     {
15654         __IM uint32_t P0_QMRPC6;       /*!< (@ 0x000022D8) Qci Meter Red Packet Count                                 */
15655 
15656         struct
15657         {
15658             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15659             uint32_t            : 16;
15660         } P0_QMRPC6_b;
15661     };
15662 
15663     union
15664     {
15665         __IOM uint32_t P0_QMDESC7;     /*!< (@ 0x000022DC) Qci Port n Flow Meter 7 Descriptor Register                */
15666 
15667         struct
15668         {
15669             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
15670             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
15671             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
15672             uint32_t           : 29;
15673         } P0_QMDESC7_b;
15674     };
15675 
15676     union
15677     {
15678         __IOM uint32_t P0_QMCBSC7;     /*!< (@ 0x000022E0) Qci Meter CBS Configuration Port n, Meter 7                */
15679 
15680         struct
15681         {
15682             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
15683             uint32_t           : 14;
15684         } P0_QMCBSC7_b;
15685     };
15686 
15687     union
15688     {
15689         __IOM uint32_t P0_QMCIRC7;     /*!< (@ 0x000022E4) Qci Meter CIR Configuration n 7                            */
15690 
15691         struct
15692         {
15693             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
15694             uint32_t           : 15;
15695         } P0_QMCIRC7_b;
15696     };
15697 
15698     union
15699     {
15700         __IM uint32_t P0_QMGPC7;       /*!< (@ 0x000022E8) Qci Meter Green Packet Count                               */
15701 
15702         struct
15703         {
15704             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
15705             uint32_t            : 16;
15706         } P0_QMGPC7_b;
15707     };
15708 
15709     union
15710     {
15711         __IM uint32_t P0_QMRPC7;       /*!< (@ 0x000022EC) Qci Meter Red Packet Count                                 */
15712 
15713         struct
15714         {
15715             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
15716             uint32_t            : 16;
15717         } P0_QMRPC7_b;
15718     };
15719 
15720     union
15721     {
15722         __IOM uint32_t P0_QMEC;        /*!< (@ 0x000022F0) Qci Meter Enable Configuration                             */
15723 
15724         struct
15725         {
15726             __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
15727             uint32_t          : 24;
15728         } P0_QMEC_b;
15729     };
15730 
15731     union
15732     {
15733         __IOM uint32_t P0_QMEIS;       /*!< (@ 0x000022F4) Qci Meter Error Interrupt Status                           */
15734 
15735         struct
15736         {
15737             __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
15738             uint32_t             : 24;
15739         } P0_QMEIS_b;
15740     };
15741 
15742     union
15743     {
15744         __IOM uint32_t P0_QMEIE;       /*!< (@ 0x000022F8) Qci Meter Error Interrupt Enable                           */
15745 
15746         struct
15747         {
15748             __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
15749             uint32_t             : 24;
15750         } P0_QMEIE_b;
15751     };
15752 
15753     union
15754     {
15755         __OM uint32_t P0_QMEID;        /*!< (@ 0x000022FC) Qci Meter Error Interrupt Disable                          */
15756 
15757         struct
15758         {
15759             __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
15760             uint32_t            : 24;
15761         } P0_QMEID_b;
15762     };
15763 
15764     union
15765     {
15766         __IOM uint32_t P0_PCP_REMAP;       /*!< (@ 0x00002300) Port 0 VLAN Priority Code Point (PCP) Remap                */
15767 
15768         struct
15769         {
15770             __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
15771             __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
15772             __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
15773             __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
15774             __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
15775             __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
15776             __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
15777             __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
15778             uint32_t                  : 8;
15779         } P0_PCP_REMAP_b;
15780     };
15781 
15782     union
15783     {
15784         __IOM uint32_t P0_VLAN_TAG;    /*!< (@ 0x00002304) Port 0 VLAN TAG Information for Priority Regeneration      */
15785 
15786         struct
15787         {
15788             __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
15789             __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
15790             __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
15791             __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
15792         } P0_VLAN_TAG_b;
15793     };
15794 
15795     union
15796     {
15797         __IOM uint32_t P0_VLAN_MODE;   /*!< (@ 0x00002308) Port 0 VLAN Mode                                           */
15798 
15799         struct
15800         {
15801             __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
15802             __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
15803             uint32_t            : 28;
15804         } P0_VLAN_MODE_b;
15805     };
15806 
15807     union
15808     {
15809         __IM uint32_t P0_VIC_DROP_CNT;       /*!< (@ 0x0000230C) Port 0 VLAN Ingress Check Drop Frame Counter               */
15810 
15811         struct
15812         {
15813             __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
15814             uint32_t                   : 16;
15815         } P0_VIC_DROP_CNT_b;
15816     };
15817     __IM uint32_t RESERVED66[6];
15818 
15819     union
15820     {
15821         __IM uint32_t P0_LOOKUP_HIT_CNT;       /*!< (@ 0x00002328) Port 0 DST Address Lookup Hit Counter                      */
15822 
15823         struct
15824         {
15825             __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
15826             uint32_t                     : 8;
15827         } P0_LOOKUP_HIT_CNT_b;
15828     };
15829 
15830     union
15831     {
15832         __IOM uint32_t P0_ERROR_STATUS; /*!< (@ 0x0000232C) Port 0 Frame Parser Runtime Error Status                   */
15833 
15834         struct
15835         {
15836             __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
15837             __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
15838                                          *   parser                                                                    */
15839             __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
15840             __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
15841             __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
15842             uint32_t              : 27;
15843         } P0_ERROR_STATUS_b;
15844     };
15845 
15846     union
15847     {
15848         __IOM uint32_t P0_ERROR_MASK;   /*!< (@ 0x00002330) Port 0 Frame Parser Runtime Error Mask                     */
15849 
15850         struct
15851         {
15852             __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
15853             __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
15854             __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
15855             __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
15856             __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
15857             uint32_t               : 27;
15858         } P0_ERROR_MASK_b;
15859     };
15860     __IM uint32_t RESERVED67[35];
15861 
15862     union
15863     {
15864         __IM uint32_t CHANNEL_STATE;   /*!< (@ 0x000023C0) Enable/Disable State of Ingress Channels                   */
15865 
15866         struct
15867         {
15868             __IM uint32_t CH0ACT : 1;  /*!< [0..0] CH0ACT                                                             */
15869             __IM uint32_t CH1ACT : 1;  /*!< [1..1] CH1ACT                                                             */
15870             __IM uint32_t CH2ACT : 1;  /*!< [2..2] CH2ACT                                                             */
15871             uint32_t             : 29;
15872         } CHANNEL_STATE_b;
15873     };
15874 
15875     union
15876     {
15877         __OM uint32_t CHANNEL_ENABLE;  /*!< (@ 0x000023C4) Enable Operation of Channel                                */
15878 
15879         struct
15880         {
15881             __OM uint32_t CH0ENA : 1;  /*!< [0..0] CH0ENA                                                             */
15882             __OM uint32_t CH1ENA : 1;  /*!< [1..1] CH1ENA                                                             */
15883             __OM uint32_t CH2ENA : 1;  /*!< [2..2] CH2ENA                                                             */
15884             uint32_t             : 29;
15885         } CHANNEL_ENABLE_b;
15886     };
15887 
15888     union
15889     {
15890         __OM uint32_t CHANNEL_DISABLE; /*!< (@ 0x000023C8) Disable and Reset Operation of Channel                     */
15891 
15892         struct
15893         {
15894             __OM uint32_t CH0DIS : 1;  /*!< [0..0] CH0DIS                                                             */
15895             __OM uint32_t CH1DIS : 1;  /*!< [1..1] CH1DIS                                                             */
15896             __OM uint32_t CH2DIS : 1;  /*!< [2..2] CH2DIS                                                             */
15897             uint32_t             : 29;
15898         } CHANNEL_DISABLE_b;
15899     };
15900 
15901     union
15902     {
15903         __IOM uint32_t ASI_MEM_WDATA[4]; /*!< (@ 0x000023CC) Memory Write Data Word [0..3]                              */
15904 
15905         struct
15906         {
15907             __IOM uint32_t WDATA : 32;   /*!< [31..0] Destination MAC address regeneration write data                   */
15908         } ASI_MEM_WDATA_b[4];
15909     };
15910 
15911     union
15912     {
15913         __IOM uint32_t ASI_MEM_ADDR;    /*!< (@ 0x000023DC) Memory Address and R/W Control                             */
15914 
15915         struct
15916         {
15917             __IOM uint32_t ADDR    : 7; /*!< [6..0] Memory access address                                              */
15918             __IOM uint32_t MEM_WEN : 1; /*!< [7..7] MEM_WEN                                                            */
15919             __IOM uint32_t MEM_REQ : 3; /*!< [10..8] Memory access request                                             */
15920             uint32_t               : 21;
15921         } ASI_MEM_ADDR_b;
15922     };
15923 
15924     union
15925     {
15926         __IM uint32_t ASI_MEM_RDATA[4]; /*!< (@ 0x000023E0) Memory Read Data Word [0..3]                               */
15927 
15928         struct
15929         {
15930             __IM uint32_t RDATA : 32;   /*!< [31..0] Destination MAC address regeneration read data                    */
15931         } ASI_MEM_RDATA_b[4];
15932     };
15933     __IM uint32_t RESERVED68[4];
15934 
15935     union
15936     {
15937         __IOM uint32_t P1_QSTMACU0;    /*!< (@ 0x00002400) Qci Stream Filter Table MAC Address Upper Part             */
15938 
15939         struct
15940         {
15941             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
15942             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
15943             uint32_t            : 15;
15944         } P1_QSTMACU0_b;
15945     };
15946 
15947     union
15948     {
15949         __IOM uint32_t P1_QSTMACD0;    /*!< (@ 0x00002404) Qci Stream Filter Table MAC Address Downer Part            */
15950 
15951         struct
15952         {
15953             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
15954         } P1_QSTMACD0_b;
15955     };
15956 
15957     union
15958     {
15959         __IOM uint32_t P1_QSTMAMU0;    /*!< (@ 0x00002408) Qci Stream Filter Table MAC Address Mask Upper
15960                                         *                  Part                                                       */
15961 
15962         struct
15963         {
15964             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
15965             uint32_t             : 16;
15966         } P1_QSTMAMU0_b;
15967     };
15968 
15969     union
15970     {
15971         __IOM uint32_t P1_QSTMAMD0;    /*!< (@ 0x0000240C) Qci Stream Filter Table MAC Address Mask Downer
15972                                         *                  Part                                                       */
15973 
15974         struct
15975         {
15976             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
15977         } P1_QSTMAMD0_b;
15978     };
15979 
15980     union
15981     {
15982         __IOM uint32_t P1_QSFTVL0;      /*!< (@ 0x00002410) Qci Stream Filter Table VLAN                               */
15983 
15984         struct
15985         {
15986             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
15987             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
15988             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
15989             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
15990             uint32_t              : 14;
15991         } P1_QSFTVL0_b;
15992     };
15993 
15994     union
15995     {
15996         __IOM uint32_t P1_QSFTVLM0;      /*!< (@ 0x00002414) Qci Stream Filter Table VLAN Mask                          */
15997 
15998         struct
15999         {
16000             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16001             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16002             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16003             uint32_t               : 16;
16004         } P1_QSFTVLM0_b;
16005     };
16006 
16007     union
16008     {
16009         __IOM uint32_t P1_QSFTBL0;     /*!< (@ 0x00002418) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16010 
16011         struct
16012         {
16013             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16014             uint32_t             : 3;
16015             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16016             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16017             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16018             uint32_t             : 1;
16019             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16020             uint32_t             : 3;
16021             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16022             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16023             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16024             uint32_t             : 3;
16025         } P1_QSFTBL0_b;
16026     };
16027 
16028     union
16029     {
16030         __IM uint32_t P1_QSMFC0;       /*!< (@ 0x0000241C) Qci Stream Match Packet Count                              */
16031 
16032         struct
16033         {
16034             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16035             uint32_t            : 16;
16036         } P1_QSMFC0_b;
16037     };
16038 
16039     union
16040     {
16041         __IM uint32_t P1_QMSPPC0;      /*!< (@ 0x00002420) Qci MSDU Passed Packet Count                               */
16042 
16043         struct
16044         {
16045             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16046             uint32_t             : 16;
16047         } P1_QMSPPC0_b;
16048     };
16049 
16050     union
16051     {
16052         __IM uint32_t P1_QMSRPC0;      /*!< (@ 0x00002424) Qci MSDU Reject Packet Count                               */
16053 
16054         struct
16055         {
16056             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16057             uint32_t             : 16;
16058         } P1_QMSRPC0_b;
16059     };
16060 
16061     union
16062     {
16063         __IOM uint32_t P1_QSTMACU1;    /*!< (@ 0x00002428) Qci Stream Filter Table MAC Address Upper Part             */
16064 
16065         struct
16066         {
16067             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
16068             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
16069             uint32_t            : 15;
16070         } P1_QSTMACU1_b;
16071     };
16072 
16073     union
16074     {
16075         __IOM uint32_t P1_QSTMACD1;    /*!< (@ 0x0000242C) Qci Stream Filter Table MAC Address Downer Part            */
16076 
16077         struct
16078         {
16079             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
16080         } P1_QSTMACD1_b;
16081     };
16082 
16083     union
16084     {
16085         __IOM uint32_t P1_QSTMAMU1;    /*!< (@ 0x00002430) Qci Stream Filter Table MAC Address Mask Upper
16086                                         *                  Part                                                       */
16087 
16088         struct
16089         {
16090             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
16091             uint32_t             : 16;
16092         } P1_QSTMAMU1_b;
16093     };
16094 
16095     union
16096     {
16097         __IOM uint32_t P1_QSTMAMD1;    /*!< (@ 0x00002434) Qci Stream Filter Table MAC Address Mask Downer
16098                                         *                  Part                                                       */
16099 
16100         struct
16101         {
16102             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
16103         } P1_QSTMAMD1_b;
16104     };
16105 
16106     union
16107     {
16108         __IOM uint32_t P1_QSFTVL1;      /*!< (@ 0x00002438) Qci Stream Filter Table VLAN                               */
16109 
16110         struct
16111         {
16112             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
16113             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
16114             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
16115             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
16116             uint32_t              : 14;
16117         } P1_QSFTVL1_b;
16118     };
16119 
16120     union
16121     {
16122         __IOM uint32_t P1_QSFTVLM1;      /*!< (@ 0x0000243C) Qci Stream Filter Table VLAN Mask                          */
16123 
16124         struct
16125         {
16126             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16127             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16128             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16129             uint32_t               : 16;
16130         } P1_QSFTVLM1_b;
16131     };
16132 
16133     union
16134     {
16135         __IOM uint32_t P1_QSFTBL1;     /*!< (@ 0x00002440) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16136 
16137         struct
16138         {
16139             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16140             uint32_t             : 3;
16141             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16142             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16143             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16144             uint32_t             : 1;
16145             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16146             uint32_t             : 3;
16147             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16148             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16149             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16150             uint32_t             : 3;
16151         } P1_QSFTBL1_b;
16152     };
16153 
16154     union
16155     {
16156         __IM uint32_t P1_QSMFC1;       /*!< (@ 0x00002444) Qci Stream Match Packet Count                              */
16157 
16158         struct
16159         {
16160             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16161             uint32_t            : 16;
16162         } P1_QSMFC1_b;
16163     };
16164 
16165     union
16166     {
16167         __IM uint32_t P1_QMSPPC1;      /*!< (@ 0x00002448) Qci MSDU Passed Packet Count                               */
16168 
16169         struct
16170         {
16171             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16172             uint32_t             : 16;
16173         } P1_QMSPPC1_b;
16174     };
16175 
16176     union
16177     {
16178         __IM uint32_t P1_QMSRPC1;      /*!< (@ 0x0000244C) Qci MSDU Reject Packet Count                               */
16179 
16180         struct
16181         {
16182             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16183             uint32_t             : 16;
16184         } P1_QMSRPC1_b;
16185     };
16186 
16187     union
16188     {
16189         __IOM uint32_t P1_QSTMACU2;    /*!< (@ 0x00002450) Qci Stream Filter Table MAC Address Upper Part             */
16190 
16191         struct
16192         {
16193             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
16194             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
16195             uint32_t            : 15;
16196         } P1_QSTMACU2_b;
16197     };
16198 
16199     union
16200     {
16201         __IOM uint32_t P1_QSTMACD2;    /*!< (@ 0x00002454) Qci Stream Filter Table MAC Address Downer Part            */
16202 
16203         struct
16204         {
16205             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
16206         } P1_QSTMACD2_b;
16207     };
16208 
16209     union
16210     {
16211         __IOM uint32_t P1_QSTMAMU2;    /*!< (@ 0x00002458) Qci Stream Filter Table MAC Address Mask Upper
16212                                         *                  Part                                                       */
16213 
16214         struct
16215         {
16216             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
16217             uint32_t             : 16;
16218         } P1_QSTMAMU2_b;
16219     };
16220 
16221     union
16222     {
16223         __IOM uint32_t P1_QSTMAMD2;    /*!< (@ 0x0000245C) Qci Stream Filter Table MAC Address Mask Downer
16224                                         *                  Part                                                       */
16225 
16226         struct
16227         {
16228             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
16229         } P1_QSTMAMD2_b;
16230     };
16231 
16232     union
16233     {
16234         __IOM uint32_t P1_QSFTVL2;      /*!< (@ 0x00002460) Qci Stream Filter Table VLAN                               */
16235 
16236         struct
16237         {
16238             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
16239             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
16240             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
16241             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
16242             uint32_t              : 14;
16243         } P1_QSFTVL2_b;
16244     };
16245 
16246     union
16247     {
16248         __IOM uint32_t P1_QSFTVLM2;      /*!< (@ 0x00002464) Qci Stream Filter Table VLAN Mask                          */
16249 
16250         struct
16251         {
16252             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16253             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16254             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16255             uint32_t               : 16;
16256         } P1_QSFTVLM2_b;
16257     };
16258 
16259     union
16260     {
16261         __IOM uint32_t P1_QSFTBL2;     /*!< (@ 0x00002468) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16262 
16263         struct
16264         {
16265             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16266             uint32_t             : 3;
16267             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16268             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16269             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16270             uint32_t             : 1;
16271             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16272             uint32_t             : 3;
16273             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16274             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16275             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16276             uint32_t             : 3;
16277         } P1_QSFTBL2_b;
16278     };
16279 
16280     union
16281     {
16282         __IM uint32_t P1_QSMFC2;       /*!< (@ 0x0000246C) Qci Stream Match Packet Count                              */
16283 
16284         struct
16285         {
16286             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16287             uint32_t            : 16;
16288         } P1_QSMFC2_b;
16289     };
16290 
16291     union
16292     {
16293         __IM uint32_t P1_QMSPPC2;      /*!< (@ 0x00002470) Qci MSDU Passed Packet Count                               */
16294 
16295         struct
16296         {
16297             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16298             uint32_t             : 16;
16299         } P1_QMSPPC2_b;
16300     };
16301 
16302     union
16303     {
16304         __IM uint32_t P1_QMSRPC2;      /*!< (@ 0x00002474) Qci MSDU Reject Packet Count                               */
16305 
16306         struct
16307         {
16308             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16309             uint32_t             : 16;
16310         } P1_QMSRPC2_b;
16311     };
16312 
16313     union
16314     {
16315         __IOM uint32_t P1_QSTMACU3;    /*!< (@ 0x00002478) Qci Stream Filter Table MAC Address Upper Part             */
16316 
16317         struct
16318         {
16319             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
16320             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
16321             uint32_t            : 15;
16322         } P1_QSTMACU3_b;
16323     };
16324 
16325     union
16326     {
16327         __IOM uint32_t P1_QSTMACD3;    /*!< (@ 0x0000247C) Qci Stream Filter Table MAC Address Downer Part            */
16328 
16329         struct
16330         {
16331             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
16332         } P1_QSTMACD3_b;
16333     };
16334 
16335     union
16336     {
16337         __IOM uint32_t P1_QSTMAMU3;    /*!< (@ 0x00002480) Qci Stream Filter Table MAC Address Mask Upper
16338                                         *                  Part                                                       */
16339 
16340         struct
16341         {
16342             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
16343             uint32_t             : 16;
16344         } P1_QSTMAMU3_b;
16345     };
16346 
16347     union
16348     {
16349         __IOM uint32_t P1_QSTMAMD3;    /*!< (@ 0x00002484) Qci Stream Filter Table MAC Address Mask Downer
16350                                         *                  Part                                                       */
16351 
16352         struct
16353         {
16354             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
16355         } P1_QSTMAMD3_b;
16356     };
16357 
16358     union
16359     {
16360         __IOM uint32_t P1_QSFTVL3;      /*!< (@ 0x00002488) Qci Stream Filter Table VLAN                               */
16361 
16362         struct
16363         {
16364             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
16365             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
16366             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
16367             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
16368             uint32_t              : 14;
16369         } P1_QSFTVL3_b;
16370     };
16371 
16372     union
16373     {
16374         __IOM uint32_t P1_QSFTVLM3;      /*!< (@ 0x0000248C) Qci Stream Filter Table VLAN Mask                          */
16375 
16376         struct
16377         {
16378             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16379             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16380             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16381             uint32_t               : 16;
16382         } P1_QSFTVLM3_b;
16383     };
16384 
16385     union
16386     {
16387         __IOM uint32_t P1_QSFTBL3;     /*!< (@ 0x00002490) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16388 
16389         struct
16390         {
16391             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16392             uint32_t             : 3;
16393             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16394             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16395             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16396             uint32_t             : 1;
16397             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16398             uint32_t             : 3;
16399             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16400             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16401             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16402             uint32_t             : 3;
16403         } P1_QSFTBL3_b;
16404     };
16405 
16406     union
16407     {
16408         __IM uint32_t P1_QSMFC3;       /*!< (@ 0x00002494) Qci Stream Match Packet Count                              */
16409 
16410         struct
16411         {
16412             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16413             uint32_t            : 16;
16414         } P1_QSMFC3_b;
16415     };
16416 
16417     union
16418     {
16419         __IM uint32_t P1_QMSPPC3;      /*!< (@ 0x00002498) Qci MSDU Passed Packet Count                               */
16420 
16421         struct
16422         {
16423             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16424             uint32_t             : 16;
16425         } P1_QMSPPC3_b;
16426     };
16427 
16428     union
16429     {
16430         __IM uint32_t P1_QMSRPC3;      /*!< (@ 0x0000249C) Qci MSDU Reject Packet Count                               */
16431 
16432         struct
16433         {
16434             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16435             uint32_t             : 16;
16436         } P1_QMSRPC3_b;
16437     };
16438 
16439     union
16440     {
16441         __IOM uint32_t P1_QSTMACU4;    /*!< (@ 0x000024A0) Qci Stream Filter Table MAC Address Upper Part             */
16442 
16443         struct
16444         {
16445             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
16446             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
16447             uint32_t            : 15;
16448         } P1_QSTMACU4_b;
16449     };
16450 
16451     union
16452     {
16453         __IOM uint32_t P1_QSTMACD4;    /*!< (@ 0x000024A4) Qci Stream Filter Table MAC Address Downer Part            */
16454 
16455         struct
16456         {
16457             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
16458         } P1_QSTMACD4_b;
16459     };
16460 
16461     union
16462     {
16463         __IOM uint32_t P1_QSTMAMU4;    /*!< (@ 0x000024A8) Qci Stream Filter Table MAC Address Mask Upper
16464                                         *                  Part                                                       */
16465 
16466         struct
16467         {
16468             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
16469             uint32_t             : 16;
16470         } P1_QSTMAMU4_b;
16471     };
16472 
16473     union
16474     {
16475         __IOM uint32_t P1_QSTMAMD4;    /*!< (@ 0x000024AC) Qci Stream Filter Table MAC Address Mask Downer
16476                                         *                  Part                                                       */
16477 
16478         struct
16479         {
16480             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
16481         } P1_QSTMAMD4_b;
16482     };
16483 
16484     union
16485     {
16486         __IOM uint32_t P1_QSFTVL4;      /*!< (@ 0x000024B0) Qci Stream Filter Table VLAN                               */
16487 
16488         struct
16489         {
16490             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
16491             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
16492             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
16493             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
16494             uint32_t              : 14;
16495         } P1_QSFTVL4_b;
16496     };
16497 
16498     union
16499     {
16500         __IOM uint32_t P1_QSFTVLM4;      /*!< (@ 0x000024B4) Qci Stream Filter Table VLAN Mask                          */
16501 
16502         struct
16503         {
16504             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16505             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16506             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16507             uint32_t               : 16;
16508         } P1_QSFTVLM4_b;
16509     };
16510 
16511     union
16512     {
16513         __IOM uint32_t P1_QSFTBL4;     /*!< (@ 0x000024B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16514 
16515         struct
16516         {
16517             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16518             uint32_t             : 3;
16519             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16520             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16521             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16522             uint32_t             : 1;
16523             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16524             uint32_t             : 3;
16525             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16526             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16527             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16528             uint32_t             : 3;
16529         } P1_QSFTBL4_b;
16530     };
16531 
16532     union
16533     {
16534         __IM uint32_t P1_QSMFC4;       /*!< (@ 0x000024BC) Qci Stream Match Packet Count                              */
16535 
16536         struct
16537         {
16538             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16539             uint32_t            : 16;
16540         } P1_QSMFC4_b;
16541     };
16542 
16543     union
16544     {
16545         __IM uint32_t P1_QMSPPC4;      /*!< (@ 0x000024C0) Qci MSDU Passed Packet Count                               */
16546 
16547         struct
16548         {
16549             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16550             uint32_t             : 16;
16551         } P1_QMSPPC4_b;
16552     };
16553 
16554     union
16555     {
16556         __IM uint32_t P1_QMSRPC4;      /*!< (@ 0x000024C4) Qci MSDU Reject Packet Count                               */
16557 
16558         struct
16559         {
16560             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16561             uint32_t             : 16;
16562         } P1_QMSRPC4_b;
16563     };
16564 
16565     union
16566     {
16567         __IOM uint32_t P1_QSTMACU5;    /*!< (@ 0x000024C8) Qci Stream Filter Table MAC Address Upper Part             */
16568 
16569         struct
16570         {
16571             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
16572             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
16573             uint32_t            : 15;
16574         } P1_QSTMACU5_b;
16575     };
16576 
16577     union
16578     {
16579         __IOM uint32_t P1_QSTMACD5;    /*!< (@ 0x000024CC) Qci Stream Filter Table MAC Address Downer Part            */
16580 
16581         struct
16582         {
16583             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
16584         } P1_QSTMACD5_b;
16585     };
16586 
16587     union
16588     {
16589         __IOM uint32_t P1_QSTMAMU5;    /*!< (@ 0x000024D0) Qci Stream Filter Table MAC Address Mask Upper
16590                                         *                  Part                                                       */
16591 
16592         struct
16593         {
16594             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
16595             uint32_t             : 16;
16596         } P1_QSTMAMU5_b;
16597     };
16598 
16599     union
16600     {
16601         __IOM uint32_t P1_QSTMAMD5;    /*!< (@ 0x000024D4) Qci Stream Filter Table MAC Address Mask Downer
16602                                         *                  Part                                                       */
16603 
16604         struct
16605         {
16606             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
16607         } P1_QSTMAMD5_b;
16608     };
16609 
16610     union
16611     {
16612         __IOM uint32_t P1_QSFTVL5;      /*!< (@ 0x000024D8) Qci Stream Filter Table VLAN                               */
16613 
16614         struct
16615         {
16616             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
16617             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
16618             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
16619             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
16620             uint32_t              : 14;
16621         } P1_QSFTVL5_b;
16622     };
16623 
16624     union
16625     {
16626         __IOM uint32_t P1_QSFTVLM5;      /*!< (@ 0x000024DC) Qci Stream Filter Table VLAN Mask                          */
16627 
16628         struct
16629         {
16630             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16631             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16632             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16633             uint32_t               : 16;
16634         } P1_QSFTVLM5_b;
16635     };
16636 
16637     union
16638     {
16639         __IOM uint32_t P1_QSFTBL5;     /*!< (@ 0x000024E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16640 
16641         struct
16642         {
16643             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16644             uint32_t             : 3;
16645             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16646             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16647             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16648             uint32_t             : 1;
16649             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16650             uint32_t             : 3;
16651             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16652             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16653             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16654             uint32_t             : 3;
16655         } P1_QSFTBL5_b;
16656     };
16657 
16658     union
16659     {
16660         __IM uint32_t P1_QSMFC5;       /*!< (@ 0x000024E4) Qci Stream Match Packet Count                              */
16661 
16662         struct
16663         {
16664             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16665             uint32_t            : 16;
16666         } P1_QSMFC5_b;
16667     };
16668 
16669     union
16670     {
16671         __IM uint32_t P1_QMSPPC5;      /*!< (@ 0x000024E8) Qci MSDU Passed Packet Count                               */
16672 
16673         struct
16674         {
16675             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16676             uint32_t             : 16;
16677         } P1_QMSPPC5_b;
16678     };
16679 
16680     union
16681     {
16682         __IM uint32_t P1_QMSRPC5;      /*!< (@ 0x000024EC) Qci MSDU Reject Packet Count                               */
16683 
16684         struct
16685         {
16686             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16687             uint32_t             : 16;
16688         } P1_QMSRPC5_b;
16689     };
16690 
16691     union
16692     {
16693         __IOM uint32_t P1_QSTMACU6;    /*!< (@ 0x000024F0) Qci Stream Filter Table MAC Address Upper Part             */
16694 
16695         struct
16696         {
16697             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
16698             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
16699             uint32_t            : 15;
16700         } P1_QSTMACU6_b;
16701     };
16702 
16703     union
16704     {
16705         __IOM uint32_t P1_QSTMACD6;    /*!< (@ 0x000024F4) Qci Stream Filter Table MAC Address Downer Part            */
16706 
16707         struct
16708         {
16709             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
16710         } P1_QSTMACD6_b;
16711     };
16712 
16713     union
16714     {
16715         __IOM uint32_t P1_QSTMAMU6;    /*!< (@ 0x000024F8) Qci Stream Filter Table MAC Address Mask Upper
16716                                         *                  Part                                                       */
16717 
16718         struct
16719         {
16720             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
16721             uint32_t             : 16;
16722         } P1_QSTMAMU6_b;
16723     };
16724 
16725     union
16726     {
16727         __IOM uint32_t P1_QSTMAMD6;    /*!< (@ 0x000024FC) Qci Stream Filter Table MAC Address Mask Downer
16728                                         *                  Part                                                       */
16729 
16730         struct
16731         {
16732             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
16733         } P1_QSTMAMD6_b;
16734     };
16735 
16736     union
16737     {
16738         __IOM uint32_t P1_QSFTVL6;      /*!< (@ 0x00002500) Qci Stream Filter Table VLAN                               */
16739 
16740         struct
16741         {
16742             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
16743             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
16744             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
16745             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
16746             uint32_t              : 14;
16747         } P1_QSFTVL6_b;
16748     };
16749 
16750     union
16751     {
16752         __IOM uint32_t P1_QSFTVLM6;      /*!< (@ 0x00002504) Qci Stream Filter Table VLAN Mask                          */
16753 
16754         struct
16755         {
16756             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16757             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16758             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16759             uint32_t               : 16;
16760         } P1_QSFTVLM6_b;
16761     };
16762 
16763     union
16764     {
16765         __IOM uint32_t P1_QSFTBL6;     /*!< (@ 0x00002508) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16766 
16767         struct
16768         {
16769             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16770             uint32_t             : 3;
16771             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16772             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16773             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16774             uint32_t             : 1;
16775             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16776             uint32_t             : 3;
16777             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16778             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16779             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16780             uint32_t             : 3;
16781         } P1_QSFTBL6_b;
16782     };
16783 
16784     union
16785     {
16786         __IM uint32_t P1_QSMFC6;       /*!< (@ 0x0000250C) Qci Stream Match Packet Count                              */
16787 
16788         struct
16789         {
16790             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16791             uint32_t            : 16;
16792         } P1_QSMFC6_b;
16793     };
16794 
16795     union
16796     {
16797         __IM uint32_t P1_QMSPPC6;      /*!< (@ 0x00002510) Qci MSDU Passed Packet Count                               */
16798 
16799         struct
16800         {
16801             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16802             uint32_t             : 16;
16803         } P1_QMSPPC6_b;
16804     };
16805 
16806     union
16807     {
16808         __IM uint32_t P1_QMSRPC6;      /*!< (@ 0x00002514) Qci MSDU Reject Packet Count                               */
16809 
16810         struct
16811         {
16812             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16813             uint32_t             : 16;
16814         } P1_QMSRPC6_b;
16815     };
16816 
16817     union
16818     {
16819         __IOM uint32_t P1_QSTMACU7;    /*!< (@ 0x00002518) Qci Stream Filter Table MAC Address Upper Part             */
16820 
16821         struct
16822         {
16823             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
16824             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
16825             uint32_t            : 15;
16826         } P1_QSTMACU7_b;
16827     };
16828 
16829     union
16830     {
16831         __IOM uint32_t P1_QSTMACD7;    /*!< (@ 0x0000251C) Qci Stream Filter Table MAC Address Downer Part            */
16832 
16833         struct
16834         {
16835             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
16836         } P1_QSTMACD7_b;
16837     };
16838 
16839     union
16840     {
16841         __IOM uint32_t P1_QSTMAMU7;    /*!< (@ 0x00002520) Qci Stream Filter Table MAC Address Mask Upper
16842                                         *                  Part                                                       */
16843 
16844         struct
16845         {
16846             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
16847             uint32_t             : 16;
16848         } P1_QSTMAMU7_b;
16849     };
16850 
16851     union
16852     {
16853         __IOM uint32_t P1_QSTMAMD7;    /*!< (@ 0x00002524) Qci Stream Filter Table MAC Address Mask Downer
16854                                         *                  Part                                                       */
16855 
16856         struct
16857         {
16858             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
16859         } P1_QSTMAMD7_b;
16860     };
16861 
16862     union
16863     {
16864         __IOM uint32_t P1_QSFTVL7;      /*!< (@ 0x00002528) Qci Stream Filter Table VLAN                               */
16865 
16866         struct
16867         {
16868             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
16869             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
16870             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
16871             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
16872             uint32_t              : 14;
16873         } P1_QSFTVL7_b;
16874     };
16875 
16876     union
16877     {
16878         __IOM uint32_t P1_QSFTVLM7;      /*!< (@ 0x0000252C) Qci Stream Filter Table VLAN Mask                          */
16879 
16880         struct
16881         {
16882             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
16883             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
16884             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
16885             uint32_t               : 16;
16886         } P1_QSFTVLM7_b;
16887     };
16888 
16889     union
16890     {
16891         __IOM uint32_t P1_QSFTBL7;     /*!< (@ 0x00002530) Qci Stream Filter Table SDU/Gate/Meter ID                  */
16892 
16893         struct
16894         {
16895             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
16896             uint32_t             : 3;
16897             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
16898             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
16899             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
16900             uint32_t             : 1;
16901             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
16902             uint32_t             : 3;
16903             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
16904             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
16905             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
16906             uint32_t             : 3;
16907         } P1_QSFTBL7_b;
16908     };
16909 
16910     union
16911     {
16912         __IM uint32_t P1_QSMFC7;       /*!< (@ 0x00002534) Qci Stream Match Packet Count                              */
16913 
16914         struct
16915         {
16916             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
16917             uint32_t            : 16;
16918         } P1_QSMFC7_b;
16919     };
16920 
16921     union
16922     {
16923         __IM uint32_t P1_QMSPPC7;      /*!< (@ 0x00002538) Qci MSDU Passed Packet Count                               */
16924 
16925         struct
16926         {
16927             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
16928             uint32_t             : 16;
16929         } P1_QMSPPC7_b;
16930     };
16931 
16932     union
16933     {
16934         __IM uint32_t P1_QMSRPC7;      /*!< (@ 0x0000253C) Qci MSDU Reject Packet Count                               */
16935 
16936         struct
16937         {
16938             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
16939             uint32_t             : 16;
16940         } P1_QMSRPC7_b;
16941     };
16942     __IM uint32_t RESERVED69[42];
16943 
16944     union
16945     {
16946         __IOM uint32_t P1_QSEIS;       /*!< (@ 0x000025E8) Qci Stream Filter Error Interrupt Status (SDU
16947                                         *                  Oversize)                                                  */
16948 
16949         struct
16950         {
16951             __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
16952             uint32_t              : 24;
16953         } P1_QSEIS_b;
16954     };
16955 
16956     union
16957     {
16958         __IOM uint32_t P1_QSEIE;       /*!< (@ 0x000025EC) Qci Stream Filter Error Interrupt Enable                   */
16959 
16960         struct
16961         {
16962             __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
16963             uint32_t              : 24;
16964         } P1_QSEIE_b;
16965     };
16966 
16967     union
16968     {
16969         __OM uint32_t P1_QSEID;        /*!< (@ 0x000025F0) Qci Stream Filter Error Interrupt Disable                  */
16970 
16971         struct
16972         {
16973             __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
16974             uint32_t             : 24;
16975         } P1_QSEID_b;
16976     };
16977     __IM uint32_t RESERVED70[3];
16978 
16979     union
16980     {
16981         __IOM uint32_t P1_QGMOD;       /*!< (@ 0x00002600) Qci Gate Mode Register                                     */
16982 
16983         struct
16984         {
16985             __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
16986             uint32_t             : 24;
16987         } P1_QGMOD_b;
16988     };
16989 
16990     union
16991     {
16992         __IM uint32_t P1_QGPPC;        /*!< (@ 0x00002604) Qci Gate (All) Passed Packet Count Port 1                  */
16993 
16994         struct
16995         {
16996             __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
16997             uint32_t            : 16;
16998         } P1_QGPPC_b;
16999     };
17000 
17001     union
17002     {
17003         __IM uint32_t P1_QGDPC0;       /*!< (@ 0x00002608) Qci Gate 0 Dropped Packet Count Port n                     */
17004 
17005         struct
17006         {
17007             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17008             uint32_t            : 16;
17009         } P1_QGDPC0_b;
17010     };
17011     __IM uint32_t RESERVED71;
17012 
17013     union
17014     {
17015         __IM uint32_t P1_QGDPC1;       /*!< (@ 0x00002610) Qci Gate 1 Dropped Packet Count Port n                     */
17016 
17017         struct
17018         {
17019             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17020             uint32_t            : 16;
17021         } P1_QGDPC1_b;
17022     };
17023     __IM uint32_t RESERVED72;
17024 
17025     union
17026     {
17027         __IM uint32_t P1_QGDPC2;       /*!< (@ 0x00002618) Qci Gate 2 Dropped Packet Count Port n                     */
17028 
17029         struct
17030         {
17031             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17032             uint32_t            : 16;
17033         } P1_QGDPC2_b;
17034     };
17035     __IM uint32_t RESERVED73;
17036 
17037     union
17038     {
17039         __IM uint32_t P1_QGDPC3;       /*!< (@ 0x00002620) Qci Gate 3 Dropped Packet Count Port n                     */
17040 
17041         struct
17042         {
17043             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17044             uint32_t            : 16;
17045         } P1_QGDPC3_b;
17046     };
17047     __IM uint32_t RESERVED74;
17048 
17049     union
17050     {
17051         __IM uint32_t P1_QGDPC4;       /*!< (@ 0x00002628) Qci Gate 4 Dropped Packet Count Port n                     */
17052 
17053         struct
17054         {
17055             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17056             uint32_t            : 16;
17057         } P1_QGDPC4_b;
17058     };
17059     __IM uint32_t RESERVED75;
17060 
17061     union
17062     {
17063         __IM uint32_t P1_QGDPC5;       /*!< (@ 0x00002630) Qci Gate 5 Dropped Packet Count Port n                     */
17064 
17065         struct
17066         {
17067             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17068             uint32_t            : 16;
17069         } P1_QGDPC5_b;
17070     };
17071     __IM uint32_t RESERVED76;
17072 
17073     union
17074     {
17075         __IM uint32_t P1_QGDPC6;       /*!< (@ 0x00002638) Qci Gate 6 Dropped Packet Count Port n                     */
17076 
17077         struct
17078         {
17079             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17080             uint32_t            : 16;
17081         } P1_QGDPC6_b;
17082     };
17083     __IM uint32_t RESERVED77;
17084 
17085     union
17086     {
17087         __IM uint32_t P1_QGDPC7;       /*!< (@ 0x00002640) Qci Gate 7 Dropped Packet Count Port n                     */
17088 
17089         struct
17090         {
17091             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
17092             uint32_t            : 16;
17093         } P1_QGDPC7_b;
17094     };
17095 
17096     union
17097     {
17098         __IOM uint32_t P1_QGEIS;       /*!< (@ 0x00002644) Qci Gate Error Interrupt Status                            */
17099 
17100         struct
17101         {
17102             __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
17103             uint32_t              : 24;
17104         } P1_QGEIS_b;
17105     };
17106 
17107     union
17108     {
17109         __IOM uint32_t P1_QGEIE;       /*!< (@ 0x00002648) Qci Gate Error Interrupt Enable                            */
17110 
17111         struct
17112         {
17113             __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
17114             uint32_t              : 24;
17115         } P1_QGEIE_b;
17116     };
17117 
17118     union
17119     {
17120         __OM uint32_t P1_QGEID;        /*!< (@ 0x0000264C) Qci Gate Error Interrupt Disable                           */
17121 
17122         struct
17123         {
17124             __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
17125             uint32_t             : 24;
17126         } P1_QGEID_b;
17127     };
17128 
17129     union
17130     {
17131         __IOM uint32_t P1_QMDESC0;     /*!< (@ 0x00002650) Qci Port n Flow Meter 0 Descriptor Register                */
17132 
17133         struct
17134         {
17135             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17136             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17137             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17138             uint32_t           : 29;
17139         } P1_QMDESC0_b;
17140     };
17141 
17142     union
17143     {
17144         __IOM uint32_t P1_QMCBSC0;     /*!< (@ 0x00002654) Qci Meter CBS Configuration Port n, Meter 0                */
17145 
17146         struct
17147         {
17148             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17149             uint32_t           : 14;
17150         } P1_QMCBSC0_b;
17151     };
17152 
17153     union
17154     {
17155         __IOM uint32_t P1_QMCIRC0;     /*!< (@ 0x00002658) Qci Meter CIR Configuration n 0                            */
17156 
17157         struct
17158         {
17159             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17160             uint32_t           : 15;
17161         } P1_QMCIRC0_b;
17162     };
17163 
17164     union
17165     {
17166         __IM uint32_t P1_QMGPC0;       /*!< (@ 0x0000265C) Qci Meter Green Packet Count                               */
17167 
17168         struct
17169         {
17170             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17171             uint32_t            : 16;
17172         } P1_QMGPC0_b;
17173     };
17174 
17175     union
17176     {
17177         __IM uint32_t P1_QMRPC0;       /*!< (@ 0x00002660) Qci Meter Red Packet Count                                 */
17178 
17179         struct
17180         {
17181             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17182             uint32_t            : 16;
17183         } P1_QMRPC0_b;
17184     };
17185 
17186     union
17187     {
17188         __IOM uint32_t P1_QMDESC1;     /*!< (@ 0x00002664) Qci Port n Flow Meter 1 Descriptor Register                */
17189 
17190         struct
17191         {
17192             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17193             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17194             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17195             uint32_t           : 29;
17196         } P1_QMDESC1_b;
17197     };
17198 
17199     union
17200     {
17201         __IOM uint32_t P1_QMCBSC1;     /*!< (@ 0x00002668) Qci Meter CBS Configuration Port n, Meter 1                */
17202 
17203         struct
17204         {
17205             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17206             uint32_t           : 14;
17207         } P1_QMCBSC1_b;
17208     };
17209 
17210     union
17211     {
17212         __IOM uint32_t P1_QMCIRC1;     /*!< (@ 0x0000266C) Qci Meter CIR Configuration n 1                            */
17213 
17214         struct
17215         {
17216             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17217             uint32_t           : 15;
17218         } P1_QMCIRC1_b;
17219     };
17220 
17221     union
17222     {
17223         __IM uint32_t P1_QMGPC1;       /*!< (@ 0x00002670) Qci Meter Green Packet Count                               */
17224 
17225         struct
17226         {
17227             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17228             uint32_t            : 16;
17229         } P1_QMGPC1_b;
17230     };
17231 
17232     union
17233     {
17234         __IM uint32_t P1_QMRPC1;       /*!< (@ 0x00002674) Qci Meter Red Packet Count                                 */
17235 
17236         struct
17237         {
17238             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17239             uint32_t            : 16;
17240         } P1_QMRPC1_b;
17241     };
17242 
17243     union
17244     {
17245         __IOM uint32_t P1_QMDESC2;     /*!< (@ 0x00002678) Qci Port n Flow Meter 2 Descriptor Register                */
17246 
17247         struct
17248         {
17249             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17250             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17251             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17252             uint32_t           : 29;
17253         } P1_QMDESC2_b;
17254     };
17255 
17256     union
17257     {
17258         __IOM uint32_t P1_QMCBSC2;     /*!< (@ 0x0000267C) Qci Meter CBS Configuration Port n, Meter 2                */
17259 
17260         struct
17261         {
17262             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17263             uint32_t           : 14;
17264         } P1_QMCBSC2_b;
17265     };
17266 
17267     union
17268     {
17269         __IOM uint32_t P1_QMCIRC2;     /*!< (@ 0x00002680) Qci Meter CIR Configuration n 2                            */
17270 
17271         struct
17272         {
17273             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17274             uint32_t           : 15;
17275         } P1_QMCIRC2_b;
17276     };
17277 
17278     union
17279     {
17280         __IM uint32_t P1_QMGPC2;       /*!< (@ 0x00002684) Qci Meter Green Packet Count                               */
17281 
17282         struct
17283         {
17284             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17285             uint32_t            : 16;
17286         } P1_QMGPC2_b;
17287     };
17288 
17289     union
17290     {
17291         __IM uint32_t P1_QMRPC2;       /*!< (@ 0x00002688) Qci Meter Red Packet Count                                 */
17292 
17293         struct
17294         {
17295             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17296             uint32_t            : 16;
17297         } P1_QMRPC2_b;
17298     };
17299 
17300     union
17301     {
17302         __IOM uint32_t P1_QMDESC3;     /*!< (@ 0x0000268C) Qci Port n Flow Meter 3 Descriptor Register                */
17303 
17304         struct
17305         {
17306             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17307             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17308             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17309             uint32_t           : 29;
17310         } P1_QMDESC3_b;
17311     };
17312 
17313     union
17314     {
17315         __IOM uint32_t P1_QMCBSC3;     /*!< (@ 0x00002690) Qci Meter CBS Configuration Port n, Meter 3                */
17316 
17317         struct
17318         {
17319             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17320             uint32_t           : 14;
17321         } P1_QMCBSC3_b;
17322     };
17323 
17324     union
17325     {
17326         __IOM uint32_t P1_QMCIRC3;     /*!< (@ 0x00002694) Qci Meter CIR Configuration n 3                            */
17327 
17328         struct
17329         {
17330             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17331             uint32_t           : 15;
17332         } P1_QMCIRC3_b;
17333     };
17334 
17335     union
17336     {
17337         __IM uint32_t P1_QMGPC3;       /*!< (@ 0x00002698) Qci Meter Green Packet Count                               */
17338 
17339         struct
17340         {
17341             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17342             uint32_t            : 16;
17343         } P1_QMGPC3_b;
17344     };
17345 
17346     union
17347     {
17348         __IM uint32_t P1_QMRPC3;       /*!< (@ 0x0000269C) Qci Meter Red Packet Count                                 */
17349 
17350         struct
17351         {
17352             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17353             uint32_t            : 16;
17354         } P1_QMRPC3_b;
17355     };
17356 
17357     union
17358     {
17359         __IOM uint32_t P1_QMDESC4;     /*!< (@ 0x000026A0) Qci Port n Flow Meter 4 Descriptor Register                */
17360 
17361         struct
17362         {
17363             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17364             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17365             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17366             uint32_t           : 29;
17367         } P1_QMDESC4_b;
17368     };
17369 
17370     union
17371     {
17372         __IOM uint32_t P1_QMCBSC4;     /*!< (@ 0x000026A4) Qci Meter CBS Configuration Port n, Meter 4                */
17373 
17374         struct
17375         {
17376             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17377             uint32_t           : 14;
17378         } P1_QMCBSC4_b;
17379     };
17380 
17381     union
17382     {
17383         __IOM uint32_t P1_QMCIRC4;     /*!< (@ 0x000026A8) Qci Meter CIR Configuration n 4                            */
17384 
17385         struct
17386         {
17387             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17388             uint32_t           : 15;
17389         } P1_QMCIRC4_b;
17390     };
17391 
17392     union
17393     {
17394         __IM uint32_t P1_QMGPC4;       /*!< (@ 0x000026AC) Qci Meter Green Packet Count                               */
17395 
17396         struct
17397         {
17398             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17399             uint32_t            : 16;
17400         } P1_QMGPC4_b;
17401     };
17402 
17403     union
17404     {
17405         __IM uint32_t P1_QMRPC4;       /*!< (@ 0x000026B0) Qci Meter Red Packet Count                                 */
17406 
17407         struct
17408         {
17409             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17410             uint32_t            : 16;
17411         } P1_QMRPC4_b;
17412     };
17413 
17414     union
17415     {
17416         __IOM uint32_t P1_QMDESC5;     /*!< (@ 0x000026B4) Qci Port n Flow Meter 5 Descriptor Register                */
17417 
17418         struct
17419         {
17420             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17421             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17422             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17423             uint32_t           : 29;
17424         } P1_QMDESC5_b;
17425     };
17426 
17427     union
17428     {
17429         __IOM uint32_t P1_QMCBSC5;     /*!< (@ 0x000026B8) Qci Meter CBS Configuration Port n, Meter 5                */
17430 
17431         struct
17432         {
17433             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17434             uint32_t           : 14;
17435         } P1_QMCBSC5_b;
17436     };
17437 
17438     union
17439     {
17440         __IOM uint32_t P1_QMCIRC5;     /*!< (@ 0x000026BC) Qci Meter CIR Configuration n 5                            */
17441 
17442         struct
17443         {
17444             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17445             uint32_t           : 15;
17446         } P1_QMCIRC5_b;
17447     };
17448 
17449     union
17450     {
17451         __IM uint32_t P1_QMGPC5;       /*!< (@ 0x000026C0) Qci Meter Green Packet Count                               */
17452 
17453         struct
17454         {
17455             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17456             uint32_t            : 16;
17457         } P1_QMGPC5_b;
17458     };
17459 
17460     union
17461     {
17462         __IM uint32_t P1_QMRPC5;       /*!< (@ 0x000026C4) Qci Meter Red Packet Count                                 */
17463 
17464         struct
17465         {
17466             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17467             uint32_t            : 16;
17468         } P1_QMRPC5_b;
17469     };
17470 
17471     union
17472     {
17473         __IOM uint32_t P1_QMDESC6;     /*!< (@ 0x000026C8) Qci Port n Flow Meter 6 Descriptor Register                */
17474 
17475         struct
17476         {
17477             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17478             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17479             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17480             uint32_t           : 29;
17481         } P1_QMDESC6_b;
17482     };
17483 
17484     union
17485     {
17486         __IOM uint32_t P1_QMCBSC6;     /*!< (@ 0x000026CC) Qci Meter CBS Configuration Port n, Meter 6                */
17487 
17488         struct
17489         {
17490             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17491             uint32_t           : 14;
17492         } P1_QMCBSC6_b;
17493     };
17494 
17495     union
17496     {
17497         __IOM uint32_t P1_QMCIRC6;     /*!< (@ 0x000026D0) Qci Meter CIR Configuration n 6                            */
17498 
17499         struct
17500         {
17501             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17502             uint32_t           : 15;
17503         } P1_QMCIRC6_b;
17504     };
17505 
17506     union
17507     {
17508         __IM uint32_t P1_QMGPC6;       /*!< (@ 0x000026D4) Qci Meter Green Packet Count                               */
17509 
17510         struct
17511         {
17512             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17513             uint32_t            : 16;
17514         } P1_QMGPC6_b;
17515     };
17516 
17517     union
17518     {
17519         __IM uint32_t P1_QMRPC6;       /*!< (@ 0x000026D8) Qci Meter Red Packet Count                                 */
17520 
17521         struct
17522         {
17523             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17524             uint32_t            : 16;
17525         } P1_QMRPC6_b;
17526     };
17527 
17528     union
17529     {
17530         __IOM uint32_t P1_QMDESC7;     /*!< (@ 0x000026DC) Qci Port n Flow Meter 7 Descriptor Register                */
17531 
17532         struct
17533         {
17534             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
17535             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
17536             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
17537             uint32_t           : 29;
17538         } P1_QMDESC7_b;
17539     };
17540 
17541     union
17542     {
17543         __IOM uint32_t P1_QMCBSC7;     /*!< (@ 0x000026E0) Qci Meter CBS Configuration Port n, Meter 7                */
17544 
17545         struct
17546         {
17547             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
17548             uint32_t           : 14;
17549         } P1_QMCBSC7_b;
17550     };
17551 
17552     union
17553     {
17554         __IOM uint32_t P1_QMCIRC7;     /*!< (@ 0x000026E4) Qci Meter CIR Configuration n 7                            */
17555 
17556         struct
17557         {
17558             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
17559             uint32_t           : 15;
17560         } P1_QMCIRC7_b;
17561     };
17562 
17563     union
17564     {
17565         __IM uint32_t P1_QMGPC7;       /*!< (@ 0x000026E8) Qci Meter Green Packet Count                               */
17566 
17567         struct
17568         {
17569             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
17570             uint32_t            : 16;
17571         } P1_QMGPC7_b;
17572     };
17573 
17574     union
17575     {
17576         __IM uint32_t P1_QMRPC7;       /*!< (@ 0x000026EC) Qci Meter Red Packet Count                                 */
17577 
17578         struct
17579         {
17580             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
17581             uint32_t            : 16;
17582         } P1_QMRPC7_b;
17583     };
17584 
17585     union
17586     {
17587         __IOM uint32_t P1_QMEC;        /*!< (@ 0x000026F0) Qci Meter Enable Configuration                             */
17588 
17589         struct
17590         {
17591             __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
17592             uint32_t          : 24;
17593         } P1_QMEC_b;
17594     };
17595 
17596     union
17597     {
17598         __IOM uint32_t P1_QMEIS;       /*!< (@ 0x000026F4) Qci Meter Error Interrupt Status                           */
17599 
17600         struct
17601         {
17602             __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
17603             uint32_t             : 24;
17604         } P1_QMEIS_b;
17605     };
17606 
17607     union
17608     {
17609         __IOM uint32_t P1_QMEIE;       /*!< (@ 0x000026F8) Qci Meter Error Interrupt Enable                           */
17610 
17611         struct
17612         {
17613             __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
17614             uint32_t             : 24;
17615         } P1_QMEIE_b;
17616     };
17617 
17618     union
17619     {
17620         __OM uint32_t P1_QMEID;        /*!< (@ 0x000026FC) Qci Meter Error Interrupt Disable                          */
17621 
17622         struct
17623         {
17624             __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
17625             uint32_t            : 24;
17626         } P1_QMEID_b;
17627     };
17628 
17629     union
17630     {
17631         __IOM uint32_t P1_PCP_REMAP;       /*!< (@ 0x00002700) Port 1 VLAN Priority Code Point (PCP) Remap                */
17632 
17633         struct
17634         {
17635             __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
17636             __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
17637             __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
17638             __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
17639             __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
17640             __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
17641             __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
17642             __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
17643             uint32_t                  : 8;
17644         } P1_PCP_REMAP_b;
17645     };
17646 
17647     union
17648     {
17649         __IOM uint32_t P1_VLAN_TAG;    /*!< (@ 0x00002704) Port 1 VLAN TAG Information for Priority Regeneration      */
17650 
17651         struct
17652         {
17653             __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
17654             __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
17655             __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
17656             __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
17657         } P1_VLAN_TAG_b;
17658     };
17659 
17660     union
17661     {
17662         __IOM uint32_t P1_VLAN_MODE;   /*!< (@ 0x00002708) Port 1 VLAN Mode                                           */
17663 
17664         struct
17665         {
17666             __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
17667             __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
17668             uint32_t            : 28;
17669         } P1_VLAN_MODE_b;
17670     };
17671 
17672     union
17673     {
17674         __IM uint32_t P1_VIC_DROP_CNT;       /*!< (@ 0x0000270C) Port 1 VLAN Ingress Check Drop Frame Counter               */
17675 
17676         struct
17677         {
17678             __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
17679             uint32_t                   : 16;
17680         } P1_VIC_DROP_CNT_b;
17681     };
17682     __IM uint32_t RESERVED78[6];
17683 
17684     union
17685     {
17686         __IM uint32_t P1_LOOKUP_HIT_CNT;       /*!< (@ 0x00002728) Port 1 DST Address Lookup Hit Counter                      */
17687 
17688         struct
17689         {
17690             __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
17691             uint32_t                     : 8;
17692         } P1_LOOKUP_HIT_CNT_b;
17693     };
17694 
17695     union
17696     {
17697         __IOM uint32_t P1_ERROR_STATUS; /*!< (@ 0x0000272C) Port 1 Frame Parser Runtime Error Status                   */
17698 
17699         struct
17700         {
17701             __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
17702             __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
17703                                          *   parser                                                                    */
17704             __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
17705             __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
17706             __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
17707             uint32_t              : 27;
17708         } P1_ERROR_STATUS_b;
17709     };
17710 
17711     union
17712     {
17713         __IOM uint32_t P1_ERROR_MASK;   /*!< (@ 0x00002730) Port 1 Frame Parser Runtime Error Mask                     */
17714 
17715         struct
17716         {
17717             __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
17718             __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
17719             __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
17720             __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
17721             __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
17722             uint32_t               : 27;
17723         } P1_ERROR_MASK_b;
17724     };
17725     __IM uint32_t RESERVED79[51];
17726 
17727     union
17728     {
17729         __IOM uint32_t P2_QSTMACU0;    /*!< (@ 0x00002800) Qci Stream Filter Table MAC Address Upper Part             */
17730 
17731         struct
17732         {
17733             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
17734             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
17735             uint32_t            : 15;
17736         } P2_QSTMACU0_b;
17737     };
17738 
17739     union
17740     {
17741         __IOM uint32_t P2_QSTMACD0;    /*!< (@ 0x00002804) Qci Stream Filter Table MAC Address Downer Part            */
17742 
17743         struct
17744         {
17745             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
17746         } P2_QSTMACD0_b;
17747     };
17748 
17749     union
17750     {
17751         __IOM uint32_t P2_QSTMAMU0;    /*!< (@ 0x00002808) Qci Stream Filter Table MAC Address Mask Upper
17752                                         *                  Part                                                       */
17753 
17754         struct
17755         {
17756             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
17757             uint32_t             : 16;
17758         } P2_QSTMAMU0_b;
17759     };
17760 
17761     union
17762     {
17763         __IOM uint32_t P2_QSTMAMD0;    /*!< (@ 0x0000280C) Qci Stream Filter Table MAC Address Mask Downer
17764                                         *                  Part                                                       */
17765 
17766         struct
17767         {
17768             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
17769         } P2_QSTMAMD0_b;
17770     };
17771 
17772     union
17773     {
17774         __IOM uint32_t P2_QSFTVL0;      /*!< (@ 0x00002810) Qci Stream Filter Table VLAN                               */
17775 
17776         struct
17777         {
17778             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
17779             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
17780             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
17781             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
17782             uint32_t              : 14;
17783         } P2_QSFTVL0_b;
17784     };
17785 
17786     union
17787     {
17788         __IOM uint32_t P2_QSFTVLM0;      /*!< (@ 0x00002814) Qci Stream Filter Table VLAN Mask                          */
17789 
17790         struct
17791         {
17792             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
17793             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
17794             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
17795             uint32_t               : 16;
17796         } P2_QSFTVLM0_b;
17797     };
17798 
17799     union
17800     {
17801         __IOM uint32_t P2_QSFTBL0;     /*!< (@ 0x00002818) Qci Stream Filter Table SDU/Gate/Meter ID                  */
17802 
17803         struct
17804         {
17805             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
17806             uint32_t             : 3;
17807             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
17808             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
17809             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
17810             uint32_t             : 1;
17811             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
17812             uint32_t             : 3;
17813             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
17814             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
17815             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
17816             uint32_t             : 3;
17817         } P2_QSFTBL0_b;
17818     };
17819 
17820     union
17821     {
17822         __IM uint32_t P2_QSMFC0;       /*!< (@ 0x0000281C) Qci Stream Match Packet Count                              */
17823 
17824         struct
17825         {
17826             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
17827             uint32_t            : 16;
17828         } P2_QSMFC0_b;
17829     };
17830 
17831     union
17832     {
17833         __IM uint32_t P2_QMSPPC0;      /*!< (@ 0x00002820) Qci MSDU Passed Packet Count                               */
17834 
17835         struct
17836         {
17837             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
17838             uint32_t             : 16;
17839         } P2_QMSPPC0_b;
17840     };
17841 
17842     union
17843     {
17844         __IM uint32_t P2_QMSRPC0;      /*!< (@ 0x00002824) Qci MSDU Reject Packet Count                               */
17845 
17846         struct
17847         {
17848             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
17849             uint32_t             : 16;
17850         } P2_QMSRPC0_b;
17851     };
17852 
17853     union
17854     {
17855         __IOM uint32_t P2_QSTMACU1;    /*!< (@ 0x00002828) Qci Stream Filter Table MAC Address Upper Part             */
17856 
17857         struct
17858         {
17859             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
17860             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
17861             uint32_t            : 15;
17862         } P2_QSTMACU1_b;
17863     };
17864 
17865     union
17866     {
17867         __IOM uint32_t P2_QSTMACD1;    /*!< (@ 0x0000282C) Qci Stream Filter Table MAC Address Downer Part            */
17868 
17869         struct
17870         {
17871             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
17872         } P2_QSTMACD1_b;
17873     };
17874 
17875     union
17876     {
17877         __IOM uint32_t P2_QSTMAMU1;    /*!< (@ 0x00002830) Qci Stream Filter Table MAC Address Mask Upper
17878                                         *                  Part                                                       */
17879 
17880         struct
17881         {
17882             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
17883             uint32_t             : 16;
17884         } P2_QSTMAMU1_b;
17885     };
17886 
17887     union
17888     {
17889         __IOM uint32_t P2_QSTMAMD1;    /*!< (@ 0x00002834) Qci Stream Filter Table MAC Address Mask Downer
17890                                         *                  Part                                                       */
17891 
17892         struct
17893         {
17894             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
17895         } P2_QSTMAMD1_b;
17896     };
17897 
17898     union
17899     {
17900         __IOM uint32_t P2_QSFTVL1;      /*!< (@ 0x00002838) Qci Stream Filter Table VLAN                               */
17901 
17902         struct
17903         {
17904             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
17905             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
17906             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
17907             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
17908             uint32_t              : 14;
17909         } P2_QSFTVL1_b;
17910     };
17911 
17912     union
17913     {
17914         __IOM uint32_t P2_QSFTVLM1;      /*!< (@ 0x0000283C) Qci Stream Filter Table VLAN Mask                          */
17915 
17916         struct
17917         {
17918             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
17919             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
17920             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
17921             uint32_t               : 16;
17922         } P2_QSFTVLM1_b;
17923     };
17924 
17925     union
17926     {
17927         __IOM uint32_t P2_QSFTBL1;     /*!< (@ 0x00002840) Qci Stream Filter Table SDU/Gate/Meter ID                  */
17928 
17929         struct
17930         {
17931             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
17932             uint32_t             : 3;
17933             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
17934             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
17935             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
17936             uint32_t             : 1;
17937             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
17938             uint32_t             : 3;
17939             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
17940             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
17941             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
17942             uint32_t             : 3;
17943         } P2_QSFTBL1_b;
17944     };
17945 
17946     union
17947     {
17948         __IM uint32_t P2_QSMFC1;       /*!< (@ 0x00002844) Qci Stream Match Packet Count                              */
17949 
17950         struct
17951         {
17952             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
17953             uint32_t            : 16;
17954         } P2_QSMFC1_b;
17955     };
17956 
17957     union
17958     {
17959         __IM uint32_t P2_QMSPPC1;      /*!< (@ 0x00002848) Qci MSDU Passed Packet Count                               */
17960 
17961         struct
17962         {
17963             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
17964             uint32_t             : 16;
17965         } P2_QMSPPC1_b;
17966     };
17967 
17968     union
17969     {
17970         __IM uint32_t P2_QMSRPC1;      /*!< (@ 0x0000284C) Qci MSDU Reject Packet Count                               */
17971 
17972         struct
17973         {
17974             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
17975             uint32_t             : 16;
17976         } P2_QMSRPC1_b;
17977     };
17978 
17979     union
17980     {
17981         __IOM uint32_t P2_QSTMACU2;    /*!< (@ 0x00002850) Qci Stream Filter Table MAC Address Upper Part             */
17982 
17983         struct
17984         {
17985             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
17986             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
17987             uint32_t            : 15;
17988         } P2_QSTMACU2_b;
17989     };
17990 
17991     union
17992     {
17993         __IOM uint32_t P2_QSTMACD2;    /*!< (@ 0x00002854) Qci Stream Filter Table MAC Address Downer Part            */
17994 
17995         struct
17996         {
17997             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
17998         } P2_QSTMACD2_b;
17999     };
18000 
18001     union
18002     {
18003         __IOM uint32_t P2_QSTMAMU2;    /*!< (@ 0x00002858) Qci Stream Filter Table MAC Address Mask Upper
18004                                         *                  Part                                                       */
18005 
18006         struct
18007         {
18008             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
18009             uint32_t             : 16;
18010         } P2_QSTMAMU2_b;
18011     };
18012 
18013     union
18014     {
18015         __IOM uint32_t P2_QSTMAMD2;    /*!< (@ 0x0000285C) Qci Stream Filter Table MAC Address Mask Downer
18016                                         *                  Part                                                       */
18017 
18018         struct
18019         {
18020             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
18021         } P2_QSTMAMD2_b;
18022     };
18023 
18024     union
18025     {
18026         __IOM uint32_t P2_QSFTVL2;      /*!< (@ 0x00002860) Qci Stream Filter Table VLAN                               */
18027 
18028         struct
18029         {
18030             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
18031             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
18032             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
18033             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
18034             uint32_t              : 14;
18035         } P2_QSFTVL2_b;
18036     };
18037 
18038     union
18039     {
18040         __IOM uint32_t P2_QSFTVLM2;      /*!< (@ 0x00002864) Qci Stream Filter Table VLAN Mask                          */
18041 
18042         struct
18043         {
18044             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
18045             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
18046             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
18047             uint32_t               : 16;
18048         } P2_QSFTVLM2_b;
18049     };
18050 
18051     union
18052     {
18053         __IOM uint32_t P2_QSFTBL2;     /*!< (@ 0x00002868) Qci Stream Filter Table SDU/Gate/Meter ID                  */
18054 
18055         struct
18056         {
18057             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
18058             uint32_t             : 3;
18059             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
18060             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
18061             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
18062             uint32_t             : 1;
18063             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
18064             uint32_t             : 3;
18065             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
18066             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
18067             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
18068             uint32_t             : 3;
18069         } P2_QSFTBL2_b;
18070     };
18071 
18072     union
18073     {
18074         __IM uint32_t P2_QSMFC2;       /*!< (@ 0x0000286C) Qci Stream Match Packet Count                              */
18075 
18076         struct
18077         {
18078             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
18079             uint32_t            : 16;
18080         } P2_QSMFC2_b;
18081     };
18082 
18083     union
18084     {
18085         __IM uint32_t P2_QMSPPC2;      /*!< (@ 0x00002870) Qci MSDU Passed Packet Count                               */
18086 
18087         struct
18088         {
18089             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
18090             uint32_t             : 16;
18091         } P2_QMSPPC2_b;
18092     };
18093 
18094     union
18095     {
18096         __IM uint32_t P2_QMSRPC2;      /*!< (@ 0x00002874) Qci MSDU Reject Packet Count                               */
18097 
18098         struct
18099         {
18100             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
18101             uint32_t             : 16;
18102         } P2_QMSRPC2_b;
18103     };
18104 
18105     union
18106     {
18107         __IOM uint32_t P2_QSTMACU3;    /*!< (@ 0x00002878) Qci Stream Filter Table MAC Address Upper Part             */
18108 
18109         struct
18110         {
18111             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
18112             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
18113             uint32_t            : 15;
18114         } P2_QSTMACU3_b;
18115     };
18116 
18117     union
18118     {
18119         __IOM uint32_t P2_QSTMACD3;    /*!< (@ 0x0000287C) Qci Stream Filter Table MAC Address Downer Part            */
18120 
18121         struct
18122         {
18123             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
18124         } P2_QSTMACD3_b;
18125     };
18126 
18127     union
18128     {
18129         __IOM uint32_t P2_QSTMAMU3;    /*!< (@ 0x00002880) Qci Stream Filter Table MAC Address Mask Upper
18130                                         *                  Part                                                       */
18131 
18132         struct
18133         {
18134             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
18135             uint32_t             : 16;
18136         } P2_QSTMAMU3_b;
18137     };
18138 
18139     union
18140     {
18141         __IOM uint32_t P2_QSTMAMD3;    /*!< (@ 0x00002884) Qci Stream Filter Table MAC Address Mask Downer
18142                                         *                  Part                                                       */
18143 
18144         struct
18145         {
18146             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
18147         } P2_QSTMAMD3_b;
18148     };
18149 
18150     union
18151     {
18152         __IOM uint32_t P2_QSFTVL3;      /*!< (@ 0x00002888) Qci Stream Filter Table VLAN                               */
18153 
18154         struct
18155         {
18156             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
18157             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
18158             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
18159             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
18160             uint32_t              : 14;
18161         } P2_QSFTVL3_b;
18162     };
18163 
18164     union
18165     {
18166         __IOM uint32_t P2_QSFTVLM3;      /*!< (@ 0x0000288C) Qci Stream Filter Table VLAN Mask                          */
18167 
18168         struct
18169         {
18170             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
18171             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
18172             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
18173             uint32_t               : 16;
18174         } P2_QSFTVLM3_b;
18175     };
18176 
18177     union
18178     {
18179         __IOM uint32_t P2_QSFTBL3;     /*!< (@ 0x00002890) Qci Stream Filter Table SDU/Gate/Meter ID                  */
18180 
18181         struct
18182         {
18183             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
18184             uint32_t             : 3;
18185             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
18186             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
18187             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
18188             uint32_t             : 1;
18189             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
18190             uint32_t             : 3;
18191             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
18192             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
18193             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
18194             uint32_t             : 3;
18195         } P2_QSFTBL3_b;
18196     };
18197 
18198     union
18199     {
18200         __IM uint32_t P2_QSMFC3;       /*!< (@ 0x00002894) Qci Stream Match Packet Count                              */
18201 
18202         struct
18203         {
18204             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
18205             uint32_t            : 16;
18206         } P2_QSMFC3_b;
18207     };
18208 
18209     union
18210     {
18211         __IM uint32_t P2_QMSPPC3;      /*!< (@ 0x00002898) Qci MSDU Passed Packet Count                               */
18212 
18213         struct
18214         {
18215             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
18216             uint32_t             : 16;
18217         } P2_QMSPPC3_b;
18218     };
18219 
18220     union
18221     {
18222         __IM uint32_t P2_QMSRPC3;      /*!< (@ 0x0000289C) Qci MSDU Reject Packet Count                               */
18223 
18224         struct
18225         {
18226             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
18227             uint32_t             : 16;
18228         } P2_QMSRPC3_b;
18229     };
18230 
18231     union
18232     {
18233         __IOM uint32_t P2_QSTMACU4;    /*!< (@ 0x000028A0) Qci Stream Filter Table MAC Address Upper Part             */
18234 
18235         struct
18236         {
18237             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
18238             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
18239             uint32_t            : 15;
18240         } P2_QSTMACU4_b;
18241     };
18242 
18243     union
18244     {
18245         __IOM uint32_t P2_QSTMACD4;    /*!< (@ 0x000028A4) Qci Stream Filter Table MAC Address Downer Part            */
18246 
18247         struct
18248         {
18249             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
18250         } P2_QSTMACD4_b;
18251     };
18252 
18253     union
18254     {
18255         __IOM uint32_t P2_QSTMAMU4;    /*!< (@ 0x000028A8) Qci Stream Filter Table MAC Address Mask Upper
18256                                         *                  Part                                                       */
18257 
18258         struct
18259         {
18260             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
18261             uint32_t             : 16;
18262         } P2_QSTMAMU4_b;
18263     };
18264 
18265     union
18266     {
18267         __IOM uint32_t P2_QSTMAMD4;    /*!< (@ 0x000028AC) Qci Stream Filter Table MAC Address Mask Downer
18268                                         *                  Part                                                       */
18269 
18270         struct
18271         {
18272             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
18273         } P2_QSTMAMD4_b;
18274     };
18275 
18276     union
18277     {
18278         __IOM uint32_t P2_QSFTVL4;      /*!< (@ 0x000028B0) Qci Stream Filter Table VLAN                               */
18279 
18280         struct
18281         {
18282             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
18283             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
18284             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
18285             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
18286             uint32_t              : 14;
18287         } P2_QSFTVL4_b;
18288     };
18289 
18290     union
18291     {
18292         __IOM uint32_t P2_QSFTVLM4;      /*!< (@ 0x000028B4) Qci Stream Filter Table VLAN Mask                          */
18293 
18294         struct
18295         {
18296             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
18297             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
18298             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
18299             uint32_t               : 16;
18300         } P2_QSFTVLM4_b;
18301     };
18302 
18303     union
18304     {
18305         __IOM uint32_t P2_QSFTBL4;     /*!< (@ 0x000028B8) Qci Stream Filter Table SDU/Gate/Meter ID                  */
18306 
18307         struct
18308         {
18309             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
18310             uint32_t             : 3;
18311             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
18312             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
18313             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
18314             uint32_t             : 1;
18315             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
18316             uint32_t             : 3;
18317             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
18318             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
18319             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
18320             uint32_t             : 3;
18321         } P2_QSFTBL4_b;
18322     };
18323 
18324     union
18325     {
18326         __IM uint32_t P2_QSMFC4;       /*!< (@ 0x000028BC) Qci Stream Match Packet Count                              */
18327 
18328         struct
18329         {
18330             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
18331             uint32_t            : 16;
18332         } P2_QSMFC4_b;
18333     };
18334 
18335     union
18336     {
18337         __IM uint32_t P2_QMSPPC4;      /*!< (@ 0x000028C0) Qci MSDU Passed Packet Count                               */
18338 
18339         struct
18340         {
18341             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
18342             uint32_t             : 16;
18343         } P2_QMSPPC4_b;
18344     };
18345 
18346     union
18347     {
18348         __IM uint32_t P2_QMSRPC4;      /*!< (@ 0x000028C4) Qci MSDU Reject Packet Count                               */
18349 
18350         struct
18351         {
18352             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
18353             uint32_t             : 16;
18354         } P2_QMSRPC4_b;
18355     };
18356 
18357     union
18358     {
18359         __IOM uint32_t P2_QSTMACU5;    /*!< (@ 0x000028C8) Qci Stream Filter Table MAC Address Upper Part             */
18360 
18361         struct
18362         {
18363             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
18364             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
18365             uint32_t            : 15;
18366         } P2_QSTMACU5_b;
18367     };
18368 
18369     union
18370     {
18371         __IOM uint32_t P2_QSTMACD5;    /*!< (@ 0x000028CC) Qci Stream Filter Table MAC Address Downer Part            */
18372 
18373         struct
18374         {
18375             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
18376         } P2_QSTMACD5_b;
18377     };
18378 
18379     union
18380     {
18381         __IOM uint32_t P2_QSTMAMU5;    /*!< (@ 0x000028D0) Qci Stream Filter Table MAC Address Mask Upper
18382                                         *                  Part                                                       */
18383 
18384         struct
18385         {
18386             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
18387             uint32_t             : 16;
18388         } P2_QSTMAMU5_b;
18389     };
18390 
18391     union
18392     {
18393         __IOM uint32_t P2_QSTMAMD5;    /*!< (@ 0x000028D4) Qci Stream Filter Table MAC Address Mask Downer
18394                                         *                  Part                                                       */
18395 
18396         struct
18397         {
18398             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
18399         } P2_QSTMAMD5_b;
18400     };
18401 
18402     union
18403     {
18404         __IOM uint32_t P2_QSFTVL5;      /*!< (@ 0x000028D8) Qci Stream Filter Table VLAN                               */
18405 
18406         struct
18407         {
18408             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
18409             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
18410             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
18411             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
18412             uint32_t              : 14;
18413         } P2_QSFTVL5_b;
18414     };
18415 
18416     union
18417     {
18418         __IOM uint32_t P2_QSFTVLM5;      /*!< (@ 0x000028DC) Qci Stream Filter Table VLAN Mask                          */
18419 
18420         struct
18421         {
18422             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
18423             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
18424             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
18425             uint32_t               : 16;
18426         } P2_QSFTVLM5_b;
18427     };
18428 
18429     union
18430     {
18431         __IOM uint32_t P2_QSFTBL5;     /*!< (@ 0x000028E0) Qci Stream Filter Table SDU/Gate/Meter ID                  */
18432 
18433         struct
18434         {
18435             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
18436             uint32_t             : 3;
18437             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
18438             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
18439             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
18440             uint32_t             : 1;
18441             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
18442             uint32_t             : 3;
18443             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
18444             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
18445             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
18446             uint32_t             : 3;
18447         } P2_QSFTBL5_b;
18448     };
18449 
18450     union
18451     {
18452         __IM uint32_t P2_QSMFC5;       /*!< (@ 0x000028E4) Qci Stream Match Packet Count                              */
18453 
18454         struct
18455         {
18456             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
18457             uint32_t            : 16;
18458         } P2_QSMFC5_b;
18459     };
18460 
18461     union
18462     {
18463         __IM uint32_t P2_QMSPPC5;      /*!< (@ 0x000028E8) Qci MSDU Passed Packet Count                               */
18464 
18465         struct
18466         {
18467             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
18468             uint32_t             : 16;
18469         } P2_QMSPPC5_b;
18470     };
18471 
18472     union
18473     {
18474         __IM uint32_t P2_QMSRPC5;      /*!< (@ 0x000028EC) Qci MSDU Reject Packet Count                               */
18475 
18476         struct
18477         {
18478             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
18479             uint32_t             : 16;
18480         } P2_QMSRPC5_b;
18481     };
18482 
18483     union
18484     {
18485         __IOM uint32_t P2_QSTMACU6;    /*!< (@ 0x000028F0) Qci Stream Filter Table MAC Address Upper Part             */
18486 
18487         struct
18488         {
18489             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
18490             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
18491             uint32_t            : 15;
18492         } P2_QSTMACU6_b;
18493     };
18494 
18495     union
18496     {
18497         __IOM uint32_t P2_QSTMACD6;    /*!< (@ 0x000028F4) Qci Stream Filter Table MAC Address Downer Part            */
18498 
18499         struct
18500         {
18501             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
18502         } P2_QSTMACD6_b;
18503     };
18504 
18505     union
18506     {
18507         __IOM uint32_t P2_QSTMAMU6;    /*!< (@ 0x000028F8) Qci Stream Filter Table MAC Address Mask Upper
18508                                         *                  Part                                                       */
18509 
18510         struct
18511         {
18512             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
18513             uint32_t             : 16;
18514         } P2_QSTMAMU6_b;
18515     };
18516 
18517     union
18518     {
18519         __IOM uint32_t P2_QSTMAMD6;    /*!< (@ 0x000028FC) Qci Stream Filter Table MAC Address Mask Downer
18520                                         *                  Part                                                       */
18521 
18522         struct
18523         {
18524             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
18525         } P2_QSTMAMD6_b;
18526     };
18527 
18528     union
18529     {
18530         __IOM uint32_t P2_QSFTVL6;      /*!< (@ 0x00002900) Qci Stream Filter Table VLAN                               */
18531 
18532         struct
18533         {
18534             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
18535             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
18536             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
18537             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
18538             uint32_t              : 14;
18539         } P2_QSFTVL6_b;
18540     };
18541 
18542     union
18543     {
18544         __IOM uint32_t P2_QSFTVLM6;      /*!< (@ 0x00002904) Qci Stream Filter Table VLAN Mask                          */
18545 
18546         struct
18547         {
18548             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
18549             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
18550             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
18551             uint32_t               : 16;
18552         } P2_QSFTVLM6_b;
18553     };
18554 
18555     union
18556     {
18557         __IOM uint32_t P2_QSFTBL6;     /*!< (@ 0x00002908) Qci Stream Filter Table SDU/Gate/Meter ID                  */
18558 
18559         struct
18560         {
18561             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
18562             uint32_t             : 3;
18563             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
18564             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
18565             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
18566             uint32_t             : 1;
18567             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
18568             uint32_t             : 3;
18569             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
18570             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
18571             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
18572             uint32_t             : 3;
18573         } P2_QSFTBL6_b;
18574     };
18575 
18576     union
18577     {
18578         __IM uint32_t P2_QSMFC6;       /*!< (@ 0x0000290C) Qci Stream Match Packet Count                              */
18579 
18580         struct
18581         {
18582             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
18583             uint32_t            : 16;
18584         } P2_QSMFC6_b;
18585     };
18586 
18587     union
18588     {
18589         __IM uint32_t P2_QMSPPC6;      /*!< (@ 0x00002910) Qci MSDU Passed Packet Count                               */
18590 
18591         struct
18592         {
18593             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
18594             uint32_t             : 16;
18595         } P2_QMSPPC6_b;
18596     };
18597 
18598     union
18599     {
18600         __IM uint32_t P2_QMSRPC6;      /*!< (@ 0x00002914) Qci MSDU Reject Packet Count                               */
18601 
18602         struct
18603         {
18604             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
18605             uint32_t             : 16;
18606         } P2_QMSRPC6_b;
18607     };
18608 
18609     union
18610     {
18611         __IOM uint32_t P2_QSTMACU7;    /*!< (@ 0x00002918) Qci Stream Filter Table MAC Address Upper Part             */
18612 
18613         struct
18614         {
18615             __IOM uint32_t MACA : 16;  /*!< [15..0] Qci stream filter table MAC address[47:32]                        */
18616             __IOM uint32_t DASA : 1;   /*!< [16..16] MAC address (MACA) select                                        */
18617             uint32_t            : 15;
18618         } P2_QSTMACU7_b;
18619     };
18620 
18621     union
18622     {
18623         __IOM uint32_t P2_QSTMACD7;    /*!< (@ 0x0000291C) Qci Stream Filter Table MAC Address Downer Part            */
18624 
18625         struct
18626         {
18627             __IOM uint32_t MACA : 32;  /*!< [31..0] Qci stream filter table MAC address[31:0]                         */
18628         } P2_QSTMACD7_b;
18629     };
18630 
18631     union
18632     {
18633         __IOM uint32_t P2_QSTMAMU7;    /*!< (@ 0x00002920) Qci Stream Filter Table MAC Address Mask Upper
18634                                         *                  Part                                                       */
18635 
18636         struct
18637         {
18638             __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32]               */
18639             uint32_t             : 16;
18640         } P2_QSTMAMU7_b;
18641     };
18642 
18643     union
18644     {
18645         __IOM uint32_t P2_QSTMAMD7;    /*!< (@ 0x00002924) Qci Stream Filter Table MAC Address Mask Downer
18646                                         *                  Part                                                       */
18647 
18648         struct
18649         {
18650             __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0]                */
18651         } P2_QSTMAMD7_b;
18652     };
18653 
18654     union
18655     {
18656         __IOM uint32_t P2_QSFTVL7;      /*!< (@ 0x00002928) Qci Stream Filter Table VLAN                               */
18657 
18658         struct
18659         {
18660             __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID                                                            */
18661             __IOM uint32_t DEI    : 1;  /*!< [12..12] DEI                                                              */
18662             __IOM uint32_t PCP    : 3;  /*!< [15..13] PCP                                                              */
18663             __IOM uint32_t TAGMD  : 2;  /*!< [17..16] TAGMD                                                            */
18664             uint32_t              : 14;
18665         } P2_QSFTVL7_b;
18666     };
18667 
18668     union
18669     {
18670         __IOM uint32_t P2_QSFTVLM7;      /*!< (@ 0x0000292C) Qci Stream Filter Table VLAN Mask                          */
18671 
18672         struct
18673         {
18674             __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask                    */
18675             __IOM uint32_t DEIM    : 1;  /*!< [12..12] DEIM                                                             */
18676             __IOM uint32_t PCPM    : 3;  /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask                   */
18677             uint32_t               : 16;
18678         } P2_QSFTVLM7_b;
18679     };
18680 
18681     union
18682     {
18683         __IOM uint32_t P2_QSFTBL7;     /*!< (@ 0x00002930) Qci Stream Filter Table SDU/Gate/Meter ID                  */
18684 
18685         struct
18686         {
18687             __IOM uint32_t QSTE  : 1;  /*!< [0..0] QSTE                                                               */
18688             uint32_t             : 3;
18689             __IOM uint32_t GAID  : 3;  /*!< [6..4] GAID                                                               */
18690             __IOM uint32_t GAIDV : 1;  /*!< [7..7] GAIDV                                                              */
18691             __IOM uint32_t MEID  : 3;  /*!< [10..8] MEID                                                              */
18692             uint32_t             : 1;
18693             __IOM uint32_t MEIDV : 1;  /*!< [12..12] MEIDV                                                            */
18694             uint32_t             : 3;
18695             __IOM uint32_t MSDU  : 11; /*!< [26..16] Qci stream filter table max SDU size                             */
18696             __IOM uint32_t MSDUE : 1;  /*!< [27..27] MSDUE                                                            */
18697             __IOM uint32_t QSMSM : 1;  /*!< [28..28] Qci stream MSDU mode                                             */
18698             uint32_t             : 3;
18699         } P2_QSFTBL7_b;
18700     };
18701 
18702     union
18703     {
18704         __IM uint32_t P2_QSMFC7;       /*!< (@ 0x00002934) Qci Stream Match Packet Count                              */
18705 
18706         struct
18707         {
18708             __IM uint32_t QSMFC : 16;  /*!< [15..0] Qci stream match packet count                                     */
18709             uint32_t            : 16;
18710         } P2_QSMFC7_b;
18711     };
18712 
18713     union
18714     {
18715         __IM uint32_t P2_QMSPPC7;      /*!< (@ 0x00002938) Qci MSDU Passed Packet Count                               */
18716 
18717         struct
18718         {
18719             __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count                                      */
18720             uint32_t             : 16;
18721         } P2_QMSPPC7_b;
18722     };
18723 
18724     union
18725     {
18726         __IM uint32_t P2_QMSRPC7;      /*!< (@ 0x0000293C) Qci MSDU Reject Packet Count                               */
18727 
18728         struct
18729         {
18730             __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count                                    */
18731             uint32_t             : 16;
18732         } P2_QMSRPC7_b;
18733     };
18734     __IM uint32_t RESERVED80[42];
18735 
18736     union
18737     {
18738         __IOM uint32_t P2_QSEIS;       /*!< (@ 0x000029E8) Qci Stream Filter Error Interrupt Status (SDU
18739                                         *                  Oversize)                                                  */
18740 
18741         struct
18742         {
18743             __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s]                           */
18744             uint32_t              : 24;
18745         } P2_QSEIS_b;
18746     };
18747 
18748     union
18749     {
18750         __IOM uint32_t P2_QSEIE;       /*!< (@ 0x000029EC) Qci Stream Filter Error Interrupt Enable                   */
18751 
18752         struct
18753         {
18754             __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s]                           */
18755             uint32_t              : 24;
18756         } P2_QSEIE_b;
18757     };
18758 
18759     union
18760     {
18761         __OM uint32_t P2_QSEID;        /*!< (@ 0x000029F0) Qci Stream Filter Error Interrupt Disable                  */
18762 
18763         struct
18764         {
18765             __OM uint32_t QSMOID : 8;  /*!< [7..0] MSDU oversize frames Interrupt Disable[s]                          */
18766             uint32_t             : 24;
18767         } P2_QSEID_b;
18768     };
18769     __IM uint32_t RESERVED81[3];
18770 
18771     union
18772     {
18773         __IOM uint32_t P2_QGMOD;       /*!< (@ 0x00002A00) Qci Gate Mode Register                                     */
18774 
18775         struct
18776         {
18777             __IOM uint32_t QGMOD : 8;  /*!< [7..0] Flow gate mode[g]                                                  */
18778             uint32_t             : 24;
18779         } P2_QGMOD_b;
18780     };
18781 
18782     union
18783     {
18784         __IM uint32_t P2_QGPPC;        /*!< (@ 0x00002A04) Qci Gate (All) Passed Packet Count Port 2                  */
18785 
18786         struct
18787         {
18788             __IM uint32_t QGPPC : 16;  /*!< [15..0] Qci gate passed packet count                                      */
18789             uint32_t            : 16;
18790         } P2_QGPPC_b;
18791     };
18792 
18793     union
18794     {
18795         __IM uint32_t P2_QGDPC0;       /*!< (@ 0x00002A08) Qci Gate 0 Dropped Packet Count Port n                     */
18796 
18797         struct
18798         {
18799             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18800             uint32_t            : 16;
18801         } P2_QGDPC0_b;
18802     };
18803     __IM uint32_t RESERVED82;
18804 
18805     union
18806     {
18807         __IM uint32_t P2_QGDPC1;       /*!< (@ 0x00002A10) Qci Gate 1 Dropped Packet Count Port n                     */
18808 
18809         struct
18810         {
18811             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18812             uint32_t            : 16;
18813         } P2_QGDPC1_b;
18814     };
18815     __IM uint32_t RESERVED83;
18816 
18817     union
18818     {
18819         __IM uint32_t P2_QGDPC2;       /*!< (@ 0x00002A18) Qci Gate 2 Dropped Packet Count Port n                     */
18820 
18821         struct
18822         {
18823             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18824             uint32_t            : 16;
18825         } P2_QGDPC2_b;
18826     };
18827     __IM uint32_t RESERVED84;
18828 
18829     union
18830     {
18831         __IM uint32_t P2_QGDPC3;       /*!< (@ 0x00002A20) Qci Gate 3 Dropped Packet Count Port n                     */
18832 
18833         struct
18834         {
18835             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18836             uint32_t            : 16;
18837         } P2_QGDPC3_b;
18838     };
18839     __IM uint32_t RESERVED85;
18840 
18841     union
18842     {
18843         __IM uint32_t P2_QGDPC4;       /*!< (@ 0x00002A28) Qci Gate 4 Dropped Packet Count Port n                     */
18844 
18845         struct
18846         {
18847             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18848             uint32_t            : 16;
18849         } P2_QGDPC4_b;
18850     };
18851     __IM uint32_t RESERVED86;
18852 
18853     union
18854     {
18855         __IM uint32_t P2_QGDPC5;       /*!< (@ 0x00002A30) Qci Gate 5 Dropped Packet Count Port n                     */
18856 
18857         struct
18858         {
18859             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18860             uint32_t            : 16;
18861         } P2_QGDPC5_b;
18862     };
18863     __IM uint32_t RESERVED87;
18864 
18865     union
18866     {
18867         __IM uint32_t P2_QGDPC6;       /*!< (@ 0x00002A38) Qci Gate 6 Dropped Packet Count Port n                     */
18868 
18869         struct
18870         {
18871             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18872             uint32_t            : 16;
18873         } P2_QGDPC6_b;
18874     };
18875     __IM uint32_t RESERVED88;
18876 
18877     union
18878     {
18879         __IM uint32_t P2_QGDPC7;       /*!< (@ 0x00002A40) Qci Gate 7 Dropped Packet Count Port n                     */
18880 
18881         struct
18882         {
18883             __IM uint32_t QGDPC : 16;  /*!< [15..0] Qci gate dropped packet count                                     */
18884             uint32_t            : 16;
18885         } P2_QGDPC7_b;
18886     };
18887 
18888     union
18889     {
18890         __IOM uint32_t P2_QGEIS;       /*!< (@ 0x00002A44) Qci Gate Error Interrupt Status                            */
18891 
18892         struct
18893         {
18894             __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g]                                   */
18895             uint32_t              : 24;
18896         } P2_QGEIS_b;
18897     };
18898 
18899     union
18900     {
18901         __IOM uint32_t P2_QGEIE;       /*!< (@ 0x00002A48) Qci Gate Error Interrupt Enable                            */
18902 
18903         struct
18904         {
18905             __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g]                                   */
18906             uint32_t              : 24;
18907         } P2_QGEIE_b;
18908     };
18909 
18910     union
18911     {
18912         __OM uint32_t P2_QGEID;        /*!< (@ 0x00002A4C) Qci Gate Error Interrupt Disable                           */
18913 
18914         struct
18915         {
18916             __OM uint32_t QGMOID : 8;  /*!< [7..0] Gating error Interrupt Disable[g]                                  */
18917             uint32_t             : 24;
18918         } P2_QGEID_b;
18919     };
18920 
18921     union
18922     {
18923         __IOM uint32_t P2_QMDESC0;     /*!< (@ 0x00002A50) Qci Port n Flow Meter 0 Descriptor Register                */
18924 
18925         struct
18926         {
18927             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
18928             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
18929             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
18930             uint32_t           : 29;
18931         } P2_QMDESC0_b;
18932     };
18933 
18934     union
18935     {
18936         __IOM uint32_t P2_QMCBSC0;     /*!< (@ 0x00002A54) Qci Meter CBS Configuration Port n, Meter 0                */
18937 
18938         struct
18939         {
18940             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
18941             uint32_t           : 14;
18942         } P2_QMCBSC0_b;
18943     };
18944 
18945     union
18946     {
18947         __IOM uint32_t P2_QMCIRC0;     /*!< (@ 0x00002A58) Qci Meter CIR Configuration n 0                            */
18948 
18949         struct
18950         {
18951             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
18952             uint32_t           : 15;
18953         } P2_QMCIRC0_b;
18954     };
18955 
18956     union
18957     {
18958         __IM uint32_t P2_QMGPC0;       /*!< (@ 0x00002A5C) Qci Meter Green Packet Count                               */
18959 
18960         struct
18961         {
18962             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
18963             uint32_t            : 16;
18964         } P2_QMGPC0_b;
18965     };
18966 
18967     union
18968     {
18969         __IM uint32_t P2_QMRPC0;       /*!< (@ 0x00002A60) Qci Meter Red Packet Count                                 */
18970 
18971         struct
18972         {
18973             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
18974             uint32_t            : 16;
18975         } P2_QMRPC0_b;
18976     };
18977 
18978     union
18979     {
18980         __IOM uint32_t P2_QMDESC1;     /*!< (@ 0x00002A64) Qci Port n Flow Meter 1 Descriptor Register                */
18981 
18982         struct
18983         {
18984             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
18985             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
18986             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
18987             uint32_t           : 29;
18988         } P2_QMDESC1_b;
18989     };
18990 
18991     union
18992     {
18993         __IOM uint32_t P2_QMCBSC1;     /*!< (@ 0x00002A68) Qci Meter CBS Configuration Port n, Meter 1                */
18994 
18995         struct
18996         {
18997             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
18998             uint32_t           : 14;
18999         } P2_QMCBSC1_b;
19000     };
19001 
19002     union
19003     {
19004         __IOM uint32_t P2_QMCIRC1;     /*!< (@ 0x00002A6C) Qci Meter CIR Configuration n 1                            */
19005 
19006         struct
19007         {
19008             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
19009             uint32_t           : 15;
19010         } P2_QMCIRC1_b;
19011     };
19012 
19013     union
19014     {
19015         __IM uint32_t P2_QMGPC1;       /*!< (@ 0x00002A70) Qci Meter Green Packet Count                               */
19016 
19017         struct
19018         {
19019             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
19020             uint32_t            : 16;
19021         } P2_QMGPC1_b;
19022     };
19023 
19024     union
19025     {
19026         __IM uint32_t P2_QMRPC1;       /*!< (@ 0x00002A74) Qci Meter Red Packet Count                                 */
19027 
19028         struct
19029         {
19030             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
19031             uint32_t            : 16;
19032         } P2_QMRPC1_b;
19033     };
19034 
19035     union
19036     {
19037         __IOM uint32_t P2_QMDESC2;     /*!< (@ 0x00002A78) Qci Port n Flow Meter 2 Descriptor Register                */
19038 
19039         struct
19040         {
19041             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
19042             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
19043             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
19044             uint32_t           : 29;
19045         } P2_QMDESC2_b;
19046     };
19047 
19048     union
19049     {
19050         __IOM uint32_t P2_QMCBSC2;     /*!< (@ 0x00002A7C) Qci Meter CBS Configuration Port n, Meter 2                */
19051 
19052         struct
19053         {
19054             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
19055             uint32_t           : 14;
19056         } P2_QMCBSC2_b;
19057     };
19058 
19059     union
19060     {
19061         __IOM uint32_t P2_QMCIRC2;     /*!< (@ 0x00002A80) Qci Meter CIR Configuration n 2                            */
19062 
19063         struct
19064         {
19065             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
19066             uint32_t           : 15;
19067         } P2_QMCIRC2_b;
19068     };
19069 
19070     union
19071     {
19072         __IM uint32_t P2_QMGPC2;       /*!< (@ 0x00002A84) Qci Meter Green Packet Count                               */
19073 
19074         struct
19075         {
19076             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
19077             uint32_t            : 16;
19078         } P2_QMGPC2_b;
19079     };
19080 
19081     union
19082     {
19083         __IM uint32_t P2_QMRPC2;       /*!< (@ 0x00002A88) Qci Meter Red Packet Count                                 */
19084 
19085         struct
19086         {
19087             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
19088             uint32_t            : 16;
19089         } P2_QMRPC2_b;
19090     };
19091 
19092     union
19093     {
19094         __IOM uint32_t P2_QMDESC3;     /*!< (@ 0x00002A8C) Qci Port n Flow Meter 3 Descriptor Register                */
19095 
19096         struct
19097         {
19098             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
19099             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
19100             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
19101             uint32_t           : 29;
19102         } P2_QMDESC3_b;
19103     };
19104 
19105     union
19106     {
19107         __IOM uint32_t P2_QMCBSC3;     /*!< (@ 0x00002A90) Qci Meter CBS Configuration Port n, Meter 3                */
19108 
19109         struct
19110         {
19111             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
19112             uint32_t           : 14;
19113         } P2_QMCBSC3_b;
19114     };
19115 
19116     union
19117     {
19118         __IOM uint32_t P2_QMCIRC3;     /*!< (@ 0x00002A94) Qci Meter CIR Configuration n 3                            */
19119 
19120         struct
19121         {
19122             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
19123             uint32_t           : 15;
19124         } P2_QMCIRC3_b;
19125     };
19126 
19127     union
19128     {
19129         __IM uint32_t P2_QMGPC3;       /*!< (@ 0x00002A98) Qci Meter Green Packet Count                               */
19130 
19131         struct
19132         {
19133             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
19134             uint32_t            : 16;
19135         } P2_QMGPC3_b;
19136     };
19137 
19138     union
19139     {
19140         __IM uint32_t P2_QMRPC3;       /*!< (@ 0x00002A9C) Qci Meter Red Packet Count                                 */
19141 
19142         struct
19143         {
19144             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
19145             uint32_t            : 16;
19146         } P2_QMRPC3_b;
19147     };
19148 
19149     union
19150     {
19151         __IOM uint32_t P2_QMDESC4;     /*!< (@ 0x00002AA0) Qci Port n Flow Meter 4 Descriptor Register                */
19152 
19153         struct
19154         {
19155             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
19156             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
19157             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
19158             uint32_t           : 29;
19159         } P2_QMDESC4_b;
19160     };
19161 
19162     union
19163     {
19164         __IOM uint32_t P2_QMCBSC4;     /*!< (@ 0x00002AA4) Qci Meter CBS Configuration Port n, Meter 4                */
19165 
19166         struct
19167         {
19168             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
19169             uint32_t           : 14;
19170         } P2_QMCBSC4_b;
19171     };
19172 
19173     union
19174     {
19175         __IOM uint32_t P2_QMCIRC4;     /*!< (@ 0x00002AA8) Qci Meter CIR Configuration n 4                            */
19176 
19177         struct
19178         {
19179             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
19180             uint32_t           : 15;
19181         } P2_QMCIRC4_b;
19182     };
19183 
19184     union
19185     {
19186         __IM uint32_t P2_QMGPC4;       /*!< (@ 0x00002AAC) Qci Meter Green Packet Count                               */
19187 
19188         struct
19189         {
19190             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
19191             uint32_t            : 16;
19192         } P2_QMGPC4_b;
19193     };
19194 
19195     union
19196     {
19197         __IM uint32_t P2_QMRPC4;       /*!< (@ 0x00002AB0) Qci Meter Red Packet Count                                 */
19198 
19199         struct
19200         {
19201             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
19202             uint32_t            : 16;
19203         } P2_QMRPC4_b;
19204     };
19205 
19206     union
19207     {
19208         __IOM uint32_t P2_QMDESC5;     /*!< (@ 0x00002AB4) Qci Port n Flow Meter 5 Descriptor Register                */
19209 
19210         struct
19211         {
19212             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
19213             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
19214             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
19215             uint32_t           : 29;
19216         } P2_QMDESC5_b;
19217     };
19218 
19219     union
19220     {
19221         __IOM uint32_t P2_QMCBSC5;     /*!< (@ 0x00002AB8) Qci Meter CBS Configuration Port n, Meter 5                */
19222 
19223         struct
19224         {
19225             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
19226             uint32_t           : 14;
19227         } P2_QMCBSC5_b;
19228     };
19229 
19230     union
19231     {
19232         __IOM uint32_t P2_QMCIRC5;     /*!< (@ 0x00002ABC) Qci Meter CIR Configuration n 5                            */
19233 
19234         struct
19235         {
19236             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
19237             uint32_t           : 15;
19238         } P2_QMCIRC5_b;
19239     };
19240 
19241     union
19242     {
19243         __IM uint32_t P2_QMGPC5;       /*!< (@ 0x00002AC0) Qci Meter Green Packet Count                               */
19244 
19245         struct
19246         {
19247             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
19248             uint32_t            : 16;
19249         } P2_QMGPC5_b;
19250     };
19251 
19252     union
19253     {
19254         __IM uint32_t P2_QMRPC5;       /*!< (@ 0x00002AC4) Qci Meter Red Packet Count                                 */
19255 
19256         struct
19257         {
19258             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
19259             uint32_t            : 16;
19260         } P2_QMRPC5_b;
19261     };
19262 
19263     union
19264     {
19265         __IOM uint32_t P2_QMDESC6;     /*!< (@ 0x00002AC8) Qci Port n Flow Meter 6 Descriptor Register                */
19266 
19267         struct
19268         {
19269             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
19270             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
19271             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
19272             uint32_t           : 29;
19273         } P2_QMDESC6_b;
19274     };
19275 
19276     union
19277     {
19278         __IOM uint32_t P2_QMCBSC6;     /*!< (@ 0x00002ACC) Qci Meter CBS Configuration Port n, Meter 6                */
19279 
19280         struct
19281         {
19282             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
19283             uint32_t           : 14;
19284         } P2_QMCBSC6_b;
19285     };
19286 
19287     union
19288     {
19289         __IOM uint32_t P2_QMCIRC6;     /*!< (@ 0x00002AD0) Qci Meter CIR Configuration n 6                            */
19290 
19291         struct
19292         {
19293             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
19294             uint32_t           : 15;
19295         } P2_QMCIRC6_b;
19296     };
19297 
19298     union
19299     {
19300         __IM uint32_t P2_QMGPC6;       /*!< (@ 0x00002AD4) Qci Meter Green Packet Count                               */
19301 
19302         struct
19303         {
19304             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
19305             uint32_t            : 16;
19306         } P2_QMGPC6_b;
19307     };
19308 
19309     union
19310     {
19311         __IM uint32_t P2_QMRPC6;       /*!< (@ 0x00002AD8) Qci Meter Red Packet Count                                 */
19312 
19313         struct
19314         {
19315             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
19316             uint32_t            : 16;
19317         } P2_QMRPC6_b;
19318     };
19319 
19320     union
19321     {
19322         __IOM uint32_t P2_QMDESC7;     /*!< (@ 0x00002ADC) Qci Port n Flow Meter 7 Descriptor Register                */
19323 
19324         struct
19325         {
19326             __IOM uint32_t RFD : 1;    /*!< [0..0] Red frame drop                                                     */
19327             __IOM uint32_t MM  : 1;    /*!< [1..1] Flow meter mode                                                    */
19328             __IOM uint32_t CF  : 1;    /*!< [2..2] Coupling flag                                                      */
19329             uint32_t           : 29;
19330         } P2_QMDESC7_b;
19331     };
19332 
19333     union
19334     {
19335         __IOM uint32_t P2_QMCBSC7;     /*!< (@ 0x00002AE0) Qci Meter CBS Configuration Port n, Meter 7                */
19336 
19337         struct
19338         {
19339             __IOM uint32_t CBS : 18;   /*!< [17..0] CBS (Committed Burst Size)                                        */
19340             uint32_t           : 14;
19341         } P2_QMCBSC7_b;
19342     };
19343 
19344     union
19345     {
19346         __IOM uint32_t P2_QMCIRC7;     /*!< (@ 0x00002AE4) Qci Meter CIR Configuration n 7                            */
19347 
19348         struct
19349         {
19350             __IOM uint32_t CIR : 17;   /*!< [16..0] CIR (Committed Information Rate)                                  */
19351             uint32_t           : 15;
19352         } P2_QMCIRC7_b;
19353     };
19354 
19355     union
19356     {
19357         __IM uint32_t P2_QMGPC7;       /*!< (@ 0x00002AE8) Qci Meter Green Packet Count                               */
19358 
19359         struct
19360         {
19361             __IM uint32_t QMGPC : 16;  /*!< [15..0] Qci meter green packet count                                      */
19362             uint32_t            : 16;
19363         } P2_QMGPC7_b;
19364     };
19365 
19366     union
19367     {
19368         __IM uint32_t P2_QMRPC7;       /*!< (@ 0x00002AEC) Qci Meter Red Packet Count                                 */
19369 
19370         struct
19371         {
19372             __IM uint32_t QMRPC : 16;  /*!< [15..0] Qci meter red packet count                                        */
19373             uint32_t            : 16;
19374         } P2_QMRPC7_b;
19375     };
19376 
19377     union
19378     {
19379         __IOM uint32_t P2_QMEC;        /*!< (@ 0x00002AF0) Qci Meter Enable Configuration                             */
19380 
19381         struct
19382         {
19383             __IOM uint32_t ME : 8;     /*!< [7..0] Enable meter[m]                                                    */
19384             uint32_t          : 24;
19385         } P2_QMEC_b;
19386     };
19387 
19388     union
19389     {
19390         __IOM uint32_t P2_QMEIS;       /*!< (@ 0x00002AF4) Qci Meter Error Interrupt Status                           */
19391 
19392         struct
19393         {
19394             __IOM uint32_t QRFIS : 8;  /*!< [7..0] Red frames Interrupt status[m]                                     */
19395             uint32_t             : 24;
19396         } P2_QMEIS_b;
19397     };
19398 
19399     union
19400     {
19401         __IOM uint32_t P2_QMEIE;       /*!< (@ 0x00002AF8) Qci Meter Error Interrupt Enable                           */
19402 
19403         struct
19404         {
19405             __IOM uint32_t QRFIE : 8;  /*!< [7..0] Red frames Interrupt Enable[m]                                     */
19406             uint32_t             : 24;
19407         } P2_QMEIE_b;
19408     };
19409 
19410     union
19411     {
19412         __OM uint32_t P2_QMEID;        /*!< (@ 0x00002AFC) Qci Meter Error Interrupt Disable                          */
19413 
19414         struct
19415         {
19416             __OM uint32_t QRFID : 8;   /*!< [7..0] Red frames Interrupt Disable[m]                                    */
19417             uint32_t            : 24;
19418         } P2_QMEID_b;
19419     };
19420 
19421     union
19422     {
19423         __IOM uint32_t P2_PCP_REMAP;       /*!< (@ 0x00002B00) Port 2 VLAN Priority Code Point (PCP) Remap                */
19424 
19425         struct
19426         {
19427             __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0                                                         */
19428             __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1                                                         */
19429             __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2                                                         */
19430             __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3                                                        */
19431             __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4                                                       */
19432             __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5                                                       */
19433             __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6                                                       */
19434             __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7                                                       */
19435             uint32_t                  : 8;
19436         } P2_PCP_REMAP_b;
19437     };
19438 
19439     union
19440     {
19441         __IOM uint32_t P2_VLAN_TAG;    /*!< (@ 0x00002B04) Port 2 VLAN TAG Information for Priority Regeneration      */
19442 
19443         struct
19444         {
19445             __IOM uint32_t VID  : 12;  /*!< [11..0] VID                                                               */
19446             __IOM uint32_t DEI  : 1;   /*!< [12..12] DEI                                                              */
19447             __IOM uint32_t PCP  : 3;   /*!< [15..13] PCP                                                              */
19448             __IOM uint32_t TPID : 16;  /*!< [31..16] TPID                                                             */
19449         } P2_VLAN_TAG_b;
19450     };
19451 
19452     union
19453     {
19454         __IOM uint32_t P2_VLAN_MODE;   /*!< (@ 0x00002B08) Port 2 VLAN Mode                                           */
19455 
19456         struct
19457         {
19458             __IOM uint32_t VITM : 2;   /*!< [1..0] VLAN input tagging mode                                            */
19459             __IOM uint32_t VICM : 2;   /*!< [3..2] VLAN input verification mode                                       */
19460             uint32_t            : 28;
19461         } P2_VLAN_MODE_b;
19462     };
19463 
19464     union
19465     {
19466         __IM uint32_t P2_VIC_DROP_CNT;       /*!< (@ 0x00002B0C) Port 2 VLAN Ingress Check Drop Frame Counter               */
19467 
19468         struct
19469         {
19470             __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count                        */
19471             uint32_t                   : 16;
19472         } P2_VIC_DROP_CNT_b;
19473     };
19474     __IM uint32_t RESERVED89[6];
19475 
19476     union
19477     {
19478         __IM uint32_t P2_LOOKUP_HIT_CNT;       /*!< (@ 0x00002B28) Port 2 DST Address Lookup Hit Counter                      */
19479 
19480         struct
19481         {
19482             __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count                                           */
19483             uint32_t                     : 8;
19484         } P2_LOOKUP_HIT_CNT_b;
19485     };
19486 
19487     union
19488     {
19489         __IOM uint32_t P2_ERROR_STATUS; /*!< (@ 0x00002B2C) Port 2 Frame Parser Runtime Error Status                   */
19490 
19491         struct
19492         {
19493             __IOM uint32_t SOPERR : 1;  /*!< [0..0] SOP error detected in frame parser                                 */
19494             __IOM uint32_t PUNDSZ : 1;  /*!< [1..1] Preemptable frame under size error detected in frame
19495                                          *   parser                                                                    */
19496             __IOM uint32_t POVRSZ : 1;  /*!< [2..2] Preemptable frame over size error detected in frame parser         */
19497             __IOM uint32_t EUNDSZ : 1;  /*!< [3..3] Express frame under size error detected in frame parser            */
19498             __IOM uint32_t EOVRSZ : 1;  /*!< [4..4] Express frame over size error detected in frame parser             */
19499             uint32_t              : 27;
19500         } P2_ERROR_STATUS_b;
19501     };
19502 
19503     union
19504     {
19505         __IOM uint32_t P2_ERROR_MASK;   /*!< (@ 0x00002B30) Port 2 Frame Parser Runtime Error Mask                     */
19506 
19507         struct
19508         {
19509             __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error)                                   */
19510             __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error)          */
19511             __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error)           */
19512             __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error)              */
19513             __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error)               */
19514             uint32_t               : 27;
19515         } P2_ERROR_MASK_b;
19516     };
19517     __IM uint32_t RESERVED90[564];
19518 
19519     union
19520     {
19521         __IM uint32_t STATN_STATUS;    /*!< (@ 0x00003404) Statistics Status Register                                 */
19522 
19523         struct
19524         {
19525             __IM uint32_t BUSY : 1;    /*!< [0..0] Statistics module is busy                                          */
19526             uint32_t           : 31;
19527         } STATN_STATUS_b;
19528     };
19529 
19530     union
19531     {
19532         __IOM uint32_t STATN_CONFIG;   /*!< (@ 0x00003408) Statistics Configure Register                              */
19533 
19534         struct
19535         {
19536             uint32_t                     : 1;
19537             __IOM uint32_t CLEAR_ON_READ : 1; /*!< [1..1] When set to 1, a read to a counter resets it to 0. When
19538                                                *   set to 0 (default), counters are not affected by read.                    */
19539             uint32_t             : 29;
19540             __IOM uint32_t RESET : 1;         /*!< [31..31] When set to 1, all internal functions are aborted and
19541                                                *   return to a stable state (flushes prescalers). It also
19542                                                *   triggers a clear of all counter memory (all ports are cleared)
19543                                                *   by setting STATN_CONTROL.CMD_CLEAR with all mask bits.
19544                                                *   Capture memory is not reset.                                              */
19545         } STATN_CONFIG_b;
19546     };
19547 
19548     union
19549     {
19550         __IOM uint32_t STATN_CONTROL;     /*!< (@ 0x0000340C) Statistics Control Register                                */
19551 
19552         struct
19553         {
19554             __IOM uint32_t CHANMASK : 4;  /*!< [3..0] One bit per port. Bit 0 = port 0, bit 1 = port 1, and
19555                                            *   so on.                                                                    */
19556             uint32_t                 : 25;
19557             __IOM uint32_t CLEAR_PRE : 1; /*!< [29..29] Clear the internal pre-scaler counters of ports when
19558                                            *   a clear occurs. This bit can be used together with the
19559                                            *   CMD_CLEAR command to clear the internal pre-scaler counters
19560                                            *   of the ports.                                                             */
19561             uint32_t                 : 1;
19562             __IOM uint32_t CMD_CLEAR : 1; /*!< [31..31] Clear Channel Counters Command                                   */
19563         } STATN_CONTROL_b;
19564     };
19565 
19566     union
19567     {
19568         __IOM uint32_t STATN_CLEARVALUE_LO;          /*!< (@ 0x00003410) Statistics Clear Value Lower Register                      */
19569 
19570         struct
19571         {
19572             __IOM uint32_t STATN_CLEARVALUE_LO : 32; /*!< [31..0] 32-bit value written into statistics memory when a clear
19573                                                       *   command (STATN_CONTROL.CMD_CLEAR) is triggered (see ),
19574                                                       *   or when a clear-after-read is used.                                       */
19575         } STATN_CLEARVALUE_LO_b;
19576     };
19577     __IM uint32_t RESERVED91[21];
19578 
19579     union
19580     {
19581         __IM uint32_t ODISC0;          /*!< (@ 0x00003468) Port 0 Discarded Outgoing Frame Count Register             */
19582 
19583         struct
19584         {
19585             __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
19586                                         *   congestion.                                                               */
19587         } ODISC0_b;
19588     };
19589 
19590     union
19591     {
19592         __IM uint32_t IDISC_VLAN0;         /*!< (@ 0x0000346C) Port 0 Discarded Incoming VLAN Tagged Frame Count
19593                                             *                  Register                                                   */
19594 
19595         struct
19596         {
19597             __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
19598                                             *   or missing VLAN ID while VLAN verification was enabled.                   */
19599         } IDISC_VLAN0_b;
19600     };
19601 
19602     union
19603     {
19604         __IM uint32_t IDISC_UNTAGGED0;         /*!< (@ 0x00003470) Port 0 Discarded Incoming VLAN Untagged Frame
19605                                                 *                  Count Register                                             */
19606 
19607         struct
19608         {
19609             __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
19610                                                 *   tag.                                                                      */
19611         } IDISC_UNTAGGED0_b;
19612     };
19613 
19614     union
19615     {
19616         __IM uint32_t IDISC_BLOCKED0;         /*!< (@ 0x00003474) Port 0 Discarded Incoming Blocked Frame Count
19617                                                *                  Register                                                   */
19618 
19619         struct
19620         {
19621             __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
19622                                                *   the port is configured in blocking mode.                                  */
19623         } IDISC_BLOCKED0_b;
19624     };
19625 
19626     union
19627     {
19628         __IM uint32_t IDISC_ANY0;         /*!< (@ 0x00003478) Port 0 Discarded Any Frame Count Register (n
19629                                            *                  = 0 to 3)                                                  */
19630 
19631         struct
19632         {
19633             __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
19634                                            *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
19635         } IDISC_ANY0_b;
19636     };
19637 
19638     union
19639     {
19640         __IM uint32_t IDISC_SRCFLT0;         /*!< (@ 0x0000347C) Port 0 Discarded Address Source Count Register             */
19641 
19642         struct
19643         {
19644             __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
19645                                               *   due to the MAC address source filter.                                     */
19646         } IDISC_SRCFLT0_b;
19647     };
19648 
19649     union
19650     {
19651         __IM uint32_t TX_HOLD_REQ_CNT0;         /*!< (@ 0x00003480) Port 0 TX Hold Request Count Register                      */
19652 
19653         struct
19654         {
19655             __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
19656         } TX_HOLD_REQ_CNT0_b;
19657     };
19658 
19659     union
19660     {
19661         __IM uint32_t TX_FRAG_CNT0;         /*!< (@ 0x00003484) Port 0 TX for Preemption Count Register                    */
19662 
19663         struct
19664         {
19665             __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
19666                                              *   due to preemption.                                                        */
19667         } TX_FRAG_CNT0_b;
19668     };
19669 
19670     union
19671     {
19672         __IM uint32_t RX_FRAG_CNT0;         /*!< (@ 0x00003488) Port 0 RX Continuation Count Register                      */
19673 
19674         struct
19675         {
19676             __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
19677         } RX_FRAG_CNT0_b;
19678     };
19679 
19680     union
19681     {
19682         __IM uint32_t RX_ASSY_OK_CNT0;         /*!< (@ 0x0000348C) Port 0 RX Preempted Frame Success Count Register           */
19683 
19684         struct
19685         {
19686             __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
19687                                                 *   assembled.                                                                */
19688         } RX_ASSY_OK_CNT0_b;
19689     };
19690 
19691     union
19692     {
19693         __IM uint32_t RX_ASSY_ERR_CNT0;         /*!< (@ 0x00003490) Port 0 RX Preempted Frame Incorrect Count Register         */
19694 
19695         struct
19696         {
19697             __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
19698                                                  *   assembled.                                                                */
19699             uint32_t : 16;
19700         } RX_ASSY_ERR_CNT0_b;
19701     };
19702 
19703     union
19704     {
19705         __IM uint32_t RX_SMD_ERR_CNT0;         /*!< (@ 0x00003494) Port 0 RX SMD Frame Count Register                         */
19706 
19707         struct
19708         {
19709             __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
19710                                                 *   and no assembly is in progress.                                           */
19711             uint32_t : 16;
19712         } RX_SMD_ERR_CNT0_b;
19713     };
19714 
19715     union
19716     {
19717         __IM uint32_t TX_VERIFY_OK_CNT0;        /*!< (@ 0x00003498) Port 0 TX VERIFY Frame Count Register                      */
19718 
19719         struct
19720         {
19721             __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
19722             uint32_t                       : 24;
19723         } TX_VERIFY_OK_CNT0_b;
19724     };
19725 
19726     union
19727     {
19728         __IM uint32_t TX_RESPONSE_OK_CNT0;        /*!< (@ 0x0000349C) Port 0 TX RESPONSE Frame Count Register                    */
19729 
19730         struct
19731         {
19732             __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
19733             uint32_t                         : 24;
19734         } TX_RESPONSE_OK_CNT0_b;
19735     };
19736 
19737     union
19738     {
19739         __IM uint32_t RX_VERIFY_OK_CNT0;        /*!< (@ 0x000034A0) Port 0 RX VERIFY Frame Count Register                      */
19740 
19741         struct
19742         {
19743             __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
19744             uint32_t                       : 24;
19745         } RX_VERIFY_OK_CNT0_b;
19746     };
19747 
19748     union
19749     {
19750         __IM uint32_t RX_RESPONSE_OK_CNT0;        /*!< (@ 0x000034A4) Port 0 RX RESPONSE Frame Count Register                    */
19751 
19752         struct
19753         {
19754             __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
19755             uint32_t                         : 24;
19756         } RX_RESPONSE_OK_CNT0_b;
19757     };
19758 
19759     union
19760     {
19761         __IM uint32_t RX_VERIFY_BAD_CNT0;        /*!< (@ 0x000034A8) Port 0 RX Error VERIFY Frame Count Register                */
19762 
19763         struct
19764         {
19765             __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
19766             uint32_t                        : 24;
19767         } RX_VERIFY_BAD_CNT0_b;
19768     };
19769 
19770     union
19771     {
19772         __IM uint32_t RX_RESPONSE_BAD_CNT0;        /*!< (@ 0x000034AC) Port 0 RX Error RESPONSE Frame Count Register              */
19773 
19774         struct
19775         {
19776             __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
19777             uint32_t                          : 24;
19778         } RX_RESPONSE_BAD_CNT0_b;
19779     };
19780 
19781     union
19782     {
19783         __IM uint32_t ODISC1;          /*!< (@ 0x000034B0) Port 1 Discarded Outgoing Frame Count Register             */
19784 
19785         struct
19786         {
19787             __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
19788                                         *   congestion.                                                               */
19789         } ODISC1_b;
19790     };
19791 
19792     union
19793     {
19794         __IM uint32_t IDISC_VLAN1;         /*!< (@ 0x000034B4) Port 1 Discarded Incoming VLAN Tagged Frame Count
19795                                             *                  Register                                                   */
19796 
19797         struct
19798         {
19799             __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
19800                                             *   or missing VLAN ID while VLAN verification was enabled.                   */
19801         } IDISC_VLAN1_b;
19802     };
19803 
19804     union
19805     {
19806         __IM uint32_t IDISC_UNTAGGED1;         /*!< (@ 0x000034B8) Port 1 Discarded Incoming VLAN Untagged Frame
19807                                                 *                  Count Register                                             */
19808 
19809         struct
19810         {
19811             __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
19812                                                 *   tag.                                                                      */
19813         } IDISC_UNTAGGED1_b;
19814     };
19815 
19816     union
19817     {
19818         __IM uint32_t IDISC_BLOCKED1;         /*!< (@ 0x000034BC) Port 1 Discarded Incoming Blocked Frame Count
19819                                                *                  Register                                                   */
19820 
19821         struct
19822         {
19823             __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
19824                                                *   the port is configured in blocking mode.                                  */
19825         } IDISC_BLOCKED1_b;
19826     };
19827 
19828     union
19829     {
19830         __IM uint32_t IDISC_ANY1;         /*!< (@ 0x000034C0) Port 1 Discarded Any Frame Count Register (n
19831                                            *                  = 0 to 3)                                                  */
19832 
19833         struct
19834         {
19835             __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
19836                                            *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
19837         } IDISC_ANY1_b;
19838     };
19839 
19840     union
19841     {
19842         __IM uint32_t IDISC_SRCFLT1;         /*!< (@ 0x000034C4) Port 1 Discarded Address Source Count Register             */
19843 
19844         struct
19845         {
19846             __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
19847                                               *   due to the MAC address source filter.                                     */
19848         } IDISC_SRCFLT1_b;
19849     };
19850 
19851     union
19852     {
19853         __IM uint32_t TX_HOLD_REQ_CNT1;         /*!< (@ 0x000034C8) Port 1 TX Hold Request Count Register                      */
19854 
19855         struct
19856         {
19857             __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
19858         } TX_HOLD_REQ_CNT1_b;
19859     };
19860 
19861     union
19862     {
19863         __IM uint32_t TX_FRAG_CNT1;         /*!< (@ 0x000034CC) Port 1 TX for Preemption Count Register                    */
19864 
19865         struct
19866         {
19867             __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
19868                                              *   due to preemption.                                                        */
19869         } TX_FRAG_CNT1_b;
19870     };
19871 
19872     union
19873     {
19874         __IM uint32_t RX_FRAG_CNT1;         /*!< (@ 0x000034D0) Port 1 RX Continuation Count Register                      */
19875 
19876         struct
19877         {
19878             __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
19879         } RX_FRAG_CNT1_b;
19880     };
19881 
19882     union
19883     {
19884         __IM uint32_t RX_ASSY_OK_CNT1;         /*!< (@ 0x000034D4) Port 1 RX Preempted Frame Success Count Register           */
19885 
19886         struct
19887         {
19888             __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
19889                                                 *   assembled.                                                                */
19890         } RX_ASSY_OK_CNT1_b;
19891     };
19892 
19893     union
19894     {
19895         __IM uint32_t RX_ASSY_ERR_CNT1;         /*!< (@ 0x000034D8) Port 1 RX Preempted Frame Incorrect Count Register         */
19896 
19897         struct
19898         {
19899             __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
19900                                                  *   assembled.                                                                */
19901             uint32_t : 16;
19902         } RX_ASSY_ERR_CNT1_b;
19903     };
19904 
19905     union
19906     {
19907         __IM uint32_t RX_SMD_ERR_CNT1;         /*!< (@ 0x000034DC) Port 1 RX SMD Frame Count Register                         */
19908 
19909         struct
19910         {
19911             __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
19912                                                 *   and no assembly is in progress.                                           */
19913             uint32_t : 16;
19914         } RX_SMD_ERR_CNT1_b;
19915     };
19916 
19917     union
19918     {
19919         __IM uint32_t TX_VERIFY_OK_CNT1;        /*!< (@ 0x000034E0) Port 1 TX VERIFY Frame Count Register                      */
19920 
19921         struct
19922         {
19923             __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
19924             uint32_t                       : 24;
19925         } TX_VERIFY_OK_CNT1_b;
19926     };
19927 
19928     union
19929     {
19930         __IM uint32_t TX_RESPONSE_OK_CNT1;        /*!< (@ 0x000034E4) Port 1 TX RESPONSE Frame Count Register                    */
19931 
19932         struct
19933         {
19934             __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
19935             uint32_t                         : 24;
19936         } TX_RESPONSE_OK_CNT1_b;
19937     };
19938 
19939     union
19940     {
19941         __IM uint32_t RX_VERIFY_OK_CNT1;        /*!< (@ 0x000034E8) Port 1 RX VERIFY Frame Count Register                      */
19942 
19943         struct
19944         {
19945             __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
19946             uint32_t                       : 24;
19947         } RX_VERIFY_OK_CNT1_b;
19948     };
19949 
19950     union
19951     {
19952         __IM uint32_t RX_RESPONSE_OK_CNT1;        /*!< (@ 0x000034EC) Port 1 RX RESPONSE Frame Count Register                    */
19953 
19954         struct
19955         {
19956             __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
19957             uint32_t                         : 24;
19958         } RX_RESPONSE_OK_CNT1_b;
19959     };
19960 
19961     union
19962     {
19963         __IM uint32_t RX_VERIFY_BAD_CNT1;        /*!< (@ 0x000034F0) Port 1 RX Error VERIFY Frame Count Register                */
19964 
19965         struct
19966         {
19967             __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
19968             uint32_t                        : 24;
19969         } RX_VERIFY_BAD_CNT1_b;
19970     };
19971 
19972     union
19973     {
19974         __IM uint32_t RX_RESPONSE_BAD_CNT1;        /*!< (@ 0x000034F4) Port 1 RX Error RESPONSE Frame Count Register              */
19975 
19976         struct
19977         {
19978             __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
19979             uint32_t                          : 24;
19980         } RX_RESPONSE_BAD_CNT1_b;
19981     };
19982 
19983     union
19984     {
19985         __IM uint32_t ODISC2;          /*!< (@ 0x000034F8) Port 2 Discarded Outgoing Frame Count Register             */
19986 
19987         struct
19988         {
19989             __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
19990                                         *   congestion.                                                               */
19991         } ODISC2_b;
19992     };
19993 
19994     union
19995     {
19996         __IM uint32_t IDISC_VLAN2;         /*!< (@ 0x000034FC) Port 2 Discarded Incoming VLAN Tagged Frame Count
19997                                             *                  Register                                                   */
19998 
19999         struct
20000         {
20001             __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
20002                                             *   or missing VLAN ID while VLAN verification was enabled.                   */
20003         } IDISC_VLAN2_b;
20004     };
20005 
20006     union
20007     {
20008         __IM uint32_t IDISC_UNTAGGED2;         /*!< (@ 0x00003500) Port 2 Discarded Incoming VLAN Untagged Frame
20009                                                 *                  Count Register                                             */
20010 
20011         struct
20012         {
20013             __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
20014                                                 *   tag.                                                                      */
20015         } IDISC_UNTAGGED2_b;
20016     };
20017 
20018     union
20019     {
20020         __IM uint32_t IDISC_BLOCKED2;         /*!< (@ 0x00003504) Port 2 Discarded Incoming Blocked Frame Count
20021                                                *                  Register                                                   */
20022 
20023         struct
20024         {
20025             __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
20026                                                *   the port is configured in blocking mode.                                  */
20027         } IDISC_BLOCKED2_b;
20028     };
20029 
20030     union
20031     {
20032         __IM uint32_t IDISC_ANY2;         /*!< (@ 0x00003508) Port 2 Discarded Any Frame Count Register (n
20033                                            *                  = 0 to 3)                                                  */
20034 
20035         struct
20036         {
20037             __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
20038                                            *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
20039         } IDISC_ANY2_b;
20040     };
20041 
20042     union
20043     {
20044         __IM uint32_t IDISC_SRCFLT2;         /*!< (@ 0x0000350C) Port 2 Discarded Address Source Count Register             */
20045 
20046         struct
20047         {
20048             __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded
20049                                               *   due to the MAC address source filter.                                     */
20050         } IDISC_SRCFLT2_b;
20051     };
20052 
20053     union
20054     {
20055         __IM uint32_t TX_HOLD_REQ_CNT2;         /*!< (@ 0x00003510) Port 2 TX Hold Request Count Register                      */
20056 
20057         struct
20058         {
20059             __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT                                                   */
20060         } TX_HOLD_REQ_CNT2_b;
20061     };
20062 
20063     union
20064     {
20065         __IM uint32_t TX_FRAG_CNT2;         /*!< (@ 0x00003514) Port 2 TX for Preemption Count Register                    */
20066 
20067         struct
20068         {
20069             __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted
20070                                              *   due to preemption.                                                        */
20071         } TX_FRAG_CNT2_b;
20072     };
20073 
20074     union
20075     {
20076         __IM uint32_t RX_FRAG_CNT2;         /*!< (@ 0x00003518) Port 2 RX Continuation Count Register                      */
20077 
20078         struct
20079         {
20080             __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received.        */
20081         } RX_FRAG_CNT2_b;
20082     };
20083 
20084     union
20085     {
20086         __IM uint32_t RX_ASSY_OK_CNT2;         /*!< (@ 0x0000351C) Port 2 RX Preempted Frame Success Count Register           */
20087 
20088         struct
20089         {
20090             __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully
20091                                                 *   assembled.                                                                */
20092         } RX_ASSY_OK_CNT2_b;
20093     };
20094 
20095     union
20096     {
20097         __IM uint32_t RX_ASSY_ERR_CNT2;         /*!< (@ 0x00003520) Port 2 RX Preempted Frame Incorrect Count Register         */
20098 
20099         struct
20100         {
20101             __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly
20102                                                  *   assembled.                                                                */
20103             uint32_t : 16;
20104         } RX_ASSY_ERR_CNT2_b;
20105     };
20106 
20107     union
20108     {
20109         __IM uint32_t RX_SMD_ERR_CNT2;         /*!< (@ 0x00003524) Port 2 RX SMD Frame Count Register                         */
20110 
20111         struct
20112         {
20113             __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received
20114                                                 *   and no assembly is in progress.                                           */
20115             uint32_t : 16;
20116         } RX_SMD_ERR_CNT2_b;
20117     };
20118 
20119     union
20120     {
20121         __IM uint32_t TX_VERIFY_OK_CNT2;        /*!< (@ 0x00003528) Port 2 TX VERIFY Frame Count Register                      */
20122 
20123         struct
20124         {
20125             __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted.              */
20126             uint32_t                       : 24;
20127         } TX_VERIFY_OK_CNT2_b;
20128     };
20129 
20130     union
20131     {
20132         __IM uint32_t TX_RESPONSE_OK_CNT2;        /*!< (@ 0x0000352C) Port 2 TX RESPONSE Frame Count Register                    */
20133 
20134         struct
20135         {
20136             __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted.            */
20137             uint32_t                         : 24;
20138         } TX_RESPONSE_OK_CNT2_b;
20139     };
20140 
20141     union
20142     {
20143         __IM uint32_t RX_VERIFY_OK_CNT2;        /*!< (@ 0x00003530) Port 2 RX VERIFY Frame Count Register                      */
20144 
20145         struct
20146         {
20147             __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received.           */
20148             uint32_t                       : 24;
20149         } RX_VERIFY_OK_CNT2_b;
20150     };
20151 
20152     union
20153     {
20154         __IM uint32_t RX_RESPONSE_OK_CNT2;        /*!< (@ 0x00003534) Port 2 RX RESPONSE Frame Count Register                    */
20155 
20156         struct
20157         {
20158             __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received.         */
20159             uint32_t                         : 24;
20160         } RX_RESPONSE_OK_CNT2_b;
20161     };
20162 
20163     union
20164     {
20165         __IM uint32_t RX_VERIFY_BAD_CNT2;        /*!< (@ 0x00003538) Port 2 RX Error VERIFY Frame Count Register                */
20166 
20167         struct
20168         {
20169             __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received.         */
20170             uint32_t                        : 24;
20171         } RX_VERIFY_BAD_CNT2_b;
20172     };
20173 
20174     union
20175     {
20176         __IM uint32_t RX_RESPONSE_BAD_CNT2;        /*!< (@ 0x0000353C) Port 2 RX Error RESPONSE Frame Count Register              */
20177 
20178         struct
20179         {
20180             __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received.       */
20181             uint32_t                          : 24;
20182         } RX_RESPONSE_BAD_CNT2_b;
20183     };
20184 
20185     union
20186     {
20187         __IM uint32_t ODISC3;          /*!< (@ 0x00003540) Port 3 Discarded Outgoing Frame Count Register             */
20188 
20189         struct
20190         {
20191             __IM uint32_t ODISC : 32;  /*!< [31..0] Port n outgoing frames discarded due to output queue
20192                                         *   congestion.                                                               */
20193         } ODISC3_b;
20194     };
20195 
20196     union
20197     {
20198         __IM uint32_t IDISC_VLAN3;         /*!< (@ 0x00003544) Port 3 Discarded Incoming VLAN Tagged Frame Count
20199                                             *                  Register                                                   */
20200 
20201         struct
20202         {
20203             __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching
20204                                             *   or missing VLAN ID while VLAN verification was enabled.                   */
20205         } IDISC_VLAN3_b;
20206     };
20207 
20208     union
20209     {
20210         __IM uint32_t IDISC_UNTAGGED3;         /*!< (@ 0x00003548) Port 3 Discarded Incoming VLAN Untagged Frame
20211                                                 *                  Count Register                                             */
20212 
20213         struct
20214         {
20215             __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN
20216                                                 *   tag.                                                                      */
20217         } IDISC_UNTAGGED3_b;
20218     };
20219 
20220     union
20221     {
20222         __IM uint32_t IDISC_BLOCKED3;         /*!< (@ 0x0000354C) Port 3 Discarded Incoming Blocked Frame Count
20223                                                *                  Register                                                   */
20224 
20225         struct
20226         {
20227             __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as
20228                                                *   the port is configured in blocking mode.                                  */
20229         } IDISC_BLOCKED3_b;
20230     };
20231 
20232     union
20233     {
20234         __IM uint32_t IDISC_ANY3;         /*!< (@ 0x00003550) Port 3 Discarded Any Frame Count Register (n
20235                                            *                  = 0 to 3)                                                  */
20236 
20237         struct
20238         {
20239             __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes
20240                                            *   IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED.              */
20241         } IDISC_ANY3_b;
20242     };
20243     __IM uint32_t RESERVED92[363];
20244 
20245     union
20246     {
20247         __IOM uint32_t MMCTL_OUT_CT;       /*!< (@ 0x00003B00) Cut-Through Register                                       */
20248 
20249         struct
20250         {
20251             __IOM uint32_t CT_OVR_ENA : 3; /*!< [2..0] Per-port bit mask to enable overriding the Cut-Through
20252                                             *   (CT) behavior of the output ports with CT_OVR. When set
20253                                             *   to 0, the frames are transmitted CT if the CT flag of the
20254                                             *   frame context is set.                                                     */
20255             uint32_t              : 13;
20256             __IOM uint32_t CT_OVR : 3;     /*!< [18..16] 1 bit per-port value to set the Cut Through behavior
20257                                             *   of the output ports. When set to 0, all frames are sent
20258                                             *   as Store & Forward (SF) frames. When set to 1, frames with
20259                                             *   the CT flag set in the frame context are started as soon
20260                                             *   as the frame context information is available.                            */
20261             uint32_t : 13;
20262         } MMCTL_OUT_CT_b;
20263     };
20264 
20265     union
20266     {
20267         __IOM uint32_t MMCTL_CTFL_P0_3_ENA; /*!< (@ 0x00003B04) Cut-Through Frame Length Enable Register                   */
20268 
20269         struct
20270         {
20271             __IOM uint32_t CTFL_P0_ENA : 8; /*!< [7..0] Port 0 bit mask of n bits, where n is the number of queues
20272                                              *   per port indicating whether the CTFL is used for Cut-Through
20273                                              *   (CT) frames. When set to 1, a CT frame requires a CTFL
20274                                              *   entry to be written as a CT frame in the output memory.                   */
20275             __IOM uint32_t CTFL_P1_ENA : 8; /*!< [15..8] Port 1 bit mask of n bits, where n is the number of
20276                                              *   queues per port indicating whether the CTFL is used for
20277                                              *   Cut-Through (CT) frames. When set to 1, a CT frame requires
20278                                              *   a CTFL entry to be written as a CT frame in the output
20279                                              *   memory.                                                                   */
20280             __IOM uint32_t CTFL_P2_ENA : 8; /*!< [23..16] Port 2 bit mask of n bits, where n is the number of
20281                                              *   queues per port indicating whether the CTFL is used for
20282                                              *   Cut-Through (CT) frames. When set to 1, a CT frame requires
20283                                              *   a CTFL entry to be written as a CT frame in the output
20284                                              *   memory.                                                                   */
20285             uint32_t : 8;
20286         } MMCTL_CTFL_P0_3_ENA_b;
20287     };
20288     __IM uint32_t RESERVED93[6];
20289 
20290     union
20291     {
20292         __IOM uint32_t MMCTL_YELLOW_BYTE_LENGTH_P[3]; /*!< (@ 0x00003B20) Port [0..2] Yellow Period Byte Length Register            */
20293 
20294         struct
20295         {
20296             uint32_t                  : 2;
20297             __IOM uint32_t YELLOW_LEN : 14; /*!< [15..2] Length in bytes of the YELLOW period for port n. Determines
20298                                              *   whether a frame can be transmitted before the YELLOW period
20299                                              *   expires. The value is programmed in increments of 4 bytes
20300                                              *   excluding the MAC overhead (IPG, Preamble and FCS if appended)
20301                                              *   of the frame.                                                             */
20302             __IOM uint32_t YLEN_EN : 1;     /*!< [16..16] When set to 1, enables transmission when OUT_CT_ENA
20303                                              *   is low only if the frame length is less than YELLOW_LEN.
20304                                              *   If cleared, YELLOW_LEN is ignored and frames are always
20305                                              *   transmitted in SF mode when OUT_CT_ENA is 0.                              */
20306             uint32_t : 15;
20307         } MMCTL_YELLOW_BYTE_LENGTH_P_b[3];
20308     };
20309     __IM uint32_t RESERVED94[5];
20310 
20311     union
20312     {
20313         __IOM uint32_t MMCTL_POOL0_CTR; /*!< (@ 0x00003B40) Memory Pool Counter (n = 0 to 1)                           */
20314 
20315         struct
20316         {
20317             __IOM uint32_t CELLS : 10;  /*!< [9..0] Memory pool configuration for pool n. Configures, in
20318                                          *   cells, the size of each memory pool.                                      */
20319             uint32_t           : 6;
20320             __IM uint32_t USED : 10;    /*!< [25..16] Reports the current available number of used cells
20321                                          *   for this memory pool. The used number of free cells can
20322                                          *   be calculated as CELLS - USED.                                          */
20323             uint32_t : 6;
20324         } MMCTL_POOL0_CTR_b;
20325     };
20326 
20327     union
20328     {
20329         __IOM uint32_t MMCTL_POOL1_CTR; /*!< (@ 0x00003B44) Memory Pool Counter (n = 0 to 1)                           */
20330 
20331         struct
20332         {
20333             __IOM uint32_t CELLS : 10;  /*!< [9..0] Memory pool configuration for pool n. Configures, in
20334                                          *   cells, the size of each memory pool.                                      */
20335             uint32_t           : 6;
20336             __IM uint32_t USED : 10;    /*!< [25..16] Reports the current available number of used cells
20337                                          *   for this memory pool. The used number of free cells can
20338                                          *   be calculated as CELLS - USED.                                          */
20339             uint32_t : 6;
20340         } MMCTL_POOL1_CTR_b;
20341     };
20342     __IM uint32_t RESERVED95[6];
20343 
20344     union
20345     {
20346         __IOM uint32_t MMCTL_POOL_GLOBAL; /*!< (@ 0x00003B60) Memory Pool Configuration Register                         */
20347 
20348         struct
20349         {
20350             __IOM uint32_t CELLS : 10;    /*!< [9..0] Memory pool configuration for the global pool. Configures,
20351                                            *   in cells, the size of the global shared pool.                             */
20352             uint32_t           : 6;
20353             __IM uint32_t USED : 10;      /*!< [25..16] Reports the current number of used cells for the global
20354                                            *   shared pool. The used number of free cells can be calculated
20355                                            *   as CELLS - USED.                                                        */
20356             uint32_t : 6;
20357         } MMCTL_POOL_GLOBAL_b;
20358     };
20359 
20360     union
20361     {
20362         __IM uint32_t MMCTL_POOL_STATUS;  /*!< (@ 0x00003B64) Memory Pool Status Register                                */
20363 
20364         struct
20365         {
20366             __IM uint32_t QUEUE_FULL : 8; /*!< [7..0] Per-queue pool full indication. Indicates for each queue
20367                                            *   whether all the blocks in the corresponding pool and global
20368                                            *   pool are allocated.                                                       */
20369             uint32_t : 24;
20370         } MMCTL_POOL_STATUS_b;
20371     };
20372 
20373     union
20374     {
20375         __IOM uint32_t MMCTL_POOL_QMAP; /*!< (@ 0x00003B68) Queue MAP Register                                         */
20376 
20377         struct
20378         {
20379             __IOM uint32_t Q0_MAP : 1;  /*!< [0..0] Queue 0 Memory Pool                                                */
20380             uint32_t              : 2;
20381             __IOM uint32_t Q0_ENA : 1;  /*!< [3..3] Queue 0 Memory Pool Enabled                                        */
20382             __IOM uint32_t Q1_MAP : 1;  /*!< [4..4] Queue 1 Memory Pool                                                */
20383             uint32_t              : 2;
20384             __IOM uint32_t Q1_ENA : 1;  /*!< [7..7] Queue 1 Memory Pool Enabled                                        */
20385             __IOM uint32_t Q2_MAP : 1;  /*!< [8..8] Queue 2 Memory Pool                                                */
20386             uint32_t              : 2;
20387             __IOM uint32_t Q2_ENA : 1;  /*!< [11..11] Queue 2 Memory Pool Enabled                                      */
20388             __IOM uint32_t Q3_MAP : 1;  /*!< [12..12] Queue 3 Memory Pool                                              */
20389             uint32_t              : 2;
20390             __IOM uint32_t Q3_ENA : 1;  /*!< [15..15] Queue 3 Memory Pool Enabled                                      */
20391             __IOM uint32_t Q4_MAP : 1;  /*!< [16..16] Queue 4 Memory Pool                                              */
20392             uint32_t              : 2;
20393             __IOM uint32_t Q4_ENA : 1;  /*!< [19..19] Queue 4 Memory Pool Enabled                                      */
20394             __IOM uint32_t Q5_MAP : 1;  /*!< [20..20] Queue 5 Memory Pool                                              */
20395             uint32_t              : 2;
20396             __IOM uint32_t Q5_ENA : 1;  /*!< [23..23] Queue 5 Memory Pool Enabled                                      */
20397             __IOM uint32_t Q6_MAP : 1;  /*!< [24..24] Queue 6 Memory Pool                                              */
20398             uint32_t              : 2;
20399             __IOM uint32_t Q6_ENA : 1;  /*!< [27..27] Queue 6 Memory Pool Enabled                                      */
20400             __IOM uint32_t Q7_MAP : 1;  /*!< [28..28] Queue 7 Memory Pool                                              */
20401             uint32_t              : 2;
20402             __IOM uint32_t Q7_ENA : 1;  /*!< [31..31] Queue 7 Memory Pool Enabled                                      */
20403         } MMCTL_POOL_QMAP_b;
20404     };
20405 
20406     union
20407     {
20408         __OM uint32_t MMCTL_QGATE;         /*!< (@ 0x00003B6C) Queue Gate State Register                                  */
20409 
20410         struct
20411         {
20412             __OM uint32_t PORT_MASK : 4;   /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue
20413                                             *   gate state is changed for that port as indicated by QUEUE_GATE.           */
20414             uint32_t                 : 12;
20415             __OM uint32_t QUEUE_GATE : 16; /*!< [31..16] 2-bit per queue indicating the action to be performed
20416                                             *   on each queue of the ports indicated by PORT_MASK.                        */
20417         } MMCTL_QGATE_b;
20418     };
20419 
20420     union
20421     {
20422         __OM uint32_t MMCTL_QTRIG;        /*!< (@ 0x00003B70) Queue Trigger Register                                     */
20423 
20424         struct
20425         {
20426             __OM uint32_t PORT_MASK : 4;  /*!< [3..0] Per-port bit mask. When set to 1 for a port, a frame
20427                                            *   is triggered from the closed queues indicated by QUEUE_TRIG.              */
20428             uint32_t                 : 12;
20429             __OM uint32_t QUEUE_TRIG : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame
20430                                            *   is to be transmitted from the ports indicated by PORT_MASK.
20431                                            *   When set to 1, a single frame is transmitted per indicated
20432                                            *   port in PORT_MASK among the queues indicated by QUEUE_TRIG.               */
20433             uint32_t : 8;
20434         } MMCTL_QTRIG_b;
20435     };
20436 
20437     union
20438     {
20439         __OM uint32_t MMCTL_QFLUSH;       /*!< (@ 0x00003B74) Flush Event Select Register                                */
20440 
20441         struct
20442         {
20443             __OM uint32_t PORT_MASK : 4;  /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue
20444                                            *   flush status is changed for that port for the queues indicated
20445                                            *   in QUEUE_MASK.                                                            */
20446             uint32_t                 : 12;
20447             __OM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1 bit per queue indicating for which queues of the
20448                                            *   ports indicated by PORT_MASK the flush state is changed
20449                                            *   as indicated in ACTION.                                                   */
20450             __OM uint32_t ACTION : 2;     /*!< [25..24] Selects the flush state for the queues indicated by
20451                                            *   QUEUE_MASK in the ports indicated by PORT_MASK. Possible
20452                                            *   actions are:                                                              */
20453             uint32_t : 6;
20454         } MMCTL_QFLUSH_b;
20455     };
20456 
20457     union
20458     {
20459         __IM uint32_t MMCTL_QCLOSED_STATUS_P0_3; /*!< (@ 0x00003B78) Queue Closed Status Register                               */
20460 
20461         struct
20462         {
20463             __IM uint32_t P0_STATUS : 8;         /*!< [7..0] Per-queue closed status of Port 0 (1-bit per queue).
20464                                                   *   A 0 indicates that the queue is open (enabled), and a 1
20465                                                   *   indicates that the queue is closed (disabled).                            */
20466             __IM uint32_t P1_STATUS : 8;         /*!< [15..8] Per-queue closed status of Port 1 (1-bit per queue).
20467                                                   *   A 0 indicates that the queue is open (enabled), and a 1
20468                                                   *   indicates that the queue is closed (disabled).                            */
20469             __IM uint32_t P2_STATUS : 8;         /*!< [23..16] Per-queue closed status of Port 2 (1-bit per queue).
20470                                                   *   A 0 indicates that the queue is open (enabled), and a 1
20471                                                   *   indicates that the queue is closed (disabled).                            */
20472             uint32_t : 8;
20473         } MMCTL_QCLOSED_STATUS_P0_3_b;
20474     };
20475     __IM uint32_t RESERVED96;
20476 
20477     union
20478     {
20479         __IOM uint32_t MMCTL_1FRAME_MODE_P[3]; /*!< (@ 0x00003B80) Port [0..2] 1-Frame Mode Configuration Register            */
20480 
20481         struct
20482         {
20483             __IOM uint32_t Q_1FRAME_ENA : 8;   /*!< [7..0] 1 bit per queue. Setting a bit to 1 enables the 1-frame
20484                                                 *   mode for that queue for port n. In this mode, only one
20485                                                 *   frame is allowed in the queue. If a new frame is received,
20486                                                 *   the old frame is discarded.                                               */
20487             uint32_t                 : 8;
20488             __IOM uint32_t Q_BUF_ENA : 8;      /*!< [23..16] 1 bit per queue. Setting a bit to 1 enables the buffer
20489                                                 *   mode behavior for that queue for port n. This mode requires
20490                                                 *   also that Q_1FRAME_ENA is set to 1.                                       */
20491             uint32_t : 8;
20492         } MMCTL_1FRAME_MODE_P_b[3];
20493     };
20494     __IM uint32_t RESERVED97[5];
20495 
20496     union
20497     {
20498         __IM uint32_t MMCTL_P0_3_QUEUE_STATUS; /*!< (@ 0x00003BA0) Queue Status Indicator                                     */
20499 
20500         struct
20501         {
20502             __IM uint32_t P0_Q_STATUS : 8;     /*!< [7..0] Port 0 Per-Queue Bit Indication                                    */
20503             __IM uint32_t P1_Q_STATUS : 8;     /*!< [15..8] Port 1 Per-Queue Bit Indication                                   */
20504             __IM uint32_t P2_Q_STATUS : 8;     /*!< [23..16] Port 2 Per-Queue Bit Indication                                  */
20505             uint32_t                  : 8;
20506         } MMCTL_P0_3_QUEUE_STATUS_b;
20507     };
20508     __IM uint32_t RESERVED98;
20509 
20510     union
20511     {
20512         __IM uint32_t MMCTL_P0_3_FLUSH_STATUS; /*!< (@ 0x00003BA8) Queue Flush Status Indicator                               */
20513 
20514         struct
20515         {
20516             __IM uint32_t P0_F_STATUS : 8;     /*!< [7..0] Port 0 per-Queue Bit Indication on whether the queue
20517                                                 *   is flushing frames (read 1) or not (read 0).                              */
20518             __IM uint32_t P1_F_STATUS : 8;     /*!< [15..8] Port 1 per-Queue Bit Indication on whether the queue
20519                                                 *   is flushing frames (read 1) or not (read 0).                              */
20520             __IM uint32_t P2_F_STATUS : 8;     /*!< [23..16] Port 2 per-Queue Bit Indication on whether the queue
20521                                                 *   is flushing frames (read 1) or not (read 0).                              */
20522             uint32_t : 8;
20523         } MMCTL_P0_3_FLUSH_STATUS_b;
20524     };
20525     __IM uint32_t RESERVED99;
20526 
20527     union
20528     {
20529         __IOM uint32_t MMCTL_DLY_QTRIGGER_CTRL; /*!< (@ 0x00003BB0) Delayed Queue Trigger Control Register                     */
20530 
20531         struct
20532         {
20533             __IOM uint32_t DELAY_TIME : 30;     /*!< [29..0] 30-bit time in nanoseconds indicates the time after
20534                                                  *   the trigger request from the pattern matchers to generate
20535                                                  *   the event.                                                                */
20536             __IOM uint32_t TIMER_SEL : 1;       /*!< [30..30] Select the source timer to use for calculating the
20537                                                  *   time.                                                                     */
20538             uint32_t : 1;
20539         } MMCTL_DLY_QTRIGGER_CTRL_b;
20540     };
20541 
20542     union
20543     {
20544         __IOM uint32_t MMCTL_PREEMPT_QUEUES;      /*!< (@ 0x00003BB4) Preemptable Queues Configures Register                     */
20545 
20546         struct
20547         {
20548             __IOM uint32_t PREEMPT_ENA : 8;       /*!< [7..0] Per-queue enable bit to configure which queues are used
20549                                                    *   for preemptable traffic. Set to 1 the corresponding bit
20550                                                    *   to configure a queue to be preemptable.                                   */
20551             __IOM uint32_t PREEMPT_ON_QCLOSE : 8; /*!< [15..8] Per-queue configuration bit to enable preempting a frame
20552                                                    *   when the queue goes from OPEN to CLOSED. When the corresponding
20553                                                    *   bit is set to 1 and the queue is configured as preemptable
20554                                                    *   in PREEMPT_ENA, a queue close event causes the current
20555                                                    *   frame to be preempted, if preemption is operational.                      */
20556             uint32_t : 16;
20557         } MMCTL_PREEMPT_QUEUES_b;
20558     };
20559 
20560     union
20561     {
20562         __IOM uint32_t MMCTL_HOLD_CONTROL;         /*!< (@ 0x00003BB8) Request Preemption Register                                */
20563 
20564         struct
20565         {
20566             __IOM uint32_t Q_HOLD_REQ_FORCE : 3;   /*!< [2..0] A per-port bit that forces a preempt request using MM_CTL.request
20567                                                     *   (hold_req). When this bit is set to 1, it overrides other
20568                                                     *   sources of hold request, including the TDMA controller.                   */
20569             uint32_t                          : 13;
20570             __IOM uint32_t Q_HOLD_REQ_RELEASE : 3; /*!< [18..16] A per-port bit that forces a release of preemption
20571                                                     *   request using MM_CTL.request (hold_req). When this bit
20572                                                     *   is set to 1, it overrides other sources of hold request,
20573                                                     *   including the TDMA controller and Q_HOLD_REQ_FORCE[2:0].                  */
20574             uint32_t : 13;
20575         } MMCTL_HOLD_CONTROL_b;
20576     };
20577 
20578     union
20579     {
20580         __IM uint32_t MMCTL_PREEMPT_STATUS;   /*!< (@ 0x00003BBC) Preemption State Register                                  */
20581 
20582         struct
20583         {
20584             __IM uint32_t PREEMPT_STATE : 3;  /*!< [2..0] A per-port bit that indicates if a port is in a preempted
20585                                                *   state. This is a real-time indication meant for debugging.                */
20586             uint32_t                     : 13;
20587             __IM uint32_t HOLD_REQ_STATE : 3; /*!< [18..16] A per-port bit that indicates if a port is preempted
20588                                                *   using MM_CTL.request (hold_req). This is a real-time indication
20589                                                *   meant for debugging.                                                      */
20590             uint32_t : 13;
20591         } MMCTL_PREEMPT_STATUS_b;
20592     };
20593 
20594     union
20595     {
20596         __IOM uint32_t MMCTL_CQF_CTRL_P[4];  /*!< (@ 0x00003BC0) Port [0..3] Cyclic Queuing and Forwarding Control
20597                                               *                  Register                                                   */
20598 
20599         struct
20600         {
20601             __IOM uint32_t PRIO_ENABLE0 : 8; /*!< [7..0] A per-queue enable to select which ingress priorities
20602                                               *   are queued in the two CQF queues.                                         */
20603             __IOM uint32_t QUEUE_SEL0 : 3;   /*!< [10..8] Select which two physical queues are used for CQF. The
20604                                               *   queues used are QUEUE_SEL0 and QUEUE_SEL0 + 1. Frames are
20605                                               *   written into QUEUE_SEL0 when the gate control selected
20606                                               *   with GATE_SEL0 is 0, and into QUEUE_SEL0 + 1 when the gate
20607                                               *   control is 1.                                                             */
20608             __IOM uint32_t GATE_SEL0 : 3;    /*!< [13..11] Select which gate control signal is used for selecting
20609                                               *   the output queue (these signals are the same as the ETHSW_TDMAOUT
20610                                               *   pins).                                                                    */
20611             __IOM uint32_t USE_SOP0 : 1;     /*!< [14..14] When set to 1, the CFQ queue is determined when the
20612                                               *   SOP is received at the frame writer in the memory controller.
20613                                               *   When set to 0, the queue is determined when the EOP is
20614                                               *   received at the frame writer.                                             */
20615             __IOM uint32_t REF_SEL0 : 1;     /*!< [15..15] Select whether the gate control signal used for the
20616                                               *   CQF group is based on the egress port when set to 0, or
20617                                               *   the ingress port when set to 1.                                           */
20618             uint32_t : 16;
20619         } MMCTL_CQF_CTRL_P_b[4];
20620     };
20621     __IM uint32_t RESERVED100[4];
20622 
20623     union
20624     {
20625         __IM uint32_t MMCTL_P0_3_QCLOSED_NONEMPTY; /*!< (@ 0x00003BE0) Port Queue Status Register                                 */
20626 
20627         struct
20628         {
20629             __IM uint32_t P0_Q_STATUS : 8;         /*!< [7..0] Port 0 per-queue bit indication on whether the queue
20630                                                     *   transitioned from open to closed state while frames were
20631                                                     *   still queued.                                                             */
20632             __IM uint32_t P1_Q_STATUS : 8;         /*!< [15..8] Port 1 per-queue bit indication on whether the queue
20633                                                     *   transitioned from open to closed state while frames were
20634                                                     *   still queued.                                                             */
20635             __IM uint32_t P2_Q_STATUS : 8;         /*!< [23..16] Port 2 per-queue bit indication on whether the queue
20636                                                     *   transitioned from open to closed state while frames were
20637                                                     *   still queued.                                                             */
20638             __IM uint32_t P3_Q_STATUS : 8;         /*!< [31..24] Port 3 per-queue bit indication on whether the queue
20639                                                     *   transitioned from open to closed state while frames were
20640                                                     *   still queued.                                                             */
20641         } MMCTL_P0_3_QCLOSED_NONEMPTY_b;
20642     };
20643     __IM uint32_t RESERVED101;
20644 
20645     union
20646     {
20647         __IOM uint32_t MMCTL_PREEMPT_EXTRA;   /*!< (@ 0x00003BE8) Frame Preemption Extra Configuration Register              */
20648 
20649         struct
20650         {
20651             __IOM uint32_t MIN_PFRM_ADJ : 4;  /*!< [3..0] Adjust the minimum mPacket length, in increments of 4
20652                                                *   bytes.                                                                    */
20653             __IOM uint32_t LAST_PFRM_ADJ : 4; /*!< [7..4] Adjust the preemptable threshold when reaching the end
20654                                                *   of the frame, in increments of 4 bytes. Incrementing this
20655                                                *   value increments the length of the last mPacket.                          */
20656             uint32_t : 24;
20657         } MMCTL_PREEMPT_EXTRA_b;
20658     };
20659     __IM uint32_t RESERVED102[5];
20660 
20661     union
20662     {
20663         __IOM uint32_t DLR_CONTROL;             /*!< (@ 0x00003C00) DLR Control Register                                       */
20664 
20665         struct
20666         {
20667             __IOM uint32_t ENABLE : 1;          /*!< [0..0] Enable DLR extension module. When set, the DLR module
20668                                                  *   becomes active. When DLR is enabled, the LOOP_FILTER_ENA
20669                                                  *   must also be enabled for proper DLR operation.                            */
20670             __IOM uint32_t AUTOFLUSH : 1;       /*!< [1..1] Enable automatic flushing of unicast entries in address
20671                                                  *   table if ring reconfiguration occurs (see also DLR interrupt
20672                                                  *   IRQ_flush_macaddr_ena in DLR_IRQ_CONTROL).                                */
20673             __IOM uint32_t LOOP_FILTER_ENA : 1; /*!< [2..2] Enable the loop filter function. When set to 1, the ingress
20674                                                  *   loop filter is enabled. This can be enabled regardless
20675                                                  *   of the DLR ENABLE state, allowing the loop filter function
20676                                                  *   to operate when DLR is not used.                                          */
20677             uint32_t                    : 1;
20678             __IOM uint32_t IGNORE_INVTM : 1;    /*!< [4..4] Enable ignore beacon frames with invalid timeout timer.
20679                                                  *   When enabled (set to 1) frames with timeout timer value
20680                                                  *   not within a range of 200 microseconds to 500 milliseconds
20681                                                  *   are ignored and parameters are not locally stored or considered
20682                                                  *   for state transitions. The invalid timeout timer value
20683                                                  *   is always stored within the DLR_INV_TMOUT register irrespective
20684                                                  *   of the value of this bit. Ignored frames are forwarded
20685                                                  *   normally.                                                                 */
20686             uint32_t               : 3;
20687             __IOM uint32_t US_TIME : 12;        /*!< [19..8] Number of clock cycles required for 1 microsecond for
20688                                                  *   the switch operating clock. This LSI operates at 200 MHz,
20689                                                  *   therefore this register must be set to 0xC8. The value
20690                                                  *   after reset must be changed.                                              */
20691             uint32_t : 12;
20692         } DLR_CONTROL_b;
20693     };
20694 
20695     union
20696     {
20697         __IM uint32_t DLR_STATUS;             /*!< (@ 0x00003C04) DLR Status Register                                        */
20698 
20699         struct
20700         {
20701             __IM uint32_t LastBcnRcvPort : 2; /*!< [1..0] Last Beacon Receive Port                                           */
20702             uint32_t                     : 6;
20703             __IM uint32_t NODE_STATE     : 8; /*!< [15..8] Local Node Current State                                          */
20704             __IM uint32_t LINK_STATUS    : 2; /*!< [17..16] Link Status                                                      */
20705             uint32_t                     : 6;
20706             __IM uint32_t TOPOLOGY       : 8; /*!< [31..24] Current Network Topology                                         */
20707         } DLR_STATUS_b;
20708     };
20709 
20710     union
20711     {
20712         __IOM uint32_t DLR_ETH_TYP;          /*!< (@ 0x00003C08) DLR Ethernet Type Register                                 */
20713 
20714         struct
20715         {
20716             __IOM uint32_t DLR_ETH_TYP : 16; /*!< [15..0] Ethernet type to compare for DLR frame detection (initial
20717                                               *   value is 0x80E1)                                                          */
20718             uint32_t : 16;
20719         } DLR_ETH_TYP_b;
20720     };
20721 
20722     union
20723     {
20724         __IOM uint32_t DLR_IRQ_CONTROL;               /*!< (@ 0x00003C0C) DLR Interrupt Control Register                             */
20725 
20726         struct
20727         {
20728             __IOM uint32_t IRQ_state_chng_ena    : 1; /*!< [0..0] Enable Interrupt for State Change                                  */
20729             __IOM uint32_t IRQ_flush_macaddr_ena : 1; /*!< [1..1] Enable Flush Local MAC Address Table Interrupt.                    */
20730             __IOM uint32_t IRQ_stop_nbchk0_ena   : 1; /*!< [2..2] Enable Stop Request Neighbor Check Timeout Timer Interrupt
20731                                                        *   for Port 0.                                                               */
20732             __IOM uint32_t IRQ_stop_nbchk1_ena : 1;   /*!< [3..3] Enable Stop Request Neighbor Check Timeout Timer Interrupt
20733                                                        *   for Port 1.                                                               */
20734             __IOM uint32_t IRQ_bec_tmr0_exp_ena : 1;  /*!< [4..4] IRQ_bec_tmr0_exp_ena                                               */
20735             __IOM uint32_t IRQ_bec_tmr1_exp_ena : 1;  /*!< [5..5] Enable Interrupt on Beacon Timeout Timer Expire for Port
20736                                                        *   1.                                                                        */
20737             __IOM uint32_t IRQ_supr_chng_ena  : 1;    /*!< [6..6] Enable Interrupt on Ring Supervisor Change.                        */
20738             __IOM uint32_t IRQ_link_chng0_ena : 1;    /*!< [7..7] Enable Link Status Change Interrupt Event for Port 0.              */
20739             __IOM uint32_t IRQ_link_chng1_ena : 1;    /*!< [8..8] Enable Link Status Change Interrupt Event for Port 1.              */
20740             __IOM uint32_t IRQ_sup_ignord_ena : 1;    /*!< [9..9] Enable interrupt on beacon frame detection from a supervisor
20741                                                        *   with lower precedence than the current ring supervisor
20742                                                        *   or lower numeric value for MAC address when precedence
20743                                                        *   is same.                                                                  */
20744             __IOM uint32_t IRQ_ip_addr_chng_ena : 1;  /*!< [10..10] Enable interrupt on IP address change detection within
20745                                                        *   beacon frame from ring supervisor.                                        */
20746             __IOM uint32_t IRQ_invalid_tmr_ena : 1;   /*!< [11..11] Enable interrupt on invalid range for beacon timeout
20747                                                        *   timer value detection.                                                    */
20748             __IOM uint32_t IRQ_bec_rcv0_ena : 1;      /*!< [12..12] Enable interrupt on beacon frame detection on port
20749                                                        *   0.                                                                        */
20750             __IOM uint32_t IRQ_bec_rcv1_ena : 1;      /*!< [13..13] Enable interrupt on beacon frame detection on port
20751                                                        *   1.                                                                        */
20752             __IOM uint32_t IRQ_frm_dscrd0 : 1;        /*!< [14..14] Enable interrupt on frame discard due to source address
20753                                                        *   match with the local address on port 0.                                   */
20754             __IOM uint32_t IRQ_frm_dscrd1 : 1;        /*!< [15..15] Enable Interrupt on Frame discard due to source address
20755                                                        *   match with the local address on port 1.                                   */
20756             uint32_t                  : 13;
20757             __IOM uint32_t low_int_en : 1;            /*!< [29..29] Enable active-low interrupt. Asserted to use active-low
20758                                                        *   interrupt signal instead of active-high interrupt signal.                 */
20759             __OM uint32_t atomic_OR : 1;              /*!< [30..30] When set during a register-write, the enable bits are
20760                                                        *   ORed into the current setting of the register. By writing
20761                                                        *   this bit at the same time, only the target bit can be set
20762                                                        *   to 1.                                                                     */
20763             __OM uint32_t atomic_AND : 1;             /*!< [31..31] When set during a register-write, the enable bits are
20764                                                        *   ANDed with the current setting of the register. By writing
20765                                                        *   this bit at the same time, only the target bit can be set
20766                                                        *   to 0.                                                                     */
20767         } DLR_IRQ_CONTROL_b;
20768     };
20769 
20770     union
20771     {
20772         __IOM uint32_t DLR_IRQ_STAT_ACK;                /*!< (@ 0x00003C10) DLR Interrupt Status/ACK Register                          */
20773 
20774         struct
20775         {
20776             __IOM uint32_t state_chng_IRQ_pending : 1;  /*!< [0..0] Latched State Change Event                                         */
20777             __IOM uint32_t flush_IRQ_pending      : 1;  /*!< [1..1] Latched Flush Event for MAC Address Learning Table                 */
20778             __IOM uint32_t nbchk0_IRQ_pending     : 1;  /*!< [2..2] Stop Request Event for Neighbor Check Timeout Timer for
20779                                                          *   Port 0                                                                    */
20780             __IOM uint32_t nbchk1_IRQ_pending : 1;      /*!< [3..3] Stop Request Event for Neighbor Check Timeout Timer for
20781                                                          *   Port 1                                                                    */
20782             __IOM uint32_t bec_tmr0_IRQ_pending   : 1;  /*!< [4..4] Beacon Timeout Timer Expire Event for Port 0                       */
20783             __IOM uint32_t bec_tmr1_IRQ_pending   : 1;  /*!< [5..5] Beacon Timeout Timer Expire Event for Port 1                       */
20784             __IOM uint32_t supr_chng_IRQ_pending  : 1;  /*!< [6..6] Latched Supervisor Change Event                                    */
20785             __IOM uint32_t Link0_IRQ_pending      : 1;  /*!< [7..7] Latched Link Status Change Event for Port 0                        */
20786             __IOM uint32_t Link1_IRQ_pending      : 1;  /*!< [8..8] Latched Link Status Change Event for Port 1                        */
20787             __IOM uint32_t sup_ignord_IRQ_pending : 1;  /*!< [9..9] Latched Event for Beacon Frame Detection from Ignored
20788                                                          *   Supervisor                                                                */
20789             __IOM uint32_t ip_chng_IRQ_pending     : 1; /*!< [10..10] Latched IP Address Change Event                                  */
20790             __IOM uint32_t invalid_tmr_IRQ_pending : 1; /*!< [11..11] Latched Event on Invalid Beacon Timeout Timer Value
20791                                                          *  Detection Within Beacon Frame on Port 0 or Port 1                         */
20792             __IOM uint32_t bec_rcv0_IRQ_pending   : 1;  /*!< [12..12] Latched Event on Beacon Frame Detection on Port 0                */
20793             __IOM uint32_t bec_rcv1_IRQ_pending   : 1;  /*!< [13..13] Latched Event on Beacon Frame Detection on Port 1                */
20794             __IOM uint32_t frm_dscrd0_IRQ_pending : 1;  /*!< [14..14] Latched Event on Frame Discard Due to Source Address
20795                                                          *   Match with the Local Address on Port 0 (Loop Filter)                      */
20796             __IOM uint32_t frm_dscrd1_IRQ_pending : 1;  /*!< [15..15] Latched Event on Frame Discard Due to Source Address
20797                                                          *   Match with the Local Address on Port 1 (Loop Filter)                      */
20798             uint32_t : 16;
20799         } DLR_IRQ_STAT_ACK_b;
20800     };
20801 
20802     union
20803     {
20804         __IOM uint32_t DLR_LOC_MAClo;    /*!< (@ 0x00003C14) DLR Local MAC Address Low Register                         */
20805 
20806         struct
20807         {
20808             __IOM uint32_t LOC_MAC : 32; /*!< [31..0] First 4 octets of the Local MAC address for loop filter           */
20809         } DLR_LOC_MAClo_b;
20810     };
20811 
20812     union
20813     {
20814         __IOM uint32_t DLR_LOC_MAChi;    /*!< (@ 0x00003C18) DLR Local MAC Address High Register                        */
20815 
20816         struct
20817         {
20818             __IOM uint32_t LOC_MAC : 16; /*!< [15..0] Last 2 octets of local MAC address for loop filter                */
20819             uint32_t               : 16;
20820         } DLR_LOC_MAChi_b;
20821     };
20822     __IM uint32_t RESERVED103;
20823 
20824     union
20825     {
20826         __IM uint32_t DLR_SUPR_MAClo;    /*!< (@ 0x00003C20) DLR Supervisor MAC Address Low Register                    */
20827 
20828         struct
20829         {
20830             __IM uint32_t SUPR_MAC : 32; /*!< [31..0] First 4 octets of the active ring supervisor of the
20831                                           *   MAC address extracted from the Source Address field of
20832                                           *   the beacon frame.                                                         */
20833         } DLR_SUPR_MAClo_b;
20834     };
20835 
20836     union
20837     {
20838         __IM uint32_t DLR_SUPR_MAChi;    /*!< (@ 0x00003C24) DLR Supervisor MAC Address High Register                   */
20839 
20840         struct
20841         {
20842             __IM uint32_t SUPR_MAC : 16; /*!< [15..0] Last 2 octets of the active ring supervisor of the MAC
20843                                           *   address extracted from the Source Address field of the
20844                                           *   beacon frame.                                                             */
20845             __IM uint32_t PRECE : 8;     /*!< [23..16] Precedence value of the ring supervisor extracted from
20846                                           *   the Supervisor precedence field of the beacon frame.                      */
20847             uint32_t : 8;
20848         } DLR_SUPR_MAChi_b;
20849     };
20850 
20851     union
20852     {
20853         __IM uint32_t DLR_STATE_VLAN;     /*!< (@ 0x00003C28) DLR Ring Status/VLAN Register                              */
20854 
20855         struct
20856         {
20857             __IM uint32_t RINGSTAT : 8;   /*!< [7..0] DLR ring state extracted from the Ring State field of
20858                                            *   the beacon frame.                                                         */
20859             __IM uint32_t VLANVALID : 1;  /*!< [8..8] VLAN Valid                                                         */
20860             uint32_t                : 7;
20861             __IM uint32_t VLANINFO  : 16; /*!< [31..16] IEEE 802.1Q VLAN Tag control field extracted from the
20862                                            *   VLAN info field of the beacon frame.                                      */
20863         } DLR_STATE_VLAN_b;
20864     };
20865 
20866     union
20867     {
20868         __IM uint32_t DLR_BEC_TMOUT;      /*!< (@ 0x00003C2C) DLR Beacon Timeout Register                                */
20869 
20870         struct
20871         {
20872             __IM uint32_t BEC_TMOUT : 32; /*!< [31..0] Beacon timeout timer value extracted from the Beacon
20873                                            *   Timeout in microseconds field of the beacon frame.                        */
20874         } DLR_BEC_TMOUT_b;
20875     };
20876 
20877     union
20878     {
20879         __IM uint32_t DLR_BEC_INTRVL;      /*!< (@ 0x00003C30) DLR Beacon Interval Register                               */
20880 
20881         struct
20882         {
20883             __IM uint32_t BEC_INTRVL : 32; /*!< [31..0] Beacon interval extracted from the Beacon Interval field
20884                                             *   of the beacon frame                                                       */
20885         } DLR_BEC_INTRVL_b;
20886     };
20887 
20888     union
20889     {
20890         __IM uint32_t DLR_SUPR_IPADR;      /*!< (@ 0x00003C34) DLR Supervisor IP Address Register                         */
20891 
20892         struct
20893         {
20894             __IM uint32_t SUPR_IPADR : 32; /*!< [31..0] IP address of the ring supervisor extracted from the
20895                                             *   Source IP address field of the beacon frame. A value of
20896                                             *   0x0 can be received when supervisor has no IP address.                    */
20897         } DLR_SUPR_IPADR_b;
20898     };
20899 
20900     union
20901     {
20902         __IM uint32_t DLR_ETH_STYP_VER; /*!< (@ 0x00003C38) DLR Sub Type/Protocol Version Register                     */
20903 
20904         struct
20905         {
20906             __IM uint32_t SUBTYPE : 8;  /*!< [7..0] DLR Ring Ether Sub Type extracted from the Ring Sub Type
20907                                          *   field of the beacon frame.                                                */
20908             __IM uint32_t PROTVER : 8;  /*!< [15..8] DLR Ring Protocol Version extracted from the Ring Protocol
20909                                          *   Version field of the beacon frame.                                        */
20910             __IM uint32_t SPORT : 8;    /*!< [23..16] Source port extracted from the Source Port field of
20911                                          *   the beacon frame.                                                         */
20912             uint32_t : 8;
20913         } DLR_ETH_STYP_VER_b;
20914     };
20915 
20916     union
20917     {
20918         __IM uint32_t DLR_INV_TMOUT;      /*!< (@ 0x00003C3C) DLR Beacon Timeout Timer Register                          */
20919 
20920         struct
20921         {
20922             __IM uint32_t INV_TMOUT : 32; /*!< [31..0] Last out of range Beacon timeout timer value extracted
20923                                            *   from beacon frame on any of the port.                                     */
20924         } DLR_INV_TMOUT_b;
20925     };
20926 
20927     union
20928     {
20929         __IM uint32_t DLR_SEQ_ID;      /*!< (@ 0x00003C40) DLR Sequence ID Register                                   */
20930 
20931         struct
20932         {
20933             __IM uint32_t SEQ_ID : 32; /*!< [31..0] Sequence ID of the last beacon frame extracted from
20934                                         *   the Sequence ID field of the beacon frame on port 0 or
20935                                         *   port 1. Sequence ID of the ignored frames is not stored.                  */
20936         } DLR_SEQ_ID_b;
20937     };
20938     __IM uint32_t RESERVED104[5];
20939 
20940     union
20941     {
20942         __IOM uint32_t DLR_DSTlo;        /*!< (@ 0x00003C58) DLR Beacon Destination Address Low Register                */
20943 
20944         struct
20945         {
20946             __IOM uint32_t DLR_DST : 32; /*!< [31..0] First 4 octets of the beacon frame destination multicast
20947                                           *   address (01-21-6C-00-00-01).                                              */
20948         } DLR_DSTlo_b;
20949     };
20950 
20951     union
20952     {
20953         __IOM uint32_t DLR_DSThi;        /*!< (@ 0x00003C5C) DLR Beacon Destination Address High Register               */
20954 
20955         struct
20956         {
20957             __IOM uint32_t DLR_DST : 16; /*!< [15..0] Last 2 octets of the beacon frame destination multicast
20958                                           *   address (01-21-6C-00-00-01).                                              */
20959             uint32_t : 16;
20960         } DLR_DSThi_b;
20961     };
20962 
20963     union
20964     {
20965         __IM uint32_t DLR_RX_STAT0;      /*!< (@ 0x00003C60) DLR Received Frame Statistic Register 0                    */
20966 
20967         struct
20968         {
20969             __IM uint32_t RX_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 0                        */
20970         } DLR_RX_STAT0_b;
20971     };
20972 
20973     union
20974     {
20975         __IM uint32_t DLR_RX_ERR_STAT0;      /*!< (@ 0x00003C64) DLR Received Frame Error Statistic Register 0              */
20976 
20977         struct
20978         {
20979             __IM uint32_t RX_ERR_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port
20980                                               *   0                                                                         */
20981         } DLR_RX_ERR_STAT0_b;
20982     };
20983     __IM uint32_t RESERVED105;
20984 
20985     union
20986     {
20987         __IOM uint32_t DLR_RX_LF_STAT0;     /*!< (@ 0x00003C6C) DLR Received Frame Loop Filter Statistic Register
20988                                              *                  0                                                          */
20989 
20990         struct
20991         {
20992             __IOM uint32_t RX_LF_STAT0 : 8; /*!< [7..0] Number of discarded frames in port 0 due to loop filtering
20993                                              *   when LOOP_FILTER_ENA is set to 1. Saturates at 255.                       */
20994             uint32_t : 24;
20995         } DLR_RX_LF_STAT0_b;
20996     };
20997 
20998     union
20999     {
21000         __IM uint32_t DLR_RX_STAT1;      /*!< (@ 0x00003C70) DLR Received Frame Statistic Register 1                    */
21001 
21002         struct
21003         {
21004             __IM uint32_t RX_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 1                        */
21005         } DLR_RX_STAT1_b;
21006     };
21007 
21008     union
21009     {
21010         __IM uint32_t DLR_RX_ERR_STAT1;      /*!< (@ 0x00003C74) DLR Received Frame Error Statistic Register 1              */
21011 
21012         struct
21013         {
21014             __IM uint32_t RX_ERR_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port
21015                                               *   1                                                                         */
21016         } DLR_RX_ERR_STAT1_b;
21017     };
21018     __IM uint32_t RESERVED106;
21019 
21020     union
21021     {
21022         __IOM uint32_t DLR_RX_LF_STAT1;     /*!< (@ 0x00003C7C) DLR Received Frame Loop Filter Statistic Register
21023                                              *                  1                                                          */
21024 
21025         struct
21026         {
21027             __IOM uint32_t RX_LF_STAT1 : 8; /*!< [7..0] Number of discarded frames in port 1 due to loop filtering
21028                                              *   when LOOP_FILTER_ENA is set to 1. Saturates at 255.                       */
21029             uint32_t : 24;
21030         } DLR_RX_LF_STAT1_b;
21031     };
21032     __IM uint32_t RESERVED107[32];
21033 
21034     union
21035     {
21036         __IOM uint32_t PRP_CONFIG;               /*!< (@ 0x00003D00) PRP Configuration Register                                 */
21037 
21038         struct
21039         {
21040             __IOM uint32_t PRP_ENA       : 1;    /*!< [0..0] Enable PRP Operation                                               */
21041             __IOM uint32_t RX_DUP_ACCEPT : 1;    /*!< [1..1] Enable Duplicate Accept Mode of Operation at Receive               */
21042             __IOM uint32_t RX_REMOVE_RCT : 1;    /*!< [2..2] Allow PRP Port RX to Remove the RCT                                */
21043             __IOM uint32_t TX_RCT_MODE   : 2;    /*!< [4..3] Control Appending the RCT to Transmitted Frames on the
21044                                                   *   Redundant Ports                                                           */
21045             __IOM uint32_t TX_RCT_BROADCAST : 1; /*!< [5..5] Should be 1 normally.                                              */
21046             __IOM uint32_t TX_RCT_MULTICAST : 1; /*!< [6..6] Should be 1 normally.                                              */
21047             __IOM uint32_t TX_RCT_UNKNOWN   : 1; /*!< [7..7] Should be 1 normally.                                              */
21048             __IOM uint32_t TX_RCT_1588      : 1; /*!< [8..8] Setting this bit affects IEEE 1588 frames that are forwarded
21049                                                   *   through the switch (for example, when used as RedBox) to
21050                                                   *   both PRP_GROUP ports. Locally generated IEEE 1588 frames
21051                                                   *   (peer-delay request/response) are not affected by this
21052                                                   *   setting.                                                                  */
21053             __IOM uint32_t RCT_LEN_CHK_DIS : 1;  /*!< [9..9] When set to 1, disables the RCT length field checking
21054                                                   *   against the actual frame length.                                          */
21055             uint32_t                   : 6;
21056             __IOM uint32_t PRP_AGE_ENA : 1;      /*!< [16..16] Enable History Memory Aging Timer                                */
21057             uint32_t                   : 15;
21058         } PRP_CONFIG_b;
21059     };
21060 
21061     union
21062     {
21063         __IOM uint32_t PRP_GROUP;         /*!< (@ 0x00003D04) PRP Port Group Register                                    */
21064 
21065         struct
21066         {
21067             __IOM uint32_t PRP_GROUP : 3; /*!< [2..0] Defines which two ports should be treated as redundant
21068                                            *   ports for PRP.                                                            */
21069             uint32_t                 : 13;
21070             __IOM uint32_t LANB_MASK : 3; /*!< [18..16] Defines which of the ports is considered the LAN B
21071                                            *   port.                                                                     */
21072             uint32_t : 13;
21073         } PRP_GROUP_b;
21074     };
21075 
21076     union
21077     {
21078         __IOM uint32_t PRP_SUFFIX;          /*!< (@ 0x00003D08) PRP RCT Suffix                                             */
21079 
21080         struct
21081         {
21082             __IOM uint32_t PRP_SUFFIX : 16; /*!< [15..0] The Redundancy Control Trailer (RCT) suffix (initial
21083                                              *   value is 0x88FB)                                                          */
21084             uint32_t : 16;
21085         } PRP_SUFFIX_b;
21086     };
21087 
21088     union
21089     {
21090         __IOM uint32_t PRP_LANID;      /*!< (@ 0x00003D0C) PRP LAN Identifier                                         */
21091 
21092         struct
21093         {
21094             __IOM uint32_t LANAID : 4; /*!< [3..0] LAN A Identifier                                                   */
21095             __IOM uint32_t LANBID : 4; /*!< [7..4] LAN B Identifier                                                   */
21096             uint32_t              : 24;
21097         } PRP_LANID_b;
21098     };
21099 
21100     union
21101     {
21102         __IOM uint32_t DUP_W;          /*!< (@ 0x00003D10) PRP Max Duplicate Detection Window Size                    */
21103 
21104         struct
21105         {
21106             __IOM uint32_t DUP_W : 8;  /*!< [7..0] Maximum Duplicate Detect Window Size                               */
21107             uint32_t             : 24;
21108         } DUP_W_b;
21109     };
21110 
21111     union
21112     {
21113         __IOM uint32_t PRP_AGETIME;          /*!< (@ 0x00003D14) PRP Aging Time Define Register                             */
21114 
21115         struct
21116         {
21117             __IOM uint32_t PRP_AGETIME : 24; /*!< [23..0] Timeout in steps of 32 switch operating clock cycles
21118                                               *   to control aging of duplicate history data.                               */
21119             uint32_t : 8;
21120         } PRP_AGETIME_b;
21121     };
21122 
21123     union
21124     {
21125         __IOM uint32_t PRP_IRQ_CONTROL;    /*!< (@ 0x00003D18) PRP Interrupt Control Register                             */
21126 
21127         struct
21128         {
21129             __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Enable Interrupt for Memory Error Indications.                     */
21130             __IOM uint32_t WRONGLAN   : 1; /*!< [1..1] Enable interrupt for frames received at a redundant port
21131                                             *   with an invalid LAN identifier in its redundancy trailer.                 */
21132             __IOM uint32_t OUTOFSEQ : 1;   /*!< [2..2] Enable interrupt for frames received and accepted but
21133                                             *   have an unexpected sequence number.                                       */
21134             __IOM uint32_t SEQMISSING : 1; /*!< [3..3] Enable interrupt for frames received and accepted that
21135                                             *   caused the history to skip a sequence number that was never
21136                                             *   received (for example, a missing sequence number is being
21137                                             *   ignored and is now treated as a candidate for dropping).                  */
21138             uint32_t : 28;
21139         } PRP_IRQ_CONTROL_b;
21140     };
21141 
21142     union
21143     {
21144         __IOM uint32_t PRP_IRQ_STAT_ACK;   /*!< (@ 0x00003D1C) PRP Interrupt Status/ACK Register                          */
21145 
21146         struct
21147         {
21148             __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Interrupt Pending Indication                                       */
21149             __IOM uint32_t WRONGLAN   : 1; /*!< [1..1] This bit functions the same as MEMTOOLATE bit.                     */
21150             __IOM uint32_t OUTOFSEQ   : 1; /*!< [2..2] This bit functions the same as MEMTOOLATE bit.                     */
21151             __IOM uint32_t SEQMISSING : 1; /*!< [3..3] This bit functions the same as MEMTOOLATE bit.                     */
21152             uint32_t                  : 28;
21153         } PRP_IRQ_STAT_ACK_b;
21154     };
21155 
21156     union
21157     {
21158         __IOM uint32_t RM_ADDR_CTRL;           /*!< (@ 0x00003D20) PRP History Memory Transactions Control Register           */
21159 
21160         struct
21161         {
21162             __IOM uint32_t address       : 12; /*!< [11..0] Memory Address for Read and Write Transactions                    */
21163             uint32_t                     : 10;
21164             __IOM uint32_t CLEAR_DYNAMIC : 1;  /*!< [22..22] When set to 1, scan the complete table for valid dynamic
21165                                                 *   history entries and deletes them (writes entry with all
21166                                                 *   0s).                                                                      */
21167             __IOM uint32_t CLEAR_MEMORY : 1;   /*!< [23..23] When set to 1, write all memory locations with 0.                */
21168             uint32_t                    : 1;
21169             __IOM uint32_t WRITE        : 1;   /*!< [25..25] When set to 1, perform a Single Write Transaction.               */
21170             __IOM uint32_t READ         : 1;   /*!< [26..26] When set to 1, perform Single Read Transaction.                  */
21171             uint32_t                    : 2;
21172             __IOM uint32_t CLEAR        : 1;   /*!< [29..29] When set to 1, write all 0s to the entry selected by
21173                                                 *   the given address.                                                        */
21174             uint32_t           : 1;
21175             __IM uint32_t BUSY : 1;            /*!< [31..31] Transaction Busy Indication                                      */
21176         } RM_ADDR_CTRL_b;
21177     };
21178 
21179     union
21180     {
21181         __IOM uint32_t RM_DATA;          /*!< (@ 0x00003D24) PRP Memory Data Register                                   */
21182 
21183         struct
21184         {
21185             __IOM uint32_t RM_DATA : 32; /*!< [31..0] Memory data register for read/write transactions controlled
21186                                           *   by RM_ADDR_CTRL.                                                          */
21187         } RM_DATA_b;
21188     };
21189 
21190     union
21191     {
21192         __IOM uint32_t RM_DATA_HI;          /*!< (@ 0x00003D28) PRP Memory Data Higher Register                            */
21193 
21194         struct
21195         {
21196             __IOM uint32_t RM_DATA_HI : 32; /*!< [31..0] A Second Data Register                                            */
21197         } RM_DATA_HI_b;
21198     };
21199 
21200     union
21201     {
21202         __IM uint32_t RM_STATUS;           /*!< (@ 0x00003D2C) PRP Memory Controller Status Indication                    */
21203 
21204         struct
21205         {
21206             __IM uint32_t ageaddress : 12; /*!< [11..0] Address of an entry which the aging process inspects
21207                                             *   when the aging timer expires next time.                                   */
21208             uint32_t : 20;
21209         } RM_STATUS_b;
21210     };
21211 
21212     union
21213     {
21214         __IOM uint32_t TxSeqTooLate;         /*!< (@ 0x00003D30) PRP Frame Transmission Retrieval of Failed Sequence        */
21215 
21216         struct
21217         {
21218             __IOM uint32_t TxSeqTooLate : 4; /*!< [3..0] Retrieval of a Sequence Number Failed                              */
21219             uint32_t                    : 28;
21220         } TxSeqTooLate_b;
21221     };
21222 
21223     union
21224     {
21225         __IM uint32_t CntErrWrongLanA;          /*!< (@ 0x00003D34) PRP Wrong ID LAN-A Count Register                          */
21226 
21227         struct
21228         {
21229             __IM uint32_t CntErrWrongLanA : 32; /*!< [31..0] Valid frames received on LAN A which have an RCT (valid
21230                                                  *   length + suffix) but LAN ID is not matching LAN A.                        */
21231         } CntErrWrongLanA_b;
21232     };
21233 
21234     union
21235     {
21236         __IM uint32_t CntErrWrongLanB;          /*!< (@ 0x00003D38) PRP Wrong ID LAN-B Count Register                          */
21237 
21238         struct
21239         {
21240             __IM uint32_t CntErrWrongLanB : 32; /*!< [31..0] Valid frames received on LAN B which have an RCT (valid
21241                                                  *   length + suffix) but LAN ID is not matching LAN B.                        */
21242         } CntErrWrongLanB_b;
21243     };
21244 
21245     union
21246     {
21247         __IM uint32_t CntDupLanA;          /*!< (@ 0x00003D3C) PRP Duplicate LAN-A Count Register                         */
21248 
21249         struct
21250         {
21251             __IM uint32_t CntDupLanA : 32; /*!< [31..0] Valid frames received on LAN A that were dropped by
21252                                             *   duplicate detection.                                                      */
21253         } CntDupLanA_b;
21254     };
21255 
21256     union
21257     {
21258         __IM uint32_t CntDupLanB;          /*!< (@ 0x00003D40) PRP Duplicate LAN-B Count Register                         */
21259 
21260         struct
21261         {
21262             __IM uint32_t CntDupLanB : 32; /*!< [31..0] Valid frames received on LAN B that were dropped by
21263                                             *   duplicate detection.                                                      */
21264         } CntDupLanB_b;
21265     };
21266 
21267     union
21268     {
21269         __IM uint32_t CntOutOfSeqLowA;          /*!< (@ 0x00003D44) PRP Sequence Error Low LAN-A Count Register                */
21270 
21271         struct
21272         {
21273             __IM uint32_t CntOutOfSeqLowA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with a sequence
21274                                                  *   number less than last window (DUP_W).                                     */
21275         } CntOutOfSeqLowA_b;
21276     };
21277 
21278     union
21279     {
21280         __IM uint32_t CntOutOfSeqLowB;          /*!< (@ 0x00003D48) PRP Sequence Error Low LAN-B Count Register                */
21281 
21282         struct
21283         {
21284             __IM uint32_t CntOutOfSeqLowB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with a sequence
21285                                                  *   number less than last window (DUP_W).                                     */
21286         } CntOutOfSeqLowB_b;
21287     };
21288 
21289     union
21290     {
21291         __IM uint32_t CntOutOfSeqA;          /*!< (@ 0x00003D4C) PRP Sequence Error LAN-A Count Register                    */
21292 
21293         struct
21294         {
21295             __IM uint32_t CntOutOfSeqA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with an
21296                                               *   unexpected sequence number.                                               */
21297         } CntOutOfSeqA_b;
21298     };
21299 
21300     union
21301     {
21302         __IM uint32_t CntOutOfSeqB;          /*!< (@ 0x00003D50) PRP Sequence Error LAN-B Count Register                    */
21303 
21304         struct
21305         {
21306             __IM uint32_t CntOutOfSeqB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with an
21307                                               *   unexpected sequence number.                                               */
21308         } CntOutOfSeqB_b;
21309     };
21310 
21311     union
21312     {
21313         __IM uint32_t CntAcceptA;          /*!< (@ 0x00003D54) PRP Valid Frame LAN-A Count Register                       */
21314 
21315         struct
21316         {
21317             __IM uint32_t CntAcceptA : 32; /*!< [31..0] Valid frames received on LAN A which had a valid sequence
21318                                             *   number in the expected range.                                             */
21319         } CntAcceptA_b;
21320     };
21321 
21322     union
21323     {
21324         __IM uint32_t CntAcceptB;          /*!< (@ 0x00003D58) PRP Valid Frame LAN-B Count Register                       */
21325 
21326         struct
21327         {
21328             __IM uint32_t CntAcceptB : 32; /*!< [31..0] Valid frames received on LAN B which had a valid sequence
21329                                             *   number in the expected range.                                             */
21330         } CntAcceptB_b;
21331     };
21332 
21333     union
21334     {
21335         __IM uint32_t CntMissing;          /*!< (@ 0x00003D5C) PRP Drop History Adjustment Count                          */
21336 
21337         struct
21338         {
21339             __IM uint32_t CntMissing : 32; /*!< [31..0] Indicates adjustment of the drop history as a frame
21340                                             *   was received with a sequence number of expected + history
21341                                             + 1. This occurs if the same frame was dropped in both
21342                                             +   LAN segments (one sequence number is missing) and the history
21343                                             +   is now extended beyond that sequence number (causing it
21344                                             +   to be treated as drop allowed).                                           */
21345         } CntMissing_b;
21346     };
21347     __IM uint32_t RESERVED108[40];
21348 
21349     union
21350     {
21351         __IOM uint32_t HUB_CONFIG;             /*!< (@ 0x00003E00) HUB Configuration Register                                 */
21352 
21353         struct
21354         {
21355             __IOM uint32_t HUB_ENA        : 1; /*!< [0..0] Enable Integrated HUB Operation                                    */
21356             __IOM uint32_t RETRANSMIT_ENA : 1; /*!< [1..1] Enable Hub Retransmit Capability                                   */
21357             __IOM uint32_t TRIGGER_MODE   : 1; /*!< [2..2] Enable Single Frame Trigger Mode                                   */
21358             __IOM uint32_t HUB_ISOLATE    : 1; /*!< [3..3] Isolate all hub ports from the other ports of the switch
21359                                                 *   and allow communication with management port only. It is
21360                                                 *   then up to the application of the management port to implement
21361                                                 *   some bridging functionality to other ports as required.                   */
21362             __IOM uint32_t TIMER_SEL     : 1;  /*!< [4..4] Select the timer to use for timed triggers                         */
21363             uint32_t                     : 1;
21364             __IOM uint32_t IPG_WAIT      : 3;  /*!< [8..6] IPG_WAIT                                                           */
21365             __IOM uint32_t CRS_GEN       : 1;  /*!< [9..9] CRS_GEN                                                            */
21366             __IOM uint32_t PRMB_GEN_DIS  : 1;  /*!< [10..10] PRMB_GEN_DIS                                                     */
21367             __IOM uint32_t JAM_WAIT_IDLE : 1;  /*!< [11..11] JAM_WAIT_IDLE                                                    */
21368             uint32_t                     : 20;
21369         } HUB_CONFIG_b;
21370     };
21371 
21372     union
21373     {
21374         __IOM uint32_t HUB_GROUP;         /*!< (@ 0x00003E04) HUB Port Group Register                                    */
21375 
21376         struct
21377         {
21378             __IOM uint32_t HUB_GROUP : 3; /*!< [2..0] Define all ports that should be combined to a Hub Group.           */
21379             uint32_t                 : 29;
21380         } HUB_GROUP_b;
21381     };
21382 
21383     union
21384     {
21385         __IOM uint32_t HUB_DEFPORT;         /*!< (@ 0x00003E08) HUB Default Port Selection Register                        */
21386 
21387         struct
21388         {
21389             __IOM uint32_t HUB_DEFPORT : 3; /*!< [2..0] The default port within the Hub Group where all traffic
21390                                              *   from a port outside the group is forwarded to port (bit
21391                                              *   0 = port 0, bit 1 = port 1, and bit 2 = port 2). If a frame
21392                                              *   should be forwarded to any of the hub ports, the frame
21393                                              *   is sent to this port only. The copy function of the hub
21394                                              *   copies it to all PHY interfaces of the group eventually.                  */
21395             uint32_t : 29;
21396         } HUB_DEFPORT_b;
21397     };
21398 
21399     union
21400     {
21401         __IOM uint32_t HUB_TRIGGER_IMMEDIATE;         /*!< (@ 0x00003E0C) HUB Transmission Trigger Immediate Register                */
21402 
21403         struct
21404         {
21405             __IOM uint32_t HUB_TRIGGER_IMMEDIATE : 3; /*!< [2..0] Trigger immediate transmission of a single frame from
21406                                                        *   given port within the hub group (bit 0 = port 0, bit 1
21407                                                        *   = port 1, and bit 2 = port 2).                                            */
21408             uint32_t : 29;
21409         } HUB_TRIGGER_IMMEDIATE_b;
21410     };
21411 
21412     union
21413     {
21414         __IOM uint32_t HUB_TRIGGER_AT;         /*!< (@ 0x00003E10) HUB Transmission Trigger At Register                       */
21415 
21416         struct
21417         {
21418             __IOM uint32_t HUB_TRIGGER_AT : 3; /*!< [2..0] Trigger Transmission of a Single Frame at a Specific
21419                                                 *   Time (bit 0 = port 0, bit 1 = port 1, and bit 2 = port
21420                                                 *   2).                                                                       */
21421             uint32_t : 29;
21422         } HUB_TRIGGER_AT_b;
21423     };
21424 
21425     union
21426     {
21427         __IOM uint32_t HUB_TTIME;          /*!< (@ 0x00003E14) HUB Transmission Time Define Register                      */
21428 
21429         struct
21430         {
21431             __IOM uint32_t HUB_TTIME : 32; /*!< [31..0] Define the Time Value when a Trigger Should Occur                 */
21432         } HUB_TTIME_b;
21433     };
21434 
21435     union
21436     {
21437         __IOM uint32_t HUB_IRQ_CONTROL;           /*!< (@ 0x00003E18) HUB Interrupt Control Register                             */
21438 
21439         struct
21440         {
21441             __IOM uint32_t RX_TRIGGER : 3;        /*!< [2..0] Enable Interrupt on Receive Pattern Match Trigger Function         */
21442             __IOM uint32_t CHANGE_DET : 1;        /*!< [3..3] Enable interrupt for hub TX state machine port state
21443                                                    *   change request detection                                                  */
21444             __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] Enable interrupt when hub transmit started after writing
21445                                                    *   the HUB_TRIGGER_IMMEDIATE register                                        */
21446             __IOM uint32_t TRIGGER_TIMER : 1;     /*!< [5..5] Enable interrupt when hub transmit started after writing
21447                                                    *   the HUB_TRIGGER_TIME register and the timeout value is
21448                                                    *   reached (register HUB_TTIME).                                             */
21449             uint32_t : 26;
21450         } HUB_IRQ_CONTROL_b;
21451     };
21452 
21453     union
21454     {
21455         __IOM uint32_t HUB_IRQ_STAT_ACK;          /*!< (@ 0x00003E1C) HUB Interrupt Status/ACK Register                          */
21456 
21457         struct
21458         {
21459             __IOM uint32_t RX_TRIGGER        : 3; /*!< [2..0] Interrupt Pending Indication                                       */
21460             __IOM uint32_t CHANGE_DET        : 1; /*!< [3..3] This bit functions the same as RX_TRIGGER bit.                     */
21461             __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] This bit functions the same as RX_TRIGGER bit.                     */
21462             __IOM uint32_t TRIGGER_TIMER     : 1; /*!< [5..5] This bit functions the same as RX_TRIGGER bit.                     */
21463             uint32_t                         : 26;
21464         } HUB_IRQ_STAT_ACK_b;
21465     };
21466 
21467     union
21468     {
21469         __IM uint32_t HUB_STATUS;                /*!< (@ 0x00003E20) HUB Status Register                                        */
21470 
21471         struct
21472         {
21473             __IM uint32_t PORTS_ACTIVE : 3;      /*!< [2..0] When this bit is 1, it shows the currently active ports
21474                                                   *   of the Hub group which are allowed for transmit.                          */
21475             uint32_t                : 6;
21476             __IM uint32_t TX_ACTIVE : 1;         /*!< [9..9] When this bit is 1, the hub global transmit state machine
21477                                                   *   has successfully entered Hub mode and is now controlling
21478                                                   *   the hub group.                                                            */
21479             __IM uint32_t TX_BUSY : 1;           /*!< [10..10] When this bit is 1, the local device currently transmits
21480                                                   *   data to all ports within the hub group.                                   */
21481             __IM uint32_t Speed_OK : 1;          /*!< [11..11] When this bit is 1, it indicates that the port speed
21482                                                   *   of all group ports match.                                                 */
21483             __IM uint32_t TX_Change_Pending : 1; /*!< [12..12] Indicate a pending change request in the hub transmitter
21484                                                   *   that is unsolved and cause the hub to stop operation (no
21485                                                   *   longer performing any transmissions).                                     */
21486             uint32_t : 19;
21487         } HUB_STATUS_b;
21488     };
21489 
21490     union
21491     {
21492         __IM uint32_t HUB_OPORT_STATUS;         /*!< (@ 0x00003E24) HUB Output Port Status Register                            */
21493 
21494         struct
21495         {
21496             __IM uint32_t HUB_OPORT_STATUS : 3; /*!< [2..0] Per Output Port Data Available Status                              */
21497             uint32_t                       : 29;
21498         } HUB_OPORT_STATUS_b;
21499     };
21500     __IM uint32_t RESERVED109[22];
21501 
21502     union
21503     {
21504         __IOM uint32_t TDMA_CONFIG;             /*!< (@ 0x00003E80) TDMA Configuration Register                                */
21505 
21506         struct
21507         {
21508             __IOM uint32_t TDMA_ENA   : 1;      /*!< [0..0] Enable TDMA Scheduler                                              */
21509             __IM uint32_t  WAIT_START : 1;      /*!< [1..1] Status bit which is set as long as the scheduler is enabled
21510                                                  *   but has not yet reached the time given in register TDMA_START.            */
21511             __IOM uint32_t TIMER_SEL : 1;       /*!< [2..2] Select which timer to use as the time source for the
21512                                                  *   scheduler                                                                 */
21513             uint32_t                    : 1;
21514             __IM uint32_t  RED_PERIOD   : 1;    /*!< [4..4] Read only bit indicating the current period for Profinet           */
21515             __IOM uint32_t RED_OVRD_ENA : 1;    /*!< [5..5] Enables overriding the RED period status, regardless
21516                                                  *   of the indication by the TCV.                                             */
21517             __IOM uint32_t RED_OVRD     : 1;    /*!< [6..6] Override Value for the RED Period                                  */
21518             __OM uint32_t  IN_CT_WREN   : 1;    /*!< [7..7] IN_CT_WREN                                                         */
21519             __OM uint32_t  OUT_CT_WREN  : 1;    /*!< [8..8] Enable writing the OUT_CT_ENA control to the egress ports.         */
21520             __OM uint32_t  HOLD_REQ_CLR : 1;    /*!< [9..9] Writing 1 to this register clears the state of TDMA hold
21521                                                  *   request.                                                                  */
21522             uint32_t                       : 2;
21523             __IM uint32_t TIMER_SEL_ACTIVE : 1; /*!< [12..12] Return the current timer being used for the TDMA Scheduler       */
21524             uint32_t                       : 3;
21525             __IOM uint32_t IN_CT_ENA       : 4; /*!< [19..16] On read, return the current status of the ingress Cut-Through
21526                                                  *   enable indicated by the TDMA scheduler. On write, override
21527                                                  *   the ingress Cut-Through enable if IN_CT_WREN is also 1.                   */
21528             uint32_t                  : 4;
21529             __IOM uint32_t OUT_CT_ENA : 4;      /*!< [27..24] On read, return the current status of the egress Cut-Through
21530                                                  *   enable indicated by the TDMA scheduler. On write, override
21531                                                  *   the egress Cut-Through enable if OUT_CT_WREN is also 1.                   */
21532             uint32_t : 4;
21533         } TDMA_CONFIG_b;
21534     };
21535 
21536     union
21537     {
21538         __IOM uint32_t TDMA_ENA_CTRL;     /*!< (@ 0x00003E84) TDMA Scheduling Enable Control Register                    */
21539 
21540         struct
21541         {
21542             __IOM uint32_t PORT_ENA : 4;  /*!< [3..0] Set to 1 to indicate that a port is operating in TDMA
21543                                            *   mode. When set to 1 for a port, the port does not prefetch
21544                                            *   another frame until the current frame in progress is done
21545                                            *   and if TDMA_PREBUF_DIS in COMMAND_CONFIG is set to 1. This
21546                                            *   helps adding precision to the queue gating operations indicated
21547                                            *   by the TDMA at the expense of loss of line rate.                          */
21548             uint32_t                 : 12;
21549             __IOM uint32_t QGATE_DIS : 8; /*!< [23..16] One bit per output queue. When a bit is set to 1, the
21550                                            *   TDMA scheduler gating commands do not affect the queue
21551                                            *   even if the queue mask in the TCV control data is set to
21552                                            *   1.                                                                        */
21553             __IOM uint32_t QTRIG_DIS : 8; /*!< [31..24] One bit per output queue. When a bit is set to 1, the
21554                                            *   TDMA scheduler triggering commands do not affect the queue
21555                                            *   even if the queue mask in the TCV control data is set to
21556                                            *   1.                                                                        */
21557         } TDMA_ENA_CTRL_b;
21558     };
21559 
21560     union
21561     {
21562         __IOM uint32_t TDMA_START;          /*!< (@ 0x00003E88) TDMA Start Time Set Register                               */
21563 
21564         struct
21565         {
21566             __IOM uint32_t TDMA_START : 32; /*!< [31..0] Set the start time for the very first cycle after system
21567                                              *   initialization has completed. The value is compared with
21568                                              *   the system time (selected in TDMA_CONFIG.TIMER_SEL) and
21569                                              *   when it is reached (crossed), the scheduler begins with
21570                                              *   its first cycle. The 2nd cycle is then at TDMA_START +
21571                                              *   TDMA_CYCLE.                                                               */
21572         } TDMA_START_b;
21573     };
21574 
21575     union
21576     {
21577         __IOM uint32_t TDMA_MODULO;          /*!< (@ 0x00003E8C) TDMA System Timer Modulo                                   */
21578 
21579         struct
21580         {
21581             __IOM uint32_t TDMA_MODULO : 32; /*!< [31..0] The System Timer Modulo                                           */
21582         } TDMA_MODULO_b;
21583     };
21584 
21585     union
21586     {
21587         __IOM uint32_t TDMA_CYCLE;          /*!< (@ 0x00003E90) TDMA Periodic Cycle Set Register                           */
21588 
21589         struct
21590         {
21591             __IOM uint32_t TDMA_CYCLE : 32; /*!< [31..0] The periodic cycle time for the scheduler given in system
21592                                              *   timer time.                                                               */
21593         } TDMA_CYCLE_b;
21594     };
21595 
21596     union
21597     {
21598         __IOM uint32_t TCV_SEQ_ADDR;        /*!< (@ 0x00003E94) TCV Sequence Address Register                              */
21599 
21600         struct
21601         {
21602             __IOM uint32_t TCV_S_ADDR : 12; /*!< [11..0] Address to write to or read from in the TCV sequence
21603                                              *   table.                                                                    */
21604             uint32_t                 : 19;
21605             __IOM uint32_t ADDR_AINC : 1;   /*!< [31..31] When set to 1, read and write operations performed
21606                                              *   using TCV_SEQ_CTRL causes the address in TCV_S_ADDR to
21607                                              *   auto-increment after the operation.                                       */
21608         } TCV_SEQ_ADDR_b;
21609     };
21610 
21611     union
21612     {
21613         __IOM uint32_t TCV_SEQ_CTRL;      /*!< (@ 0x00003E98) TCV Sequence Table Control Register                        */
21614 
21615         struct
21616         {
21617             __IOM uint32_t START : 1;     /*!< [0..0] Indicate this TCV must be executed after the next cycle
21618                                            *   start                                                                     */
21619             __IOM uint32_t INT : 1;       /*!< [1..1] Indicates this TCV generates an interrupt to the CPU
21620                                            *   when activated                                                            */
21621             __IOM uint32_t TCV_D_IDX : 9; /*!< [10..2] Index to the TCV Data Entry                                       */
21622             uint32_t                 : 11;
21623             __IOM uint32_t GPIO      : 8; /*!< [29..22] Generic bits that control the output pins ETHSW_TDMAOUTn
21624                                            *   (n = 0 to 7)                                                              */
21625             uint32_t                 : 1;
21626             __IOM uint32_t READ_MODE : 1; /*!< [31..31] When set to 1, a read operation is performed instead
21627                                            *   of writing to the TCV sequence table. The read data (START,
21628                                            *   INT, TCV_D_IDX[8:0], and GPIO) can be obtained by reading
21629                                            *   this register afterwards. On read, this field always returns
21630                                            *   0.                                                                        */
21631         } TCV_SEQ_CTRL_b;
21632     };
21633 
21634     union
21635     {
21636         __IOM uint32_t TCV_SEQ_LAST;   /*!< (@ 0x00003E9C) TCV Sequence Last Entry                                    */
21637 
21638         struct
21639         {
21640             __IOM uint32_t LAST : 12;  /*!< [11..0] Defines the last entry to read from the TCV sequence
21641                                         *   table when the TDMA scheduler is operating.                               */
21642             uint32_t             : 4;
21643             __IM uint32_t ACTIVE : 12; /*!< [27..16] Return the active TCV sequence entry.                            */
21644             uint32_t             : 4;
21645         } TCV_SEQ_LAST_b;
21646     };
21647 
21648     union
21649     {
21650         __IOM uint32_t TCV_D_ADDR;          /*!< (@ 0x00003EA0) TCV Data Address Register                                  */
21651 
21652         struct
21653         {
21654             __IOM uint32_t ADDR        : 9; /*!< [8..0] Address to read from/write to in the TCV data table                */
21655             uint32_t                   : 22;
21656             __IOM uint32_t AINC_WR_ENA : 1; /*!< [31..31] Auto-Increment Enable                                            */
21657         } TCV_D_ADDR_b;
21658     };
21659 
21660     union
21661     {
21662         __IOM uint32_t TCV_D_OFFSET;          /*!< (@ 0x00003EA4) TCV Data Offset Register                                   */
21663 
21664         struct
21665         {
21666             __IOM uint32_t TCV_D_OFFSET : 32; /*!< [31..0] 32-bit time offset for the TCV data entry indicated
21667                                                *   by TCV_D_ADDR. When accessing the table, TCV_D_OFFSET must
21668                                                *   be read or written before TCV_D_CTRL.                                     */
21669         } TCV_D_OFFSET_b;
21670     };
21671 
21672     union
21673     {
21674         __IOM uint32_t TCV_D_CTRL;           /*!< (@ 0x00003EA8) TCV Data Control Register                                  */
21675 
21676         struct
21677         {
21678             __IOM uint32_t INC_CTR0     : 1; /*!< [0..0] Increment Control for Counter 0                                    */
21679             __IOM uint32_t INC_CTR1     : 1; /*!< [1..1] Increment Control for Counter 1                                    */
21680             __IOM uint32_t RED_PERIOD   : 1; /*!< [2..2] Period Color Control (for Profinet IRT)                            */
21681             __IOM uint32_t OUT_CT_ENA   : 1; /*!< [3..3] Output Cut-Through Enable                                          */
21682             __IOM uint32_t IN_CT_ENA    : 1; /*!< [4..4] Input Cut-Through Enable                                           */
21683             __IOM uint32_t TRIGGER_MODE : 1; /*!< [5..5] Trigger mode enable when set to 1. GATE_MODE must be
21684                                               *   0, otherwise, GATE_MODE has precedence.                                   */
21685             __IOM uint32_t GATE_MODE : 1;    /*!< [6..6] Gate mode enable when set to 1.                                    */
21686             __IOM uint32_t HOLD_REQ  : 1;    /*!< [7..7] Preemption hold request. Generates a hold request to
21687                                               *   ports enabled in PMASK.                                                   */
21688             __IOM uint32_t QGATE : 8;        /*!< [15..8] Bits mask, one per output queue                                   */
21689             __IOM uint32_t PMASK : 4;        /*!< [19..16] Bits mask, one per output port                                   */
21690             uint32_t             : 12;
21691         } TCV_D_CTRL_b;
21692     };
21693 
21694     union
21695     {
21696         __IOM uint32_t TDMA_CTR0;          /*!< (@ 0x00003EAC) TDMA Counter 0                                             */
21697 
21698         struct
21699         {
21700             __IOM uint32_t TDMA_CTR0 : 32; /*!< [31..0] 32-bit counter that is incremented when the TCV field
21701                                             *   INC_CTR0 is set to 1.                                                     */
21702         } TDMA_CTR0_b;
21703     };
21704 
21705     union
21706     {
21707         __IOM uint32_t TDMA_CTR1;         /*!< (@ 0x00003EB0) TDMA Counter 1                                             */
21708 
21709         struct
21710         {
21711             __IOM uint32_t VALUE     : 8; /*!< [7..0] Current Counter Value                                              */
21712             __OM uint32_t  WRITE_ENA : 1; /*!< [8..8] Write Enable for VALUE                                             */
21713             uint32_t                 : 7;
21714             __IOM uint32_t MAX       : 8; /*!< [23..16] Counter Maximum Value                                            */
21715             __IOM uint32_t INT_VALUE : 8; /*!< [31..24] Interrupt Value                                                  */
21716         } TDMA_CTR1_b;
21717     };
21718 
21719     union
21720     {
21721         __IOM uint32_t TDMA_TCV_START;          /*!< (@ 0x00003EB4) TDMA TCV Sequence Entry Start                              */
21722 
21723         struct
21724         {
21725             __IOM uint32_t TDMA_TCV_START : 12; /*!< [11..0] Define the TCV_SEQ entry to start from.                           */
21726             uint32_t                      : 20;
21727         } TDMA_TCV_START_b;
21728     };
21729 
21730     union
21731     {
21732         __IM uint32_t TIME_LOAD_NEXT;          /*!< (@ 0x00003EB8) TDMA Calculated Next Loading Time                          */
21733 
21734         struct
21735         {
21736             __IM uint32_t TIME_LOAD_NEXT : 32; /*!< [31..0] Status giving the calculated time the scheduler loads
21737                                                 *   into its internal compare register after the current running
21738                                                 *   slot end is reached (not the end of the current slot).                    */
21739         } TIME_LOAD_NEXT_b;
21740     };
21741 
21742     union
21743     {
21744         __IOM uint32_t TDMA_IRQ_CONTROL;    /*!< (@ 0x00003EBC) TDMA IRQ Control Register                                  */
21745 
21746         struct
21747         {
21748             __IOM uint32_t TCV_INT_EN  : 1; /*!< [0..0] Enable Interrupts Generated by the TCV                             */
21749             uint32_t                   : 12;
21750             __IOM uint32_t CTR1_INT_EN : 1; /*!< [13..13] Enable Interrupts Generated from Counter 1                       */
21751             uint32_t                   : 18;
21752         } TDMA_IRQ_CONTROL_b;
21753     };
21754 
21755     union
21756     {
21757         __IOM uint32_t TDMA_IRQ_STAT_ACK; /*!< (@ 0x00003EC0) TDMA IRQ Status/ACK Register                               */
21758 
21759         struct
21760         {
21761             __IOM uint32_t TCV_ACK  : 1;  /*!< [0..0] TCV Execution Event                                                */
21762             uint32_t                : 12;
21763             __IOM uint32_t CTR1_ACK : 1;  /*!< [13..13] Counter 1 Event                                                  */
21764             uint32_t                : 18;
21765         } TDMA_IRQ_STAT_ACK_b;
21766     };
21767 
21768     union
21769     {
21770         __IOM uint32_t TDMA_GPIO;           /*!< (@ 0x00003EC4) TDMA GPIO Register                                         */
21771 
21772         struct
21773         {
21774             __IM uint32_t GPIO_STATUS : 8;  /*!< [7..0] Status of the GPIO Output Pins                                     */
21775             uint32_t                  : 8;
21776             __IOM uint32_t GPIO_MODE  : 16; /*!< [31..16] 2 bits per GPIO pin to configure its operating mode              */
21777         } TDMA_GPIO_b;
21778     };
21779     __IM uint32_t RESERVED110[14];
21780 
21781     union
21782     {
21783         __IOM uint32_t RXMATCH_CONFIG[4];   /*!< (@ 0x00003F00) RX Pattern Matcher Configuration for Port [0..3]           */
21784 
21785         struct
21786         {
21787             __IOM uint32_t PATTERN_EN : 12; /*!< [11..0] Enable Patterns on the Port (RX)                                  */
21788             uint32_t                  : 20;
21789         } RXMATCH_CONFIG_b[4];
21790     };
21791     __IM uint32_t RESERVED111[12];
21792 
21793     union
21794     {
21795         __IOM uint32_t PATTERN_CTRL[12];        /*!< (@ 0x00003F40) RX Pattern Matcher Function Control for Pattern
21796                                                  *                  [0..11]                                                    */
21797 
21798         struct
21799         {
21800             __IOM uint32_t MATCH_NOT : 1;       /*!< [0..0] When set, a match is reported and the functions of this
21801                                                  *   control are executed if the pattern does not match.                       */
21802             __IOM uint32_t MGMTFWD : 1;         /*!< [1..1] When set, the frame is forwarded to the management port
21803                                                  *   only (suppressing destination address lookup).                            */
21804             __IOM uint32_t DISCARD       : 1;   /*!< [2..2] When set, the frame is discarded.                                  */
21805             __IOM uint32_t SET_PRIO      : 1;   /*!< [3..3] Set frame priority, overriding normal classification.              */
21806             __IOM uint32_t MODE          : 2;   /*!< [5..4] Selects the operating mode                                         */
21807             __IOM uint32_t TIMER_SEL_OVR : 1;   /*!< [6..6] Overrides the default timer to use by timestamp operations
21808                                                  *   when set to 1, using instead the value in TIMER_SEL.                      */
21809             __IOM uint32_t FORCE_FORWARD : 1;   /*!< [7..7] When set, the frame is forwarded to the ports indicated
21810                                                  *   in PORTMASK, ignoring the result from L2 lookups.                         */
21811             __IOM uint32_t HUBTRIGGER : 1;      /*!< [8..8] When set, the port defined in the PORTMASK setting is
21812                                                  *   allowed for transmitting one frame.                                       */
21813             __IOM uint32_t MATCH_RED : 1;       /*!< [9..9] Enable the pattern matcher only when the TDMA indicates
21814                                                  *   that this is the RED period.                                              */
21815             __IOM uint32_t MATCH_NOT_RED : 1;   /*!< [10..10] Enable the pattern matcher only when the TDMA indicates
21816                                                  *   that this is not the RED period.                                          */
21817             __IOM uint32_t VLAN_SKIP : 1;       /*!< [11..11] When set to 1, for operating modes 1, 2, and 3. The
21818                                                  *   first Length/Type after the MAC source address is compared
21819                                                  *   against 0x8100. If it matches, a VLAN tag is assumed and
21820                                                  *   4 bytes are skipped.                                                      */
21821             __IOM uint32_t PRIORITY : 3;        /*!< [14..12] Priority of the frame used when SET_PRIO is set. The
21822                                                  *   priority is used to forward the frame into the corresponding
21823                                                  *   output queue of a port.                                                   */
21824             __IOM uint32_t LEARNING_DIS : 1;    /*!< [15..15] When set to 1, the hardware learning function is not
21825                                                  *   executed.                                                                 */
21826             __IOM uint32_t PORTMASK : 4;        /*!< [19..16] A port mask used depending on the control bits (for
21827                                                  *   example, HUBTRIGGER).                                                     */
21828             uint32_t                   : 2;
21829             __IOM uint32_t IMC_TRIGGER : 1;     /*!< [22..22] When set, the ports defined in the PORTMASK setting
21830                                                  *   are allowed for transmitting one frame from the queues
21831                                                  *   indicated by QUEUESEL. The trigger request is sent to the
21832                                                  *   integrated memory controller.                                             */
21833             __IOM uint32_t IMC_TRIGGER_DLY : 1; /*!< [23..23] When set, the ports defined in the PORTMASK setting
21834                                                  *   are allowed for transmitting one frame from the queues
21835                                                  *   indicated by QUEUESEL. The trigger request is sent to the
21836                                                  *   integrated memory controller and the event is delayed by
21837                                                  *   the value programmed in MMCTL_DLY_QTRIGGER_CTRL.                          */
21838             __IOM uint32_t SWAP_BYTES : 1;      /*!< [24..24] Applicable only for operating modes 1, 2, and 3. When
21839                                                  *   set to 1, the byte order is swapped from the order received
21840                                                  *   by the frame. When set to 0, the first byte received by
21841                                                  *   the frame is set into position 0 for comparison. When set
21842                                                  *   to 1, the first byte received is set into position 3 (for
21843                                                  *   mode 1) or position 2 (for mode 2 and 3) for comparison.                  */
21844             __IOM uint32_t MATCH_LT : 1;        /*!< [25..25] For operating modes 1, 2, and 3. When set to 1, the
21845                                                  *   Length/Type field in the frame after the MAC source address
21846                                                  *   is compared against the value in length_type in the compare
21847                                                  *   register. If VLAN_SKIP is set and the frame has a VLAN
21848                                                  *   tag with Length/Type of 0x8100 then the comparison is performed
21849                                                  *   in the Length/Type following the VLAN tag.                                */
21850             __IOM uint32_t TIMER_SEL : 1;       /*!< [26..26] Override value to use when TIMER_SEL_OVR is set to
21851                                                  *   1 for selecting the timer for this frame.                                 */
21852             uint32_t                : 1;
21853             __IOM uint32_t QUEUESEL : 4;        /*!< [31..28] A queue selector for the HUBTRIGGER function. Selects
21854                                                  *   the queue to trigger a frame, or sets from 0x8 to 0xF to
21855                                                  *   select one among all queues.                                              */
21856         } PATTERN_CTRL_b[12];
21857     };
21858     __IM uint32_t RESERVED112[4];
21859 
21860     union
21861     {
21862         __IOM uint32_t PATTERN_IRQ_CONTROL; /*!< (@ 0x00003F80) RX Pattern Matcher Interrupt Control Register              */
21863 
21864         struct
21865         {
21866             __IOM uint32_t MATCHINT  : 12;  /*!< [11..0] Enable Interrupt on Receive Pattern Match                         */
21867             uint32_t                 : 4;
21868             __IOM uint32_t ERROR_INT : 4;   /*!< [19..16] Enable Interrupt on Internal Pattern Matcher Error               */
21869             uint32_t                 : 12;
21870         } PATTERN_IRQ_CONTROL_b;
21871     };
21872 
21873     union
21874     {
21875         __IOM uint32_t PATTERN_IRQ_STAT_ACK; /*!< (@ 0x00003F84) RX Pattern Matcher Interrupt Status/ACK Register           */
21876 
21877         struct
21878         {
21879             __IOM uint32_t MATCHINT : 12;    /*!< [11..0] Interrupt pending indication for the corresponding pattern
21880                                               *   match events (see ).                                                      */
21881             uint32_t                 : 4;
21882             __IOM uint32_t ERROR_INT : 4;    /*!< [19..16] Interrupt pending indication for a pattern matcher
21883                                               *   error, per port.                                                          */
21884             uint32_t : 12;
21885         } PATTERN_IRQ_STAT_ACK_b;
21886     };
21887 
21888     union
21889     {
21890         __IOM uint32_t PTRN_VLANID;          /*!< (@ 0x00003F88) Custom VLAN ID Register                                    */
21891 
21892         struct
21893         {
21894             __IOM uint32_t PTRN_VLANID : 16; /*!< [15..0] Custom VLAN ID to use. The default VLAN ID 0x8100 is
21895                                               *   always considered by the hardware. This value can be changed
21896                                               *   to detect other VLANs like 0x8808.                                        */
21897             uint32_t : 16;
21898         } PTRN_VLANID_b;
21899     };
21900 
21901     union
21902     {
21903         __IOM uint32_t PATTERN_SEL;         /*!< (@ 0x00003F8C) RX Pattern Number Selection Register                       */
21904 
21905         struct
21906         {
21907             __IOM uint32_t PATTERN_SEL : 4; /*!< [3..0] Define the pattern number which is selected for read/write
21908                                              *   through the PTRN_CMP_* and PTRN_MSK_* registers.                          */
21909             uint32_t : 28;
21910         } PATTERN_SEL_b;
21911     };
21912     __IM uint32_t RESERVED113[12];
21913 
21914     union
21915     {
21916         __IOM uint32_t PTRN_CMP_30;          /*!< (@ 0x00003FC0) Pattern Compare Value Bytes 3 .. 0                         */
21917 
21918         struct
21919         {
21920             __IOM uint32_t PTRN_CMP_30 : 32; /*!< [31..0] Pattern Compare Value Bytes 3 .. 0                                */
21921         } PTRN_CMP_30_b;
21922     };
21923 
21924     union
21925     {
21926         __IOM uint32_t PTRN_CMP_74;          /*!< (@ 0x00003FC4) Pattern Compare Value Bytes 7 .. 4                         */
21927 
21928         struct
21929         {
21930             __IOM uint32_t PTRN_CMP_74 : 32; /*!< [31..0] Pattern Compare Value Bytes 7 .. 4                                */
21931         } PTRN_CMP_74_b;
21932     };
21933 
21934     union
21935     {
21936         __IOM uint32_t PTRN_CMP_118;          /*!< (@ 0x00003FC8) Pattern Compare Value Bytes 11 .. 8                        */
21937 
21938         struct
21939         {
21940             __IOM uint32_t PTRN_CMP_118 : 32; /*!< [31..0] Pattern Compare Value Bytes 11 .. 8                               */
21941         } PTRN_CMP_118_b;
21942     };
21943     __IM uint32_t RESERVED114;
21944 
21945     union
21946     {
21947         __IOM uint32_t PTRN_MSK_30;          /*!< (@ 0x00003FD0) Pattern Mask for Bytes 3 .. 0                              */
21948 
21949         struct
21950         {
21951             __IOM uint32_t PTRN_MSK_30 : 32; /*!< [31..0] PTRN_MSK_30                                                       */
21952         } PTRN_MSK_30_b;
21953     };
21954 
21955     union
21956     {
21957         __IOM uint32_t PTRN_MSK_74;          /*!< (@ 0x00003FD4) Pattern Mask for Bytes 7 .. 4                              */
21958 
21959         struct
21960         {
21961             __IOM uint32_t PTRN_MSK_74 : 32; /*!< [31..0] PTRN_MSK_74                                                       */
21962         } PTRN_MSK_74_b;
21963     };
21964 
21965     union
21966     {
21967         __IOM uint32_t PTRN_MSK_118;          /*!< (@ 0x00003FD8) Pattern Mask for Bytes 11 .. 8                             */
21968 
21969         struct
21970         {
21971             __IOM uint32_t PTRN_MSK_118 : 32; /*!< [31..0] PTRN_MSK_118                                                      */
21972         } PTRN_MSK_118_b;
21973     };
21974 } R_ETHSW_Type;                               /*!< Size = 16348 (0x3fdc)                                                     */
21975 
21976 /* =========================================================================================================================== */
21977 /* ================                                           R_ESC                                           ================ */
21978 /* =========================================================================================================================== */
21979 
21980 /**
21981  * @brief EtherCAT Slave Controller (R_ESC)
21982  */
21983 
21984 typedef struct                         /*!< (@ 0x80130000) R_ESC Structure                                            */
21985 {
21986     union
21987     {
21988         __IM uint8_t TYPE;             /*!< (@ 0x00000000) Type Register                                              */
21989 
21990         struct
21991         {
21992             __IM uint8_t TYPE : 8;     /*!< [7..0] Type of the EtherCAT slave controller                              */
21993         } TYPE_b;
21994     };
21995 
21996     union
21997     {
21998         __IM uint8_t REVISION;         /*!< (@ 0x00000001) Revision Register                                          */
21999 
22000         struct
22001         {
22002             __IM uint8_t REV : 8;      /*!< [7..0] Revision of the EtherCAT slave controller                          */
22003         } REVISION_b;
22004     };
22005 
22006     union
22007     {
22008         __IM uint8_t BUILD;            /*!< (@ 0x00000002) Build Register                                             */
22009 
22010         struct
22011         {
22012             __IM uint8_t BUILD : 8;    /*!< [7..0] Build number of the EtherCAT slave controller                      */
22013         } BUILD_b;
22014     };
22015     __IM uint8_t RESERVED;
22016 
22017     union
22018     {
22019         __IM uint8_t FMMU_NUM;         /*!< (@ 0x00000004) FMMU Supported Register                                    */
22020 
22021         struct
22022         {
22023             __IM uint8_t NUMFMMU : 8;  /*!< [7..0] Number of FMMU channels supported in the EtherCAT slave
22024                                         *   controller                                                                */
22025         } FMMU_NUM_b;
22026     };
22027 
22028     union
22029     {
22030         __IM uint8_t SYNC_MANAGER;     /*!< (@ 0x00000005) SyncManager Supported Register                             */
22031 
22032         struct
22033         {
22034             __IM uint8_t NUMSYNC : 8;  /*!< [7..0] Number of SyncManager channels supported in the EtherCAT
22035                                         *   slave controller                                                          */
22036         } SYNC_MANAGER_b;
22037     };
22038 
22039     union
22040     {
22041         __IM uint8_t RAM_SIZE;         /*!< (@ 0x00000006) RAM Size Register                                          */
22042 
22043         struct
22044         {
22045             __IM uint8_t RAMSIZE : 8;  /*!< [7..0] Process data RAM size supported in the EtherCAT slave
22046                                         *   controller (unit: KB)                                                     */
22047         } RAM_SIZE_b;
22048     };
22049 
22050     union
22051     {
22052         __IM uint8_t PORT_DESC;        /*!< (@ 0x00000007) Port Descriptor Register                                   */
22053 
22054         struct
22055         {
22056             __IM uint8_t P0 : 2;       /*!< [1..0] Port 0 configuration                                               */
22057             __IM uint8_t P1 : 2;       /*!< [3..2] Port 1 configuration                                               */
22058             __IM uint8_t P2 : 2;       /*!< [5..4] Port 2 configuration                                               */
22059             __IM uint8_t P3 : 2;       /*!< [7..6] Port 3 configuration                                               */
22060         } PORT_DESC_b;
22061     };
22062 
22063     union
22064     {
22065         __IM uint16_t FEATURE;            /*!< (@ 0x00000008) ESC Features Supported Register                            */
22066 
22067         struct
22068         {
22069             __IM uint16_t FMMU       : 1; /*!< [0..0] FMMU Operation                                                     */
22070             uint16_t                 : 1;
22071             __IM uint16_t DC         : 1; /*!< [2..2] Distributed Clock                                                  */
22072             __IM uint16_t DCWID      : 1; /*!< [3..3] Distributed Clock Width                                            */
22073             uint16_t                 : 2;
22074             __IM uint16_t LINKDECMII : 1; /*!< [6..6] Enhanced Link Detection in MII                                     */
22075             __IM uint16_t FCS        : 1; /*!< [7..7] Separate handling of FCS errors                                    */
22076             __IM uint16_t DCSYNC     : 1; /*!< [8..8] Enhanced DC SYNC activation                                        */
22077             __IM uint16_t LRW        : 1; /*!< [9..9] EtherCAT LRW command support                                       */
22078             __IM uint16_t RWSUPP     : 1; /*!< [10..10] EtherCAT read/write command support (BRW, APRW, FPRW)            */
22079             __IM uint16_t FSCONFIG   : 1; /*!< [11..11] Fixed FMMU/SyncManager configuration                             */
22080             uint16_t                 : 4;
22081         } FEATURE_b;
22082     };
22083     __IM uint16_t RESERVED1;
22084     __IM uint32_t RESERVED2;
22085 
22086     union
22087     {
22088         __IM uint16_t STATION_ADR;      /*!< (@ 0x00000010) Configured Station Address Register                        */
22089 
22090         struct
22091         {
22092             __IM uint16_t NODADDR : 16; /*!< [15..0] Node Addressing Address Indication                                */
22093         } STATION_ADR_b;
22094     };
22095 
22096     union
22097     {
22098         __IOM uint16_t STATION_ALIAS;       /*!< (@ 0x00000012) Configured Station Alias Register                          */
22099 
22100         struct
22101         {
22102             __IOM uint16_t NODALIADDR : 16; /*!< [15..0] Alias Address Indication                                          */
22103         } STATION_ALIAS_b;
22104     };
22105     __IM uint32_t RESERVED3[3];
22106 
22107     union
22108     {
22109         __IM uint8_t WR_REG_ENABLE;    /*!< (@ 0x00000020) Write Register Enable Register                             */
22110 
22111         struct
22112         {
22113             __IM uint8_t ENABLE : 1;   /*!< [0..0] Register Write Protection Unlock                                   */
22114             uint8_t             : 7;
22115         } WR_REG_ENABLE_b;
22116     };
22117 
22118     union
22119     {
22120         __IM uint8_t WR_REG_PROTECT;   /*!< (@ 0x00000021) Write Register Protection Register                         */
22121 
22122         struct
22123         {
22124             __IM uint8_t PROTECT : 1;  /*!< [0..0] Register Write Protection Specification                            */
22125             uint8_t              : 7;
22126         } WR_REG_PROTECT_b;
22127     };
22128     __IM uint16_t RESERVED4;
22129     __IM uint32_t RESERVED5[3];
22130 
22131     union
22132     {
22133         __IM uint8_t ESC_WR_ENABLE;    /*!< (@ 0x00000030) ESC Write Enable Register                                  */
22134 
22135         struct
22136         {
22137             __IM uint8_t ENABLE : 1;   /*!< [0..0] Register/Memory Write Protection Unlock                            */
22138             uint8_t             : 7;
22139         } ESC_WR_ENABLE_b;
22140     };
22141 
22142     union
22143     {
22144         __IM uint8_t ESC_WR_PROTECT;   /*!< (@ 0x00000031) ESC Write Protection Register                              */
22145 
22146         struct
22147         {
22148             __IM uint8_t PROTECT : 1;  /*!< [0..0] Register/Memory Write Protection Specification                     */
22149             uint8_t              : 7;
22150         } ESC_WR_PROTECT_b;
22151     };
22152     __IM uint16_t RESERVED6;
22153     __IM uint32_t RESERVED7[3];
22154 
22155     union
22156     {
22157         union
22158         {
22159             __IM uint8_t ESC_RESET_ECAT_R;   /*!< (@ 0x00000040) ESC Reset ECAT Register for read                           */
22160 
22161             struct
22162             {
22163                 __IM uint8_t RESET_ECAT : 2; /*!< [1..0] Reset Progress Status                                              */
22164                 uint8_t                 : 6;
22165             } ESC_RESET_ECAT_R_b;
22166         };
22167 
22168         union
22169         {
22170             __IM uint8_t ESC_RESET_ECAT_W;   /*!< (@ 0x00000040) ESC Reset ECAT Register for write                          */
22171 
22172             struct
22173             {
22174                 __IM uint8_t RESET_ECAT : 8; /*!< [7..0] Software Reset Setting                                             */
22175             } ESC_RESET_ECAT_W_b;
22176         };
22177     };
22178 
22179     union
22180     {
22181         union
22182         {
22183             __IOM uint8_t ESC_RESET_PDI_R;   /*!< (@ 0x00000041) ESC Reset PDI Register for read                            */
22184 
22185             struct
22186             {
22187                 __IOM uint8_t RESET_PDI : 2; /*!< [1..0] Reset Progress Status                                              */
22188                 uint8_t                 : 6;
22189             } ESC_RESET_PDI_R_b;
22190         };
22191 
22192         union
22193         {
22194             __IOM uint8_t ESC_RESET_PDI_W;   /*!< (@ 0x00000041) ESC Reset PDI Register for write                           */
22195 
22196             struct
22197             {
22198                 __IOM uint8_t RESET_PDI : 8; /*!< [7..0] Software Reset Setting                                             */
22199             } ESC_RESET_PDI_W_b;
22200         };
22201     };
22202     __IM uint16_t RESERVED8;
22203     __IM uint32_t RESERVED9[47];
22204 
22205     union
22206     {
22207         __IM uint32_t ESC_DL_CONTROL;   /*!< (@ 0x00000100) ESC DL Control Register                                    */
22208 
22209         struct
22210         {
22211             __IM uint32_t FWDRULE  : 1; /*!< [0..0] Forwarding Rule                                                    */
22212             __IM uint32_t TEMPUSE  : 1; /*!< [1..1] Temporary Use of Bits 15 to 8 Settings                             */
22213             uint32_t               : 6;
22214             __IM uint32_t LP0      : 2; /*!< [9..8] Loop Port 0 Configuration                                          */
22215             __IM uint32_t LP1      : 2; /*!< [11..10] Loop Port 1 Configuration                                        */
22216             __IM uint32_t LP2      : 2; /*!< [13..12] Loop Port 2 Configuration                                        */
22217             __IM uint32_t LP3      : 2; /*!< [15..14] Loop Port 3 Configuration                                        */
22218             __IM uint32_t RXFIFO   : 3; /*!< [18..16] RX FIFO Size                                                     */
22219             uint32_t               : 5;
22220             __IM uint32_t STAALIAS : 1; /*!< [24..24] Station Alias Status                                             */
22221             uint32_t               : 7;
22222         } ESC_DL_CONTROL_b;
22223     };
22224     __IM uint32_t RESERVED10;
22225 
22226     union
22227     {
22228         __IM uint16_t PHYSICAL_RW_OFFSET; /*!< (@ 0x00000108) Physical Read/Write Offset Register                        */
22229 
22230         struct
22231         {
22232             __IM uint16_t RWOFFSET : 16;  /*!< [15..0] Offset between Read and Write Addresses                           */
22233         } PHYSICAL_RW_OFFSET_b;
22234     };
22235     __IM uint16_t RESERVED11;
22236     __IM uint32_t RESERVED12;
22237 
22238     union
22239     {
22240         __IM uint16_t ESC_DL_STATUS;    /*!< (@ 0x00000110) ESC DL Status Register                                     */
22241 
22242         struct
22243         {
22244             __IM uint16_t PDIOPE   : 1; /*!< [0..0] PDI/EEPROM Load State Indication                                   */
22245             __IM uint16_t PDIWDST  : 1; /*!< [1..1] PDI Watchdog Timer Status                                          */
22246             __IM uint16_t ENHLINKD : 1; /*!< [2..2] Enhanced Link Detection Indication                                 */
22247             uint16_t               : 1;
22248             __IM uint16_t PHYP0    : 1; /*!< [4..4] Port 0 Link State Indication                                       */
22249             __IM uint16_t PHYP1    : 1; /*!< [5..5] Port 1 Link State Indication                                       */
22250             __IM uint16_t PHYP2    : 1; /*!< [6..6] Port 2 Link State Indication                                       */
22251             __IM uint16_t PHYP3    : 1; /*!< [7..7] Port 3 Link State Indication                                       */
22252             __IM uint16_t LP0      : 1; /*!< [8..8] Loop Port 0 State Indication                                       */
22253             __IM uint16_t COMP0    : 1; /*!< [9..9] Port 0 Communication State Indication                              */
22254             __IM uint16_t LP1      : 1; /*!< [10..10] Loop Port 1 State Indication                                     */
22255             __IM uint16_t COMP1    : 1; /*!< [11..11] Port 1 Communication State Indication                            */
22256             __IM uint16_t LP2      : 1; /*!< [12..12] Loop Port 2 State Indication                                     */
22257             __IM uint16_t COMP2    : 1; /*!< [13..13] Port 2 Communication State Indication                            */
22258             __IM uint16_t LP3      : 1; /*!< [14..14] Loop Port 3 State Indication                                     */
22259             __IM uint16_t COMP3    : 1; /*!< [15..15] Port 3 Communication State Indication                            */
22260         } ESC_DL_STATUS_b;
22261     };
22262     __IM uint16_t RESERVED13;
22263     __IM uint32_t RESERVED14[3];
22264 
22265     union
22266     {
22267         __IM uint16_t AL_CONTROL;        /*!< (@ 0x00000120) AL Control Register                                        */
22268 
22269         struct
22270         {
22271             __IM uint16_t INISTATE  : 4; /*!< [3..0] Change the state transition of the device state machine.           */
22272             __IM uint16_t ERRINDACK : 1; /*!< [4..4] Error Indication Acknowledge (Response)                            */
22273             __IM uint16_t DEVICEID  : 1; /*!< [5..5] Device ID Request                                                  */
22274             uint16_t                : 10;
22275         } AL_CONTROL_b;
22276     };
22277     __IM uint16_t RESERVED15;
22278     __IM uint32_t RESERVED16[3];
22279 
22280     union
22281     {
22282         __IOM uint16_t AL_STATUS;        /*!< (@ 0x00000130) AL Status Register                                         */
22283 
22284         struct
22285         {
22286             __IOM uint16_t ACTSTATE : 4; /*!< [3..0] State Machine State Indication                                     */
22287             __IOM uint16_t ERR      : 1; /*!< [4..4] Error State Indication                                             */
22288             __IOM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Load State Indication                                    */
22289             uint16_t                : 10;
22290         } AL_STATUS_b;
22291     };
22292     __IM uint16_t RESERVED17;
22293 
22294     union
22295     {
22296         __IOM uint16_t AL_STATUS_CODE;      /*!< (@ 0x00000134) AL Status Code Register                                    */
22297 
22298         struct
22299         {
22300             __IOM uint16_t STATUSCODE : 16; /*!< [15..0] AL status code                                                    */
22301         } AL_STATUS_CODE_b;
22302     };
22303     __IM uint16_t RESERVED18;
22304 
22305     union
22306     {
22307         __IOM uint8_t RUN_LED_OVERRIDE;   /*!< (@ 0x00000138) RUN LED Override Register                                  */
22308 
22309         struct
22310         {
22311             __IOM uint8_t LEDCODE : 4;    /*!< [3..0] LED Code Indication (FSM state: Bits [3:0] of the AL
22312                                            *   Status register, AL_STATUS)                                               */
22313             __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting                                                   */
22314             uint8_t                  : 3;
22315         } RUN_LED_OVERRIDE_b;
22316     };
22317 
22318     union
22319     {
22320         __IOM uint8_t ERR_LED_OVERRIDE;   /*!< (@ 0x00000139) ERR LED Override Register                                  */
22321 
22322         struct
22323         {
22324             __IOM uint8_t LEDCODE    : 4; /*!< [3..0] LED Code Indication                                                */
22325             __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting                                                   */
22326             uint8_t                  : 3;
22327         } ERR_LED_OVERRIDE_b;
22328     };
22329     __IM uint16_t RESERVED19;
22330     __IM uint32_t RESERVED20;
22331 
22332     union
22333     {
22334         __IM uint8_t PDI_CONTROL;      /*!< (@ 0x00000140) PDI Control Register                                       */
22335 
22336         struct
22337         {
22338             __IM uint8_t PDI : 8;      /*!< [7..0] Process Data Interface. In this LSI, the following value
22339                                         *   is indicated.                                                             */
22340         } PDI_CONTROL_b;
22341     };
22342 
22343     union
22344     {
22345         __IM uint8_t ESC_CONFIG;       /*!< (@ 0x00000141) ESC Configuration Register                                 */
22346 
22347         struct
22348         {
22349             __IM uint8_t DEVEMU  : 1;  /*!< [0..0] Device emulation (control of AL status)                            */
22350             __IM uint8_t ENLALLP : 1;  /*!< [1..1] Sets enhanced link detection for all ports                         */
22351             __IM uint8_t DCSYNC  : 1;  /*!< [2..2] Sets the SYNC output unit for distributed clocks (fixed
22352                                         *   to 1 in this LSI)                                                         */
22353             __IM uint8_t DCLATCH : 1;  /*!< [3..3] Sets the latch input unit for distributed clocks                   */
22354             __IM uint8_t ENLP0   : 1;  /*!< [4..4] Port 0 Enhanced Link Detection Setting                             */
22355             __IM uint8_t ENLP1   : 1;  /*!< [5..5] Port 1 Enhanced Link Detection Setting                             */
22356             __IM uint8_t ENLP2   : 1;  /*!< [6..6] Port 2 Enhanced Link Detection Setting                             */
22357             __IM uint8_t ENLP3   : 1;  /*!< [7..7] Port 3 Enhanced Link Detection Setting                             */
22358         } ESC_CONFIG_b;
22359     };
22360     __IM uint16_t RESERVED21;
22361     __IM uint32_t RESERVED22[3];
22362 
22363     union
22364     {
22365         __IM uint8_t PDI_CONFIG;           /*!< (@ 0x00000150) PDI Configuration Register                                 */
22366 
22367         struct
22368         {
22369             __IM uint8_t ONCHIPBUSCLK : 5; /*!< [4..0] On-Chip Bus Clock Indication                                       */
22370             __IM uint8_t ONCHIPBUS    : 3; /*!< [7..5] On-Chip Bus Type Indication                                        */
22371         } PDI_CONFIG_b;
22372     };
22373 
22374     union
22375     {
22376         __IM uint8_t SYNC_LATCH_CONFIG; /*!< (@ 0x00000151) SYNC/LATCH PDI Configuration Register                      */
22377 
22378         struct
22379         {
22380             __IM uint8_t SYNC0OUT : 2;  /*!< [1..0] SYNC0 Output Driver and Polarity Indication                        */
22381             __IM uint8_t SYNCLAT0 : 1;  /*!< [2..2] SYNC0/LATCH0 Indication                                            */
22382             __IM uint8_t SYNC0MAP : 1;  /*!< [3..3] SYNC0 State Mapping Indication                                     */
22383             __IM uint8_t SYNC1OUT : 2;  /*!< [5..4] SYNC1 Output Driver and Polarity Indication                        */
22384             __IM uint8_t SYNCLAT1 : 1;  /*!< [6..6] SYNC1/LATCH1 Indication                                            */
22385             __IM uint8_t SYNC1MAP : 1;  /*!< [7..7] SYNC1 State Mapping Indication                                     */
22386         } SYNC_LATCH_CONFIG_b;
22387     };
22388 
22389     union
22390     {
22391         __IM uint16_t EXT_PDI_CONFIG;     /*!< (@ 0x00000152) Extended PDI Configuration Register                        */
22392 
22393         struct
22394         {
22395             __IM uint16_t DATABUSWID : 2; /*!< [1..0] PDI Data Bus Width Indication                                      */
22396             uint16_t                 : 14;
22397         } EXT_PDI_CONFIG_b;
22398     };
22399     __IM uint32_t RESERVED23[43];
22400 
22401     union
22402     {
22403         __IM uint16_t ECAT_EVENT_MASK;     /*!< (@ 0x00000200) ECAT Event Mask Register                                   */
22404 
22405         struct
22406         {
22407             __IM uint16_t ECATEVMASK : 16; /*!< [15..0] Event Request Mask Setting                                        */
22408         } ECAT_EVENT_MASK_b;
22409     };
22410     __IM uint16_t RESERVED24;
22411 
22412     union
22413     {
22414         __IOM uint32_t AL_EVENT_MASK;     /*!< (@ 0x00000204) AL Event Mask Register                                     */
22415 
22416         struct
22417         {
22418             __IOM uint32_t ALEVMASK : 32; /*!< [31..0] Event Request Mask Setting                                        */
22419         } AL_EVENT_MASK_b;
22420     };
22421     __IM uint32_t RESERVED25[2];
22422 
22423     union
22424     {
22425         __IM uint16_t ECAT_EVENT_REQ;  /*!< (@ 0x00000210) ECAT Event Request Register                                */
22426 
22427         struct
22428         {
22429             __IM uint16_t DCLATCH : 1; /*!< [0..0] DC Latch Event State Indication                                    */
22430             uint16_t              : 1;
22431             __IM uint16_t DLSTA   : 1; /*!< [2..2] DL Status Event State Indication                                   */
22432             __IM uint16_t ALSTA   : 1; /*!< [3..3] AL Status Event State Indication                                   */
22433             __IM uint16_t SMSTA0  : 1; /*!< [4..4] Mirror value of SyncManager 0 Status Indication                    */
22434             __IM uint16_t SMSTA1  : 1; /*!< [5..5] Mirror value of SyncManager 1 Status Indication                    */
22435             __IM uint16_t SMSTA2  : 1; /*!< [6..6] Mirror value of SyncManager 2 Status Indication                    */
22436             __IM uint16_t SMSTA3  : 1; /*!< [7..7] Mirror value of SyncManager 3 Status Indication                    */
22437             __IM uint16_t SMSTA4  : 1; /*!< [8..8] Mirror value of SyncManager 4 Status Indication                    */
22438             __IM uint16_t SMSTA5  : 1; /*!< [9..9] Mirror value of SyncManager 5 Status Indication                    */
22439             __IM uint16_t SMSTA6  : 1; /*!< [10..10] Mirror value of SyncManager 6 Status Indication                  */
22440             __IM uint16_t SMSTA7  : 1; /*!< [11..11] Mirror value of SyncManager 7 Status Indication                  */
22441             uint16_t              : 4;
22442         } ECAT_EVENT_REQ_b;
22443     };
22444     __IM uint16_t RESERVED26;
22445     __IM uint32_t RESERVED27[3];
22446 
22447     union
22448     {
22449         __IM uint32_t AL_EVENT_REQ;       /*!< (@ 0x00000220) AL Event Request Register                                  */
22450 
22451         struct
22452         {
22453             __IM uint32_t ALCTRL     : 1; /*!< [0..0] AL Control Event State Indication                                  */
22454             __IM uint32_t DCLATCH    : 1; /*!< [1..1] DC Latch Event State Indication                                    */
22455             __IM uint32_t DCSYNC0STA : 1; /*!< [2..2] DC SYNC0 State Indication                                          */
22456             __IM uint32_t DCSYNC1STA : 1; /*!< [3..3] DC SYNC1 State Indication                                          */
22457             __IM uint32_t SYNCACT    : 1; /*!< [4..4] SyncManager Activation Indication                                  */
22458             uint32_t                 : 1;
22459             __IM uint32_t WDPD       : 1; /*!< [6..6] Watchdog Process Data Indication                                   */
22460             uint32_t                 : 1;
22461             __IM uint32_t SMINT0     : 1; /*!< [8..8] SyncManager 0 interrupt (bit 0 or 1 of the SyncManager
22462                                            *   status register (0x0805))                                                 */
22463             __IM uint32_t SMINT1 : 1;     /*!< [9..9] SyncManager 1 interrupt (bit 0 or 1 of the SyncManager
22464                                            *   status register (0x080D))                                                 */
22465             __IM uint32_t SMINT2 : 1;     /*!< [10..10] SyncManager 2 interrupt (bit 0 or 1 of the SyncManager
22466                                            *   status register (0x0815))                                                 */
22467             __IM uint32_t SMINT3 : 1;     /*!< [11..11] SyncManager 3 interrupt (bit 0 or 1 of the SyncManager
22468                                            *   status register (0x081D))                                                 */
22469             __IM uint32_t SMINT4 : 1;     /*!< [12..12] SyncManager 4 interrupt (bit 0 or 1 of the SyncManager
22470                                            *   status register (0x0825))                                                 */
22471             __IM uint32_t SMINT5 : 1;     /*!< [13..13] SyncManager 5 interrupt (bit 0 or 1 of the SyncManager
22472                                            *   status register (0x082D))                                                 */
22473             __IM uint32_t SMINT6 : 1;     /*!< [14..14] SyncManager 6 interrupt (bit 0 or 1 of the SyncManager
22474                                            *   status register (0x0835))                                                 */
22475             __IM uint32_t SMINT7 : 1;     /*!< [15..15] SyncManager 7 interrupt (bit 0 or 1 of the SyncManager
22476                                            *   status register (0x083D))                                                 */
22477             uint32_t : 16;
22478         } AL_EVENT_REQ_b;
22479     };
22480     __IM uint32_t RESERVED28[55];
22481 
22482     union
22483     {
22484         __IM uint16_t RX_ERR_COUNT[3];   /*!< (@ 0x00000300) RX Error Counter [0..2] Register (n = 0 to 2)              */
22485 
22486         struct
22487         {
22488             __IM uint16_t INVFRMCNT : 8; /*!< [7..0] Invalid Frame Counter Value Indication                             */
22489             __IM uint16_t RXERRCNT  : 8; /*!< [15..8] RX Frame Error Counter Value Indication                           */
22490         } RX_ERR_COUNT_b[3];
22491     };
22492     __IM uint16_t RESERVED29;
22493 
22494     union
22495     {
22496         __IM uint8_t FWD_RX_ERR_COUNT[3]; /*!< (@ 0x00000308) Forwarded RX Error Counter [0..2] Register (n
22497                                            *                  = 0 to 2)                                                  */
22498 
22499         struct
22500         {
22501             __IM uint8_t FWDERRCNT : 8;   /*!< [7..0] Forwarded Error Counter Value Indication                           */
22502         } FWD_RX_ERR_COUNT_b[3];
22503     };
22504     __IM uint8_t RESERVED30;
22505 
22506     union
22507     {
22508         __IM uint8_t ECAT_PROC_ERR_COUNT; /*!< (@ 0x0000030C) ECAT Processing Unit Error Counter Register                */
22509 
22510         struct
22511         {
22512             __IM uint8_t EPUERRCNT : 8;   /*!< [7..0] Processing Unit Error Counter Value Indication                     */
22513         } ECAT_PROC_ERR_COUNT_b;
22514     };
22515 
22516     union
22517     {
22518         __IM uint8_t PDI_ERR_COUNT;     /*!< (@ 0x0000030D) PDI Error Counter Register                                 */
22519 
22520         struct
22521         {
22522             __IM uint8_t PDIERRCNT : 8; /*!< [7..0] PDI Error Counter Value Indication                                 */
22523         } PDI_ERR_COUNT_b;
22524     };
22525     __IM uint16_t RESERVED31;
22526 
22527     union
22528     {
22529         __IM uint8_t LOST_LINK_COUNT[3];  /*!< (@ 0x00000310) Lost Link Counter [0..2] Register (n = 0 to 2)             */
22530 
22531         struct
22532         {
22533             __IM uint8_t LOSTLINKCNT : 8; /*!< [7..0] Lost Link Counter Value Indication                                 */
22534         } LOST_LINK_COUNT_b[3];
22535     };
22536     __IM uint8_t  RESERVED32;
22537     __IM uint32_t RESERVED33[59];
22538 
22539     union
22540     {
22541         __IM uint16_t WD_DIVIDE;       /*!< (@ 0x00000400) Watchdog Divider Register                                  */
22542 
22543         struct
22544         {
22545             __IM uint16_t WDDIV : 16;  /*!< [15..0] Watchdog Clock Frequency Divisor Setting                          */
22546         } WD_DIVIDE_b;
22547     };
22548     __IM uint16_t RESERVED34;
22549     __IM uint32_t RESERVED35[3];
22550 
22551     union
22552     {
22553         __IM uint16_t WDT_PDI;           /*!< (@ 0x00000410) Watchdog Time PDI Register                                 */
22554 
22555         struct
22556         {
22557             __IM uint16_t WDTIMPDI : 16; /*!< [15..0] Watchdog Overflow Time Setting                                    */
22558         } WDT_PDI_b;
22559     };
22560     __IM uint16_t RESERVED36;
22561     __IM uint32_t RESERVED37[3];
22562 
22563     union
22564     {
22565         __IM uint16_t WDT_DATA;         /*!< (@ 0x00000420) Watchdog Time Process Data Register                        */
22566 
22567         struct
22568         {
22569             __IM uint16_t WDTIMPD : 16; /*!< [15..0] Watchdog Overflow Time Setting                                    */
22570         } WDT_DATA_b;
22571     };
22572     __IM uint16_t RESERVED38;
22573     __IM uint32_t RESERVED39[7];
22574 
22575     union
22576     {
22577         __IM uint16_t WDS_DATA;        /*!< (@ 0x00000440) Watchdog Status Process Data Register                      */
22578 
22579         struct
22580         {
22581             __IM uint16_t WDSTAPD : 1; /*!< [0..0] Watchdog State Indication                                          */
22582             uint16_t              : 15;
22583         } WDS_DATA_b;
22584     };
22585 
22586     union
22587     {
22588         __IM uint8_t WDC_DATA;         /*!< (@ 0x00000442) Watchdog Counter Process Data Register                     */
22589 
22590         struct
22591         {
22592             __IM uint8_t WDCNTPD : 8;  /*!< [7..0] Watchdog Counter Value Indication                                  */
22593         } WDC_DATA_b;
22594     };
22595 
22596     union
22597     {
22598         __IM uint8_t WDC_PDI;          /*!< (@ 0x00000443) Watchdog Counter PDI Register                              */
22599 
22600         struct
22601         {
22602             __IM uint8_t WDCNTPDI : 8; /*!< [7..0] Watchdog Counter Value Indication                                  */
22603         } WDC_PDI_b;
22604     };
22605     __IM uint32_t RESERVED40[47];
22606 
22607     union
22608     {
22609         __IM uint8_t EEP_CONF;          /*!< (@ 0x00000500) EEPROM Configuration Register                              */
22610 
22611         struct
22612         {
22613             __IM uint8_t CTRLPDI   : 1; /*!< [0..0] PDI EEPROM Control                                                 */
22614             __IM uint8_t FORCEECAT : 1; /*!< [1..1] EEPROM Access Right Change                                         */
22615             uint8_t                : 6;
22616         } EEP_CONF_b;
22617     };
22618 
22619     union
22620     {
22621         __IOM uint8_t EEP_STATE;         /*!< (@ 0x00000501) EEPROM PDI Access State Register                           */
22622 
22623         struct
22624         {
22625             __IOM uint8_t PDIACCESS : 1; /*!< [0..0] EEPROM Access Right Setting                                        */
22626             uint8_t                 : 7;
22627         } EEP_STATE_b;
22628     };
22629 
22630     union
22631     {
22632         __IOM uint16_t EEP_CONT_STAT;     /*!< (@ 0x00000502) EEPROM Control/Status Register                             */
22633 
22634         struct
22635         {
22636             __IM uint16_t ECATWREN   : 1; /*!< [0..0] ECAT Write Enable                                                  */
22637             uint16_t                 : 5;
22638             __IM uint16_t  READBYTE  : 1; /*!< [6..6] EEPROM Read Byte Indication                                        */
22639             __IM uint16_t  PROMSIZE  : 1; /*!< [7..7] EEPROM Algorithm Indication                                        */
22640             __IOM uint16_t COMMAND   : 3; /*!< [10..8] Command                                                           */
22641             __IM uint16_t  CKSUMERR  : 1; /*!< [11..11] Checksum Error Indication                                        */
22642             __IM uint16_t  LOADSTA   : 1; /*!< [12..12] EEPROM Loading Status Indication                                 */
22643             __IM uint16_t  ACKCMDERR : 1; /*!< [13..13] Acknowledge/Command Error Indication                             */
22644             __IM uint16_t  WRENERR   : 1; /*!< [14..14] Write Enable Error Indication                                    */
22645             __IM uint16_t  BUSY      : 1; /*!< [15..15] EEPROM Interface State Indication                                */
22646         } EEP_CONT_STAT_b;
22647     };
22648 
22649     union
22650     {
22651         __IOM uint32_t EEP_ADR;          /*!< (@ 0x00000504) EEPROM Address Register                                    */
22652 
22653         struct
22654         {
22655             __IOM uint32_t ADDRESS : 32; /*!< [31..0] EEPROM Address Setting                                            */
22656         } EEP_ADR_b;
22657     };
22658 
22659     union
22660     {
22661         __IOM uint32_t EEP_DATA;        /*!< (@ 0x00000508) EEPROM Data Register                                       */
22662 
22663         struct
22664         {
22665             __IOM uint32_t LODATA : 16; /*!< [15..0] Data to be written to the EEPROM or data read from the
22666                                          *   EEPROM (lower 2 bytes)                                                    */
22667             __IM uint32_t HIDATA : 16;  /*!< [31..16] Data read from the EEPROM (upper 2 bytes)                        */
22668         } EEP_DATA_b;
22669     };
22670     __IM uint32_t RESERVED41;
22671 
22672     union
22673     {
22674         __IOM uint16_t MII_CONT_STAT;     /*!< (@ 0x00000510) MII Management Control/Status Register                     */
22675 
22676         struct
22677         {
22678             __IM uint16_t  WREN      : 1; /*!< [0..0] Write Enable                                                       */
22679             __IM uint16_t  PDICTRL   : 1; /*!< [1..1] PDI Control Indication                                             */
22680             __IM uint16_t  MILINK    : 1; /*!< [2..2] MI Link Detection                                                  */
22681             __IM uint16_t  PHYOFFSET : 5; /*!< [7..3] PHY Address Offset Indication                                      */
22682             __IOM uint16_t COMMAND   : 2; /*!< [9..8] Command                                                            */
22683             uint16_t                 : 3;
22684             __IOM uint16_t READERR   : 1; /*!< [13..13] Read Error Indication                                            */
22685             __IM uint16_t  CMDERR    : 1; /*!< [14..14] Command Error Indication                                         */
22686             __IM uint16_t  BUSY      : 1; /*!< [15..15] MII Management State Indication                                  */
22687         } MII_CONT_STAT_b;
22688     };
22689 
22690     union
22691     {
22692         __IOM uint8_t PHY_ADR;         /*!< (@ 0x00000512) PHY Address Register                                       */
22693 
22694         struct
22695         {
22696             __IOM uint8_t PHYADDR : 5; /*!< [4..0] PHY Address Setting                                                */
22697             uint8_t               : 3;
22698         } PHY_ADR_b;
22699     };
22700 
22701     union
22702     {
22703         __IOM uint8_t PHY_REG_ADR;        /*!< (@ 0x00000513) PHY Register Address Register                              */
22704 
22705         struct
22706         {
22707             __IOM uint8_t PHYREGADDR : 5; /*!< [4..0] Address of PHY register                                            */
22708             uint8_t                  : 3;
22709         } PHY_REG_ADR_b;
22710     };
22711 
22712     union
22713     {
22714         __IOM uint16_t PHY_DATA;            /*!< (@ 0x00000514) PHY Data Register                                          */
22715 
22716         struct
22717         {
22718             __IOM uint16_t PHYREGDATA : 16; /*!< [15..0] PHY Register Data Indication/Setting                              */
22719         } PHY_DATA_b;
22720     };
22721 
22722     union
22723     {
22724         __IM uint8_t MII_ECAT_ACS_STAT; /*!< (@ 0x00000516) MII Management ECAT Access State Register                  */
22725 
22726         struct
22727         {
22728             __IM uint8_t ACSMII : 1;    /*!< [0..0] MII Management Interface Access Right Setting                      */
22729             uint8_t             : 7;
22730         } MII_ECAT_ACS_STAT_b;
22731     };
22732 
22733     union
22734     {
22735         __IOM uint8_t MII_PDI_ACS_STAT; /*!< (@ 0x00000517) MII Management PDI Access State Register                   */
22736 
22737         struct
22738         {
22739             __IOM uint8_t ACSMII : 1;   /*!< [0..0] Right of access to the MII management interface                    */
22740             __IM uint8_t  FORPDI : 1;   /*!< [1..1] Forced change of access by the PDI (forced change of
22741                                          *   bit 0)                                                                    */
22742             uint8_t : 6;
22743         } MII_PDI_ACS_STAT_b;
22744     };
22745     __IM uint32_t         RESERVED42[58];
22746     __IOM R_ESC_FMMU_Type FMMU[8];     /*!< (@ 0x00000600) FMMU [0..7] Registers (n = 0 to 7)                         */
22747     __IM uint32_t         RESERVED43[96];
22748     __IOM R_ESC_SM_Type   SM[8];       /*!< (@ 0x00000800) SyncManager [0..7] Registers (n = 0 to 7)                  */
22749     __IM uint32_t         RESERVED44[48];
22750 
22751     union
22752     {
22753         __IM uint32_t DC_RCV_TIME_PORT[3]; /*!< (@ 0x00000900) Receive Time Port [0..2] Register                          */
22754 
22755         struct
22756         {
22757             __IM uint32_t RCVTIME0 : 32;   /*!< [31..0] Receive Time Indication/Latch                                     */
22758         } DC_RCV_TIME_PORT_b[3];
22759     };
22760     __IM uint32_t RESERVED45;
22761     __IM uint32_t DC_SYS_TIME_L;           /*!< (@ 0x00000910) System Time Register L                                     */
22762     __IM uint32_t DC_SYS_TIME_H;           /*!< (@ 0x00000914) System Time Register H                                     */
22763     __IM uint32_t DC_RCV_TIME_UNIT_L;      /*!< (@ 0x00000918) Receive Time ECAT Processing Unit Register L               */
22764     __IM uint32_t DC_RCV_TIME_UNIT_H;      /*!< (@ 0x0000091C) Receive Time ECAT Processing Unit Register H               */
22765     __IM uint32_t DC_SYS_TIME_OFFSET_L;    /*!< (@ 0x00000920) System Time Offset Register L                              */
22766     __IM uint32_t DC_SYS_TIME_OFFSET_H;    /*!< (@ 0x00000924) System Time Offset Register H                              */
22767 
22768     union
22769     {
22770         __IM uint32_t DC_SYS_TIME_DELAY;   /*!< (@ 0x00000928) System Time Delay Register                                 */
22771 
22772         struct
22773         {
22774             __IM uint32_t SYSTIMDLY : 32;  /*!< [31..0] Propagation Delay Indication                                      */
22775         } DC_SYS_TIME_DELAY_b;
22776     };
22777 
22778     union
22779     {
22780         __IM uint32_t DC_SYS_TIME_DIFF; /*!< (@ 0x0000092C) System Time Difference Register                            */
22781 
22782         struct
22783         {
22784             __IM uint32_t DIFF : 31;    /*!< [30..0] System Time Mean Difference Indication                            */
22785             __IM uint32_t LCP  : 1;     /*!< [31..31] System Time Greater/Less Indication                              */
22786         } DC_SYS_TIME_DIFF_b;
22787     };
22788 
22789     union
22790     {
22791         __IM uint16_t DC_SPEED_COUNT_START; /*!< (@ 0x00000930) Speed Counter Start Register                               */
22792 
22793         struct
22794         {
22795             __IM uint16_t SPDCNTSTRT : 15;  /*!< [14..0] Drift Correction Bandwidth Setting                                */
22796             uint16_t                 : 1;
22797         } DC_SPEED_COUNT_START_b;
22798     };
22799 
22800     union
22801     {
22802         __IM uint16_t DC_SPEED_COUNT_DIFF; /*!< (@ 0x00000932) Speed Counter Difference Register                          */
22803 
22804         struct
22805         {
22806             __IM uint16_t SPDCNTDIFF : 16; /*!< [15..0] Clock Period Deviation Indication                                 */
22807         } DC_SPEED_COUNT_DIFF_b;
22808     };
22809 
22810     union
22811     {
22812         __IM uint8_t DC_SYS_TIME_DIFF_FIL_DEPTH; /*!< (@ 0x00000934) System Time Difference Filter Depth Register               */
22813 
22814         struct
22815         {
22816             __IM uint8_t SYSTIMDEP : 4;          /*!< [3..0] Filter Depth Setting                                               */
22817             uint8_t                : 4;
22818         } DC_SYS_TIME_DIFF_FIL_DEPTH_b;
22819     };
22820 
22821     union
22822     {
22823         __IM uint8_t DC_SPEED_COUNT_FIL_DEPTH; /*!< (@ 0x00000935) Speed Counter Filter Depth Register                        */
22824 
22825         struct
22826         {
22827             __IM uint8_t CLKPERDEP : 4;        /*!< [3..0] Filter Depth Setting                                               */
22828             uint8_t                : 4;
22829         } DC_SPEED_COUNT_FIL_DEPTH_b;
22830     };
22831     __IM uint16_t RESERVED46;
22832     __IM uint32_t RESERVED47[18];
22833 
22834     union
22835     {
22836         __IM uint8_t DC_CYC_CONT;      /*!< (@ 0x00000980) Cyclic Unit Control Register                               */
22837 
22838         struct
22839         {
22840             __IM uint8_t SYNCOUT : 1;  /*!< [0..0] SYNC Output Unit Control Setting                                   */
22841             uint8_t              : 3;
22842             __IM uint8_t LATCH0  : 1;  /*!< [4..4] Latch Input Unit 0 Control Setting                                 */
22843             __IM uint8_t LATCH1  : 1;  /*!< [5..5] Latch Input Unit 1 Control Setting                                 */
22844             uint8_t              : 2;
22845         } DC_CYC_CONT_b;
22846     };
22847 
22848     union
22849     {
22850         __IOM uint8_t DC_ACT;               /*!< (@ 0x00000981) Activation Register                                        */
22851 
22852         struct
22853         {
22854             __IOM uint8_t SYNCACT      : 1; /*!< [0..0] Sync Output Unit Activation                                        */
22855             __IOM uint8_t SYNC0        : 1; /*!< [1..1] SYNC0 Output Setting                                               */
22856             __IOM uint8_t SYNC1        : 1; /*!< [2..2] SYNC1 Output Setting                                               */
22857             __IOM uint8_t AUTOACT      : 1; /*!< [3..3] SYNC Output Unit Activation                                        */
22858             __IOM uint8_t EXTSTARTTIME : 1; /*!< [4..4] Start Time Cyclic Operation Extension                              */
22859             __IOM uint8_t STARTTIME    : 1; /*!< [5..5] Start Time Plausibility                                            */
22860             __IOM uint8_t NEARFUTURE   : 1; /*!< [6..6] Near Future Range Setting                                          */
22861             __IOM uint8_t DBGPULSE     : 1; /*!< [7..7] Debug Pulse Setting                                                */
22862         } DC_ACT_b;
22863     };
22864 
22865     union
22866     {
22867         __IM uint16_t DC_PULSE_LEN;      /*!< (@ 0x00000982) SYNC Signal Pulse Length Register                          */
22868 
22869         struct
22870         {
22871             __IM uint16_t PULSELEN : 16; /*!< [15..0] SYNC Signal Pulse Length Indication                               */
22872         } DC_PULSE_LEN_b;
22873     };
22874 
22875     union
22876     {
22877         __IM uint8_t DC_ACT_STAT;       /*!< (@ 0x00000984) Activation Status Register                                 */
22878 
22879         struct
22880         {
22881             __IM uint8_t SYNC0ACT  : 1; /*!< [0..0] SYNC0 Status Indication                                            */
22882             __IM uint8_t SYNC1ACT  : 1; /*!< [1..1] SYNC1 Status Indication                                            */
22883             __IM uint8_t STARTTIME : 1; /*!< [2..2] Plausibility Result Indication                                     */
22884             uint8_t                : 5;
22885         } DC_ACT_STAT_b;
22886     };
22887     __IM uint8_t  RESERVED48;
22888     __IM uint16_t RESERVED49;
22889     __IM uint32_t RESERVED50;
22890     __IM uint16_t RESERVED51;
22891 
22892     union
22893     {
22894         __IM uint8_t DC_SYNC0_STAT;    /*!< (@ 0x0000098E) SYNC0 Status Register                                      */
22895 
22896         struct
22897         {
22898             __IM uint8_t SYNC0STA : 1; /*!< [0..0] SYNC0 State Indication                                             */
22899             uint8_t               : 7;
22900         } DC_SYNC0_STAT_b;
22901     };
22902 
22903     union
22904     {
22905         __IM uint8_t DC_SYNC1_STAT;       /*!< (@ 0x0000098F) SYNC1 Status Register                                      */
22906 
22907         struct
22908         {
22909             __IM uint8_t SYNC1STA : 1;    /*!< [0..0] SYNC1 State Indication                                             */
22910             uint8_t               : 7;
22911         } DC_SYNC1_STAT_b;
22912     };
22913     __IOM uint32_t DC_CYC_START_TIME_L;   /*!< (@ 0x00000990) Start Time Cyclic Operation/Next SYNC0 Pulse
22914                                            *                  Register L                                                 */
22915     __IOM uint32_t DC_CYC_START_TIME_H;   /*!< (@ 0x00000994) Start Time Cyclic Operation/Next SYNC0 Pulse
22916                                            *                  Register H                                                 */
22917     __IM uint32_t DC_NEXT_SYNC1_PULSE_L;  /*!< (@ 0x00000998) Next SYNC1 Pulse Register L                                */
22918     __IM uint32_t DC_NEXT_SYNC1_PULSE_H;  /*!< (@ 0x0000099C) Next SYNC1 Pulse Register H                                */
22919 
22920     union
22921     {
22922         __IOM uint32_t DC_SYNC0_CYC_TIME; /*!< (@ 0x000009A0) SYNC0 Cycle Time Register                                  */
22923 
22924         struct
22925         {
22926             __IOM uint32_t SYNC0CYC : 32; /*!< [31..0] Time Between Consecutive SYNC0 Pulses                             */
22927         } DC_SYNC0_CYC_TIME_b;
22928     };
22929 
22930     union
22931     {
22932         __IOM uint32_t DC_SYNC1_CYC_TIME; /*!< (@ 0x000009A4) SYNC1 Cycle Time Register                                  */
22933 
22934         struct
22935         {
22936             __IOM uint32_t SYNC1CYC : 32; /*!< [31..0] Time between SYNC1 and SYNC0 Pulses                               */
22937         } DC_SYNC1_CYC_TIME_b;
22938     };
22939 
22940     union
22941     {
22942         __IOM uint8_t DC_LATCH0_CONT;  /*!< (@ 0x000009A8) Latch 0 Control Register                                   */
22943 
22944         struct
22945         {
22946             __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 0 Positive Edge Function Setting                             */
22947             __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 0 Negative Edge Function Setting                             */
22948             uint8_t               : 6;
22949         } DC_LATCH0_CONT_b;
22950     };
22951 
22952     union
22953     {
22954         __IOM uint8_t DC_LATCH1_CONT;  /*!< (@ 0x000009A9) Latch 1 Control Register                                   */
22955 
22956         struct
22957         {
22958             __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 1 Positive Edge Function Setting                             */
22959             __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 1 Negative Edge Function Setting                             */
22960             uint8_t               : 6;
22961         } DC_LATCH1_CONT_b;
22962     };
22963     __IM uint16_t RESERVED52[2];
22964 
22965     union
22966     {
22967         __IM uint8_t DC_LATCH0_STAT;   /*!< (@ 0x000009AE) Latch 0 Status Register                                    */
22968 
22969         struct
22970         {
22971             __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 0 Positive Edge Event Indication                             */
22972             __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 0 Negative Edge Event Indication                             */
22973             __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 0 Input Pin State Indication                                 */
22974             uint8_t               : 5;
22975         } DC_LATCH0_STAT_b;
22976     };
22977 
22978     union
22979     {
22980         __IM uint8_t DC_LATCH1_STAT;    /*!< (@ 0x000009AF) Latch 1 Status Register                                    */
22981 
22982         struct
22983         {
22984             __IM uint8_t EVENTPOS : 1;  /*!< [0..0] Latch 1 Positive Edge Event Indication                             */
22985             __IM uint8_t EVENTNEG : 1;  /*!< [1..1] Latch 1 Negative Edge Event Indication                             */
22986             __IM uint8_t PINSTATE : 1;  /*!< [2..2] Latch 1 Input Pin State Indication                                 */
22987             uint8_t               : 5;
22988         } DC_LATCH1_STAT_b;
22989     };
22990     __IM uint32_t DC_LATCH0_TIME_POS_L; /*!< (@ 0x000009B0) Latch 0 Time Positive Edge Register L                      */
22991     __IM uint32_t DC_LATCH0_TIME_POS_H; /*!< (@ 0x000009B4) Latch 0 Time Positive Edge Register H                      */
22992     __IM uint32_t DC_LATCH0_TIME_NEG_L; /*!< (@ 0x000009B8) Latch 0 Time Negative Edge Register L                      */
22993     __IM uint32_t DC_LATCH0_TIME_NEG_H; /*!< (@ 0x000009BC) Latch 0 Time Negative Edge Register H                      */
22994     __IM uint32_t DC_LATCH1_TIME_POS_L; /*!< (@ 0x000009C0) Latch 1 Time Positive Edge Register L                      */
22995     __IM uint32_t DC_LATCH1_TIME_POS_H; /*!< (@ 0x000009C4) Latch 1 Time Positive Edge Register H                      */
22996     __IM uint32_t DC_LATCH1_TIME_NEG_L; /*!< (@ 0x000009C8) Latch 1 Time Negative Edge Register L                      */
22997     __IM uint32_t DC_LATCH1_TIME_NEG_H; /*!< (@ 0x000009CC) Latch 1 Time Negative Edge Register H                      */
22998     __IM uint32_t RESERVED53[8];
22999 
23000     union
23001     {
23002         __IM uint32_t DC_ECAT_CNG_EV_TIME; /*!< (@ 0x000009F0) Buffer Change Event Time Register                          */
23003 
23004         struct
23005         {
23006             __IM uint32_t ECATCHANGE : 32; /*!< [31..0] Local Time Indication                                             */
23007         } DC_ECAT_CNG_EV_TIME_b;
23008     };
23009     __IM uint32_t RESERVED54;
23010 
23011     union
23012     {
23013         __IM uint32_t DC_PDI_START_EV_TIME; /*!< (@ 0x000009F8) PDI Buffer Start Event Time Register                       */
23014 
23015         struct
23016         {
23017             __IM uint32_t PDISTART : 32;    /*!< [31..0] Local Time Indication                                             */
23018         } DC_PDI_START_EV_TIME_b;
23019     };
23020 
23021     union
23022     {
23023         __IM uint32_t DC_PDI_CNG_EV_TIME; /*!< (@ 0x000009FC) PDI Buffer Change Event Time Register                      */
23024 
23025         struct
23026         {
23027             __IM uint32_t PDICHANGE : 32; /*!< [31..0] Local Time Indication                                             */
23028         } DC_PDI_CNG_EV_TIME_b;
23029     };
23030     __IM uint32_t RESERVED55[256];
23031     __IM uint32_t PRODUCT_ID_L;           /*!< (@ 0x00000E00) Product ID Register L                                      */
23032     __IM uint32_t PRODUCT_ID_H;           /*!< (@ 0x00000E04) Product ID Register H                                      */
23033 
23034     union
23035     {
23036         __IM uint32_t VENDOR_ID_L;        /*!< (@ 0x00000E08) Vendor ID Register L                                       */
23037 
23038         struct
23039         {
23040             __IM uint32_t VENDORID : 32;  /*!< [31..0] Vendor ID Indication                                              */
23041         } VENDOR_ID_L_b;
23042     };
23043 } R_ESC_Type;                             /*!< Size = 3596 (0xe0c)                                                       */
23044 
23045 /* =========================================================================================================================== */
23046 /* ================                                          R_USBHC                                          ================ */
23047 /* =========================================================================================================================== */
23048 
23049 /**
23050  * @brief USB 2.0 HS Host Module (R_USBHC)
23051  */
23052 
23053 typedef struct                         /*!< (@ 0x80200000) R_USBHC Structure                                          */
23054 {
23055     union
23056     {
23057         __IM uint32_t HCREVISION;      /*!< (@ 0x00000000) HcRevision Register                                        */
23058 
23059         struct
23060         {
23061             __IM uint32_t REV : 8;     /*!< [7..0] HCI revision                                                       */
23062             uint32_t          : 24;
23063         } HCREVISION_b;
23064     };
23065 
23066     union
23067     {
23068         __IOM uint32_t HCCONTROL;      /*!< (@ 0x00000004) HcControl Register                                         */
23069 
23070         struct
23071         {
23072             __IOM uint32_t CBSR : 2;   /*!< [1..0] Control/bulk transfer service ratio (ControlBulkServiceRatio)      */
23073             __IOM uint32_t PLE  : 1;   /*!< [2..2] Periodic list setting (PeriodicListEnable)                         */
23074             __IOM uint32_t IE   : 1;   /*!< [3..3] Isochronous ED processing setting (IsochronousEnable)              */
23075             __IOM uint32_t CLE  : 1;   /*!< [4..4] Control list processing setting (ControlListEnable)                */
23076             __IOM uint32_t BLE  : 1;   /*!< [5..5] Bulk list processing setting (BulkListEnable)                      */
23077             __IOM uint32_t HCFS : 2;   /*!< [7..6] Host logic operation status (Host Controller FunctionalState)      */
23078             __IOM uint32_t IR   : 1;   /*!< [8..8] HcInterruptStatus interrupt path setting (InterruptRouting)        */
23079             __IOM uint32_t RWC  : 1;   /*!< [9..9] Remote Wakeup support setting (RemoteWakeUpConnect)                */
23080             __IOM uint32_t RWE  : 1;   /*!< [10..10] PME assertion control (RemoteWakeUpEnable)                       */
23081             uint32_t            : 21;
23082         } HCCONTROL_b;
23083     };
23084 
23085     union
23086     {
23087         __IOM uint32_t HCCOMMANDSTATUS; /*!< (@ 0x00000008) HcCommandStatus Register                                   */
23088 
23089         struct
23090         {
23091             __OM uint32_t  HCR : 1;     /*!< [0..0] Host logic software reset start (HostController Reset)             */
23092             __IOM uint32_t CLF : 1;     /*!< [1..1] Control list TD (ControlList Filled)                               */
23093             __IOM uint32_t BLF : 1;     /*!< [2..2] Bulk list TD (BulkListFilled)                                      */
23094             __OM uint32_t  OCR : 1;     /*!< [3..3] Host logic control right change (OwnershipChangeRequest)           */
23095             uint32_t           : 12;
23096             __IM uint32_t SOC  : 2;     /*!< [17..16] Schedule overrun count (Scheduling OverrunCount)                 */
23097             uint32_t           : 14;
23098         } HCCOMMANDSTATUS_b;
23099     };
23100 
23101     union
23102     {
23103         __IOM uint32_t HCINTERRUPTSTATUS; /*!< (@ 0x0000000C) HcInterruptStatus Register                                 */
23104 
23105         struct
23106         {
23107             __IOM uint32_t SO  : 1;       /*!< [0..0] USB schedule overrun (Scheduling Overrun)                          */
23108             __IOM uint32_t WDH : 1;       /*!< [1..1] Host logic HccaDoneHead update (Writeback Done Head)               */
23109             __IOM uint32_t SF  : 1;       /*!< [2..2] HccaFrameNumber update (StartOfFrame)                              */
23110             __IOM uint32_t RD  : 1;       /*!< [3..3] Resume detection (Resume Detected)                                 */
23111             __IOM uint32_t UE  : 1;       /*!< [4..4] USB non-related system error detection (Unrecoverable
23112                                            *   Error)                                                                    */
23113             __IOM uint32_t FNO  : 1;      /*!< [5..5] FrameNumber bit MSB change (Frame Number Overflow)                 */
23114             __IOM uint32_t RHSC : 1;      /*!< [6..6] HcRhStatus/HcRhPortStatus register status (RootHubStatus
23115                                            *   Change)                                                                   */
23116             uint32_t          : 23;
23117             __IOM uint32_t OC : 1;        /*!< [30..30] Host logic control right change (OwnershipChange)                */
23118             uint32_t          : 1;
23119         } HCINTERRUPTSTATUS_b;
23120     };
23121 
23122     union
23123     {
23124         __IOM uint32_t HCINTERRUPTENABLE; /*!< (@ 0x00000010) HcInterruptEnable Register                                 */
23125 
23126         struct
23127         {
23128             __IOM uint32_t SOE   : 1;     /*!< [0..0] SO interrupt source enable (Scheduling OverrunEnable)              */
23129             __IOM uint32_t WDHE  : 1;     /*!< [1..1] WDH interrupt source enable (WritebackDone HeadEnable)             */
23130             __IOM uint32_t SFE   : 1;     /*!< [2..2] SF interrupt source enable (StartOfFrame)                          */
23131             __IOM uint32_t RDE   : 1;     /*!< [3..3] RD interrupt source enable (Resume DetectedEnable)                 */
23132             __IOM uint32_t UEE   : 1;     /*!< [4..4] UE interrupt source enable (Unrecoverable ErrorEnable)             */
23133             __IOM uint32_t FNOE  : 1;     /*!< [5..5] FNO interrupt source enable (FrameNumber OverflowEnable)           */
23134             __IOM uint32_t RHSCE : 1;     /*!< [6..6] RHSC interrupt source enable (RootHubStatus ChangeEnable)          */
23135             uint32_t             : 23;
23136             __IOM uint32_t OCE   : 1;     /*!< [30..30] OC interrupt source enable (OwnershipChangeEnable)               */
23137             __IOM uint32_t MIE   : 1;     /*!< [31..31] Interrupt 8 source enable (MasterInterrupt Enable)               */
23138         } HCINTERRUPTENABLE_b;
23139     };
23140 
23141     union
23142     {
23143         __IOM uint32_t HCINTERRUPTDISABLE; /*!< (@ 0x00000014) HcInterruptDisable Register                                */
23144 
23145         struct
23146         {
23147             __IOM uint32_t SOD   : 1;      /*!< [0..0] SO interrupt source disable (Scheduling Overrun Disable)           */
23148             __IOM uint32_t WDHD  : 1;      /*!< [1..1] WDH interrupt source disable (Writeback DoneHead Disable)          */
23149             __IOM uint32_t SFD   : 1;      /*!< [2..2] SF interrupt source disable (StartOfFrame Disable)                 */
23150             __IOM uint32_t RDD   : 1;      /*!< [3..3] RD interrupt source disable (Resume Detected Disable)              */
23151             __IOM uint32_t UED   : 1;      /*!< [4..4] UE interrupt source disable (Unrecoverable ErrorDisable)           */
23152             __IOM uint32_t FNOD  : 1;      /*!< [5..5] FNO interrupt source disable (FrameNumberOverflow Disable)         */
23153             __IOM uint32_t RHSCD : 1;      /*!< [6..6] RHSC interrupt source disable (RootHub StatusChange Disable)       */
23154             uint32_t             : 23;
23155             __IOM uint32_t OCD   : 1;      /*!< [30..30] OC interrupt source disable (OwnershipChangeDisable)             */
23156             __IOM uint32_t MID   : 1;      /*!< [31..31] Interrupt 8 source disable (Master Interrupt Disable)            */
23157         } HCINTERRUPTDISABLE_b;
23158     };
23159 
23160     union
23161     {
23162         __IOM uint32_t HCHCCA;         /*!< (@ 0x00000018) HcHCCA Register                                            */
23163 
23164         struct
23165         {
23166             uint32_t             : 8;
23167             __IOM uint32_t RAMBA : 24; /*!< [31..8] RAM base address setting                                          */
23168         } HCHCCA_b;
23169     };
23170 
23171     union
23172     {
23173         __IM uint32_t HCPERIODCCURRENTIED; /*!< (@ 0x0000001C) HcPeriodicCurrentED Register                               */
23174 
23175         struct
23176         {
23177             uint32_t           : 4;
23178             __IM uint32_t PCED : 28;   /*!< [31..4] ED physical address (PeriodicCurrentED)                           */
23179         } HCPERIODCCURRENTIED_b;
23180     };
23181 
23182     union
23183     {
23184         __IOM uint32_t HCCONTROLHEADED; /*!< (@ 0x00000020) HcControlHeadED Register                                   */
23185 
23186         struct
23187         {
23188             uint32_t            : 4;
23189             __IOM uint32_t CHED : 28;  /*!< [31..4] Start ED physical address (ControlHeadED)                         */
23190         } HCCONTROLHEADED_b;
23191     };
23192 
23193     union
23194     {
23195         __IOM uint32_t HCCONTROLCURRENTED; /*!< (@ 0x00000024) HcControlCurrentED Register                                */
23196 
23197         struct
23198         {
23199             uint32_t            : 4;
23200             __IOM uint32_t CCED : 28;  /*!< [31..4] ED physical address (ControlCurrentED)                            */
23201         } HCCONTROLCURRENTED_b;
23202     };
23203 
23204     union
23205     {
23206         __IOM uint32_t HCBULKHEADED;   /*!< (@ 0x00000028) HcBulkHeadED Register                                      */
23207 
23208         struct
23209         {
23210             uint32_t            : 4;
23211             __IOM uint32_t BHED : 28;  /*!< [31..4] Start ED physical address (BulkHeadED)                            */
23212         } HCBULKHEADED_b;
23213     };
23214 
23215     union
23216     {
23217         __IOM uint32_t HCBULKCURRENTED; /*!< (@ 0x0000002C) HcBulkCurrentED Register                                   */
23218 
23219         struct
23220         {
23221             uint32_t            : 4;
23222             __IOM uint32_t BCED : 28;  /*!< [31..4] ED physical address (BulkCurrentED)                               */
23223         } HCBULKCURRENTED_b;
23224     };
23225 
23226     union
23227     {
23228         __IM uint32_t HCDONEHEAD;      /*!< (@ 0x00000030) HcDoneHead Register                                        */
23229 
23230         struct
23231         {
23232             uint32_t         : 4;
23233             __IM uint32_t DH : 28;     /*!< [31..4] HcDoneHead physical address (DoneHead)                            */
23234         } HCDONEHEAD_b;
23235     };
23236 
23237     union
23238     {
23239         __IOM uint32_t HCFMINTERVAL;   /*!< (@ 0x00000034) HcFmInterval Register                                      */
23240 
23241         struct
23242         {
23243             __IOM uint32_t FI    : 14; /*!< [13..0] Frame interval setting (FrameInterval)                            */
23244             uint32_t             : 2;
23245             __IOM uint32_t FSMPS : 15; /*!< [30..16] FS transfer packet maximum size setting (FSLagest DataPacket)    */
23246             __IOM uint32_t FIT   : 1;  /*!< [31..31] Frame synchronization (FrameInterval Toggle)                     */
23247         } HCFMINTERVAL_b;
23248     };
23249 
23250     union
23251     {
23252         __IM uint32_t HCFNREMAINING;   /*!< (@ 0x00000038) HcFmRemaining Register                                     */
23253 
23254         struct
23255         {
23256             __IM uint32_t FR  : 14;    /*!< [13..0] Down counter frame (FrameRemaining)                               */
23257             uint32_t          : 17;
23258             __IM uint32_t FRT : 1;     /*!< [31..31] Frame synchronization (FrameRemainingToggle)                     */
23259         } HCFNREMAINING_b;
23260     };
23261 
23262     union
23263     {
23264         __IM uint32_t HCFMNUMBER;      /*!< (@ 0x0000003C) HcFmNumber Register                                        */
23265 
23266         struct
23267         {
23268             __IM uint32_t FN : 16;     /*!< [15..0] Elapsed frame number (FrameNumber)                                */
23269             uint32_t         : 16;
23270         } HCFMNUMBER_b;
23271     };
23272 
23273     union
23274     {
23275         __IOM uint32_t HCPERIODSTART;  /*!< (@ 0x00000040) HcPeriodicStart Register                                   */
23276 
23277         struct
23278         {
23279             __IOM uint32_t PS : 14;    /*!< [13..0] Periodic list processing start time (PeriodicStart)               */
23280             uint32_t          : 18;
23281         } HCPERIODSTART_b;
23282     };
23283 
23284     union
23285     {
23286         __IOM uint32_t HCLSTHRESHOLD;  /*!< (@ 0x00000044) HcLSThreshold Register                                     */
23287 
23288         struct
23289         {
23290             __IOM uint32_t LS : 12;    /*!< [11..0] Transferrable threshold (LSThreshold)                             */
23291             uint32_t          : 20;
23292         } HCLSTHRESHOLD_b;
23293     };
23294 
23295     union
23296     {
23297         __IOM uint32_t HCRHDESCRIPTORA; /*!< (@ 0x00000048) HcRhDescriptorA Register                                   */
23298 
23299         struct
23300         {
23301             __IM uint32_t  NDP  : 8;    /*!< [7..0] Downstream port number (NumberDownstreamPorts)                     */
23302             __IOM uint32_t PSM  : 1;    /*!< [8..8] Power switch control (PowerSwitchingMode)                          */
23303             __IOM uint32_t NPS  : 1;    /*!< [9..9] Power control (NoPower Switching)                                  */
23304             __IM uint32_t  DT   : 1;    /*!< [10..10] Device type (DeviceType)                                         */
23305             __IOM uint32_t OCPM : 1;    /*!< [11..11] Overcurrent state reporting (OverCurrentProtection
23306                                          *   Mode)                                                                     */
23307             __IOM uint32_t NOCP   : 1;  /*!< [12..12] Overcurrent function support (NoOver Current Protection)         */
23308             uint32_t              : 11;
23309             __IOM uint32_t POTPGT : 8;  /*!< [31..24] Wait time (PowerOnToPowerGood Time)                              */
23310         } HCRHDESCRIPTORA_b;
23311     };
23312 
23313     union
23314     {
23315         __IOM uint32_t HCRHDESCRIPTORB; /*!< (@ 0x0000004C) HcRhDescriptorB Register                                   */
23316 
23317         struct
23318         {
23319             __IOM uint32_t DR   : 16;   /*!< [15..0] Device Removable                                                  */
23320             __IOM uint32_t PPCM : 16;   /*!< [31..16] Port Power Control Mask                                          */
23321         } HCRHDESCRIPTORB_b;
23322     };
23323 
23324     union
23325     {
23326         __IOM uint32_t HCRHSTATUS;     /*!< (@ 0x00000050) HcRhStatus Register                                        */
23327 
23328         struct
23329         {
23330             __IOM uint32_t LPS  : 1;   /*!< [0..0] Local power status (LocalPowerStatus)                              */
23331             __IM uint32_t  OCI  : 1;   /*!< [1..1] Overcurrent indicator (OverCurrent Indicator)                      */
23332             uint32_t            : 13;
23333             __IOM uint32_t DRWE : 1;   /*!< [15..15] Device remote start enable (DeviceRemoteWakeupEnable)            */
23334             __IOM uint32_t LPSC : 1;   /*!< [16..16] Local power status change (LocalPowerStatusChange)               */
23335             __IOM uint32_t OCIC : 1;   /*!< [17..17] OCI bit change report (OverCurrent Indicate Change)              */
23336             uint32_t            : 13;
23337             __OM uint32_t CRWE  : 1;   /*!< [31..31] DRWE bit clear (Clear Remote Wakeup Enable)                      */
23338         } HCRHSTATUS_b;
23339     };
23340 
23341     union
23342     {
23343         __IOM uint32_t HCRHPORTSTATUS1; /*!< (@ 0x00000054) HcRhPortStatus1 Register                                   */
23344 
23345         struct
23346         {
23347             __IOM uint32_t CCS  : 1;    /*!< [0..0] Connection status indication (CurrentConnectStatus)                */
23348             __IOM uint32_t PES  : 1;    /*!< [1..1] Port enable status (PortEnableStatus)                              */
23349             __IOM uint32_t PSS  : 1;    /*!< [2..2] Suspend/Resume status (PortSuspendStatus)                          */
23350             __IM uint32_t  POCI : 1;    /*!< [3..3] Downstream port overcurrent detection (PortOverCurrentIndicator)   */
23351             __IOM uint32_t PRS  : 1;    /*!< [4..4] Port reset status (PortResetStatus)                                */
23352             uint32_t            : 3;
23353             __IOM uint32_t PPS  : 1;    /*!< [8..8] Power status (PortPowerStatus)                                     */
23354             __IOM uint32_t LSDA : 1;    /*!< [9..9] Device speed (LowSpeedDeviceAttached)                              */
23355             uint32_t            : 6;
23356             __IOM uint32_t CSC  : 1;    /*!< [16..16] CCS bit status (ConnectStatus Change)                            */
23357             __IOM uint32_t PESC : 1;    /*!< [17..17] PES bit status (PortEnable StatusChange)                         */
23358             __IOM uint32_t PSSC : 1;    /*!< [18..18] RESUME sequence complete (PortSuspend StatusChange)              */
23359             __IOM uint32_t OCIC : 1;    /*!< [19..19] Overcurrent state detection (OverCurrent IndicateChange)         */
23360             __IOM uint32_t PRSC : 1;    /*!< [20..20] Port reset complete (PortReset StatusChange)                     */
23361             uint32_t            : 11;
23362         } HCRHPORTSTATUS1_b;
23363     };
23364     __IM uint32_t RESERVED[42];
23365 
23366     union
23367     {
23368         __IM uint32_t CAPL_VERSION;    /*!< (@ 0x00000100) Capability Registers Length and EHCI Version
23369                                         *                  Number Register                                            */
23370 
23371         struct
23372         {
23373             __IM uint32_t CRL   : 8;   /*!< [7..0] Capability Registers Length                                        */
23374             uint32_t            : 8;
23375             __IM uint32_t HCIVN : 16;  /*!< [31..16] EHCI Version Number                                              */
23376         } CAPL_VERSION_b;
23377     };
23378 
23379     union
23380     {
23381         __IM uint32_t HCSPARAMS;           /*!< (@ 0x00000104) Structural Parameters Register                             */
23382 
23383         struct
23384         {
23385             __IM uint32_t N_PORTS     : 4; /*!< [3..0] Number of downstream ports (Number of Ports)                       */
23386             __IM uint32_t PPC         : 1; /*!< [4..4] Port power control (Port Power Control)                            */
23387             uint32_t                  : 2;
23388             __IM uint32_t PTRR        : 1; /*!< [7..7] Port routing rules                                                 */
23389             __IM uint32_t N_PCC       : 4; /*!< [11..8] Number of ports (Number of Ports per Companion Controller)        */
23390             __IM uint32_t N_CC        : 4; /*!< [15..12] Number of OHCI host logic (Number of Companion Controller)       */
23391             __IM uint32_t P_INDICATOR : 1; /*!< [16..16] Port indicator control support                                   */
23392             uint32_t                  : 3;
23393             __IM uint32_t DBGPTNUM    : 4; /*!< [23..20] Debug port number                                                */
23394             uint32_t                  : 8;
23395         } HCSPARAMS_b;
23396     };
23397 
23398     union
23399     {
23400         __IM uint32_t HCCPARAMS;       /*!< (@ 0x00000108) Capability Parameters Register                             */
23401 
23402         struct
23403         {
23404             __IM uint32_t AC64 : 1;    /*!< [0..0] Memory pointer selection                                           */
23405             __IM uint32_t PFLF : 1;    /*!< [1..1] Programming frame list flag                                        */
23406             __IM uint32_t ASPC : 1;    /*!< [2..2] Asynchronous schedule park support capability                      */
23407             uint32_t           : 1;
23408             __IM uint32_t IST  : 4;    /*!< [7..4] Isochronous data structure threshold                               */
23409             __IM uint32_t EECP : 8;    /*!< [15..8] Offset address (EHCI Extend Capabilities Pointer)                 */
23410             __IM uint32_t HP   : 1;    /*!< [16..16] Hardware prefetch capability                                     */
23411             __IM uint32_t LPMC : 1;    /*!< [17..17] Link power management capability                                 */
23412             __IM uint32_t PCEC : 1;    /*!< [18..18] Per-port change event capability                                 */
23413             __IM uint32_t PL32 : 1;    /*!< [19..19] 32-frame periodic list capability                                */
23414             uint32_t           : 12;
23415         } HCCPARAMS_b;
23416     };
23417     __IM uint32_t HCSP_PORTROUTE;      /*!< (@ 0x0000010C) Companion Port Route Description Register                  */
23418     __IM uint32_t RESERVED1[4];
23419 
23420     union
23421     {
23422         __IOM uint32_t USBCMD;          /*!< (@ 0x00000120) USB Command Register                                       */
23423 
23424         struct
23425         {
23426             __IOM uint32_t RS      : 1; /*!< [0..0] EHCI host logic run/stop (Run/Stop)                                */
23427             __IOM uint32_t HCRESET : 1; /*!< [1..1] Host logic initialization (Host Controller Reset)                  */
23428             __IOM uint32_t FLS     : 2; /*!< [3..2] Frame list size                                                    */
23429             __IOM uint32_t PSE     : 1; /*!< [4..4] Periodic schedule enable                                           */
23430             __IOM uint32_t ASYNSE  : 1; /*!< [5..5] Asynchronous schedule enable                                       */
23431             __IOM uint32_t IAAD    : 1; /*!< [6..6] Interrupt on Async Advance Doorbell                                */
23432             __IM uint32_t  LHCR    : 1; /*!< [7..7] Light host controller reset execution status                       */
23433             __IOM uint32_t ASPMC   : 2; /*!< [9..8] Asynchronous schedule park mode count                              */
23434             uint32_t               : 1;
23435             __IOM uint32_t ASPME   : 1; /*!< [11..11] Asynchronous schedule park mode enable                           */
23436             uint32_t               : 3;
23437             __IOM uint32_t PPCEE   : 1; /*!< [15..15] Per-port change event enable                                     */
23438             __IOM uint32_t ITC     : 8; /*!< [23..16] Host logic interrupt generation maximum rate (Interrupt
23439                                          *   Threshold Control)                                                        */
23440             __IOM uint32_t HIRD : 4;    /*!< [27..24] Host-Initiated Resume Duration (Minimum K-state drive
23441                                          *   time)                                                                     */
23442             uint32_t : 4;
23443         } USBCMD_b;
23444     };
23445 
23446     union
23447     {
23448         __IOM uint32_t USBSTS;             /*!< (@ 0x00000124) USB Status Register                                        */
23449 
23450         struct
23451         {
23452             __IOM uint32_t USBINT    : 1;  /*!< [0..0] USB transfer complete (USB Interrupt)                              */
23453             __IOM uint32_t USBERRINT : 1;  /*!< [1..1] USB transaction status (USB Error Interrupt)                       */
23454             __IOM uint32_t PTCGDET   : 1;  /*!< [2..2] Port state change detection                                        */
23455             __IOM uint32_t FLROV     : 1;  /*!< [3..3] Frame list rollover                                                */
23456             __IOM uint32_t HSYSE     : 1;  /*!< [4..4] Host system error                                                  */
23457             __IOM uint32_t IAAIS     : 1;  /*!< [5..5] Async advance interrupt status                                     */
23458             uint32_t                 : 6;
23459             __IM uint32_t  EHCSTS    : 1;  /*!< [12..12] EHCI host logic status (HCHalted)                                */
23460             __IM uint32_t  RECLAM    : 1;  /*!< [13..13] Empty asynchronous schedule detection (Reclamation)              */
23461             __IM uint32_t  PSCHSTS   : 1;  /*!< [14..14] Periodic schedule status                                         */
23462             __IM uint32_t  ASS       : 1;  /*!< [15..15] Asynchronous schedule status                                     */
23463             __IOM uint32_t PTCGDETC  : 16; /*!< [31..16] Port-n Change Detect                                             */
23464         } USBSTS_b;
23465     };
23466 
23467     union
23468     {
23469         __IOM uint32_t USBINTR;           /*!< (@ 0x00000128) USB Interrupt Enable Register                              */
23470 
23471         struct
23472         {
23473             __IOM uint32_t USBIE    : 1;  /*!< [0..0] USB interrupt enable                                               */
23474             __IOM uint32_t USBEIE   : 1;  /*!< [1..1] USB error interrupt enable                                         */
23475             __IOM uint32_t PTCGIE   : 1;  /*!< [2..2] Port change interrupt enable                                       */
23476             __IOM uint32_t FMLSTROE : 1;  /*!< [3..3] Frame list rollover enable                                         */
23477             __IOM uint32_t HSEE     : 1;  /*!< [4..4] Host system error enable                                           */
23478             __IOM uint32_t INTAADVE : 1;  /*!< [5..5] Interrupt on async advance enable                                  */
23479             uint32_t                : 10;
23480             __IOM uint32_t PCGIE    : 16; /*!< [31..16] Port-n Change Interrupt Enable                                   */
23481         } USBINTR_b;
23482     };
23483 
23484     union
23485     {
23486         __IOM uint32_t FRINDEX;             /*!< (@ 0x0000012C) USB Frame Index Register                                   */
23487 
23488         struct
23489         {
23490             __IOM uint32_t FRAMEINDEX : 14; /*!< [13..0] Frame index                                                       */
23491             uint32_t                  : 18;
23492         } FRINDEX_b;
23493     };
23494     __IM uint32_t CTRLDSSEGMENT;            /*!< (@ 0x00000130) Control Data Structure Segment Register                    */
23495 
23496     union
23497     {
23498         __IOM uint32_t PERIODICLISTBASE;    /*!< (@ 0x00000134) Periodic Frame List Base Address Register                  */
23499 
23500         struct
23501         {
23502             uint32_t             : 12;
23503             __IOM uint32_t PFLSA : 20; /*!< [31..12] Periodic frame list start address                                */
23504         } PERIODICLISTBASE_b;
23505     };
23506 
23507     union
23508     {
23509         __IOM uint32_t ASYNCLISTADDR;  /*!< (@ 0x00000138) Next Asynchronous List Address Register                    */
23510 
23511         struct
23512         {
23513             uint32_t           : 5;
23514             __IOM uint32_t LPL : 27;   /*!< [31..5] Asynchronous Queue Head link pointer address (Link Pointer
23515                                         *   Low)                                                                      */
23516         } ASYNCLISTADDR_b;
23517     };
23518     __IM uint32_t RESERVED2[9];
23519 
23520     union
23521     {
23522         __IOM uint32_t CONFIGFLAG;     /*!< (@ 0x00000160) Configure Flag Register                                    */
23523 
23524         struct
23525         {
23526             __IOM uint32_t CF : 1;     /*!< [0..0] Port routing control circuit configuration flag (Configure
23527                                         *   Flag)                                                                     */
23528             uint32_t : 31;
23529         } CONFIGFLAG_b;
23530     };
23531 
23532     union
23533     {
23534         __IOM uint32_t PORTSC1;            /*!< (@ 0x00000164) Port 1 Status and Control Register                         */
23535 
23536         struct
23537         {
23538             __IM uint32_t  CCSTS    : 1;   /*!< [0..0] Port connection status                                             */
23539             __IOM uint32_t CSC      : 1;   /*!< [1..1] Connect status change                                              */
23540             __IOM uint32_t PTE      : 1;   /*!< [2..2] Port enable/disable status                                         */
23541             __IOM uint32_t PTESC    : 1;   /*!< [3..3] Port enable/disable status change                                  */
23542             __IM uint32_t  OVCACT   : 1;   /*!< [4..4] Port overcurrent status                                            */
23543             __IOM uint32_t OVCC     : 1;   /*!< [5..5] Over-current Change                                                */
23544             __IOM uint32_t FRCPTRSM : 1;   /*!< [6..6] Force Port Resume (Port resume detection flag)                     */
23545             __IOM uint32_t SUSPEND  : 1;   /*!< [7..7] Port suspend                                                       */
23546             __IOM uint32_t PTRST    : 1;   /*!< [8..8] Port reset status                                                  */
23547             __IOM uint32_t LPMCTL   : 1;   /*!< [9..9] LPM control                                                        */
23548             __IM uint32_t  LINESTS  : 2;   /*!< [11..10] D+/D- logic level                                              */
23549             __IOM uint32_t PP       : 1;   /*!< [12..12] Port Power Supply Control (Port Power)                           */
23550             __IOM uint32_t PTOWNR   : 1;   /*!< [13..13] Port ownership                                                   */
23551             __IM uint32_t  PTINDCTL : 2;   /*!< [15..14] As the host logic does not support the port indicator
23552                                             *   control function, these bits are set to 00b.                              */
23553             __IOM uint32_t PTTST    : 4;   /*!< [19..16] Pin test control                                                 */
23554             __IOM uint32_t WKCNNT_E : 1;   /*!< [20..20] Device connection detection enable (Wake on Connect
23555                                             *   Enable)                                                                   */
23556             __IOM uint32_t WKDSCNNT_E : 1; /*!< [21..21] Device disconnection detection enable (Wake on Disconnect
23557                                             *   Enable)                                                                   */
23558             __IOM uint32_t WKOC_E : 1;     /*!< [22..22] Overcurrent state detection enable (Wake on Over-current
23559                                             *   Enable)                                                                   */
23560             __IOM uint32_t SUSPSTS : 2;    /*!< [24..23] Suspend status                                                   */
23561             __IOM uint32_t DVADDR  : 7;    /*!< [31..25] USB device address                                               */
23562         } PORTSC1_b;
23563     };
23564     __IM uint32_t RESERVED3[38];
23565 
23566     union
23567     {
23568         __IOM uint32_t INTENABLE;            /*!< (@ 0x00000200) INT_ENABLE Register                                        */
23569 
23570         struct
23571         {
23572             __IOM uint32_t AHB_INTEN    : 1; /*!< [0..0] AHB_INT bit control                                                */
23573             __IOM uint32_t USBH_INTAEN  : 1; /*!< [1..1] USBH_INTA bit control                                              */
23574             __IOM uint32_t USBH_INTBEN  : 1; /*!< [2..2] USBH_INTB bit control                                              */
23575             __IOM uint32_t UCOM_INTEN   : 1; /*!< [3..3] UCOM_INT bit control                                               */
23576             __IOM uint32_t WAKEON_INTEN : 1; /*!< [4..4] WAKEON_INT bit control                                             */
23577             uint32_t                    : 27;
23578         } INTENABLE_b;
23579     };
23580 
23581     union
23582     {
23583         __IOM uint32_t INTSTATUS;          /*!< (@ 0x00000204) INT_STATUS Register                                        */
23584 
23585         struct
23586         {
23587             __IOM uint32_t AHB_INT    : 1; /*!< [0..0] AHB bus error indication                                           */
23588             __IM uint32_t  USBH_INTA  : 1; /*!< [1..1] OHCI interrupt status                                              */
23589             __IM uint32_t  USBH_INTB  : 1; /*!< [2..2] USBH_INTB EHCI interrupt status                                    */
23590             __IM uint32_t  UCOM_INT   : 1; /*!< [3..3] UCOM register interrupt status                                     */
23591             __IOM uint32_t WAKEON_INT : 1; /*!< [4..4] WAKEON interrupt status                                            */
23592             uint32_t                  : 27;
23593         } INTSTATUS_b;
23594     };
23595 
23596     union
23597     {
23598         __IOM uint32_t AHBBUSCTR;             /*!< (@ 0x00000208) AHB_BUS_CTR Register                                       */
23599 
23600         struct
23601         {
23602             __IOM uint32_t MAX_BURST_LEN : 2; /*!< [1..0] Maximum burst length                                               */
23603             uint32_t                     : 2;
23604             __IOM uint32_t ALIGN_ADDRESS : 2; /*!< [5..4] Address boundary setting                                           */
23605             uint32_t                     : 2;
23606             __IOM uint32_t PROT_MODE     : 1; /*!< [8..8] This bit selects the MHPROT[3:0] mode when the AHB master
23607                                                *   interface initiates a transfer.                                           */
23608             uint32_t                 : 3;
23609             __IOM uint32_t PROT_TYPE : 4;     /*!< [15..12] These bits set MHPROT[3:0] when the AHB master interface
23610                                                *   initiates a transfer.                                                     */
23611             uint32_t : 16;
23612         } AHBBUSCTR_b;
23613     };
23614 
23615     union
23616     {
23617         __IOM uint32_t USBCTR;           /*!< (@ 0x0000020C) USBCTR Register                                            */
23618 
23619         struct
23620         {
23621             __OM uint32_t  USBH_RST : 1; /*!< [0..0] Software reset for the core                                        */
23622             __IOM uint32_t PLL_RST  : 1; /*!< [1..1] Reset of USB PHY PLL                                               */
23623             __IOM uint32_t DIRPD    : 1; /*!< [2..2] Direct transition to power-down state                              */
23624             uint32_t                : 29;
23625         } USBCTR_b;
23626     };
23627     __IM uint32_t RESERVED4[60];
23628 
23629     union
23630     {
23631         __IM uint32_t REVID;           /*!< (@ 0x00000300) Revision and Core ID Register                              */
23632 
23633         struct
23634         {
23635             __IM uint32_t MINV   : 8;  /*!< [7..0] Minor Version                                                      */
23636             __IM uint32_t MAJV   : 8;  /*!< [15..8] Major Version                                                     */
23637             uint32_t             : 8;
23638             __IM uint32_t COREID : 8;  /*!< [31..24] Core ID                                                          */
23639         } REVID_b;
23640     };
23641     __IM uint32_t RESERVED5[3];
23642 
23643     union
23644     {
23645         __IOM uint32_t OCSLPTIMSET;          /*!< (@ 0x00000310) Overcurrent Detection/Sleep Timer Setting Register         */
23646 
23647         struct
23648         {
23649             __IOM uint32_t TIMER_OC    : 20; /*!< [19..0] Overcurrent Timer setting                                         */
23650             __IOM uint32_t TIMER_SLEEP : 9;  /*!< [28..20] Detection/Sleep Timer Setting                                    */
23651             uint32_t                   : 3;
23652         } OCSLPTIMSET_b;
23653     };
23654     __IM uint32_t RESERVED6[315];
23655 
23656     union
23657     {
23658         __IOM uint32_t COMMCTRL;       /*!< (@ 0x00000800) Common Control Register                                    */
23659 
23660         struct
23661         {
23662             uint32_t            : 31;
23663             __IOM uint32_t PERI : 1;   /*!< [31..31] USB mode setting                                                 */
23664         } COMMCTRL_b;
23665     };
23666 
23667     union
23668     {
23669         __IOM uint32_t OBINTSTA;             /*!< (@ 0x00000804) OTG-BC Interrupt Status Register                           */
23670 
23671         struct
23672         {
23673             __IOM uint32_t IDCHG_STA    : 1; /*!< [0..0] USB_OTGID change status                                            */
23674             __IOM uint32_t OCINT_STA    : 1; /*!< [1..1] USB_OVRCUR assertion status                                        */
23675             __IOM uint32_t VBSTACHG_STA : 1; /*!< [2..2] VBSTA[3:0] change status                                           */
23676             __IOM uint32_t VBSTAINT_STA : 1; /*!< [3..3] VBUS voltage status interrupt                                      */
23677             uint32_t                    : 12;
23678             __IOM uint32_t DMMONCHG_STA : 1; /*!< [16..16] DMMON change status                                              */
23679             __IOM uint32_t DPMONCHG_STA : 1; /*!< [17..17] DPMON change status                                              */
23680             uint32_t                    : 14;
23681         } OBINTSTA_b;
23682     };
23683 
23684     union
23685     {
23686         __IOM uint32_t OBINTEN;             /*!< (@ 0x00000808) OTG-BC Interrupt Enable Register                           */
23687 
23688         struct
23689         {
23690             __IOM uint32_t IDCHG_EN    : 1; /*!< [0..0] IDCHG_STA Interrupt enable                                         */
23691             __IOM uint32_t OCINT_EN    : 1; /*!< [1..1] OCINT_STA interrupt enable                                         */
23692             __IOM uint32_t VBSTACHG_EN : 1; /*!< [2..2] VBSTACHG_STA interrupt enable                                      */
23693             __IOM uint32_t VBSTAINT_EN : 1; /*!< [3..3] VBSTAINT_STA interrupt enable                                      */
23694             uint32_t                   : 12;
23695             __IOM uint32_t DMMONCHG_EN : 1; /*!< [16..16] DMMONCHG_STA interrupt enable                                    */
23696             __IOM uint32_t DPMONCHG_EN : 1; /*!< [17..17] DPMONCHG_STA interrupt enable                                    */
23697             uint32_t                   : 14;
23698         } OBINTEN_b;
23699     };
23700 
23701     union
23702     {
23703         __IOM uint32_t VBCTRL;            /*!< (@ 0x0000080C) VBUS Control Register                                      */
23704 
23705         struct
23706         {
23707             __IOM uint32_t VBOUT     : 1; /*!< [0..0] VBUS drive control (USB_VBUSEN pin)                                */
23708             __IOM uint32_t VBUSENSEL : 1; /*!< [1..1] USB_VBUSEN pin control                                             */
23709             uint32_t                 : 2;
23710             __IOM uint32_t VGPUO     : 1; /*!< [4..4] USB_EXICEN pin control                                             */
23711             uint32_t                 : 11;
23712             __IOM uint32_t OCCLRIEN  : 1; /*!< [16..16] USB_VBUSEN pin control at occurrence of overcurrent              */
23713             __IOM uint32_t OCISEL    : 1; /*!< [17..17] Overcurrent detection                                            */
23714             uint32_t                 : 2;
23715             __IOM uint32_t VBLVL     : 4; /*!< [23..20] VBUS level detection                                             */
23716             uint32_t                 : 4;
23717             __IM uint32_t VBSTA      : 4; /*!< [31..28] VBUS indication                                                  */
23718         } VBCTRL_b;
23719     };
23720 
23721     union
23722     {
23723         __IOM uint32_t LINECTRL1;        /*!< (@ 0x00000810) Line Control Port 1 Register                               */
23724 
23725         struct
23726         {
23727             __IM uint32_t IDMON   : 1;   /*!< [0..0] Indicates a value of USB_OTGID input pin.                          */
23728             uint32_t              : 1;
23729             __IM uint32_t DMMON   : 1;   /*!< [2..2] Indicates a value of USB bus DM.                                   */
23730             __IM uint32_t DPMON   : 1;   /*!< [3..3] Indicates a value of USB bus DP.                                   */
23731             uint32_t              : 12;
23732             __IOM uint32_t DM_RPD : 1;   /*!< [16..16] Controls USB bus (DM) 15 kOhm pulldown resistor when
23733                                           *   DMPPD_EN = 1.                                                             */
23734             __IOM uint32_t DMRPD_EN : 1; /*!< [17..17] Enables DM_RPD to control USB bus (DM) 15 kOhm pulldown
23735                                           *   resistor.                                                                 */
23736             __IOM uint32_t DP_RPD : 1;   /*!< [18..18] Controls USB bus (DP) 15 kOhm pulldown resistor when
23737                                           *   DRPPD_EN = 1.                                                             */
23738             __IOM uint32_t DPRPD_EN : 1; /*!< [19..19] Enables DP_RPD to control USB bus (DP) 15 kOhm pulldown
23739                                           *   resistor.                                                                 */
23740             uint32_t : 12;
23741         } LINECTRL1_b;
23742     };
23743 } R_USBHC_Type;                          /*!< Size = 2068 (0x814)                                                       */
23744 
23745 /* =========================================================================================================================== */
23746 /* ================                                          R_USBF                                           ================ */
23747 /* =========================================================================================================================== */
23748 
23749 /**
23750  * @brief USB 2.0 Host and Function Module (R_USBF)
23751  */
23752 
23753 typedef struct                         /*!< (@ 0x80201000) R_USBF Structure                                           */
23754 {
23755     union
23756     {
23757         __IOM uint16_t SYSCFG0;        /*!< (@ 0x00000000) System Configuration Control Register 0                    */
23758 
23759         struct
23760         {
23761             __IOM uint16_t USBE  : 1;  /*!< [0..0] USB Block Operation Enable                                         */
23762             uint16_t             : 3;
23763             __IOM uint16_t DPRPU : 1;  /*!< [4..4] D+ Line Resistor Control                                           */
23764             __IOM uint16_t DRPD  : 1;  /*!< [5..5] D+/D- Line Resistor Control                                      */
23765             uint16_t             : 1;
23766             __IOM uint16_t HSE   : 1;  /*!< [7..7] High-Speed Operation Enable                                        */
23767             __IOM uint16_t CNEN  : 1;  /*!< [8..8] Single-End Receiver Operation Enable                               */
23768             uint16_t             : 7;
23769         } SYSCFG0_b;
23770     };
23771 
23772     union
23773     {
23774         __IOM uint16_t SYSCFG1;        /*!< (@ 0x00000002) System Configuration Control Register 1                    */
23775 
23776         struct
23777         {
23778             __IOM uint16_t BWAIT : 6;  /*!< [5..0] CPU Bus Access Wait Specification                                  */
23779             uint16_t             : 2;
23780             __IOM uint16_t AWAIT : 6;  /*!< [13..8] AHB-DMA Bridge Bus Access Wait Specification                      */
23781             uint16_t             : 2;
23782         } SYSCFG1_b;
23783     };
23784 
23785     union
23786     {
23787         __IM uint16_t SYSSTS0;         /*!< (@ 0x00000004) System Configuration Status Register                       */
23788 
23789         struct
23790         {
23791             __IM uint16_t LNST : 2;    /*!< [1..0] USB Data Line Status Monitor                                       */
23792             uint16_t           : 14;
23793         } SYSSTS0_b;
23794     };
23795     __IM uint16_t RESERVED;
23796 
23797     union
23798     {
23799         __IOM uint16_t DVSTCTR0;       /*!< (@ 0x00000008) Device State Control Register 0                            */
23800 
23801         struct
23802         {
23803             __IM uint16_t RHST  : 3;   /*!< [2..0] Reset Handshake                                                    */
23804             uint16_t            : 5;
23805             __IOM uint16_t WKUP : 1;   /*!< [8..8] Wakeup Output                                                      */
23806             uint16_t            : 7;
23807         } DVSTCTR0_b;
23808     };
23809     __IM uint16_t RESERVED1;
23810 
23811     union
23812     {
23813         __IOM uint16_t TESTMODE;       /*!< (@ 0x0000000C) USB Test Mode Register                                     */
23814 
23815         struct
23816         {
23817             __IOM uint16_t UTST : 4;   /*!< [3..0] Test Mode                                                          */
23818             uint16_t            : 12;
23819         } TESTMODE_b;
23820     };
23821     __IM uint16_t RESERVED2;
23822     __IM uint32_t RESERVED3;
23823 
23824     union
23825     {
23826         union
23827         {
23828             __IOM uint32_t CFIFO;             /*!< (@ 0x00000014) FIFO Port Register                                         */
23829 
23830             struct
23831             {
23832                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
23833             } CFIFO_b;
23834         };
23835 
23836         struct
23837         {
23838             union
23839             {
23840                 __IOM uint16_t CFIFOL;  /*!< (@ 0x00000014) FIFO Port Register                                         */
23841                 __IOM uint8_t  CFIFOLL; /*!< (@ 0x00000014) FIFO Port Register                                         */
23842             };
23843 
23844             union
23845             {
23846                 union
23847                 {
23848                     __IOM uint16_t CFIFOH;            /*!< (@ 0x00000016) FIFO Port Register                                         */
23849 
23850                     struct
23851                     {
23852                         __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
23853                     } CFIFOH_b;
23854                 };
23855 
23856                 struct
23857                 {
23858                     __IM uint8_t RESERVED4;
23859 
23860                     union
23861                     {
23862                         __IOM uint8_t CFIFOHH;          /*!< (@ 0x00000017) FIFO Port Register                                         */
23863 
23864                         struct
23865                         {
23866                             __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
23867                         } CFIFOHH_b;
23868                     };
23869                 };
23870             };
23871         };
23872     };
23873 
23874     union
23875     {
23876         union
23877         {
23878             __IOM uint32_t D0FIFO;            /*!< (@ 0x00000018) FIFO Port Register                                         */
23879 
23880             struct
23881             {
23882                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
23883             } D0FIFO_b;
23884         };
23885 
23886         struct
23887         {
23888             union
23889             {
23890                 __IOM uint16_t D0FIFOL;  /*!< (@ 0x00000018) FIFO Port Register                                         */
23891                 __IOM uint8_t  D0FIFOLL; /*!< (@ 0x00000018) FIFO Port Register                                         */
23892             };
23893 
23894             union
23895             {
23896                 union
23897                 {
23898                     __IOM uint16_t D0FIFOH;           /*!< (@ 0x0000001A) FIFO Port Register                                         */
23899 
23900                     struct
23901                     {
23902                         __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
23903                     } D0FIFOH_b;
23904                 };
23905 
23906                 struct
23907                 {
23908                     __IM uint8_t RESERVED5;
23909 
23910                     union
23911                     {
23912                         __IOM uint8_t D0FIFOHH;         /*!< (@ 0x0000001B) FIFO Port Register                                         */
23913 
23914                         struct
23915                         {
23916                             __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
23917                         } D0FIFOHH_b;
23918                     };
23919                 };
23920             };
23921         };
23922     };
23923 
23924     union
23925     {
23926         union
23927         {
23928             __IOM uint32_t D1FIFO;            /*!< (@ 0x0000001C) FIFO Port Register                                         */
23929 
23930             struct
23931             {
23932                 __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port                                                         */
23933             } D1FIFO_b;
23934         };
23935 
23936         struct
23937         {
23938             union
23939             {
23940                 __IOM uint16_t D1FIFOL;  /*!< (@ 0x0000001C) FIFO Port Register                                         */
23941                 __IOM uint8_t  D1FIFOLL; /*!< (@ 0x0000001C) FIFO Port Register                                         */
23942             };
23943 
23944             union
23945             {
23946                 union
23947                 {
23948                     __IOM uint16_t D1FIFOH;           /*!< (@ 0x0000001E) FIFO Port Register                                         */
23949 
23950                     struct
23951                     {
23952                         __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port                                                         */
23953                     } D1FIFOH_b;
23954                 };
23955 
23956                 struct
23957                 {
23958                     __IM uint8_t RESERVED6;
23959 
23960                     union
23961                     {
23962                         __IOM uint8_t D1FIFOHH;         /*!< (@ 0x0000001F) FIFO Port Register                                         */
23963 
23964                         struct
23965                         {
23966                             __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port                                                          */
23967                         } D1FIFOHH_b;
23968                     };
23969                 };
23970             };
23971         };
23972     };
23973 
23974     union
23975     {
23976         __IOM uint16_t CFIFOSEL;        /*!< (@ 0x00000020) CFIFO Port Select Register                                 */
23977 
23978         struct
23979         {
23980             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
23981             uint16_t               : 1;
23982             __IOM uint16_t ISEL    : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected                    */
23983             uint16_t               : 2;
23984             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
23985             uint16_t               : 1;
23986             __IOM uint16_t MBW     : 2; /*!< [11..10] CFIFO Port Access Bit Width                                      */
23987             uint16_t               : 2;
23988             __IOM uint16_t REW     : 1; /*!< [14..14] Buffer Pointer Rewind                                            */
23989             __IOM uint16_t RCNT    : 1; /*!< [15..15] Read Count Mode                                                  */
23990         } CFIFOSEL_b;
23991     };
23992 
23993     union
23994     {
23995         __IOM uint16_t CFIFOCTR;       /*!< (@ 0x00000022) FIFO Port Control Register                                 */
23996 
23997         struct
23998         {
23999             __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
24000             uint16_t            : 1;
24001             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
24002             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
24003             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
24004         } CFIFOCTR_b;
24005     };
24006     __IM uint32_t RESERVED7;
24007 
24008     union
24009     {
24010         __IOM uint16_t D0FIFOSEL;       /*!< (@ 0x00000028) D0FIFO Port Select Register                                */
24011 
24012         struct
24013         {
24014             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
24015             uint16_t               : 4;
24016             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
24017             uint16_t               : 1;
24018             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
24019             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA Request Enable                                               */
24020             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe
24021                                          *   Data is Read                                                              */
24022             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
24023             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
24024         } D0FIFOSEL_b;
24025     };
24026 
24027     union
24028     {
24029         __IOM uint16_t D0FIFOCTR;      /*!< (@ 0x0000002A) FIFO Port Control Register                                 */
24030 
24031         struct
24032         {
24033             __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
24034             uint16_t            : 1;
24035             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
24036             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
24037             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
24038         } D0FIFOCTR_b;
24039     };
24040 
24041     union
24042     {
24043         __IOM uint16_t D1FIFOSEL;       /*!< (@ 0x0000002C) D1FIFO Port Select Register                                */
24044 
24045         struct
24046         {
24047             __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification                                */
24048             uint16_t               : 4;
24049             __IOM uint16_t BIGEND  : 1; /*!< [8..8] FIFO Port Endian Control                                           */
24050             uint16_t               : 1;
24051             __IOM uint16_t MBW     : 2; /*!< [11..10] FIFO Port Access Bit Width                                       */
24052             __IOM uint16_t DREQE   : 1; /*!< [12..12] DMA Request Enable                                               */
24053             __IOM uint16_t DCLRM   : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe
24054                                          *   Data is Read                                                              */
24055             __IOM uint16_t REW  : 1;    /*!< [14..14] Buffer Pointer Rewind                                            */
24056             __IOM uint16_t RCNT : 1;    /*!< [15..15] Read Count Mode                                                  */
24057         } D1FIFOSEL_b;
24058     };
24059 
24060     union
24061     {
24062         __IOM uint16_t D1FIFOCTR;      /*!< (@ 0x0000002E) FIFO Port Control Register                                 */
24063 
24064         struct
24065         {
24066             __IM uint16_t DTLN  : 12;  /*!< [11..0] Receive Data Length                                               */
24067             uint16_t            : 1;
24068             __IM uint16_t  FRDY : 1;   /*!< [13..13] FIFO Port Ready                                                  */
24069             __IOM uint16_t BCLR : 1;   /*!< [14..14] CPU Buffer Clear                                                 */
24070             __IOM uint16_t BVAL : 1;   /*!< [15..15] Buffer Memory Valid Flag                                         */
24071         } D1FIFOCTR_b;
24072     };
24073 
24074     union
24075     {
24076         __IOM uint16_t INTENB0;        /*!< (@ 0x00000030) Interrupt Enable Register 0                                */
24077 
24078         struct
24079         {
24080             uint16_t             : 8;
24081             __IOM uint16_t BRDYE : 1;  /*!< [8..8] Buffer Ready Interrupt Enable                                      */
24082             __IOM uint16_t NRDYE : 1;  /*!< [9..9] Buffer Not Ready Response Interrupt Enable                         */
24083             __IOM uint16_t BEMPE : 1;  /*!< [10..10] Buffer Empty Interrupt Enable                                    */
24084             __IOM uint16_t CTRE  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Enable               */
24085             __IOM uint16_t DVSE  : 1;  /*!< [12..12] Device State Transition Interrupt Enable                         */
24086             __IOM uint16_t SOFE  : 1;  /*!< [13..13] Frame Number Update Interrupt Enable                             */
24087             __IOM uint16_t RSME  : 1;  /*!< [14..14] Resume Interrupt Enable                                          */
24088             __IOM uint16_t VBSE  : 1;  /*!< [15..15] VBUS Interrupt Enable                                            */
24089         } INTENB0_b;
24090     };
24091 
24092     union
24093     {
24094         __IOM uint16_t INTENB1;           /*!< (@ 0x00000032) Interrupt Enable Register 1                                */
24095 
24096         struct
24097         {
24098             __IOM uint16_t PDDETINTE : 1; /*!< [0..0] PDDETINT Detection Interrupt Enable                                */
24099             uint16_t                 : 15;
24100         } INTENB1_b;
24101     };
24102     __IM uint16_t RESERVED8;
24103 
24104     union
24105     {
24106         __IOM uint16_t BRDYENB;            /*!< (@ 0x00000036) BRDY Interrupt Enable Register                             */
24107 
24108         struct
24109         {
24110             __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe                                */
24111             uint16_t                 : 6;
24112         } BRDYENB_b;
24113     };
24114 
24115     union
24116     {
24117         __IOM uint16_t NRDYENB;            /*!< (@ 0x00000038) NRDY Interrupt Enable Register                             */
24118 
24119         struct
24120         {
24121             __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe                                */
24122             uint16_t                 : 6;
24123         } NRDYENB_b;
24124     };
24125 
24126     union
24127     {
24128         __IOM uint16_t BEMPENB;            /*!< (@ 0x0000003A) BEMP Interrupt Enable Register                             */
24129 
24130         struct
24131         {
24132             __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe                                */
24133             uint16_t                 : 6;
24134         } BEMPENB_b;
24135     };
24136 
24137     union
24138     {
24139         __IOM uint16_t SOFCFG;         /*!< (@ 0x0000003C) SOF Pin Configuration Register                             */
24140 
24141         struct
24142         {
24143             uint16_t               : 4;
24144             __IM uint16_t  EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status                                   */
24145             __IOM uint16_t INTL    : 1; /*!< [5..5] Interrupt Output Sense Select                                      */
24146             __IOM uint16_t BRDYM   : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing                             */
24147             uint16_t               : 9;
24148         } SOFCFG_b;
24149     };
24150     __IM uint16_t RESERVED9;
24151 
24152     union
24153     {
24154         __IOM uint16_t INTSTS0;        /*!< (@ 0x00000040) Interrupt Status Register 0                                */
24155 
24156         struct
24157         {
24158             __IM uint16_t  CTSQ  : 3;  /*!< [2..0] Control Transfer Stage                                             */
24159             __IOM uint16_t VALID : 1;  /*!< [3..3] USB Request Reception                                              */
24160             __IM uint16_t  DVSQ  : 3;  /*!< [6..4] Device State                                                       */
24161             __IM uint16_t  VBSTS : 1;  /*!< [7..7] VBUS Input Status                                                  */
24162             __IM uint16_t  BRDY  : 1;  /*!< [8..8] BRDY Interrupt Status                                              */
24163             __IM uint16_t  NRDY  : 1;  /*!< [9..9] NRDY Interrupt Status                                              */
24164             __IM uint16_t  BEMP  : 1;  /*!< [10..10] BEMP Interrupt Status                                            */
24165             __IOM uint16_t CTRT  : 1;  /*!< [11..11] Control Transfer Stage Transition Interrupt Status               */
24166             __IOM uint16_t DVST  : 1;  /*!< [12..12] Device State Transition Interrupt Status                         */
24167             __IOM uint16_t SOFR  : 1;  /*!< [13..13] Frame Number Update Interrupt Status                             */
24168             __IOM uint16_t RESM  : 1;  /*!< [14..14] Resume Interrupt Status                                          */
24169             __IOM uint16_t VBINT : 1;  /*!< [15..15] VBUS Change Detect Interrupt Status                              */
24170         } INTSTS0_b;
24171     };
24172 
24173     union
24174     {
24175         __IOM uint16_t INTSTS1;          /*!< (@ 0x00000042) Interrupt Status Register 1                                */
24176 
24177         struct
24178         {
24179             __IOM uint16_t PDDETINT : 1; /*!< [0..0] PDDET Detection Interrupt Status                                   */
24180             uint16_t                : 15;
24181         } INTSTS1_b;
24182     };
24183     __IM uint16_t RESERVED10;
24184 
24185     union
24186     {
24187         __IOM uint16_t BRDYSTS;           /*!< (@ 0x00000046) BRDY Interrupt Status Register                             */
24188 
24189         struct
24190         {
24191             __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe                                */
24192             uint16_t                : 6;
24193         } BRDYSTS_b;
24194     };
24195 
24196     union
24197     {
24198         __IOM uint16_t NRDYSTS;           /*!< (@ 0x00000048) NRDY Interrupt Status Register                             */
24199 
24200         struct
24201         {
24202             __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe                                */
24203             uint16_t                : 6;
24204         } NRDYSTS_b;
24205     };
24206 
24207     union
24208     {
24209         __IOM uint16_t BEMPSTS;           /*!< (@ 0x0000004A) BEMP Interrupt Status Register                             */
24210 
24211         struct
24212         {
24213             __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe                                */
24214             uint16_t                : 6;
24215         } BEMPSTS_b;
24216     };
24217 
24218     union
24219     {
24220         __IOM uint16_t FRMNUM;         /*!< (@ 0x0000004C) Frame Number Register                                      */
24221 
24222         struct
24223         {
24224             __IM uint16_t FRNM  : 11;  /*!< [10..0] Frame Number                                                      */
24225             uint16_t            : 3;
24226             __IOM uint16_t CRCE : 1;   /*!< [14..14] CRC Error Detection Status                                       */
24227             __IOM uint16_t OVRN : 1;   /*!< [15..15] Overrun/Underrun Detection Status                                */
24228         } FRMNUM_b;
24229     };
24230 
24231     union
24232     {
24233         __IM uint16_t UFRMNUM;         /*!< (@ 0x0000004E) Frame Number Register                                      */
24234 
24235         struct
24236         {
24237             __IM uint16_t UFRNM : 3;   /*!< [2..0] Microframe Number                                                  */
24238             uint16_t            : 13;
24239         } UFRMNUM_b;
24240     };
24241 
24242     union
24243     {
24244         __IM uint16_t USBADDR;         /*!< (@ 0x00000050) USB Address Register                                       */
24245 
24246         struct
24247         {
24248             __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address                                                        */
24249             uint16_t              : 9;
24250         } USBADDR_b;
24251     };
24252     __IM uint16_t RESERVED11;
24253 
24254     union
24255     {
24256         __IM uint16_t USBREQ;                /*!< (@ 0x00000054) USB Request Type Register                                  */
24257 
24258         struct
24259         {
24260             __IM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request Type                                                       */
24261             __IM uint16_t BREQUEST      : 8; /*!< [15..8] Request                                                           */
24262         } USBREQ_b;
24263     };
24264 
24265     union
24266     {
24267         __IM uint16_t USBVAL;          /*!< (@ 0x00000056) USB Request Value Register                                 */
24268 
24269         struct
24270         {
24271             __IM uint16_t WVALUE : 16; /*!< [15..0] Value                                                             */
24272         } USBVAL_b;
24273     };
24274 
24275     union
24276     {
24277         __IM uint16_t USBINDX;         /*!< (@ 0x00000058) USB Request Index Register                                 */
24278 
24279         struct
24280         {
24281             __IM uint16_t WINDEX : 16; /*!< [15..0] Index                                                             */
24282         } USBINDX_b;
24283     };
24284 
24285     union
24286     {
24287         __IM uint16_t USBLENG;          /*!< (@ 0x0000005A) USB Request Length Register                                */
24288 
24289         struct
24290         {
24291             __IM uint16_t WLENGTH : 16; /*!< [15..0] Length                                                            */
24292         } USBLENG_b;
24293     };
24294 
24295     union
24296     {
24297         __IOM uint16_t DCPCFG;         /*!< (@ 0x0000005C) DCP Configuration Register                                 */
24298 
24299         struct
24300         {
24301             uint16_t              : 7;
24302             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Disabling PIPE at the End of Transfer                              */
24303             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
24304             uint16_t              : 7;
24305         } DCPCFG_b;
24306     };
24307 
24308     union
24309     {
24310         __IOM uint16_t DCPMAXP;        /*!< (@ 0x0000005E) DCP Maximum Packet Size Register                           */
24311 
24312         struct
24313         {
24314             __IOM uint16_t MXPS : 7;   /*!< [6..0] Maximum Packet Size                                                */
24315             uint16_t            : 9;
24316         } DCPMAXP_b;
24317     };
24318 
24319     union
24320     {
24321         __IOM uint16_t DCPCTR;         /*!< (@ 0x00000060) DCP Control Register                                       */
24322 
24323         struct
24324         {
24325             __IOM uint16_t PID   : 2;  /*!< [1..0] Response PID                                                       */
24326             __IOM uint16_t CCPL  : 1;  /*!< [2..2] Control Transfer End Enable                                        */
24327             uint16_t             : 2;
24328             __IM uint16_t  PBUSY : 1;  /*!< [5..5] PIPE Busy                                                          */
24329             __IM uint16_t  SQMON : 1;  /*!< [6..6] Sequence Toggle Bit Monitor                                        */
24330             __IOM uint16_t SQSET : 1;  /*!< [7..7] Toggle Bit Set                                                     */
24331             __IOM uint16_t SQCLR : 1;  /*!< [8..8] Toggle Bit Clear                                                   */
24332             uint16_t             : 6;
24333             __IM uint16_t BSTS   : 1;  /*!< [15..15] Buffer Status                                                    */
24334         } DCPCTR_b;
24335     };
24336     __IM uint16_t RESERVED12;
24337 
24338     union
24339     {
24340         __IOM uint16_t PIPESEL;         /*!< (@ 0x00000064) Pipe Window Select Register                                */
24341 
24342         struct
24343         {
24344             __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select                                                 */
24345             uint16_t               : 12;
24346         } PIPESEL_b;
24347     };
24348     __IM uint16_t RESERVED13;
24349 
24350     union
24351     {
24352         __IOM uint16_t PIPECFG;        /*!< (@ 0x00000068) Pipe Configuration Register                                */
24353 
24354         struct
24355         {
24356             __IOM uint16_t EPNUM  : 4; /*!< [3..0] Endpoint Number                                                    */
24357             __IOM uint16_t DIR    : 1; /*!< [4..4] Transfer Direction                                                 */
24358             uint16_t              : 2;
24359             __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disable at the End of Transfer                                */
24360             __IOM uint16_t CNTMD  : 1; /*!< [8..8] Continuous Transfer Mode                                           */
24361             __IOM uint16_t DBLB   : 1; /*!< [9..9] Double Buffer Mode                                                 */
24362             __IOM uint16_t BFRE   : 1; /*!< [10..10] BRDY Interrupt Operation Specification                           */
24363             uint16_t              : 3;
24364             __IOM uint16_t TYPE   : 2; /*!< [15..14] Transfer Type                                                    */
24365         } PIPECFG_b;
24366     };
24367 
24368     union
24369     {
24370         __IOM uint16_t PIPEBUF;         /*!< (@ 0x0000006A) Pipe Buffer Specification Register                         */
24371 
24372         struct
24373         {
24374             __IOM uint16_t BUFNMB  : 8; /*!< [7..0] Buffer number                                                      */
24375             uint16_t               : 2;
24376             __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer size                                                      */
24377             uint16_t               : 1;
24378         } PIPEBUF_b;
24379     };
24380 
24381     union
24382     {
24383         __IOM uint16_t PIPEMAXP;       /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register                          */
24384 
24385         struct
24386         {
24387             __IOM uint16_t MXPS : 11;  /*!< [10..0] Maximum Packet Size                                               */
24388             uint16_t            : 5;
24389         } PIPEMAXP_b;
24390     };
24391 
24392     union
24393     {
24394         __IOM uint16_t PIPEPERI;       /*!< (@ 0x0000006E) Pipe Timing Control Register                               */
24395 
24396         struct
24397         {
24398             __IOM uint16_t IITV : 3;   /*!< [2..0] Interval Error Detection Spacing                                   */
24399             uint16_t            : 9;
24400             __IOM uint16_t IFIS : 1;   /*!< [12..12] Isochronous IN Buffer Flush                                      */
24401             uint16_t            : 3;
24402         } PIPEPERI_b;
24403     };
24404 
24405     union
24406     {
24407         __IOM uint16_t PIPE_CTR[9];    /*!< (@ 0x00000070) PIPE[0..8] Control Register                                */
24408 
24409         struct
24410         {
24411             __IOM uint16_t PID    : 2; /*!< [1..0] Response PID                                                       */
24412             uint16_t              : 3;
24413             __IM uint16_t  PBUSY  : 1; /*!< [5..5] PIPE Busy                                                          */
24414             __IM uint16_t  SQMON  : 1; /*!< [6..6] Toggle Bit Confirm                                                 */
24415             __IOM uint16_t SQSET  : 1; /*!< [7..7] Toggle Bit Set                                                     */
24416             __IOM uint16_t SQCLR  : 1; /*!< [8..8] Toggle Bit Clear                                                   */
24417             __IOM uint16_t ACLRM  : 1; /*!< [9..9] Auto Buffer Clear Mode                                             */
24418             __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode                                               */
24419             uint16_t              : 3;
24420             __IM uint16_t INBUFM  : 1; /*!< [14..14] Transfer Buffer Monitor                                          */
24421             __IM uint16_t BSTS    : 1; /*!< [15..15] Buffer Status                                                    */
24422         } PIPE_CTR_b[9];
24423     };
24424     __IM uint16_t             RESERVED14;
24425     __IM uint32_t             RESERVED15[3];
24426     __IOM R_USBF_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) PIPEn Transaction Counter Registers (n=1-5)                */
24427     __IM uint32_t             RESERVED16[23];
24428     __IM uint16_t             RESERVED17;
24429 
24430     union
24431     {
24432         __IOM uint16_t LPSTS;          /*!< (@ 0x00000102) Low Power Status Register                                  */
24433 
24434         struct
24435         {
24436             uint16_t             : 14;
24437             __IOM uint16_t SUSPM : 1;  /*!< [14..14] UTMI SuspendM Control                                            */
24438             uint16_t             : 1;
24439         } LPSTS_b;
24440     };
24441     __IM uint32_t         RESERVED18[191];
24442     __IOM R_USBF_CHa_Type CHa[2];      /*!< (@ 0x00000400) Next Register Set                                          */
24443     __IM uint32_t         RESERVED19[96];
24444     __IOM R_USBF_CHb_Type CHb[2];      /*!< (@ 0x00000600) Skip Register Set                                          */
24445     __IM uint32_t         RESERVED20[48];
24446 
24447     union
24448     {
24449         __IOM uint32_t DCTRL;          /*!< (@ 0x00000700) DMA Control Register                                       */
24450 
24451         struct
24452         {
24453             __IOM uint32_t PR   : 1;   /*!< [0..0] Priority                                                           */
24454             uint32_t            : 15;
24455             __IOM uint32_t LDPR : 4;   /*!< [19..16] Link Descriptor PROT                                             */
24456             uint32_t            : 4;
24457             __IOM uint32_t LWPR : 4;   /*!< [27..24] Link WriteBack PROT                                              */
24458             uint32_t            : 4;
24459         } DCTRL_b;
24460     };
24461 
24462     union
24463     {
24464         __IOM uint32_t DSCITVL;        /*!< (@ 0x00000704) Descriptor Interval Register                               */
24465 
24466         struct
24467         {
24468             uint32_t             : 8;
24469             __IOM uint32_t DITVL : 8;  /*!< [15..8] Descriptor Interval                                               */
24470             uint32_t             : 16;
24471         } DSCITVL_b;
24472     };
24473     __IM uint32_t RESERVED21[2];
24474 
24475     union
24476     {
24477         __IM uint32_t DSTAT_EN;        /*!< (@ 0x00000710) DMA Status EN Register                                     */
24478 
24479         struct
24480         {
24481             __IM uint32_t EN0 : 1;     /*!< [0..0] Channel 0 EN                                                       */
24482             __IM uint32_t EN1 : 1;     /*!< [1..1] Channel 1 EN                                                       */
24483             uint32_t          : 30;
24484         } DSTAT_EN_b;
24485     };
24486 
24487     union
24488     {
24489         __IM uint32_t DSTAT_ER;        /*!< (@ 0x00000714) DMA Status ER Register                                     */
24490 
24491         struct
24492         {
24493             __IM uint32_t ER0 : 1;     /*!< [0..0] Channel 0 ER                                                       */
24494             __IM uint32_t ER1 : 1;     /*!< [1..1] Channel 1 ER                                                       */
24495             uint32_t          : 30;
24496         } DSTAT_ER_b;
24497     };
24498 
24499     union
24500     {
24501         __IM uint32_t DSTAT_END;       /*!< (@ 0x00000718) DMA Status END Register                                    */
24502 
24503         struct
24504         {
24505             __IM uint32_t END0 : 1;    /*!< [0..0] Channel 0 END                                                      */
24506             __IM uint32_t END1 : 1;    /*!< [1..1] Channel 1 END                                                      */
24507             uint32_t           : 30;
24508         } DSTAT_END_b;
24509     };
24510 
24511     union
24512     {
24513         __IM uint32_t DSTAT_TC;        /*!< (@ 0x0000071C) DMA Status TC Register                                     */
24514 
24515         struct
24516         {
24517             __IM uint32_t TC0 : 1;     /*!< [0..0] Channel 0 TC                                                       */
24518             __IM uint32_t TC1 : 1;     /*!< [1..1] Channel 1 TC                                                       */
24519             uint32_t          : 30;
24520         } DSTAT_TC_b;
24521     };
24522 
24523     union
24524     {
24525         __IM uint32_t DSTAT_SUS;       /*!< (@ 0x00000720) DMA Status SUS Register                                    */
24526 
24527         struct
24528         {
24529             __IM uint32_t SUS0 : 1;    /*!< [0..0] Channel 0 SUS                                                      */
24530             __IM uint32_t SUS1 : 1;    /*!< [1..1] Channel 1 SUS                                                      */
24531             uint32_t           : 30;
24532         } DSTAT_SUS_b;
24533     };
24534 } R_USBF_Type;                         /*!< Size = 1828 (0x724)                                                       */
24535 
24536 /* =========================================================================================================================== */
24537 /* ================                                           R_BSC                                           ================ */
24538 /* =========================================================================================================================== */
24539 
24540 /**
24541  * @brief Bus State Controller (R_BSC)
24542  */
24543 
24544 typedef struct                         /*!< (@ 0x80210000) R_BSC Structure                                            */
24545 {
24546     union
24547     {
24548         __IOM uint32_t CMNCR;          /*!< (@ 0x00000000) Common Control Register                                    */
24549 
24550         struct
24551         {
24552             uint32_t             : 9;
24553             __IOM uint32_t DPRTY : 2;  /*!< [10..9] DMA Burst Transfer Priority                                       */
24554             uint32_t             : 13;
24555             __IOM uint32_t AL    : 1;  /*!< [24..24] Acknowledge Level                                                */
24556             uint32_t             : 3;
24557             __IOM uint32_t TL    : 1;  /*!< [28..28] Transfer End Level                                               */
24558             uint32_t             : 3;
24559         } CMNCR_b;
24560     };
24561 
24562     union
24563     {
24564         __IOM uint32_t CSnBCR[6];      /*!< (@ 0x00000004) CS[0..5] Space Bus Control Register                        */
24565 
24566         struct
24567         {
24568             uint32_t             : 9;
24569             __IOM uint32_t BSZ   : 2;  /*!< [10..9] Data Bus Width Specification                                      */
24570             uint32_t             : 1;
24571             __IOM uint32_t TYPE  : 3;  /*!< [14..12] Memory Connected to a Space                                      */
24572             uint32_t             : 1;
24573             __IOM uint32_t IWRRS : 3;  /*!< [18..16] Idle State Insertion between Read-Read Cycles in the
24574                                         *   Same CS Space                                                             */
24575             __IOM uint32_t IWRRD : 3;  /*!< [21..19] Idle State Insertion between Read-Read Cycles in Different
24576                                         *   CS Spaces                                                                 */
24577             __IOM uint32_t IWRWS : 3;  /*!< [24..22] Idle State Insertion between Read-Write Cycles in the
24578                                         *   Same CS Space                                                             */
24579             __IOM uint32_t IWRWD : 3;  /*!< [27..25] Idle State Insertion between Read-Write Cycles in Different
24580                                         *   CS Spaces                                                                 */
24581             __IOM uint32_t IWW : 3;    /*!< [30..28] Idle Cycles between Write-Read Cycles and Write-Write
24582                                         *   Cycles                                                                    */
24583             uint32_t : 1;
24584         } CSnBCR_b[6];
24585     };
24586     __IM uint32_t RESERVED[3];
24587 
24588     union
24589     {
24590         union
24591         {
24592             __IOM uint32_t CS0WCR_0;    /*!< (@ 0x00000028) CS0 Space Wait Control Register for Normal Space,
24593                                          *                  SRAM with Byte Selection                                   */
24594 
24595             struct
24596             {
24597                 __IOM uint32_t HW : 2;  /*!< [1..0] Delay States from RD#, WEn# Negation to Address, CS0#
24598                                          *   Negation                                                                  */
24599                 uint32_t          : 4;
24600                 __IOM uint32_t WM : 1;  /*!< [6..6] External Wait Mask Specification                                   */
24601                 __IOM uint32_t WR : 4;  /*!< [10..7] Number of Access Waits                                            */
24602                 __IOM uint32_t SW : 2;  /*!< [12..11] Number of Delay Cycles from Address, CSn# Assertion
24603                                          *   to RD#, WEn# Assertion                                                    */
24604                 uint32_t           : 7;
24605                 __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
24606                 uint32_t           : 11;
24607             } CS0WCR_0_b;
24608         };
24609 
24610         union
24611         {
24612             __IOM uint32_t CS0WCR_1;   /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM
24613                                         *                  with Clocked Asynchronous                                  */
24614 
24615             struct
24616             {
24617                 uint32_t           : 6;
24618                 __IOM uint32_t WM  : 1; /*!< [6..6] External Wait Mask Specification                                   */
24619                 __IOM uint32_t W   : 4; /*!< [10..7] Number of Access Waits                                            */
24620                 uint32_t           : 5;
24621                 __IOM uint32_t BW  : 2; /*!< [17..16] Number of Waits during Burst Access                              */
24622                 uint32_t           : 2;
24623                 __IOM uint32_t BST : 2; /*!< [21..20] Burst Count Specification                                        */
24624                 uint32_t           : 10;
24625             } CS0WCR_1_b;
24626         };
24627 
24628         union
24629         {
24630             __IOM uint32_t CS0WCR_2;   /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM
24631                                         *                  with Clocked Synchronous                                   */
24632 
24633             struct
24634             {
24635                 uint32_t          : 6;
24636                 __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification                                   */
24637                 __IOM uint32_t W  : 4; /*!< [10..7] Number of Access Waits                                            */
24638                 uint32_t          : 5;
24639                 __IOM uint32_t BW : 2; /*!< [17..16] Number of Burst Wait Cycles                                      */
24640                 uint32_t          : 14;
24641             } CS0WCR_2_b;
24642         };
24643     };
24644     __IM uint32_t RESERVED1;
24645 
24646     union
24647     {
24648         union
24649         {
24650             __IOM uint32_t CS2WCR_0;   /*!< (@ 0x00000030) CS2 Space Wait Control Register for Normal Space,
24651                                         *                  SRAM with Byte Selection                                   */
24652 
24653             struct
24654             {
24655                 uint32_t           : 6;
24656                 __IOM uint32_t WM  : 1; /*!< [6..6] External Wait Mask Specification                                   */
24657                 __IOM uint32_t WR  : 4; /*!< [10..7] Number of Access Waits                                            */
24658                 uint32_t           : 9;
24659                 __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
24660                 uint32_t           : 11;
24661             } CS2WCR_0_b;
24662         };
24663 
24664         union
24665         {
24666             __IOM uint32_t CS2WCR_1;   /*!< (@ 0x00000030) CS2 Space Wait Control Register for SDRAM                  */
24667 
24668             struct
24669             {
24670                 uint32_t            : 7;
24671                 __IOM uint32_t A2CL : 2; /*!< [8..7] CAS Latency for Area 2                                             */
24672                 uint32_t            : 23;
24673             } CS2WCR_1_b;
24674         };
24675     };
24676 
24677     union
24678     {
24679         union
24680         {
24681             __IOM uint32_t CS3WCR_0;   /*!< (@ 0x00000034) CS3 Space Wait Control Register for Normal Space,
24682                                         *                  SRAM with Byte Selection                                   */
24683 
24684             struct
24685             {
24686                 uint32_t           : 6;
24687                 __IOM uint32_t WM  : 1; /*!< [6..6] External Wait Mask Specification                                   */
24688                 __IOM uint32_t WR  : 4; /*!< [10..7] Number of Access Waits                                            */
24689                 uint32_t           : 9;
24690                 __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select                      */
24691                 uint32_t           : 11;
24692             } CS3WCR_0_b;
24693         };
24694 
24695         union
24696         {
24697             __IOM uint32_t CS3WCR_1;      /*!< (@ 0x00000034) CS3 Space Wait Control Register for SDRAM                  */
24698 
24699             struct
24700             {
24701                 __IOM uint32_t WTRC : 2;  /*!< [1..0] Number of Idle States from REF Command/Self-Refresh Release
24702                                            *   to ACTV/REF/MRS Command                                                   */
24703                 uint32_t             : 1;
24704                 __IOM uint32_t TRWL  : 2; /*!< [4..3] Number of Auto-Precharge Startup Wait Cycles                       */
24705                 uint32_t             : 2;
24706                 __IOM uint32_t A3CL  : 2; /*!< [8..7] CAS Latency for Area 3                                             */
24707                 uint32_t             : 1;
24708                 __IOM uint32_t WTRCD : 2; /*!< [11..10] Number of Waits between ACTV Command and READ(A)/WRIT(A)
24709                                            *   Command                                                                   */
24710                 uint32_t            : 1;
24711                 __IOM uint32_t WTRP : 2;  /*!< [14..13] Number of Auto-Precharge Completion Wait States                  */
24712                 uint32_t            : 17;
24713             } CS3WCR_1_b;
24714         };
24715     };
24716     __IM uint32_t RESERVED2;
24717 
24718     union
24719     {
24720         __IOM uint32_t CS5WCR;           /*!< (@ 0x0000003C) CS5 Space Wait Control Register for Normal Space,
24721                                           *                  SRAM with Byte Selection, and MPX-I/O                      */
24722 
24723         struct
24724         {
24725             __IOM uint32_t HW : 2;       /*!< [1..0] Delay Cycles from RD#, WEn# to Address, CS5#                       */
24726             uint32_t          : 4;
24727             __IOM uint32_t WM : 1;       /*!< [6..6] External Wait Mask Specification                                   */
24728             __IOM uint32_t WR : 4;       /*!< [10..7] Number of Read Access Waits                                       */
24729             __IOM uint32_t SW : 2;       /*!< [12..11] Number of Delay Cycles from Address, CS5# Assertion
24730                                           *   to RD#, WEn# Assertion                                                    */
24731             uint32_t                : 3;
24732             __IOM uint32_t WW       : 3; /*!< [18..16] Number of Write Access Waits                                     */
24733             uint32_t                : 1;
24734             __IOM uint32_t MPXWSBAS : 1; /*!< [20..20] MPX-I/O Interface Address Cycle Wait and SRAM with
24735                                           *   Byte Selection Byte Access Select                                         */
24736             __IOM uint32_t SZSEL : 1;    /*!< [21..21] MPX-I/O Interface Bus Width Specification                        */
24737             uint32_t             : 10;
24738         } CS5WCR_b;
24739     };
24740     __IM uint32_t RESERVED3[3];
24741 
24742     union
24743     {
24744         __IOM uint32_t SDCR;           /*!< (@ 0x0000004C) SDRAM Control Register                                     */
24745 
24746         struct
24747         {
24748             __IOM uint32_t A3COL : 2;  /*!< [1..0] Number of Bits of Column Address for Area 3                        */
24749             uint32_t             : 1;
24750             __IOM uint32_t A3ROW : 2;  /*!< [4..3] Number of Bits of Row Address for Area 3                           */
24751             uint32_t             : 3;
24752             __IOM uint32_t BACTV : 1;  /*!< [8..8] Bank Active Mode                                                   */
24753             __IOM uint32_t PDOWN : 1;  /*!< [9..9] Power-Down Mode                                                    */
24754             __IOM uint32_t RMODE : 1;  /*!< [10..10] Refresh Mode                                                     */
24755             __IOM uint32_t RFSH  : 1;  /*!< [11..11] Refresh Control                                                  */
24756             uint32_t             : 1;
24757             __IOM uint32_t DEEP  : 1;  /*!< [13..13] Deep Power-Down Mode                                             */
24758             uint32_t             : 2;
24759             __IOM uint32_t A2COL : 2;  /*!< [17..16] Number of Bits of Column Address for Area 2                      */
24760             uint32_t             : 1;
24761             __IOM uint32_t A2ROW : 2;  /*!< [20..19] Number of Bits of Row Address for Area 2                         */
24762             uint32_t             : 11;
24763         } SDCR_b;
24764     };
24765     __IOM uint32_t RTCSR;              /*!< (@ 0x00000050) Refresh Timer Control/Status Register                      */
24766     __IOM uint32_t RTCNT;              /*!< (@ 0x00000054) Refresh Timer Counter                                      */
24767     __IOM uint32_t RTCOR;              /*!< (@ 0x00000058) Refresh Time Constant Register                             */
24768     __IM uint32_t  RESERVED4;
24769 
24770     union
24771     {
24772         __IOM uint32_t TOSCOR[6];       /*!< (@ 0x00000060) Timeout Cycle Constant Register [0..5]                     */
24773 
24774         struct
24775         {
24776             __IOM uint32_t TOCNUM : 16; /*!< [15..0] Timeout Cycle Number                                              */
24777             uint32_t              : 16;
24778         } TOSCOR_b[6];
24779     };
24780     __IM uint32_t RESERVED5[2];
24781 
24782     union
24783     {
24784         __IOM uint32_t TOSTR;            /*!< (@ 0x00000080) Timeout Status Register                                    */
24785 
24786         struct
24787         {
24788             __IOM uint32_t CS0TOSTF : 1; /*!< [0..0] CS0 Space Timeout Status Flag                                      */
24789             uint32_t                : 1;
24790             __IOM uint32_t CS2TOSTF : 1; /*!< [2..2] CS2 Space Timeout Status Flag                                      */
24791             __IOM uint32_t CS3TOSTF : 1; /*!< [3..3] CS3 Space Timeout Status Flag                                      */
24792             uint32_t                : 1;
24793             __IOM uint32_t CS5TOSTF : 1; /*!< [5..5] CS5 Space Timeout Status Flag                                      */
24794             uint32_t                : 26;
24795         } TOSTR_b;
24796     };
24797 
24798     union
24799     {
24800         __IOM uint32_t TOENR;           /*!< (@ 0x00000084) Timeout Enable Register                                    */
24801 
24802         struct
24803         {
24804             __IOM uint32_t CS0TOEN : 1; /*!< [0..0] CS0 Space Timeout Detection Enable                                 */
24805             uint32_t               : 1;
24806             __IOM uint32_t CS2TOEN : 1; /*!< [2..2] CS2 Space Timeout Detection Enable                                 */
24807             __IOM uint32_t CS3TOEN : 1; /*!< [3..3] CS3 Space Timeout Detection Enable                                 */
24808             uint32_t               : 1;
24809             __IOM uint32_t CS5TOEN : 1; /*!< [5..5] CS5 Space Timeout Detection Enable                                 */
24810             uint32_t               : 26;
24811         } TOENR_b;
24812     };
24813 } R_BSC_Type;                           /*!< Size = 136 (0x88)                                                         */
24814 
24815 /* =========================================================================================================================== */
24816 /* ================                                          R_XSPI0                                          ================ */
24817 /* =========================================================================================================================== */
24818 
24819 /**
24820  * @brief xSPI (R_XSPI0)
24821  */
24822 
24823 typedef struct                         /*!< (@ 0x80220000) R_XSPI0 Structure                                          */
24824 {
24825     union
24826     {
24827         __IOM uint32_t WRAPCFG;        /*!< (@ 0x00000000) xSPI Wrapper Configuration Register                        */
24828 
24829         struct
24830         {
24831             uint32_t                : 8;
24832             __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0                                               */
24833             uint32_t                : 11;
24834             __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1                                              */
24835             uint32_t                : 3;
24836         } WRAPCFG_b;
24837     };
24838 
24839     union
24840     {
24841         __IOM uint32_t COMCFG;         /*!< (@ 0x00000004) xSPI Common Configuration Register                         */
24842 
24843         struct
24844         {
24845             uint32_t               : 16;
24846             __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension                                */
24847             __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension                                 */
24848             uint32_t               : 14;
24849         } COMCFG_b;
24850     };
24851 
24852     union
24853     {
24854         __IOM uint32_t BMCFG;           /*!< (@ 0x00000008) xSPI Bridge Map Configuration Register                     */
24855 
24856         struct
24857         {
24858             __IOM uint32_t WRMD    : 1; /*!< [0..0] AHB Write Response mode                                            */
24859             uint32_t               : 6;
24860             __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode                                      */
24861             __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size                                                 */
24862             __IOM uint32_t PREEN   : 1; /*!< [16..16] Prefetch enable                                                  */
24863             uint32_t               : 15;
24864         } BMCFG_b;
24865     };
24866     __IM uint32_t          RESERVED;
24867     __IOM R_XSPI0_CSa_Type CSa[2];     /*!< (@ 0x00000010) xSPI Command Map Configuration Register [0..1]             */
24868     __IM uint32_t          RESERVED1[8];
24869 
24870     union
24871     {
24872         __IOM uint32_t LIOCFGCS[2];        /*!< (@ 0x00000050) xSPI Link I/O Configuration Register CSn                   */
24873 
24874         struct
24875         {
24876             __IOM uint32_t PRTMD     : 10; /*!< [9..0] Protocol mode                                                      */
24877             __IOM uint32_t LATEMD    : 1;  /*!< [10..10] Latency mode                                                     */
24878             __IOM uint32_t WRMSKMD   : 1;  /*!< [11..11] Write mask mode                                                  */
24879             uint32_t                 : 4;
24880             __IOM uint32_t CSMIN     : 4;  /*!< [19..16] CS minimum idle term                                             */
24881             __IOM uint32_t CSASTEX   : 1;  /*!< [20..20] CS asserting extension                                           */
24882             __IOM uint32_t CSNEGEX   : 1;  /*!< [21..21] CS negating extension                                            */
24883             __IOM uint32_t SDRDRV    : 1;  /*!< [22..22] SDR driving timing                                               */
24884             __IOM uint32_t SDRSMPMD  : 1;  /*!< [23..23] SDR Sampling mode                                                */
24885             __IOM uint32_t SDRSMPSFT : 4;  /*!< [27..24] SDR Sampling window shift                                        */
24886             __IOM uint32_t DDRSMPEX  : 4;  /*!< [31..28] DDR sampling window extend                                       */
24887         } LIOCFGCS_b[2];
24888     };
24889     __IM uint32_t RESERVED2[2];
24890 
24891     union
24892     {
24893         __IOM uint32_t BMCTL0;         /*!< (@ 0x00000060) xSPI Bridge Map Control Register 0                         */
24894 
24895         struct
24896         {
24897             __IOM uint32_t CS0ACC : 2; /*!< [1..0] AHB channel to slave0 memory area access enable                    */
24898             __IOM uint32_t CS1ACC : 2; /*!< [3..2] AHB channel to slave1 memory area access enable                    */
24899             uint32_t              : 28;
24900         } BMCTL0_b;
24901     };
24902 
24903     union
24904     {
24905         __OM uint32_t BMCTL1;          /*!< (@ 0x00000064) xSPI Bridge Map Control Register 1                         */
24906 
24907         struct
24908         {
24909             uint32_t              : 8;
24910             __OM uint32_t MWRPUSH : 1; /*!< [8..8] Memory Write Data Push                                             */
24911             uint32_t              : 1;
24912             __OM uint32_t PBUFCLR : 1; /*!< [10..10] Prefetch Buffer clear                                            */
24913             uint32_t              : 21;
24914         } BMCTL1_b;
24915     };
24916 
24917     union
24918     {
24919         __IOM uint32_t CMCTL;             /*!< (@ 0x00000068) xSPI Command Map Control Register                          */
24920 
24921         struct
24922         {
24923             __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code                                                */
24924             __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code                                                */
24925             __IOM uint32_t XIPEN     : 1; /*!< [16..16] XiP mode enable                                                  */
24926             uint32_t                 : 15;
24927         } CMCTL_b;
24928     };
24929 
24930     union
24931     {
24932         __IOM uint32_t CSSCTL;          /*!< (@ 0x0000006C) xSPI CS Size Control Register                              */
24933 
24934         struct
24935         {
24936             __IOM uint32_t CS0SIZE : 6; /*!< [5..0] CS0 (slave0) size                                                  */
24937             uint32_t               : 2;
24938             __IOM uint32_t CS1SIZE : 6; /*!< [13..8] CS1 (slave1) size                                                 */
24939             uint32_t               : 18;
24940         } CSSCTL_b;
24941     };
24942 
24943     union
24944     {
24945         __IOM uint32_t CDCTL0;         /*!< (@ 0x00000070) xSPI Command Manual Control Register 0                     */
24946 
24947         struct
24948         {
24949             __IOM uint32_t TRREQ  : 1; /*!< [0..0] Transaction request                                                */
24950             __IOM uint32_t PERMD  : 1; /*!< [1..1] Periodic mode                                                      */
24951             uint32_t              : 1;
24952             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
24953             __IOM uint32_t TRNUM  : 2; /*!< [5..4] Transaction number                                                 */
24954             uint32_t              : 10;
24955             __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval                                    */
24956             uint32_t              : 3;
24957             __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat                                      */
24958             uint32_t              : 4;
24959         } CDCTL0_b;
24960     };
24961 
24962     union
24963     {
24964         __IOM uint32_t CDCTL1;          /*!< (@ 0x00000074) xSPI Command Manual Control Register 1                     */
24965 
24966         struct
24967         {
24968             __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value                               */
24969         } CDCTL1_b;
24970     };
24971 
24972     union
24973     {
24974         __IOM uint32_t CDCTL2;          /*!< (@ 0x00000078) xSPI Command Manual Control Register 2                     */
24975 
24976         struct
24977         {
24978             __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value                                 */
24979         } CDCTL2_b;
24980     };
24981     __IM uint32_t          RESERVED3;
24982     __IOM R_XSPI0_BUF_Type BUF[4];      /*!< (@ 0x00000080) xSPI Command Manual Buf [0..3]                             */
24983     __IM uint32_t          RESERVED4[16];
24984 
24985     union
24986     {
24987         __IOM uint32_t LPCTL0;         /*!< (@ 0x00000100) xSPI Link Pattern Control Register 0                       */
24988 
24989         struct
24990         {
24991             __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request                                                    */
24992             uint32_t              : 2;
24993             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
24994             __IOM uint32_t XDPIN  : 2; /*!< [5..4] XiP Disable pattern pin                                            */
24995             uint32_t              : 10;
24996             __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length                             */
24997             uint32_t              : 2;
24998             __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value                              */
24999             __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length                             */
25000             uint32_t              : 2;
25001             __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value                              */
25002         } LPCTL0_b;
25003     };
25004 
25005     union
25006     {
25007         __IOM uint32_t LPCTL1;         /*!< (@ 0x00000104) xSPI Link Pattern Control Register 1                       */
25008 
25009         struct
25010         {
25011             __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request                                                    */
25012             uint32_t              : 1;
25013             __IOM uint32_t CSSEL  : 1; /*!< [3..3] Chip select                                                        */
25014             __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat                                               */
25015             uint32_t              : 2;
25016             __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width                                               */
25017             uint32_t              : 1;
25018             __IOM uint32_t RSTSU  : 3; /*!< [14..12] Reset pattern data output setup time                             */
25019             uint32_t              : 17;
25020         } LPCTL1_b;
25021     };
25022 
25023     union
25024     {
25025         __IOM uint32_t LIOCTL;         /*!< (@ 0x00000108) xSPI Link I/O Control Register                             */
25026 
25027         struct
25028         {
25029             __IOM uint32_t WPCS0  : 1; /*!< [0..0] WP drive for slave0                                                */
25030             __IOM uint32_t WPCS1  : 1; /*!< [1..1] WP drive for slave1                                                */
25031             uint32_t              : 14;
25032             __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave0                                           */
25033             __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave1                                           */
25034             uint32_t              : 14;
25035         } LIOCTL_b;
25036     };
25037     __IM uint32_t          RESERVED5[9];
25038     __IOM R_XSPI0_CSb_Type CSb[2];     /*!< (@ 0x00000130) xSPI Command Calibration Control register [0..1]           */
25039     __IM uint32_t          RESERVED6[4];
25040 
25041     union
25042     {
25043         __IM uint32_t VERSTT;          /*!< (@ 0x00000180) xSPI Version Register                                      */
25044 
25045         struct
25046         {
25047             __IM uint32_t VER : 32;    /*!< [31..0] Version                                                           */
25048         } VERSTT_b;
25049     };
25050 
25051     union
25052     {
25053         __IM uint32_t COMSTT;          /*!< (@ 0x00000184) xSPI Common Status Register                                */
25054 
25055         struct
25056         {
25057             __IM uint32_t MEMACC  : 1; /*!< [0..0] Memory access ongoing                                              */
25058             uint32_t              : 3;
25059             __IM uint32_t PBUFNE  : 1; /*!< [4..4] Prefetch Buffer Not Empty                                          */
25060             uint32_t              : 1;
25061             __IM uint32_t WRBUFNE : 1; /*!< [6..6] Write Buffer Not Empty                                             */
25062             uint32_t              : 9;
25063             __IM uint32_t ECSCS0  : 1; /*!< [16..16] ECS monitor for slave0                                           */
25064             __IM uint32_t INTCS0  : 1; /*!< [17..17] INT monitor for slave0                                           */
25065             __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0                                          */
25066             uint32_t              : 1;
25067             __IM uint32_t ECSCS1  : 1; /*!< [20..20] ECS monitor for slave1                                           */
25068             __IM uint32_t INTCS1  : 1; /*!< [21..21] INT monitor for slave1                                           */
25069             __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1                                          */
25070             uint32_t              : 9;
25071         } COMSTT_b;
25072     };
25073 
25074     union
25075     {
25076         __IM uint32_t CASTTCS[2];      /*!< (@ 0x00000188) xSPI Calibration Status Register CSn                       */
25077 
25078         struct
25079         {
25080             __IM uint32_t CASUC : 32;  /*!< [31..0] Calibration Success                                               */
25081         } CASTTCS_b[2];
25082     };
25083 
25084     union
25085     {
25086         __IM uint32_t INTS;              /*!< (@ 0x00000190) xSPI Interrupt Status Register                             */
25087 
25088         struct
25089         {
25090             __IM uint32_t CMDCMP    : 1; /*!< [0..0] Command Completed                                                  */
25091             __IM uint32_t PATCMP    : 1; /*!< [1..1] Pattern Completed                                                  */
25092             __IM uint32_t INICMP    : 1; /*!< [2..2] Initial Sequence Completed                                         */
25093             __IM uint32_t PERTO     : 1; /*!< [3..3] Periodic transaction timeout                                       */
25094             __IM uint32_t DSTOCS0   : 1; /*!< [4..4] DS timeout for slave0                                              */
25095             __IM uint32_t DSTOCS1   : 1; /*!< [5..5] DS timeout for slave1                                              */
25096             uint32_t                : 2;
25097             __IM uint32_t ECSCS0    : 1; /*!< [8..8] ECC error detection for slave0                                     */
25098             __IM uint32_t ECSCS1    : 1; /*!< [9..9] ECC error detection for slave1                                     */
25099             uint32_t                : 2;
25100             __IM uint32_t INTCS0    : 1; /*!< [12..12] Interrupt detection for slave0                                   */
25101             __IM uint32_t INTCS1    : 1; /*!< [13..13] Interrupt detection for slave1                                   */
25102             uint32_t                : 2;
25103             __IM uint32_t BRGOF     : 1; /*!< [16..16] Bridge Buffer overflow                                           */
25104             uint32_t                : 1;
25105             __IM uint32_t BRGUF     : 1; /*!< [18..18] Bridge Buffer underflow                                          */
25106             uint32_t                : 1;
25107             __IM uint32_t BUSERR    : 1; /*!< [20..20] AHB bus error                                                    */
25108             uint32_t                : 7;
25109             __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0                                    */
25110             __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1                                    */
25111             __IM uint32_t CASUCCS0  : 1; /*!< [30..30] Calibration success for slave0                                   */
25112             __IM uint32_t CASUCCS1  : 1; /*!< [31..31] Calibration success for slave1                                   */
25113         } INTS_b;
25114     };
25115 
25116     union
25117     {
25118         __OM uint32_t INTC;               /*!< (@ 0x00000194) xSPI Interrupt Clear Register                              */
25119 
25120         struct
25121         {
25122             __OM uint32_t CMDCMPC    : 1; /*!< [0..0] Command Completed interrupt clear                                  */
25123             __OM uint32_t PATCMPC    : 1; /*!< [1..1] Pattern Completed interrupt clear                                  */
25124             __OM uint32_t INICMPC    : 1; /*!< [2..2] Initial Sequence Completed interrupt clear                         */
25125             __OM uint32_t PERTOC     : 1; /*!< [3..3] Periodic transaction timeout interrupt clear                       */
25126             __OM uint32_t DSTOCS0C   : 1; /*!< [4..4] DS timeout for slave0 interrupt clear                              */
25127             __OM uint32_t DSTOCS1C   : 1; /*!< [5..5] DS timeout for slave1 interrupt clear                              */
25128             uint32_t                 : 2;
25129             __OM uint32_t ECSCS0C    : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear                     */
25130             __OM uint32_t ECSCS1C    : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear                     */
25131             uint32_t                 : 2;
25132             __OM uint32_t INTCS0C    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear                   */
25133             __OM uint32_t INTCS1C    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear                   */
25134             uint32_t                 : 2;
25135             __OM uint32_t BRGOFC     : 1; /*!< [16..16] Bridge Buffer overflow interrupt clear                           */
25136             uint32_t                 : 1;
25137             __OM uint32_t BRGUFC     : 1; /*!< [18..18] Bridge Buffer underflow interrupt clear                          */
25138             uint32_t                 : 1;
25139             __OM uint32_t BUSERRC    : 1; /*!< [20..20] AHB bus error interrupt clear                                    */
25140             uint32_t                 : 7;
25141             __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear                    */
25142             __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear                    */
25143             __OM uint32_t CASUCCS0C  : 1; /*!< [30..30] Calibration success for slave0 interrupt clear                   */
25144             __OM uint32_t CASUCCS1C  : 1; /*!< [31..31] Calibration success for slave1 interrupt clear                   */
25145         } INTC_b;
25146     };
25147 
25148     union
25149     {
25150         __IOM uint32_t INTE;               /*!< (@ 0x00000198) xSPI Interrupt Enable Register                             */
25151 
25152         struct
25153         {
25154             __IOM uint32_t CMDCMPE    : 1; /*!< [0..0] Command Completed interrupt enable                                 */
25155             __IOM uint32_t PATCMPE    : 1; /*!< [1..1] Pattern Completed interrupt enable                                 */
25156             __IOM uint32_t INICMPE    : 1; /*!< [2..2] Initial Sequence Completed interrupt enable                        */
25157             __IOM uint32_t PERTOE     : 1; /*!< [3..3] Periodic transaction timeout interrupt enable                      */
25158             __IOM uint32_t DSTOCS0E   : 1; /*!< [4..4] DS timeout for slave0 interrupt enable                             */
25159             __IOM uint32_t DSTOCS1E   : 1; /*!< [5..5] DS timeout for slave1 interrupt enable                             */
25160             uint32_t                  : 2;
25161             __IOM uint32_t ECSCS0E    : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable                    */
25162             __IOM uint32_t ECSCS1E    : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable                    */
25163             uint32_t                  : 2;
25164             __IOM uint32_t INTCS0E    : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable                  */
25165             __IOM uint32_t INTCS1E    : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable                  */
25166             uint32_t                  : 2;
25167             __IOM uint32_t BRGOFE     : 1; /*!< [16..16] Bridge Buffer overflow interrupt enable                          */
25168             uint32_t                  : 1;
25169             __IOM uint32_t BRGUFE     : 1; /*!< [18..18] Bridge Buffer underflow interrupt enable                         */
25170             uint32_t                  : 1;
25171             __IOM uint32_t BUSERRE    : 1; /*!< [20..20] AHB bus error interrupt enable                                   */
25172             uint32_t                  : 7;
25173             __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable                   */
25174             __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable                   */
25175             __IOM uint32_t CASUCCS0E  : 1; /*!< [30..30] Calibration success for slave0 interrupt enable                  */
25176             __IOM uint32_t CASUCCS1E  : 1; /*!< [31..31] Calibration success for slave1 interrupt enable                  */
25177         } INTE_b;
25178     };
25179 } R_XSPI0_Type;                            /*!< Size = 412 (0x19c)                                                        */
25180 
25181 /* =========================================================================================================================== */
25182 /* ================                                         R_MBXSEM                                          ================ */
25183 /* =========================================================================================================================== */
25184 
25185 /**
25186  * @brief Mailbox and Semaphore (R_MBXSEM)
25187  */
25188 
25189 typedef struct                         /*!< (@ 0x80240000) R_MBXSEM Structure                                         */
25190 {
25191     union
25192     {
25193         __IOM uint32_t SEM[8];         /*!< (@ 0x00000000) Semaphore Register [0..7]                                  */
25194 
25195         struct
25196         {
25197             __IOM uint32_t SEM : 1;    /*!< [0..0] Semaphore bit                                                      */
25198             uint32_t           : 31;
25199         } SEM_b[8];
25200     };
25201 
25202     union
25203     {
25204         __IOM uint32_t SEMRCEN;          /*!< (@ 0x00000020) Semaphore Read Clear Enable Register                       */
25205 
25206         struct
25207         {
25208             __IOM uint32_t SEMRCEN0 : 1; /*!< [0..0] SEMRCEN0                                                           */
25209             __IOM uint32_t SEMRCEN1 : 1; /*!< [1..1] SEMRCEN1                                                           */
25210             __IOM uint32_t SEMRCEN2 : 1; /*!< [2..2] SEMRCEN2                                                           */
25211             __IOM uint32_t SEMRCEN3 : 1; /*!< [3..3] SEMRCEN3                                                           */
25212             __IOM uint32_t SEMRCEN4 : 1; /*!< [4..4] SEMRCEN4                                                           */
25213             __IOM uint32_t SEMRCEN5 : 1; /*!< [5..5] SEMRCEN5                                                           */
25214             __IOM uint32_t SEMRCEN6 : 1; /*!< [6..6] SEMRCEN6                                                           */
25215             __IOM uint32_t SEMRCEN7 : 1; /*!< [7..7] SEMRCEN7                                                           */
25216             uint32_t                : 24;
25217         } SEMRCEN_b;
25218     };
25219     __IM uint32_t RESERVED[7];
25220 
25221     union
25222     {
25223         __IM uint32_t MBXH2C[4];       /*!< (@ 0x00000040) Host to CR52 Mailbox Register [0..3]                       */
25224 
25225         struct
25226         {
25227             __IM uint32_t MBX : 32;    /*!< [31..0] MBX                                                               */
25228         } MBXH2C_b[4];
25229     };
25230 
25231     union
25232     {
25233         __IM uint32_t MBXISETH2C;        /*!< (@ 0x00000050) Host to CR52 Mailbox Interrupt Set Register                */
25234 
25235         struct
25236         {
25237             __IM uint32_t MBX_INT0S : 1; /*!< [0..0] Generates or indicates MBX_INT0 interrupt of mailbox
25238                                           *   from external host CPU to internal Cortex-R52.                            */
25239             __IM uint32_t MBX_INT1S : 1; /*!< [1..1] Generates or indicates MBX_INT1 interrupt of mailbox
25240                                           *   from external host CPU to internal Cortex-R52.                            */
25241             __IM uint32_t MBX_INT2S : 1; /*!< [2..2] Generates or indicates MBX_INT2 interrupt of mailbox
25242                                           *   from external host CPU to internal Cortex-R52.                            */
25243             __IM uint32_t MBX_INT3S : 1; /*!< [3..3] Generates or indicates MBX_INT3 interrupt of mailbox
25244                                           *   from external host CPU to internal Cortex-R52.                            */
25245             uint32_t : 28;
25246         } MBXISETH2C_b;
25247     };
25248 
25249     union
25250     {
25251         __IOM uint32_t MBXICLRH2C;        /*!< (@ 0x00000054) Host to CR52 Mailbox Interrupt Clear Register              */
25252 
25253         struct
25254         {
25255             __IOM uint32_t MBX_INT0C : 1; /*!< [0..0] Clears or indicates MBX_INT0 interrupt of mailbox from
25256                                            *   external host CPU to internal Cortex-R52.                                 */
25257             __IOM uint32_t MBX_INT1C : 1; /*!< [1..1] Clears or indicates MBX_INT1 interrupt of mailbox from
25258                                            *   external host CPU to internal Cortex-R52.                                 */
25259             __IOM uint32_t MBX_INT2C : 1; /*!< [2..2] Clears or indicates MBX_INT2 interrupt of mailbox from
25260                                            *   external host CPU to internal Cortex-R52.                                 */
25261             __IOM uint32_t MBX_INT3C : 1; /*!< [3..3] Clears or indicates MBX_INT3 interrupt of mailbox from
25262                                            *   external host CPU to internal Cortex-R52.                                 */
25263             uint32_t : 28;
25264         } MBXICLRH2C_b;
25265     };
25266     __IM uint32_t RESERVED1[10];
25267 
25268     union
25269     {
25270         __IOM uint32_t MBXC2H[4];      /*!< (@ 0x00000080) CR52 to Host Mailbox Register [0..3]                       */
25271 
25272         struct
25273         {
25274             __IOM uint32_t MBX : 32;   /*!< [31..0] MBX                                                               */
25275         } MBXC2H_b[4];
25276     };
25277 
25278     union
25279     {
25280         __IOM uint32_t MBXISETC2H;         /*!< (@ 0x00000090) CR52 to Host Mailbox Interrupt Set Register                */
25281 
25282         struct
25283         {
25284             __IOM uint32_t MBX_HINT0S : 1; /*!< [0..0] Generates or indicates MBX_HINT0 interrupt of mailbox
25285                                             *   from internal Cortex-R52 to external host CPU.                            */
25286             __IOM uint32_t MBX_HINT1S : 1; /*!< [1..1] Generates or indicates MBX_HINT1 interrupt of mailbox
25287                                             *   from internal Cortex-R52 to external host CPU.                            */
25288             __IOM uint32_t MBX_HINT2S : 1; /*!< [2..2] Generates or indicates MBX_HINT2 interrupt of mailbox
25289                                             *   from internal Cortex-R52 to external host CPU.                            */
25290             __IOM uint32_t MBX_HINT3S : 1; /*!< [3..3] Generates or indicates MBX_HINT3 interrupt of mailbox
25291                                             *   from internal Cortex-R52 to external host CPU.                            */
25292             uint32_t : 28;
25293         } MBXISETC2H_b;
25294     };
25295 
25296     union
25297     {
25298         __IM uint32_t MBXICLRC2H;         /*!< (@ 0x00000094) CR52 to Host Mailbox Interrupt Clear Register              */
25299 
25300         struct
25301         {
25302             __IM uint32_t MBX_HINT0C : 1; /*!< [0..0] Clears or indicates MBX_HINT0 interrupt of mailbox from
25303                                            *   internal Cortex-R52 to external host CPU.                                 */
25304             __IM uint32_t MBX_HINT1C : 1; /*!< [1..1] Clears or indicates MBX_HINT1 interrupt of mailbox from
25305                                            *   internal Cortex-R52 to external host CPU.                                 */
25306             __IM uint32_t MBX_HINT2C : 1; /*!< [2..2] Clears or indicates MBX_HINT2 interrupt of mailbox from
25307                                            *   internal Cortex-R52 to external host CPU.                                 */
25308             __IM uint32_t MBX_HINT3C : 1; /*!< [3..3] Clears or indicates MBX_HINT3 interrupt of mailbox from
25309                                            *   internal Cortex-R52 to external host CPU.                                 */
25310             uint32_t : 28;
25311         } MBXICLRC2H_b;
25312     };
25313 } R_MBXSEM_Type;                          /*!< Size = 152 (0x98)                                                         */
25314 
25315 /* =========================================================================================================================== */
25316 /* ================                                         R_SHOSTIF                                         ================ */
25317 /* =========================================================================================================================== */
25318 
25319 /**
25320  * @brief Serial Host Interface (R_SHOSTIF)
25321  */
25322 
25323 typedef struct                         /*!< (@ 0x80241000) R_SHOSTIF Structure                                        */
25324 {
25325     union
25326     {
25327         __IOM uint32_t CTRLR0;         /*!< (@ 0x00000000) Control Register 0                                         */
25328 
25329         struct
25330         {
25331             uint32_t             : 8;
25332             __IOM uint32_t SCPH  : 1;  /*!< [8..8] Serial Clock Phase                                                 */
25333             __IOM uint32_t SCPOL : 1;  /*!< [9..9] Serial Clock Polarity                                              */
25334             uint32_t             : 22;
25335         } CTRLR0_b;
25336     };
25337     __IM uint32_t RESERVED;
25338 
25339     union
25340     {
25341         __IOM uint32_t ENR;            /*!< (@ 0x00000008) Enable Register                                            */
25342 
25343         struct
25344         {
25345             __IOM uint32_t ENABLE : 1; /*!< [0..0] SHOSTIF Enable                                                     */
25346             uint32_t              : 31;
25347         } ENR_b;
25348     };
25349     __IM uint32_t RESERVED1[2];
25350 
25351     union
25352     {
25353         __IOM uint32_t RXFBTR;         /*!< (@ 0x00000014) Receive FIFO Burst Threshold Register                      */
25354 
25355         struct
25356         {
25357             __IOM uint32_t RXFBTL : 6; /*!< [5..0] Receive FIFO Burst Threshold                                       */
25358             uint32_t              : 26;
25359         } RXFBTR_b;
25360     };
25361 
25362     union
25363     {
25364         __IOM uint32_t TXFTLR;         /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register                     */
25365 
25366         struct
25367         {
25368             __IOM uint32_t TFT : 6;    /*!< [5..0] Transmit FIFO Threshold                                            */
25369             uint32_t           : 26;
25370         } TXFTLR_b;
25371     };
25372 
25373     union
25374     {
25375         __IOM uint32_t RXFTLR;         /*!< (@ 0x0000001C) Receive FIFO Threshold Level Register                      */
25376 
25377         struct
25378         {
25379             __IOM uint32_t RFT : 6;    /*!< [5..0] Receive FIFO Threshold                                             */
25380             uint32_t           : 26;
25381         } RXFTLR_b;
25382     };
25383     __IM uint32_t RESERVED2[2];
25384 
25385     union
25386     {
25387         __IM uint32_t SR;              /*!< (@ 0x00000028) Status Register                                            */
25388 
25389         struct
25390         {
25391             __IM uint32_t BUSY : 1;    /*!< [0..0] Busy Flag                                                          */
25392             uint32_t           : 31;
25393         } SR_b;
25394     };
25395 
25396     union
25397     {
25398         __IOM uint32_t IMR;            /*!< (@ 0x0000002C) Interrupt Mask Register                                    */
25399 
25400         struct
25401         {
25402             __IOM uint32_t TXEIM  : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask                                 */
25403             uint32_t              : 2;
25404             __IOM uint32_t RXOIM  : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask                               */
25405             __IOM uint32_t RXFIM  : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask                                   */
25406             uint32_t              : 2;
25407             __IOM uint32_t TXUIM  : 1; /*!< [7..7] Transmit FIFO Underflow Mask                                       */
25408             __IOM uint32_t AHBEM  : 1; /*!< [8..8] AHB Error Interrupt Mask                                           */
25409             __IOM uint32_t SPIMEM : 1; /*!< [9..9] SPI Master Error Interrupt Mask                                    */
25410             uint32_t              : 22;
25411         } IMR_b;
25412     };
25413 
25414     union
25415     {
25416         __IM uint32_t ISR;             /*!< (@ 0x00000030) Interrupt Status Register                                  */
25417 
25418         struct
25419         {
25420             __IM uint32_t TXEIS  : 1;  /*!< [0..0] Transmit FIFO Empty Interrupt Status                               */
25421             uint32_t             : 2;
25422             __IM uint32_t RXOIS  : 1;  /*!< [3..3] Receive FIFO Overflow Interrupt Status                             */
25423             __IM uint32_t RXFIS  : 1;  /*!< [4..4] Receive FIFO Full Interrupt Status                                 */
25424             uint32_t             : 2;
25425             __IM uint32_t TXUIS  : 1;  /*!< [7..7] Transmit FIFO Underflow Status                                     */
25426             __IM uint32_t AHBES  : 1;  /*!< [8..8] AHB Error Interrupt Status                                         */
25427             __IM uint32_t SPIMES : 1;  /*!< [9..9] SPI Master Error Interrupt Status                                  */
25428             uint32_t             : 22;
25429         } ISR_b;
25430     };
25431 
25432     union
25433     {
25434         __IM uint32_t RISR;            /*!< (@ 0x00000034) Raw Interrupt Status Register                              */
25435 
25436         struct
25437         {
25438             __IM uint32_t TXEIR  : 1;  /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status                           */
25439             uint32_t             : 2;
25440             __IM uint32_t RXOIR  : 1;  /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status                         */
25441             __IM uint32_t RXFIR  : 1;  /*!< [4..4] Receive FIFO Full Raw Interrupt Status                             */
25442             uint32_t             : 2;
25443             __IM uint32_t TXUIR  : 1;  /*!< [7..7] Transmit FIFO Underflow Raw Interrupt Status                       */
25444             __IM uint32_t AHBER  : 1;  /*!< [8..8] AHB Error Raw Interrupt Status                                     */
25445             __IM uint32_t SPIMER : 1;  /*!< [9..9] SPI Master Error Raw Interrupt Status                              */
25446             uint32_t             : 22;
25447         } RISR_b;
25448     };
25449 
25450     union
25451     {
25452         __IM uint32_t TXUICR;          /*!< (@ 0x00000038) Transmit FIFO Underflow Interrupt Clear Register           */
25453 
25454         struct
25455         {
25456             __IM uint32_t TXUICR : 1;  /*!< [0..0] Clear Transmit FIFO Underflow Interrupt                            */
25457             uint32_t             : 31;
25458         } TXUICR_b;
25459     };
25460 
25461     union
25462     {
25463         __IM uint32_t RXOICR;          /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register             */
25464 
25465         struct
25466         {
25467             __IM uint32_t RXOICR : 1;  /*!< [0..0] Clear Receive FIFO Overflow Interrupt                              */
25468             uint32_t             : 31;
25469         } RXOICR_b;
25470     };
25471 
25472     union
25473     {
25474         __IM uint32_t SPIMECR;         /*!< (@ 0x00000040) SPI Master Interrupt Clear Register                        */
25475 
25476         struct
25477         {
25478             __IM uint32_t SPIMECR : 1; /*!< [0..0] Clear SPI Master Error interrupt                                   */
25479             uint32_t              : 31;
25480         } SPIMECR_b;
25481     };
25482 
25483     union
25484     {
25485         __IM uint32_t AHBECR;          /*!< (@ 0x00000044) AHB Error Clear Register                                   */
25486 
25487         struct
25488         {
25489             __IM uint32_t AHBECR : 1;  /*!< [0..0] Clear AHB Error Interrupt                                          */
25490             uint32_t             : 31;
25491         } AHBECR_b;
25492     };
25493 
25494     union
25495     {
25496         __IM uint32_t ICR;             /*!< (@ 0x00000048) Interrupt Clear Register                                   */
25497 
25498         struct
25499         {
25500             __IM uint32_t ICR : 1;     /*!< [0..0] Clear Interrupts                                                   */
25501             uint32_t          : 31;
25502         } ICR_b;
25503     };
25504 } R_SHOSTIF_Type;                      /*!< Size = 76 (0x4c)                                                          */
25505 
25506 /* =========================================================================================================================== */
25507 /* ================                                         R_PHOSTIF                                         ================ */
25508 /* =========================================================================================================================== */
25509 
25510 /**
25511  * @brief Parallel Host Interface (R_PHOSTIF)
25512  */
25513 
25514 typedef struct                          /*!< (@ 0x80242000) R_PHOSTIF Structure                                        */
25515 {
25516     union
25517     {
25518         __IOM uint16_t HIFBCC;          /*!< (@ 0x00000000) HOSTIF Bus Control Register                                */
25519 
25520         struct
25521         {
25522             __IOM uint16_t RBUFON0 : 1; /*!< [0..0] RBUFON0                                                            */
25523             __IOM uint16_t RBUFON1 : 1; /*!< [1..1] RBUFON1                                                            */
25524             __IOM uint16_t RBUFON2 : 1; /*!< [2..2] RBUFON2                                                            */
25525             __IOM uint16_t RBUFON3 : 1; /*!< [3..3] RBUFON3                                                            */
25526             __IOM uint16_t RBUFON4 : 1; /*!< [4..4] RBUFON4                                                            */
25527             __IOM uint16_t RBUFON5 : 1; /*!< [5..5] RBUFON5                                                            */
25528             uint16_t               : 2;
25529             __IOM uint16_t RBUFONX : 1; /*!< [8..8] RBUFONX                                                            */
25530             uint16_t               : 3;
25531             __IOM uint16_t BSTON   : 1; /*!< [12..12] BSTON                                                            */
25532             __IOM uint16_t WRPON   : 1; /*!< [13..13] WRPON                                                            */
25533             uint16_t               : 2;
25534         } HIFBCC_b;
25535     };
25536     __IM uint16_t RESERVED;
25537 
25538     union
25539     {
25540         __IOM uint16_t HIFBTC;         /*!< (@ 0x00000004) HOSTIF Timing Control Register                             */
25541 
25542         struct
25543         {
25544             __IOM uint16_t WRSTD : 3;  /*!< [2..0] Specifies the timing for detecting the start of write
25545                                         *   operation by the HWRSTB# signal.                                          */
25546             uint16_t             : 1;
25547             __IOM uint16_t RDSTD : 2;  /*!< [5..4] Specifies the timing for detecting the start of read
25548                                         *   operation by the HRD# signal.                                             */
25549             uint16_t             : 2;
25550             __IOM uint16_t PASTD : 3;  /*!< [10..8] PASTD                                                             */
25551             uint16_t             : 1;
25552             __IOM uint16_t RDDTS : 2;  /*!< [13..12] RDDTS                                                            */
25553             uint16_t             : 2;
25554         } HIFBTC_b;
25555     };
25556     __IM uint16_t RESERVED1;
25557 
25558     union
25559     {
25560         __IOM uint16_t HIFPRC;          /*!< (@ 0x00000008) HOSTIF Page ROM Control Register                           */
25561 
25562         struct
25563         {
25564             __IOM uint16_t PAGEON0 : 1; /*!< [0..0] PAGEON0                                                            */
25565             __IOM uint16_t PAGEON1 : 1; /*!< [1..1] PAGEON1                                                            */
25566             __IOM uint16_t PAGEON2 : 1; /*!< [2..2] PAGEON2                                                            */
25567             __IOM uint16_t PAGEON3 : 1; /*!< [3..3] PAGEON3                                                            */
25568             __IOM uint16_t PAGEON4 : 1; /*!< [4..4] PAGEON4                                                            */
25569             __IOM uint16_t PAGEON5 : 1; /*!< [5..5] PAGEON5                                                            */
25570             uint16_t               : 2;
25571             __IOM uint16_t PAGEONX : 1; /*!< [8..8] PAGEONX                                                            */
25572             uint16_t               : 3;
25573             __IOM uint16_t PAGESZ  : 1; /*!< [12..12] PAGESZ                                                           */
25574             uint16_t               : 3;
25575         } HIFPRC_b;
25576     };
25577     __IM uint16_t RESERVED2;
25578 
25579     union
25580     {
25581         __IOM uint16_t HIFIRC;         /*!< (@ 0x0000000C) HOSTIF Interrupt Request Control Register                  */
25582 
25583         struct
25584         {
25585             __IOM uint16_t ERRRSP : 1; /*!< [0..0] This bit is set to 1 on reception of an error response
25586                                         *   from internal slave modules.                                              */
25587             uint16_t : 15;
25588         } HIFIRC_b;
25589     };
25590     __IM uint16_t RESERVED3;
25591 
25592     union
25593     {
25594         __IM uint32_t HIFECR0;          /*!< (@ 0x00000010) HOSTIF Error Source Register 0                             */
25595 
25596         struct
25597         {
25598             __IM uint32_t ERRADDR : 32; /*!< [31..0] ERRADDR                                                           */
25599         } HIFECR0_b;
25600     };
25601 
25602     union
25603     {
25604         __IM uint16_t HIFECR1;         /*!< (@ 0x00000014) HOSTIF Error Source Register 1                             */
25605 
25606         struct
25607         {
25608             __IM uint16_t ERRSZ : 3;   /*!< [2..0] ERRSZ                                                              */
25609             __IM uint16_t ERRWR : 1;   /*!< [3..3] ERRWR                                                              */
25610             uint16_t            : 12;
25611         } HIFECR1_b;
25612     };
25613     __IM uint16_t RESERVED4;
25614     __IM uint32_t RESERVED5[2];
25615 
25616     union
25617     {
25618         __IOM uint16_t HIFMON1;        /*!< (@ 0x00000020) HOSTIF Monitor Register 1                                  */
25619 
25620         struct
25621         {
25622             __IOM uint16_t HIFRDY : 1; /*!< [0..0] HIFRDY                                                             */
25623             __IM uint16_t  BUSSEL : 1; /*!< [1..1] BUSSEL                                                             */
25624             uint16_t              : 1;
25625             __IM uint16_t HIFSYNC : 1; /*!< [3..3] HIFSYNC                                                            */
25626             uint16_t              : 12;
25627         } HIFMON1_b;
25628     };
25629     __IM uint16_t RESERVED6;
25630 
25631     union
25632     {
25633         __IM uint16_t HIFMON2;         /*!< (@ 0x00000024) HOSTIF Monitor Register 2                                  */
25634 
25635         struct
25636         {
25637             __IM uint16_t HIFBCC : 1;  /*!< [0..0] HIFBCC                                                             */
25638             __IM uint16_t HIFBTC : 1;  /*!< [1..1] HIFBTC                                                             */
25639             __IM uint16_t HIFPRC : 1;  /*!< [2..2] HIFPRC                                                             */
25640             __IM uint16_t HIFIRC : 1;  /*!< [3..3] HIFIRC                                                             */
25641             __IM uint16_t HIFXAL : 1;  /*!< [4..4] HIFXAL                                                             */
25642             __IM uint16_t HIFXAH : 1;  /*!< [5..5] HIFXAH                                                             */
25643             uint16_t             : 10;
25644         } HIFMON2_b;
25645     };
25646     __IM uint16_t RESERVED7;
25647 
25648     union
25649     {
25650         __IM uint16_t HIFMON3;         /*!< (@ 0x00000028) HOSTIF Monitor Register 3                                  */
25651 
25652         struct
25653         {
25654             __IM uint16_t HIFEXT0 : 1; /*!< [0..0] HIFEXT0                                                            */
25655             __IM uint16_t HIFEXT1 : 1; /*!< [1..1] HIFEXT1                                                            */
25656             uint16_t              : 14;
25657         } HIFMON3_b;
25658     };
25659     __IM uint16_t RESERVED8;
25660     __IM uint32_t RESERVED9;
25661 
25662     union
25663     {
25664         __IOM uint16_t HIFXAL;         /*!< (@ 0x00000030) HOSTIF Specified Area Lower-limit Register                 */
25665 
25666         struct
25667         {
25668             __IOM uint16_t XADDRL : 9; /*!< [8..0] Specifies the lower-limit address of the specified area
25669                                         *   to be set in the external bus address space.                              */
25670             uint16_t : 7;
25671         } HIFXAL_b;
25672     };
25673     __IM uint16_t RESERVED10;
25674 
25675     union
25676     {
25677         __IOM uint16_t HIFXAH;         /*!< (@ 0x00000034) HOSTIF Specified Area Upper-limit Register                 */
25678 
25679         struct
25680         {
25681             __IOM uint16_t XADDRH : 9; /*!< [8..0] Specifies the upper-limit address of the specified area
25682                                         *   to be set in the external bus address space.                              */
25683             uint16_t : 7;
25684         } HIFXAH_b;
25685     };
25686     __IM uint16_t RESERVED11;
25687     __IM uint32_t RESERVED12[18];
25688 
25689     union
25690     {
25691         __IOM uint16_t HIFEXT0;        /*!< (@ 0x00000080) HOSTIF Synchronous Burst Transfer Control Register
25692                                         *                  0                                                          */
25693 
25694         struct
25695         {
25696             __IOM uint16_t KESSBI : 1; /*!< [0..0] KESSBI                                                             */
25697             uint16_t              : 1;
25698             __IOM uint16_t KESDTI : 1; /*!< [2..2] KESDTI                                                             */
25699             __IOM uint16_t KESAVI : 1; /*!< [3..3] KESAVI                                                             */
25700             __IOM uint16_t KESDTO : 1; /*!< [4..4] KESDTO                                                             */
25701             __IOM uint16_t KESWTO : 1; /*!< [5..5] KESWTO                                                             */
25702             uint16_t              : 3;
25703             __IOM uint16_t CNDWEO : 1; /*!< [9..9] CNDWEO                                                             */
25704             uint16_t              : 5;
25705             __IOM uint16_t MODTRN : 1; /*!< [15..15] MODTRN                                                           */
25706         } HIFEXT0_b;
25707     };
25708     __IM uint16_t RESERVED13;
25709 
25710     union
25711     {
25712         __IOM uint16_t HIFEXT1;        /*!< (@ 0x00000084) HOSTIF Synchronous Burst Transfer Control Register
25713                                         *                  1                                                          */
25714 
25715         struct
25716         {
25717             __IOM uint16_t DLYWA : 4;  /*!< [3..0] Minimum time from the last input of the Low level on
25718                                         *   the HBS# pin to the point where write data is received.
25719                                         *   (twc)DLYWA[3:0]CNDWEO = 0CNDWEO = 0HWRSTB# = 0HWRSTB# =
25720                                         *   1HWRSTB# = 0HWRSTB# = 10x034450x134450x234450x344450x455550x566660x677770
25721                                         *   788880x899990x9101010100xA111111110xB121212120xC131313130xD141414140xE151
25722                                         *   15150xF16161616                                                           */
25723             uint16_t             : 4;
25724             __IOM uint16_t DLYRA : 4;  /*!< [11..8] Minimum time from the last input of the Low level on
25725                                         *   the HBS# pin to the point where read data can be acquired.
25726                                         *   (trc)DLYRA[3:0]CNDWEO = 0CNDWEO = 10x0450x1450x2550x3660x4770x5880x6990x7
25727                                         *   0100x811110x912120xA13130xB14140xC15150xD16160xE17170xF1818               */
25728             uint16_t : 4;
25729         } HIFEXT1_b;
25730     };
25731     __IM uint16_t RESERVED14;
25732 } R_PHOSTIF_Type;                      /*!< Size = 136 (0x88)                                                         */
25733 
25734 /* =========================================================================================================================== */
25735 /* ================                                         R_SYSC_NS                                         ================ */
25736 /* =========================================================================================================================== */
25737 
25738 /**
25739  * @brief System Control for Non-safety region (R_SYSC_NS)
25740  */
25741 
25742 typedef struct                               /*!< (@ 0x80280000) R_SYSC_NS Structure                                        */
25743 {
25744     union
25745     {
25746         __IOM uint32_t SCKCR;                /*!< (@ 0x00000000) System Clock Control Register                              */
25747 
25748         struct
25749         {
25750             __IOM uint32_t FSELXSPI0 : 3;    /*!< [2..0] Set the frequency of the clock provided to xSPI Unit
25751                                               *   0 in combination with bit 6 (DIVSELXSPI0). The combination
25752                                               *   is shown below.                                                           */
25753             uint32_t                   : 3;
25754             __IOM uint32_t DIVSELXSPI0 : 1;  /*!< [6..6] Select the base clock to generate serial clock for xSPI
25755                                               *   Unit 0                                                                    */
25756             uint32_t                 : 1;
25757             __IOM uint32_t FSELXSPI1 : 3;    /*!< [10..8] Set the frequency of the clock provided to xSPI Unit
25758                                               *   1 in combination with bit 14 (DIVSELXSPI1).                               */
25759             uint32_t                   : 3;
25760             __IOM uint32_t DIVSELXSPI1 : 1;  /*!< [14..14] Select the base clock to generate serial clock for
25761                                               *   xSPI Unit 1                                                               */
25762             uint32_t            : 1;
25763             __IOM uint32_t CKIO : 3;         /*!< [18..16] Set the frequency of the external bus clock (CKIO)
25764                                               *   and the clock supplied to BSC in combination with the DIVSELSUB
25765                                               *   in the SCKCR2 register. The combination is shown below.                   */
25766             uint32_t                 : 1;
25767             __IOM uint32_t FSELCANFD : 1;    /*!< [20..20] Select the frequency of the clock supplied to CANFD              */
25768             __IOM uint32_t PHYSEL    : 1;    /*!< [21..21] Select the Ethernet PHY reference clock output (ETHn_REFCLK,
25769                                               *   n = 0 to 2)                                                               */
25770             __IOM uint32_t CLMASEL : 1;      /*!< [22..22] Select alternative clock when main clock abnormal oscillation
25771                                               *   is detected in CLMA3                                                      */
25772             uint32_t                    : 1;
25773             __IOM uint32_t SPI0ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock
25774                                               *   is selected in SPI0                                                       */
25775             __IOM uint32_t SPI1ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock
25776                                               *   is selected in SPI1                                                       */
25777             __IOM uint32_t SPI2ASYNCSEL : 1; /*!< [26..26] Select clock frequency when asynchronous serial clock
25778                                               *   is selected in SPI2                                                       */
25779             __IOM uint32_t SCI0ASYNCSEL : 1; /*!< [27..27] Select clock frequency when asynchronous serial clock
25780                                               *   is selected in SCI0                                                       */
25781             __IOM uint32_t SCI1ASYNCSEL : 1; /*!< [28..28] Select clock frequency when asynchronous serial clock
25782                                               *   is selected in SCI1                                                       */
25783             __IOM uint32_t SCI2ASYNCSEL : 1; /*!< [29..29] Select clock frequency when asynchronous serial clock
25784                                               *   is selected in SCI2                                                       */
25785             __IOM uint32_t SCI3ASYNCSEL : 1; /*!< [30..30] Select clock frequency when asynchronous serial clock
25786                                               *   is selected in SCI3                                                       */
25787             __IOM uint32_t SCI4ASYNCSEL : 1; /*!< [31..31] Select clock frequency when asynchronous serial clock
25788                                               *   is selected in SCI4                                                       */
25789         } SCKCR_b;
25790     };
25791     __IM uint32_t RESERVED[127];
25792 
25793     union
25794     {
25795         __IOM uint32_t RSTSR0;         /*!< (@ 0x00000200) Reset Status Register 0                                    */
25796 
25797         struct
25798         {
25799             uint32_t             : 1;
25800             __IOM uint32_t TRF   : 1;  /*!< [1..1] RES# Pin Reset Detect Flag                                         */
25801             __IOM uint32_t ERRF  : 1;  /*!< [2..2] Error Reset Detect Flag                                            */
25802             __IOM uint32_t SWRSF : 1;  /*!< [3..3] System Software Reset Detect Flag                                  */
25803             __IOM uint32_t SWR0F : 1;  /*!< [4..4] CPU0 Software Reset Detect Flag                                    */
25804             uint32_t             : 27;
25805         } RSTSR0_b;
25806     };
25807     __IM uint32_t RESERVED1[15];
25808 
25809     union
25810     {
25811         __IOM uint32_t MRCTLA;         /*!< (@ 0x00000240) Module Reset Control Register A                            */
25812 
25813         struct
25814         {
25815             uint32_t                : 4;
25816             __IOM uint32_t MRCTLA04 : 1; /*!< [4..4] xSPI Unit 0 Reset Control                                          */
25817             __IOM uint32_t MRCTLA05 : 1; /*!< [5..5] xSPI Unit 1 Reset Control                                          */
25818             uint32_t                : 26;
25819         } MRCTLA_b;
25820     };
25821     __IM uint32_t RESERVED2[3];
25822 
25823     union
25824     {
25825         __IOM uint32_t MRCTLE;           /*!< (@ 0x00000250) Module Reset Control Register E                            */
25826 
25827         struct
25828         {
25829             __IOM uint32_t MRCTLE00 : 1; /*!< [0..0] GMAC (PCLKH clock domain) Reset Control                            */
25830             __IOM uint32_t MRCTLE01 : 1; /*!< [1..1] GMAC (PCLKM clock domain) Reset Control                            */
25831             __IOM uint32_t MRCTLE02 : 1; /*!< [2..2] ETHSW Reset Control                                                */
25832             __IOM uint32_t MRCTLE03 : 1; /*!< [3..3] ESC (Bus clock domain) Reset Control                               */
25833             __IOM uint32_t MRCTLE04 : 1; /*!< [4..4] ESC (IP clock domain) Reset Control                                */
25834             __IOM uint32_t MRCTLE05 : 1; /*!< [5..5] Ethernet Subsystem Register Reset Control                          */
25835             __IOM uint32_t MRCTLE06 : 1; /*!< [6..6] MII Converter Reset Control                                        */
25836             uint32_t                : 25;
25837         } MRCTLE_b;
25838     };
25839     __IM uint32_t RESERVED3[43];
25840 
25841     union
25842     {
25843         __IOM uint32_t MSTPCRA;           /*!< (@ 0x00000300) Module Stop Control Register A                             */
25844 
25845         struct
25846         {
25847             __IOM uint32_t MSTPCRA00 : 1; /*!< [0..0] BSC Module Stop                                                    */
25848             uint32_t                 : 3;
25849             __IOM uint32_t MSTPCRA04 : 1; /*!< [4..4] xSPI Unit 0 Module Stop                                            */
25850             __IOM uint32_t MSTPCRA05 : 1; /*!< [5..5] xSPI Unit 1 Module Stop                                            */
25851             uint32_t                 : 2;
25852             __IOM uint32_t MSTPCRA08 : 1; /*!< [8..8] SCI Unit 0 Module Stop                                             */
25853             __IOM uint32_t MSTPCRA09 : 1; /*!< [9..9] SCI Unit 1 Module Stop                                             */
25854             __IOM uint32_t MSTPCRA10 : 1; /*!< [10..10] SCI Unit 2 Module Stop                                           */
25855             __IOM uint32_t MSTPCRA11 : 1; /*!< [11..11] SCI Unit 3 Module Stop                                           */
25856             __IOM uint32_t MSTPCRA12 : 1; /*!< [12..12] SCI Unit 4 Module Stop                                           */
25857             uint32_t                 : 19;
25858         } MSTPCRA_b;
25859     };
25860 
25861     union
25862     {
25863         __IOM uint32_t MSTPCRB;           /*!< (@ 0x00000304) Module Stop Control Register B                             */
25864 
25865         struct
25866         {
25867             __IOM uint32_t MSTPCRB00 : 1; /*!< [0..0] IIC Unit 0 Module Stop                                             */
25868             __IOM uint32_t MSTPCRB01 : 1; /*!< [1..1] IIC Unit 1 Module Stop                                             */
25869             uint32_t                 : 2;
25870             __IOM uint32_t MSTPCRB04 : 1; /*!< [4..4] SPI Unit 0 Module Stop                                             */
25871             __IOM uint32_t MSTPCRB05 : 1; /*!< [5..5] SPI Unit 1 Module Stop                                             */
25872             __IOM uint32_t MSTPCRB06 : 1; /*!< [6..6] SPI Unit 2 Module Stop                                             */
25873             uint32_t                 : 25;
25874         } MSTPCRB_b;
25875     };
25876 
25877     union
25878     {
25879         __IOM uint32_t MSTPCRC;           /*!< (@ 0x00000308) Module Stop Control Register C                             */
25880 
25881         struct
25882         {
25883             __IOM uint32_t MSTPCRC00 : 1; /*!< [0..0] MTU3 Module Stop                                                   */
25884             __IOM uint32_t MSTPCRC01 : 1; /*!< [1..1] GPT Unit 0 Module Stop                                             */
25885             __IOM uint32_t MSTPCRC02 : 1; /*!< [2..2] GPT Unit 1 Module Stop                                             */
25886             uint32_t                 : 2;
25887             __IOM uint32_t MSTPCRC05 : 1; /*!< [5..5] TFU Module Stop                                                    */
25888             __IOM uint32_t MSTPCRC06 : 1; /*!< [6..6] ADC12 Unit 0 Module Stop                                           */
25889             __IOM uint32_t MSTPCRC07 : 1; /*!< [7..7] ADC12 Unit 1 Module Stop                                           */
25890             uint32_t                 : 24;
25891         } MSTPCRC_b;
25892     };
25893 
25894     union
25895     {
25896         __IOM uint32_t MSTPCRD;           /*!< (@ 0x0000030C) Module Stop Control Register D                             */
25897 
25898         struct
25899         {
25900             __IOM uint32_t MSTPCRD00 : 1; /*!< [0..0] DSMIF Unit 0 Module Stop                                           */
25901             __IOM uint32_t MSTPCRD01 : 1; /*!< [1..1] DSMIF Unit 1 Module Stop                                           */
25902             __IOM uint32_t MSTPCRD02 : 1; /*!< [2..2] CMT Unit 0 Module Stop                                             */
25903             __IOM uint32_t MSTPCRD03 : 1; /*!< [3..3] CMT Unit 1 Module Stop                                             */
25904             __IOM uint32_t MSTPCRD04 : 1; /*!< [4..4] CMT Unit 2 Module Stop                                             */
25905             __IOM uint32_t MSTPCRD05 : 1; /*!< [5..5] CMTW Unit 0 Module Stop                                            */
25906             __IOM uint32_t MSTPCRD06 : 1; /*!< [6..6] CMTW Unit 1 Module Stop                                            */
25907             __IOM uint32_t MSTPCRD07 : 1; /*!< [7..7] TSU Module Stop                                                    */
25908             __IOM uint32_t MSTPCRD08 : 1; /*!< [8..8] DOC Module Stop                                                    */
25909             __IOM uint32_t MSTPCRD09 : 1; /*!< [9..9] CRC Unit 0 Module Stop                                             */
25910             __IOM uint32_t MSTPCRD10 : 1; /*!< [10..10] CANFD Module Stop                                                */
25911             __IOM uint32_t MSTPCRD11 : 1; /*!< [11..11] CKIO Module Stop                                                 */
25912             uint32_t                 : 20;
25913         } MSTPCRD_b;
25914     };
25915 
25916     union
25917     {
25918         __IOM uint32_t MSTPCRE;           /*!< (@ 0x00000310) Module Stop Control Register E                             */
25919 
25920         struct
25921         {
25922             __IOM uint32_t MSTPCRE00 : 1; /*!< [0..0] GMAC Module Stop                                                   */
25923             __IOM uint32_t MSTPCRE01 : 1; /*!< [1..1] ETHSW Module Stop                                                  */
25924             __IOM uint32_t MSTPCRE02 : 1; /*!< [2..2] ESC Module Stop                                                    */
25925             __IOM uint32_t MSTPCRE03 : 1; /*!< [3..3] Ethernet Subsystem Register Module Stop                            */
25926             uint32_t                 : 4;
25927             __IOM uint32_t MSTPCRE08 : 1; /*!< [8..8] USB Module Stop                                                    */
25928             uint32_t                 : 23;
25929         } MSTPCRE_b;
25930     };
25931     __IM uint32_t RESERVED4[891];
25932 
25933     union
25934     {
25935         __IM uint32_t MD_MON;          /*!< (@ 0x00001100) Operating Mode Monitor Register                            */
25936 
25937         struct
25938         {
25939             __IM uint32_t MDDMON  : 1; /*!< [0..0] MDD status flag                                                    */
25940             uint32_t              : 7;
25941             __IM uint32_t MDP     : 1; /*!< [8..8] Package type                                                       */
25942             uint32_t              : 3;
25943             __IM uint32_t MD0MON  : 1; /*!< [12..12] MD0 pin status flag                                              */
25944             __IM uint32_t MD1MON  : 1; /*!< [13..13] MD1 pin status flag                                              */
25945             __IM uint32_t MD2MON  : 1; /*!< [14..14] MD2 pin status flag                                              */
25946             uint32_t              : 1;
25947             __IM uint32_t MDV0MON : 1; /*!< [16..16] MDV0 status flag (ETH0 domain)                                   */
25948             __IM uint32_t MDV1MON : 1; /*!< [17..17] MDV1 status flag (ETH1 domain)                                   */
25949             __IM uint32_t MDV2MON : 1; /*!< [18..18] MDV2 status flag (ETH2 domain)                                   */
25950             __IM uint32_t MDV3MON : 1; /*!< [19..19] MDV3 status flag (xSPI0 domain)                                  */
25951             __IM uint32_t MDV4MON : 1; /*!< [20..20] MDV4 status flag (xSPI1 domain)                                  */
25952             uint32_t              : 11;
25953         } MD_MON_b;
25954     };
25955 } R_SYSC_NS_Type;                      /*!< Size = 4356 (0x1104)                                                      */
25956 
25957 /* =========================================================================================================================== */
25958 /* ================                                           R_ELO                                           ================ */
25959 /* =========================================================================================================================== */
25960 
25961 /**
25962  * @brief Evnet Link Option Setting (R_ELO)
25963  */
25964 
25965 typedef struct                         /*!< (@ 0x80281200) R_ELO Structure                                            */
25966 {
25967     union
25968     {
25969         __IOM uint32_t ELOPA;          /*!< (@ 0x00000000) Event Link Option Setting Register A                       */
25970 
25971         struct
25972         {
25973             __IOM uint32_t MTU0MD : 2; /*!< [1..0] MTU0 Operation Select                                              */
25974             uint32_t              : 4;
25975             __IOM uint32_t MTU3MD : 2; /*!< [7..6] MTU3 Operation Select                                              */
25976             uint32_t              : 24;
25977         } ELOPA_b;
25978     };
25979 
25980     union
25981     {
25982         __IOM uint32_t ELOPB;          /*!< (@ 0x00000004) Event Link Option Setting Register B                       */
25983 
25984         struct
25985         {
25986             __IOM uint32_t MTU4MD : 2; /*!< [1..0] MTU4 Operation Select                                              */
25987             uint32_t              : 30;
25988         } ELOPB_b;
25989     };
25990 } R_ELO_Type;                          /*!< Size = 8 (0x8)                                                            */
25991 
25992 /* =========================================================================================================================== */
25993 /* ================                                         R_RWP_NS                                          ================ */
25994 /* =========================================================================================================================== */
25995 
25996 /**
25997  * @brief Register Write Protection for Non-safety Area (R_RWP_NS)
25998  */
25999 
26000 typedef struct                         /*!< (@ 0x80281A10) R_RWP_NS Structure                                         */
26001 {
26002     union
26003     {
26004         __IOM uint32_t PRCRN;          /*!< (@ 0x00000000) Non_Safety Area Protect Register                           */
26005 
26006         struct
26007         {
26008             __IOM uint32_t PRC0 : 1;   /*!< [0..0] Protect 0                                                          */
26009             __IOM uint32_t PRC1 : 1;   /*!< [1..1] Protect 1                                                          */
26010             __IOM uint32_t PRC2 : 1;   /*!< [2..2] Protect 2                                                          */
26011             uint32_t            : 5;
26012             __OM uint32_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
26013             uint32_t            : 16;
26014         } PRCRN_b;
26015     };
26016 } R_RWP_NS_Type;                       /*!< Size = 4 (0x4)                                                            */
26017 
26018 /* =========================================================================================================================== */
26019 /* ================                                           R_RTC                                           ================ */
26020 /* =========================================================================================================================== */
26021 
26022 /**
26023  * @brief Real Time Clock (R_RTC)
26024  */
26025 
26026 typedef struct                         /*!< (@ 0x81009000) R_RTC Structure                                            */
26027 {
26028     union
26029     {
26030         __IOM uint32_t RTCA0CTL0;      /*!< (@ 0x00000000) RTC Control Register 0                                     */
26031 
26032         struct
26033         {
26034             uint32_t                 : 4;
26035             __IOM uint32_t RTCA0SLSB : 1; /*!< [4..4] RTCA0SCMP enable/disable setting                                   */
26036             __IOM uint32_t RTCA0AMPM : 1; /*!< [5..5] RTCA0HOUR, RTCA0ALH display format selection bit                   */
26037             __IM uint32_t  RTCA0CEST : 1; /*!< [6..6] RTC Controller Enable Status                                       */
26038             __IOM uint32_t RTCA0CE   : 1; /*!< [7..7] RTC Controller Enable Bit                                          */
26039             uint32_t                 : 24;
26040         } RTCA0CTL0_b;
26041     };
26042 
26043     union
26044     {
26045         __IOM uint32_t RTCA0CTL1;         /*!< (@ 0x00000004) RTC Control Register 1                                     */
26046 
26047         struct
26048         {
26049             __IOM uint32_t RTCA0CT   : 3; /*!< [2..0] Fixed interval interrupt (RTC_PRD) output setting bit              */
26050             __IOM uint32_t RTCA01SE  : 1; /*!< [3..3] 1 second interrupt (RTC_1S) output enable bit                      */
26051             __IOM uint32_t RTCA0ALME : 1; /*!< [4..4] Alarm interrupt (RTC_ALM) output enable bit                        */
26052             __IOM uint32_t RTCA01HZE : 1; /*!< [5..5] This bit enables/disables 1 Hz pulse output (RTCAT1HZ).            */
26053             uint32_t                 : 26;
26054         } RTCA0CTL1_b;
26055     };
26056 
26057     union
26058     {
26059         __IOM uint32_t RTCA0CTL2;         /*!< (@ 0x00000008) RTC Control Register 2                                     */
26060 
26061         struct
26062         {
26063             __IOM uint32_t RTCA0WAIT : 1; /*!< [0..0] RTC Controller Counter Wait Control                                */
26064             __IM uint32_t  RTCA0WST  : 1; /*!< [1..1] RTC Controller Counter Wait Status                                 */
26065             __IOM uint32_t RTCA0RSUB : 1; /*!< [2..2] RTCA0SUBC Data Transfer Control                                    */
26066             __IM uint32_t  RTCA0RSST : 1; /*!< [3..3] RTCA0SRBU Transfer Status                                          */
26067             __IM uint32_t  RTCA0WSST : 1; /*!< [4..4] RTCA0SCMP Write Status                                             */
26068             uint32_t                 : 27;
26069         } RTCA0CTL2_b;
26070     };
26071 
26072     union
26073     {
26074         __IM uint32_t RTCA0SUBC;          /*!< (@ 0x0000000C) RTC Sub Count Register                                     */
26075 
26076         struct
26077         {
26078             __IM uint32_t RTCA0SUBC : 22; /*!< [21..0] Register that counts the 1 second reference time                  */
26079             uint32_t                : 10;
26080         } RTCA0SUBC_b;
26081     };
26082 
26083     union
26084     {
26085         __IM uint32_t RTCA0SRBU;          /*!< (@ 0x00000010) RTC Sub Count Register Read Buffer                         */
26086 
26087         struct
26088         {
26089             __IM uint32_t RTCA0SRBU : 22; /*!< [21..0] Read buffer register of RTCA0SUBC                                 */
26090             uint32_t                : 10;
26091         } RTCA0SRBU_b;
26092     };
26093 
26094     union
26095     {
26096         __IOM uint32_t RTCA0SEC;         /*!< (@ 0x00000014) RTC Sec Count Buffer Register                              */
26097 
26098         struct
26099         {
26100             __IOM uint32_t RTCA0SEC : 7; /*!< [6..0] Buffer register to read/write RTC Second Count register
26101                                           *   (RTCA0SECC).                                                              */
26102             uint32_t : 25;
26103         } RTCA0SEC_b;
26104     };
26105 
26106     union
26107     {
26108         __IOM uint32_t RTCA0MIN;         /*!< (@ 0x00000018) RTC Min Count Buffer Register                              */
26109 
26110         struct
26111         {
26112             __IOM uint32_t RTCA0MIN : 7; /*!< [6..0] Buffer register to read/write RTC Minute Count register
26113                                           *   (RTCA0MINC).                                                              */
26114             uint32_t : 25;
26115         } RTCA0MIN_b;
26116     };
26117 
26118     union
26119     {
26120         __IOM uint32_t RTCA0HOUR;         /*!< (@ 0x0000001C) RTC Hour Count Buffer Register                             */
26121 
26122         struct
26123         {
26124             __IOM uint32_t RTCA0HOUR : 6; /*!< [5..0] Buffer register to read/write RTC Hour Count register
26125                                            *   (RTCA0HOURC).                                                             */
26126             uint32_t : 26;
26127         } RTCA0HOUR_b;
26128     };
26129 
26130     union
26131     {
26132         __IOM uint32_t RTCA0WEEK;         /*!< (@ 0x00000020) RTC Week Count Buffer Register                             */
26133 
26134         struct
26135         {
26136             __IOM uint32_t RTCA0WEEK : 3; /*!< [2..0] Buffer register to read/write RTC Week Count register
26137                                            *   (RTCA0WEEKC).                                                             */
26138             uint32_t : 29;
26139         } RTCA0WEEK_b;
26140     };
26141 
26142     union
26143     {
26144         __IOM uint32_t RTCA0DAY;         /*!< (@ 0x00000024) RTC Day Count Buffer Register                              */
26145 
26146         struct
26147         {
26148             __IOM uint32_t RTCA0DAY : 6; /*!< [5..0] Buffer register to read/write RTC Day Count register
26149                                           *   (RTCA0DAYC).                                                              */
26150             uint32_t : 26;
26151         } RTCA0DAY_b;
26152     };
26153 
26154     union
26155     {
26156         __IOM uint32_t RTCA0MONTH;         /*!< (@ 0x00000028) RTC Month Count Buffer Register                            */
26157 
26158         struct
26159         {
26160             __IOM uint32_t RTCA0MONTH : 5; /*!< [4..0] Buffer register to read/write RTC Month Count register
26161                                             *   (RTCA0MONC).                                                              */
26162             uint32_t : 27;
26163         } RTCA0MONTH_b;
26164     };
26165 
26166     union
26167     {
26168         __IOM uint32_t RTCA0YEAR;         /*!< (@ 0x0000002C) RTC Year Count Buffer Register                             */
26169 
26170         struct
26171         {
26172             __IOM uint32_t RTCA0YEAR : 8; /*!< [7..0] Buffer register to read/write RTC Year Count register
26173                                            *   (RTCA0YEARC).                                                             */
26174             uint32_t : 24;
26175         } RTCA0YEAR_b;
26176     };
26177 
26178     union
26179     {
26180         __IOM uint32_t RTCA0TIME;         /*!< (@ 0x00000030) RTC Time Set Register                                      */
26181 
26182         struct
26183         {
26184             __IOM uint32_t RTCA0SEC  : 8; /*!< [7..0] See RTCA0SEC register                                              */
26185             __IOM uint32_t RTCA0MIN  : 8; /*!< [15..8] See RTCA0MIN register                                             */
26186             __IOM uint32_t RTCA0HOUR : 8; /*!< [23..16] See RTCA0HOUR register                                           */
26187             uint32_t                 : 8;
26188         } RTCA0TIME_b;
26189     };
26190 
26191     union
26192     {
26193         __IOM uint32_t RTCA0CAL;           /*!< (@ 0x00000034) RTC Calendar Set Register                                  */
26194 
26195         struct
26196         {
26197             __IOM uint32_t RTCA0WEEK  : 8; /*!< [7..0] See RTCA0WEEK register                                             */
26198             __IOM uint32_t RTCA0DAY   : 8; /*!< [15..8] See RTCA0DAY register                                             */
26199             __IOM uint32_t RTCA0MONTH : 8; /*!< [23..16] See RTCA0MONTH register                                          */
26200             __IOM uint32_t RTCA0YEAR  : 8; /*!< [31..24] See RTCA0YEAR register                                           */
26201         } RTCA0CAL_b;
26202     };
26203     __IM uint32_t RESERVED;
26204 
26205     union
26206     {
26207         __IOM uint32_t RTCA0SCMP;          /*!< (@ 0x0000003C) RTC Sub Count Compare Register                             */
26208 
26209         struct
26210         {
26211             __IOM uint32_t RTCA0SCMP : 22; /*!< [21..0] Register that sets the compare value of RTCA0SUBC (sub-counter).  */
26212             uint32_t                 : 10;
26213         } RTCA0SCMP_b;
26214     };
26215 
26216     union
26217     {
26218         __IOM uint32_t RTCA0ALM;         /*!< (@ 0x00000040) RTC Alarm Min Set Register                                 */
26219 
26220         struct
26221         {
26222             __IOM uint32_t RTCA0ALM : 7; /*!< [6..0] RTCA0ALM is a register that performs the minute setting
26223                                           *   for the alarm interrupt.                                                  */
26224             uint32_t : 25;
26225         } RTCA0ALM_b;
26226     };
26227 
26228     union
26229     {
26230         __IOM uint32_t RTCA0ALH;         /*!< (@ 0x00000044) RTC Alarm Hour Set Register                                */
26231 
26232         struct
26233         {
26234             __IOM uint32_t RTCA0ALH : 6; /*!< [5..0] RTCA0ALH is a register that performs the hour setting
26235                                           *   for the alarm interrupt.                                                  */
26236             uint32_t : 26;
26237         } RTCA0ALH_b;
26238     };
26239 
26240     union
26241     {
26242         __IOM uint32_t RTCA0ALW;          /*!< (@ 0x00000048) RTC Alarm Week Set Register                                */
26243 
26244         struct
26245         {
26246             __IOM uint32_t RTCA0ALW0 : 1; /*!< [0..0] Alarm interrupt day of the week setting bit 0                      */
26247             __IOM uint32_t RTCA0ALW1 : 1; /*!< [1..1] Alarm interrupt day of the week setting bit 1                      */
26248             __IOM uint32_t RTCA0ALW2 : 1; /*!< [2..2] Alarm interrupt day of the week setting bit 2                      */
26249             __IOM uint32_t RTCA0ALW3 : 1; /*!< [3..3] Alarm interrupt day of the week setting bit 3                      */
26250             __IOM uint32_t RTCA0ALW4 : 1; /*!< [4..4] Alarm interrupt day of the week setting bit 4                      */
26251             __IOM uint32_t RTCA0ALW5 : 1; /*!< [5..5] Alarm interrupt day of the week setting bit 5                      */
26252             __IOM uint32_t RTCA0ALW6 : 1; /*!< [6..6] Alarm interrupt day of the week setting bit 6                      */
26253             uint32_t                 : 25;
26254         } RTCA0ALW_b;
26255     };
26256 
26257     union
26258     {
26259         __IM uint32_t RTCA0SECC;         /*!< (@ 0x0000004C) RTC Second Count Register                                  */
26260 
26261         struct
26262         {
26263             __IM uint32_t RTCA0SECC : 7; /*!< [6..0] Counts up the seconds                                              */
26264             uint32_t                : 25;
26265         } RTCA0SECC_b;
26266     };
26267 
26268     union
26269     {
26270         __IM uint32_t RTCA0MINC;         /*!< (@ 0x00000050) RTC Minute Count Register                                  */
26271 
26272         struct
26273         {
26274             __IM uint32_t RTCA0MINC : 7; /*!< [6..0] Counts up the minutes                                              */
26275             uint32_t                : 25;
26276         } RTCA0MINC_b;
26277     };
26278 
26279     union
26280     {
26281         __IM uint32_t RTCA0HOURC;         /*!< (@ 0x00000054) RTC Hour Count Register                                    */
26282 
26283         struct
26284         {
26285             __IM uint32_t RTCA0HOURC : 6; /*!< [5..0] Counts up the hours                                                */
26286             uint32_t                 : 26;
26287         } RTCA0HOURC_b;
26288     };
26289 
26290     union
26291     {
26292         __IM uint32_t RTCA0WEEKC;         /*!< (@ 0x00000058) RTC Week Count Register                                    */
26293 
26294         struct
26295         {
26296             __IM uint32_t RTCA0WEEKC : 3; /*!< [2..0] Counts up the weeks                                                */
26297             uint32_t                 : 29;
26298         } RTCA0WEEKC_b;
26299     };
26300 
26301     union
26302     {
26303         __IM uint32_t RTCA0DAYC;         /*!< (@ 0x0000005C) RTC Day Count Register                                     */
26304 
26305         struct
26306         {
26307             __IM uint32_t RTCA0DAYC : 6; /*!< [5..0] Counts up the days                                                 */
26308             uint32_t                : 26;
26309         } RTCA0DAYC_b;
26310     };
26311 
26312     union
26313     {
26314         __IM uint32_t RTCA0MONC;         /*!< (@ 0x00000060) RTC Month Count Register                                   */
26315 
26316         struct
26317         {
26318             __IM uint32_t RTCA0MONC : 5; /*!< [4..0] Counts up the months                                               */
26319             uint32_t                : 27;
26320         } RTCA0MONC_b;
26321     };
26322 
26323     union
26324     {
26325         __IM uint32_t RTCA0YEARC;         /*!< (@ 0x00000064) RTC Year Count Register                                    */
26326 
26327         struct
26328         {
26329             __IM uint32_t RTCA0YEARC : 8; /*!< [7..0] Counts up the years                                                */
26330             uint32_t                 : 24;
26331         } RTCA0YEARC_b;
26332     };
26333 
26334     union
26335     {
26336         __IM uint32_t RTCA0TIMEC;         /*!< (@ 0x00000068) RTC Time Count Register                                    */
26337 
26338         struct
26339         {
26340             __IM uint32_t RTCA0SECC  : 8; /*!< [7..0] See RTCA0SECC register                                             */
26341             __IM uint32_t RTCA0MINC  : 8; /*!< [15..8] See RTCA0MINC register                                            */
26342             __IM uint32_t RTCA0HOURC : 8; /*!< [23..16] See RTCA0HOURC register                                          */
26343             uint32_t                 : 8;
26344         } RTCA0TIMEC_b;
26345     };
26346 
26347     union
26348     {
26349         __IM uint32_t RTCA0CALC;          /*!< (@ 0x0000006C) RTC Calendar Count Register                                */
26350 
26351         struct
26352         {
26353             __IM uint32_t RTCA0WEEKC : 8; /*!< [7..0] See RTCA0WEEKC register                                            */
26354             __IM uint32_t RTCA0DAYC  : 8; /*!< [15..8] See RTCA0DAYC register                                            */
26355             __IM uint32_t RTCA0MONC  : 8; /*!< [23..16] See RTCA0MONC register                                           */
26356             __IM uint32_t RTCA0YEARC : 8; /*!< [31..24] See RTCA0YEARC register                                          */
26357         } RTCA0CALC_b;
26358     };
26359 } R_RTC_Type;                             /*!< Size = 112 (0x70)                                                         */
26360 
26361 /* =========================================================================================================================== */
26362 /* ================                                          R_POEG2                                          ================ */
26363 /* =========================================================================================================================== */
26364 
26365 /**
26366  * @brief GPT Port Output Enable 2 (R_POEG2)
26367  */
26368 
26369 typedef struct                         /*!< (@ 0x8100A000) R_POEG2 Structure                                          */
26370 {
26371     union
26372     {
26373         __IOM uint32_t POEG2GA;        /*!< (@ 0x00000000) POEG2 Group A Setting Register                             */
26374 
26375         struct
26376         {
26377             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
26378             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
26379             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
26380             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
26381             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
26382             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
26383             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
26384             uint32_t             : 9;
26385             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
26386             uint32_t             : 11;
26387             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
26388             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
26389             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
26390         } POEG2GA_b;
26391     };
26392     __IM uint32_t RESERVED[255];
26393 
26394     union
26395     {
26396         __IOM uint32_t POEG2GB;        /*!< (@ 0x00000400) POEG2 Group B Setting Register                             */
26397 
26398         struct
26399         {
26400             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
26401             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
26402             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
26403             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
26404             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
26405             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
26406             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
26407             uint32_t             : 9;
26408             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
26409             uint32_t             : 11;
26410             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
26411             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
26412             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
26413         } POEG2GB_b;
26414     };
26415     __IM uint32_t RESERVED1[255];
26416 
26417     union
26418     {
26419         __IOM uint32_t POEG2GC;        /*!< (@ 0x00000800) POEG2 Group C Setting Register                             */
26420 
26421         struct
26422         {
26423             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
26424             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
26425             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
26426             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
26427             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
26428             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
26429             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
26430             uint32_t             : 9;
26431             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
26432             uint32_t             : 11;
26433             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
26434             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
26435             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
26436         } POEG2GC_b;
26437     };
26438     __IM uint32_t RESERVED2[255];
26439 
26440     union
26441     {
26442         __IOM uint32_t POEG2GD;        /*!< (@ 0x00000C00) POEG2 Group D Setting Register                             */
26443 
26444         struct
26445         {
26446             __IOM uint32_t PIDF  : 1;  /*!< [0..0] Port Input Detection Flag                                          */
26447             __IOM uint32_t IOCF  : 1;  /*!< [1..1] GPT Output Stop Request Detection Flag                             */
26448             __IOM uint32_t OSTPF : 1;  /*!< [2..2] Oscillation Stop Detection Flag                                    */
26449             __IOM uint32_t SSF   : 1;  /*!< [3..3] Software Stop Flag                                                 */
26450             __IOM uint32_t PIDE  : 1;  /*!< [4..4] Port Input Detection Enable                                        */
26451             __IOM uint32_t IOCE  : 1;  /*!< [5..5] GPT Output Stop Request Enable                                     */
26452             __IOM uint32_t OSTPE : 1;  /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
26453             uint32_t             : 9;
26454             __IM uint32_t ST     : 1;  /*!< [16..16] GTETRGn Input Status Flag                                        */
26455             uint32_t             : 11;
26456             __IOM uint32_t INV   : 1;  /*!< [28..28] GTETRGn Input Inverting                                          */
26457             __IOM uint32_t NFEN  : 1;  /*!< [29..29] Noise filter Enable                                              */
26458             __IOM uint32_t NFCS  : 2;  /*!< [31..30] Noise filter Clock Select                                        */
26459         } POEG2GD_b;
26460     };
26461 } R_POEG2_Type;                        /*!< Size = 3076 (0xc04)                                                       */
26462 
26463 /* =========================================================================================================================== */
26464 /* ================                                           R_OTP                                           ================ */
26465 /* =========================================================================================================================== */
26466 
26467 /**
26468  * @brief One-Time Programmable Memory (R_OTP)
26469  */
26470 
26471 typedef struct                         /*!< (@ 0x81028000) R_OTP Structure                                            */
26472 {
26473     union
26474     {
26475         __IOM uint32_t OTPPWR;         /*!< (@ 0x00000000) OTP Power Control Register                                 */
26476 
26477         struct
26478         {
26479             __IOM uint32_t PWR  : 1;   /*!< [0..0] OTP power on/off setting                                           */
26480             uint32_t            : 3;
26481             __IOM uint32_t ACCL : 1;   /*!< [4..4] Selects OTP access I/F                                             */
26482             uint32_t            : 27;
26483         } OTPPWR_b;
26484     };
26485 
26486     union
26487     {
26488         __IOM uint32_t OTPSTR;             /*!< (@ 0x00000004) OTP Access Status Register                                 */
26489 
26490         struct
26491         {
26492             __IM uint32_t CMD_RDY : 1;     /*!< [0..0] Indicates whether OTP controller is ready to receive
26493                                             *   command or not.                                                           */
26494             __IM uint32_t ERR_WR      : 2; /*!< [2..1] OTP write status                                                   */
26495             __IM uint32_t ERR_WP      : 1; /*!< [3..3] Write protection error                                             */
26496             __IM uint32_t ERR_RP      : 1; /*!< [4..4] Read protection error                                              */
26497             uint32_t                  : 3;
26498             __IOM uint32_t ERR_RDY_WR : 1; /*!< [8..8] OTP write command ready error                                      */
26499             __IOM uint32_t ERR_RDY_RD : 1; /*!< [9..9] OTP read command ready error                                       */
26500             uint32_t                  : 5;
26501             __IM uint32_t CNT_ST_IDLE : 1; /*!< [15..15] Indicates status of OTP controller                               */
26502             uint32_t                  : 16;
26503         } OTPSTR_b;
26504     };
26505 
26506     union
26507     {
26508         __IOM uint32_t OTPSTAWR;       /*!< (@ 0x00000008) OTP Write Command Register                                 */
26509 
26510         struct
26511         {
26512             __IOM uint32_t STAWR : 1;  /*!< [0..0] OTP write start                                                    */
26513             uint32_t             : 31;
26514         } OTPSTAWR_b;
26515     };
26516 
26517     union
26518     {
26519         __IOM uint32_t OTPADRWR;       /*!< (@ 0x0000000C) OTP Write Address Register                                 */
26520 
26521         struct
26522         {
26523             __IOM uint32_t ADRWR : 9;  /*!< [8..0] OTP write address                                                  */
26524             uint32_t             : 23;
26525         } OTPADRWR_b;
26526     };
26527 
26528     union
26529     {
26530         __IOM uint32_t OTPDATAWR;       /*!< (@ 0x00000010) OTP Write Data Register                                    */
26531 
26532         struct
26533         {
26534             __IOM uint32_t DATAWR : 16; /*!< [15..0] OTP write data                                                    */
26535             uint32_t              : 16;
26536         } OTPDATAWR_b;
26537     };
26538 
26539     union
26540     {
26541         __IOM uint32_t OTPADRRD;       /*!< (@ 0x00000014) OTP Read Address Register                                  */
26542 
26543         struct
26544         {
26545             __IOM uint32_t ADRRD : 9;  /*!< [8..0] OTP read address                                                   */
26546             uint32_t             : 23;
26547         } OTPADRRD_b;
26548     };
26549 
26550     union
26551     {
26552         __IM uint32_t OTPDATARD;       /*!< (@ 0x00000018) OTP Read Data Register                                     */
26553 
26554         struct
26555         {
26556             __IM uint32_t DATARD : 16; /*!< [15..0] OTP read data                                                     */
26557             uint32_t             : 16;
26558         } OTPDATARD_b;
26559     };
26560 } R_OTP_Type;                          /*!< Size = 28 (0x1c)                                                          */
26561 
26562 /* =========================================================================================================================== */
26563 /* ================                                          R_PTADR                                          ================ */
26564 /* =========================================================================================================================== */
26565 
26566 /**
26567  * @brief Port Address Selection (R_PTADR)
26568  */
26569 
26570 typedef struct                         /*!< (@ 0x81030C00) R_PTADR Structure                                          */
26571 {
26572     union
26573     {
26574         __IOM uint8_t RSELP[25];       /*!< (@ 0x00000000) Port [0..24] Region Select Register                        */
26575 
26576         struct
26577         {
26578             __IOM uint8_t RS0 : 1;     /*!< [0..0] Pm_n pin I/O port registers Region Select (n = bit position)       */
26579             __IOM uint8_t RS1 : 1;     /*!< [1..1] Pm_n pin I/O port registers Region Select (n = bit position)       */
26580             __IOM uint8_t RS2 : 1;     /*!< [2..2] Pm_n pin I/O port registers Region Select (n = bit position)       */
26581             __IOM uint8_t RS3 : 1;     /*!< [3..3] Pm_n pin I/O port registers Region Select (n = bit position)       */
26582             __IOM uint8_t RS4 : 1;     /*!< [4..4] Pm_n pin I/O port registers Region Select (n = bit position)       */
26583             __IOM uint8_t RS5 : 1;     /*!< [5..5] Pm_n pin I/O port registers Region Select (n = bit position)       */
26584             __IOM uint8_t RS6 : 1;     /*!< [6..6] Pm_n pin I/O port registers Region Select (n = bit position)       */
26585             __IOM uint8_t RS7 : 1;     /*!< [7..7] Pm_n pin I/O port registers Region Select (n = bit position)       */
26586         } RSELP_b[25];
26587     };
26588 } R_PTADR_Type;                        /*!< Size = 25 (0x19)                                                          */
26589 
26590 /* =========================================================================================================================== */
26591 /* ================                                         R_SYSRAM0                                         ================ */
26592 /* =========================================================================================================================== */
26593 
26594 /**
26595  * @brief System SRAM 0 (R_SYSRAM0)
26596  */
26597 
26598 typedef struct                         /*!< (@ 0x81040000) R_SYSRAM0 Structure                                        */
26599 {
26600     __IOM R_SYSRAM0_W_Type W[4];       /*!< (@ 0x00000000) System SRAM Wn Registers (n = 0 to 3)                      */
26601 } R_SYSRAM0_Type;                      /*!< Size = 256 (0x100)                                                        */
26602 
26603 /* =========================================================================================================================== */
26604 /* ================                                           R_ICU                                           ================ */
26605 /* =========================================================================================================================== */
26606 
26607 /**
26608  * @brief Interrupt Controller (R_ICU)
26609  */
26610 
26611 typedef struct                         /*!< (@ 0x81048000) R_ICU Structure                                            */
26612 {
26613     union
26614     {
26615         __OM uint32_t S_SWINT;         /*!< (@ 0x00000000) Software Interrupt Register for Safety Register            */
26616 
26617         struct
26618         {
26619             __OM uint32_t IC6 : 1;     /*!< [0..0] Software Interrupt register                                        */
26620             __OM uint32_t IC7 : 1;     /*!< [1..1] Software Interrupt register                                        */
26621             uint32_t          : 30;
26622         } S_SWINT_b;
26623     };
26624 
26625     union
26626     {
26627         __IOM uint32_t S_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register for Safety
26628                                          *                  Register                                                   */
26629 
26630         struct
26631         {
26632             __IOM uint32_t FLT14  : 1;  /*!< [0..0] Noise filter enable for IRQ14                                      */
26633             __IOM uint32_t FLT15  : 1;  /*!< [1..1] Noise filter enable for IRQ15                                      */
26634             __IOM uint32_t FLTNMI : 1;  /*!< [2..2] Noise filter enable for NMI                                        */
26635             uint32_t              : 29;
26636         } S_PORTNF_FLTSEL_b;
26637     };
26638 
26639     union
26640     {
26641         __IOM uint32_t S_PORTNF_CLKSEL;  /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register for Safety
26642                                           *                  Register                                                   */
26643 
26644         struct
26645         {
26646             __IOM uint32_t CKSEL14 : 2;  /*!< [1..0] Select noise filter sampling frequency dividend rate
26647                                           *   for IRQ14.                                                                */
26648             __IOM uint32_t CKSEL15 : 2;  /*!< [3..2] Select noise filter sampling frequency dividend rate
26649                                           *   for IRQ15.                                                                */
26650             __IOM uint32_t CKSELNMI : 2; /*!< [5..4] Select noise filter sampling frequency dividend rate
26651                                           *   for NMI.                                                                  */
26652             uint32_t : 26;
26653         } S_PORTNF_CLKSEL_b;
26654     };
26655 
26656     union
26657     {
26658         __IOM uint32_t S_PORTNF_MD;    /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register for
26659                                         *                  Safety Register                                            */
26660 
26661         struct
26662         {
26663             __IOM uint32_t MD14  : 2;  /*!< [1..0] Select detection mode for IRQ14                                    */
26664             __IOM uint32_t MD15  : 2;  /*!< [3..2] Select detection mode for IRQ15                                    */
26665             __IOM uint32_t MDNMI : 2;  /*!< [5..4] Select detection mode for NMI                                      */
26666             uint32_t             : 26;
26667         } S_PORTNF_MD_b;
26668     };
26669     __IM uint32_t RESERVED[20];
26670 
26671     union
26672     {
26673         __IM uint32_t CPU0ERR_STAT;    /*!< (@ 0x00000060) CPU0 Error Event Status Register                           */
26674 
26675         struct
26676         {
26677             __IM uint32_t ER_ST0  : 1; /*!< [0..0] Indicate captured error status for CPU0_ERREVENT0                  */
26678             __IM uint32_t ER_ST1  : 1; /*!< [1..1] Indicate captured error status for CPU0_ERREVENT1                  */
26679             __IM uint32_t ER_ST2  : 1; /*!< [2..2] Indicate captured error status for CPU0_ERREVENT2                  */
26680             __IM uint32_t ER_ST3  : 1; /*!< [3..3] Indicate captured error status for CPU0_ERREVENT3                  */
26681             __IM uint32_t ER_ST4  : 1; /*!< [4..4] Indicate captured error status for CPU0_ERREVENT4                  */
26682             __IM uint32_t ER_ST5  : 1; /*!< [5..5] Indicate captured error status for CPU0_ERREVENT5                  */
26683             __IM uint32_t ER_ST6  : 1; /*!< [6..6] Indicate captured error status for CPU0_ERREVENT6                  */
26684             __IM uint32_t ER_ST7  : 1; /*!< [7..7] Indicate captured error status for CPU0_ERREVENT7                  */
26685             __IM uint32_t ER_ST8  : 1; /*!< [8..8] Indicate captured error status for CPU0_ERREVENT8                  */
26686             __IM uint32_t ER_ST9  : 1; /*!< [9..9] Indicate captured error status for CPU0_ERREVENT9                  */
26687             __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for CPU0_ERREVENT10               */
26688             __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for CPU0_ERREVENT11               */
26689             __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for CPU0_ERREVENT12               */
26690             __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for CPU0_ERREVENT13               */
26691             __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for CPU0_ERREVENT14               */
26692             __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for CPU0_ERREVENT15               */
26693             __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for CPU0_ERREVENT16               */
26694             __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for CPU0_ERREVENT17               */
26695             __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for CPU0_ERREVENT18               */
26696             __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for CPU0_ERREVENT19               */
26697             __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for CPU0_ERREVENT20               */
26698             __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for CPU0_ERREVENT21               */
26699             __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for CPU0_ERREVENT22               */
26700             __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for CPU0_ERREVENT23               */
26701             __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for CPU0_ERREVENT24               */
26702             __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for CPU0_ERREVENT25               */
26703             uint32_t              : 6;
26704         } CPU0ERR_STAT_b;
26705     };
26706     __IM uint32_t RESERVED1;
26707 
26708     union
26709     {
26710         __IM uint32_t PERIERR_STAT0;   /*!< (@ 0x00000068) Peripheral Error Event Status Register 0                   */
26711 
26712         struct
26713         {
26714             __IM uint32_t ER_ST0  : 1; /*!< [0..0] Indicate captured error status for CLMA3_INT                       */
26715             __IM uint32_t ER_ST1  : 1; /*!< [1..1] Indicate captured error status for CLMA0_INT                       */
26716             __IM uint32_t ER_ST2  : 1; /*!< [2..2] Indicate captured error status for CLMA1_INT                       */
26717             __IM uint32_t ER_ST3  : 1; /*!< [3..3] Indicate captured error status for CLMA2_INT                       */
26718             __IM uint32_t ER_ST4  : 1; /*!< [4..4] Indicate captured error status for BSC_WTO                         */
26719             __IM uint32_t ER_ST5  : 1; /*!< [5..5] Indicate captured error status for DMAC0_ERR                       */
26720             __IM uint32_t ER_ST6  : 1; /*!< [6..6] Indicate captured error status for DMAC1_ERR                       */
26721             __IM uint32_t ER_ST7  : 1; /*!< [7..7] Indicate captured error status for WDT_NMIUNDF0                    */
26722             uint32_t              : 1;
26723             __IM uint32_t ER_ST9  : 1; /*!< [9..9] Indicate captured error status for USB_FDMAERR                     */
26724             __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for DSMIF0_LTCSE                  */
26725             __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for DSMIF0_UTCSE                  */
26726             __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for DSMIF0_LTODE0                 */
26727             __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for DSMIF0_LTODE1                 */
26728             __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for DSMIF0_LTODE2                 */
26729             __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for DSMIF0_UTODE0                 */
26730             __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for DSMIF0_UTODE1                 */
26731             __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for DSMIF0_UTODE2                 */
26732             __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for DSMIF0_SCDE0                  */
26733             __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for DSMIF0_SCDE1                  */
26734             __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for DSMIF0_SCDE2                  */
26735             __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for DSMIF1_LTCSE                  */
26736             __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for DSMIF1_UTCSE                  */
26737             __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for DSMIF1_LTODE0                 */
26738             __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for DSMIF1_LTODE1                 */
26739             __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for DSMIF1_LTODE2                 */
26740             __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate captured error status for DSMIF1_UTODE0                 */
26741             __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for DSMIF1_UTODE1                 */
26742             __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for DSMIF1_UTODE2                 */
26743             __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate captured error status for DSMIF1_SCDE0                  */
26744             __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate captured error status for DSMIF1_SCDE1                  */
26745             __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate captured error status for DSMIF1_SCDE2                  */
26746         } PERIERR_STAT0_b;
26747     };
26748 
26749     union
26750     {
26751         __IM uint32_t PERIERR_STAT1;   /*!< (@ 0x0000006C) Peripheral Error Event Status Register 1                   */
26752 
26753         struct
26754         {
26755             __IM uint32_t ER_ST0  : 1; /*!< [0..0] Indicate captured error status for DOC_DOPCI                       */
26756             __IM uint32_t ER_ST1  : 1; /*!< [1..1] Indicate captured error status for SRAM0_IE1                       */
26757             __IM uint32_t ER_ST2  : 1; /*!< [2..2] Indicate captured error status for SRAM0_IE2                       */
26758             __IM uint32_t ER_ST3  : 1; /*!< [3..3] Indicate captured error status for SRAM0_OVF                       */
26759             __IM uint32_t ER_ST4  : 1; /*!< [4..4] Indicate captured error status for SRAM1_IE1                       */
26760             __IM uint32_t ER_ST5  : 1; /*!< [5..5] Indicate captured error status for SRAM1_IE2                       */
26761             __IM uint32_t ER_ST6  : 1; /*!< [6..6] Indicate captured error status for SRAM1_OVF                       */
26762             __IM uint32_t ER_ST7  : 1; /*!< [7..7] Indicate captured error status for SRAM2_IE1                       */
26763             __IM uint32_t ER_ST8  : 1; /*!< [8..8] Indicate captured error status for SRAM2_IE2                       */
26764             __IM uint32_t ER_ST9  : 1; /*!< [9..9] Indicate captured error status for SRAM2_OVF                       */
26765             uint32_t              : 3;
26766             __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for BUS_ERRINT                    */
26767             uint32_t              : 1;
26768             __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for MPU_SHOSTIF                   */
26769             __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for MPU_PHOSTIF                   */
26770             __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for MPU_DMACR0                    */
26771             __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for MPU_DMACW0                    */
26772             __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for MPU_DMACR1                    */
26773             __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for MPU_DMACW1                    */
26774             __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for MPU_GMACR                     */
26775             __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for MPU_GMACW                     */
26776             __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for MPU_USBH                      */
26777             __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for MPU_USBF                      */
26778             uint32_t              : 2;
26779             __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for MPU_DBGR                      */
26780             __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for MPU_DBGW                      */
26781             uint32_t              : 3;
26782         } PERIERR_STAT1_b;
26783     };
26784 
26785     union
26786     {
26787         __OM uint32_t CPU0ERR_CLR;     /*!< (@ 0x00000070) CPU0 Error Event Status Clear Register                     */
26788 
26789         struct
26790         {
26791             __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for CPU0ERR_STAT register
26792                                         *   by writing 1                                                              */
26793             __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for CPU0ERR_STAT register
26794                                         *   by writing 1                                                              */
26795             __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for CPU0ERR_STAT register
26796                                         *   by writing 1                                                              */
26797             __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for CPU0ERR_STAT register
26798                                         *   by writing 1                                                              */
26799             __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for CPU0ERR_STAT register
26800                                         *   by writing 1                                                              */
26801             __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for CPU0ERR_STAT register
26802                                         *   by writing 1                                                              */
26803             __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for CPU0ERR_STAT register
26804                                         *   by writing 1                                                              */
26805             __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for CPU0ERR_STAT register
26806                                         *   by writing 1                                                              */
26807             __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for CPU0ERR_STAT register
26808                                         *   by writing 1                                                              */
26809             __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for CPU0ERR_STAT register
26810                                         *   by writing 1                                                              */
26811             __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for CPU0ERR_STAT register
26812                                         *   by writing 1                                                              */
26813             __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for CPU0ERR_STAT register
26814                                         *   by writing 1                                                              */
26815             __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for CPU0ERR_STAT register
26816                                         *   by writing 1                                                              */
26817             __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for CPU0ERR_STAT register
26818                                         *   by writing 1                                                              */
26819             __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for CPU0ERR_STAT register
26820                                         *   by writing 1                                                              */
26821             __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for CPU0ERR_STAT register
26822                                         *   by writing 1                                                              */
26823             __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for CPU0ERR_STAT register
26824                                         *   by writing 1                                                              */
26825             __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for CPU0ERR_STAT register
26826                                         *   by writing 1                                                              */
26827             __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for CPU0ERR_STAT register
26828                                         *   by writing 1                                                              */
26829             __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for CPU0ERR_STAT register
26830                                         *   by writing 1                                                              */
26831             __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for CPU0ERR_STAT register
26832                                         *   by writing 1                                                              */
26833             __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for CPU0ERR_STAT register
26834                                         *   by writing 1                                                              */
26835             __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for CPU0ERR_STAT register
26836                                         *   by writing 1                                                              */
26837             __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for CPU0ERR_STAT register
26838                                         *   by writing 1                                                              */
26839             __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for CPU0ERR_STAT register
26840                                         *   by writing 1                                                              */
26841             __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for CPU0ERR_STAT register
26842                                         *   by writing 1                                                              */
26843             uint32_t : 6;
26844         } CPU0ERR_CLR_b;
26845     };
26846     __IM uint32_t RESERVED2;
26847 
26848     union
26849     {
26850         __OM uint32_t PERIERR_CLR0;    /*!< (@ 0x00000078) Peripheral Error Event Status Clear Register
26851                                         *                  0                                                          */
26852 
26853         struct
26854         {
26855             __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for PERIERR_STAT0 register
26856                                         *   by writing 1                                                              */
26857             __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for PERIERR_STAT0 register
26858                                         *   by writing 1                                                              */
26859             __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for PERIERR_STAT0 register
26860                                         *   by writing 1                                                              */
26861             __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for PERIERR_STAT0 register
26862                                         *   by writing 1                                                              */
26863             __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for PERIERR_STAT0 register
26864                                         *   by writing 1                                                              */
26865             __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for PERIERR_STAT0 register
26866                                         *   by writing 1                                                              */
26867             __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for PERIERR_STAT0 register
26868                                         *   by writing 1                                                              */
26869             __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for PERIERR_STAT0 register
26870                                         *   by writing 1                                                              */
26871             uint32_t             : 1;
26872             __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for PERIERR_STAT0 register
26873                                         *   by writing 1                                                              */
26874             __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for PERIERR_STAT0 register
26875                                         *   by writing 1                                                              */
26876             __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for PERIERR_STAT0 register
26877                                         *   by writing 1                                                              */
26878             __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for PERIERR_STAT0 register
26879                                         *   by writing 1                                                              */
26880             __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT0 register
26881                                         *   by writing 1                                                              */
26882             __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for PERIERR_STAT0 register
26883                                         *   by writing 1                                                              */
26884             __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT0 register
26885                                         *   by writing 1                                                              */
26886             __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT0 register
26887                                         *   by writing 1                                                              */
26888             __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT0 register
26889                                         *   by writing 1                                                              */
26890             __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT0 register
26891                                         *   by writing 1                                                              */
26892             __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT0 register
26893                                         *   by writing 1                                                              */
26894             __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT0 register
26895                                         *   by writing 1                                                              */
26896             __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT0 register
26897                                         *   by writing 1                                                              */
26898             __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT0 register
26899                                         *   by writing 1                                                              */
26900             __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT0 register
26901                                         *   by writing 1                                                              */
26902             __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT0 register
26903                                         *   by writing 1                                                              */
26904             __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for PERIERR_STAT0 register
26905                                         *   by writing 1                                                              */
26906             __OM uint32_t ER_CL26 : 1; /*!< [26..26] Clear captured error status for PERIERR_STAT0 register
26907                                         *   by writing 1                                                              */
26908             __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT0 register
26909                                         *   by writing 1                                                              */
26910             __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT0 register
26911                                         *   by writing 1                                                              */
26912             __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for PERIERR_STAT0 register
26913                                         *   by writing 1                                                              */
26914             __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for PERIERR_STAT0 register
26915                                         *   by writing 1                                                              */
26916             __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for PERIERR_STAT0 register
26917                                         *   by writing 1                                                              */
26918         } PERIERR_CLR0_b;
26919     };
26920 
26921     union
26922     {
26923         __OM uint32_t PERIERR_CLR1;    /*!< (@ 0x0000007C) Peripheral Error Event Status Clear Register
26924                                         *                  1                                                          */
26925 
26926         struct
26927         {
26928             __OM uint32_t ER_CL0 : 1;  /*!< [0..0] Clear captured error status for PERIERR_STAT1 register
26929                                         *   by writing 1                                                              */
26930             __OM uint32_t ER_CL1 : 1;  /*!< [1..1] Clear captured error status for PERIERR_STAT1 register
26931                                         *   by writing 1                                                              */
26932             __OM uint32_t ER_CL2 : 1;  /*!< [2..2] Clear captured error status for PERIERR_STAT1 register
26933                                         *   by writing 1                                                              */
26934             __OM uint32_t ER_CL3 : 1;  /*!< [3..3] Clear captured error status for PERIERR_STAT1 register
26935                                         *   by writing 1                                                              */
26936             __OM uint32_t ER_CL4 : 1;  /*!< [4..4] Clear captured error status for PERIERR_STAT1 register
26937                                         *   by writing 1                                                              */
26938             __OM uint32_t ER_CL5 : 1;  /*!< [5..5] Clear captured error status for PERIERR_STAT1 register
26939                                         *   by writing 1                                                              */
26940             __OM uint32_t ER_CL6 : 1;  /*!< [6..6] Clear captured error status for PERIERR_STAT1 register
26941                                         *   by writing 1                                                              */
26942             __OM uint32_t ER_CL7 : 1;  /*!< [7..7] Clear captured error status for PERIERR_STAT1 register
26943                                         *   by writing 1                                                              */
26944             __OM uint32_t ER_CL8 : 1;  /*!< [8..8] Clear captured error status for PERIERR_STAT1 register
26945                                         *   by writing 1                                                              */
26946             __OM uint32_t ER_CL9 : 1;  /*!< [9..9] Clear captured error status for PERIERR_STAT1 register
26947                                         *   by writing 1                                                              */
26948             uint32_t              : 3;
26949             __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT1 register
26950                                         *   by writing 1                                                              */
26951             uint32_t              : 1;
26952             __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT1 register
26953                                         *   by writing 1                                                              */
26954             __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT1 register
26955                                         *   by writing 1                                                              */
26956             __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT1 register
26957                                         *   by writing 1                                                              */
26958             __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT1 register
26959                                         *   by writing 1                                                              */
26960             __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT1 register
26961                                         *   by writing 1                                                              */
26962             __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT1 register
26963                                         *   by writing 1                                                              */
26964             __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT1 register
26965                                         *   by writing 1                                                              */
26966             __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT1 register
26967                                         *   by writing 1                                                              */
26968             __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT1 register
26969                                         *   by writing 1                                                              */
26970             __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT1 register
26971                                         *   by writing 1                                                              */
26972             uint32_t              : 2;
26973             __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT1 register
26974                                         *   by writing 1                                                              */
26975             __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT1 register
26976                                         *   by writing 1                                                              */
26977             uint32_t : 3;
26978         } PERIERR_CLR1_b;
26979     };
26980 
26981     union
26982     {
26983         __IOM uint32_t CPU0ERR_RSTMSK;  /*!< (@ 0x00000080) CPU0 Error Event Reset Mask Register                       */
26984 
26985         struct
26986         {
26987             __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for CPU0ERR_STAT       */
26988             __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for CPU0ERR_STAT       */
26989             __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for CPU0ERR_STAT       */
26990             __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for CPU0ERR_STAT       */
26991             __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for CPU0ERR_STAT       */
26992             __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for CPU0ERR_STAT       */
26993             __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for CPU0ERR_STAT       */
26994             __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for CPU0ERR_STAT       */
26995             __IOM uint32_t RS_MK8  : 1; /*!< [8..8] Mask captured error status as a reset event for CPU0ERR_STAT       */
26996             __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for CPU0ERR_STAT       */
26997             __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for CPU0ERR_STAT     */
26998             __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for CPU0ERR_STAT     */
26999             __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for CPU0ERR_STAT     */
27000             __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for CPU0ERR_STAT     */
27001             __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for CPU0ERR_STAT     */
27002             __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for CPU0ERR_STAT     */
27003             __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for CPU0ERR_STAT     */
27004             __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for CPU0ERR_STAT     */
27005             __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for CPU0ERR_STAT     */
27006             __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for CPU0ERR_STAT     */
27007             __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for CPU0ERR_STAT     */
27008             __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for CPU0ERR_STAT     */
27009             __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for CPU0ERR_STAT     */
27010             __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for CPU0ERR_STAT     */
27011             __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for CPU0ERR_STAT     */
27012             __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for CPU0ERR_STAT     */
27013             uint32_t               : 6;
27014         } CPU0ERR_RSTMSK_b;
27015     };
27016     __IM uint32_t RESERVED3;
27017 
27018     union
27019     {
27020         __IOM uint32_t PERIERR_RSTMSK0; /*!< (@ 0x00000088) Peripheral Error Event Reset Mask Register 0               */
27021 
27022         struct
27023         {
27024             __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT0      */
27025             __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT0      */
27026             __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT0      */
27027             __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT0      */
27028             __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT0      */
27029             __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT0      */
27030             __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT0      */
27031             __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT0      */
27032             uint32_t               : 1;
27033             __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT0      */
27034             __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT0    */
27035             __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT0    */
27036             __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT0    */
27037             __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT0    */
27038             __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT0    */
27039             __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT0    */
27040             __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT0    */
27041             __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT0    */
27042             __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT0    */
27043             __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT0    */
27044             __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT0    */
27045             __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT0    */
27046             __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT0    */
27047             __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT0    */
27048             __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT0    */
27049             __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for PERIERR_STAT0    */
27050             __IOM uint32_t RS_MK26 : 1; /*!< [26..26] Mask captured error status as a reset event for PERIERR_STAT0    */
27051             __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT0    */
27052             __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT0    */
27053             __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT0    */
27054             __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT0    */
27055             __IOM uint32_t RS_MK31 : 1; /*!< [31..31] Mask captured error status as a reset event for PERIERR_STAT0    */
27056         } PERIERR_RSTMSK0_b;
27057     };
27058 
27059     union
27060     {
27061         __IOM uint32_t PERIERR_RSTMSK1; /*!< (@ 0x0000008C) Peripheral Error Event Reset Mask Register 1               */
27062 
27063         struct
27064         {
27065             __IOM uint32_t RS_MK0  : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT1      */
27066             __IOM uint32_t RS_MK1  : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT1      */
27067             __IOM uint32_t RS_MK2  : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT1      */
27068             __IOM uint32_t RS_MK3  : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT1      */
27069             __IOM uint32_t RS_MK4  : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT1      */
27070             __IOM uint32_t RS_MK5  : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT1      */
27071             __IOM uint32_t RS_MK6  : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT1      */
27072             __IOM uint32_t RS_MK7  : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT1      */
27073             __IOM uint32_t RS_MK8  : 1; /*!< [8..8] Mask captured error status as a reset event for PERIERR_STAT1      */
27074             __IOM uint32_t RS_MK9  : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT1      */
27075             uint32_t               : 3;
27076             __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT1    */
27077             uint32_t               : 1;
27078             __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT1    */
27079             __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT1    */
27080             __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT1    */
27081             __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT1    */
27082             __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT1    */
27083             __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT1    */
27084             __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT1    */
27085             __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT1    */
27086             __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT1    */
27087             __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT1    */
27088             uint32_t               : 2;
27089             __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT1    */
27090             __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT1    */
27091             uint32_t               : 3;
27092         } PERIERR_RSTMSK1_b;
27093     };
27094 
27095     union
27096     {
27097         __IOM uint32_t CPU0ERR_E0MSK;   /*!< (@ 0x00000090) CPU0 E0 Error Event Mask Register                          */
27098 
27099         struct
27100         {
27101             __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an CPU0_ERR0 event for
27102                                          *   CPU0ERR_STAT                                                              */
27103             __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an CPU0_ERR0 event for
27104                                          *   CPU0ERR_STAT                                                              */
27105             __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an CPU0_ERR0 event for
27106                                          *   CPU0ERR_STAT                                                              */
27107             __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an CPU0_ERR0 event for
27108                                          *   CPU0ERR_STAT                                                              */
27109             __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an CPU0_ERR0 event for
27110                                          *   CPU0ERR_STAT                                                              */
27111             __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an CPU0_ERR0 event for
27112                                          *   CPU0ERR_STAT                                                              */
27113             __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an CPU0_ERR0 event for
27114                                          *   CPU0ERR_STAT                                                              */
27115             __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an CPU0_ERR0 event for
27116                                          *   CPU0ERR_STAT                                                              */
27117             __IOM uint32_t E0_MK8 : 1;  /*!< [8..8] Mask captured error status as an CPU0_ERR0 event for
27118                                          *   CPU0ERR_STAT                                                              */
27119             __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an CPU0_ERR0 event for
27120                                          *   CPU0ERR_STAT                                                              */
27121             __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR0 event for
27122                                          *   CPU0ERR_STAT                                                              */
27123             __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR0 event for
27124                                          *   CPU0ERR_STAT                                                              */
27125             __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR0 event for
27126                                          *   CPU0ERR_STAT                                                              */
27127             __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR0 event for
27128                                          *   CPU0ERR_STAT                                                              */
27129             __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR0 event for
27130                                          *   CPU0ERR_STAT                                                              */
27131             __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR0 event for
27132                                          *   CPU0ERR_STAT                                                              */
27133             __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR0 event for
27134                                          *   CPU0ERR_STAT                                                              */
27135             __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR0 event for
27136                                          *   CPU0ERR_STAT                                                              */
27137             __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR0 event for
27138                                          *   CPU0ERR_STAT                                                              */
27139             __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR0 event for
27140                                          *   CPU0ERR_STAT                                                              */
27141             __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR0 event for
27142                                          *   CPU0ERR_STAT                                                              */
27143             __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR0 event for
27144                                          *   CPU0ERR_STAT                                                              */
27145             __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR0 event for
27146                                          *   CPU0ERR_STAT                                                              */
27147             __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR0 event for
27148                                          *   CPU0ERR_STAT                                                              */
27149             __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR0 event for
27150                                          *   CPU0ERR_STAT                                                              */
27151             __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR0 event for
27152                                          *   CPU0ERR_STAT                                                              */
27153             uint32_t : 6;
27154         } CPU0ERR_E0MSK_b;
27155     };
27156     __IM uint32_t RESERVED4;
27157 
27158     union
27159     {
27160         __IOM uint32_t PERIERR_E0MSK0;  /*!< (@ 0x00000098) Peripheral E0 Error Event Mask Register 0                  */
27161 
27162         struct
27163         {
27164             __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR0 event for
27165                                          *   PERIERR_STAT0                                                             */
27166             __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR0 event for
27167                                          *   PERIERR_STAT0                                                             */
27168             __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR0 event for
27169                                          *   PERIERR_STAT0                                                             */
27170             __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR0 event for
27171                                          *   PERIERR_STAT0                                                             */
27172             __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR0 event for
27173                                          *   PERIERR_STAT0                                                             */
27174             __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR0 event for
27175                                          *   PERIERR_STAT0                                                             */
27176             __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR0 event for
27177                                          *   PERIERR_STAT0                                                             */
27178             __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR0 event for
27179                                          *   PERIERR_STAT0                                                             */
27180             uint32_t              : 1;
27181             __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR0 event for
27182                                          *   PERIERR_STAT0                                                             */
27183             __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR0 event for
27184                                          *   PERIERR_STAT0                                                             */
27185             __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR0 event for
27186                                          *   PERIERR_STAT0                                                             */
27187             __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR0 event for
27188                                          *   PERIERR_STAT0                                                             */
27189             __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for
27190                                          *   PERIERR_STAT0                                                             */
27191             __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR0 event for
27192                                          *   PERIERR_STAT0                                                             */
27193             __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for
27194                                          *   PERIERR_STAT0                                                             */
27195             __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for
27196                                          *   PERIERR_STAT0                                                             */
27197             __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for
27198                                          *   PERIERR_STAT0                                                             */
27199             __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for
27200                                          *   PERIERR_STAT0                                                             */
27201             __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for
27202                                          *   PERIERR_STAT0                                                             */
27203             __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for
27204                                          *   PERIERR_STAT0                                                             */
27205             __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for
27206                                          *   PERIERR_STAT0                                                             */
27207             __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for
27208                                          *   PERIERR_STAT0                                                             */
27209             __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for
27210                                          *   PERIERR_STAT0                                                             */
27211             __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for
27212                                          *   PERIERR_STAT0                                                             */
27213             __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR0 event for
27214                                          *   PERIERR_STAT0                                                             */
27215             __IOM uint32_t E0_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR0 event for
27216                                          *   PERIERR_STAT0                                                             */
27217             __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for
27218                                          *   PERIERR_STAT0                                                             */
27219             __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for
27220                                          *   PERIERR_STAT0                                                             */
27221             __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR0 event for
27222                                          *   PERIERR_STAT0                                                             */
27223             __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR0 event for
27224                                          *   PERIERR_STAT0                                                             */
27225             __IOM uint32_t E0_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR0 event for
27226                                          *   PERIERR_STAT0                                                             */
27227         } PERIERR_E0MSK0_b;
27228     };
27229 
27230     union
27231     {
27232         __IOM uint32_t PERIERR_E0MSK1;  /*!< (@ 0x0000009C) Peripheral E0 Error Event Mask Register 1                  */
27233 
27234         struct
27235         {
27236             __IOM uint32_t E0_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR0 event for
27237                                          *   PERIERR_STAT1                                                             */
27238             __IOM uint32_t E0_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR0 event for
27239                                          *   PERIERR_STAT1                                                             */
27240             __IOM uint32_t E0_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR0 event for
27241                                          *   PERIERR_STAT1                                                             */
27242             __IOM uint32_t E0_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR0 event for
27243                                          *   PERIERR_STAT1                                                             */
27244             __IOM uint32_t E0_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR0 event for
27245                                          *   PERIERR_STAT1                                                             */
27246             __IOM uint32_t E0_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR0 event for
27247                                          *   PERIERR_STAT1                                                             */
27248             __IOM uint32_t E0_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR0 event for
27249                                          *   PERIERR_STAT1                                                             */
27250             __IOM uint32_t E0_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR0 event for
27251                                          *   PERIERR_STAT1                                                             */
27252             __IOM uint32_t E0_MK8 : 1;  /*!< [8..8] Mask captured error status as an PERI_ERR0 event for
27253                                          *   PERIERR_STAT1                                                             */
27254             __IOM uint32_t E0_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR0 event for
27255                                          *   PERIERR_STAT1                                                             */
27256             uint32_t               : 3;
27257             __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for
27258                                          *   PERIERR_STAT1                                                             */
27259             uint32_t               : 1;
27260             __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for
27261                                          *   PERIERR_STAT1                                                             */
27262             __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for
27263                                          *   PERIERR_STAT1                                                             */
27264             __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for
27265                                          *   PERIERR_STAT1                                                             */
27266             __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for
27267                                          *   PERIERR_STAT1                                                             */
27268             __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for
27269                                          *   PERIERR_STAT1                                                             */
27270             __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for
27271                                          *   PERIERR_STAT1                                                             */
27272             __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for
27273                                          *   PERIERR_STAT1                                                             */
27274             __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for
27275                                          *   PERIERR_STAT1                                                             */
27276             __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for
27277                                          *   PERIERR_STAT1                                                             */
27278             __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for
27279                                          *   PERIERR_STAT1                                                             */
27280             uint32_t               : 2;
27281             __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for
27282                                          *   PERIERR_STAT1                                                             */
27283             __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for
27284                                          *   PERIERR_STAT1                                                             */
27285             uint32_t : 3;
27286         } PERIERR_E0MSK1_b;
27287     };
27288     __IM uint32_t RESERVED5[24];
27289 
27290     union
27291     {
27292         __IOM uint32_t CPU0ERR_E1MSK;   /*!< (@ 0x00000100) CPU0 E1 Error Event Mask Register                          */
27293 
27294         struct
27295         {
27296             __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an CPU0_ERR1 event for
27297                                          *   CPU0ERR_STAT                                                              */
27298             __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an CPU0_ERR1 event for
27299                                          *   CPU0ERR_STAT                                                              */
27300             __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an CPU0_ERR1 event for
27301                                          *   CPU0ERR_STAT                                                              */
27302             __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an CPU0_ERR1 event for
27303                                          *   CPU0ERR_STAT                                                              */
27304             __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an CPU0_ERR1 event for
27305                                          *   CPU0ERR_STAT                                                              */
27306             __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an CPU0_ERR1 event for
27307                                          *   CPU0ERR_STAT                                                              */
27308             __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an CPU0_ERR1 event for
27309                                          *   CPU0ERR_STAT                                                              */
27310             __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an CPU0_ERR1 event for
27311                                          *   CPU0ERR_STAT                                                              */
27312             __IOM uint32_t E1_MK8 : 1;  /*!< [8..8] Mask captured error status as an CPU0_ERR1 event for
27313                                          *   CPU0ERR_STAT                                                              */
27314             __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an CPU0_ERR1 event for
27315                                          *   CPU0ERR_STAT                                                              */
27316             __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR1 event for
27317                                          *   CPU0ERR_STAT                                                              */
27318             __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR1 event for
27319                                          *   CPU0ERR_STAT                                                              */
27320             __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR1 event for
27321                                          *   CPU0ERR_STAT                                                              */
27322             __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR1 event for
27323                                          *   CPU0ERR_STAT                                                              */
27324             __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR1 event for
27325                                          *   CPU0ERR_STAT                                                              */
27326             __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR1 event for
27327                                          *   CPU0ERR_STAT                                                              */
27328             __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR1 event for
27329                                          *   CPU0ERR_STAT                                                              */
27330             __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR1 event for
27331                                          *   CPU0ERR_STAT                                                              */
27332             __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR1 event for
27333                                          *   CPU0ERR_STAT                                                              */
27334             __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR1 event for
27335                                          *   CPU0ERR_STAT                                                              */
27336             __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR1 event for
27337                                          *   CPU0ERR_STAT                                                              */
27338             __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR1 event for
27339                                          *   CPU0ERR_STAT                                                              */
27340             __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR1 event for
27341                                          *   CPU0ERR_STAT                                                              */
27342             __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR1 event for
27343                                          *   CPU0ERR_STAT                                                              */
27344             __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR1 event for
27345                                          *   CPU0ERR_STAT                                                              */
27346             __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR1 event for
27347                                          *   CPU0ERR_STAT                                                              */
27348             uint32_t : 6;
27349         } CPU0ERR_E1MSK_b;
27350     };
27351     __IM uint32_t RESERVED6;
27352 
27353     union
27354     {
27355         __IOM uint32_t PERIERR_E1MSK0;  /*!< (@ 0x00000108) Peripheral E1 Error Event Mask Register 0                  */
27356 
27357         struct
27358         {
27359             __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR1 event for
27360                                          *   PERIERR_STAT0                                                             */
27361             __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR1 event for
27362                                          *   PERIERR_STAT0                                                             */
27363             __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR1 event for
27364                                          *   PERIERR_STAT0                                                             */
27365             __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR1 event for
27366                                          *   PERIERR_STAT0                                                             */
27367             __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR1 event for
27368                                          *   PERIERR_STAT0                                                             */
27369             __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR1 event for
27370                                          *   PERIERR_STAT0                                                             */
27371             __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR1 event for
27372                                          *   PERIERR_STAT0                                                             */
27373             __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR1 event for
27374                                          *   PERIERR_STAT0                                                             */
27375             uint32_t              : 1;
27376             __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR1 event for
27377                                          *   PERIERR_STAT0                                                             */
27378             __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR1 event for
27379                                          *   PERIERR_STAT0                                                             */
27380             __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR1 event for
27381                                          *   PERIERR_STAT0                                                             */
27382             __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR1 event for
27383                                          *   PERIERR_STAT0                                                             */
27384             __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for
27385                                          *   PERIERR_STAT0                                                             */
27386             __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR1 event for
27387                                          *   PERIERR_STAT0                                                             */
27388             __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for
27389                                          *   PERIERR_STAT0                                                             */
27390             __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for
27391                                          *   PERIERR_STAT0                                                             */
27392             __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for
27393                                          *   PERIERR_STAT0                                                             */
27394             __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for
27395                                          *   PERIERR_STAT0                                                             */
27396             __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for
27397                                          *   PERIERR_STAT0                                                             */
27398             __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for
27399                                          *   PERIERR_STAT0                                                             */
27400             __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for
27401                                          *   PERIERR_STAT0                                                             */
27402             __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for
27403                                          *   PERIERR_STAT0                                                             */
27404             __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for
27405                                          *   PERIERR_STAT0                                                             */
27406             __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for
27407                                          *   PERIERR_STAT0                                                             */
27408             __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR1 event for
27409                                          *   PERIERR_STAT0                                                             */
27410             __IOM uint32_t E1_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR1 event for
27411                                          *   PERIERR_STAT0                                                             */
27412             __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for
27413                                          *   PERIERR_STAT0                                                             */
27414             __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for
27415                                          *   PERIERR_STAT0                                                             */
27416             __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR1 event for
27417                                          *   PERIERR_STAT0                                                             */
27418             __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR1 event for
27419                                          *   PERIERR_STAT0                                                             */
27420             __IOM uint32_t E1_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR1 event for
27421                                          *   PERIERR_STAT0                                                             */
27422         } PERIERR_E1MSK0_b;
27423     };
27424 
27425     union
27426     {
27427         __IOM uint32_t PERIERR_E1MSK1;  /*!< (@ 0x0000010C) Peripheral E1 Error Event Mask Register 1                  */
27428 
27429         struct
27430         {
27431             __IOM uint32_t E1_MK0 : 1;  /*!< [0..0] Mask captured error status as an PERI_ERR1 event for
27432                                          *   PERIERR_STAT1                                                             */
27433             __IOM uint32_t E1_MK1 : 1;  /*!< [1..1] Mask captured error status as an PERI_ERR1 event for
27434                                          *   PERIERR_STAT1                                                             */
27435             __IOM uint32_t E1_MK2 : 1;  /*!< [2..2] Mask captured error status as an PERI_ERR1 event for
27436                                          *   PERIERR_STAT1                                                             */
27437             __IOM uint32_t E1_MK3 : 1;  /*!< [3..3] Mask captured error status as an PERI_ERR1 event for
27438                                          *   PERIERR_STAT1                                                             */
27439             __IOM uint32_t E1_MK4 : 1;  /*!< [4..4] Mask captured error status as an PERI_ERR1 event for
27440                                          *   PERIERR_STAT1                                                             */
27441             __IOM uint32_t E1_MK5 : 1;  /*!< [5..5] Mask captured error status as an PERI_ERR1 event for
27442                                          *   PERIERR_STAT1                                                             */
27443             __IOM uint32_t E1_MK6 : 1;  /*!< [6..6] Mask captured error status as an PERI_ERR1 event for
27444                                          *   PERIERR_STAT1                                                             */
27445             __IOM uint32_t E1_MK7 : 1;  /*!< [7..7] Mask captured error status as an PERI_ERR1 event for
27446                                          *   PERIERR_STAT1                                                             */
27447             __IOM uint32_t E1_MK8 : 1;  /*!< [8..8] Mask captured error status as an PERI_ERR1 event for
27448                                          *   PERIERR_STAT1                                                             */
27449             __IOM uint32_t E1_MK9 : 1;  /*!< [9..9] Mask captured error status as an PERI_ERR1 event for
27450                                          *   PERIERR_STAT1                                                             */
27451             uint32_t               : 3;
27452             __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for
27453                                          *   PERIERR_STAT1                                                             */
27454             uint32_t               : 1;
27455             __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for
27456                                          *   PERIERR_STAT1                                                             */
27457             __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for
27458                                          *   PERIERR_STAT1                                                             */
27459             __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for
27460                                          *   PERIERR_STAT1                                                             */
27461             __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for
27462                                          *   PERIERR_STAT1                                                             */
27463             __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for
27464                                          *   PERIERR_STAT1                                                             */
27465             __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for
27466                                          *   PERIERR_STAT1                                                             */
27467             __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for
27468                                          *   PERIERR_STAT1                                                             */
27469             __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for
27470                                          *   PERIERR_STAT1                                                             */
27471             __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for
27472                                          *   PERIERR_STAT1                                                             */
27473             __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for
27474                                          *   PERIERR_STAT1                                                             */
27475             uint32_t               : 2;
27476             __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for
27477                                          *   PERIERR_STAT1                                                             */
27478             __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for
27479                                          *   PERIERR_STAT1                                                             */
27480             uint32_t : 3;
27481         } PERIERR_E1MSK1_b;
27482     };
27483 } R_ICU_Type;                           /*!< Size = 272 (0x110)                                                        */
27484 
27485 /* =========================================================================================================================== */
27486 /* ================                                         R_SYSC_S                                          ================ */
27487 /* =========================================================================================================================== */
27488 
27489 /**
27490  * @brief Register Write Protection for Safety Area (R_SYSC_S)
27491  */
27492 
27493 typedef struct                         /*!< (@ 0x81280000) R_SYSC_S Structure                                         */
27494 {
27495     __IM uint32_t RESERVED;
27496 
27497     union
27498     {
27499         __IOM uint32_t SCKCR2;               /*!< (@ 0x00000004) System Clock Control Register 2                            */
27500 
27501         struct
27502         {
27503             __IOM uint32_t FSELCPU0 : 1;     /*!< [0..0] Set the frequency of the clock provided to Coretex-R52
27504                                               *   CPU0 in combination with bit 5 (DIVSELSUB). The combination
27505                                               *   is shown below.                                                           */
27506             uint32_t                    : 4;
27507             __IOM uint32_t DIVSELSUB    : 1; /*!< [5..5] Select the base clock frequency for peripheral module.             */
27508             uint32_t                    : 18;
27509             __IOM uint32_t SPI3ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock
27510                                               *   is selected in SPI3                                                       */
27511             __IOM uint32_t SCI5ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock
27512                                               *   is selected in SCI5                                                       */
27513             uint32_t : 6;
27514         } SCKCR2_b;
27515     };
27516     __IM uint32_t RESERVED1[6];
27517 
27518     union
27519     {
27520         __IM uint32_t PLL0MON;         /*!< (@ 0x00000020) PLL0 Monitor Register                                      */
27521 
27522         struct
27523         {
27524             __IM uint32_t PLL0MON : 1; /*!< [0..0] PLL0 Lock State Monitor                                            */
27525             uint32_t              : 31;
27526         } PLL0MON_b;
27527     };
27528     __IM uint32_t RESERVED2[7];
27529 
27530     union
27531     {
27532         __IM uint32_t PLL1MON;         /*!< (@ 0x00000040) PLL1 Monitor Register                                      */
27533 
27534         struct
27535         {
27536             __IM uint32_t PLL1MON : 1; /*!< [0..0] PLL1 Lock State Monitor                                            */
27537             uint32_t              : 31;
27538         } PLL1MON_b;
27539     };
27540     __IM uint32_t RESERVED3[3];
27541 
27542     union
27543     {
27544         __IOM uint32_t PLL1EN;         /*!< (@ 0x00000050) PLL1 Enable Register                                       */
27545 
27546         struct
27547         {
27548             __IOM uint32_t PLL1EN : 1; /*!< [0..0] PLL1 Enable                                                        */
27549             uint32_t              : 31;
27550         } PLL1EN_b;
27551     };
27552     __IM uint32_t RESERVED4[7];
27553 
27554     union
27555     {
27556         __IOM uint32_t LOCOCR;         /*!< (@ 0x00000070) Low-Speed On-Chip Oscillator Control Register              */
27557 
27558         struct
27559         {
27560             __IOM uint32_t LCSTP : 1;  /*!< [0..0] LOCO Stop                                                          */
27561             uint32_t             : 31;
27562         } LOCOCR_b;
27563     };
27564     __IM uint32_t RESERVED5[3];
27565 
27566     union
27567     {
27568         __IOM uint32_t HIZCTRLEN;         /*!< (@ 0x00000080) High-Impedance Control Enable Register                     */
27569 
27570         struct
27571         {
27572             __IOM uint32_t CLMA3MASK : 1; /*!< [0..0] CLMA3 error mask to POE3 and POEG                                  */
27573             __IOM uint32_t CLMA0MASK : 1; /*!< [1..1] CLMA0 error mask to POE3 and POEG                                  */
27574             __IOM uint32_t CLMA1MASK : 1; /*!< [2..2] CLMA1 error mask to POE3 and POEG                                  */
27575             uint32_t                 : 29;
27576         } HIZCTRLEN_b;
27577     };
27578     __IM uint32_t RESERVED6[99];
27579 
27580     union
27581     {
27582         __OM uint32_t SWRSYS;          /*!< (@ 0x00000210) System Software Reset Register                             */
27583 
27584         struct
27585         {
27586             __OM uint32_t SWR : 32;    /*!< [31..0] System Software Reset                                             */
27587         } SWRSYS_b;
27588     };
27589     __IM uint32_t RESERVED7[3];
27590 
27591     union
27592     {
27593         __IOM uint32_t SWRCPU0;        /*!< (@ 0x00000220) CPU0 Software Reset Register                               */
27594 
27595         struct
27596         {
27597             __IOM uint32_t SWR : 32;   /*!< [31..0] CPU0 Software Reset                                               */
27598         } SWRCPU0_b;
27599     };
27600     __IM uint32_t RESERVED8[15];
27601 
27602     union
27603     {
27604         __IOM uint32_t MRCTLI;           /*!< (@ 0x00000260) Module Reset Control Register I                            */
27605 
27606         struct
27607         {
27608             __IOM uint32_t MRCTLI00 : 1; /*!< [0..0] PHOSTIF Reset Control                                              */
27609             __IOM uint32_t MRCTLI01 : 1; /*!< [1..1] SHOSTIF (Master bus clock domain) Reset Control                    */
27610             __IOM uint32_t MRCTLI02 : 1; /*!< [2..2] SHOSTIF (Slave bus clock domain) Reset Control                     */
27611             __IOM uint32_t MRCTLI03 : 1; /*!< [3..3] SHOSTIF (IP clock domain) Reset Control                            */
27612             uint32_t                : 28;
27613         } MRCTLI_b;
27614     };
27615     __IM uint32_t RESERVED9[44];
27616 
27617     union
27618     {
27619         __IOM uint32_t MSTPCRF;           /*!< (@ 0x00000314) Module Stop Control Register F                             */
27620 
27621         struct
27622         {
27623             __IOM uint32_t MSTPCRF00 : 1; /*!< [0..0] Trace Clock for Debugging Interface Module Stop                    */
27624             uint32_t                 : 31;
27625         } MSTPCRF_b;
27626     };
27627 
27628     union
27629     {
27630         __IOM uint32_t MSTPCRG;           /*!< (@ 0x00000318) Module Stop Control Register G                             */
27631 
27632         struct
27633         {
27634             __IOM uint32_t MSTPCRG00 : 1; /*!< [0..0] SCI Unit 5 Module Stop                                             */
27635             __IOM uint32_t MSTPCRG01 : 1; /*!< [1..1] IIC Unit 2 Module Stop                                             */
27636             __IOM uint32_t MSTPCRG02 : 1; /*!< [2..2] SPI Unit 3 Module Stop                                             */
27637             __IOM uint32_t MSTPCRG03 : 1; /*!< [3..3] GPT Unit 2 Module Stop                                             */
27638             __IOM uint32_t MSTPCRG04 : 1; /*!< [4..4] CRC Unit 1 Module Stop                                             */
27639             __IOM uint32_t MSTPCRG05 : 1; /*!< [5..5] RTC Module Stop                                                    */
27640             uint32_t                 : 2;
27641             __IOM uint32_t MSTPCRG08 : 1; /*!< [8..8] CLMA3 Module Stop                                                  */
27642             __IOM uint32_t MSTPCRG09 : 1; /*!< [9..9] CLMA0 Module Stop                                                  */
27643             __IOM uint32_t MSTPCRG10 : 1; /*!< [10..10] CLMA1 Module Stop                                                */
27644             __IOM uint32_t MSTPCRG11 : 1; /*!< [11..11] CLMA2 Module Stop                                                */
27645             uint32_t                 : 20;
27646         } MSTPCRG_b;
27647     };
27648     __IM uint32_t RESERVED10;
27649 
27650     union
27651     {
27652         __IOM uint32_t MSTPCRI;           /*!< (@ 0x00000320) Module Stop Control Register I                             */
27653 
27654         struct
27655         {
27656             __IOM uint32_t MSTPCRI00 : 1; /*!< [0..0] PHOSTIF Module Stop                                                */
27657             __IOM uint32_t MSTPCRI01 : 1; /*!< [1..1] SHOSTIF Module Stop                                                */
27658             uint32_t                 : 30;
27659         } MSTPCRI_b;
27660     };
27661 } R_SYSC_S_Type;                          /*!< Size = 804 (0x324)                                                        */
27662 
27663 /* =========================================================================================================================== */
27664 /* ================                                          R_CLMA0                                          ================ */
27665 /* =========================================================================================================================== */
27666 
27667 /**
27668  * @brief Clock Monitor Circuit 0 (R_CLMA0)
27669  */
27670 
27671 typedef struct                         /*!< (@ 0x81280800) R_CLMA0 Structure                                          */
27672 {
27673     union
27674     {
27675         __IOM uint8_t CTL0;            /*!< (@ 0x00000000) CLMA Control Register 0                                    */
27676 
27677         struct
27678         {
27679             __IOM uint8_t CLME : 1;    /*!< [0..0] Clock Monitor m Enable (m = 0 to 3)                                */
27680             uint8_t            : 7;
27681         } CTL0_b;
27682     };
27683     __IM uint8_t  RESERVED;
27684     __IM uint16_t RESERVED1[3];
27685 
27686     union
27687     {
27688         __IOM uint16_t CMPL;           /*!< (@ 0x00000008) CLMA Compare Register L                                    */
27689 
27690         struct
27691         {
27692             __IOM uint16_t CMPL : 12;  /*!< [11..0] Clock Monitor m Compare L (m = 0 to 3)                            */
27693             uint16_t            : 4;
27694         } CMPL_b;
27695     };
27696     __IM uint16_t RESERVED2;
27697 
27698     union
27699     {
27700         __IOM uint16_t CMPH;           /*!< (@ 0x0000000C) CLMA Compare Register H                                    */
27701 
27702         struct
27703         {
27704             __IOM uint16_t CMPH : 12;  /*!< [11..0] Clock Monitor m Compare H (m = 0 to 3)                            */
27705             uint16_t            : 4;
27706         } CMPH_b;
27707     };
27708     __IM uint16_t RESERVED3;
27709     __OM uint8_t  PCMD;                /*!< (@ 0x00000010) CLMA Command Register                                      */
27710     __IM uint8_t  RESERVED4;
27711     __IM uint16_t RESERVED5;
27712 
27713     union
27714     {
27715         __IM uint8_t PROTSR;           /*!< (@ 0x00000014) CLMA Protection Status Register                            */
27716 
27717         struct
27718         {
27719             __IM uint8_t PRERR : 1;    /*!< [0..0] CLMAm Error (m = 0 to 3)                                           */
27720             uint8_t            : 7;
27721         } PROTSR_b;
27722     };
27723     __IM uint8_t  RESERVED6;
27724     __IM uint16_t RESERVED7;
27725 } R_CLMA0_Type;                        /*!< Size = 24 (0x18)                                                          */
27726 
27727 /* =========================================================================================================================== */
27728 /* ================                                          R_MPU0                                           ================ */
27729 /* =========================================================================================================================== */
27730 
27731 /**
27732  * @brief Master MPU 0 (R_MPU0)
27733  */
27734 
27735 typedef struct                           /*!< (@ 0x81281100) R_MPU0 Structure                                           */
27736 {
27737     __IOM R_MPU0_RGN_Type RGN[8];        /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register
27738                                           *                  [0..7]                                                     */
27739 
27740     union
27741     {
27742         __IOM uint32_t ERRINF_R;         /*!< (@ 0x00000080) Master MPU Error Information Register for AXI
27743                                           *                  type                                                       */
27744 
27745         struct
27746         {
27747             __IOM uint32_t VALID   : 1;  /*!< [0..0] Validity of access error information                               */
27748             __IM uint32_t  RW      : 1;  /*!< [1..1] Access error type                                                  */
27749             __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access error address                                              */
27750         } ERRINF_R_b;
27751     };
27752 
27753     union
27754     {
27755         __IOM uint32_t ERRINF_W;         /*!< (@ 0x00000084) Master MPU Error Information Register for AXI
27756                                           *                  type                                                       */
27757 
27758         struct
27759         {
27760             __IOM uint32_t VALID   : 1;  /*!< [0..0] Validity of access error information                               */
27761             __IM uint32_t  RW      : 1;  /*!< [1..1] Access error type                                                  */
27762             __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access error address                                              */
27763         } ERRINF_W_b;
27764     };
27765 } R_MPU0_Type;                           /*!< Size = 136 (0x88)                                                         */
27766 
27767 /* =========================================================================================================================== */
27768 /* ================                                          R_MPU3                                           ================ */
27769 /* =========================================================================================================================== */
27770 
27771 /**
27772  * @brief Master MPU 3 (R_MPU3)
27773  */
27774 
27775 typedef struct                           /*!< (@ 0x81281400) R_MPU3 Structure                                           */
27776 {
27777     __IOM R_MPU0_RGN_Type RGN[8];        /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register
27778                                           *                  [0..7]                                                     */
27779 
27780     union
27781     {
27782         __IOM uint32_t ERRINF;           /*!< (@ 0x00000080) Master MPU Error Information Register for AHB
27783                                           *                  type                                                       */
27784 
27785         struct
27786         {
27787             __IOM uint32_t VALID   : 1;  /*!< [0..0] Validity of Access Error Information                               */
27788             __IM uint32_t  RW      : 1;  /*!< [1..1] Access error type                                                  */
27789             __IM uint32_t  ERRADDR : 30; /*!< [31..2] Access Error Address                                              */
27790         } ERRINF_b;
27791     };
27792 } R_MPU3_Type;                           /*!< Size = 132 (0x84)                                                         */
27793 
27794 /* =========================================================================================================================== */
27795 /* ================                                       R_SYSRAM_CTL                                        ================ */
27796 /* =========================================================================================================================== */
27797 
27798 /**
27799  * @brief System SRAM Control (R_SYSRAM_CTL)
27800  */
27801 
27802 typedef struct                              /*!< (@ 0x81281800) R_SYSRAM_CTL Structure                                     */
27803 {
27804     union
27805     {
27806         __IOM uint32_t SYSRAM_CTRL0;        /*!< (@ 0x00000000) System SRAM Control Register 0                             */
27807 
27808         struct
27809         {
27810             __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
27811             uint32_t                   : 15;
27812             __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
27813             __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
27814             __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
27815             uint32_t                   : 2;
27816             __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
27817             uint32_t                   : 7;
27818         } SYSRAM_CTRL0_b;
27819     };
27820     __IM uint32_t RESERVED[3];
27821 
27822     union
27823     {
27824         __IOM uint32_t SYSRAM_CTRL1;        /*!< (@ 0x00000010) System SRAM Control Register 1                             */
27825 
27826         struct
27827         {
27828             __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
27829             uint32_t                   : 15;
27830             __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
27831             __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
27832             __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
27833             uint32_t                   : 2;
27834             __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
27835             uint32_t                   : 7;
27836         } SYSRAM_CTRL1_b;
27837     };
27838     __IM uint32_t RESERVED1[3];
27839 
27840     union
27841     {
27842         __IOM uint32_t SYSRAM_CTRL2;        /*!< (@ 0x00000020) System SRAM Control Register 2                             */
27843 
27844         struct
27845         {
27846             __IOM uint32_t VECEN       : 1; /*!< [0..0] Enables or disables error correction with ECC                      */
27847             uint32_t                   : 15;
27848             __IOM uint32_t VRWEN       : 4; /*!< [19..16] Enables write for each page of RAM                               */
27849             __IOM uint32_t VCEN        : 1; /*!< [20..20] Enables access to RAM                                            */
27850             __IOM uint32_t VLWEN       : 1; /*!< [21..21] Enables write for RAM                                            */
27851             uint32_t                   : 2;
27852             __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors                */
27853             uint32_t                   : 7;
27854         } SYSRAM_CTRL2_b;
27855     };
27856 } R_SYSRAM_CTL_Type;                        /*!< Size = 36 (0x24)                                                          */
27857 
27858 /* =========================================================================================================================== */
27859 /* ================                                       R_SHOSTIF_CFG                                       ================ */
27860 /* =========================================================================================================================== */
27861 
27862 /**
27863  * @brief Serial Host Interface Configuration (R_SHOSTIF_CFG)
27864  */
27865 
27866 typedef struct                             /*!< (@ 0x81281920) R_SHOSTIF_CFG Structure                                    */
27867 {
27868     union
27869     {
27870         __IOM uint32_t SHCFG;              /*!< (@ 0x00000000) SHOSTIF Configuration Register                             */
27871 
27872         struct
27873         {
27874             __IOM uint32_t SPIMODE    : 2; /*!< [1..0] SPI Frame Format Select                                            */
27875             __IOM uint32_t BYTESWAP   : 1; /*!< [2..2] Byte Swap Mode                                                     */
27876             __IOM uint32_t ADDRESSING : 1; /*!< [3..3] Addressing Mode                                                    */
27877             __IM uint32_t  SLEEP      : 1; /*!< [4..4] SHOSTIF Enable Flag Monitor                                        */
27878             uint32_t                  : 11;
27879             __IOM uint32_t INTMASKI   : 6; /*!< [21..16] Interrupt Mask Enable for Internal Interrupt (SHOST_INT)         */
27880             uint32_t                  : 2;
27881             __IOM uint32_t INTMASKE   : 6; /*!< [29..24] Interrupt Mask Enable for External Interrupt (HSPI_INT#
27882                                             *   signal)                                                                   */
27883             uint32_t : 2;
27884         } SHCFG_b;
27885     };
27886 } R_SHOSTIF_CFG_Type;                      /*!< Size = 4 (0x4)                                                            */
27887 
27888 /* =========================================================================================================================== */
27889 /* ================                                       R_PHOSTIF_CFG                                       ================ */
27890 /* =========================================================================================================================== */
27891 
27892 /**
27893  * @brief Parallel Host Interface Configuration (R_PHOSTIF_CFG)
27894  */
27895 
27896 typedef struct                            /*!< (@ 0x81281930) R_PHOSTIF_CFG Structure                                    */
27897 {
27898     union
27899     {
27900         __IOM uint32_t PHCFG;             /*!< (@ 0x00000000) PHOSTIF Configureation Register                            */
27901 
27902         struct
27903         {
27904             __IOM uint32_t MEMIFSEL  : 1; /*!< [0..0] MEMIFSEL                                                           */
27905             uint32_t                 : 3;
27906             __IOM uint32_t BUSSSEL   : 1; /*!< [4..4] BUSSSEL                                                            */
27907             uint32_t                 : 3;
27908             __IOM uint32_t HIFSYNC   : 1; /*!< [8..8] HIFSYNC                                                            */
27909             uint32_t                 : 3;
27910             __IOM uint32_t MEMCSEL   : 1; /*!< [12..12] MEMCSEL                                                          */
27911             uint32_t                 : 3;
27912             __IOM uint32_t HWRZSEL   : 1; /*!< [16..16] HWRZSEL                                                          */
27913             uint32_t                 : 3;
27914             __IOM uint32_t ADMUXMODE : 1; /*!< [20..20] ADMUXMODE                                                        */
27915             uint32_t                 : 11;
27916         } PHCFG_b;
27917     };
27918 
27919     union
27920     {
27921         __IOM uint32_t PHACC;              /*!< (@ 0x00000004) PHOSTIF Register Access Control Register                   */
27922 
27923         struct
27924         {
27925             __IOM uint32_t HIFRDYSEL  : 1; /*!< [0..0] HIFRDYSEL                                                          */
27926             uint32_t                  : 7;
27927             __IOM uint32_t HIFBCCSEL  : 1; /*!< [8..8] HIFBCCSEL                                                          */
27928             __IOM uint32_t HIFBTCSEL  : 1; /*!< [9..9] HIFBTCSEL                                                          */
27929             __IOM uint32_t HIFPRCSEL  : 1; /*!< [10..10] HIFPRCSEL                                                        */
27930             __IOM uint32_t HIFIRCSEL  : 1; /*!< [11..11] HIFIRCSEL                                                        */
27931             __IOM uint32_t HIFXALSEL  : 1; /*!< [12..12] HIFXALSEL                                                        */
27932             __IOM uint32_t HIFXAHSEL  : 1; /*!< [13..13] HIFXAHSEL                                                        */
27933             __IOM uint32_t HIFEXT0SEL : 1; /*!< [14..14] HIFEXT0SEL                                                       */
27934             __IOM uint32_t HIFEXT1SEL : 1; /*!< [15..15] HIFEXT1SEL                                                       */
27935             __IOM uint32_t CSSWAP     : 1; /*!< [16..16] CSSWAP                                                           */
27936             __IOM uint32_t BSCADMUX   : 1; /*!< [17..17] BSCADMUX                                                         */
27937             uint32_t                  : 14;
27938         } PHACC_b;
27939     };
27940 } R_PHOSTIF_CFG_Type;                      /*!< Size = 8 (0x8)                                                            */
27941 
27942 /* =========================================================================================================================== */
27943 /* ================                                          R_RWP_S                                          ================ */
27944 /* =========================================================================================================================== */
27945 
27946 /**
27947  * @brief Register Write Protection for Safety Area (R_RWP_S)
27948  */
27949 
27950 typedef struct                         /*!< (@ 0x81281A00) R_RWP_S Structure                                          */
27951 {
27952     union
27953     {
27954         __IOM uint32_t PRCRS;          /*!< (@ 0x00000000) Safety Area Protect Register                               */
27955 
27956         struct
27957         {
27958             __IOM uint32_t PRC0 : 1;   /*!< [0..0] Protect 0                                                          */
27959             __IOM uint32_t PRC1 : 1;   /*!< [1..1] Protect 1                                                          */
27960             __IOM uint32_t PRC2 : 1;   /*!< [2..2] Protect 2                                                          */
27961             __IOM uint32_t PRC3 : 1;   /*!< [3..3] Protect 3                                                          */
27962             uint32_t            : 4;
27963             __OM uint32_t PRKEY : 8;   /*!< [15..8] PRC Key Code                                                      */
27964             uint32_t            : 16;
27965         } PRCRS_b;
27966     };
27967 } R_RWP_S_Type;                        /*!< Size = 4 (0x4)                                                            */
27968 
27969 /* =========================================================================================================================== */
27970 /* ================                                           R_MTU                                           ================ */
27971 /* =========================================================================================================================== */
27972 
27973 /**
27974  * @brief Multi-Function Timer Pulse Unit (R_MTU)
27975  */
27976 
27977 typedef struct                         /*!< (@ 0x90001000) R_MTU Structure                                            */
27978 {
27979     __IM uint16_t RESERVED[261];
27980 
27981     union
27982     {
27983         __IOM uint8_t TOERA;           /*!< (@ 0x0000020A) Timer Output Master Enable Register A                      */
27984 
27985         struct
27986         {
27987             __IOM uint8_t OE3B : 1;    /*!< [0..0] Master Enable MTIOC3B                                              */
27988             __IOM uint8_t OE4A : 1;    /*!< [1..1] Master Enable MTIOC4A                                              */
27989             __IOM uint8_t OE4B : 1;    /*!< [2..2] Master Enable MTIOC4B                                              */
27990             __IOM uint8_t OE3D : 1;    /*!< [3..3] Master Enable MTIOC3D                                              */
27991             __IOM uint8_t OE4C : 1;    /*!< [4..4] Master Enable MTIOC4C                                              */
27992             __IOM uint8_t OE4D : 1;    /*!< [5..5] Master Enable MTIOC4D                                              */
27993             uint8_t            : 2;
27994         } TOERA_b;
27995     };
27996     __IM uint8_t RESERVED1[2];
27997 
27998     union
27999     {
28000         __IOM uint8_t TGCRA;           /*!< (@ 0x0000020D) Timer Gate Control Register A                              */
28001 
28002         struct
28003         {
28004             __IOM uint8_t UF  : 1;     /*!< [0..0] Output Phase Switch                                                */
28005             __IOM uint8_t VF  : 1;     /*!< [1..1] Output Phase Switch                                                */
28006             __IOM uint8_t WF  : 1;     /*!< [2..2] Output Phase Switch                                                */
28007             __IOM uint8_t FB  : 1;     /*!< [3..3] External Feedback Signal Enable                                    */
28008             __IOM uint8_t P   : 1;     /*!< [4..4] Positive-Phase Output (P) Control                                  */
28009             __IOM uint8_t N   : 1;     /*!< [5..5] Negative-Phase Output (N) Control                                  */
28010             __IOM uint8_t BDC : 1;     /*!< [6..6] Brushless DC Motor                                                 */
28011             uint8_t           : 1;
28012         } TGCRA_b;
28013     };
28014 
28015     union
28016     {
28017         __IOM uint8_t TOCR1A;          /*!< (@ 0x0000020E) Timer Output Control Register 1A                           */
28018 
28019         struct
28020         {
28021             __IOM uint8_t OLSP : 1;    /*!< [0..0] Output Level Select P                                              */
28022             __IOM uint8_t OLSN : 1;    /*!< [1..1] Output Level Select N                                              */
28023             __IOM uint8_t TOCS : 1;    /*!< [2..2] TOC Select                                                         */
28024             __IOM uint8_t TOCL : 1;    /*!< [3..3] TOC Register Write Protection                                      */
28025             uint8_t            : 2;
28026             __IOM uint8_t PSYE : 1;    /*!< [6..6] PWM Synchronous Output Enable                                      */
28027             uint8_t            : 1;
28028         } TOCR1A_b;
28029     };
28030 
28031     union
28032     {
28033         __IOM uint8_t TOCR2A;          /*!< (@ 0x0000020F) Timer Output Control Register 2A                           */
28034 
28035         struct
28036         {
28037             __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
28038             __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
28039             __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
28040             __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
28041             __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
28042             __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
28043             __IOM uint8_t BF    : 2;   /*!< [7..6] TOLBR Buffer Transfer Timing Select                                */
28044         } TOCR2A_b;
28045     };
28046     __IM uint16_t  RESERVED2[2];
28047     __IOM uint16_t TCDRA;              /*!< (@ 0x00000214) Timer Cycle Data Register A                                */
28048     __IOM uint16_t TDDRA;              /*!< (@ 0x00000216) Timer Dead Time Data Register A                            */
28049     __IM uint16_t  RESERVED3[4];
28050     __IM uint16_t  TCNTSA;             /*!< (@ 0x00000220) Timer Subcounter A                                         */
28051     __IOM uint16_t TCBRA;              /*!< (@ 0x00000222) Timer Cycle Buffer Register A                              */
28052     __IM uint16_t  RESERVED4[6];
28053 
28054     union
28055     {
28056         __IOM uint8_t TITCR1A;         /*!< (@ 0x00000230) Timer Interrupt Skipping Set Register 1A                   */
28057 
28058         struct
28059         {
28060             __IOM uint8_t T4VCOR : 3;  /*!< [2..0] TCIV4 Interrupt Skipping Count Setting                             */
28061             __IOM uint8_t T4VEN  : 1;  /*!< [3..3] TCIV4 Interrupt Skipping Enable                                    */
28062             __IOM uint8_t T3ACOR : 3;  /*!< [6..4] TGIA3 Interrupt Skipping Count Setting                             */
28063             __IOM uint8_t T3AEN  : 1;  /*!< [7..7] TGIA3 Interrupt Skipping Enable                                    */
28064         } TITCR1A_b;
28065     };
28066 
28067     union
28068     {
28069         __IM uint8_t TITCNT1A;         /*!< (@ 0x00000231) Timer Interrupt Skipping Counter 1A                        */
28070 
28071         struct
28072         {
28073             __IM uint8_t T4VCNT : 3;   /*!< [2..0] TCIV4 Interrupt Counter                                            */
28074             uint8_t             : 1;
28075             __IM uint8_t T3ACNT : 3;   /*!< [6..4] TGIA3 Interrupt Counter                                            */
28076             uint8_t             : 1;
28077         } TITCNT1A_b;
28078     };
28079 
28080     union
28081     {
28082         __IOM uint8_t TBTERA;          /*!< (@ 0x00000232) Timer Buffer Transfer Set Register A                       */
28083 
28084         struct
28085         {
28086             __IOM uint8_t BTE : 2;     /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting        */
28087             uint8_t           : 6;
28088         } TBTERA_b;
28089     };
28090     __IM uint8_t RESERVED5;
28091 
28092     union
28093     {
28094         __IOM uint8_t TDERA;           /*!< (@ 0x00000234) Timer Dead Time Enable Register A                          */
28095 
28096         struct
28097         {
28098             __IOM uint8_t TDER : 1;    /*!< [0..0] Dead Time Enable                                                   */
28099             uint8_t            : 7;
28100         } TDERA_b;
28101     };
28102     __IM uint8_t RESERVED6;
28103 
28104     union
28105     {
28106         __IOM uint8_t TOLBRA;          /*!< (@ 0x00000236) Timer Output Level Buffer Register A                       */
28107 
28108         struct
28109         {
28110             __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
28111             __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
28112             __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
28113             __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
28114             __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
28115             __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
28116             uint8_t             : 2;
28117         } TOLBRA_b;
28118     };
28119     __IM uint8_t  RESERVED7;
28120     __IM uint16_t RESERVED8;
28121 
28122     union
28123     {
28124         __IOM uint8_t TITMRA;          /*!< (@ 0x0000023A) Timer Interrupt Skipping Mode Register A                   */
28125 
28126         struct
28127         {
28128             __IOM uint8_t TITM : 1;    /*!< [0..0] Interrupt Skipping Function Select                                 */
28129             uint8_t            : 7;
28130         } TITMRA_b;
28131     };
28132 
28133     union
28134     {
28135         __IOM uint8_t TITCR2A;         /*!< (@ 0x0000023B) Timer Interrupt Skipping Set Register 2A                   */
28136 
28137         struct
28138         {
28139             __IOM uint8_t TRG4COR : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Skipping Count Setting                     */
28140             uint8_t               : 5;
28141         } TITCR2A_b;
28142     };
28143 
28144     union
28145     {
28146         __IM uint8_t TITCNT2A;         /*!< (@ 0x0000023C) Timer Interrupt Skipping Counter 2A                        */
28147 
28148         struct
28149         {
28150             __IM uint8_t TRG4CNT : 3;  /*!< [2..0] TRG4AN/TRG4BN Interrupt Counter                                    */
28151             uint8_t              : 5;
28152         } TITCNT2A_b;
28153     };
28154     __IM uint8_t  RESERVED9;
28155     __IM uint16_t RESERVED10[17];
28156 
28157     union
28158     {
28159         __IOM uint8_t TWCRA;           /*!< (@ 0x00000260) Timer Waveform Control Register A                          */
28160 
28161         struct
28162         {
28163             __IOM uint8_t WRE : 1;     /*!< [0..0] Waveform Retain Enable                                             */
28164             __IOM uint8_t SCC : 1;     /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB)                 */
28165             uint8_t           : 5;
28166             __IOM uint8_t CCE : 1;     /*!< [7..7] Compare Match Clear Enable                                         */
28167         } TWCRA_b;
28168     };
28169     __IM uint8_t  RESERVED11;
28170     __IM uint16_t RESERVED12[7];
28171 
28172     union
28173     {
28174         __IOM uint8_t TMDR2A;          /*!< (@ 0x00000270) Timer Mode Register 2A                                     */
28175 
28176         struct
28177         {
28178             __IOM uint8_t DRS : 1;     /*!< [0..0] Double Buffer Select                                               */
28179             uint8_t           : 7;
28180         } TMDR2A_b;
28181     };
28182     __IM uint8_t  RESERVED13;
28183     __IM uint16_t RESERVED14[7];
28184 
28185     union
28186     {
28187         __IOM uint8_t TSTRA;           /*!< (@ 0x00000280) Timer Start Register A                                     */
28188 
28189         struct
28190         {
28191             __IOM uint8_t CST0 : 1;    /*!< [0..0] Counter Start 0                                                    */
28192             __IOM uint8_t CST1 : 1;    /*!< [1..1] Counter Start 1                                                    */
28193             __IOM uint8_t CST2 : 1;    /*!< [2..2] Counter Start 2                                                    */
28194             __IOM uint8_t CST8 : 1;    /*!< [3..3] Counter Start 8                                                    */
28195             uint8_t            : 2;
28196             __IOM uint8_t CST3 : 1;    /*!< [6..6] Counter Start 3                                                    */
28197             __IOM uint8_t CST4 : 1;    /*!< [7..7] Counter Start 4                                                    */
28198         } TSTRA_b;
28199     };
28200 
28201     union
28202     {
28203         __IOM uint8_t TSYRA;           /*!< (@ 0x00000281) Timer Synchronous Register A                               */
28204 
28205         struct
28206         {
28207             __IOM uint8_t SYNC0 : 1;   /*!< [0..0] Timer Synchronous Operation 0                                      */
28208             __IOM uint8_t SYNC1 : 1;   /*!< [1..1] Timer Synchronous Operation 1                                      */
28209             __IOM uint8_t SYNC2 : 1;   /*!< [2..2] Timer Synchronous Operation 2                                      */
28210             uint8_t             : 3;
28211             __IOM uint8_t SYNC3 : 1;   /*!< [6..6] Timer Synchronous Operation 3                                      */
28212             __IOM uint8_t SYNC4 : 1;   /*!< [7..7] Timer Synchronous Operation 4                                      */
28213         } TSYRA_b;
28214     };
28215 
28216     union
28217     {
28218         __IOM uint8_t TCSYSTR;         /*!< (@ 0x00000282) Timer Counter Synchronous Start Register                   */
28219 
28220         struct
28221         {
28222             __IOM uint8_t SCH7 : 1;    /*!< [0..0] Synchronous Start 7                                                */
28223             __IOM uint8_t SCH6 : 1;    /*!< [1..1] Synchronous Start 6                                                */
28224             uint8_t            : 1;
28225             __IOM uint8_t SCH4 : 1;    /*!< [3..3] Synchronous Start 4                                                */
28226             __IOM uint8_t SCH3 : 1;    /*!< [4..4] Synchronous Start 3                                                */
28227             __IOM uint8_t SCH2 : 1;    /*!< [5..5] Synchronous Start 2                                                */
28228             __IOM uint8_t SCH1 : 1;    /*!< [6..6] Synchronous Start 1                                                */
28229             __IOM uint8_t SCH0 : 1;    /*!< [7..7] Synchronous Start 0                                                */
28230         } TCSYSTR_b;
28231     };
28232     __IM uint8_t RESERVED15;
28233 
28234     union
28235     {
28236         __IOM uint8_t TRWERA;          /*!< (@ 0x00000284) Timer Read/Write Enable Register A                         */
28237 
28238         struct
28239         {
28240             __IOM uint8_t RWE : 1;     /*!< [0..0] Read/Write Enable                                                  */
28241             uint8_t           : 7;
28242         } TRWERA_b;
28243     };
28244     __IM uint8_t  RESERVED16;
28245     __IM uint16_t RESERVED17[962];
28246 
28247     union
28248     {
28249         __IOM uint8_t TOERB;           /*!< (@ 0x00000A0A) Timer Output Master Enable Register B                      */
28250 
28251         struct
28252         {
28253             __IOM uint8_t OE6B : 1;    /*!< [0..0] Master Enable MTIOC6B                                              */
28254             __IOM uint8_t OE7A : 1;    /*!< [1..1] Master Enable MTIOC7A                                              */
28255             __IOM uint8_t OE7B : 1;    /*!< [2..2] Master Enable MTIOC7B                                              */
28256             __IOM uint8_t OE6D : 1;    /*!< [3..3] Master Enable MTIOC6D                                              */
28257             __IOM uint8_t OE7C : 1;    /*!< [4..4] Master Enable MTIOC7C                                              */
28258             __IOM uint8_t OE7D : 1;    /*!< [5..5] Master Enable MTIOC7D                                              */
28259             uint8_t            : 2;
28260         } TOERB_b;
28261     };
28262     __IM uint8_t  RESERVED18;
28263     __IM uint16_t RESERVED19;
28264 
28265     union
28266     {
28267         __IOM uint8_t TOCR1B;          /*!< (@ 0x00000A0E) Timer Output Control Register 1B                           */
28268 
28269         struct
28270         {
28271             __IOM uint8_t OLSP : 1;    /*!< [0..0] Output Level Select P                                              */
28272             __IOM uint8_t OLSN : 1;    /*!< [1..1] Output Level Select N                                              */
28273             __IOM uint8_t TOCS : 1;    /*!< [2..2] TOC Select                                                         */
28274             __IOM uint8_t TOCL : 1;    /*!< [3..3] TOC Register Write Protection                                      */
28275             uint8_t            : 2;
28276             __IOM uint8_t PSYE : 1;    /*!< [6..6] PWM Synchronous Output Enable                                      */
28277             uint8_t            : 1;
28278         } TOCR1B_b;
28279     };
28280 
28281     union
28282     {
28283         __IOM uint8_t TOCR2B;          /*!< (@ 0x00000A0F) Timer Output Control Register 2B                           */
28284 
28285         struct
28286         {
28287             __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
28288             __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
28289             __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
28290             __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
28291             __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
28292             __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
28293             __IOM uint8_t BF    : 2;   /*!< [7..6] TOLBR Buffer Transfer Timing Select                                */
28294         } TOCR2B_b;
28295     };
28296     __IM uint16_t  RESERVED20[2];
28297     __IOM uint16_t TCDRB;              /*!< (@ 0x00000A14) Timer Cycle Data Register B                                */
28298     __IOM uint16_t TDDRB;              /*!< (@ 0x00000A16) Timer Dead Time Data Register B                            */
28299     __IM uint16_t  RESERVED21[4];
28300     __IM uint16_t  TCNTSB;             /*!< (@ 0x00000A20) Timer Subcounter B                                         */
28301     __IOM uint16_t TCBRB;              /*!< (@ 0x00000A22) Timer Cycle Buffer Register B                              */
28302     __IM uint16_t  RESERVED22[6];
28303 
28304     union
28305     {
28306         __IOM uint8_t TITCR1B;         /*!< (@ 0x00000A30) Timer Interrupt Skipping Set Register 1B                   */
28307 
28308         struct
28309         {
28310             __IOM uint8_t T7VCOR : 3;  /*!< [2..0] TCIV7 Interrupt Skipping Count Setting                             */
28311             __IOM uint8_t T7VEN  : 1;  /*!< [3..3] TCIV7 Interrupt Skipping Enable                                    */
28312             __IOM uint8_t T6ACOR : 3;  /*!< [6..4] TGIA6 Interrupt Skipping Count Setting                             */
28313             __IOM uint8_t T6AEN  : 1;  /*!< [7..7] TGIA6 Interrupt Skipping Enable                                    */
28314         } TITCR1B_b;
28315     };
28316 
28317     union
28318     {
28319         __IM uint8_t TITCNT1B;         /*!< (@ 0x00000A31) Timer Interrupt Skipping Counter 1B                        */
28320 
28321         struct
28322         {
28323             __IM uint8_t T7VCNT : 3;   /*!< [2..0] TCIV7 Interrupt Counter                                            */
28324             uint8_t             : 1;
28325             __IM uint8_t T6ACNT : 3;   /*!< [6..4] TGIA6 Interrupt Counter                                            */
28326             uint8_t             : 1;
28327         } TITCNT1B_b;
28328     };
28329 
28330     union
28331     {
28332         __IOM uint8_t TBTERB;          /*!< (@ 0x00000A32) Timer Buffer Transfer Set Register B                       */
28333 
28334         struct
28335         {
28336             __IOM uint8_t BTE : 2;     /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting        */
28337             uint8_t           : 6;
28338         } TBTERB_b;
28339     };
28340     __IM uint8_t RESERVED23;
28341 
28342     union
28343     {
28344         __IOM uint8_t TDERB;           /*!< (@ 0x00000A34) Timer Dead Time Enable Register B                          */
28345 
28346         struct
28347         {
28348             __IOM uint8_t TDER : 1;    /*!< [0..0] Dead Time Enable                                                   */
28349             uint8_t            : 7;
28350         } TDERB_b;
28351     };
28352     __IM uint8_t RESERVED24;
28353 
28354     union
28355     {
28356         __IOM uint8_t TOLBRB;          /*!< (@ 0x00000A36) Timer Output Level Buffer Register B                       */
28357 
28358         struct
28359         {
28360             __IOM uint8_t OLS1P : 1;   /*!< [0..0] Output Level Select 1P                                             */
28361             __IOM uint8_t OLS1N : 1;   /*!< [1..1] Output Level Select 1N                                             */
28362             __IOM uint8_t OLS2P : 1;   /*!< [2..2] Output Level Select 2P                                             */
28363             __IOM uint8_t OLS2N : 1;   /*!< [3..3] Output Level Select 2N                                             */
28364             __IOM uint8_t OLS3P : 1;   /*!< [4..4] Output Level Select 3P                                             */
28365             __IOM uint8_t OLS3N : 1;   /*!< [5..5] Output Level Select 3N                                             */
28366             uint8_t             : 2;
28367         } TOLBRB_b;
28368     };
28369     __IM uint8_t  RESERVED25;
28370     __IM uint16_t RESERVED26;
28371 
28372     union
28373     {
28374         __IOM uint8_t TITMRB;          /*!< (@ 0x00000A3A) Timer Interrupt Skipping Mode Register B                   */
28375 
28376         struct
28377         {
28378             __IOM uint8_t TITM : 1;    /*!< [0..0] Interrupt Skipping Function Select                                 */
28379             uint8_t            : 7;
28380         } TITMRB_b;
28381     };
28382 
28383     union
28384     {
28385         __IOM uint8_t TITCR2B;         /*!< (@ 0x00000A3B) Timer Interrupt Skipping Set Register 2B                   */
28386 
28387         struct
28388         {
28389             __IOM uint8_t TRG7COR : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Skipping Count Setting                     */
28390             uint8_t               : 5;
28391         } TITCR2B_b;
28392     };
28393 
28394     union
28395     {
28396         __IM uint8_t TITCNT2B;         /*!< (@ 0x00000A3C) Timer Interrupt Skipping Counter 2B                        */
28397 
28398         struct
28399         {
28400             __IM uint8_t TRG7CNT : 3;  /*!< [2..0] TRG7AN/TRG7BN Interrupt Counter                                    */
28401             uint8_t              : 5;
28402         } TITCNT2B_b;
28403     };
28404     __IM uint8_t  RESERVED27;
28405     __IM uint16_t RESERVED28[17];
28406 
28407     union
28408     {
28409         __IOM uint8_t TWCRB;           /*!< (@ 0x00000A60) Timer Waveform Control Register B                          */
28410 
28411         struct
28412         {
28413             __IOM uint8_t WRE : 1;     /*!< [0..0] Waveform Retain Enable                                             */
28414             __IOM uint8_t SCC : 1;     /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB)                 */
28415             uint8_t           : 5;
28416             __IOM uint8_t CCE : 1;     /*!< [7..7] Compare Match Clear Enable                                         */
28417         } TWCRB_b;
28418     };
28419     __IM uint8_t  RESERVED29;
28420     __IM uint16_t RESERVED30[7];
28421 
28422     union
28423     {
28424         __IOM uint8_t TMDR2B;          /*!< (@ 0x00000A70) Timer Mode Register 2B                                     */
28425 
28426         struct
28427         {
28428             __IOM uint8_t DRS : 1;     /*!< [0..0] Double Buffer Select                                               */
28429             uint8_t           : 7;
28430         } TMDR2B_b;
28431     };
28432     __IM uint8_t  RESERVED31;
28433     __IM uint16_t RESERVED32[7];
28434 
28435     union
28436     {
28437         __IOM uint8_t TSTRB;           /*!< (@ 0x00000A80) Timer Start Register B                                     */
28438 
28439         struct
28440         {
28441             uint8_t            : 6;
28442             __IOM uint8_t CST6 : 1;    /*!< [6..6] Counter Start 6                                                    */
28443             __IOM uint8_t CST7 : 1;    /*!< [7..7] Counter Start 7                                                    */
28444         } TSTRB_b;
28445     };
28446 
28447     union
28448     {
28449         __IOM uint8_t TSYRB;           /*!< (@ 0x00000A81) Timer Synchronous Register B                               */
28450 
28451         struct
28452         {
28453             uint8_t             : 6;
28454             __IOM uint8_t SYNC6 : 1;   /*!< [6..6] Timer Synchronous Operation 6                                      */
28455             __IOM uint8_t SYNC7 : 1;   /*!< [7..7] Timer Synchronous Operation 7                                      */
28456         } TSYRB_b;
28457     };
28458     __IM uint16_t RESERVED33;
28459 
28460     union
28461     {
28462         __IOM uint8_t TRWERB;          /*!< (@ 0x00000A84) Timer Read/Write Enable Register B                         */
28463 
28464         struct
28465         {
28466             __IOM uint8_t RWE : 1;     /*!< [0..0] Read/Write Enable                                                  */
28467             uint8_t           : 7;
28468         } TRWERB_b;
28469     };
28470     __IM uint8_t  RESERVED34;
28471     __IM uint16_t RESERVED35;
28472 } R_MTU_Type;                          /*!< Size = 2696 (0xa88)                                                       */
28473 
28474 /* =========================================================================================================================== */
28475 /* ================                                          R_MTU3                                           ================ */
28476 /* =========================================================================================================================== */
28477 
28478 /**
28479  * @brief Multi-Function Timer Pulse Unit Channel 3 (R_MTU3)
28480  */
28481 
28482 typedef struct                         /*!< (@ 0x90001100) R_MTU3 Structure                                           */
28483 {
28484     __IM uint16_t RESERVED[128];
28485 
28486     union
28487     {
28488         __IOM uint8_t TCR;             /*!< (@ 0x00000100) Timer Control Register                                     */
28489 
28490         struct
28491         {
28492             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
28493             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
28494             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
28495         } TCR_b;
28496     };
28497     __IM uint8_t RESERVED1;
28498 
28499     union
28500     {
28501         __IOM uint8_t TMDR1;           /*!< (@ 0x00000102) Timer Mode Register 1                                      */
28502 
28503         struct
28504         {
28505             __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
28506             __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
28507             __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
28508             uint8_t           : 2;
28509         } TMDR1_b;
28510     };
28511     __IM uint8_t RESERVED2;
28512 
28513     union
28514     {
28515         __IOM uint8_t TIORH;           /*!< (@ 0x00000104) Timer I/O Control Register H                               */
28516 
28517         struct
28518         {
28519             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
28520             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
28521         } TIORH_b;
28522     };
28523 
28524     union
28525     {
28526         __IOM uint8_t TIORL;           /*!< (@ 0x00000105) Timer I/O Control Register L                               */
28527 
28528         struct
28529         {
28530             __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
28531             __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
28532         } TIORL_b;
28533     };
28534     __IM uint16_t RESERVED3;
28535 
28536     union
28537     {
28538         __IOM uint8_t TIER;            /*!< (@ 0x00000108) Timer Interrupt Enable Register                            */
28539 
28540         struct
28541         {
28542             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
28543             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
28544             __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
28545             __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
28546             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
28547             uint8_t             : 2;
28548             __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
28549         } TIER_b;
28550     };
28551     __IM uint8_t   RESERVED4;
28552     __IM uint16_t  RESERVED5[3];
28553     __IOM uint16_t TCNT;               /*!< (@ 0x00000110) Timer Counter                                              */
28554     __IM uint16_t  RESERVED6[3];
28555     __IOM uint16_t TGRA;               /*!< (@ 0x00000118) Timer General Register A                                   */
28556     __IOM uint16_t TGRB;               /*!< (@ 0x0000011A) Timer General Register B                                   */
28557     __IM uint16_t  RESERVED7[4];
28558     __IOM uint16_t TGRC;               /*!< (@ 0x00000124) Timer General Register C                                   */
28559     __IOM uint16_t TGRD;               /*!< (@ 0x00000126) Timer General Register D                                   */
28560     __IM uint16_t  RESERVED8[2];
28561 
28562     union
28563     {
28564         __IOM uint8_t TSR;             /*!< (@ 0x0000012C) Timer Status Register                                      */
28565 
28566         struct
28567         {
28568             __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
28569             __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
28570             __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
28571             __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
28572             __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
28573             __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
28574             uint8_t            : 1;
28575             __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
28576         } TSR_b;
28577     };
28578     __IM uint8_t  RESERVED9;
28579     __IM uint16_t RESERVED10[5];
28580 
28581     union
28582     {
28583         __IOM uint8_t TBTM;            /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register              */
28584 
28585         struct
28586         {
28587             __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
28588             __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
28589             uint8_t            : 6;
28590         } TBTM_b;
28591     };
28592     __IM uint8_t  RESERVED11;
28593     __IM uint16_t RESERVED12[9];
28594 
28595     union
28596     {
28597         __IOM uint8_t TCR2;            /*!< (@ 0x0000014C) Timer Control Register 2                                   */
28598 
28599         struct
28600         {
28601             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
28602             uint8_t             : 5;
28603         } TCR2_b;
28604     };
28605     __IM uint8_t   RESERVED13;
28606     __IM uint16_t  RESERVED14[18];
28607     __IOM uint16_t TGRE;               /*!< (@ 0x00000172) Timer General Register E                                   */
28608 } R_MTU3_Type;                         /*!< Size = 372 (0x174)                                                        */
28609 
28610 /* =========================================================================================================================== */
28611 /* ================                                          R_MTU4                                           ================ */
28612 /* =========================================================================================================================== */
28613 
28614 /**
28615  * @brief Multi-Function Timer Pulse Unit Channel 4 (R_MTU4)
28616  */
28617 
28618 typedef struct                         /*!< (@ 0x90001200) R_MTU4 Structure                                           */
28619 {
28620     __IM uint8_t RESERVED;
28621 
28622     union
28623     {
28624         __IOM uint8_t TCR;             /*!< (@ 0x00000001) Timer Control Register                                     */
28625 
28626         struct
28627         {
28628             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
28629             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
28630             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
28631         } TCR_b;
28632     };
28633     __IM uint8_t RESERVED1;
28634 
28635     union
28636     {
28637         __IOM uint8_t TMDR1;           /*!< (@ 0x00000003) Timer Mode Register 1                                      */
28638 
28639         struct
28640         {
28641             __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
28642             __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
28643             __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
28644             uint8_t           : 2;
28645         } TMDR1_b;
28646     };
28647     __IM uint16_t RESERVED2;
28648 
28649     union
28650     {
28651         __IOM uint8_t TIORH;           /*!< (@ 0x00000006) Timer I/O Control Register H                               */
28652 
28653         struct
28654         {
28655             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
28656             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
28657         } TIORH_b;
28658     };
28659 
28660     union
28661     {
28662         __IOM uint8_t TIORL;           /*!< (@ 0x00000007) Timer I/O Control Register L                               */
28663 
28664         struct
28665         {
28666             __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
28667             __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
28668         } TIORL_b;
28669     };
28670     __IM uint8_t RESERVED3;
28671 
28672     union
28673     {
28674         __IOM uint8_t TIER;            /*!< (@ 0x00000009) Timer Interrupt Enable Register                            */
28675 
28676         struct
28677         {
28678             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
28679             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
28680             __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
28681             __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
28682             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
28683             uint8_t             : 1;
28684             __IOM uint8_t TTGE2 : 1;   /*!< [6..6] A/D Converter Start Request Enable 2                               */
28685             __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
28686         } TIER_b;
28687     };
28688     __IM uint16_t  RESERVED4[4];
28689     __IOM uint16_t TCNT;               /*!< (@ 0x00000012) Timer Counter                                              */
28690     __IM uint16_t  RESERVED5[4];
28691     __IOM uint16_t TGRA;               /*!< (@ 0x0000001C) Timer General Register A                                   */
28692     __IOM uint16_t TGRB;               /*!< (@ 0x0000001E) Timer General Register B                                   */
28693     __IM uint16_t  RESERVED6[4];
28694     __IOM uint16_t TGRC;               /*!< (@ 0x00000028) Timer General Register C                                   */
28695     __IOM uint16_t TGRD;               /*!< (@ 0x0000002A) Timer General Register D                                   */
28696     __IM uint8_t   RESERVED7;
28697 
28698     union
28699     {
28700         __IOM uint8_t TSR;             /*!< (@ 0x0000002D) Timer Status Register                                      */
28701 
28702         struct
28703         {
28704             __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
28705             __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
28706             __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
28707             __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
28708             __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
28709             __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
28710             uint8_t            : 1;
28711             __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
28712         } TSR_b;
28713     };
28714     __IM uint16_t RESERVED8[5];
28715     __IM uint8_t  RESERVED9;
28716 
28717     union
28718     {
28719         __IOM uint8_t TBTM;            /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register              */
28720 
28721         struct
28722         {
28723             __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
28724             __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
28725             uint8_t            : 6;
28726         } TBTM_b;
28727     };
28728     __IM uint16_t RESERVED10[3];
28729 
28730     union
28731     {
28732         __IOM uint16_t TADCR;          /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register         */
28733 
28734         struct
28735         {
28736             __IOM uint16_t ITB4VE : 1; /*!< [0..0] TCIV4 Interrupt Skipping Link Enable                               */
28737             __IOM uint16_t ITB3AE : 1; /*!< [1..1] TGIA3 Interrupt Skipping Link Enable                               */
28738             __IOM uint16_t ITA4VE : 1; /*!< [2..2] TCIV4 Interrupt Skipping Link Enable                               */
28739             __IOM uint16_t ITA3AE : 1; /*!< [3..3] TGIA3 Interrupt Skipping Link Enable                               */
28740             __IOM uint16_t DT4BE  : 1; /*!< [4..4] Down-Count TRG4BN Enable                                           */
28741             __IOM uint16_t UT4BE  : 1; /*!< [5..5] Up-Count TRG4BN Enable                                             */
28742             __IOM uint16_t DT4AE  : 1; /*!< [6..6] Down-Count TRG4AN Enable                                           */
28743             __IOM uint16_t UT4AE  : 1; /*!< [7..7] Up-Count TRG4AN Enable                                             */
28744             uint16_t              : 6;
28745             __IOM uint16_t BF     : 2; /*!< [15..14] MTU4.TADCOBRA/TADCOBRB Transfer Timing Select                    */
28746         } TADCR_b;
28747     };
28748     __IM uint16_t  RESERVED11;
28749     __IOM uint16_t TADCORA;            /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register
28750                                         *                  A                                                          */
28751     __IOM uint16_t TADCORB;            /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register
28752                                         *                  B                                                          */
28753     __IOM uint16_t TADCOBRA;           /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer
28754                                         *                  Register A                                                 */
28755     __IOM uint16_t TADCOBRB;           /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer
28756                                         *                  Register B                                                 */
28757     __IM uint8_t RESERVED12;
28758 
28759     union
28760     {
28761         __IOM uint8_t TCR2;            /*!< (@ 0x0000004D) Timer Control Register 2                                   */
28762 
28763         struct
28764         {
28765             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
28766             uint8_t             : 5;
28767         } TCR2_b;
28768     };
28769     __IM uint16_t  RESERVED13[19];
28770     __IOM uint16_t TGRE;               /*!< (@ 0x00000074) Timer General Register E                                   */
28771     __IOM uint16_t TGRF;               /*!< (@ 0x00000076) Timer General Register F                                   */
28772 } R_MTU4_Type;                         /*!< Size = 120 (0x78)                                                         */
28773 
28774 /* =========================================================================================================================== */
28775 /* ================                                         R_MTU_NF                                          ================ */
28776 /* =========================================================================================================================== */
28777 
28778 /**
28779  * @brief Multi-Function Timer Pulse Unit Noise Filter (R_MTU_NF)
28780  */
28781 
28782 typedef struct                         /*!< (@ 0x90001290) R_MTU_NF Structure                                         */
28783 {
28784     union
28785     {
28786         __IOM uint8_t NFCR0;           /*!< (@ 0x00000000) Noise Filter Control Register 0                            */
28787 
28788         struct
28789         {
28790             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28791             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28792             __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
28793             __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
28794             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28795             uint8_t             : 2;
28796         } NFCR0_b;
28797     };
28798 
28799     union
28800     {
28801         __IOM uint8_t NFCR1;           /*!< (@ 0x00000001) Noise Filter Control Register 1                            */
28802 
28803         struct
28804         {
28805             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28806             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28807             uint8_t             : 2;
28808             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28809             uint8_t             : 2;
28810         } NFCR1_b;
28811     };
28812 
28813     union
28814     {
28815         __IOM uint8_t NFCR2;           /*!< (@ 0x00000002) Noise Filter Control Register 2                            */
28816 
28817         struct
28818         {
28819             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28820             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28821             uint8_t             : 2;
28822             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28823             uint8_t             : 2;
28824         } NFCR2_b;
28825     };
28826 
28827     union
28828     {
28829         __IOM uint8_t NFCR3;           /*!< (@ 0x00000003) Noise Filter Control Register 3                            */
28830 
28831         struct
28832         {
28833             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28834             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28835             __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
28836             __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
28837             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28838             uint8_t             : 2;
28839         } NFCR3_b;
28840     };
28841 
28842     union
28843     {
28844         __IOM uint8_t NFCR4;           /*!< (@ 0x00000004) Noise Filter Control Register 4                            */
28845 
28846         struct
28847         {
28848             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28849             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28850             __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
28851             __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
28852             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28853             uint8_t             : 2;
28854         } NFCR4_b;
28855     };
28856     __IM uint8_t RESERVED[3];
28857 
28858     union
28859     {
28860         __IOM uint8_t NFCR8;           /*!< (@ 0x00000008) Noise Filter Control Register 8                            */
28861 
28862         struct
28863         {
28864             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28865             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28866             __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
28867             __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
28868             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28869             uint8_t             : 2;
28870         } NFCR8_b;
28871     };
28872 
28873     union
28874     {
28875         __IOM uint8_t NFCRC;           /*!< (@ 0x00000009) Noise Filter Control Register C                            */
28876 
28877         struct
28878         {
28879             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28880             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28881             __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
28882             __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
28883             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28884             uint8_t             : 2;
28885         } NFCRC_b;
28886     };
28887     __IM uint8_t RESERVED1[2041];
28888 
28889     union
28890     {
28891         __IOM uint8_t NFCR6;           /*!< (@ 0x00000803) Noise Filter Control Register 6                            */
28892 
28893         struct
28894         {
28895             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28896             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28897             __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
28898             __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
28899             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28900             uint8_t             : 2;
28901         } NFCR6_b;
28902     };
28903 
28904     union
28905     {
28906         __IOM uint8_t NFCR7;           /*!< (@ 0x00000804) Noise Filter Control Register 7                            */
28907 
28908         struct
28909         {
28910             __IOM uint8_t NFAEN : 1;   /*!< [0..0] Noise Filter A Enable                                              */
28911             __IOM uint8_t NFBEN : 1;   /*!< [1..1] Noise Filter B Enable                                              */
28912             __IOM uint8_t NFCEN : 1;   /*!< [2..2] Noise Filter C Enable                                              */
28913             __IOM uint8_t NFDEN : 1;   /*!< [3..3] Noise Filter D Enable                                              */
28914             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28915             uint8_t             : 2;
28916         } NFCR7_b;
28917     };
28918 
28919     union
28920     {
28921         __IOM uint8_t NFCR5;           /*!< (@ 0x00000805) Noise Filter Control Register 5                            */
28922 
28923         struct
28924         {
28925             __IOM uint8_t NFUEN : 1;   /*!< [0..0] Noise Filter U Enable                                              */
28926             __IOM uint8_t NFVEN : 1;   /*!< [1..1] Noise Filter V Enable                                              */
28927             __IOM uint8_t NFWEN : 1;   /*!< [2..2] Noise Filter W Enable                                              */
28928             uint8_t             : 1;
28929             __IOM uint8_t NFCS  : 2;   /*!< [5..4] Noise Filter Clock Select                                          */
28930             uint8_t             : 2;
28931         } NFCR5_b;
28932     };
28933 } R_MTU_NF_Type;                       /*!< Size = 2054 (0x806)                                                       */
28934 
28935 /* =========================================================================================================================== */
28936 /* ================                                          R_MTU0                                           ================ */
28937 /* =========================================================================================================================== */
28938 
28939 /**
28940  * @brief Multi-Function Timer Pulse Unit Channel 0 (R_MTU0)
28941  */
28942 
28943 typedef struct                         /*!< (@ 0x90001300) R_MTU0 Structure                                           */
28944 {
28945     union
28946     {
28947         __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
28948 
28949         struct
28950         {
28951             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
28952             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
28953             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
28954         } TCR_b;
28955     };
28956 
28957     union
28958     {
28959         __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
28960 
28961         struct
28962         {
28963             __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
28964             __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
28965             __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
28966             __IOM uint8_t BFE : 1;     /*!< [6..6] Buffer Operation E                                                 */
28967             uint8_t           : 1;
28968         } TMDR1_b;
28969     };
28970 
28971     union
28972     {
28973         __IOM uint8_t TIORH;           /*!< (@ 0x00000002) Timer I/O Control Register H                               */
28974 
28975         struct
28976         {
28977             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
28978             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
28979         } TIORH_b;
28980     };
28981 
28982     union
28983     {
28984         __IOM uint8_t TIORL;           /*!< (@ 0x00000003) Timer I/O Control Register L                               */
28985 
28986         struct
28987         {
28988             __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
28989             __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
28990         } TIORL_b;
28991     };
28992 
28993     union
28994     {
28995         __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
28996 
28997         struct
28998         {
28999             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
29000             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
29001             __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
29002             __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
29003             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
29004             uint8_t             : 2;
29005             __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
29006         } TIER_b;
29007     };
29008     __IM uint8_t   RESERVED;
29009     __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
29010     __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
29011     __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
29012     __IOM uint16_t TGRC;               /*!< (@ 0x0000000C) Timer General Register C                                   */
29013     __IOM uint16_t TGRD;               /*!< (@ 0x0000000E) Timer General Register D                                   */
29014     __IM uint16_t  RESERVED1[8];
29015     __IOM uint16_t TGRE;               /*!< (@ 0x00000020) Timer General Register E                                   */
29016     __IOM uint16_t TGRF;               /*!< (@ 0x00000022) Timer General Register F                                   */
29017 
29018     union
29019     {
29020         __IOM uint8_t TIER2;           /*!< (@ 0x00000024) Timer Interrupt Enable Register 2                          */
29021 
29022         struct
29023         {
29024             __IOM uint8_t TGIEE : 1;   /*!< [0..0] TGR Interrupt Enable E                                             */
29025             __IOM uint8_t TGIEF : 1;   /*!< [1..1] TGR Interrupt Enable F                                             */
29026             uint8_t             : 5;
29027             __IOM uint8_t TTGE2 : 1;   /*!< [7..7] A/D Converter Start Request Enable 2                               */
29028         } TIER2_b;
29029     };
29030     __IM uint8_t RESERVED2;
29031 
29032     union
29033     {
29034         __IOM uint8_t TBTM;            /*!< (@ 0x00000026) Timer Buffer Operation Transfer Mode Register              */
29035 
29036         struct
29037         {
29038             __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
29039             __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
29040             __IOM uint8_t TTSE : 1;    /*!< [2..2] Timing Select E                                                    */
29041             uint8_t            : 5;
29042         } TBTM_b;
29043     };
29044     __IM uint8_t RESERVED3;
29045 
29046     union
29047     {
29048         __IOM uint8_t TCR2;            /*!< (@ 0x00000028) Timer Control Register 2                                   */
29049 
29050         struct
29051         {
29052             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29053             uint8_t             : 5;
29054         } TCR2_b;
29055     };
29056     __IM uint8_t  RESERVED4;
29057     __IM uint16_t RESERVED5;
29058 } R_MTU0_Type;                         /*!< Size = 44 (0x2c)                                                          */
29059 
29060 /* =========================================================================================================================== */
29061 /* ================                                          R_MTU1                                           ================ */
29062 /* =========================================================================================================================== */
29063 
29064 /**
29065  * @brief Multi-Function Timer Pulse Unit Channel 1 (R_MTU1)
29066  */
29067 
29068 typedef struct                         /*!< (@ 0x90001380) R_MTU1 Structure                                           */
29069 {
29070     union
29071     {
29072         __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
29073 
29074         struct
29075         {
29076             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
29077             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
29078             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
29079         } TCR_b;
29080     };
29081 
29082     union
29083     {
29084         __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
29085 
29086         struct
29087         {
29088             __IOM uint8_t MD : 4;      /*!< [3..0] Mode Select                                                        */
29089             uint8_t          : 4;
29090         } TMDR1_b;
29091     };
29092 
29093     union
29094     {
29095         __IOM uint8_t TIOR;            /*!< (@ 0x00000002) Timer I/O Control Register                                 */
29096 
29097         struct
29098         {
29099             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
29100             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
29101         } TIOR_b;
29102     };
29103     __IM uint8_t RESERVED;
29104 
29105     union
29106     {
29107         __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
29108 
29109         struct
29110         {
29111             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
29112             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
29113             uint8_t             : 2;
29114             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
29115             __IOM uint8_t TCIEU : 1;   /*!< [5..5] Underflow Interrupt Enable                                         */
29116             uint8_t             : 1;
29117             __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
29118         } TIER_b;
29119     };
29120 
29121     union
29122     {
29123         __IOM uint8_t TSR;             /*!< (@ 0x00000005) Timer Status Register                                      */
29124 
29125         struct
29126         {
29127             __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
29128             __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
29129             __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
29130             __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
29131             __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
29132             __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
29133             uint8_t            : 1;
29134             __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
29135         } TSR_b;
29136     };
29137     __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
29138     __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
29139     __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
29140     __IM uint32_t  RESERVED1;
29141 
29142     union
29143     {
29144         __IOM uint8_t TICCR;           /*!< (@ 0x00000010) Timer Input Capture Control Register                       */
29145 
29146         struct
29147         {
29148             __IOM uint8_t I1AE : 1;    /*!< [0..0] Input Capture Enable                                               */
29149             __IOM uint8_t I1BE : 1;    /*!< [1..1] Input Capture Enable                                               */
29150             __IOM uint8_t I2AE : 1;    /*!< [2..2] Input Capture Enable                                               */
29151             __IOM uint8_t I2BE : 1;    /*!< [3..3] Input Capture Enable                                               */
29152             uint8_t            : 4;
29153         } TICCR_b;
29154     };
29155 
29156     union
29157     {
29158         __IOM uint8_t TMDR3;           /*!< (@ 0x00000011) Timer Mode Register 3                                      */
29159 
29160         struct
29161         {
29162             __IOM uint8_t LWA     : 1; /*!< [0..0] MTU1/MTU2 Combination Longword Access Control                      */
29163             __IOM uint8_t PHCKSEL : 1; /*!< [1..1] External Input Phase Clock Select                                  */
29164             uint8_t               : 6;
29165         } TMDR3_b;
29166     };
29167     __IM uint16_t RESERVED2;
29168 
29169     union
29170     {
29171         __IOM uint8_t TCR2;            /*!< (@ 0x00000014) Timer Control Register 2                                   */
29172 
29173         struct
29174         {
29175             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29176             __IOM uint8_t PCB   : 2;   /*!< [4..3] Functional Expansion Control for Phase Counting Modes
29177                                         *   2, 3, and 5                                                               */
29178             uint8_t : 3;
29179         } TCR2_b;
29180     };
29181     __IM uint8_t   RESERVED3;
29182     __IM uint16_t  RESERVED4;
29183     __IM uint32_t  RESERVED5[2];
29184     __IOM uint32_t TCNTLW;             /*!< (@ 0x00000020) Timer Longword Counter                                     */
29185     __IOM uint32_t TGRALW;             /*!< (@ 0x00000024) Timer Longword General Register A                          */
29186     __IOM uint32_t TGRBLW;             /*!< (@ 0x00000028) Timer Longword General Register B                          */
29187 } R_MTU1_Type;                         /*!< Size = 44 (0x2c)                                                          */
29188 
29189 /* =========================================================================================================================== */
29190 /* ================                                          R_MTU2                                           ================ */
29191 /* =========================================================================================================================== */
29192 
29193 /**
29194  * @brief Multi-Function Timer Pulse Unit Channel 2 (R_MTU2)
29195  */
29196 
29197 typedef struct                         /*!< (@ 0x90001400) R_MTU2 Structure                                           */
29198 {
29199     union
29200     {
29201         __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
29202 
29203         struct
29204         {
29205             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
29206             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
29207             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
29208         } TCR_b;
29209     };
29210 
29211     union
29212     {
29213         __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
29214 
29215         struct
29216         {
29217             __IOM uint8_t MD : 4;      /*!< [3..0] Mode Select                                                        */
29218             uint8_t          : 4;
29219         } TMDR1_b;
29220     };
29221 
29222     union
29223     {
29224         __IOM uint8_t TIOR;            /*!< (@ 0x00000002) Timer I/O Control Register                                 */
29225 
29226         struct
29227         {
29228             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
29229             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
29230         } TIOR_b;
29231     };
29232     __IM uint8_t RESERVED;
29233 
29234     union
29235     {
29236         __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
29237 
29238         struct
29239         {
29240             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
29241             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
29242             uint8_t             : 2;
29243             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
29244             __IOM uint8_t TCIEU : 1;   /*!< [5..5] Underflow Interrupt Enable                                         */
29245             uint8_t             : 1;
29246             __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
29247         } TIER_b;
29248     };
29249 
29250     union
29251     {
29252         __IOM uint8_t TSR;             /*!< (@ 0x00000005) Timer Status Register                                      */
29253 
29254         struct
29255         {
29256             __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
29257             __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
29258             __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
29259             __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
29260             __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
29261             __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
29262             uint8_t            : 1;
29263             __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
29264         } TSR_b;
29265     };
29266     __IOM uint16_t TCNT;               /*!< (@ 0x00000006) Timer Counter                                              */
29267     __IOM uint16_t TGRA;               /*!< (@ 0x00000008) Timer General Register A                                   */
29268     __IOM uint16_t TGRB;               /*!< (@ 0x0000000A) Timer General Register B                                   */
29269 
29270     union
29271     {
29272         __IOM uint8_t TCR2;            /*!< (@ 0x0000000C) Timer Control Register 2                                   */
29273 
29274         struct
29275         {
29276             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29277             __IOM uint8_t PCB   : 2;   /*!< [4..3] Functional Expansion Control for Phase Counting Modes
29278                                         *   2, 3, and 5                                                               */
29279             uint8_t : 3;
29280         } TCR2_b;
29281     };
29282     __IM uint8_t  RESERVED1;
29283     __IM uint16_t RESERVED2;
29284 } R_MTU2_Type;                         /*!< Size = 16 (0x10)                                                          */
29285 
29286 /* =========================================================================================================================== */
29287 /* ================                                          R_MTU8                                           ================ */
29288 /* =========================================================================================================================== */
29289 
29290 /**
29291  * @brief Multi-Function Timer Pulse Unit Channel 8 (R_MTU8)
29292  */
29293 
29294 typedef struct                         /*!< (@ 0x90001600) R_MTU8 Structure                                           */
29295 {
29296     union
29297     {
29298         __IOM uint8_t TCR;             /*!< (@ 0x00000000) Timer Control Register                                     */
29299 
29300         struct
29301         {
29302             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
29303             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
29304             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
29305         } TCR_b;
29306     };
29307 
29308     union
29309     {
29310         __IOM uint8_t TMDR1;           /*!< (@ 0x00000001) Timer Mode Register 1                                      */
29311 
29312         struct
29313         {
29314             __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
29315             __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
29316             __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
29317             uint8_t           : 2;
29318         } TMDR1_b;
29319     };
29320 
29321     union
29322     {
29323         __IOM uint8_t TIORH;           /*!< (@ 0x00000002) Timer I/O Control Register H                               */
29324 
29325         struct
29326         {
29327             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
29328             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
29329         } TIORH_b;
29330     };
29331 
29332     union
29333     {
29334         __IOM uint8_t TIORL;           /*!< (@ 0x00000003) Timer I/O Control Register L                               */
29335 
29336         struct
29337         {
29338             __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
29339             __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
29340         } TIORL_b;
29341     };
29342 
29343     union
29344     {
29345         __IOM uint8_t TIER;            /*!< (@ 0x00000004) Timer Interrupt Enable Register                            */
29346 
29347         struct
29348         {
29349             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
29350             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
29351             __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
29352             __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
29353             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
29354             uint8_t             : 3;
29355         } TIER_b;
29356     };
29357     __IM uint8_t RESERVED;
29358 
29359     union
29360     {
29361         __IOM uint8_t TCR2;            /*!< (@ 0x00000006) Timer Control Register 2                                   */
29362 
29363         struct
29364         {
29365             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29366             uint8_t             : 5;
29367         } TCR2_b;
29368     };
29369     __IM uint8_t   RESERVED1;
29370     __IOM uint32_t TCNT;               /*!< (@ 0x00000008) Timer Counter                                              */
29371     __IOM uint32_t TGRA;               /*!< (@ 0x0000000C) Timer General Register A                                   */
29372     __IOM uint32_t TGRB;               /*!< (@ 0x00000010) Timer General Register B                                   */
29373     __IOM uint32_t TGRC;               /*!< (@ 0x00000014) Timer General Register C                                   */
29374     __IOM uint32_t TGRD;               /*!< (@ 0x00000018) Timer General Register D                                   */
29375 } R_MTU8_Type;                         /*!< Size = 28 (0x1c)                                                          */
29376 
29377 /* =========================================================================================================================== */
29378 /* ================                                          R_MTU6                                           ================ */
29379 /* =========================================================================================================================== */
29380 
29381 /**
29382  * @brief Multi-Function Timer Pulse Unit Channel 6 (R_MTU6)
29383  */
29384 
29385 typedef struct                         /*!< (@ 0x90001900) R_MTU6 Structure                                           */
29386 {
29387     __IM uint16_t RESERVED[128];
29388 
29389     union
29390     {
29391         __IOM uint8_t TCR;             /*!< (@ 0x00000100) Timer Control Register                                     */
29392 
29393         struct
29394         {
29395             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
29396             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
29397             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
29398         } TCR_b;
29399     };
29400     __IM uint8_t RESERVED1;
29401 
29402     union
29403     {
29404         __IOM uint8_t TMDR1;           /*!< (@ 0x00000102) Timer Mode Register 1                                      */
29405 
29406         struct
29407         {
29408             __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
29409             __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
29410             __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
29411             uint8_t           : 2;
29412         } TMDR1_b;
29413     };
29414     __IM uint8_t RESERVED2;
29415 
29416     union
29417     {
29418         __IOM uint8_t TIORH;           /*!< (@ 0x00000104) Timer I/O Control Register H                               */
29419 
29420         struct
29421         {
29422             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
29423             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
29424         } TIORH_b;
29425     };
29426 
29427     union
29428     {
29429         __IOM uint8_t TIORL;           /*!< (@ 0x00000105) Timer I/O Control Register L                               */
29430 
29431         struct
29432         {
29433             __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
29434             __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
29435         } TIORL_b;
29436     };
29437     __IM uint16_t RESERVED3;
29438 
29439     union
29440     {
29441         __IOM uint8_t TIER;            /*!< (@ 0x00000108) Timer Interrupt Enable Register                            */
29442 
29443         struct
29444         {
29445             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
29446             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
29447             __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
29448             __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
29449             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
29450             uint8_t             : 2;
29451             __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
29452         } TIER_b;
29453     };
29454     __IM uint8_t   RESERVED4;
29455     __IM uint16_t  RESERVED5[3];
29456     __IOM uint16_t TCNT;               /*!< (@ 0x00000110) Timer Counter                                              */
29457     __IM uint16_t  RESERVED6[3];
29458     __IOM uint16_t TGRA;               /*!< (@ 0x00000118) Timer General Register A                                   */
29459     __IOM uint16_t TGRB;               /*!< (@ 0x0000011A) Timer General Register B                                   */
29460     __IM uint16_t  RESERVED7[4];
29461     __IOM uint16_t TGRC;               /*!< (@ 0x00000124) Timer General Register C                                   */
29462     __IOM uint16_t TGRD;               /*!< (@ 0x00000126) Timer General Register D                                   */
29463     __IM uint16_t  RESERVED8[2];
29464 
29465     union
29466     {
29467         __IOM uint8_t TSR;             /*!< (@ 0x0000012C) Timer Status Register                                      */
29468 
29469         struct
29470         {
29471             __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
29472             __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
29473             __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
29474             __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
29475             __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
29476             __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
29477             uint8_t            : 1;
29478             __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
29479         } TSR_b;
29480     };
29481     __IM uint8_t  RESERVED9;
29482     __IM uint16_t RESERVED10[5];
29483 
29484     union
29485     {
29486         __IOM uint8_t TBTM;            /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register              */
29487 
29488         struct
29489         {
29490             __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
29491             __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
29492             uint8_t            : 6;
29493         } TBTM_b;
29494     };
29495     __IM uint8_t  RESERVED11;
29496     __IM uint16_t RESERVED12[9];
29497 
29498     union
29499     {
29500         __IOM uint8_t TCR2;            /*!< (@ 0x0000014C) Timer Control Register 2                                   */
29501 
29502         struct
29503         {
29504             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29505             uint8_t             : 5;
29506         } TCR2_b;
29507     };
29508     __IM uint8_t  RESERVED13;
29509     __IM uint16_t RESERVED14;
29510 
29511     union
29512     {
29513         __IOM uint8_t TSYCR;           /*!< (@ 0x00000150) Timer Synchronous Clear Register                           */
29514 
29515         struct
29516         {
29517             __IOM uint8_t CE2B : 1;    /*!< [0..0] Clear Enable 2B                                                    */
29518             __IOM uint8_t CE2A : 1;    /*!< [1..1] Clear Enable 2A                                                    */
29519             __IOM uint8_t CE1B : 1;    /*!< [2..2] Clear Enable 1B                                                    */
29520             __IOM uint8_t CE1A : 1;    /*!< [3..3] Clear Enable 1A                                                    */
29521             __IOM uint8_t CE0D : 1;    /*!< [4..4] Clear Enable 0D                                                    */
29522             __IOM uint8_t CE0C : 1;    /*!< [5..5] Clear Enable 0C                                                    */
29523             __IOM uint8_t CE0B : 1;    /*!< [6..6] Clear Enable 0B                                                    */
29524             __IOM uint8_t CE0A : 1;    /*!< [7..7] Clear Enable 0A                                                    */
29525         } TSYCR_b;
29526     };
29527     __IM uint8_t   RESERVED15;
29528     __IM uint16_t  RESERVED16[16];
29529     __IOM uint16_t TGRE;               /*!< (@ 0x00000172) Timer General Register E                                   */
29530 } R_MTU6_Type;                         /*!< Size = 372 (0x174)                                                        */
29531 
29532 /* =========================================================================================================================== */
29533 /* ================                                          R_MTU7                                           ================ */
29534 /* =========================================================================================================================== */
29535 
29536 /**
29537  * @brief Multi-Function Timer Pulse Unit Channel 7 (R_MTU7)
29538  */
29539 
29540 typedef struct                         /*!< (@ 0x90001A00) R_MTU7 Structure                                           */
29541 {
29542     __IM uint8_t RESERVED;
29543 
29544     union
29545     {
29546         __IOM uint8_t TCR;             /*!< (@ 0x00000001) Timer Control Register                                     */
29547 
29548         struct
29549         {
29550             __IOM uint8_t TPSC : 3;    /*!< [2..0] Time Prescaler Select                                              */
29551             __IOM uint8_t CKEG : 2;    /*!< [4..3] Clock Edge Select                                                  */
29552             __IOM uint8_t CCLR : 3;    /*!< [7..5] Counter Clear Source Select                                        */
29553         } TCR_b;
29554     };
29555     __IM uint8_t RESERVED1;
29556 
29557     union
29558     {
29559         __IOM uint8_t TMDR1;           /*!< (@ 0x00000003) Timer Mode Register 1                                      */
29560 
29561         struct
29562         {
29563             __IOM uint8_t MD  : 4;     /*!< [3..0] Mode Select                                                        */
29564             __IOM uint8_t BFA : 1;     /*!< [4..4] Buffer Operation A                                                 */
29565             __IOM uint8_t BFB : 1;     /*!< [5..5] Buffer Operation B                                                 */
29566             uint8_t           : 2;
29567         } TMDR1_b;
29568     };
29569     __IM uint16_t RESERVED2;
29570 
29571     union
29572     {
29573         __IOM uint8_t TIORH;           /*!< (@ 0x00000006) Timer I/O Control Register H                               */
29574 
29575         struct
29576         {
29577             __IOM uint8_t IOA : 4;     /*!< [3..0] I/O Control A                                                      */
29578             __IOM uint8_t IOB : 4;     /*!< [7..4] I/O Control B                                                      */
29579         } TIORH_b;
29580     };
29581 
29582     union
29583     {
29584         __IOM uint8_t TIORL;           /*!< (@ 0x00000007) Timer I/O Control Register L                               */
29585 
29586         struct
29587         {
29588             __IOM uint8_t IOC : 4;     /*!< [3..0] I/O Control A                                                      */
29589             __IOM uint8_t IOD : 4;     /*!< [7..4] I/O Control B                                                      */
29590         } TIORL_b;
29591     };
29592     __IM uint8_t RESERVED3;
29593 
29594     union
29595     {
29596         __IOM uint8_t TIER;            /*!< (@ 0x00000009) Timer Interrupt Enable Register                            */
29597 
29598         struct
29599         {
29600             __IOM uint8_t TGIEA : 1;   /*!< [0..0] TGR Interrupt Enable A                                             */
29601             __IOM uint8_t TGIEB : 1;   /*!< [1..1] TGR Interrupt Enable B                                             */
29602             __IOM uint8_t TGIEC : 1;   /*!< [2..2] TGR Interrupt Enable C                                             */
29603             __IOM uint8_t TGIED : 1;   /*!< [3..3] TGR Interrupt Enable D                                             */
29604             __IOM uint8_t TCIEV : 1;   /*!< [4..4] Overflow Interrupt Enable                                          */
29605             uint8_t             : 1;
29606             __IOM uint8_t TTGE2 : 1;   /*!< [6..6] A/D Converter Start Request Enable 2                               */
29607             __IOM uint8_t TTGE  : 1;   /*!< [7..7] A/D Converter Start Request Enable                                 */
29608         } TIER_b;
29609     };
29610     __IM uint16_t  RESERVED4[4];
29611     __IOM uint16_t TCNT;               /*!< (@ 0x00000012) Timer Counter                                              */
29612     __IM uint16_t  RESERVED5[4];
29613     __IOM uint16_t TGRA;               /*!< (@ 0x0000001C) Timer General Register A                                   */
29614     __IOM uint16_t TGRB;               /*!< (@ 0x0000001E) Timer General Register B                                   */
29615     __IM uint16_t  RESERVED6[4];
29616     __IOM uint16_t TGRC;               /*!< (@ 0x00000028) Timer General Register C                                   */
29617     __IOM uint16_t TGRD;               /*!< (@ 0x0000002A) Timer General Register D                                   */
29618     __IM uint8_t   RESERVED7;
29619 
29620     union
29621     {
29622         __IOM uint8_t TSR;             /*!< (@ 0x0000002D) Timer Status Register                                      */
29623 
29624         struct
29625         {
29626             __IOM uint8_t TGFA : 1;    /*!< [0..0] Input Capture/Output Compare Flag A                                */
29627             __IOM uint8_t TGFB : 1;    /*!< [1..1] Input Capture/Output Compare Flag B                                */
29628             __IOM uint8_t TGFC : 1;    /*!< [2..2] Input Capture/Output Compare Flag C                                */
29629             __IOM uint8_t TGFD : 1;    /*!< [3..3] Input Capture/Output Compare Flag D                                */
29630             __IOM uint8_t TCFV : 1;    /*!< [4..4] Overflow flag                                                      */
29631             __IOM uint8_t TCFU : 1;    /*!< [5..5] Underflow flag                                                     */
29632             uint8_t            : 1;
29633             __IM uint8_t TCFD  : 1;    /*!< [7..7] Count Direction Flag                                               */
29634         } TSR_b;
29635     };
29636     __IM uint16_t RESERVED8[5];
29637     __IM uint8_t  RESERVED9;
29638 
29639     union
29640     {
29641         __IOM uint8_t TBTM;            /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register              */
29642 
29643         struct
29644         {
29645             __IOM uint8_t TTSA : 1;    /*!< [0..0] Timing Select A                                                    */
29646             __IOM uint8_t TTSB : 1;    /*!< [1..1] Timing Select B                                                    */
29647             uint8_t            : 6;
29648         } TBTM_b;
29649     };
29650     __IM uint16_t RESERVED10[3];
29651 
29652     union
29653     {
29654         __IOM uint16_t TADCR;          /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register         */
29655 
29656         struct
29657         {
29658             __IOM uint16_t ITB7VE : 1; /*!< [0..0] TCIV7 Interrupt Skipping Link Enable                               */
29659             __IOM uint16_t ITB6AE : 1; /*!< [1..1] TGIA6 Interrupt Skipping Link Enable                               */
29660             __IOM uint16_t ITA7VE : 1; /*!< [2..2] TCIV7 Interrupt Skipping Link Enable                               */
29661             __IOM uint16_t ITA6AE : 1; /*!< [3..3] TGIA6 Interrupt Skipping Link Enable                               */
29662             __IOM uint16_t DT7BE  : 1; /*!< [4..4] Down-Count TRG7BN Enable                                           */
29663             __IOM uint16_t UT7BE  : 1; /*!< [5..5] Up-Count TRG7BN Enable                                             */
29664             __IOM uint16_t DT7AE  : 1; /*!< [6..6] Down-Count TRG7AN Enable                                           */
29665             __IOM uint16_t UT7AE  : 1; /*!< [7..7] Up-Count TRG7AN Enable                                             */
29666             uint16_t              : 6;
29667             __IOM uint16_t BF     : 2; /*!< [15..14] MTU7.TADCOBRA/TADCOBRB Transfer Timing Select                    */
29668         } TADCR_b;
29669     };
29670     __IM uint16_t  RESERVED11;
29671     __IOM uint16_t TADCORA;            /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register
29672                                         *                  A                                                          */
29673     __IOM uint16_t TADCORB;            /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register
29674                                         *                  B                                                          */
29675     __IOM uint16_t TADCOBRA;           /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer
29676                                         *                  Register A                                                 */
29677     __IOM uint16_t TADCOBRB;           /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer
29678                                         *                  Register B                                                 */
29679     __IM uint8_t RESERVED12;
29680 
29681     union
29682     {
29683         __IOM uint8_t TCR2;            /*!< (@ 0x0000004D) Timer Control Register 2                                   */
29684 
29685         struct
29686         {
29687             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29688             uint8_t             : 5;
29689         } TCR2_b;
29690     };
29691     __IM uint16_t  RESERVED13[19];
29692     __IOM uint16_t TGRE;               /*!< (@ 0x00000074) Timer General Register E                                   */
29693     __IOM uint16_t TGRF;               /*!< (@ 0x00000076) Timer General Register F                                   */
29694 } R_MTU7_Type;                         /*!< Size = 120 (0x78)                                                         */
29695 
29696 /* =========================================================================================================================== */
29697 /* ================                                          R_MTU5                                           ================ */
29698 /* =========================================================================================================================== */
29699 
29700 /**
29701  * @brief Multi-Function Timer Pulse Unit Channel 5 (R_MTU5)
29702  */
29703 
29704 typedef struct                         /*!< (@ 0x90001C00) R_MTU5 Structure                                           */
29705 {
29706     __IM uint16_t  RESERVED[64];
29707     __IOM uint16_t TCNTU;              /*!< (@ 0x00000080) Timer Counter U                                            */
29708     __IOM uint16_t TGRU;               /*!< (@ 0x00000082) Timer General Register U                                   */
29709 
29710     union
29711     {
29712         __IOM uint8_t TCRU;            /*!< (@ 0x00000084) Timer Control Register U                                   */
29713 
29714         struct
29715         {
29716             __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
29717             uint8_t            : 6;
29718         } TCRU_b;
29719     };
29720 
29721     union
29722     {
29723         __IOM uint8_t TCR2U;           /*!< (@ 0x00000085) Timer Control Register 2U                                  */
29724 
29725         struct
29726         {
29727             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29728             __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
29729             uint8_t             : 3;
29730         } TCR2U_b;
29731     };
29732 
29733     union
29734     {
29735         __IOM uint8_t TIORU;           /*!< (@ 0x00000086) Timer I/O Control Register U                               */
29736 
29737         struct
29738         {
29739             __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
29740             uint8_t           : 3;
29741         } TIORU_b;
29742     };
29743     __IM uint8_t   RESERVED1;
29744     __IM uint16_t  RESERVED2[4];
29745     __IOM uint16_t TCNTV;              /*!< (@ 0x00000090) Timer Counter V                                            */
29746     __IOM uint16_t TGRV;               /*!< (@ 0x00000092) Timer General Register V                                   */
29747 
29748     union
29749     {
29750         __IOM uint8_t TCRV;            /*!< (@ 0x00000094) Timer Control Register V                                   */
29751 
29752         struct
29753         {
29754             __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
29755             uint8_t            : 6;
29756         } TCRV_b;
29757     };
29758 
29759     union
29760     {
29761         __IOM uint8_t TCR2V;           /*!< (@ 0x00000095) Timer Control Register 2V                                  */
29762 
29763         struct
29764         {
29765             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29766             __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
29767             uint8_t             : 3;
29768         } TCR2V_b;
29769     };
29770 
29771     union
29772     {
29773         __IOM uint8_t TIORV;           /*!< (@ 0x00000096) Timer I/O Control Register V                               */
29774 
29775         struct
29776         {
29777             __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
29778             uint8_t           : 3;
29779         } TIORV_b;
29780     };
29781     __IM uint8_t   RESERVED3;
29782     __IM uint16_t  RESERVED4[4];
29783     __IOM uint16_t TCNTW;              /*!< (@ 0x000000A0) Timer Counter W                                            */
29784     __IOM uint16_t TGRW;               /*!< (@ 0x000000A2) Timer General Register W                                   */
29785 
29786     union
29787     {
29788         __IOM uint8_t TCRW;            /*!< (@ 0x000000A4) Timer Control Register W                                   */
29789 
29790         struct
29791         {
29792             __IOM uint8_t TPSC : 2;    /*!< [1..0] Time Prescaler Select                                              */
29793             uint8_t            : 6;
29794         } TCRW_b;
29795     };
29796 
29797     union
29798     {
29799         __IOM uint8_t TCR2W;           /*!< (@ 0x000000A5) Timer Control Register 2W                                  */
29800 
29801         struct
29802         {
29803             __IOM uint8_t TPSC2 : 3;   /*!< [2..0] Time Prescaler Select                                              */
29804             __IOM uint8_t CKEG  : 2;   /*!< [4..3] Clock Edge Select                                                  */
29805             uint8_t             : 3;
29806         } TCR2W_b;
29807     };
29808 
29809     union
29810     {
29811         __IOM uint8_t TIORW;           /*!< (@ 0x000000A6) Timer I/O Control Register W                               */
29812 
29813         struct
29814         {
29815             __IOM uint8_t IOC : 5;     /*!< [4..0] I/O Control C                                                      */
29816             uint8_t           : 3;
29817         } TIORW_b;
29818     };
29819     __IM uint8_t  RESERVED5;
29820     __IM uint16_t RESERVED6[5];
29821 
29822     union
29823     {
29824         __IOM uint8_t TIER;            /*!< (@ 0x000000B2) Timer Interrupt Enable Register                            */
29825 
29826         struct
29827         {
29828             __IOM uint8_t TGIE5W : 1;  /*!< [0..0] TGR Interrupt Enable 5W                                            */
29829             __IOM uint8_t TGIE5V : 1;  /*!< [1..1] TGR Interrupt Enable 5V                                            */
29830             __IOM uint8_t TGIE5U : 1;  /*!< [2..2] TGR Interrupt Enable 5U                                            */
29831             uint8_t              : 5;
29832         } TIER_b;
29833     };
29834     __IM uint8_t RESERVED7;
29835 
29836     union
29837     {
29838         __IOM uint8_t TSTR;            /*!< (@ 0x000000B4) Timer Start Register                                       */
29839 
29840         struct
29841         {
29842             __IOM uint8_t CSTW5 : 1;   /*!< [0..0] Counter Start W5                                                   */
29843             __IOM uint8_t CSTV5 : 1;   /*!< [1..1] Counter Start V5                                                   */
29844             __IOM uint8_t CSTU5 : 1;   /*!< [2..2] Counter Start U5                                                   */
29845             uint8_t             : 5;
29846         } TSTR_b;
29847     };
29848     __IM uint8_t RESERVED8;
29849 
29850     union
29851     {
29852         __IOM uint8_t TCNTCMPCLR;       /*!< (@ 0x000000B6) Timer Compare Match Clear Register                         */
29853 
29854         struct
29855         {
29856             __IOM uint8_t CMPCLR5W : 1; /*!< [0..0] TCNT Compare Clear 5W                                              */
29857             __IOM uint8_t CMPCLR5V : 1; /*!< [1..1] TCNT Compare Clear 5V                                              */
29858             __IOM uint8_t CMPCLR5U : 1; /*!< [2..2] TCNT Compare Clear 5U                                              */
29859             uint8_t                : 5;
29860         } TCNTCMPCLR_b;
29861     };
29862     __IM uint8_t  RESERVED9;
29863     __IM uint16_t RESERVED10;
29864 } R_MTU5_Type;                         /*!< Size = 186 (0xba)                                                         */
29865 
29866 /* =========================================================================================================================== */
29867 /* ================                                           R_TFU                                           ================ */
29868 /* =========================================================================================================================== */
29869 
29870 /**
29871  * @brief Trigonometric Function Unit (R_TFU)
29872  */
29873 
29874 typedef struct                         /*!< (@ 0x90003000) R_TFU Structure                                            */
29875 {
29876     __IM uint32_t RESERVED[2];
29877 
29878     union
29879     {
29880         __IM uint8_t TRGSTS;           /*!< (@ 0x00000008) Trigonometric Status Register                              */
29881 
29882         struct
29883         {
29884             __IM uint8_t BSYF : 1;     /*!< [0..0] Calculation in progress flag                                       */
29885             __IM uint8_t ERRF : 1;     /*!< [1..1] Input error flag                                                   */
29886             uint8_t           : 6;
29887         } TRGSTS_b;
29888     };
29889     __IM uint8_t  RESERVED1;
29890     __IM uint16_t RESERVED2;
29891     __IM uint32_t RESERVED3;
29892 
29893     union
29894     {
29895         __IOM float SCDT0;             /*!< (@ 0x00000010) Sine Cosine Data Register 0                                */
29896 
29897         struct
29898         {
29899             __IOM uint32_t SCDT0 : 32; /*!< [31..0] Sine Cosine Data Register 0 (single-precision floating-point)     */
29900         } SCDT0_b;
29901     };
29902 
29903     union
29904     {
29905         __IOM float SCDT1;             /*!< (@ 0x00000014) Sine Cosine Data Register 1                                */
29906 
29907         struct
29908         {
29909             __IOM uint32_t SCDT1 : 32; /*!< [31..0] Sine Cosine Data Register 1 (single-precision floating-point)     */
29910         } SCDT1_b;
29911     };
29912 
29913     union
29914     {
29915         __IOM float ATDT0;             /*!< (@ 0x00000018) Arctangent Data Register 0                                 */
29916 
29917         struct
29918         {
29919             __IOM uint32_t ATDT0 : 32; /*!< [31..0] Arctangent Data Register 0 (single-precision floating-point)      */
29920         } ATDT0_b;
29921     };
29922 
29923     union
29924     {
29925         __IOM float ATDT1;             /*!< (@ 0x0000001C) Arctangent Data Register 1                                 */
29926 
29927         struct
29928         {
29929             __IOM uint32_t ATDT1 : 32; /*!< [31..0] Arctangent Data Register 1 (single-precision floating-point)      */
29930         } ATDT1_b;
29931     };
29932 } R_TFU_Type;                          /*!< Size = 32 (0x20)                                                          */
29933 
29934 /* =========================================================================================================================== */
29935 /* ================                                          R_POE3                                           ================ */
29936 /* =========================================================================================================================== */
29937 
29938 /**
29939  * @brief Port Output Enable 3 (R_POE3)
29940  */
29941 
29942 typedef struct                         /*!< (@ 0x90005000) R_POE3 Structure                                           */
29943 {
29944     union
29945     {
29946         __IOM uint16_t ICSR1;          /*!< (@ 0x00000000) Input Level Control/Status Register 1                      */
29947 
29948         struct
29949         {
29950             __IOM uint16_t POE0M : 2;  /*!< [1..0] POE0 Mode Select                                                   */
29951             uint16_t             : 6;
29952             __IOM uint16_t PIE1  : 1;  /*!< [8..8] Port Interrupt Enable 1                                            */
29953             uint16_t             : 3;
29954             __IOM uint16_t POE0F : 1;  /*!< [12..12] POE0 Flag                                                        */
29955             uint16_t             : 3;
29956         } ICSR1_b;
29957     };
29958 
29959     union
29960     {
29961         __IOM uint16_t OCSR1;          /*!< (@ 0x00000002) Output Level Control/Status Register 1                     */
29962 
29963         struct
29964         {
29965             uint16_t            : 8;
29966             __IOM uint16_t OIE1 : 1;   /*!< [8..8] Output Short Circuit Interrupt Enable 1                            */
29967             __IOM uint16_t OCE1 : 1;   /*!< [9..9] Output Short Circuit High-Impedance Enable 1                       */
29968             uint16_t            : 5;
29969             __IOM uint16_t OSF1 : 1;   /*!< [15..15] Output Short Circuit Flag 1                                      */
29970         } OCSR1_b;
29971     };
29972 
29973     union
29974     {
29975         __IOM uint16_t ICSR2;          /*!< (@ 0x00000004) Input Level Control/Status Register 2                      */
29976 
29977         struct
29978         {
29979             __IOM uint16_t POE4M : 2;  /*!< [1..0] POE4 Mode Select                                                   */
29980             uint16_t             : 6;
29981             __IOM uint16_t PIE2  : 1;  /*!< [8..8] Port Interrupt Enable 2                                            */
29982             uint16_t             : 3;
29983             __IOM uint16_t POE4F : 1;  /*!< [12..12] POE4 Flag                                                        */
29984             uint16_t             : 3;
29985         } ICSR2_b;
29986     };
29987 
29988     union
29989     {
29990         __IOM uint16_t OCSR2;          /*!< (@ 0x00000006) Output Level Control/Status Register 2                     */
29991 
29992         struct
29993         {
29994             uint16_t            : 8;
29995             __IOM uint16_t OIE2 : 1;   /*!< [8..8] Output Short Circuit Interrupt Enable 2                            */
29996             __IOM uint16_t OCE2 : 1;   /*!< [9..9] Output Short Circuit High-Impedance Enable 2                       */
29997             uint16_t            : 5;
29998             __IOM uint16_t OSF2 : 1;   /*!< [15..15] Output Short Circuit Flag 2                                      */
29999         } OCSR2_b;
30000     };
30001 
30002     union
30003     {
30004         __IOM uint16_t ICSR3;          /*!< (@ 0x00000008) Input Level Control/Status Register 3                      */
30005 
30006         struct
30007         {
30008             __IOM uint16_t POE8M : 2;  /*!< [1..0] POE8 Mode Select                                                   */
30009             uint16_t             : 6;
30010             __IOM uint16_t PIE3  : 1;  /*!< [8..8] Port Interrupt Enable 3                                            */
30011             __IOM uint16_t POE8E : 1;  /*!< [9..9] POE8 High-Impedance Enable                                         */
30012             uint16_t             : 2;
30013             __IOM uint16_t POE8F : 1;  /*!< [12..12] POE8 Flag                                                        */
30014             uint16_t             : 3;
30015         } ICSR3_b;
30016     };
30017 
30018     union
30019     {
30020         __IOM uint8_t SPOER;              /*!< (@ 0x0000000A) Software Port Output Enable Register                       */
30021 
30022         struct
30023         {
30024             __IOM uint8_t MTUCH34HIZ : 1; /*!< [0..0] MTU3 and MTU4 Output High-Impedance Enable                         */
30025             __IOM uint8_t MTUCH67HIZ : 1; /*!< [1..1] MTU6 and MTU7 Output High-Impedance Enable                         */
30026             __IOM uint8_t MTUCH0HIZ  : 1; /*!< [2..2] MTU0 Pin High-Impedance Enable                                     */
30027             uint8_t                  : 5;
30028         } SPOER_b;
30029     };
30030 
30031     union
30032     {
30033         __IOM uint8_t POECR1;          /*!< (@ 0x0000000B) Port Output Enable Control Register 1                      */
30034 
30035         struct
30036         {
30037             __IOM uint8_t MTU0AZE : 1; /*!< [0..0] MTIOC0A High-Impedance Enable                                      */
30038             __IOM uint8_t MTU0BZE : 1; /*!< [1..1] MTIOC0B High-Impedance Enable                                      */
30039             __IOM uint8_t MTU0CZE : 1; /*!< [2..2] MTIOC0C High-Impedance Enable                                      */
30040             __IOM uint8_t MTU0DZE : 1; /*!< [3..3] MTIOC0D High-Impedance Enable                                      */
30041             uint8_t               : 4;
30042         } POECR1_b;
30043     };
30044 
30045     union
30046     {
30047         __IOM uint16_t POECR2;           /*!< (@ 0x0000000C) Port Output Enable Control Register 2                      */
30048 
30049         struct
30050         {
30051             __IOM uint16_t MTU7BDZE : 1; /*!< [0..0] MTIOC7B/MTIOC7D High-Impedance Enable                              */
30052             __IOM uint16_t MTU7ACZE : 1; /*!< [1..1] MTIOC7A/MTIOC7C High-Impedance Enable                              */
30053             __IOM uint16_t MTU6BDZE : 1; /*!< [2..2] MTIOC6B/MTIOC6D High-Impedance Enable                              */
30054             uint16_t                : 5;
30055             __IOM uint16_t MTU4BDZE : 1; /*!< [8..8] MTIOC4B/MTIOC4D High-Impedance Enable                              */
30056             __IOM uint16_t MTU4ACZE : 1; /*!< [9..9] MTIOC4A/MTIOC4C High-Impedance Enable                              */
30057             __IOM uint16_t MTU3BDZE : 1; /*!< [10..10] MTIOC3B/MTIOC3D High-Impedance Enable                            */
30058             uint16_t                : 5;
30059         } POECR2_b;
30060     };
30061     __IM uint16_t RESERVED;
30062 
30063     union
30064     {
30065         __IOM uint16_t POECR4;         /*!< (@ 0x00000010) Port Output Enable Control Register 4                      */
30066 
30067         struct
30068         {
30069             uint16_t                    : 2;
30070             __IOM uint16_t IC2ADDMT34ZE : 1; /*!< [2..2] MTU3 and MTU4 High-Impedance POE4F Add                             */
30071             __IOM uint16_t IC3ADDMT34ZE : 1; /*!< [3..3] MTU3 and MTU4 High-Impedance POE8F Add                             */
30072             __IOM uint16_t IC4ADDMT34ZE : 1; /*!< [4..4] MTU3 and MTU4 High-Impedance POE10F Add                            */
30073             __IOM uint16_t IC5ADDMT34ZE : 1; /*!< [5..5] MTU3 and MTU4 High-Impedance POE11F Add                            */
30074             __IOM uint16_t DE0ADDMT34ZE : 1; /*!< [6..6] MTU3 and MTU4 High-Impedance DERR0ST Add                           */
30075             __IOM uint16_t DE1ADDMT34ZE : 1; /*!< [7..7] MTU3 and MTU4 High-Impedance DERR1ST Add                           */
30076             uint16_t                    : 1;
30077             __IOM uint16_t IC1ADDMT67ZE : 1; /*!< [9..9] MTU6 and MTU7 High-Impedance POE0F Add                             */
30078             uint16_t                    : 1;
30079             __IOM uint16_t IC3ADDMT67ZE : 1; /*!< [11..11] MTU6 and MTU7 High-Impedance POE8F Add                           */
30080             __IOM uint16_t IC4ADDMT67ZE : 1; /*!< [12..12] MTU6 and MTU7 High-Impedance POE10F Add                          */
30081             __IOM uint16_t IC5ADDMT67ZE : 1; /*!< [13..13] MTU6 and MTU7 High-Impedance POE11F Add                          */
30082             __IOM uint16_t DE0ADDMT67ZE : 1; /*!< [14..14] MTU6 and MTU7 High-Impedance DERR0ST Add                         */
30083             __IOM uint16_t DE1ADDMT67ZE : 1; /*!< [15..15] MTU6 and MTU7 High-Impedance DERR1ST Add                         */
30084         } POECR4_b;
30085     };
30086 
30087     union
30088     {
30089         __IOM uint16_t POECR5;         /*!< (@ 0x00000012) Port Output Enable Control Register 5                      */
30090 
30091         struct
30092         {
30093             uint16_t                   : 1;
30094             __IOM uint16_t IC1ADDMT0ZE : 1; /*!< [1..1] MTU0 High-Impedance POE0F Add                                      */
30095             __IOM uint16_t IC2ADDMT0ZE : 1; /*!< [2..2] MTU0 High-Impedance POE4F Add                                      */
30096             uint16_t                   : 1;
30097             __IOM uint16_t IC4ADDMT0ZE : 1; /*!< [4..4] MTU0 High-Impedance POE10F Add                                     */
30098             __IOM uint16_t IC5ADDMT0ZE : 1; /*!< [5..5] MTU0 High-Impedance POE11F Add                                     */
30099             __IOM uint16_t DE0ADDMT0ZE : 1; /*!< [6..6] MTU0 High-Impedance DERR0ST Add                                    */
30100             __IOM uint16_t DE1ADDMT0ZE : 1; /*!< [7..7] MTU0 High-Impedance DERR1ST Add                                    */
30101             uint16_t                   : 8;
30102         } POECR5_b;
30103     };
30104     __IM uint16_t RESERVED1;
30105 
30106     union
30107     {
30108         __IOM uint16_t ICSR4;          /*!< (@ 0x00000016) Input Level Control/Status Register 4                      */
30109 
30110         struct
30111         {
30112             __IOM uint16_t POE10M : 2; /*!< [1..0] POE10 Mode Select                                                  */
30113             uint16_t              : 6;
30114             __IOM uint16_t PIE4   : 1; /*!< [8..8] Port Interrupt Enable 4                                            */
30115             __IOM uint16_t POE10E : 1; /*!< [9..9] POE10 High-Impedance Enable                                        */
30116             uint16_t              : 2;
30117             __IOM uint16_t POE10F : 1; /*!< [12..12] POE10 Flag                                                       */
30118             uint16_t              : 3;
30119         } ICSR4_b;
30120     };
30121 
30122     union
30123     {
30124         __IOM uint16_t ICSR5;          /*!< (@ 0x00000018) Input Level Control/Status Register 5                      */
30125 
30126         struct
30127         {
30128             __IOM uint16_t POE11M : 2; /*!< [1..0] POE11 Mode Select                                                  */
30129             uint16_t              : 6;
30130             __IOM uint16_t PIE5   : 1; /*!< [8..8] Port Interrupt Enable 5                                            */
30131             __IOM uint16_t POE11E : 1; /*!< [9..9] POE11 High-Impedance Enable                                        */
30132             uint16_t              : 2;
30133             __IOM uint16_t POE11F : 1; /*!< [12..12] POE11 Flag                                                       */
30134             uint16_t              : 3;
30135         } ICSR5_b;
30136     };
30137 
30138     union
30139     {
30140         __IOM uint16_t ALR1;           /*!< (@ 0x0000001A) Active Level Setting Register 1                            */
30141 
30142         struct
30143         {
30144             __IOM uint16_t OLSG0A : 1; /*!< [0..0] MTIOC3B Pin Active Level Setting                                   */
30145             __IOM uint16_t OLSG0B : 1; /*!< [1..1] MTIOC3D Pin Active Level Setting                                   */
30146             __IOM uint16_t OLSG1A : 1; /*!< [2..2] MTIOC4A Pin Active Level Setting                                   */
30147             __IOM uint16_t OLSG1B : 1; /*!< [3..3] MTIOC4C Pin Active Level Setting                                   */
30148             __IOM uint16_t OLSG2A : 1; /*!< [4..4] MTIOC4B Pin Active Level Setting                                   */
30149             __IOM uint16_t OLSG2B : 1; /*!< [5..5] MTIOC4D Pin Active Level Setting                                   */
30150             uint16_t              : 1;
30151             __IOM uint16_t OLSEN  : 1; /*!< [7..7] Active Level Setting Enable                                        */
30152             uint16_t              : 8;
30153         } ALR1_b;
30154     };
30155 
30156     union
30157     {
30158         __IOM uint16_t ICSR6;          /*!< (@ 0x0000001C) Input Level Control/Status Register 6                      */
30159 
30160         struct
30161         {
30162             uint16_t              : 9;
30163             __IOM uint16_t OSTSTE : 1; /*!< [9..9] Oscillation Stop High-Impedance Enable                             */
30164             uint16_t              : 2;
30165             __IOM uint16_t OSTSTF : 1; /*!< [12..12] Oscillation Stop High-Impedance Flag                             */
30166             uint16_t              : 3;
30167         } ICSR6_b;
30168     };
30169 
30170     union
30171     {
30172         __IOM uint16_t ICSR7;          /*!< (@ 0x0000001E) Input Level Control/Status Register 7                      */
30173 
30174         struct
30175         {
30176             uint16_t               : 6;
30177             __IOM uint16_t DERR0IE : 1; /*!< [6..6] DSMIF0 Error Interrupt Enable                                      */
30178             __IOM uint16_t DERR1IE : 1; /*!< [7..7] DSMIF1 Error Interrupt Enable                                      */
30179             uint16_t               : 5;
30180             __IM uint16_t DERR0ST  : 1; /*!< [13..13] DSMIF0 Error Status                                              */
30181             __IM uint16_t DERR1ST  : 1; /*!< [14..14] DSMIF1 Error Status                                              */
30182             uint16_t               : 1;
30183         } ICSR7_b;
30184     };
30185     __IM uint16_t RESERVED2[2];
30186 
30187     union
30188     {
30189         __IOM uint8_t M0SELR1;         /*!< (@ 0x00000024) MTU0 Pin Select Register 1                                 */
30190 
30191         struct
30192         {
30193             __IOM uint8_t M0ASEL : 4;  /*!< [3..0] MTU0-A (MTIOC0A) Pin Select                                        */
30194             __IOM uint8_t M0BSEL : 4;  /*!< [7..4] MTU0-B (MTIOC0B) Pin Select                                        */
30195         } M0SELR1_b;
30196     };
30197 
30198     union
30199     {
30200         __IOM uint8_t M0SELR2;         /*!< (@ 0x00000025) MTU0 Pin Select Register 2                                 */
30201 
30202         struct
30203         {
30204             __IOM uint8_t M0CSEL : 4;  /*!< [3..0] MTU0-C (MTIOC0C) Pin Select                                        */
30205             __IOM uint8_t M0DSEL : 4;  /*!< [7..4] MTU0-D (MTIOC0D) Pin Select                                        */
30206         } M0SELR2_b;
30207     };
30208 
30209     union
30210     {
30211         __IOM uint8_t M3SELR;          /*!< (@ 0x00000026) MTU3 Pin Select Register                                   */
30212 
30213         struct
30214         {
30215             __IOM uint8_t M3BSEL : 4;  /*!< [3..0] MTU3-B (MTIOC3B) Pin Select                                        */
30216             __IOM uint8_t M3DSEL : 4;  /*!< [7..4] MTU3-D (MTIOC3D) Pin Select                                        */
30217         } M3SELR_b;
30218     };
30219 
30220     union
30221     {
30222         __IOM uint8_t M4SELR1;         /*!< (@ 0x00000027) MTU4 Pin Select Register 1                                 */
30223 
30224         struct
30225         {
30226             __IOM uint8_t M4ASEL : 4;  /*!< [3..0] MTU4-A (MTIOC4A) Pin Select                                        */
30227             __IOM uint8_t M4CSEL : 4;  /*!< [7..4] MTU4-C (MTIOC4C) Pin Select                                        */
30228         } M4SELR1_b;
30229     };
30230 
30231     union
30232     {
30233         __IOM uint8_t M4SELR2;         /*!< (@ 0x00000028) MTU4 Pin Select Register 2                                 */
30234 
30235         struct
30236         {
30237             __IOM uint8_t M4BSEL : 4;  /*!< [3..0] MTU4-B (MTIOC4B) Pin Select                                        */
30238             __IOM uint8_t M4DSEL : 4;  /*!< [7..4] MTU4-D (MTIOC4D) Pin Select                                        */
30239         } M4SELR2_b;
30240     };
30241     __IM uint8_t RESERVED3;
30242 
30243     union
30244     {
30245         __IOM uint8_t M6SELR;          /*!< (@ 0x0000002A) MTU6 Pin Select Register                                   */
30246 
30247         struct
30248         {
30249             __IOM uint8_t M6BSEL : 4;  /*!< [3..0] MTU6-B (MTIOC6B) Pin Select                                        */
30250             __IOM uint8_t M6DSEL : 4;  /*!< [7..4] MTU6-D (MTIOC6D) Pin Select                                        */
30251         } M6SELR_b;
30252     };
30253 
30254     union
30255     {
30256         __IOM uint8_t M7SELR1;         /*!< (@ 0x0000002B) MTU7 Pin Select Register 1                                 */
30257 
30258         struct
30259         {
30260             __IOM uint8_t M7ASEL : 4;  /*!< [3..0] MTU7-A (MTIOC7A) Pin Select                                        */
30261             __IOM uint8_t M7CSEL : 4;  /*!< [7..4] MTU7-C (MTIOC7C) Pin Select                                        */
30262         } M7SELR1_b;
30263     };
30264 
30265     union
30266     {
30267         __IOM uint8_t M7SELR2;         /*!< (@ 0x0000002C) MTU7 Pin Select Register 2                                 */
30268 
30269         struct
30270         {
30271             __IOM uint8_t M7BSEL : 4;  /*!< [3..0] MTU7-B (MTIOC7B) Pin Select                                        */
30272             __IOM uint8_t M7DSEL : 4;  /*!< [7..4] MTU7-D (MTIOC7D) Pin Select                                        */
30273         } M7SELR2_b;
30274     };
30275     __IM uint8_t  RESERVED4;
30276     __IM uint16_t RESERVED5;
30277 } R_POE3_Type;                         /*!< Size = 48 (0x30)                                                          */
30278 
30279 /* =========================================================================================================================== */
30280 /* ================                                          R_POEG0                                          ================ */
30281 /* =========================================================================================================================== */
30282 
30283 /**
30284  * @brief GPT Port Output Enable 0 (R_POEG0)
30285  */
30286 
30287 typedef struct                          /*!< (@ 0x90006000) R_POEG0 Structure                                          */
30288 {
30289     union
30290     {
30291         __IOM uint32_t POEG0GA;         /*!< (@ 0x00000000) POEG0 Group A Setting Register                             */
30292 
30293         struct
30294         {
30295             __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
30296             __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
30297             __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
30298             __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
30299             __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
30300             __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
30301             __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
30302             uint32_t               : 9;
30303             __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
30304             uint32_t               : 7;
30305             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
30306             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
30307             __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
30308             __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
30309             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
30310             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
30311             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
30312         } POEG0GA_b;
30313     };
30314     __IM uint32_t RESERVED[255];
30315 
30316     union
30317     {
30318         __IOM uint32_t POEG0GB;         /*!< (@ 0x00000400) POEG0 Group B Setting Register                             */
30319 
30320         struct
30321         {
30322             __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
30323             __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
30324             __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
30325             __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
30326             __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
30327             __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
30328             __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
30329             uint32_t               : 9;
30330             __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
30331             uint32_t               : 7;
30332             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
30333             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
30334             __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
30335             __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
30336             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
30337             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
30338             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
30339         } POEG0GB_b;
30340     };
30341     __IM uint32_t RESERVED1[255];
30342 
30343     union
30344     {
30345         __IOM uint32_t POEG0GC;         /*!< (@ 0x00000800) POEG0 Group C Setting Register                             */
30346 
30347         struct
30348         {
30349             __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
30350             __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
30351             __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
30352             __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
30353             __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
30354             __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
30355             __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
30356             uint32_t               : 9;
30357             __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
30358             uint32_t               : 7;
30359             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
30360             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
30361             __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
30362             __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
30363             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
30364             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
30365             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
30366         } POEG0GC_b;
30367     };
30368     __IM uint32_t RESERVED2[255];
30369 
30370     union
30371     {
30372         __IOM uint32_t POEG0GD;         /*!< (@ 0x00000C00) POEG0 Group D Setting Register                             */
30373 
30374         struct
30375         {
30376             __IOM uint32_t PIDF    : 1; /*!< [0..0] Port Input Detection Flag                                          */
30377             __IOM uint32_t IOCF    : 1; /*!< [1..1] GPT Output Stop Request Detection Flag                             */
30378             __IOM uint32_t OSTPF   : 1; /*!< [2..2] Oscillation Stop Detection Flag                                    */
30379             __IOM uint32_t SSF     : 1; /*!< [3..3] Software Stop Flag                                                 */
30380             __IOM uint32_t PIDE    : 1; /*!< [4..4] Port Input Detection Enable                                        */
30381             __IOM uint32_t IOCE    : 1; /*!< [5..5] GPT Output Stop Request Enable                                     */
30382             __IOM uint32_t OSTPE   : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation                  */
30383             uint32_t               : 9;
30384             __IM uint32_t ST       : 1; /*!< [16..16] GTETRGn Input Status Flag                                        */
30385             uint32_t               : 7;
30386             __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status                                              */
30387             __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status                                              */
30388             __IOM uint32_t DERR0E  : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection                 */
30389             __IOM uint32_t DERR1E  : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection                 */
30390             __IOM uint32_t INV     : 1; /*!< [28..28] GTETRGn Input Inverting                                          */
30391             __IOM uint32_t NFEN    : 1; /*!< [29..29] Noise filter Enable                                              */
30392             __IOM uint32_t NFCS    : 2; /*!< [31..30] Noise filter Clock Select                                        */
30393         } POEG0GD_b;
30394     };
30395 } R_POEG0_Type;                         /*!< Size = 3076 (0xc04)                                                       */
30396 
30397 /* =========================================================================================================================== */
30398 /* ================                                         R_DSMIF0                                          ================ */
30399 /* =========================================================================================================================== */
30400 
30401 /**
30402  * @brief Delta-sigma Interface 0 (R_DSMIF0)
30403  */
30404 
30405 typedef struct                         /*!< (@ 0x90008000) R_DSMIF0 Structure                                         */
30406 {
30407     __IM uint32_t RESERVED[16];
30408 
30409     union
30410     {
30411         __IOM uint32_t DSSEICR;        /*!< (@ 0x00000040) Overcurrent Sum Error Detect Interrupt Control
30412                                         *                  Register                                                   */
30413 
30414         struct
30415         {
30416             __IOM uint32_t ISEL : 1;   /*!< [0..0] Overcurrent sum error lower limit detection interrupt
30417                                         *   enable bit                                                                */
30418             __IOM uint32_t ISEH : 1;   /*!< [1..1] Overcurrent sum error upper limit detection interrupt
30419                                         *   enable bit                                                                */
30420             uint32_t : 30;
30421         } DSSEICR_b;
30422     };
30423 
30424     union
30425     {
30426         __IOM uint32_t DSSECSR;        /*!< (@ 0x00000044) Overcurrent Sum Error Detect Channel Setting
30427                                         *                  Register                                                   */
30428 
30429         struct
30430         {
30431             __IOM uint32_t SEDM : 3;   /*!< [2..0] Overcurrent sum error detect mode setting bit                      */
30432             uint32_t            : 29;
30433         } DSSECSR_b;
30434     };
30435 
30436     union
30437     {
30438         __IOM uint32_t DSSELTR;          /*!< (@ 0x00000048) Overcurrent Sum Error Detect Low Threshold Register        */
30439 
30440         struct
30441         {
30442             __IOM uint32_t SCMPTBL : 18; /*!< [17..0] Overcurrent sum error detect lower limit                          */
30443             uint32_t               : 14;
30444         } DSSELTR_b;
30445     };
30446 
30447     union
30448     {
30449         __IOM uint32_t DSSEHTR;          /*!< (@ 0x0000004C) Overcurrent Sum Error Detect High Threshold Register       */
30450 
30451         struct
30452         {
30453             __IOM uint32_t SCMPTBH : 18; /*!< [17..0] Overcurrent sum error detect upper limit                          */
30454             uint32_t               : 14;
30455         } DSSEHTR_b;
30456     };
30457 
30458     union
30459     {
30460         __IOM uint32_t DSSECR;         /*!< (@ 0x00000050) Overcurrent Sum Error Detect Control Register              */
30461 
30462         struct
30463         {
30464             __IOM uint32_t SEEL : 1;   /*!< [0..0] Overcurrent sum error lower limit detection enable bit             */
30465             __IOM uint32_t SEEH : 1;   /*!< [1..1] Overcurrent sum error upper limit detection enable bit             */
30466             uint32_t            : 30;
30467         } DSSECR_b;
30468     };
30469     __IM uint32_t RESERVED1[3];
30470 
30471     union
30472     {
30473         __IOM uint32_t DSSECDR[3];     /*!< (@ 0x00000060) Overcurrent Sum Error Detect Capture Data Register
30474                                         *                  [0..2]                                                     */
30475 
30476         struct
30477         {
30478             __IOM uint32_t SECDR : 16; /*!< [15..0] Overcurrent sum error detect capture data n                       */
30479             uint32_t             : 16;
30480         } DSSECDR_b[3];
30481     };
30482     __IM uint32_t RESERVED2[37];
30483 
30484     union
30485     {
30486         __IOM uint32_t DSCSTRTR;        /*!< (@ 0x00000100) Channel Software Start Trigger Register                    */
30487 
30488         struct
30489         {
30490             __IOM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger                                            */
30491             __IOM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger                                            */
30492             __IOM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger                                            */
30493             uint32_t               : 29;
30494         } DSCSTRTR_b;
30495     };
30496 
30497     union
30498     {
30499         __IOM uint32_t DSCSTPTR;        /*!< (@ 0x00000104) Channel Software Stop Trigger Register                     */
30500 
30501         struct
30502         {
30503             __IOM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger                                             */
30504             __IOM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger                                             */
30505             __IOM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger                                             */
30506             uint32_t               : 29;
30507         } DSCSTPTR_b;
30508     };
30509     __IM uint32_t RESERVED3[2];
30510 
30511     union
30512     {
30513         __IM uint32_t DSCESR;          /*!< (@ 0x00000110) Channel Error Status Register                              */
30514 
30515         struct
30516         {
30517             __IM uint32_t OCFL0   : 1; /*!< [0..0] Channel 0 overcurrent lower limit detection flag                   */
30518             __IM uint32_t OCFL1   : 1; /*!< [1..1] Channel 1 overcurrent lower limit detection flag                   */
30519             __IM uint32_t OCFL2   : 1; /*!< [2..2] Channel 2 overcurrent lower limit detection flag                   */
30520             uint32_t              : 1;
30521             __IM uint32_t OCFH0   : 1; /*!< [4..4] Channel 0 overcurrent upper limit detection flag                   */
30522             __IM uint32_t OCFH1   : 1; /*!< [5..5] Channel 1 overcurrent upper limit detection flag                   */
30523             __IM uint32_t OCFH2   : 1; /*!< [6..6] Channel 2 overcurrent upper limit detection flag                   */
30524             uint32_t              : 1;
30525             __IM uint32_t SCF0    : 1; /*!< [8..8] Channel 0 short circuit detection flag                             */
30526             __IM uint32_t SCF1    : 1; /*!< [9..9] Channel 1 short circuit detection flag                             */
30527             __IM uint32_t SCF2    : 1; /*!< [10..10] Channel 2 short circuit detection flag                           */
30528             uint32_t              : 5;
30529             __IM uint32_t SUMERRL : 1; /*!< [16..16] Overcurrent sum error lower limit detection flag                 */
30530             __IM uint32_t SUMERRH : 1; /*!< [17..17] Overcurrent sum error upper limit detection flag                 */
30531             uint32_t              : 14;
30532         } DSCESR_b;
30533     };
30534     __IM uint32_t RESERVED4;
30535 
30536     union
30537     {
30538         __IM uint32_t DSCSR;           /*!< (@ 0x00000118) Channel Status Register                                    */
30539 
30540         struct
30541         {
30542             __IM uint32_t DUF0 : 1;    /*!< [0..0] Channel 0 Data Update flag                                         */
30543             __IM uint32_t DUF1 : 1;    /*!< [1..1] Channel 1 Data Update flag                                         */
30544             __IM uint32_t DUF2 : 1;    /*!< [2..2] Channel 2 Data Update flag                                         */
30545             uint32_t           : 29;
30546         } DSCSR_b;
30547     };
30548 
30549     union
30550     {
30551         __IM uint32_t DSCSSR;           /*!< (@ 0x0000011C) Channel State Status Register                              */
30552 
30553         struct
30554         {
30555             __IM uint32_t CHSTATE0 : 1; /*!< [0..0] Channel 0 state                                                    */
30556             uint32_t               : 3;
30557             __IM uint32_t CHSTATE1 : 1; /*!< [4..4] Channel 1 state                                                    */
30558             uint32_t               : 3;
30559             __IM uint32_t CHSTATE2 : 1; /*!< [8..8] Channel 2 state                                                    */
30560             uint32_t               : 23;
30561         } DSCSSR_b;
30562     };
30563 
30564     union
30565     {
30566         __OM uint32_t DSCESCR;            /*!< (@ 0x00000120) Channel Error Status Clear Register                        */
30567 
30568         struct
30569         {
30570             __OM uint32_t CLROCFL0   : 1; /*!< [0..0] Channel 0 Overcurrent Lower Limit Detection Flag Clear             */
30571             __OM uint32_t CLROCFL1   : 1; /*!< [1..1] Channel 1 Overcurrent Lower Limit Detection Flag Clear             */
30572             __OM uint32_t CLROCFL2   : 1; /*!< [2..2] Channel 2 Overcurrent Lower Limit Detection Flag Clear             */
30573             uint32_t                 : 1;
30574             __OM uint32_t CLROCFH0   : 1; /*!< [4..4] Channel 0 Overcurrent Upper Limit Detection Flag Clear             */
30575             __OM uint32_t CLROCFH1   : 1; /*!< [5..5] Channel 1 Overcurrent Upper Limit Detection Flag Clear             */
30576             __OM uint32_t CLROCFH2   : 1; /*!< [6..6] Channel 2 Overcurrent Upper Limit Detection Flag Clear             */
30577             uint32_t                 : 1;
30578             __OM uint32_t CLRSCF0    : 1; /*!< [8..8] Channel 0 Short Circuit Detection Flag Clear                       */
30579             __OM uint32_t CLRSCF1    : 1; /*!< [9..9] Channel 1 Short Circuit Detection Flag Clear                       */
30580             __OM uint32_t CLRSCF2    : 1; /*!< [10..10] Channel 2 Short Circuit Detection Flag Clear                     */
30581             uint32_t                 : 5;
30582             __OM uint32_t CLRSUMERRL : 1; /*!< [16..16] Overcurrent Sum Error Lower Limit Detection Flag Clear           */
30583             __OM uint32_t CLRSUMERRH : 1; /*!< [17..17] Overcurrent Sum Error Upper Limit Detection Flag Clear           */
30584             uint32_t                 : 14;
30585         } DSCESCR_b;
30586     };
30587     __IM uint32_t RESERVED5;
30588 
30589     union
30590     {
30591         __OM uint32_t DSCSCR;          /*!< (@ 0x00000128) Channel Status Clear Register                              */
30592 
30593         struct
30594         {
30595             __OM uint32_t CLRDUF0 : 1; /*!< [0..0] Channel 0 Data Update Flag Clear                                   */
30596             __OM uint32_t CLRDUF1 : 1; /*!< [1..1] Channel 1 Data Update Flag Clear                                   */
30597             __OM uint32_t CLRDUF2 : 1; /*!< [2..2] Channel 2 Data Update Flag Clear                                   */
30598             uint32_t              : 29;
30599         } DSCSCR_b;
30600     };
30601     __IM uint32_t          RESERVED6[21];
30602     __IOM R_DSMIF0_CH_Type CH[3];      /*!< (@ 0x00000180) Channel Registers [0..2]                                   */
30603 } R_DSMIF0_Type;                       /*!< Size = 816 (0x330)                                                        */
30604 
30605 /* =========================================================================================================================== */
30606 /* ================                                           R_GSC                                           ================ */
30607 /* =========================================================================================================================== */
30608 
30609 /**
30610  * @brief Global System Counter (R_GSC)
30611  */
30612 
30613 typedef struct                         /*!< (@ 0xC0060000) R_GSC Structure                                            */
30614 {
30615     union
30616     {
30617         __IOM uint32_t CNTCR;          /*!< (@ 0x00000000) Global System Counter Control Register                     */
30618 
30619         struct
30620         {
30621             __IOM uint32_t EN   : 1;   /*!< [0..0] Counter Enable                                                     */
30622             __IOM uint32_t HDBG : 1;   /*!< [1..1] Halt on Debug                                                      */
30623             uint32_t            : 30;
30624         } CNTCR_b;
30625     };
30626 
30627     union
30628     {
30629         __IM uint32_t CNTSR;           /*!< (@ 0x00000004) Global System Counter Status Register                      */
30630 
30631         struct
30632         {
30633             uint32_t           : 1;
30634             __IM uint32_t DBGH : 1;    /*!< [1..1] Debug Halted                                                       */
30635             uint32_t           : 30;
30636         } CNTSR_b;
30637     };
30638 
30639     union
30640     {
30641         __IOM uint32_t CNTCVL;               /*!< (@ 0x00000008) Global System Counter Current Value Lower Register         */
30642 
30643         struct
30644         {
30645             __IOM uint32_t CNTCVL_L_32 : 32; /*!< [31..0] Current value of the counter, lower 32 bits                       */
30646         } CNTCVL_b;
30647     };
30648 
30649     union
30650     {
30651         __IOM uint32_t CNTCVU;               /*!< (@ 0x0000000C) Global System Counter Current Value Upper Register         */
30652 
30653         struct
30654         {
30655             __IOM uint32_t CNTCVU_U_32 : 32; /*!< [31..0] Current value of the counter, upper 32 bits                       */
30656         } CNTCVU_b;
30657     };
30658     __IM uint32_t RESERVED[4];
30659 
30660     union
30661     {
30662         __IOM uint32_t CNTFID0;        /*!< (@ 0x00000020) Global System Counter Base Frequency ID Register           */
30663 
30664         struct
30665         {
30666             __IOM uint32_t FREQ : 32;  /*!< [31..0] Frequency in number of ticks per second                           */
30667         } CNTFID0_b;
30668     };
30669 } R_GSC_Type;                          /*!< Size = 36 (0x24)                                                          */
30670 
30671 /** @} */ /* End of group Device_Peripheral_peripherals */
30672 
30673 /* =========================================================================================================================== */
30674 /* ================                          Device Specific Peripheral Address Map                           ================ */
30675 /* =========================================================================================================================== */
30676 
30677 /** @addtogroup Device_Peripheral_peripheralAddr
30678  * @{
30679  */
30680 
30681  #define R_GPT7_BASE           0x80000000UL
30682  #define R_GPT8_BASE           0x80000100UL
30683  #define R_GPT9_BASE           0x80000200UL
30684  #define R_GPT10_BASE          0x80000300UL
30685  #define R_GPT11_BASE          0x80000400UL
30686  #define R_GPT12_BASE          0x80000500UL
30687  #define R_GPT13_BASE          0x80000600UL
30688  #define R_SCI0_BASE           0x80001000UL
30689  #define R_SCI1_BASE           0x80001400UL
30690  #define R_SCI2_BASE           0x80001800UL
30691  #define R_SCI3_BASE           0x80001C00UL
30692  #define R_SCI4_BASE           0x80002000UL
30693  #define R_SPI0_BASE           0x80003000UL
30694  #define R_SPI1_BASE           0x80003400UL
30695  #define R_SPI2_BASE           0x80003800UL
30696  #define R_CRC0_BASE           0x80004000UL
30697  #define R_CANFD_BASE          0x80020000UL
30698  #define R_CMT_BASE            0x80040000UL
30699  #define R_CMTW0_BASE          0x80041000UL
30700  #define R_CMTW1_BASE          0x80041400UL
30701  #define R_WDT0_BASE           0x80042000UL
30702  #define R_IIC0_BASE           0x80043000UL
30703  #define R_IIC1_BASE           0x80043400UL
30704  #define R_DOC_BASE            0x80044000UL
30705  #define R_ADC121_BASE         0x80045000UL
30706  #define R_TSU_BASE            0x80046000UL
30707  #define R_POEG1_BASE          0x80047000UL
30708  #define R_DMAC0_BASE          0x80080000UL
30709  #define R_DMAC1_BASE          0x80081000UL
30710  #define R_ICU_NS_BASE         0x80090000UL
30711  #define R_ELC_BASE            0x80090010UL
30712  #define R_DMA_BASE            0x80090060UL
30713  #define R_PORT_NSR_BASE       0x800A0000UL
30714  #define R_GMAC_BASE           0x80100000UL
30715  #define R_ETHSS_BASE          0x80110000UL
30716  #define R_ESC_INI_BASE        0x80110200UL
30717  #define R_ETHSW_PTP_BASE      0x80110400UL
30718  #define R_ETHSW_BASE          0x80120000UL
30719  #define R_ESC_BASE            0x80130000UL
30720  #define R_USBHC_BASE          0x80200000UL
30721  #define R_USBF_BASE           0x80201000UL
30722  #define R_BSC_BASE            0x80210000UL
30723  #define R_XSPI0_BASE          0x80220000UL
30724  #define R_XSPI1_BASE          0x80221000UL
30725  #define R_MBXSEM_BASE         0x80240000UL
30726  #define R_SHOSTIF_BASE        0x80241000UL
30727  #define R_PHOSTIF_BASE        0x80242000UL
30728  #define R_SYSC_NS_BASE        0x80280000UL
30729  #define R_ELO_BASE            0x80281200UL
30730  #define R_RWP_NS_BASE         0x80281A10UL
30731  #define R_GPT14_BASE          0x81000000UL
30732  #define R_GPT15_BASE          0x81000100UL
30733  #define R_GPT16_BASE          0x81000200UL
30734  #define R_GPT17_BASE          0x81000300UL
30735  #define R_SCI5_BASE           0x81001000UL
30736  #define R_SPI3_BASE           0x81002000UL
30737  #define R_CRC1_BASE           0x81003000UL
30738  #define R_IIC2_BASE           0x81008000UL
30739  #define R_RTC_BASE            0x81009000UL
30740  #define R_POEG2_BASE          0x8100A000UL
30741  #define R_OTP_BASE            0x81028000UL
30742  #define R_PORT_SR_BASE        0x81030000UL
30743  #define R_PTADR_BASE          0x81030C00UL
30744  #define R_SYSRAM0_BASE        0x81040000UL
30745  #define R_SYSRAM1_BASE        0x81041000UL
30746  #define R_SYSRAM2_BASE        0x81042000UL
30747  #define R_ICU_BASE            0x81048000UL
30748  #define R_SYSC_S_BASE         0x81280000UL
30749  #define R_CLMA0_BASE          0x81280800UL
30750  #define R_CLMA1_BASE          0x81280820UL
30751  #define R_CLMA2_BASE          0x81280840UL
30752  #define R_CLMA3_BASE          0x81280860UL
30753  #define R_MPU0_BASE           0x81281100UL
30754  #define R_MPU1_BASE           0x81281200UL
30755  #define R_MPU2_BASE           0x81281300UL
30756  #define R_MPU3_BASE           0x81281400UL
30757  #define R_MPU4_BASE           0x81281500UL
30758  #define R_MPU6_BASE           0x81281700UL
30759  #define R_SYSRAM_CTL_BASE     0x81281800UL
30760  #define R_SHOSTIF_CFG_BASE    0x81281920UL
30761  #define R_PHOSTIF_CFG_BASE    0x81281930UL
30762  #define R_RWP_S_BASE          0x81281A00UL
30763  #define R_MPU7_BASE           0x81281C00UL
30764  #define R_MPU8_BASE           0x81281D00UL
30765  #define R_MTU_BASE            0x90001000UL
30766  #define R_MTU3_BASE           0x90001100UL
30767  #define R_MTU4_BASE           0x90001200UL
30768  #define R_MTU_NF_BASE         0x90001290UL
30769  #define R_MTU0_BASE           0x90001300UL
30770  #define R_MTU1_BASE           0x90001380UL
30771  #define R_MTU2_BASE           0x90001400UL
30772  #define R_MTU8_BASE           0x90001600UL
30773  #define R_MTU6_BASE           0x90001900UL
30774  #define R_MTU7_BASE           0x90001A00UL
30775  #define R_MTU5_BASE           0x90001C00UL
30776  #define R_GPT0_BASE           0x90002000UL
30777  #define R_GPT1_BASE           0x90002100UL
30778  #define R_GPT2_BASE           0x90002200UL
30779  #define R_GPT3_BASE           0x90002300UL
30780  #define R_GPT4_BASE           0x90002400UL
30781  #define R_GPT5_BASE           0x90002500UL
30782  #define R_GPT6_BASE           0x90002600UL
30783  #define R_TFU_BASE            0x90003000UL
30784  #define R_ADC120_BASE         0x90004000UL
30785  #define R_POE3_BASE           0x90005000UL
30786  #define R_POEG0_BASE          0x90006000UL
30787  #define R_DSMIF0_BASE         0x90008000UL
30788  #define R_DSMIF1_BASE         0x90008400UL
30789  #define R_GSC_BASE            0xC0060000UL
30790 
30791 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
30792 
30793 /* =========================================================================================================================== */
30794 /* ================                                  Peripheral declaration                                   ================ */
30795 /* =========================================================================================================================== */
30796 
30797 /** @addtogroup Device_Peripheral_declaration
30798  * @{
30799  */
30800 
30801  #define R_GPT7           ((R_GPT0_Type *) R_GPT7_BASE)
30802  #define R_GPT8           ((R_GPT0_Type *) R_GPT8_BASE)
30803  #define R_GPT9           ((R_GPT0_Type *) R_GPT9_BASE)
30804  #define R_GPT10          ((R_GPT0_Type *) R_GPT10_BASE)
30805  #define R_GPT11          ((R_GPT0_Type *) R_GPT11_BASE)
30806  #define R_GPT12          ((R_GPT0_Type *) R_GPT12_BASE)
30807  #define R_GPT13          ((R_GPT0_Type *) R_GPT13_BASE)
30808  #define R_SCI0           ((R_SCI0_Type *) R_SCI0_BASE)
30809  #define R_SCI1           ((R_SCI0_Type *) R_SCI1_BASE)
30810  #define R_SCI2           ((R_SCI0_Type *) R_SCI2_BASE)
30811  #define R_SCI3           ((R_SCI0_Type *) R_SCI3_BASE)
30812  #define R_SCI4           ((R_SCI0_Type *) R_SCI4_BASE)
30813  #define R_SPI0           ((R_SPI0_Type *) R_SPI0_BASE)
30814  #define R_SPI1           ((R_SPI0_Type *) R_SPI1_BASE)
30815  #define R_SPI2           ((R_SPI0_Type *) R_SPI2_BASE)
30816  #define R_CRC0           ((R_CRC0_Type *) R_CRC0_BASE)
30817  #define R_CANFD          ((R_CANFD_Type *) R_CANFD_BASE)
30818  #define R_CMT            ((R_CMT_Type *) R_CMT_BASE)
30819  #define R_CMTW0          ((R_CMTW0_Type *) R_CMTW0_BASE)
30820  #define R_CMTW1          ((R_CMTW0_Type *) R_CMTW1_BASE)
30821  #define R_WDT0           ((R_WDT0_Type *) R_WDT0_BASE)
30822  #define R_IIC0           ((R_IIC0_Type *) R_IIC0_BASE)
30823  #define R_IIC1           ((R_IIC0_Type *) R_IIC1_BASE)
30824  #define R_DOC            ((R_DOC_Type *) R_DOC_BASE)
30825  #define R_ADC121         ((R_ADC121_Type *) R_ADC121_BASE)
30826  #define R_TSU            ((R_TSU_Type *) R_TSU_BASE)
30827  #define R_POEG1          ((R_POEG1_Type *) R_POEG1_BASE)
30828  #define R_DMAC0          ((R_DMAC0_Type *) R_DMAC0_BASE)
30829  #define R_DMAC1          ((R_DMAC0_Type *) R_DMAC1_BASE)
30830  #define R_ICU_NS         ((R_ICU_NS_Type *) R_ICU_NS_BASE)
30831  #define R_ELC            ((R_ELC_Type *) R_ELC_BASE)
30832  #define R_DMA            ((R_DMA_Type *) R_DMA_BASE)
30833  #define R_PORT_NSR       ((R_PORT_COMMON_Type *) R_PORT_NSR_BASE)
30834  #define R_GMAC           ((R_GMAC_Type *) R_GMAC_BASE)
30835  #define R_ETHSS          ((R_ETHSS_Type *) R_ETHSS_BASE)
30836  #define R_ESC_INI        ((R_ESC_INI_Type *) R_ESC_INI_BASE)
30837  #define R_ETHSW_PTP      ((R_ETHSW_PTP_Type *) R_ETHSW_PTP_BASE)
30838  #define R_ETHSW          ((R_ETHSW_Type *) R_ETHSW_BASE)
30839  #define R_ESC            ((R_ESC_Type *) R_ESC_BASE)
30840  #define R_USBHC          ((R_USBHC_Type *) R_USBHC_BASE)
30841  #define R_USBF           ((R_USBF_Type *) R_USBF_BASE)
30842  #define R_BSC            ((R_BSC_Type *) R_BSC_BASE)
30843  #define R_XSPI0          ((R_XSPI0_Type *) R_XSPI0_BASE)
30844  #define R_XSPI1          ((R_XSPI0_Type *) R_XSPI1_BASE)
30845  #define R_MBXSEM         ((R_MBXSEM_Type *) R_MBXSEM_BASE)
30846  #define R_SHOSTIF        ((R_SHOSTIF_Type *) R_SHOSTIF_BASE)
30847  #define R_PHOSTIF        ((R_PHOSTIF_Type *) R_PHOSTIF_BASE)
30848  #define R_SYSC_NS        ((R_SYSC_NS_Type *) R_SYSC_NS_BASE)
30849  #define R_ELO            ((R_ELO_Type *) R_ELO_BASE)
30850  #define R_RWP_NS         ((R_RWP_NS_Type *) R_RWP_NS_BASE)
30851  #define R_GPT14          ((R_GPT0_Type *) R_GPT14_BASE)
30852  #define R_GPT15          ((R_GPT0_Type *) R_GPT15_BASE)
30853  #define R_GPT16          ((R_GPT0_Type *) R_GPT16_BASE)
30854  #define R_GPT17          ((R_GPT0_Type *) R_GPT17_BASE)
30855  #define R_SCI5           ((R_SCI0_Type *) R_SCI5_BASE)
30856  #define R_SPI3           ((R_SPI0_Type *) R_SPI3_BASE)
30857  #define R_CRC1           ((R_CRC0_Type *) R_CRC1_BASE)
30858  #define R_IIC2           ((R_IIC0_Type *) R_IIC2_BASE)
30859  #define R_RTC            ((R_RTC_Type *) R_RTC_BASE)
30860  #define R_POEG2          ((R_POEG2_Type *) R_POEG2_BASE)
30861  #define R_OTP            ((R_OTP_Type *) R_OTP_BASE)
30862  #define R_PORT_SR        ((R_PORT_COMMON_Type *) R_PORT_SR_BASE)
30863  #define R_PTADR          ((R_PTADR_Type *) R_PTADR_BASE)
30864  #define R_SYSRAM0        ((R_SYSRAM0_Type *) R_SYSRAM0_BASE)
30865  #define R_SYSRAM1        ((R_SYSRAM0_Type *) R_SYSRAM1_BASE)
30866  #define R_SYSRAM2        ((R_SYSRAM0_Type *) R_SYSRAM2_BASE)
30867  #define R_ICU            ((R_ICU_Type *) R_ICU_BASE)
30868  #define R_SYSC_S         ((R_SYSC_S_Type *) R_SYSC_S_BASE)
30869  #define R_CLMA0          ((R_CLMA0_Type *) R_CLMA0_BASE)
30870  #define R_CLMA1          ((R_CLMA0_Type *) R_CLMA1_BASE)
30871  #define R_CLMA2          ((R_CLMA0_Type *) R_CLMA2_BASE)
30872  #define R_CLMA3          ((R_CLMA0_Type *) R_CLMA3_BASE)
30873  #define R_MPU0           ((R_MPU0_Type *) R_MPU0_BASE)
30874  #define R_MPU1           ((R_MPU0_Type *) R_MPU1_BASE)
30875  #define R_MPU2           ((R_MPU0_Type *) R_MPU2_BASE)
30876  #define R_MPU3           ((R_MPU3_Type *) R_MPU3_BASE)
30877  #define R_MPU4           ((R_MPU3_Type *) R_MPU4_BASE)
30878  #define R_MPU6           ((R_MPU0_Type *) R_MPU6_BASE)
30879  #define R_SYSRAM_CTL     ((R_SYSRAM_CTL_Type *) R_SYSRAM_CTL_BASE)
30880  #define R_SHOSTIF_CFG    ((R_SHOSTIF_CFG_Type *) R_SHOSTIF_CFG_BASE)
30881  #define R_PHOSTIF_CFG    ((R_PHOSTIF_CFG_Type *) R_PHOSTIF_CFG_BASE)
30882  #define R_RWP_S          ((R_RWP_S_Type *) R_RWP_S_BASE)
30883  #define R_MPU7           ((R_MPU3_Type *) R_MPU7_BASE)
30884  #define R_MPU8           ((R_MPU3_Type *) R_MPU8_BASE)
30885  #define R_MTU            ((R_MTU_Type *) R_MTU_BASE)
30886  #define R_MTU3           ((R_MTU3_Type *) R_MTU3_BASE)
30887  #define R_MTU4           ((R_MTU4_Type *) R_MTU4_BASE)
30888  #define R_MTU_NF         ((R_MTU_NF_Type *) R_MTU_NF_BASE)
30889  #define R_MTU0           ((R_MTU0_Type *) R_MTU0_BASE)
30890  #define R_MTU1           ((R_MTU1_Type *) R_MTU1_BASE)
30891  #define R_MTU2           ((R_MTU2_Type *) R_MTU2_BASE)
30892  #define R_MTU8           ((R_MTU8_Type *) R_MTU8_BASE)
30893  #define R_MTU6           ((R_MTU6_Type *) R_MTU6_BASE)
30894  #define R_MTU7           ((R_MTU7_Type *) R_MTU7_BASE)
30895  #define R_MTU5           ((R_MTU5_Type *) R_MTU5_BASE)
30896  #define R_GPT0           ((R_GPT0_Type *) R_GPT0_BASE)
30897  #define R_GPT1           ((R_GPT0_Type *) R_GPT1_BASE)
30898  #define R_GPT2           ((R_GPT0_Type *) R_GPT2_BASE)
30899  #define R_GPT3           ((R_GPT0_Type *) R_GPT3_BASE)
30900  #define R_GPT4           ((R_GPT0_Type *) R_GPT4_BASE)
30901  #define R_GPT5           ((R_GPT0_Type *) R_GPT5_BASE)
30902  #define R_GPT6           ((R_GPT0_Type *) R_GPT6_BASE)
30903  #define R_TFU            ((R_TFU_Type *) R_TFU_BASE)
30904  #define R_ADC120         ((R_ADC121_Type *) R_ADC120_BASE)
30905  #define R_POE3           ((R_POE3_Type *) R_POE3_BASE)
30906  #define R_POEG0          ((R_POEG0_Type *) R_POEG0_BASE)
30907  #define R_DSMIF0         ((R_DSMIF0_Type *) R_DSMIF0_BASE)
30908  #define R_DSMIF1         ((R_DSMIF0_Type *) R_DSMIF1_BASE)
30909  #define R_GSC            ((R_GSC_Type *) R_GSC_BASE)
30910 
30911 /** @} */ /* End of group Device_Peripheral_declaration */
30912 
30913 /* =========================================  End of section using anonymous unions  ========================================= */
30914  #if defined(__CC_ARM)
30915   #pragma pop
30916  #elif defined(__ICCARM__)
30917 
30918 /* leave anonymous unions enabled */
30919  #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
30920   #pragma clang diagnostic pop
30921  #elif defined(__GNUC__)
30922 
30923 /* anonymous unions are enabled by default */
30924  #elif defined(__TMS470__)
30925 
30926 /* anonymous unions are enabled by default */
30927  #elif defined(__TASKING__)
30928   #pragma warning restore
30929  #elif defined(__CSMC__)
30930 
30931 /* anonymous unions are enabled by default */
30932  #endif
30933 
30934 /* =========================================================================================================================== */
30935 /* ================                                 Pos/Mask Cluster Section                                  ================ */
30936 /* =========================================================================================================================== */
30937 
30938 /** @addtogroup PosMask_clusters
30939  * @{
30940  */
30941 
30942 /* =========================================================================================================================== */
30943 /* ================                                           CFDC                                            ================ */
30944 /* =========================================================================================================================== */
30945 
30946 /* =========================================================  NCFG  ========================================================== */
30947  #define R_CANFD_CFDC_NCFG_NBRP_Pos      (0UL)          /*!< NBRP (Bit 0)                                          */
30948  #define R_CANFD_CFDC_NCFG_NBRP_Msk      (0x3ffUL)      /*!< NBRP (Bitfield-Mask: 0x3ff)                           */
30949  #define R_CANFD_CFDC_NCFG_NSJW_Pos      (10UL)         /*!< NSJW (Bit 10)                                         */
30950  #define R_CANFD_CFDC_NCFG_NSJW_Msk      (0x1fc00UL)    /*!< NSJW (Bitfield-Mask: 0x7f)                            */
30951  #define R_CANFD_CFDC_NCFG_NTSEG1_Pos    (17UL)         /*!< NTSEG1 (Bit 17)                                       */
30952  #define R_CANFD_CFDC_NCFG_NTSEG1_Msk    (0x1fe0000UL)  /*!< NTSEG1 (Bitfield-Mask: 0xff)                          */
30953  #define R_CANFD_CFDC_NCFG_NTSEG2_Pos    (25UL)         /*!< NTSEG2 (Bit 25)                                       */
30954  #define R_CANFD_CFDC_NCFG_NTSEG2_Msk    (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f)                          */
30955 /* ==========================================================  CTR  ========================================================== */
30956  #define R_CANFD_CFDC_CTR_CHMDC_Pos      (0UL)          /*!< CHMDC (Bit 0)                                         */
30957  #define R_CANFD_CFDC_CTR_CHMDC_Msk      (0x3UL)        /*!< CHMDC (Bitfield-Mask: 0x03)                           */
30958  #define R_CANFD_CFDC_CTR_CSLPR_Pos      (2UL)          /*!< CSLPR (Bit 2)                                         */
30959  #define R_CANFD_CFDC_CTR_CSLPR_Msk      (0x4UL)        /*!< CSLPR (Bitfield-Mask: 0x01)                           */
30960  #define R_CANFD_CFDC_CTR_RTBO_Pos       (3UL)          /*!< RTBO (Bit 3)                                          */
30961  #define R_CANFD_CFDC_CTR_RTBO_Msk       (0x8UL)        /*!< RTBO (Bitfield-Mask: 0x01)                            */
30962  #define R_CANFD_CFDC_CTR_BEIE_Pos       (8UL)          /*!< BEIE (Bit 8)                                          */
30963  #define R_CANFD_CFDC_CTR_BEIE_Msk       (0x100UL)      /*!< BEIE (Bitfield-Mask: 0x01)                            */
30964  #define R_CANFD_CFDC_CTR_EWIE_Pos       (9UL)          /*!< EWIE (Bit 9)                                          */
30965  #define R_CANFD_CFDC_CTR_EWIE_Msk       (0x200UL)      /*!< EWIE (Bitfield-Mask: 0x01)                            */
30966  #define R_CANFD_CFDC_CTR_EPIE_Pos       (10UL)         /*!< EPIE (Bit 10)                                         */
30967  #define R_CANFD_CFDC_CTR_EPIE_Msk       (0x400UL)      /*!< EPIE (Bitfield-Mask: 0x01)                            */
30968  #define R_CANFD_CFDC_CTR_BOEIE_Pos      (11UL)         /*!< BOEIE (Bit 11)                                        */
30969  #define R_CANFD_CFDC_CTR_BOEIE_Msk      (0x800UL)      /*!< BOEIE (Bitfield-Mask: 0x01)                           */
30970  #define R_CANFD_CFDC_CTR_BORIE_Pos      (12UL)         /*!< BORIE (Bit 12)                                        */
30971  #define R_CANFD_CFDC_CTR_BORIE_Msk      (0x1000UL)     /*!< BORIE (Bitfield-Mask: 0x01)                           */
30972  #define R_CANFD_CFDC_CTR_OLIE_Pos       (13UL)         /*!< OLIE (Bit 13)                                         */
30973  #define R_CANFD_CFDC_CTR_OLIE_Msk       (0x2000UL)     /*!< OLIE (Bitfield-Mask: 0x01)                            */
30974  #define R_CANFD_CFDC_CTR_BLIE_Pos       (14UL)         /*!< BLIE (Bit 14)                                         */
30975  #define R_CANFD_CFDC_CTR_BLIE_Msk       (0x4000UL)     /*!< BLIE (Bitfield-Mask: 0x01)                            */
30976  #define R_CANFD_CFDC_CTR_ALIE_Pos       (15UL)         /*!< ALIE (Bit 15)                                         */
30977  #define R_CANFD_CFDC_CTR_ALIE_Msk       (0x8000UL)     /*!< ALIE (Bitfield-Mask: 0x01)                            */
30978  #define R_CANFD_CFDC_CTR_TAIE_Pos       (16UL)         /*!< TAIE (Bit 16)                                         */
30979  #define R_CANFD_CFDC_CTR_TAIE_Msk       (0x10000UL)    /*!< TAIE (Bitfield-Mask: 0x01)                            */
30980  #define R_CANFD_CFDC_CTR_EOCOIE_Pos     (17UL)         /*!< EOCOIE (Bit 17)                                       */
30981  #define R_CANFD_CFDC_CTR_EOCOIE_Msk     (0x20000UL)    /*!< EOCOIE (Bitfield-Mask: 0x01)                          */
30982  #define R_CANFD_CFDC_CTR_SOCOIE_Pos     (18UL)         /*!< SOCOIE (Bit 18)                                       */
30983  #define R_CANFD_CFDC_CTR_SOCOIE_Msk     (0x40000UL)    /*!< SOCOIE (Bitfield-Mask: 0x01)                          */
30984  #define R_CANFD_CFDC_CTR_TDCVFIE_Pos    (19UL)         /*!< TDCVFIE (Bit 19)                                      */
30985  #define R_CANFD_CFDC_CTR_TDCVFIE_Msk    (0x80000UL)    /*!< TDCVFIE (Bitfield-Mask: 0x01)                         */
30986  #define R_CANFD_CFDC_CTR_BOM_Pos        (21UL)         /*!< BOM (Bit 21)                                          */
30987  #define R_CANFD_CFDC_CTR_BOM_Msk        (0x600000UL)   /*!< BOM (Bitfield-Mask: 0x03)                             */
30988  #define R_CANFD_CFDC_CTR_ERRD_Pos       (23UL)         /*!< ERRD (Bit 23)                                         */
30989  #define R_CANFD_CFDC_CTR_ERRD_Msk       (0x800000UL)   /*!< ERRD (Bitfield-Mask: 0x01)                            */
30990  #define R_CANFD_CFDC_CTR_CTME_Pos       (24UL)         /*!< CTME (Bit 24)                                         */
30991  #define R_CANFD_CFDC_CTR_CTME_Msk       (0x1000000UL)  /*!< CTME (Bitfield-Mask: 0x01)                            */
30992  #define R_CANFD_CFDC_CTR_CTMS_Pos       (25UL)         /*!< CTMS (Bit 25)                                         */
30993  #define R_CANFD_CFDC_CTR_CTMS_Msk       (0x6000000UL)  /*!< CTMS (Bitfield-Mask: 0x03)                            */
30994  #define R_CANFD_CFDC_CTR_CRCT_Pos       (30UL)         /*!< CRCT (Bit 30)                                         */
30995  #define R_CANFD_CFDC_CTR_CRCT_Msk       (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01)                            */
30996  #define R_CANFD_CFDC_CTR_ROM_Pos        (31UL)         /*!< ROM (Bit 31)                                          */
30997  #define R_CANFD_CFDC_CTR_ROM_Msk        (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01)                             */
30998 /* ==========================================================  STS  ========================================================== */
30999  #define R_CANFD_CFDC_STS_CRSTSTS_Pos    (0UL)          /*!< CRSTSTS (Bit 0)                                       */
31000  #define R_CANFD_CFDC_STS_CRSTSTS_Msk    (0x1UL)        /*!< CRSTSTS (Bitfield-Mask: 0x01)                         */
31001  #define R_CANFD_CFDC_STS_CHLTSTS_Pos    (1UL)          /*!< CHLTSTS (Bit 1)                                       */
31002  #define R_CANFD_CFDC_STS_CHLTSTS_Msk    (0x2UL)        /*!< CHLTSTS (Bitfield-Mask: 0x01)                         */
31003  #define R_CANFD_CFDC_STS_CSLPSTS_Pos    (2UL)          /*!< CSLPSTS (Bit 2)                                       */
31004  #define R_CANFD_CFDC_STS_CSLPSTS_Msk    (0x4UL)        /*!< CSLPSTS (Bitfield-Mask: 0x01)                         */
31005  #define R_CANFD_CFDC_STS_EPSTS_Pos      (3UL)          /*!< EPSTS (Bit 3)                                         */
31006  #define R_CANFD_CFDC_STS_EPSTS_Msk      (0x8UL)        /*!< EPSTS (Bitfield-Mask: 0x01)                           */
31007  #define R_CANFD_CFDC_STS_BOSTS_Pos      (4UL)          /*!< BOSTS (Bit 4)                                         */
31008  #define R_CANFD_CFDC_STS_BOSTS_Msk      (0x10UL)       /*!< BOSTS (Bitfield-Mask: 0x01)                           */
31009  #define R_CANFD_CFDC_STS_TRMSTS_Pos     (5UL)          /*!< TRMSTS (Bit 5)                                        */
31010  #define R_CANFD_CFDC_STS_TRMSTS_Msk     (0x20UL)       /*!< TRMSTS (Bitfield-Mask: 0x01)                          */
31011  #define R_CANFD_CFDC_STS_RECSTS_Pos     (6UL)          /*!< RECSTS (Bit 6)                                        */
31012  #define R_CANFD_CFDC_STS_RECSTS_Msk     (0x40UL)       /*!< RECSTS (Bitfield-Mask: 0x01)                          */
31013  #define R_CANFD_CFDC_STS_COMSTS_Pos     (7UL)          /*!< COMSTS (Bit 7)                                        */
31014  #define R_CANFD_CFDC_STS_COMSTS_Msk     (0x80UL)       /*!< COMSTS (Bitfield-Mask: 0x01)                          */
31015  #define R_CANFD_CFDC_STS_ESIF_Pos       (8UL)          /*!< ESIF (Bit 8)                                          */
31016  #define R_CANFD_CFDC_STS_ESIF_Msk       (0x100UL)      /*!< ESIF (Bitfield-Mask: 0x01)                            */
31017  #define R_CANFD_CFDC_STS_REC_Pos        (16UL)         /*!< REC (Bit 16)                                          */
31018  #define R_CANFD_CFDC_STS_REC_Msk        (0xff0000UL)   /*!< REC (Bitfield-Mask: 0xff)                             */
31019  #define R_CANFD_CFDC_STS_TEC_Pos        (24UL)         /*!< TEC (Bit 24)                                          */
31020  #define R_CANFD_CFDC_STS_TEC_Msk        (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff)                             */
31021 /* =========================================================  ERFL  ========================================================== */
31022  #define R_CANFD_CFDC_ERFL_BEF_Pos       (0UL)          /*!< BEF (Bit 0)                                           */
31023  #define R_CANFD_CFDC_ERFL_BEF_Msk       (0x1UL)        /*!< BEF (Bitfield-Mask: 0x01)                             */
31024  #define R_CANFD_CFDC_ERFL_EWF_Pos       (1UL)          /*!< EWF (Bit 1)                                           */
31025  #define R_CANFD_CFDC_ERFL_EWF_Msk       (0x2UL)        /*!< EWF (Bitfield-Mask: 0x01)                             */
31026  #define R_CANFD_CFDC_ERFL_EPF_Pos       (2UL)          /*!< EPF (Bit 2)                                           */
31027  #define R_CANFD_CFDC_ERFL_EPF_Msk       (0x4UL)        /*!< EPF (Bitfield-Mask: 0x01)                             */
31028  #define R_CANFD_CFDC_ERFL_BOEF_Pos      (3UL)          /*!< BOEF (Bit 3)                                          */
31029  #define R_CANFD_CFDC_ERFL_BOEF_Msk      (0x8UL)        /*!< BOEF (Bitfield-Mask: 0x01)                            */
31030  #define R_CANFD_CFDC_ERFL_BORF_Pos      (4UL)          /*!< BORF (Bit 4)                                          */
31031  #define R_CANFD_CFDC_ERFL_BORF_Msk      (0x10UL)       /*!< BORF (Bitfield-Mask: 0x01)                            */
31032  #define R_CANFD_CFDC_ERFL_OVLF_Pos      (5UL)          /*!< OVLF (Bit 5)                                          */
31033  #define R_CANFD_CFDC_ERFL_OVLF_Msk      (0x20UL)       /*!< OVLF (Bitfield-Mask: 0x01)                            */
31034  #define R_CANFD_CFDC_ERFL_BLF_Pos       (6UL)          /*!< BLF (Bit 6)                                           */
31035  #define R_CANFD_CFDC_ERFL_BLF_Msk       (0x40UL)       /*!< BLF (Bitfield-Mask: 0x01)                             */
31036  #define R_CANFD_CFDC_ERFL_ALF_Pos       (7UL)          /*!< ALF (Bit 7)                                           */
31037  #define R_CANFD_CFDC_ERFL_ALF_Msk       (0x80UL)       /*!< ALF (Bitfield-Mask: 0x01)                             */
31038  #define R_CANFD_CFDC_ERFL_SERR_Pos      (8UL)          /*!< SERR (Bit 8)                                          */
31039  #define R_CANFD_CFDC_ERFL_SERR_Msk      (0x100UL)      /*!< SERR (Bitfield-Mask: 0x01)                            */
31040  #define R_CANFD_CFDC_ERFL_FERR_Pos      (9UL)          /*!< FERR (Bit 9)                                          */
31041  #define R_CANFD_CFDC_ERFL_FERR_Msk      (0x200UL)      /*!< FERR (Bitfield-Mask: 0x01)                            */
31042  #define R_CANFD_CFDC_ERFL_AERR_Pos      (10UL)         /*!< AERR (Bit 10)                                         */
31043  #define R_CANFD_CFDC_ERFL_AERR_Msk      (0x400UL)      /*!< AERR (Bitfield-Mask: 0x01)                            */
31044  #define R_CANFD_CFDC_ERFL_CERR_Pos      (11UL)         /*!< CERR (Bit 11)                                         */
31045  #define R_CANFD_CFDC_ERFL_CERR_Msk      (0x800UL)      /*!< CERR (Bitfield-Mask: 0x01)                            */
31046  #define R_CANFD_CFDC_ERFL_B1ERR_Pos     (12UL)         /*!< B1ERR (Bit 12)                                        */
31047  #define R_CANFD_CFDC_ERFL_B1ERR_Msk     (0x1000UL)     /*!< B1ERR (Bitfield-Mask: 0x01)                           */
31048  #define R_CANFD_CFDC_ERFL_B0ERR_Pos     (13UL)         /*!< B0ERR (Bit 13)                                        */
31049  #define R_CANFD_CFDC_ERFL_B0ERR_Msk     (0x2000UL)     /*!< B0ERR (Bitfield-Mask: 0x01)                           */
31050  #define R_CANFD_CFDC_ERFL_ADERR_Pos     (14UL)         /*!< ADERR (Bit 14)                                        */
31051  #define R_CANFD_CFDC_ERFL_ADERR_Msk     (0x4000UL)     /*!< ADERR (Bitfield-Mask: 0x01)                           */
31052  #define R_CANFD_CFDC_ERFL_CRCREG_Pos    (16UL)         /*!< CRCREG (Bit 16)                                       */
31053  #define R_CANFD_CFDC_ERFL_CRCREG_Msk    (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff)                        */
31054 
31055 /* =========================================================================================================================== */
31056 /* ================                                           CFDC2                                           ================ */
31057 /* =========================================================================================================================== */
31058 
31059 /* =========================================================  DCFG  ========================================================== */
31060  #define R_CANFD_CFDC2_DCFG_DBRP_Pos       (0UL)          /*!< DBRP (Bit 0)                                          */
31061  #define R_CANFD_CFDC2_DCFG_DBRP_Msk       (0xffUL)       /*!< DBRP (Bitfield-Mask: 0xff)                            */
31062  #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos     (8UL)          /*!< DTSEG1 (Bit 8)                                        */
31063  #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk     (0x1f00UL)     /*!< DTSEG1 (Bitfield-Mask: 0x1f)                          */
31064  #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos     (16UL)         /*!< DTSEG2 (Bit 16)                                       */
31065  #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk     (0xf0000UL)    /*!< DTSEG2 (Bitfield-Mask: 0x0f)                          */
31066  #define R_CANFD_CFDC2_DCFG_DSJW_Pos       (24UL)         /*!< DSJW (Bit 24)                                         */
31067  #define R_CANFD_CFDC2_DCFG_DSJW_Msk       (0xf000000UL)  /*!< DSJW (Bitfield-Mask: 0x0f)                            */
31068 /* =========================================================  FDCFG  ========================================================= */
31069  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos    (0UL)          /*!< EOCCFG (Bit 0)                                        */
31070  #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk    (0x7UL)        /*!< EOCCFG (Bitfield-Mask: 0x07)                          */
31071  #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos     (8UL)          /*!< TDCOC (Bit 8)                                         */
31072  #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk     (0x100UL)      /*!< TDCOC (Bitfield-Mask: 0x01)                           */
31073  #define R_CANFD_CFDC2_FDCFG_TDCE_Pos      (9UL)          /*!< TDCE (Bit 9)                                          */
31074  #define R_CANFD_CFDC2_FDCFG_TDCE_Msk      (0x200UL)      /*!< TDCE (Bitfield-Mask: 0x01)                            */
31075  #define R_CANFD_CFDC2_FDCFG_ESIC_Pos      (10UL)         /*!< ESIC (Bit 10)                                         */
31076  #define R_CANFD_CFDC2_FDCFG_ESIC_Msk      (0x400UL)      /*!< ESIC (Bitfield-Mask: 0x01)                            */
31077  #define R_CANFD_CFDC2_FDCFG_TDCO_Pos      (16UL)         /*!< TDCO (Bit 16)                                         */
31078  #define R_CANFD_CFDC2_FDCFG_TDCO_Msk      (0xff0000UL)   /*!< TDCO (Bitfield-Mask: 0xff)                            */
31079  #define R_CANFD_CFDC2_FDCFG_GWEN_Pos      (24UL)         /*!< GWEN (Bit 24)                                         */
31080  #define R_CANFD_CFDC2_FDCFG_GWEN_Msk      (0x1000000UL)  /*!< GWEN (Bitfield-Mask: 0x01)                            */
31081  #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos     (25UL)         /*!< GWFDF (Bit 25)                                        */
31082  #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk     (0x2000000UL)  /*!< GWFDF (Bitfield-Mask: 0x01)                           */
31083  #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos     (26UL)         /*!< GWBRS (Bit 26)                                        */
31084  #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk     (0x4000000UL)  /*!< GWBRS (Bitfield-Mask: 0x01)                           */
31085  #define R_CANFD_CFDC2_FDCFG_FDOE_Pos      (28UL)         /*!< FDOE (Bit 28)                                         */
31086  #define R_CANFD_CFDC2_FDCFG_FDOE_Msk      (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01)                            */
31087  #define R_CANFD_CFDC2_FDCFG_REFE_Pos      (29UL)         /*!< REFE (Bit 29)                                         */
31088  #define R_CANFD_CFDC2_FDCFG_REFE_Msk      (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01)                            */
31089  #define R_CANFD_CFDC2_FDCFG_CLOE_Pos      (30UL)         /*!< CLOE (Bit 30)                                         */
31090  #define R_CANFD_CFDC2_FDCFG_CLOE_Msk      (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01)                            */
31091  #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos     (31UL)         /*!< CFDTE (Bit 31)                                        */
31092  #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk     (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01)                           */
31093 /* =========================================================  FDCTR  ========================================================= */
31094  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos    (0UL)          /*!< EOCCLR (Bit 0)                                        */
31095  #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk    (0x1UL)        /*!< EOCCLR (Bitfield-Mask: 0x01)                          */
31096  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos    (1UL)          /*!< SOCCLR (Bit 1)                                        */
31097  #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk    (0x2UL)        /*!< SOCCLR (Bitfield-Mask: 0x01)                          */
31098 /* =========================================================  FDSTS  ========================================================= */
31099  #define R_CANFD_CFDC2_FDSTS_TDCR_Pos      (0UL)          /*!< TDCR (Bit 0)                                          */
31100  #define R_CANFD_CFDC2_FDSTS_TDCR_Msk      (0xffUL)       /*!< TDCR (Bitfield-Mask: 0xff)                            */
31101  #define R_CANFD_CFDC2_FDSTS_EOCO_Pos      (8UL)          /*!< EOCO (Bit 8)                                          */
31102  #define R_CANFD_CFDC2_FDSTS_EOCO_Msk      (0x100UL)      /*!< EOCO (Bitfield-Mask: 0x01)                            */
31103  #define R_CANFD_CFDC2_FDSTS_SOCO_Pos      (9UL)          /*!< SOCO (Bit 9)                                          */
31104  #define R_CANFD_CFDC2_FDSTS_SOCO_Msk      (0x200UL)      /*!< SOCO (Bitfield-Mask: 0x01)                            */
31105  #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos     (15UL)         /*!< TDCVF (Bit 15)                                        */
31106  #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk     (0x8000UL)     /*!< TDCVF (Bitfield-Mask: 0x01)                           */
31107  #define R_CANFD_CFDC2_FDSTS_EOC_Pos       (16UL)         /*!< EOC (Bit 16)                                          */
31108  #define R_CANFD_CFDC2_FDSTS_EOC_Msk       (0xff0000UL)   /*!< EOC (Bitfield-Mask: 0xff)                             */
31109  #define R_CANFD_CFDC2_FDSTS_SOC_Pos       (24UL)         /*!< SOC (Bit 24)                                          */
31110  #define R_CANFD_CFDC2_FDSTS_SOC_Msk       (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff)                             */
31111 /* =========================================================  FDCRC  ========================================================= */
31112  #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos    (0UL)          /*!< CRCREG (Bit 0)                                        */
31113  #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk    (0x1fffffUL)   /*!< CRCREG (Bitfield-Mask: 0x1fffff)                      */
31114  #define R_CANFD_CFDC2_FDCRC_SCNT_Pos      (25UL)         /*!< SCNT (Bit 25)                                         */
31115  #define R_CANFD_CFDC2_FDCRC_SCNT_Msk      (0x1e000000UL) /*!< SCNT (Bitfield-Mask: 0x0f)                            */
31116 /* =========================================================  BLCT  ========================================================== */
31117  #define R_CANFD_CFDC2_BLCT_BLCE_Pos       (0UL)          /*!< BLCE (Bit 0)                                          */
31118  #define R_CANFD_CFDC2_BLCT_BLCE_Msk       (0x1UL)        /*!< BLCE (Bitfield-Mask: 0x01)                            */
31119  #define R_CANFD_CFDC2_BLCT_BLCLD_Pos      (8UL)          /*!< BLCLD (Bit 8)                                         */
31120  #define R_CANFD_CFDC2_BLCT_BLCLD_Msk      (0x100UL)      /*!< BLCLD (Bitfield-Mask: 0x01)                           */
31121 /* =========================================================  BLSTS  ========================================================= */
31122  #define R_CANFD_CFDC2_BLSTS_BLC_Pos       (3UL)          /*!< BLC (Bit 3)                                           */
31123  #define R_CANFD_CFDC2_BLSTS_BLC_Msk       (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff)                       */
31124 
31125 /* =========================================================================================================================== */
31126 /* ================                                          CFDGAFL                                          ================ */
31127 /* =========================================================================================================================== */
31128 
31129 /* ==========================================================  ID  =========================================================== */
31130  #define R_CANFD_CFDGAFL_ID_GAFLID_Pos      (0UL)          /*!< GAFLID (Bit 0)                                        */
31131  #define R_CANFD_CFDGAFL_ID_GAFLID_Msk      (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff)                    */
31132  #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos      (29UL)         /*!< GAFLLB (Bit 29)                                       */
31133  #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk      (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01)                          */
31134  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos     (30UL)         /*!< GAFLRTR (Bit 30)                                      */
31135  #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk     (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01)                         */
31136  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos     (31UL)         /*!< GAFLIDE (Bit 31)                                      */
31137  #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk     (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01)                         */
31138 /* ===========================================================  M  =========================================================== */
31139  #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos      (0UL)          /*!< GAFLIDM (Bit 0)                                       */
31140  #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk      (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff)                   */
31141  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos     (29UL)         /*!< GAFLIFL1 (Bit 29)                                     */
31142  #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk     (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01)                        */
31143  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos     (30UL)         /*!< GAFLRTRM (Bit 30)                                     */
31144  #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk     (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01)                        */
31145  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos     (31UL)         /*!< GAFLIDEM (Bit 31)                                     */
31146  #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk     (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01)                        */
31147 /* ==========================================================  P0  =========================================================== */
31148  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos     (0UL)          /*!< GAFLDLC (Bit 0)                                       */
31149  #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk     (0xfUL)        /*!< GAFLDLC (Bitfield-Mask: 0x0f)                         */
31150  #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos    (4UL)          /*!< GAFLSRD0 (Bit 4)                                      */
31151  #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk    (0x10UL)       /*!< GAFLSRD0 (Bitfield-Mask: 0x01)                        */
31152  #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos    (5UL)          /*!< GAFLSRD1 (Bit 5)                                      */
31153  #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk    (0x20UL)       /*!< GAFLSRD1 (Bitfield-Mask: 0x01)                        */
31154  #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos    (6UL)          /*!< GAFLSRD2 (Bit 6)                                      */
31155  #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk    (0x40UL)       /*!< GAFLSRD2 (Bitfield-Mask: 0x01)                        */
31156  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos    (7UL)          /*!< GAFLIFL0 (Bit 7)                                      */
31157  #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk    (0x80UL)       /*!< GAFLIFL0 (Bitfield-Mask: 0x01)                        */
31158  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos    (8UL)          /*!< GAFLRMDP (Bit 8)                                      */
31159  #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk    (0x1f00UL)     /*!< GAFLRMDP (Bitfield-Mask: 0x1f)                        */
31160  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos     (15UL)         /*!< GAFLRMV (Bit 15)                                      */
31161  #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk     (0x8000UL)     /*!< GAFLRMV (Bitfield-Mask: 0x01)                         */
31162  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos     (16UL)         /*!< GAFLPTR (Bit 16)                                      */
31163  #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk     (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff)                       */
31164 /* ==========================================================  P1  =========================================================== */
31165  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos     (0UL)          /*!< GAFLFDP (Bit 0)                                       */
31166  #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk     (0x3fffUL)     /*!< GAFLFDP (Bitfield-Mask: 0x3fff)                       */
31167 
31168 /* =========================================================================================================================== */
31169 /* ================                                           CFDRM                                           ================ */
31170 /* =========================================================================================================================== */
31171 
31172 /* ==========================================================  ID  =========================================================== */
31173  #define R_CANFD_CFDRM_ID_RMID_Pos          (0UL)          /*!< RMID (Bit 0)                                          */
31174  #define R_CANFD_CFDRM_ID_RMID_Msk          (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff)                      */
31175  #define R_CANFD_CFDRM_ID_RMRTR_Pos         (30UL)         /*!< RMRTR (Bit 30)                                        */
31176  #define R_CANFD_CFDRM_ID_RMRTR_Msk         (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01)                           */
31177  #define R_CANFD_CFDRM_ID_RMIDE_Pos         (31UL)         /*!< RMIDE (Bit 31)                                        */
31178  #define R_CANFD_CFDRM_ID_RMIDE_Msk         (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01)                           */
31179 /* ==========================================================  PTR  ========================================================== */
31180  #define R_CANFD_CFDRM_PTR_RMTS_Pos         (0UL)          /*!< RMTS (Bit 0)                                          */
31181  #define R_CANFD_CFDRM_PTR_RMTS_Msk         (0xffffUL)     /*!< RMTS (Bitfield-Mask: 0xffff)                          */
31182  #define R_CANFD_CFDRM_PTR_RMDLC_Pos        (28UL)         /*!< RMDLC (Bit 28)                                        */
31183  #define R_CANFD_CFDRM_PTR_RMDLC_Msk        (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f)                           */
31184 /* =========================================================  FDSTS  ========================================================= */
31185  #define R_CANFD_CFDRM_FDSTS_RMESI_Pos      (0UL)          /*!< RMESI (Bit 0)                                         */
31186  #define R_CANFD_CFDRM_FDSTS_RMESI_Msk      (0x1UL)        /*!< RMESI (Bitfield-Mask: 0x01)                           */
31187  #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos      (1UL)          /*!< RMBRS (Bit 1)                                         */
31188  #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk      (0x2UL)        /*!< RMBRS (Bitfield-Mask: 0x01)                           */
31189  #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos      (2UL)          /*!< RMFDF (Bit 2)                                         */
31190  #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk      (0x4UL)        /*!< RMFDF (Bitfield-Mask: 0x01)                           */
31191  #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos      (8UL)          /*!< RMIFL (Bit 8)                                         */
31192  #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk      (0x300UL)      /*!< RMIFL (Bitfield-Mask: 0x03)                           */
31193  #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos      (16UL)         /*!< RMPTR (Bit 16)                                        */
31194  #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk      (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff)                         */
31195 /* =========================================================  DF_WD  ========================================================= */
31196  #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Pos    (0UL)          /*!< RMDB_LL (Bit 0)                                       */
31197  #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Msk    (0xffUL)       /*!< RMDB_LL (Bitfield-Mask: 0xff)                         */
31198  #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Pos    (8UL)          /*!< RMDB_LH (Bit 8)                                       */
31199  #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Msk    (0xff00UL)     /*!< RMDB_LH (Bitfield-Mask: 0xff)                         */
31200  #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Pos    (16UL)         /*!< RMDB_HL (Bit 16)                                      */
31201  #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Msk    (0xff0000UL)   /*!< RMDB_HL (Bitfield-Mask: 0xff)                         */
31202  #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Pos    (24UL)         /*!< RMDB_HH (Bit 24)                                      */
31203  #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Msk    (0xff000000UL) /*!< RMDB_HH (Bitfield-Mask: 0xff)                         */
31204 /* ==========================================================  DF  =========================================================== */
31205  #define R_CANFD_CFDRM_DF_RMDB_Pos          (0UL)          /*!< RMDB (Bit 0)                                          */
31206  #define R_CANFD_CFDRM_DF_RMDB_Msk          (0xffUL)       /*!< RMDB (Bitfield-Mask: 0xff)                            */
31207 
31208 /* =========================================================================================================================== */
31209 /* ================                                           CFDRF                                           ================ */
31210 /* =========================================================================================================================== */
31211 
31212 /* ==========================================================  ID  =========================================================== */
31213  #define R_CANFD_CFDRF_ID_RFID_Pos           (0UL)          /*!< RFID (Bit 0)                                          */
31214  #define R_CANFD_CFDRF_ID_RFID_Msk           (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff)                      */
31215  #define R_CANFD_CFDRF_ID_RFRTR_Pos          (30UL)         /*!< RFRTR (Bit 30)                                        */
31216  #define R_CANFD_CFDRF_ID_RFRTR_Msk          (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01)                           */
31217  #define R_CANFD_CFDRF_ID_RFIDE_Pos          (31UL)         /*!< RFIDE (Bit 31)                                        */
31218  #define R_CANFD_CFDRF_ID_RFIDE_Msk          (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01)                           */
31219 /* ==========================================================  PTR  ========================================================== */
31220  #define R_CANFD_CFDRF_PTR_RFTS_Pos          (0UL)          /*!< RFTS (Bit 0)                                          */
31221  #define R_CANFD_CFDRF_PTR_RFTS_Msk          (0xffffUL)     /*!< RFTS (Bitfield-Mask: 0xffff)                          */
31222  #define R_CANFD_CFDRF_PTR_RFDLC_Pos         (28UL)         /*!< RFDLC (Bit 28)                                        */
31223  #define R_CANFD_CFDRF_PTR_RFDLC_Msk         (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f)                           */
31224 /* =========================================================  FDSTS  ========================================================= */
31225  #define R_CANFD_CFDRF_FDSTS_RFESI_Pos       (0UL)          /*!< RFESI (Bit 0)                                         */
31226  #define R_CANFD_CFDRF_FDSTS_RFESI_Msk       (0x1UL)        /*!< RFESI (Bitfield-Mask: 0x01)                           */
31227  #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos       (1UL)          /*!< RFBRS (Bit 1)                                         */
31228  #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk       (0x2UL)        /*!< RFBRS (Bitfield-Mask: 0x01)                           */
31229  #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos       (2UL)          /*!< RFFDF (Bit 2)                                         */
31230  #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk       (0x4UL)        /*!< RFFDF (Bitfield-Mask: 0x01)                           */
31231  #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos       (8UL)          /*!< RFIFL (Bit 8)                                         */
31232  #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk       (0x300UL)      /*!< RFIFL (Bitfield-Mask: 0x03)                           */
31233  #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Pos    (16UL)         /*!< CFDRFPTR (Bit 16)                                     */
31234  #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Msk    (0xffff0000UL) /*!< CFDRFPTR (Bitfield-Mask: 0xffff)                      */
31235 /* =========================================================  DF_WD  ========================================================= */
31236  #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Pos     (0UL)          /*!< RFDB_LL (Bit 0)                                       */
31237  #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Msk     (0xffUL)       /*!< RFDB_LL (Bitfield-Mask: 0xff)                         */
31238  #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Pos     (8UL)          /*!< RFDB_LH (Bit 8)                                       */
31239  #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Msk     (0xff00UL)     /*!< RFDB_LH (Bitfield-Mask: 0xff)                         */
31240  #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Pos     (16UL)         /*!< RFDB_HL (Bit 16)                                      */
31241  #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Msk     (0xff0000UL)   /*!< RFDB_HL (Bitfield-Mask: 0xff)                         */
31242  #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Pos     (24UL)         /*!< RFDB_HH (Bit 24)                                      */
31243  #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Msk     (0xff000000UL) /*!< RFDB_HH (Bitfield-Mask: 0xff)                         */
31244 /* ==========================================================  DF  =========================================================== */
31245  #define R_CANFD_CFDRF_DF_RFDB_Pos           (0UL)          /*!< RFDB (Bit 0)                                          */
31246  #define R_CANFD_CFDRF_DF_RFDB_Msk           (0xffUL)       /*!< RFDB (Bitfield-Mask: 0xff)                            */
31247 
31248 /* =========================================================================================================================== */
31249 /* ================                                           CFDCF                                           ================ */
31250 /* =========================================================================================================================== */
31251 
31252 /* ==========================================================  ID  =========================================================== */
31253  #define R_CANFD_CFDCF_ID_CFID_Pos          (0UL)          /*!< CFID (Bit 0)                                          */
31254  #define R_CANFD_CFDCF_ID_CFID_Msk          (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff)                      */
31255  #define R_CANFD_CFDCF_ID_THLEN_Pos         (29UL)         /*!< THLEN (Bit 29)                                        */
31256  #define R_CANFD_CFDCF_ID_THLEN_Msk         (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
31257  #define R_CANFD_CFDCF_ID_CFRTR_Pos         (30UL)         /*!< CFRTR (Bit 30)                                        */
31258  #define R_CANFD_CFDCF_ID_CFRTR_Msk         (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01)                           */
31259  #define R_CANFD_CFDCF_ID_CFIDE_Pos         (31UL)         /*!< CFIDE (Bit 31)                                        */
31260  #define R_CANFD_CFDCF_ID_CFIDE_Msk         (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01)                           */
31261 /* ==========================================================  PTR  ========================================================== */
31262  #define R_CANFD_CFDCF_PTR_CFTS_Pos         (0UL)          /*!< CFTS (Bit 0)                                          */
31263  #define R_CANFD_CFDCF_PTR_CFTS_Msk         (0xffffUL)     /*!< CFTS (Bitfield-Mask: 0xffff)                          */
31264  #define R_CANFD_CFDCF_PTR_CFDLC_Pos        (28UL)         /*!< CFDLC (Bit 28)                                        */
31265  #define R_CANFD_CFDCF_PTR_CFDLC_Msk        (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f)                           */
31266 /* ========================================================  FDCSTS  ========================================================= */
31267  #define R_CANFD_CFDCF_FDCSTS_CFESI_Pos     (0UL)          /*!< CFESI (Bit 0)                                         */
31268  #define R_CANFD_CFDCF_FDCSTS_CFESI_Msk     (0x1UL)        /*!< CFESI (Bitfield-Mask: 0x01)                           */
31269  #define R_CANFD_CFDCF_FDCSTS_CFBRS_Pos     (1UL)          /*!< CFBRS (Bit 1)                                         */
31270  #define R_CANFD_CFDCF_FDCSTS_CFBRS_Msk     (0x2UL)        /*!< CFBRS (Bitfield-Mask: 0x01)                           */
31271  #define R_CANFD_CFDCF_FDCSTS_CFFDF_Pos     (2UL)          /*!< CFFDF (Bit 2)                                         */
31272  #define R_CANFD_CFDCF_FDCSTS_CFFDF_Msk     (0x4UL)        /*!< CFFDF (Bitfield-Mask: 0x01)                           */
31273  #define R_CANFD_CFDCF_FDCSTS_CFIFL_Pos     (8UL)          /*!< CFIFL (Bit 8)                                         */
31274  #define R_CANFD_CFDCF_FDCSTS_CFIFL_Msk     (0x300UL)      /*!< CFIFL (Bitfield-Mask: 0x03)                           */
31275  #define R_CANFD_CFDCF_FDCSTS_CFPTR_Pos     (16UL)         /*!< CFPTR (Bit 16)                                        */
31276  #define R_CANFD_CFDCF_FDCSTS_CFPTR_Msk     (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff)                         */
31277 /* =========================================================  DF_WD  ========================================================= */
31278  #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Pos    (0UL)          /*!< CFDB_LL (Bit 0)                                       */
31279  #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Msk    (0xffUL)       /*!< CFDB_LL (Bitfield-Mask: 0xff)                         */
31280  #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Pos    (8UL)          /*!< CFDB_LH (Bit 8)                                       */
31281  #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Msk    (0xff00UL)     /*!< CFDB_LH (Bitfield-Mask: 0xff)                         */
31282  #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Pos    (16UL)         /*!< CFDB_HL (Bit 16)                                      */
31283  #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Msk    (0xff0000UL)   /*!< CFDB_HL (Bitfield-Mask: 0xff)                         */
31284  #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Pos    (24UL)         /*!< CFDB_HH (Bit 24)                                      */
31285  #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Msk    (0xff000000UL) /*!< CFDB_HH (Bitfield-Mask: 0xff)                         */
31286 /* ==========================================================  DF  =========================================================== */
31287  #define R_CANFD_CFDCF_DF_CFDB_Pos          (0UL)          /*!< CFDB (Bit 0)                                          */
31288  #define R_CANFD_CFDCF_DF_CFDB_Msk          (0xffUL)       /*!< CFDB (Bitfield-Mask: 0xff)                            */
31289 
31290 /* =========================================================================================================================== */
31291 /* ================                                          CFDTHL                                           ================ */
31292 /* =========================================================================================================================== */
31293 
31294 /* =========================================================  ACC0  ========================================================== */
31295  #define R_CANFD_CFDTHL_ACC0_BT_Pos      (0UL)          /*!< BT (Bit 0)                                            */
31296  #define R_CANFD_CFDTHL_ACC0_BT_Msk      (0x7UL)        /*!< BT (Bitfield-Mask: 0x07)                              */
31297  #define R_CANFD_CFDTHL_ACC0_BN_Pos      (3UL)          /*!< BN (Bit 3)                                            */
31298  #define R_CANFD_CFDTHL_ACC0_BN_Msk      (0x3f8UL)      /*!< BN (Bitfield-Mask: 0x7f)                              */
31299  #define R_CANFD_CFDTHL_ACC0_TGW_Pos     (15UL)         /*!< TGW (Bit 15)                                          */
31300  #define R_CANFD_CFDTHL_ACC0_TGW_Msk     (0x8000UL)     /*!< TGW (Bitfield-Mask: 0x01)                             */
31301  #define R_CANFD_CFDTHL_ACC0_TMTS_Pos    (16UL)         /*!< TMTS (Bit 16)                                         */
31302  #define R_CANFD_CFDTHL_ACC0_TMTS_Msk    (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff)                          */
31303 /* =========================================================  ACC1  ========================================================== */
31304  #define R_CANFD_CFDTHL_ACC1_TID_Pos     (0UL)          /*!< TID (Bit 0)                                           */
31305  #define R_CANFD_CFDTHL_ACC1_TID_Msk     (0xffffUL)     /*!< TID (Bitfield-Mask: 0xffff)                           */
31306  #define R_CANFD_CFDTHL_ACC1_TIFL_Pos    (16UL)         /*!< TIFL (Bit 16)                                         */
31307  #define R_CANFD_CFDTHL_ACC1_TIFL_Msk    (0x30000UL)    /*!< TIFL (Bitfield-Mask: 0x03)                            */
31308 
31309 /* =========================================================================================================================== */
31310 /* ================                                           CFDTM                                           ================ */
31311 /* =========================================================================================================================== */
31312 
31313 /* ==========================================================  ID  =========================================================== */
31314  #define R_CANFD_CFDTM_ID_TMID_Pos          (0UL)          /*!< TMID (Bit 0)                                          */
31315  #define R_CANFD_CFDTM_ID_TMID_Msk          (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff)                      */
31316  #define R_CANFD_CFDTM_ID_THLEN_Pos         (29UL)         /*!< THLEN (Bit 29)                                        */
31317  #define R_CANFD_CFDTM_ID_THLEN_Msk         (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01)                           */
31318  #define R_CANFD_CFDTM_ID_TMRTR_Pos         (30UL)         /*!< TMRTR (Bit 30)                                        */
31319  #define R_CANFD_CFDTM_ID_TMRTR_Msk         (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01)                           */
31320  #define R_CANFD_CFDTM_ID_TMIDE_Pos         (31UL)         /*!< TMIDE (Bit 31)                                        */
31321  #define R_CANFD_CFDTM_ID_TMIDE_Msk         (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01)                           */
31322 /* ==========================================================  PTR  ========================================================== */
31323  #define R_CANFD_CFDTM_PTR_TMDLC_Pos        (28UL)         /*!< TMDLC (Bit 28)                                        */
31324  #define R_CANFD_CFDTM_PTR_TMDLC_Msk        (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f)                           */
31325 /* =========================================================  FDCTR  ========================================================= */
31326  #define R_CANFD_CFDTM_FDCTR_TMESI_Pos      (0UL)          /*!< TMESI (Bit 0)                                         */
31327  #define R_CANFD_CFDTM_FDCTR_TMESI_Msk      (0x1UL)        /*!< TMESI (Bitfield-Mask: 0x01)                           */
31328  #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos      (1UL)          /*!< TMBRS (Bit 1)                                         */
31329  #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk      (0x2UL)        /*!< TMBRS (Bitfield-Mask: 0x01)                           */
31330  #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos      (2UL)          /*!< TMFDF (Bit 2)                                         */
31331  #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk      (0x4UL)        /*!< TMFDF (Bitfield-Mask: 0x01)                           */
31332  #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos      (8UL)          /*!< TMIFL (Bit 8)                                         */
31333  #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk      (0x300UL)      /*!< TMIFL (Bitfield-Mask: 0x03)                           */
31334  #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos      (16UL)         /*!< TMPTR (Bit 16)                                        */
31335  #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk      (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff)                         */
31336 /* =========================================================  DF_WD  ========================================================= */
31337  #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Pos    (0UL)          /*!< TMDB_LL (Bit 0)                                       */
31338  #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Msk    (0xffUL)       /*!< TMDB_LL (Bitfield-Mask: 0xff)                         */
31339  #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Pos    (8UL)          /*!< TMDB_LH (Bit 8)                                       */
31340  #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Msk    (0xff00UL)     /*!< TMDB_LH (Bitfield-Mask: 0xff)                         */
31341  #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Pos    (16UL)         /*!< TMDB_HL (Bit 16)                                      */
31342  #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Msk    (0xff0000UL)   /*!< TMDB_HL (Bitfield-Mask: 0xff)                         */
31343  #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Pos    (24UL)         /*!< TMDB_HH (Bit 24)                                      */
31344  #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Msk    (0xff000000UL) /*!< TMDB_HH (Bitfield-Mask: 0xff)                         */
31345 /* ==========================================================  DF  =========================================================== */
31346  #define R_CANFD_CFDTM_DF_TMDB_Pos          (0UL)          /*!< TMDB (Bit 0)                                          */
31347  #define R_CANFD_CFDTM_DF_TMDB_Msk          (0xffUL)       /*!< TMDB (Bitfield-Mask: 0xff)                            */
31348 
31349 /* =========================================================================================================================== */
31350 /* ================                                            CM                                             ================ */
31351 /* =========================================================================================================================== */
31352 
31353 /* ==========================================================  CR  =========================================================== */
31354  #define R_CMT_UNT_CM_CR_CKS_Pos     (0UL)    /*!< CKS (Bit 0)                                           */
31355  #define R_CMT_UNT_CM_CR_CKS_Msk     (0x3UL)  /*!< CKS (Bitfield-Mask: 0x03)                             */
31356  #define R_CMT_UNT_CM_CR_CMIE_Pos    (6UL)    /*!< CMIE (Bit 6)                                          */
31357  #define R_CMT_UNT_CM_CR_CMIE_Msk    (0x40UL) /*!< CMIE (Bitfield-Mask: 0x01)                            */
31358 /* ==========================================================  CNT  ========================================================== */
31359 /* ==========================================================  COR  ========================================================== */
31360 
31361 /* =========================================================================================================================== */
31362 /* ================                                            UNT                                            ================ */
31363 /* =========================================================================================================================== */
31364 
31365 /* ========================================================  CMSTR0  ========================================================= */
31366  #define R_CMT_UNT_CMSTR0_STR0_Pos    (0UL)   /*!< STR0 (Bit 0)                                          */
31367  #define R_CMT_UNT_CMSTR0_STR0_Msk    (0x1UL) /*!< STR0 (Bitfield-Mask: 0x01)                            */
31368  #define R_CMT_UNT_CMSTR0_STR1_Pos    (1UL)   /*!< STR1 (Bit 1)                                          */
31369  #define R_CMT_UNT_CMSTR0_STR1_Msk    (0x2UL) /*!< STR1 (Bitfield-Mask: 0x01)                            */
31370 
31371 /* =========================================================================================================================== */
31372 /* ================                                            SAR                                            ================ */
31373 /* =========================================================================================================================== */
31374 
31375 /* ===========================================================  L  =========================================================== */
31376  #define R_IIC0_SAR_L_SVA0_Pos    (0UL)    /*!< SVA0 (Bit 0)                                          */
31377  #define R_IIC0_SAR_L_SVA0_Msk    (0x1UL)  /*!< SVA0 (Bitfield-Mask: 0x01)                            */
31378  #define R_IIC0_SAR_L_SVA_Pos     (1UL)    /*!< SVA (Bit 1)                                           */
31379  #define R_IIC0_SAR_L_SVA_Msk     (0xfeUL) /*!< SVA (Bitfield-Mask: 0x7f)                             */
31380 /* ===========================================================  U  =========================================================== */
31381  #define R_IIC0_SAR_U_FS_Pos      (0UL)    /*!< FS (Bit 0)                                            */
31382  #define R_IIC0_SAR_U_FS_Msk      (0x1UL)  /*!< FS (Bitfield-Mask: 0x01)                              */
31383  #define R_IIC0_SAR_U_SVA_Pos     (1UL)    /*!< SVA (Bit 1)                                           */
31384  #define R_IIC0_SAR_U_SVA_Msk     (0x6UL)  /*!< SVA (Bitfield-Mask: 0x03)                             */
31385 
31386 /* =========================================================================================================================== */
31387 /* ================                                             N                                             ================ */
31388 /* =========================================================================================================================== */
31389 
31390 /* ==========================================================  SA  =========================================================== */
31391 /* ==========================================================  DA  =========================================================== */
31392 /* ==========================================================  TB  =========================================================== */
31393 
31394 /* =========================================================================================================================== */
31395 /* ================                                            CH                                             ================ */
31396 /* =========================================================================================================================== */
31397 
31398 /* =========================================================  CRSA  ========================================================== */
31399 /* =========================================================  CRDA  ========================================================== */
31400 /* =========================================================  CRTB  ========================================================== */
31401 /* ========================================================  CHSTAT  ========================================================= */
31402  #define R_DMAC0_GRP_CH_CHSTAT_EN_Pos         (0UL)          /*!< EN (Bit 0)                                            */
31403  #define R_DMAC0_GRP_CH_CHSTAT_EN_Msk         (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
31404  #define R_DMAC0_GRP_CH_CHSTAT_RQST_Pos       (1UL)          /*!< RQST (Bit 1)                                          */
31405  #define R_DMAC0_GRP_CH_CHSTAT_RQST_Msk       (0x2UL)        /*!< RQST (Bitfield-Mask: 0x01)                            */
31406  #define R_DMAC0_GRP_CH_CHSTAT_TACT_Pos       (2UL)          /*!< TACT (Bit 2)                                          */
31407  #define R_DMAC0_GRP_CH_CHSTAT_TACT_Msk       (0x4UL)        /*!< TACT (Bitfield-Mask: 0x01)                            */
31408  #define R_DMAC0_GRP_CH_CHSTAT_SUS_Pos        (3UL)          /*!< SUS (Bit 3)                                           */
31409  #define R_DMAC0_GRP_CH_CHSTAT_SUS_Msk        (0x8UL)        /*!< SUS (Bitfield-Mask: 0x01)                             */
31410  #define R_DMAC0_GRP_CH_CHSTAT_ER_Pos         (4UL)          /*!< ER (Bit 4)                                            */
31411  #define R_DMAC0_GRP_CH_CHSTAT_ER_Msk         (0x10UL)       /*!< ER (Bitfield-Mask: 0x01)                              */
31412  #define R_DMAC0_GRP_CH_CHSTAT_END_Pos        (5UL)          /*!< END (Bit 5)                                           */
31413  #define R_DMAC0_GRP_CH_CHSTAT_END_Msk        (0x20UL)       /*!< END (Bitfield-Mask: 0x01)                             */
31414  #define R_DMAC0_GRP_CH_CHSTAT_TC_Pos         (6UL)          /*!< TC (Bit 6)                                            */
31415  #define R_DMAC0_GRP_CH_CHSTAT_TC_Msk         (0x40UL)       /*!< TC (Bitfield-Mask: 0x01)                              */
31416  #define R_DMAC0_GRP_CH_CHSTAT_SR_Pos         (7UL)          /*!< SR (Bit 7)                                            */
31417  #define R_DMAC0_GRP_CH_CHSTAT_SR_Msk         (0x80UL)       /*!< SR (Bitfield-Mask: 0x01)                              */
31418  #define R_DMAC0_GRP_CH_CHSTAT_DL_Pos         (8UL)          /*!< DL (Bit 8)                                            */
31419  #define R_DMAC0_GRP_CH_CHSTAT_DL_Msk         (0x100UL)      /*!< DL (Bitfield-Mask: 0x01)                              */
31420  #define R_DMAC0_GRP_CH_CHSTAT_DW_Pos         (9UL)          /*!< DW (Bit 9)                                            */
31421  #define R_DMAC0_GRP_CH_CHSTAT_DW_Msk         (0x200UL)      /*!< DW (Bitfield-Mask: 0x01)                              */
31422  #define R_DMAC0_GRP_CH_CHSTAT_DER_Pos        (10UL)         /*!< DER (Bit 10)                                          */
31423  #define R_DMAC0_GRP_CH_CHSTAT_DER_Msk        (0x400UL)      /*!< DER (Bitfield-Mask: 0x01)                             */
31424  #define R_DMAC0_GRP_CH_CHSTAT_MODE_Pos       (11UL)         /*!< MODE (Bit 11)                                         */
31425  #define R_DMAC0_GRP_CH_CHSTAT_MODE_Msk       (0x800UL)      /*!< MODE (Bitfield-Mask: 0x01)                            */
31426  #define R_DMAC0_GRP_CH_CHSTAT_INTM_Pos       (16UL)         /*!< INTM (Bit 16)                                         */
31427  #define R_DMAC0_GRP_CH_CHSTAT_INTM_Msk       (0x10000UL)    /*!< INTM (Bitfield-Mask: 0x01)                            */
31428 /* ========================================================  CHCTRL  ========================================================= */
31429  #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Pos      (0UL)          /*!< SETEN (Bit 0)                                         */
31430  #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Msk      (0x1UL)        /*!< SETEN (Bitfield-Mask: 0x01)                           */
31431  #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Pos      (1UL)          /*!< CLREN (Bit 1)                                         */
31432  #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Msk      (0x2UL)        /*!< CLREN (Bitfield-Mask: 0x01)                           */
31433  #define R_DMAC0_GRP_CH_CHCTRL_STG_Pos        (2UL)          /*!< STG (Bit 2)                                           */
31434  #define R_DMAC0_GRP_CH_CHCTRL_STG_Msk        (0x4UL)        /*!< STG (Bitfield-Mask: 0x01)                             */
31435  #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Pos      (3UL)          /*!< SWRST (Bit 3)                                         */
31436  #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Msk      (0x8UL)        /*!< SWRST (Bitfield-Mask: 0x01)                           */
31437  #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Pos      (4UL)          /*!< CLRRQ (Bit 4)                                         */
31438  #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Msk      (0x10UL)       /*!< CLRRQ (Bitfield-Mask: 0x01)                           */
31439  #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Pos     (5UL)          /*!< CLREND (Bit 5)                                        */
31440  #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Msk     (0x20UL)       /*!< CLREND (Bitfield-Mask: 0x01)                          */
31441  #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Pos      (6UL)          /*!< CLRTC (Bit 6)                                         */
31442  #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Msk      (0x40UL)       /*!< CLRTC (Bitfield-Mask: 0x01)                           */
31443  #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Pos     (8UL)          /*!< SETSUS (Bit 8)                                        */
31444  #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Msk     (0x100UL)      /*!< SETSUS (Bitfield-Mask: 0x01)                          */
31445  #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Pos     (9UL)          /*!< CLRSUS (Bit 9)                                        */
31446  #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Msk     (0x200UL)      /*!< CLRSUS (Bitfield-Mask: 0x01)                          */
31447  #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Pos    (16UL)         /*!< SETINTM (Bit 16)                                      */
31448  #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Msk    (0x10000UL)    /*!< SETINTM (Bitfield-Mask: 0x01)                         */
31449  #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Pos    (17UL)         /*!< CLRINTM (Bit 17)                                      */
31450  #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Msk    (0x20000UL)    /*!< CLRINTM (Bitfield-Mask: 0x01)                         */
31451 /* =========================================================  CHCFG  ========================================================= */
31452  #define R_DMAC0_GRP_CH_CHCFG_SEL_Pos         (0UL)          /*!< SEL (Bit 0)                                           */
31453  #define R_DMAC0_GRP_CH_CHCFG_SEL_Msk         (0x7UL)        /*!< SEL (Bitfield-Mask: 0x07)                             */
31454  #define R_DMAC0_GRP_CH_CHCFG_REQD_Pos        (3UL)          /*!< REQD (Bit 3)                                          */
31455  #define R_DMAC0_GRP_CH_CHCFG_REQD_Msk        (0x8UL)        /*!< REQD (Bitfield-Mask: 0x01)                            */
31456  #define R_DMAC0_GRP_CH_CHCFG_LOEN_Pos        (4UL)          /*!< LOEN (Bit 4)                                          */
31457  #define R_DMAC0_GRP_CH_CHCFG_LOEN_Msk        (0x10UL)       /*!< LOEN (Bitfield-Mask: 0x01)                            */
31458  #define R_DMAC0_GRP_CH_CHCFG_HIEN_Pos        (5UL)          /*!< HIEN (Bit 5)                                          */
31459  #define R_DMAC0_GRP_CH_CHCFG_HIEN_Msk        (0x20UL)       /*!< HIEN (Bitfield-Mask: 0x01)                            */
31460  #define R_DMAC0_GRP_CH_CHCFG_LVL_Pos         (6UL)          /*!< LVL (Bit 6)                                           */
31461  #define R_DMAC0_GRP_CH_CHCFG_LVL_Msk         (0x40UL)       /*!< LVL (Bitfield-Mask: 0x01)                             */
31462  #define R_DMAC0_GRP_CH_CHCFG_AM_Pos          (8UL)          /*!< AM (Bit 8)                                            */
31463  #define R_DMAC0_GRP_CH_CHCFG_AM_Msk          (0x700UL)      /*!< AM (Bitfield-Mask: 0x07)                              */
31464  #define R_DMAC0_GRP_CH_CHCFG_SDS_Pos         (12UL)         /*!< SDS (Bit 12)                                          */
31465  #define R_DMAC0_GRP_CH_CHCFG_SDS_Msk         (0xf000UL)     /*!< SDS (Bitfield-Mask: 0x0f)                             */
31466  #define R_DMAC0_GRP_CH_CHCFG_DDS_Pos         (16UL)         /*!< DDS (Bit 16)                                          */
31467  #define R_DMAC0_GRP_CH_CHCFG_DDS_Msk         (0xf0000UL)    /*!< DDS (Bitfield-Mask: 0x0f)                             */
31468  #define R_DMAC0_GRP_CH_CHCFG_SAD_Pos         (20UL)         /*!< SAD (Bit 20)                                          */
31469  #define R_DMAC0_GRP_CH_CHCFG_SAD_Msk         (0x100000UL)   /*!< SAD (Bitfield-Mask: 0x01)                             */
31470  #define R_DMAC0_GRP_CH_CHCFG_DAD_Pos         (21UL)         /*!< DAD (Bit 21)                                          */
31471  #define R_DMAC0_GRP_CH_CHCFG_DAD_Msk         (0x200000UL)   /*!< DAD (Bitfield-Mask: 0x01)                             */
31472  #define R_DMAC0_GRP_CH_CHCFG_TM_Pos          (22UL)         /*!< TM (Bit 22)                                           */
31473  #define R_DMAC0_GRP_CH_CHCFG_TM_Msk          (0x400000UL)   /*!< TM (Bitfield-Mask: 0x01)                              */
31474  #define R_DMAC0_GRP_CH_CHCFG_DEM_Pos         (24UL)         /*!< DEM (Bit 24)                                          */
31475  #define R_DMAC0_GRP_CH_CHCFG_DEM_Msk         (0x1000000UL)  /*!< DEM (Bitfield-Mask: 0x01)                             */
31476  #define R_DMAC0_GRP_CH_CHCFG_TCM_Pos         (25UL)         /*!< TCM (Bit 25)                                          */
31477  #define R_DMAC0_GRP_CH_CHCFG_TCM_Msk         (0x2000000UL)  /*!< TCM (Bitfield-Mask: 0x01)                             */
31478  #define R_DMAC0_GRP_CH_CHCFG_SBE_Pos         (27UL)         /*!< SBE (Bit 27)                                          */
31479  #define R_DMAC0_GRP_CH_CHCFG_SBE_Msk         (0x8000000UL)  /*!< SBE (Bitfield-Mask: 0x01)                             */
31480  #define R_DMAC0_GRP_CH_CHCFG_RSEL_Pos        (28UL)         /*!< RSEL (Bit 28)                                         */
31481  #define R_DMAC0_GRP_CH_CHCFG_RSEL_Msk        (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01)                            */
31482  #define R_DMAC0_GRP_CH_CHCFG_RSW_Pos         (29UL)         /*!< RSW (Bit 29)                                          */
31483  #define R_DMAC0_GRP_CH_CHCFG_RSW_Msk         (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01)                             */
31484  #define R_DMAC0_GRP_CH_CHCFG_REN_Pos         (30UL)         /*!< REN (Bit 30)                                          */
31485  #define R_DMAC0_GRP_CH_CHCFG_REN_Msk         (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01)                             */
31486  #define R_DMAC0_GRP_CH_CHCFG_DMS_Pos         (31UL)         /*!< DMS (Bit 31)                                          */
31487  #define R_DMAC0_GRP_CH_CHCFG_DMS_Msk         (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01)                             */
31488 /* ========================================================  CHITVL  ========================================================= */
31489  #define R_DMAC0_GRP_CH_CHITVL_ITVL_Pos       (0UL)          /*!< ITVL (Bit 0)                                          */
31490  #define R_DMAC0_GRP_CH_CHITVL_ITVL_Msk       (0xffffUL)     /*!< ITVL (Bitfield-Mask: 0xffff)                          */
31491 /* =========================================================  CHEXT  ========================================================= */
31492  #define R_DMAC0_GRP_CH_CHEXT_SPR_Pos         (0UL)          /*!< SPR (Bit 0)                                           */
31493  #define R_DMAC0_GRP_CH_CHEXT_SPR_Msk         (0x7UL)        /*!< SPR (Bitfield-Mask: 0x07)                             */
31494  #define R_DMAC0_GRP_CH_CHEXT_SCA_Pos         (4UL)          /*!< SCA (Bit 4)                                           */
31495  #define R_DMAC0_GRP_CH_CHEXT_SCA_Msk         (0xf0UL)       /*!< SCA (Bitfield-Mask: 0x0f)                             */
31496  #define R_DMAC0_GRP_CH_CHEXT_DPR_Pos         (8UL)          /*!< DPR (Bit 8)                                           */
31497  #define R_DMAC0_GRP_CH_CHEXT_DPR_Msk         (0x700UL)      /*!< DPR (Bitfield-Mask: 0x07)                             */
31498  #define R_DMAC0_GRP_CH_CHEXT_DCA_Pos         (12UL)         /*!< DCA (Bit 12)                                          */
31499  #define R_DMAC0_GRP_CH_CHEXT_DCA_Msk         (0xf000UL)     /*!< DCA (Bitfield-Mask: 0x0f)                             */
31500 /* =========================================================  NXLA  ========================================================== */
31501 /* =========================================================  CRLA  ========================================================== */
31502 
31503 /* =========================================================================================================================== */
31504 /* ================                                            GRP                                            ================ */
31505 /* =========================================================================================================================== */
31506 
31507 /* =========================================================  DCTRL  ========================================================= */
31508  #define R_DMAC0_GRP_DCTRL_PR_Pos           (0UL)    /*!< PR (Bit 0)                                            */
31509  #define R_DMAC0_GRP_DCTRL_PR_Msk           (0x1UL)  /*!< PR (Bitfield-Mask: 0x01)                              */
31510  #define R_DMAC0_GRP_DCTRL_LVINT_Pos        (1UL)    /*!< LVINT (Bit 1)                                         */
31511  #define R_DMAC0_GRP_DCTRL_LVINT_Msk        (0x2UL)  /*!< LVINT (Bitfield-Mask: 0x01)                           */
31512 /* =======================================================  DSTAT_EN  ======================================================== */
31513  #define R_DMAC0_GRP_DSTAT_EN_EN00_Pos      (0UL)    /*!< EN00 (Bit 0)                                          */
31514  #define R_DMAC0_GRP_DSTAT_EN_EN00_Msk      (0x1UL)  /*!< EN00 (Bitfield-Mask: 0x01)                            */
31515  #define R_DMAC0_GRP_DSTAT_EN_EN01_Pos      (1UL)    /*!< EN01 (Bit 1)                                          */
31516  #define R_DMAC0_GRP_DSTAT_EN_EN01_Msk      (0x2UL)  /*!< EN01 (Bitfield-Mask: 0x01)                            */
31517  #define R_DMAC0_GRP_DSTAT_EN_EN02_Pos      (2UL)    /*!< EN02 (Bit 2)                                          */
31518  #define R_DMAC0_GRP_DSTAT_EN_EN02_Msk      (0x4UL)  /*!< EN02 (Bitfield-Mask: 0x01)                            */
31519  #define R_DMAC0_GRP_DSTAT_EN_EN03_Pos      (3UL)    /*!< EN03 (Bit 3)                                          */
31520  #define R_DMAC0_GRP_DSTAT_EN_EN03_Msk      (0x8UL)  /*!< EN03 (Bitfield-Mask: 0x01)                            */
31521  #define R_DMAC0_GRP_DSTAT_EN_EN04_Pos      (4UL)    /*!< EN04 (Bit 4)                                          */
31522  #define R_DMAC0_GRP_DSTAT_EN_EN04_Msk      (0x10UL) /*!< EN04 (Bitfield-Mask: 0x01)                            */
31523  #define R_DMAC0_GRP_DSTAT_EN_EN05_Pos      (5UL)    /*!< EN05 (Bit 5)                                          */
31524  #define R_DMAC0_GRP_DSTAT_EN_EN05_Msk      (0x20UL) /*!< EN05 (Bitfield-Mask: 0x01)                            */
31525  #define R_DMAC0_GRP_DSTAT_EN_EN06_Pos      (6UL)    /*!< EN06 (Bit 6)                                          */
31526  #define R_DMAC0_GRP_DSTAT_EN_EN06_Msk      (0x40UL) /*!< EN06 (Bitfield-Mask: 0x01)                            */
31527  #define R_DMAC0_GRP_DSTAT_EN_EN07_Pos      (7UL)    /*!< EN07 (Bit 7)                                          */
31528  #define R_DMAC0_GRP_DSTAT_EN_EN07_Msk      (0x80UL) /*!< EN07 (Bitfield-Mask: 0x01)                            */
31529 /* =======================================================  DSTAT_ER  ======================================================== */
31530  #define R_DMAC0_GRP_DSTAT_ER_ER00_Pos      (0UL)    /*!< ER00 (Bit 0)                                          */
31531  #define R_DMAC0_GRP_DSTAT_ER_ER00_Msk      (0x1UL)  /*!< ER00 (Bitfield-Mask: 0x01)                            */
31532  #define R_DMAC0_GRP_DSTAT_ER_ER01_Pos      (1UL)    /*!< ER01 (Bit 1)                                          */
31533  #define R_DMAC0_GRP_DSTAT_ER_ER01_Msk      (0x2UL)  /*!< ER01 (Bitfield-Mask: 0x01)                            */
31534  #define R_DMAC0_GRP_DSTAT_ER_ER02_Pos      (2UL)    /*!< ER02 (Bit 2)                                          */
31535  #define R_DMAC0_GRP_DSTAT_ER_ER02_Msk      (0x4UL)  /*!< ER02 (Bitfield-Mask: 0x01)                            */
31536  #define R_DMAC0_GRP_DSTAT_ER_ER03_Pos      (3UL)    /*!< ER03 (Bit 3)                                          */
31537  #define R_DMAC0_GRP_DSTAT_ER_ER03_Msk      (0x8UL)  /*!< ER03 (Bitfield-Mask: 0x01)                            */
31538  #define R_DMAC0_GRP_DSTAT_ER_ER04_Pos      (4UL)    /*!< ER04 (Bit 4)                                          */
31539  #define R_DMAC0_GRP_DSTAT_ER_ER04_Msk      (0x10UL) /*!< ER04 (Bitfield-Mask: 0x01)                            */
31540  #define R_DMAC0_GRP_DSTAT_ER_ER05_Pos      (5UL)    /*!< ER05 (Bit 5)                                          */
31541  #define R_DMAC0_GRP_DSTAT_ER_ER05_Msk      (0x20UL) /*!< ER05 (Bitfield-Mask: 0x01)                            */
31542  #define R_DMAC0_GRP_DSTAT_ER_ER06_Pos      (6UL)    /*!< ER06 (Bit 6)                                          */
31543  #define R_DMAC0_GRP_DSTAT_ER_ER06_Msk      (0x40UL) /*!< ER06 (Bitfield-Mask: 0x01)                            */
31544  #define R_DMAC0_GRP_DSTAT_ER_ER07_Pos      (7UL)    /*!< ER07 (Bit 7)                                          */
31545  #define R_DMAC0_GRP_DSTAT_ER_ER07_Msk      (0x80UL) /*!< ER07 (Bitfield-Mask: 0x01)                            */
31546 /* =======================================================  DSTAT_END  ======================================================= */
31547  #define R_DMAC0_GRP_DSTAT_END_END00_Pos    (0UL)    /*!< END00 (Bit 0)                                         */
31548  #define R_DMAC0_GRP_DSTAT_END_END00_Msk    (0x1UL)  /*!< END00 (Bitfield-Mask: 0x01)                           */
31549  #define R_DMAC0_GRP_DSTAT_END_END01_Pos    (1UL)    /*!< END01 (Bit 1)                                         */
31550  #define R_DMAC0_GRP_DSTAT_END_END01_Msk    (0x2UL)  /*!< END01 (Bitfield-Mask: 0x01)                           */
31551  #define R_DMAC0_GRP_DSTAT_END_END02_Pos    (2UL)    /*!< END02 (Bit 2)                                         */
31552  #define R_DMAC0_GRP_DSTAT_END_END02_Msk    (0x4UL)  /*!< END02 (Bitfield-Mask: 0x01)                           */
31553  #define R_DMAC0_GRP_DSTAT_END_END03_Pos    (3UL)    /*!< END03 (Bit 3)                                         */
31554  #define R_DMAC0_GRP_DSTAT_END_END03_Msk    (0x8UL)  /*!< END03 (Bitfield-Mask: 0x01)                           */
31555  #define R_DMAC0_GRP_DSTAT_END_END04_Pos    (4UL)    /*!< END04 (Bit 4)                                         */
31556  #define R_DMAC0_GRP_DSTAT_END_END04_Msk    (0x10UL) /*!< END04 (Bitfield-Mask: 0x01)                           */
31557  #define R_DMAC0_GRP_DSTAT_END_END05_Pos    (5UL)    /*!< END05 (Bit 5)                                         */
31558  #define R_DMAC0_GRP_DSTAT_END_END05_Msk    (0x20UL) /*!< END05 (Bitfield-Mask: 0x01)                           */
31559  #define R_DMAC0_GRP_DSTAT_END_END06_Pos    (6UL)    /*!< END06 (Bit 6)                                         */
31560  #define R_DMAC0_GRP_DSTAT_END_END06_Msk    (0x40UL) /*!< END06 (Bitfield-Mask: 0x01)                           */
31561  #define R_DMAC0_GRP_DSTAT_END_END07_Pos    (7UL)    /*!< END07 (Bit 7)                                         */
31562  #define R_DMAC0_GRP_DSTAT_END_END07_Msk    (0x80UL) /*!< END07 (Bitfield-Mask: 0x01)                           */
31563 /* =======================================================  DSTAT_SUS  ======================================================= */
31564  #define R_DMAC0_GRP_DSTAT_SUS_SUS00_Pos    (0UL)    /*!< SUS00 (Bit 0)                                         */
31565  #define R_DMAC0_GRP_DSTAT_SUS_SUS00_Msk    (0x1UL)  /*!< SUS00 (Bitfield-Mask: 0x01)                           */
31566  #define R_DMAC0_GRP_DSTAT_SUS_SUS01_Pos    (1UL)    /*!< SUS01 (Bit 1)                                         */
31567  #define R_DMAC0_GRP_DSTAT_SUS_SUS01_Msk    (0x2UL)  /*!< SUS01 (Bitfield-Mask: 0x01)                           */
31568  #define R_DMAC0_GRP_DSTAT_SUS_SUS02_Pos    (2UL)    /*!< SUS02 (Bit 2)                                         */
31569  #define R_DMAC0_GRP_DSTAT_SUS_SUS02_Msk    (0x4UL)  /*!< SUS02 (Bitfield-Mask: 0x01)                           */
31570  #define R_DMAC0_GRP_DSTAT_SUS_SUS03_Pos    (3UL)    /*!< SUS03 (Bit 3)                                         */
31571  #define R_DMAC0_GRP_DSTAT_SUS_SUS03_Msk    (0x8UL)  /*!< SUS03 (Bitfield-Mask: 0x01)                           */
31572  #define R_DMAC0_GRP_DSTAT_SUS_SUS04_Pos    (4UL)    /*!< SUS04 (Bit 4)                                         */
31573  #define R_DMAC0_GRP_DSTAT_SUS_SUS04_Msk    (0x10UL) /*!< SUS04 (Bitfield-Mask: 0x01)                           */
31574  #define R_DMAC0_GRP_DSTAT_SUS_SUS05_Pos    (5UL)    /*!< SUS05 (Bit 5)                                         */
31575  #define R_DMAC0_GRP_DSTAT_SUS_SUS05_Msk    (0x20UL) /*!< SUS05 (Bitfield-Mask: 0x01)                           */
31576  #define R_DMAC0_GRP_DSTAT_SUS_SUS06_Pos    (6UL)    /*!< SUS06 (Bit 6)                                         */
31577  #define R_DMAC0_GRP_DSTAT_SUS_SUS06_Msk    (0x40UL) /*!< SUS06 (Bitfield-Mask: 0x01)                           */
31578  #define R_DMAC0_GRP_DSTAT_SUS_SUS07_Pos    (7UL)    /*!< SUS07 (Bit 7)                                         */
31579  #define R_DMAC0_GRP_DSTAT_SUS_SUS07_Msk    (0x80UL) /*!< SUS07 (Bitfield-Mask: 0x01)                           */
31580 
31581 /* =========================================================================================================================== */
31582 /* ================                                           DRCTL                                           ================ */
31583 /* =========================================================================================================================== */
31584 
31585 /* ===========================================================  L  =========================================================== */
31586  #define R_PORT_NSR_DRCTL_L_DRV0_Pos    (0UL)          /*!< DRV0 (Bit 0)                                          */
31587  #define R_PORT_NSR_DRCTL_L_DRV0_Msk    (0x3UL)        /*!< DRV0 (Bitfield-Mask: 0x03)                            */
31588  #define R_PORT_NSR_DRCTL_L_PUD0_Pos    (2UL)          /*!< PUD0 (Bit 2)                                          */
31589  #define R_PORT_NSR_DRCTL_L_PUD0_Msk    (0xcUL)        /*!< PUD0 (Bitfield-Mask: 0x03)                            */
31590  #define R_PORT_NSR_DRCTL_L_SMT0_Pos    (4UL)          /*!< SMT0 (Bit 4)                                          */
31591  #define R_PORT_NSR_DRCTL_L_SMT0_Msk    (0x10UL)       /*!< SMT0 (Bitfield-Mask: 0x01)                            */
31592  #define R_PORT_NSR_DRCTL_L_SR0_Pos     (5UL)          /*!< SR0 (Bit 5)                                           */
31593  #define R_PORT_NSR_DRCTL_L_SR0_Msk     (0x20UL)       /*!< SR0 (Bitfield-Mask: 0x01)                             */
31594  #define R_PORT_NSR_DRCTL_L_DRV1_Pos    (8UL)          /*!< DRV1 (Bit 8)                                          */
31595  #define R_PORT_NSR_DRCTL_L_DRV1_Msk    (0x300UL)      /*!< DRV1 (Bitfield-Mask: 0x03)                            */
31596  #define R_PORT_NSR_DRCTL_L_PUD1_Pos    (10UL)         /*!< PUD1 (Bit 10)                                         */
31597  #define R_PORT_NSR_DRCTL_L_PUD1_Msk    (0xc00UL)      /*!< PUD1 (Bitfield-Mask: 0x03)                            */
31598  #define R_PORT_NSR_DRCTL_L_SMT1_Pos    (12UL)         /*!< SMT1 (Bit 12)                                         */
31599  #define R_PORT_NSR_DRCTL_L_SMT1_Msk    (0x1000UL)     /*!< SMT1 (Bitfield-Mask: 0x01)                            */
31600  #define R_PORT_NSR_DRCTL_L_SR1_Pos     (13UL)         /*!< SR1 (Bit 13)                                          */
31601  #define R_PORT_NSR_DRCTL_L_SR1_Msk     (0x2000UL)     /*!< SR1 (Bitfield-Mask: 0x01)                             */
31602  #define R_PORT_NSR_DRCTL_L_DRV2_Pos    (16UL)         /*!< DRV2 (Bit 16)                                         */
31603  #define R_PORT_NSR_DRCTL_L_DRV2_Msk    (0x30000UL)    /*!< DRV2 (Bitfield-Mask: 0x03)                            */
31604  #define R_PORT_NSR_DRCTL_L_PUD2_Pos    (18UL)         /*!< PUD2 (Bit 18)                                         */
31605  #define R_PORT_NSR_DRCTL_L_PUD2_Msk    (0xc0000UL)    /*!< PUD2 (Bitfield-Mask: 0x03)                            */
31606  #define R_PORT_NSR_DRCTL_L_SMT2_Pos    (20UL)         /*!< SMT2 (Bit 20)                                         */
31607  #define R_PORT_NSR_DRCTL_L_SMT2_Msk    (0x100000UL)   /*!< SMT2 (Bitfield-Mask: 0x01)                            */
31608  #define R_PORT_NSR_DRCTL_L_SR2_Pos     (21UL)         /*!< SR2 (Bit 21)                                          */
31609  #define R_PORT_NSR_DRCTL_L_SR2_Msk     (0x200000UL)   /*!< SR2 (Bitfield-Mask: 0x01)                             */
31610  #define R_PORT_NSR_DRCTL_L_DRV3_Pos    (24UL)         /*!< DRV3 (Bit 24)                                         */
31611  #define R_PORT_NSR_DRCTL_L_DRV3_Msk    (0x3000000UL)  /*!< DRV3 (Bitfield-Mask: 0x03)                            */
31612  #define R_PORT_NSR_DRCTL_L_PUD3_Pos    (26UL)         /*!< PUD3 (Bit 26)                                         */
31613  #define R_PORT_NSR_DRCTL_L_PUD3_Msk    (0xc000000UL)  /*!< PUD3 (Bitfield-Mask: 0x03)                            */
31614  #define R_PORT_NSR_DRCTL_L_SMT3_Pos    (28UL)         /*!< SMT3 (Bit 28)                                         */
31615  #define R_PORT_NSR_DRCTL_L_SMT3_Msk    (0x10000000UL) /*!< SMT3 (Bitfield-Mask: 0x01)                            */
31616  #define R_PORT_NSR_DRCTL_L_SR3_Pos     (29UL)         /*!< SR3 (Bit 29)                                          */
31617  #define R_PORT_NSR_DRCTL_L_SR3_Msk     (0x20000000UL) /*!< SR3 (Bitfield-Mask: 0x01)                             */
31618 /* ===========================================================  H  =========================================================== */
31619  #define R_PORT_NSR_DRCTL_H_DRV4_Pos    (0UL)          /*!< DRV4 (Bit 0)                                          */
31620  #define R_PORT_NSR_DRCTL_H_DRV4_Msk    (0x3UL)        /*!< DRV4 (Bitfield-Mask: 0x03)                            */
31621  #define R_PORT_NSR_DRCTL_H_PUD4_Pos    (2UL)          /*!< PUD4 (Bit 2)                                          */
31622  #define R_PORT_NSR_DRCTL_H_PUD4_Msk    (0xcUL)        /*!< PUD4 (Bitfield-Mask: 0x03)                            */
31623  #define R_PORT_NSR_DRCTL_H_SMT4_Pos    (4UL)          /*!< SMT4 (Bit 4)                                          */
31624  #define R_PORT_NSR_DRCTL_H_SMT4_Msk    (0x10UL)       /*!< SMT4 (Bitfield-Mask: 0x01)                            */
31625  #define R_PORT_NSR_DRCTL_H_SR4_Pos     (5UL)          /*!< SR4 (Bit 5)                                           */
31626  #define R_PORT_NSR_DRCTL_H_SR4_Msk     (0x20UL)       /*!< SR4 (Bitfield-Mask: 0x01)                             */
31627  #define R_PORT_NSR_DRCTL_H_DRV5_Pos    (8UL)          /*!< DRV5 (Bit 8)                                          */
31628  #define R_PORT_NSR_DRCTL_H_DRV5_Msk    (0x300UL)      /*!< DRV5 (Bitfield-Mask: 0x03)                            */
31629  #define R_PORT_NSR_DRCTL_H_PUD5_Pos    (10UL)         /*!< PUD5 (Bit 10)                                         */
31630  #define R_PORT_NSR_DRCTL_H_PUD5_Msk    (0xc00UL)      /*!< PUD5 (Bitfield-Mask: 0x03)                            */
31631  #define R_PORT_NSR_DRCTL_H_SMT5_Pos    (12UL)         /*!< SMT5 (Bit 12)                                         */
31632  #define R_PORT_NSR_DRCTL_H_SMT5_Msk    (0x1000UL)     /*!< SMT5 (Bitfield-Mask: 0x01)                            */
31633  #define R_PORT_NSR_DRCTL_H_SR5_Pos     (13UL)         /*!< SR5 (Bit 13)                                          */
31634  #define R_PORT_NSR_DRCTL_H_SR5_Msk     (0x2000UL)     /*!< SR5 (Bitfield-Mask: 0x01)                             */
31635  #define R_PORT_NSR_DRCTL_H_DRV6_Pos    (16UL)         /*!< DRV6 (Bit 16)                                         */
31636  #define R_PORT_NSR_DRCTL_H_DRV6_Msk    (0x30000UL)    /*!< DRV6 (Bitfield-Mask: 0x03)                            */
31637  #define R_PORT_NSR_DRCTL_H_PUD6_Pos    (18UL)         /*!< PUD6 (Bit 18)                                         */
31638  #define R_PORT_NSR_DRCTL_H_PUD6_Msk    (0xc0000UL)    /*!< PUD6 (Bitfield-Mask: 0x03)                            */
31639  #define R_PORT_NSR_DRCTL_H_SMT6_Pos    (20UL)         /*!< SMT6 (Bit 20)                                         */
31640  #define R_PORT_NSR_DRCTL_H_SMT6_Msk    (0x100000UL)   /*!< SMT6 (Bitfield-Mask: 0x01)                            */
31641  #define R_PORT_NSR_DRCTL_H_SR6_Pos     (21UL)         /*!< SR6 (Bit 21)                                          */
31642  #define R_PORT_NSR_DRCTL_H_SR6_Msk     (0x200000UL)   /*!< SR6 (Bitfield-Mask: 0x01)                             */
31643  #define R_PORT_NSR_DRCTL_H_DRV7_Pos    (24UL)         /*!< DRV7 (Bit 24)                                         */
31644  #define R_PORT_NSR_DRCTL_H_DRV7_Msk    (0x3000000UL)  /*!< DRV7 (Bitfield-Mask: 0x03)                            */
31645  #define R_PORT_NSR_DRCTL_H_PUD7_Pos    (26UL)         /*!< PUD7 (Bit 26)                                         */
31646  #define R_PORT_NSR_DRCTL_H_PUD7_Msk    (0xc000000UL)  /*!< PUD7 (Bitfield-Mask: 0x03)                            */
31647  #define R_PORT_NSR_DRCTL_H_SMT7_Pos    (28UL)         /*!< SMT7 (Bit 28)                                         */
31648  #define R_PORT_NSR_DRCTL_H_SMT7_Msk    (0x10000000UL) /*!< SMT7 (Bitfield-Mask: 0x01)                            */
31649  #define R_PORT_NSR_DRCTL_H_SR7_Pos     (29UL)         /*!< SR7 (Bit 29)                                          */
31650  #define R_PORT_NSR_DRCTL_H_SR7_Msk     (0x20000000UL) /*!< SR7 (Bitfield-Mask: 0x01)                             */
31651 
31652 /* =========================================================================================================================== */
31653 /* ================                                         ELC_PDBF                                          ================ */
31654 /* =========================================================================================================================== */
31655 
31656 /* ==========================================================  BY  =========================================================== */
31657  #define R_PORT_NSR_ELC_PDBF_BY_PB0_Pos    (0UL)    /*!< PB0 (Bit 0)                                           */
31658  #define R_PORT_NSR_ELC_PDBF_BY_PB0_Msk    (0x1UL)  /*!< PB0 (Bitfield-Mask: 0x01)                             */
31659  #define R_PORT_NSR_ELC_PDBF_BY_PB1_Pos    (1UL)    /*!< PB1 (Bit 1)                                           */
31660  #define R_PORT_NSR_ELC_PDBF_BY_PB1_Msk    (0x2UL)  /*!< PB1 (Bitfield-Mask: 0x01)                             */
31661  #define R_PORT_NSR_ELC_PDBF_BY_PB2_Pos    (2UL)    /*!< PB2 (Bit 2)                                           */
31662  #define R_PORT_NSR_ELC_PDBF_BY_PB2_Msk    (0x4UL)  /*!< PB2 (Bitfield-Mask: 0x01)                             */
31663  #define R_PORT_NSR_ELC_PDBF_BY_PB3_Pos    (3UL)    /*!< PB3 (Bit 3)                                           */
31664  #define R_PORT_NSR_ELC_PDBF_BY_PB3_Msk    (0x8UL)  /*!< PB3 (Bitfield-Mask: 0x01)                             */
31665  #define R_PORT_NSR_ELC_PDBF_BY_PB4_Pos    (4UL)    /*!< PB4 (Bit 4)                                           */
31666  #define R_PORT_NSR_ELC_PDBF_BY_PB4_Msk    (0x10UL) /*!< PB4 (Bitfield-Mask: 0x01)                             */
31667  #define R_PORT_NSR_ELC_PDBF_BY_PB5_Pos    (5UL)    /*!< PB5 (Bit 5)                                           */
31668  #define R_PORT_NSR_ELC_PDBF_BY_PB5_Msk    (0x20UL) /*!< PB5 (Bitfield-Mask: 0x01)                             */
31669  #define R_PORT_NSR_ELC_PDBF_BY_PB6_Pos    (6UL)    /*!< PB6 (Bit 6)                                           */
31670  #define R_PORT_NSR_ELC_PDBF_BY_PB6_Msk    (0x40UL) /*!< PB6 (Bitfield-Mask: 0x01)                             */
31671  #define R_PORT_NSR_ELC_PDBF_BY_PB7_Pos    (7UL)    /*!< PB7 (Bit 7)                                           */
31672  #define R_PORT_NSR_ELC_PDBF_BY_PB7_Msk    (0x80UL) /*!< PB7 (Bitfield-Mask: 0x01)                             */
31673 
31674 /* =========================================================================================================================== */
31675 /* ================                                           SWTM                                            ================ */
31676 /* =========================================================================================================================== */
31677 
31678 /* ==========================================================  EN  =========================================================== */
31679  #define R_ETHSW_PTP_SWTM_EN_OUTEN_Pos         (0UL)          /*!< OUTEN (Bit 0)                                         */
31680  #define R_ETHSW_PTP_SWTM_EN_OUTEN_Msk         (0x1UL)        /*!< OUTEN (Bitfield-Mask: 0x01)                           */
31681 /* =========================================================  STSEC  ========================================================= */
31682  #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Pos      (0UL)          /*!< STSEC (Bit 0)                                         */
31683  #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Msk      (0xffffffffUL) /*!< STSEC (Bitfield-Mask: 0xffffffff)                     */
31684 /* =========================================================  STNS  ========================================================== */
31685  #define R_ETHSW_PTP_SWTM_STNS_STNS_Pos        (0UL)          /*!< STNS (Bit 0)                                          */
31686  #define R_ETHSW_PTP_SWTM_STNS_STNS_Msk        (0xffffffffUL) /*!< STNS (Bitfield-Mask: 0xffffffff)                      */
31687 /* =========================================================  PSEC  ========================================================== */
31688  #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Pos        (0UL)          /*!< PSEC (Bit 0)                                          */
31689  #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Msk        (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff)                      */
31690 /* ==========================================================  PNS  ========================================================== */
31691  #define R_ETHSW_PTP_SWTM_PNS_PNS_Pos          (0UL)          /*!< PNS (Bit 0)                                           */
31692  #define R_ETHSW_PTP_SWTM_PNS_PNS_Msk          (0xffffffffUL) /*!< PNS (Bitfield-Mask: 0xffffffff)                       */
31693 /* ==========================================================  WTH  ========================================================== */
31694  #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Pos        (0UL)          /*!< WIDTH (Bit 0)                                         */
31695  #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Msk        (0xffffUL)     /*!< WIDTH (Bitfield-Mask: 0xffff)                         */
31696 /* =========================================================  MAXP  ========================================================== */
31697  #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Pos        (0UL)          /*!< MAXP (Bit 0)                                          */
31698  #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Msk        (0xffffffffUL) /*!< MAXP (Bitfield-Mask: 0xffffffff)                      */
31699 /* ========================================================  LATSEC  ========================================================= */
31700  #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Pos    (0UL)          /*!< LATSEC (Bit 0)                                        */
31701  #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Msk    (0xffffffffUL) /*!< LATSEC (Bitfield-Mask: 0xffffffff)                    */
31702 /* =========================================================  LATNS  ========================================================= */
31703  #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Pos      (0UL)          /*!< LATNS (Bit 0)                                         */
31704  #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Msk      (0xffffffffUL) /*!< LATNS (Bitfield-Mask: 0xffffffff)                     */
31705 
31706 /* =========================================================================================================================== */
31707 /* ================                                         MGMT_ADDR                                         ================ */
31708 /* =========================================================================================================================== */
31709 
31710 /* ==========================================================  lo  =========================================================== */
31711  #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Pos    (0UL)          /*!< BPDU_DST (Bit 0)                                      */
31712  #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Msk    (0xffffffffUL) /*!< BPDU_DST (Bitfield-Mask: 0xffffffff)                  */
31713 /* ==========================================================  hi  =========================================================== */
31714  #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Pos    (0UL)          /*!< BPDU_DST (Bit 0)                                      */
31715  #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Msk    (0xffffUL)     /*!< BPDU_DST (Bitfield-Mask: 0xffff)                      */
31716  #define R_ETHSW_MGMT_ADDR_hi_MASK_Pos        (16UL)         /*!< MASK (Bit 16)                                         */
31717  #define R_ETHSW_MGMT_ADDR_hi_MASK_Msk        (0xff0000UL)   /*!< MASK (Bitfield-Mask: 0xff)                            */
31718 
31719 /* =========================================================================================================================== */
31720 /* ================                                           FMMU                                            ================ */
31721 /* =========================================================================================================================== */
31722 
31723 /* ======================================================  L_START_ADR  ====================================================== */
31724  #define R_ESC_FMMU_L_START_ADR_LSTAADR_Pos      (0UL)          /*!< LSTAADR (Bit 0)                                       */
31725  #define R_ESC_FMMU_L_START_ADR_LSTAADR_Msk      (0xffffffffUL) /*!< LSTAADR (Bitfield-Mask: 0xffffffff)                   */
31726 /* ==========================================================  LEN  ========================================================== */
31727  #define R_ESC_FMMU_LEN_FMMULEN_Pos              (0UL)          /*!< FMMULEN (Bit 0)                                       */
31728  #define R_ESC_FMMU_LEN_FMMULEN_Msk              (0xffffUL)     /*!< FMMULEN (Bitfield-Mask: 0xffff)                       */
31729 /* ======================================================  L_START_BIT  ====================================================== */
31730  #define R_ESC_FMMU_L_START_BIT_LSTABIT_Pos      (0UL)          /*!< LSTABIT (Bit 0)                                       */
31731  #define R_ESC_FMMU_L_START_BIT_LSTABIT_Msk      (0x7UL)        /*!< LSTABIT (Bitfield-Mask: 0x07)                         */
31732 /* ======================================================  L_STOP_BIT  ======================================================= */
31733  #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Pos       (0UL)          /*!< LSTPBIT (Bit 0)                                       */
31734  #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Msk       (0x7UL)        /*!< LSTPBIT (Bitfield-Mask: 0x07)                         */
31735 /* ======================================================  P_START_ADR  ====================================================== */
31736  #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Pos    (0UL)          /*!< PHYSTAADR (Bit 0)                                     */
31737  #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Msk    (0xffffUL)     /*!< PHYSTAADR (Bitfield-Mask: 0xffff)                     */
31738 /* ======================================================  P_START_BIT  ====================================================== */
31739  #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Pos    (0UL)          /*!< PHYSTABIT (Bit 0)                                     */
31740  #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Msk    (0x7UL)        /*!< PHYSTABIT (Bitfield-Mask: 0x07)                       */
31741 /* =========================================================  TYPE  ========================================================== */
31742  #define R_ESC_FMMU_TYPE_READ_Pos                (0UL)          /*!< READ (Bit 0)                                          */
31743  #define R_ESC_FMMU_TYPE_READ_Msk                (0x1UL)        /*!< READ (Bitfield-Mask: 0x01)                            */
31744  #define R_ESC_FMMU_TYPE_WRITE_Pos               (1UL)          /*!< WRITE (Bit 1)                                         */
31745  #define R_ESC_FMMU_TYPE_WRITE_Msk               (0x2UL)        /*!< WRITE (Bitfield-Mask: 0x01)                           */
31746 /* ==========================================================  ACT  ========================================================== */
31747  #define R_ESC_FMMU_ACT_ACTIVATE_Pos             (0UL)          /*!< ACTIVATE (Bit 0)                                      */
31748  #define R_ESC_FMMU_ACT_ACTIVATE_Msk             (0x1UL)        /*!< ACTIVATE (Bitfield-Mask: 0x01)                        */
31749 
31750 /* =========================================================================================================================== */
31751 /* ================                                            SM                                             ================ */
31752 /* =========================================================================================================================== */
31753 
31754 /* ======================================================  P_START_ADR  ====================================================== */
31755  #define R_ESC_SM_P_START_ADR_SMSTAADDR_Pos    (0UL)      /*!< SMSTAADDR (Bit 0)                                     */
31756  #define R_ESC_SM_P_START_ADR_SMSTAADDR_Msk    (0xffffUL) /*!< SMSTAADDR (Bitfield-Mask: 0xffff)                     */
31757 /* ==========================================================  LEN  ========================================================== */
31758  #define R_ESC_SM_LEN_SMLEN_Pos                (0UL)      /*!< SMLEN (Bit 0)                                         */
31759  #define R_ESC_SM_LEN_SMLEN_Msk                (0xffffUL) /*!< SMLEN (Bitfield-Mask: 0xffff)                         */
31760 /* ========================================================  CONTROL  ======================================================== */
31761  #define R_ESC_SM_CONTROL_OPEMODE_Pos          (0UL)      /*!< OPEMODE (Bit 0)                                       */
31762  #define R_ESC_SM_CONTROL_OPEMODE_Msk          (0x3UL)    /*!< OPEMODE (Bitfield-Mask: 0x03)                         */
31763  #define R_ESC_SM_CONTROL_DIR_Pos              (2UL)      /*!< DIR (Bit 2)                                           */
31764  #define R_ESC_SM_CONTROL_DIR_Msk              (0xcUL)    /*!< DIR (Bitfield-Mask: 0x03)                             */
31765  #define R_ESC_SM_CONTROL_IRQECAT_Pos          (4UL)      /*!< IRQECAT (Bit 4)                                       */
31766  #define R_ESC_SM_CONTROL_IRQECAT_Msk          (0x10UL)   /*!< IRQECAT (Bitfield-Mask: 0x01)                         */
31767  #define R_ESC_SM_CONTROL_IRQPDI_Pos           (5UL)      /*!< IRQPDI (Bit 5)                                        */
31768  #define R_ESC_SM_CONTROL_IRQPDI_Msk           (0x20UL)   /*!< IRQPDI (Bitfield-Mask: 0x01)                          */
31769  #define R_ESC_SM_CONTROL_WDTRGEN_Pos          (6UL)      /*!< WDTRGEN (Bit 6)                                       */
31770  #define R_ESC_SM_CONTROL_WDTRGEN_Msk          (0x40UL)   /*!< WDTRGEN (Bitfield-Mask: 0x01)                         */
31771 /* ========================================================  STATUS  ========================================================= */
31772  #define R_ESC_SM_STATUS_INTWR_Pos             (0UL)      /*!< INTWR (Bit 0)                                         */
31773  #define R_ESC_SM_STATUS_INTWR_Msk             (0x1UL)    /*!< INTWR (Bitfield-Mask: 0x01)                           */
31774  #define R_ESC_SM_STATUS_INTRD_Pos             (1UL)      /*!< INTRD (Bit 1)                                         */
31775  #define R_ESC_SM_STATUS_INTRD_Msk             (0x2UL)    /*!< INTRD (Bitfield-Mask: 0x01)                           */
31776  #define R_ESC_SM_STATUS_MAILBOX_Pos           (3UL)      /*!< MAILBOX (Bit 3)                                       */
31777  #define R_ESC_SM_STATUS_MAILBOX_Msk           (0x8UL)    /*!< MAILBOX (Bitfield-Mask: 0x01)                         */
31778  #define R_ESC_SM_STATUS_BUFFERED_Pos          (4UL)      /*!< BUFFERED (Bit 4)                                      */
31779  #define R_ESC_SM_STATUS_BUFFERED_Msk          (0x30UL)   /*!< BUFFERED (Bitfield-Mask: 0x03)                        */
31780  #define R_ESC_SM_STATUS_RDBUF_Pos             (6UL)      /*!< RDBUF (Bit 6)                                         */
31781  #define R_ESC_SM_STATUS_RDBUF_Msk             (0x40UL)   /*!< RDBUF (Bitfield-Mask: 0x01)                           */
31782  #define R_ESC_SM_STATUS_WRBUF_Pos             (7UL)      /*!< WRBUF (Bit 7)                                         */
31783  #define R_ESC_SM_STATUS_WRBUF_Msk             (0x80UL)   /*!< WRBUF (Bitfield-Mask: 0x01)                           */
31784 /* ==========================================================  ACT  ========================================================== */
31785  #define R_ESC_SM_ACT_SMEN_Pos                 (0UL)      /*!< SMEN (Bit 0)                                          */
31786  #define R_ESC_SM_ACT_SMEN_Msk                 (0x1UL)    /*!< SMEN (Bitfield-Mask: 0x01)                            */
31787  #define R_ESC_SM_ACT_REPEATREQ_Pos            (1UL)      /*!< REPEATREQ (Bit 1)                                     */
31788  #define R_ESC_SM_ACT_REPEATREQ_Msk            (0x2UL)    /*!< REPEATREQ (Bitfield-Mask: 0x01)                       */
31789  #define R_ESC_SM_ACT_LATCHECAT_Pos            (6UL)      /*!< LATCHECAT (Bit 6)                                     */
31790  #define R_ESC_SM_ACT_LATCHECAT_Msk            (0x40UL)   /*!< LATCHECAT (Bitfield-Mask: 0x01)                       */
31791  #define R_ESC_SM_ACT_LATCHPDI_Pos             (7UL)      /*!< LATCHPDI (Bit 7)                                      */
31792  #define R_ESC_SM_ACT_LATCHPDI_Msk             (0x80UL)   /*!< LATCHPDI (Bitfield-Mask: 0x01)                        */
31793 /* =======================================================  PDI_CONT  ======================================================== */
31794  #define R_ESC_SM_PDI_CONT_DEACTIVE_Pos        (0UL)      /*!< DEACTIVE (Bit 0)                                      */
31795  #define R_ESC_SM_PDI_CONT_DEACTIVE_Msk        (0x1UL)    /*!< DEACTIVE (Bitfield-Mask: 0x01)                        */
31796  #define R_ESC_SM_PDI_CONT_REPEATACK_Pos       (1UL)      /*!< REPEATACK (Bit 1)                                     */
31797  #define R_ESC_SM_PDI_CONT_REPEATACK_Msk       (0x2UL)    /*!< REPEATACK (Bitfield-Mask: 0x01)                       */
31798 
31799 /* =========================================================================================================================== */
31800 /* ================                                          PIPE_TR                                          ================ */
31801 /* =========================================================================================================================== */
31802 
31803 /* ===========================================================  E  =========================================================== */
31804  #define R_USBF_PIPE_TR_E_TRCLR_Pos     (8UL)      /*!< TRCLR (Bit 8)                                         */
31805  #define R_USBF_PIPE_TR_E_TRCLR_Msk     (0x100UL)  /*!< TRCLR (Bitfield-Mask: 0x01)                           */
31806  #define R_USBF_PIPE_TR_E_TRENB_Pos     (9UL)      /*!< TRENB (Bit 9)                                         */
31807  #define R_USBF_PIPE_TR_E_TRENB_Msk     (0x200UL)  /*!< TRENB (Bitfield-Mask: 0x01)                           */
31808 /* ===========================================================  N  =========================================================== */
31809  #define R_USBF_PIPE_TR_N_TRNCNT_Pos    (0UL)      /*!< TRNCNT (Bit 0)                                        */
31810  #define R_USBF_PIPE_TR_N_TRNCNT_Msk    (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff)                        */
31811 
31812 /* =========================================================================================================================== */
31813 /* ================                                             N                                             ================ */
31814 /* =========================================================================================================================== */
31815 
31816 /* ==========================================================  SA  =========================================================== */
31817  #define R_USBF_CHa_N_SA_SAWD_Pos    (0UL)          /*!< SAWD (Bit 0)                                          */
31818  #define R_USBF_CHa_N_SA_SAWD_Msk    (0xffffffffUL) /*!< SAWD (Bitfield-Mask: 0xffffffff)                      */
31819 /* ==========================================================  DA  =========================================================== */
31820  #define R_USBF_CHa_N_DA_DA_Pos      (0UL)          /*!< DA (Bit 0)                                            */
31821  #define R_USBF_CHa_N_DA_DA_Msk      (0xffffffffUL) /*!< DA (Bitfield-Mask: 0xffffffff)                        */
31822 /* ==========================================================  TB  =========================================================== */
31823  #define R_USBF_CHa_N_TB_TB_Pos      (0UL)          /*!< TB (Bit 0)                                            */
31824  #define R_USBF_CHa_N_TB_TB_Msk      (0xffffffffUL) /*!< TB (Bitfield-Mask: 0xffffffff)                        */
31825 
31826 /* =========================================================================================================================== */
31827 /* ================                                            CHa                                            ================ */
31828 /* =========================================================================================================================== */
31829 
31830 /* =========================================================  CRSA  ========================================================== */
31831  #define R_USBF_CHa_CRSA_CRSA_Pos           (0UL)          /*!< CRSA (Bit 0)                                          */
31832  #define R_USBF_CHa_CRSA_CRSA_Msk           (0xffffffffUL) /*!< CRSA (Bitfield-Mask: 0xffffffff)                      */
31833 /* =========================================================  CRDA  ========================================================== */
31834  #define R_USBF_CHa_CRDA_CRDA_Pos           (0UL)          /*!< CRDA (Bit 0)                                          */
31835  #define R_USBF_CHa_CRDA_CRDA_Msk           (0xffffffffUL) /*!< CRDA (Bitfield-Mask: 0xffffffff)                      */
31836 /* =========================================================  CRTB  ========================================================== */
31837  #define R_USBF_CHa_CRTB_CRTB_Pos           (0UL)          /*!< CRTB (Bit 0)                                          */
31838  #define R_USBF_CHa_CRTB_CRTB_Msk           (0xffffffffUL) /*!< CRTB (Bitfield-Mask: 0xffffffff)                      */
31839 /* ========================================================  CHSTAT  ========================================================= */
31840  #define R_USBF_CHa_CHSTAT_EN_Pos           (0UL)          /*!< EN (Bit 0)                                            */
31841  #define R_USBF_CHa_CHSTAT_EN_Msk           (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
31842  #define R_USBF_CHa_CHSTAT_RQST_Pos         (1UL)          /*!< RQST (Bit 1)                                          */
31843  #define R_USBF_CHa_CHSTAT_RQST_Msk         (0x2UL)        /*!< RQST (Bitfield-Mask: 0x01)                            */
31844  #define R_USBF_CHa_CHSTAT_TACT_Pos         (2UL)          /*!< TACT (Bit 2)                                          */
31845  #define R_USBF_CHa_CHSTAT_TACT_Msk         (0x4UL)        /*!< TACT (Bitfield-Mask: 0x01)                            */
31846  #define R_USBF_CHa_CHSTAT_SUS_Pos          (3UL)          /*!< SUS (Bit 3)                                           */
31847  #define R_USBF_CHa_CHSTAT_SUS_Msk          (0x8UL)        /*!< SUS (Bitfield-Mask: 0x01)                             */
31848  #define R_USBF_CHa_CHSTAT_ER_Pos           (4UL)          /*!< ER (Bit 4)                                            */
31849  #define R_USBF_CHa_CHSTAT_ER_Msk           (0x10UL)       /*!< ER (Bitfield-Mask: 0x01)                              */
31850  #define R_USBF_CHa_CHSTAT_END_Pos          (5UL)          /*!< END (Bit 5)                                           */
31851  #define R_USBF_CHa_CHSTAT_END_Msk          (0x20UL)       /*!< END (Bitfield-Mask: 0x01)                             */
31852  #define R_USBF_CHa_CHSTAT_TC_Pos           (6UL)          /*!< TC (Bit 6)                                            */
31853  #define R_USBF_CHa_CHSTAT_TC_Msk           (0x40UL)       /*!< TC (Bitfield-Mask: 0x01)                              */
31854  #define R_USBF_CHa_CHSTAT_SR_Pos           (7UL)          /*!< SR (Bit 7)                                            */
31855  #define R_USBF_CHa_CHSTAT_SR_Msk           (0x80UL)       /*!< SR (Bitfield-Mask: 0x01)                              */
31856  #define R_USBF_CHa_CHSTAT_DL_Pos           (8UL)          /*!< DL (Bit 8)                                            */
31857  #define R_USBF_CHa_CHSTAT_DL_Msk           (0x100UL)      /*!< DL (Bitfield-Mask: 0x01)                              */
31858  #define R_USBF_CHa_CHSTAT_DW_Pos           (9UL)          /*!< DW (Bit 9)                                            */
31859  #define R_USBF_CHa_CHSTAT_DW_Msk           (0x200UL)      /*!< DW (Bitfield-Mask: 0x01)                              */
31860  #define R_USBF_CHa_CHSTAT_DER_Pos          (10UL)         /*!< DER (Bit 10)                                          */
31861  #define R_USBF_CHa_CHSTAT_DER_Msk          (0x400UL)      /*!< DER (Bitfield-Mask: 0x01)                             */
31862  #define R_USBF_CHa_CHSTAT_MODE_Pos         (11UL)         /*!< MODE (Bit 11)                                         */
31863  #define R_USBF_CHa_CHSTAT_MODE_Msk         (0x800UL)      /*!< MODE (Bitfield-Mask: 0x01)                            */
31864  #define R_USBF_CHa_CHSTAT_INTM_Pos         (16UL)         /*!< INTM (Bit 16)                                         */
31865  #define R_USBF_CHa_CHSTAT_INTM_Msk         (0x10000UL)    /*!< INTM (Bitfield-Mask: 0x01)                            */
31866  #define R_USBF_CHa_CHSTAT_DMARQM_Pos       (17UL)         /*!< DMARQM (Bit 17)                                       */
31867  #define R_USBF_CHa_CHSTAT_DMARQM_Msk       (0x20000UL)    /*!< DMARQM (Bitfield-Mask: 0x01)                          */
31868  #define R_USBF_CHa_CHSTAT_SWPRQ_Pos        (18UL)         /*!< SWPRQ (Bit 18)                                        */
31869  #define R_USBF_CHa_CHSTAT_SWPRQ_Msk        (0x40000UL)    /*!< SWPRQ (Bitfield-Mask: 0x01)                           */
31870  #define R_USBF_CHa_CHSTAT_DNUM_Pos         (24UL)         /*!< DNUM (Bit 24)                                         */
31871  #define R_USBF_CHa_CHSTAT_DNUM_Msk         (0xff000000UL) /*!< DNUM (Bitfield-Mask: 0xff)                            */
31872 /* ========================================================  CHCTRL  ========================================================= */
31873  #define R_USBF_CHa_CHCTRL_SETEN_Pos        (0UL)          /*!< SETEN (Bit 0)                                         */
31874  #define R_USBF_CHa_CHCTRL_SETEN_Msk        (0x1UL)        /*!< SETEN (Bitfield-Mask: 0x01)                           */
31875  #define R_USBF_CHa_CHCTRL_CLREN_Pos        (1UL)          /*!< CLREN (Bit 1)                                         */
31876  #define R_USBF_CHa_CHCTRL_CLREN_Msk        (0x2UL)        /*!< CLREN (Bitfield-Mask: 0x01)                           */
31877  #define R_USBF_CHa_CHCTRL_STG_Pos          (2UL)          /*!< STG (Bit 2)                                           */
31878  #define R_USBF_CHa_CHCTRL_STG_Msk          (0x4UL)        /*!< STG (Bitfield-Mask: 0x01)                             */
31879  #define R_USBF_CHa_CHCTRL_SWRST_Pos        (3UL)          /*!< SWRST (Bit 3)                                         */
31880  #define R_USBF_CHa_CHCTRL_SWRST_Msk        (0x8UL)        /*!< SWRST (Bitfield-Mask: 0x01)                           */
31881  #define R_USBF_CHa_CHCTRL_CLRRQ_Pos        (4UL)          /*!< CLRRQ (Bit 4)                                         */
31882  #define R_USBF_CHa_CHCTRL_CLRRQ_Msk        (0x10UL)       /*!< CLRRQ (Bitfield-Mask: 0x01)                           */
31883  #define R_USBF_CHa_CHCTRL_CLREND_Pos       (5UL)          /*!< CLREND (Bit 5)                                        */
31884  #define R_USBF_CHa_CHCTRL_CLREND_Msk       (0x20UL)       /*!< CLREND (Bitfield-Mask: 0x01)                          */
31885  #define R_USBF_CHa_CHCTRL_CLRTC_Pos        (6UL)          /*!< CLRTC (Bit 6)                                         */
31886  #define R_USBF_CHa_CHCTRL_CLRTC_Msk        (0x40UL)       /*!< CLRTC (Bitfield-Mask: 0x01)                           */
31887  #define R_USBF_CHa_CHCTRL_CLRDER_Pos       (7UL)          /*!< CLRDER (Bit 7)                                        */
31888  #define R_USBF_CHa_CHCTRL_CLRDER_Msk       (0x80UL)       /*!< CLRDER (Bitfield-Mask: 0x01)                          */
31889  #define R_USBF_CHa_CHCTRL_SETSUS_Pos       (8UL)          /*!< SETSUS (Bit 8)                                        */
31890  #define R_USBF_CHa_CHCTRL_SETSUS_Msk       (0x100UL)      /*!< SETSUS (Bitfield-Mask: 0x01)                          */
31891  #define R_USBF_CHa_CHCTRL_CLRSUS_Pos       (9UL)          /*!< CLRSUS (Bit 9)                                        */
31892  #define R_USBF_CHa_CHCTRL_CLRSUS_Msk       (0x200UL)      /*!< CLRSUS (Bitfield-Mask: 0x01)                          */
31893  #define R_USBF_CHa_CHCTRL_SETREN_Pos       (12UL)         /*!< SETREN (Bit 12)                                       */
31894  #define R_USBF_CHa_CHCTRL_SETREN_Msk       (0x1000UL)     /*!< SETREN (Bitfield-Mask: 0x01)                          */
31895  #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Pos    (14UL)         /*!< SETSSWPRQ (Bit 14)                                    */
31896  #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Msk    (0x4000UL)     /*!< SETSSWPRQ (Bitfield-Mask: 0x01)                       */
31897  #define R_USBF_CHa_CHCTRL_SETINTM_Pos      (16UL)         /*!< SETINTM (Bit 16)                                      */
31898  #define R_USBF_CHa_CHCTRL_SETINTM_Msk      (0x10000UL)    /*!< SETINTM (Bitfield-Mask: 0x01)                         */
31899  #define R_USBF_CHa_CHCTRL_CLRINTM_Pos      (17UL)         /*!< CLRINTM (Bit 17)                                      */
31900  #define R_USBF_CHa_CHCTRL_CLRINTM_Msk      (0x20000UL)    /*!< CLRINTM (Bitfield-Mask: 0x01)                         */
31901  #define R_USBF_CHa_CHCTRL_SETDMARQM_Pos    (18UL)         /*!< SETDMARQM (Bit 18)                                    */
31902  #define R_USBF_CHa_CHCTRL_SETDMARQM_Msk    (0x40000UL)    /*!< SETDMARQM (Bitfield-Mask: 0x01)                       */
31903  #define R_USBF_CHa_CHCTRL_CLRDMARQM_Pos    (19UL)         /*!< CLRDMARQM (Bit 19)                                    */
31904  #define R_USBF_CHa_CHCTRL_CLRDMARQM_Msk    (0x80000UL)    /*!< CLRDMARQM (Bitfield-Mask: 0x01)                       */
31905 /* =========================================================  CHCFG  ========================================================= */
31906  #define R_USBF_CHa_CHCFG_SEL_Pos           (0UL)          /*!< SEL (Bit 0)                                           */
31907  #define R_USBF_CHa_CHCFG_SEL_Msk           (0x1UL)        /*!< SEL (Bitfield-Mask: 0x01)                             */
31908  #define R_USBF_CHa_CHCFG_REQD_Pos          (3UL)          /*!< REQD (Bit 3)                                          */
31909  #define R_USBF_CHa_CHCFG_REQD_Msk          (0x8UL)        /*!< REQD (Bitfield-Mask: 0x01)                            */
31910  #define R_USBF_CHa_CHCFG_LOEN_Pos          (4UL)          /*!< LOEN (Bit 4)                                          */
31911  #define R_USBF_CHa_CHCFG_LOEN_Msk          (0x10UL)       /*!< LOEN (Bitfield-Mask: 0x01)                            */
31912  #define R_USBF_CHa_CHCFG_HIEN_Pos          (5UL)          /*!< HIEN (Bit 5)                                          */
31913  #define R_USBF_CHa_CHCFG_HIEN_Msk          (0x20UL)       /*!< HIEN (Bitfield-Mask: 0x01)                            */
31914  #define R_USBF_CHa_CHCFG_LVL_Pos           (6UL)          /*!< LVL (Bit 6)                                           */
31915  #define R_USBF_CHa_CHCFG_LVL_Msk           (0x40UL)       /*!< LVL (Bitfield-Mask: 0x01)                             */
31916  #define R_USBF_CHa_CHCFG_AM_Pos            (8UL)          /*!< AM (Bit 8)                                            */
31917  #define R_USBF_CHa_CHCFG_AM_Msk            (0x700UL)      /*!< AM (Bitfield-Mask: 0x07)                              */
31918  #define R_USBF_CHa_CHCFG_DRRP_Pos          (11UL)         /*!< DRRP (Bit 11)                                         */
31919  #define R_USBF_CHa_CHCFG_DRRP_Msk          (0x800UL)      /*!< DRRP (Bitfield-Mask: 0x01)                            */
31920  #define R_USBF_CHa_CHCFG_SDS_Pos           (12UL)         /*!< SDS (Bit 12)                                          */
31921  #define R_USBF_CHa_CHCFG_SDS_Msk           (0xf000UL)     /*!< SDS (Bitfield-Mask: 0x0f)                             */
31922  #define R_USBF_CHa_CHCFG_DDS_Pos           (16UL)         /*!< DDS (Bit 16)                                          */
31923  #define R_USBF_CHa_CHCFG_DDS_Msk           (0xf0000UL)    /*!< DDS (Bitfield-Mask: 0x0f)                             */
31924  #define R_USBF_CHa_CHCFG_SAD_Pos           (20UL)         /*!< SAD (Bit 20)                                          */
31925  #define R_USBF_CHa_CHCFG_SAD_Msk           (0x100000UL)   /*!< SAD (Bitfield-Mask: 0x01)                             */
31926  #define R_USBF_CHa_CHCFG_DAD_Pos           (21UL)         /*!< DAD (Bit 21)                                          */
31927  #define R_USBF_CHa_CHCFG_DAD_Msk           (0x200000UL)   /*!< DAD (Bitfield-Mask: 0x01)                             */
31928  #define R_USBF_CHa_CHCFG_TM_Pos            (22UL)         /*!< TM (Bit 22)                                           */
31929  #define R_USBF_CHa_CHCFG_TM_Msk            (0x400000UL)   /*!< TM (Bitfield-Mask: 0x01)                              */
31930  #define R_USBF_CHa_CHCFG_WONLY_Pos         (23UL)         /*!< WONLY (Bit 23)                                        */
31931  #define R_USBF_CHa_CHCFG_WONLY_Msk         (0x800000UL)   /*!< WONLY (Bitfield-Mask: 0x01)                           */
31932  #define R_USBF_CHa_CHCFG_DEM_Pos           (24UL)         /*!< DEM (Bit 24)                                          */
31933  #define R_USBF_CHa_CHCFG_DEM_Msk           (0x1000000UL)  /*!< DEM (Bitfield-Mask: 0x01)                             */
31934  #define R_USBF_CHa_CHCFG_DIM_Pos           (26UL)         /*!< DIM (Bit 26)                                          */
31935  #define R_USBF_CHa_CHCFG_DIM_Msk           (0x4000000UL)  /*!< DIM (Bitfield-Mask: 0x01)                             */
31936  #define R_USBF_CHa_CHCFG_SBE_Pos           (27UL)         /*!< SBE (Bit 27)                                          */
31937  #define R_USBF_CHa_CHCFG_SBE_Msk           (0x8000000UL)  /*!< SBE (Bitfield-Mask: 0x01)                             */
31938  #define R_USBF_CHa_CHCFG_RSEL_Pos          (28UL)         /*!< RSEL (Bit 28)                                         */
31939  #define R_USBF_CHa_CHCFG_RSEL_Msk          (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01)                            */
31940  #define R_USBF_CHa_CHCFG_RSW_Pos           (29UL)         /*!< RSW (Bit 29)                                          */
31941  #define R_USBF_CHa_CHCFG_RSW_Msk           (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01)                             */
31942  #define R_USBF_CHa_CHCFG_REN_Pos           (30UL)         /*!< REN (Bit 30)                                          */
31943  #define R_USBF_CHa_CHCFG_REN_Msk           (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01)                             */
31944  #define R_USBF_CHa_CHCFG_DMS_Pos           (31UL)         /*!< DMS (Bit 31)                                          */
31945  #define R_USBF_CHa_CHCFG_DMS_Msk           (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01)                             */
31946 /* ========================================================  CHITVL  ========================================================= */
31947  #define R_USBF_CHa_CHITVL_ITVL_Pos         (0UL)          /*!< ITVL (Bit 0)                                          */
31948  #define R_USBF_CHa_CHITVL_ITVL_Msk         (0xffffUL)     /*!< ITVL (Bitfield-Mask: 0xffff)                          */
31949 /* =========================================================  CHEXT  ========================================================= */
31950  #define R_USBF_CHa_CHEXT_SPR_Pos           (0UL)          /*!< SPR (Bit 0)                                           */
31951  #define R_USBF_CHa_CHEXT_SPR_Msk           (0xfUL)        /*!< SPR (Bitfield-Mask: 0x0f)                             */
31952  #define R_USBF_CHa_CHEXT_DPR_Pos           (8UL)          /*!< DPR (Bit 8)                                           */
31953  #define R_USBF_CHa_CHEXT_DPR_Msk           (0xf00UL)      /*!< DPR (Bitfield-Mask: 0x0f)                             */
31954 /* =========================================================  NXLA  ========================================================== */
31955  #define R_USBF_CHa_NXLA_NXLA_Pos           (0UL)          /*!< NXLA (Bit 0)                                          */
31956  #define R_USBF_CHa_NXLA_NXLA_Msk           (0xffffffffUL) /*!< NXLA (Bitfield-Mask: 0xffffffff)                      */
31957 /* =========================================================  CRLA  ========================================================== */
31958  #define R_USBF_CHa_CRLA_CRLA_Pos           (0UL)          /*!< CRLA (Bit 0)                                          */
31959  #define R_USBF_CHa_CRLA_CRLA_Msk           (0xffffffffUL) /*!< CRLA (Bitfield-Mask: 0xffffffff)                      */
31960 
31961 /* =========================================================================================================================== */
31962 /* ================                                            CHb                                            ================ */
31963 /* =========================================================================================================================== */
31964 
31965 /* =========================================================  SCNT  ========================================================== */
31966  #define R_USBF_CHb_SCNT_SCNT_Pos    (0UL)          /*!< SCNT (Bit 0)                                          */
31967  #define R_USBF_CHb_SCNT_SCNT_Msk    (0xffffffffUL) /*!< SCNT (Bitfield-Mask: 0xffffffff)                      */
31968 /* =========================================================  SSKP  ========================================================== */
31969  #define R_USBF_CHb_SSKP_SSKP_Pos    (0UL)          /*!< SSKP (Bit 0)                                          */
31970  #define R_USBF_CHb_SSKP_SSKP_Msk    (0xffffffffUL) /*!< SSKP (Bitfield-Mask: 0xffffffff)                      */
31971 /* =========================================================  DCNT  ========================================================== */
31972  #define R_USBF_CHb_DCNT_DCNT_Pos    (0UL)          /*!< DCNT (Bit 0)                                          */
31973  #define R_USBF_CHb_DCNT_DCNT_Msk    (0xffffffffUL) /*!< DCNT (Bitfield-Mask: 0xffffffff)                      */
31974 /* =========================================================  DSKP  ========================================================== */
31975  #define R_USBF_CHb_DSKP_DSKP_Pos    (0UL)          /*!< DSKP (Bit 0)                                          */
31976  #define R_USBF_CHb_DSKP_DSKP_Msk    (0xffffffffUL) /*!< DSKP (Bitfield-Mask: 0xffffffff)                      */
31977 
31978 /* =========================================================================================================================== */
31979 /* ================                                            CSa                                            ================ */
31980 /* =========================================================================================================================== */
31981 
31982 /* ========================================================  CMCFG0  ========================================================= */
31983  #define R_XSPI0_CSa_CMCFG0_FFMT_Pos       (0UL)          /*!< FFMT (Bit 0)                                          */
31984  #define R_XSPI0_CSa_CMCFG0_FFMT_Msk       (0x3UL)        /*!< FFMT (Bitfield-Mask: 0x03)                            */
31985  #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Pos    (2UL)          /*!< ADDSIZE (Bit 2)                                       */
31986  #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Msk    (0xcUL)        /*!< ADDSIZE (Bitfield-Mask: 0x03)                         */
31987  #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Pos    (16UL)         /*!< ADDRPEN (Bit 16)                                      */
31988  #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Msk    (0xff0000UL)   /*!< ADDRPEN (Bitfield-Mask: 0xff)                         */
31989  #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Pos    (24UL)         /*!< ADDRPCD (Bit 24)                                      */
31990  #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Msk    (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff)                         */
31991 /* ========================================================  CMCFG1  ========================================================= */
31992  #define R_XSPI0_CSa_CMCFG1_RDCMD_Pos      (0UL)          /*!< RDCMD (Bit 0)                                         */
31993  #define R_XSPI0_CSa_CMCFG1_RDCMD_Msk      (0xffffUL)     /*!< RDCMD (Bitfield-Mask: 0xffff)                         */
31994  #define R_XSPI0_CSa_CMCFG1_RDLATE_Pos     (16UL)         /*!< RDLATE (Bit 16)                                       */
31995  #define R_XSPI0_CSa_CMCFG1_RDLATE_Msk     (0x1f0000UL)   /*!< RDLATE (Bitfield-Mask: 0x1f)                          */
31996 /* ========================================================  CMCFG2  ========================================================= */
31997  #define R_XSPI0_CSa_CMCFG2_WRCMD_Pos      (0UL)          /*!< WRCMD (Bit 0)                                         */
31998  #define R_XSPI0_CSa_CMCFG2_WRCMD_Msk      (0xffffUL)     /*!< WRCMD (Bitfield-Mask: 0xffff)                         */
31999  #define R_XSPI0_CSa_CMCFG2_WRLATE_Pos     (16UL)         /*!< WRLATE (Bit 16)                                       */
32000  #define R_XSPI0_CSa_CMCFG2_WRLATE_Msk     (0x1f0000UL)   /*!< WRLATE (Bitfield-Mask: 0x1f)                          */
32001 
32002 /* =========================================================================================================================== */
32003 /* ================                                            BUF                                            ================ */
32004 /* =========================================================================================================================== */
32005 
32006 /* ==========================================================  CDT  ========================================================== */
32007  #define R_XSPI0_BUF_CDT_CMDSIZE_Pos     (0UL)          /*!< CMDSIZE (Bit 0)                                       */
32008  #define R_XSPI0_BUF_CDT_CMDSIZE_Msk     (0x3UL)        /*!< CMDSIZE (Bitfield-Mask: 0x03)                         */
32009  #define R_XSPI0_BUF_CDT_ADDSIZE_Pos     (2UL)          /*!< ADDSIZE (Bit 2)                                       */
32010  #define R_XSPI0_BUF_CDT_ADDSIZE_Msk     (0x1cUL)       /*!< ADDSIZE (Bitfield-Mask: 0x07)                         */
32011  #define R_XSPI0_BUF_CDT_DATASIZE_Pos    (5UL)          /*!< DATASIZE (Bit 5)                                      */
32012  #define R_XSPI0_BUF_CDT_DATASIZE_Msk    (0x1e0UL)      /*!< DATASIZE (Bitfield-Mask: 0x0f)                        */
32013  #define R_XSPI0_BUF_CDT_LATE_Pos        (9UL)          /*!< LATE (Bit 9)                                          */
32014  #define R_XSPI0_BUF_CDT_LATE_Msk        (0x3e00UL)     /*!< LATE (Bitfield-Mask: 0x1f)                            */
32015  #define R_XSPI0_BUF_CDT_TRTYPE_Pos      (15UL)         /*!< TRTYPE (Bit 15)                                       */
32016  #define R_XSPI0_BUF_CDT_TRTYPE_Msk      (0x8000UL)     /*!< TRTYPE (Bitfield-Mask: 0x01)                          */
32017  #define R_XSPI0_BUF_CDT_CMD_Pos         (16UL)         /*!< CMD (Bit 16)                                          */
32018  #define R_XSPI0_BUF_CDT_CMD_Msk         (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff)                           */
32019 /* ==========================================================  CDA  ========================================================== */
32020  #define R_XSPI0_BUF_CDA_ADD_Pos         (0UL)          /*!< ADD (Bit 0)                                           */
32021  #define R_XSPI0_BUF_CDA_ADD_Msk         (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff)                       */
32022 /* =========================================================  CDD0  ========================================================== */
32023  #define R_XSPI0_BUF_CDD0_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
32024  #define R_XSPI0_BUF_CDD0_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
32025 /* =========================================================  CDD1  ========================================================== */
32026  #define R_XSPI0_BUF_CDD1_DATA_Pos       (0UL)          /*!< DATA (Bit 0)                                          */
32027  #define R_XSPI0_BUF_CDD1_DATA_Msk       (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
32028 
32029 /* =========================================================================================================================== */
32030 /* ================                                            CSb                                            ================ */
32031 /* =========================================================================================================================== */
32032 
32033 /* ========================================================  CCCTL0  ========================================================= */
32034  #define R_XSPI0_CSb_CCCTL0_CAEN_Pos          (0UL)          /*!< CAEN (Bit 0)                                          */
32035  #define R_XSPI0_CSb_CCCTL0_CAEN_Msk          (0x1UL)        /*!< CAEN (Bitfield-Mask: 0x01)                            */
32036  #define R_XSPI0_CSb_CCCTL0_CANOWR_Pos        (1UL)          /*!< CANOWR (Bit 1)                                        */
32037  #define R_XSPI0_CSb_CCCTL0_CANOWR_Msk        (0x2UL)        /*!< CANOWR (Bitfield-Mask: 0x01)                          */
32038  #define R_XSPI0_CSb_CCCTL0_CAITV_Pos         (8UL)          /*!< CAITV (Bit 8)                                         */
32039  #define R_XSPI0_CSb_CCCTL0_CAITV_Msk         (0x1f00UL)     /*!< CAITV (Bitfield-Mask: 0x1f)                           */
32040  #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Pos      (16UL)         /*!< CASFTSTA (Bit 16)                                     */
32041  #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Msk      (0x1f0000UL)   /*!< CASFTSTA (Bitfield-Mask: 0x1f)                        */
32042  #define R_XSPI0_CSb_CCCTL0_CASFTEND_Pos      (24UL)         /*!< CASFTEND (Bit 24)                                     */
32043  #define R_XSPI0_CSb_CCCTL0_CASFTEND_Msk      (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f)                        */
32044 /* ========================================================  CCCTL1  ========================================================= */
32045  #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Pos     (0UL)          /*!< CACMDSIZE (Bit 0)                                     */
32046  #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Msk     (0x3UL)        /*!< CACMDSIZE (Bitfield-Mask: 0x03)                       */
32047  #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Pos     (2UL)          /*!< CAADDSIZE (Bit 2)                                     */
32048  #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Msk     (0x1cUL)       /*!< CAADDSIZE (Bitfield-Mask: 0x07)                       */
32049  #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Pos    (5UL)          /*!< CADATASIZE (Bit 5)                                    */
32050  #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Msk    (0x1e0UL)      /*!< CADATASIZE (Bitfield-Mask: 0x0f)                      */
32051  #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Pos      (16UL)         /*!< CAWRLATE (Bit 16)                                     */
32052  #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Msk      (0x1f0000UL)   /*!< CAWRLATE (Bitfield-Mask: 0x1f)                        */
32053  #define R_XSPI0_CSb_CCCTL1_CARDLATE_Pos      (24UL)         /*!< CARDLATE (Bit 24)                                     */
32054  #define R_XSPI0_CSb_CCCTL1_CARDLATE_Msk      (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f)                        */
32055 /* ========================================================  CCCTL2  ========================================================= */
32056  #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Pos       (0UL)          /*!< CAWRCMD (Bit 0)                                       */
32057  #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Msk       (0xffffUL)     /*!< CAWRCMD (Bitfield-Mask: 0xffff)                       */
32058  #define R_XSPI0_CSb_CCCTL2_CARDCMD_Pos       (16UL)         /*!< CARDCMD (Bit 16)                                      */
32059  #define R_XSPI0_CSb_CCCTL2_CARDCMD_Msk       (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff)                       */
32060 /* ========================================================  CCCTL3  ========================================================= */
32061  #define R_XSPI0_CSb_CCCTL3_CAADD_Pos         (0UL)          /*!< CAADD (Bit 0)                                         */
32062  #define R_XSPI0_CSb_CCCTL3_CAADD_Msk         (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff)                     */
32063 /* ========================================================  CCCTL4  ========================================================= */
32064  #define R_XSPI0_CSb_CCCTL4_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
32065  #define R_XSPI0_CSb_CCCTL4_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
32066 /* ========================================================  CCCTL5  ========================================================= */
32067  #define R_XSPI0_CSb_CCCTL5_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
32068  #define R_XSPI0_CSb_CCCTL5_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
32069 /* ========================================================  CCCTL6  ========================================================= */
32070  #define R_XSPI0_CSb_CCCTL6_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
32071  #define R_XSPI0_CSb_CCCTL6_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
32072 /* ========================================================  CCCTL7  ========================================================= */
32073  #define R_XSPI0_CSb_CCCTL7_CADATA_Pos        (0UL)          /*!< CADATA (Bit 0)                                        */
32074  #define R_XSPI0_CSb_CCCTL7_CADATA_Msk        (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff)                    */
32075 
32076 /* =========================================================================================================================== */
32077 /* ================                                             W                                             ================ */
32078 /* =========================================================================================================================== */
32079 
32080 /* =======================================================  EC710CTL  ======================================================== */
32081  #define R_SYSRAM0_W_EC710CTL_ECEMF_Pos      (0UL)          /*!< ECEMF (Bit 0)                                         */
32082  #define R_SYSRAM0_W_EC710CTL_ECEMF_Msk      (0x1UL)        /*!< ECEMF (Bitfield-Mask: 0x01)                           */
32083  #define R_SYSRAM0_W_EC710CTL_ECER1F_Pos     (1UL)          /*!< ECER1F (Bit 1)                                        */
32084  #define R_SYSRAM0_W_EC710CTL_ECER1F_Msk     (0x2UL)        /*!< ECER1F (Bitfield-Mask: 0x01)                          */
32085  #define R_SYSRAM0_W_EC710CTL_ECER2F_Pos     (2UL)          /*!< ECER2F (Bit 2)                                        */
32086  #define R_SYSRAM0_W_EC710CTL_ECER2F_Msk     (0x4UL)        /*!< ECER2F (Bitfield-Mask: 0x01)                          */
32087  #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Pos    (3UL)          /*!< EC1EDIC (Bit 3)                                       */
32088  #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Msk    (0x8UL)        /*!< EC1EDIC (Bitfield-Mask: 0x01)                         */
32089  #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Pos    (4UL)          /*!< EC2EDIC (Bit 4)                                       */
32090  #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Msk    (0x10UL)       /*!< EC2EDIC (Bitfield-Mask: 0x01)                         */
32091  #define R_SYSRAM0_W_EC710CTL_EC1ECP_Pos     (5UL)          /*!< EC1ECP (Bit 5)                                        */
32092  #define R_SYSRAM0_W_EC710CTL_EC1ECP_Msk     (0x20UL)       /*!< EC1ECP (Bitfield-Mask: 0x01)                          */
32093  #define R_SYSRAM0_W_EC710CTL_ECERVF_Pos     (6UL)          /*!< ECERVF (Bit 6)                                        */
32094  #define R_SYSRAM0_W_EC710CTL_ECERVF_Msk     (0x40UL)       /*!< ECERVF (Bitfield-Mask: 0x01)                          */
32095  #define R_SYSRAM0_W_EC710CTL_ECTHM_Pos      (7UL)          /*!< ECTHM (Bit 7)                                         */
32096  #define R_SYSRAM0_W_EC710CTL_ECTHM_Msk      (0x80UL)       /*!< ECTHM (Bitfield-Mask: 0x01)                           */
32097  #define R_SYSRAM0_W_EC710CTL_ECER1C_Pos     (9UL)          /*!< ECER1C (Bit 9)                                        */
32098  #define R_SYSRAM0_W_EC710CTL_ECER1C_Msk     (0x200UL)      /*!< ECER1C (Bitfield-Mask: 0x01)                          */
32099  #define R_SYSRAM0_W_EC710CTL_ECER2C_Pos     (10UL)         /*!< ECER2C (Bit 10)                                       */
32100  #define R_SYSRAM0_W_EC710CTL_ECER2C_Msk     (0x400UL)      /*!< ECER2C (Bitfield-Mask: 0x01)                          */
32101  #define R_SYSRAM0_W_EC710CTL_ECOVFF_Pos     (11UL)         /*!< ECOVFF (Bit 11)                                       */
32102  #define R_SYSRAM0_W_EC710CTL_ECOVFF_Msk     (0x800UL)      /*!< ECOVFF (Bitfield-Mask: 0x01)                          */
32103  #define R_SYSRAM0_W_EC710CTL_EMCA_Pos       (14UL)         /*!< EMCA (Bit 14)                                         */
32104  #define R_SYSRAM0_W_EC710CTL_EMCA_Msk       (0xc000UL)     /*!< EMCA (Bitfield-Mask: 0x03)                            */
32105  #define R_SYSRAM0_W_EC710CTL_ECEDF0_Pos     (16UL)         /*!< ECEDF0 (Bit 16)                                       */
32106  #define R_SYSRAM0_W_EC710CTL_ECEDF0_Msk     (0x30000UL)    /*!< ECEDF0 (Bitfield-Mask: 0x03)                          */
32107  #define R_SYSRAM0_W_EC710CTL_ECEDF1_Pos     (18UL)         /*!< ECEDF1 (Bit 18)                                       */
32108  #define R_SYSRAM0_W_EC710CTL_ECEDF1_Msk     (0xc0000UL)    /*!< ECEDF1 (Bitfield-Mask: 0x03)                          */
32109  #define R_SYSRAM0_W_EC710CTL_ECEDF2_Pos     (20UL)         /*!< ECEDF2 (Bit 20)                                       */
32110  #define R_SYSRAM0_W_EC710CTL_ECEDF2_Msk     (0x300000UL)   /*!< ECEDF2 (Bitfield-Mask: 0x03)                          */
32111  #define R_SYSRAM0_W_EC710CTL_ECEDF3_Pos     (22UL)         /*!< ECEDF3 (Bit 22)                                       */
32112  #define R_SYSRAM0_W_EC710CTL_ECEDF3_Msk     (0xc00000UL)   /*!< ECEDF3 (Bitfield-Mask: 0x03)                          */
32113  #define R_SYSRAM0_W_EC710CTL_ECEDF4_Pos     (24UL)         /*!< ECEDF4 (Bit 24)                                       */
32114  #define R_SYSRAM0_W_EC710CTL_ECEDF4_Msk     (0x3000000UL)  /*!< ECEDF4 (Bitfield-Mask: 0x03)                          */
32115  #define R_SYSRAM0_W_EC710CTL_ECEDF5_Pos     (26UL)         /*!< ECEDF5 (Bit 26)                                       */
32116  #define R_SYSRAM0_W_EC710CTL_ECEDF5_Msk     (0xc000000UL)  /*!< ECEDF5 (Bitfield-Mask: 0x03)                          */
32117  #define R_SYSRAM0_W_EC710CTL_ECEDF6_Pos     (28UL)         /*!< ECEDF6 (Bit 28)                                       */
32118  #define R_SYSRAM0_W_EC710CTL_ECEDF6_Msk     (0x30000000UL) /*!< ECEDF6 (Bitfield-Mask: 0x03)                          */
32119  #define R_SYSRAM0_W_EC710CTL_ECEDF7_Pos     (30UL)         /*!< ECEDF7 (Bit 30)                                       */
32120  #define R_SYSRAM0_W_EC710CTL_ECEDF7_Msk     (0xc0000000UL) /*!< ECEDF7 (Bitfield-Mask: 0x03)                          */
32121 /* =======================================================  EC710TMC  ======================================================== */
32122  #define R_SYSRAM0_W_EC710TMC_ECREIS_Pos     (0UL)          /*!< ECREIS (Bit 0)                                        */
32123  #define R_SYSRAM0_W_EC710TMC_ECREIS_Msk     (0x1UL)        /*!< ECREIS (Bitfield-Mask: 0x01)                          */
32124  #define R_SYSRAM0_W_EC710TMC_ECDCS_Pos      (1UL)          /*!< ECDCS (Bit 1)                                         */
32125  #define R_SYSRAM0_W_EC710TMC_ECDCS_Msk      (0x2UL)        /*!< ECDCS (Bitfield-Mask: 0x01)                           */
32126  #define R_SYSRAM0_W_EC710TMC_ECENS_Pos      (2UL)          /*!< ECENS (Bit 2)                                         */
32127  #define R_SYSRAM0_W_EC710TMC_ECENS_Msk      (0x4UL)        /*!< ECENS (Bitfield-Mask: 0x01)                           */
32128  #define R_SYSRAM0_W_EC710TMC_ECREOS_Pos     (3UL)          /*!< ECREOS (Bit 3)                                        */
32129  #define R_SYSRAM0_W_EC710TMC_ECREOS_Msk     (0x8UL)        /*!< ECREOS (Bitfield-Mask: 0x01)                          */
32130  #define R_SYSRAM0_W_EC710TMC_ECTRRS_Pos     (4UL)          /*!< ECTRRS (Bit 4)                                        */
32131  #define R_SYSRAM0_W_EC710TMC_ECTRRS_Msk     (0x10UL)       /*!< ECTRRS (Bitfield-Mask: 0x01)                          */
32132  #define R_SYSRAM0_W_EC710TMC_ECTMCE_Pos     (7UL)          /*!< ECTMCE (Bit 7)                                        */
32133  #define R_SYSRAM0_W_EC710TMC_ECTMCE_Msk     (0x80UL)       /*!< ECTMCE (Bitfield-Mask: 0x01)                          */
32134  #define R_SYSRAM0_W_EC710TMC_ETMA_Pos       (14UL)         /*!< ETMA (Bit 14)                                         */
32135  #define R_SYSRAM0_W_EC710TMC_ETMA_Msk       (0xc000UL)     /*!< ETMA (Bitfield-Mask: 0x03)                            */
32136 /* =======================================================  EC710TRC  ======================================================== */
32137  #define R_SYSRAM0_W_EC710TRC_ECERDB_Pos     (0UL)          /*!< ECERDB (Bit 0)                                        */
32138  #define R_SYSRAM0_W_EC710TRC_ECERDB_Msk     (0x7fUL)       /*!< ECERDB (Bitfield-Mask: 0x7f)                          */
32139  #define R_SYSRAM0_W_EC710TRC_ECECRD_Pos     (8UL)          /*!< ECECRD (Bit 8)                                        */
32140  #define R_SYSRAM0_W_EC710TRC_ECECRD_Msk     (0x7f00UL)     /*!< ECECRD (Bitfield-Mask: 0x7f)                          */
32141  #define R_SYSRAM0_W_EC710TRC_ECHORD_Pos     (16UL)         /*!< ECHORD (Bit 16)                                       */
32142  #define R_SYSRAM0_W_EC710TRC_ECHORD_Msk     (0x7f0000UL)   /*!< ECHORD (Bitfield-Mask: 0x7f)                          */
32143  #define R_SYSRAM0_W_EC710TRC_ECSYND_Pos     (24UL)         /*!< ECSYND (Bit 24)                                       */
32144  #define R_SYSRAM0_W_EC710TRC_ECSYND_Msk     (0x7f000000UL) /*!< ECSYND (Bitfield-Mask: 0x7f)                          */
32145 /* =======================================================  EC710TED  ======================================================== */
32146  #define R_SYSRAM0_W_EC710TED_ECEDB_Pos      (0UL)          /*!< ECEDB (Bit 0)                                         */
32147  #define R_SYSRAM0_W_EC710TED_ECEDB_Msk      (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff)                     */
32148 /* =======================================================  EC710EAD  ======================================================== */
32149  #define R_SYSRAM0_W_EC710EAD_ECEAD_Pos      (0UL)          /*!< ECEAD (Bit 0)                                         */
32150  #define R_SYSRAM0_W_EC710EAD_ECEAD_Msk      (0x7fffUL)     /*!< ECEAD (Bitfield-Mask: 0x7fff)                         */
32151 
32152 /* =========================================================================================================================== */
32153 /* ================                                            RGN                                            ================ */
32154 /* =========================================================================================================================== */
32155 
32156 /* =========================================================  STADD  ========================================================= */
32157  #define R_MPU0_RGN_STADD_RDPR_Pos        (0UL)          /*!< RDPR (Bit 0)                                          */
32158  #define R_MPU0_RGN_STADD_RDPR_Msk        (0x1UL)        /*!< RDPR (Bitfield-Mask: 0x01)                            */
32159  #define R_MPU0_RGN_STADD_WRPR_Pos        (1UL)          /*!< WRPR (Bit 1)                                          */
32160  #define R_MPU0_RGN_STADD_WRPR_Msk        (0x2UL)        /*!< WRPR (Bitfield-Mask: 0x01)                            */
32161  #define R_MPU0_RGN_STADD_STADDR_Pos      (10UL)         /*!< STADDR (Bit 10)                                       */
32162  #define R_MPU0_RGN_STADD_STADDR_Msk      (0xfffffc00UL) /*!< STADDR (Bitfield-Mask: 0x3fffff)                      */
32163 /* ========================================================  ENDADD  ========================================================= */
32164  #define R_MPU0_RGN_ENDADD_ENDADDR_Pos    (10UL)         /*!< ENDADDR (Bit 10)                                      */
32165  #define R_MPU0_RGN_ENDADD_ENDADDR_Msk    (0xfffffc00UL) /*!< ENDADDR (Bitfield-Mask: 0x3fffff)                     */
32166 
32167 /* =========================================================================================================================== */
32168 /* ================                                            CH                                             ================ */
32169 /* =========================================================================================================================== */
32170 
32171 /* =========================================================  DSICR  ========================================================= */
32172  #define R_DSMIF0_CH_DSICR_IOEL_Pos         (0UL)          /*!< IOEL (Bit 0)                                          */
32173  #define R_DSMIF0_CH_DSICR_IOEL_Msk         (0x1UL)        /*!< IOEL (Bitfield-Mask: 0x01)                            */
32174  #define R_DSMIF0_CH_DSICR_IOEH_Pos         (1UL)          /*!< IOEH (Bit 1)                                          */
32175  #define R_DSMIF0_CH_DSICR_IOEH_Msk         (0x2UL)        /*!< IOEH (Bitfield-Mask: 0x01)                            */
32176  #define R_DSMIF0_CH_DSICR_ISE_Pos          (2UL)          /*!< ISE (Bit 2)                                           */
32177  #define R_DSMIF0_CH_DSICR_ISE_Msk          (0x4UL)        /*!< ISE (Bitfield-Mask: 0x01)                             */
32178  #define R_DSMIF0_CH_DSICR_IUE_Pos          (3UL)          /*!< IUE (Bit 3)                                           */
32179  #define R_DSMIF0_CH_DSICR_IUE_Msk          (0x8UL)        /*!< IUE (Bitfield-Mask: 0x01)                             */
32180 /* ========================================================  DSCMCCR  ======================================================== */
32181  #define R_DSMIF0_CH_DSCMCCR_CKDIR_Pos      (0UL)          /*!< CKDIR (Bit 0)                                         */
32182  #define R_DSMIF0_CH_DSCMCCR_CKDIR_Msk      (0x1UL)        /*!< CKDIR (Bitfield-Mask: 0x01)                           */
32183  #define R_DSMIF0_CH_DSCMCCR_SEDGE_Pos      (7UL)          /*!< SEDGE (Bit 7)                                         */
32184  #define R_DSMIF0_CH_DSCMCCR_SEDGE_Msk      (0x80UL)       /*!< SEDGE (Bitfield-Mask: 0x01)                           */
32185  #define R_DSMIF0_CH_DSCMCCR_CKDIV_Pos      (8UL)          /*!< CKDIV (Bit 8)                                         */
32186  #define R_DSMIF0_CH_DSCMCCR_CKDIV_Msk      (0x3f00UL)     /*!< CKDIV (Bitfield-Mask: 0x3f)                           */
32187 /* ========================================================  DSCMFCR  ======================================================== */
32188  #define R_DSMIF0_CH_DSCMFCR_CMSINC_Pos     (0UL)          /*!< CMSINC (Bit 0)                                        */
32189  #define R_DSMIF0_CH_DSCMFCR_CMSINC_Msk     (0x3UL)        /*!< CMSINC (Bitfield-Mask: 0x03)                          */
32190  #define R_DSMIF0_CH_DSCMFCR_CMDEC_Pos      (8UL)          /*!< CMDEC (Bit 8)                                         */
32191  #define R_DSMIF0_CH_DSCMFCR_CMDEC_Msk      (0xff00UL)     /*!< CMDEC (Bitfield-Mask: 0xff)                           */
32192  #define R_DSMIF0_CH_DSCMFCR_CMSH_Pos       (16UL)         /*!< CMSH (Bit 16)                                         */
32193  #define R_DSMIF0_CH_DSCMFCR_CMSH_Msk       (0x1f0000UL)   /*!< CMSH (Bitfield-Mask: 0x1f)                            */
32194 /* =======================================================  DSCMCTCR  ======================================================== */
32195  #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Pos    (0UL)          /*!< CTSELA (Bit 0)                                        */
32196  #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Msk    (0x7UL)        /*!< CTSELA (Bitfield-Mask: 0x07)                          */
32197  #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Pos    (8UL)          /*!< CTSELB (Bit 8)                                        */
32198  #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Msk    (0x700UL)      /*!< CTSELB (Bitfield-Mask: 0x07)                          */
32199  #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Pos    (16UL)         /*!< DITSEL (Bit 16)                                       */
32200  #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Msk    (0x30000UL)    /*!< DITSEL (Bitfield-Mask: 0x03)                          */
32201  #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Pos     (23UL)         /*!< DEDGE (Bit 23)                                        */
32202  #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Msk     (0x800000UL)   /*!< DEDGE (Bitfield-Mask: 0x01)                           */
32203 /* ========================================================  DSEDCR  ========================================================= */
32204  #define R_DSMIF0_CH_DSEDCR_SDE_Pos         (0UL)          /*!< SDE (Bit 0)                                           */
32205  #define R_DSMIF0_CH_DSEDCR_SDE_Msk         (0x1UL)        /*!< SDE (Bitfield-Mask: 0x01)                             */
32206 /* ========================================================  DSOCFCR  ======================================================== */
32207  #define R_DSMIF0_CH_DSOCFCR_OCSINC_Pos     (0UL)          /*!< OCSINC (Bit 0)                                        */
32208  #define R_DSMIF0_CH_DSOCFCR_OCSINC_Msk     (0x3UL)        /*!< OCSINC (Bitfield-Mask: 0x03)                          */
32209  #define R_DSMIF0_CH_DSOCFCR_OCDEC_Pos      (8UL)          /*!< OCDEC (Bit 8)                                         */
32210  #define R_DSMIF0_CH_DSOCFCR_OCDEC_Msk      (0xff00UL)     /*!< OCDEC (Bitfield-Mask: 0xff)                           */
32211  #define R_DSMIF0_CH_DSOCFCR_OCSH_Pos       (16UL)         /*!< OCSH (Bit 16)                                         */
32212  #define R_DSMIF0_CH_DSOCFCR_OCSH_Msk       (0x1f0000UL)   /*!< OCSH (Bitfield-Mask: 0x1f)                            */
32213 /* ========================================================  DSOCLTR  ======================================================== */
32214  #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Pos    (0UL)          /*!< OCMPTBL (Bit 0)                                       */
32215  #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Msk    (0xffffUL)     /*!< OCMPTBL (Bitfield-Mask: 0xffff)                       */
32216 /* ========================================================  DSOCHTR  ======================================================== */
32217  #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Pos    (0UL)          /*!< OCMPTBH (Bit 0)                                       */
32218  #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Msk    (0xffffUL)     /*!< OCMPTBH (Bitfield-Mask: 0xffff)                       */
32219 /* ========================================================  DSSCTSR  ======================================================== */
32220  #define R_DSMIF0_CH_DSSCTSR_SCNTL_Pos      (0UL)          /*!< SCNTL (Bit 0)                                         */
32221  #define R_DSMIF0_CH_DSSCTSR_SCNTL_Msk      (0x1fffUL)     /*!< SCNTL (Bitfield-Mask: 0x1fff)                         */
32222  #define R_DSMIF0_CH_DSSCTSR_SCNTH_Pos      (16UL)         /*!< SCNTH (Bit 16)                                        */
32223  #define R_DSMIF0_CH_DSSCTSR_SCNTH_Msk      (0x1fff0000UL) /*!< SCNTH (Bitfield-Mask: 0x1fff)                         */
32224 /* ========================================================  DSODCR  ========================================================= */
32225  #define R_DSMIF0_CH_DSODCR_ODEL_Pos        (0UL)          /*!< ODEL (Bit 0)                                          */
32226  #define R_DSMIF0_CH_DSODCR_ODEL_Msk        (0x1UL)        /*!< ODEL (Bitfield-Mask: 0x01)                            */
32227  #define R_DSMIF0_CH_DSODCR_ODEH_Pos        (1UL)          /*!< ODEH (Bit 1)                                          */
32228  #define R_DSMIF0_CH_DSODCR_ODEH_Msk        (0x2UL)        /*!< ODEH (Bitfield-Mask: 0x01)                            */
32229 /* =======================================================  DSCSTRTR  ======================================================== */
32230  #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Pos    (0UL)          /*!< STRTRG (Bit 0)                                        */
32231  #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Msk    (0x1UL)        /*!< STRTRG (Bitfield-Mask: 0x01)                          */
32232 /* =======================================================  DSCSTPTR  ======================================================== */
32233  #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Pos    (0UL)          /*!< STPTRG (Bit 0)                                        */
32234  #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Msk    (0x1UL)        /*!< STPTRG (Bitfield-Mask: 0x01)                          */
32235 /* =========================================================  DSCDR  ========================================================= */
32236  #define R_DSMIF0_CH_DSCDR_ADDR_Pos         (0UL)          /*!< ADDR (Bit 0)                                          */
32237  #define R_DSMIF0_CH_DSCDR_ADDR_Msk         (0xffffUL)     /*!< ADDR (Bitfield-Mask: 0xffff)                          */
32238 /* ========================================================  DSCCDRA  ======================================================== */
32239  #define R_DSMIF0_CH_DSCCDRA_CDRA_Pos       (0UL)          /*!< CDRA (Bit 0)                                          */
32240  #define R_DSMIF0_CH_DSCCDRA_CDRA_Msk       (0xffffUL)     /*!< CDRA (Bitfield-Mask: 0xffff)                          */
32241 /* ========================================================  DSCCDRB  ======================================================== */
32242  #define R_DSMIF0_CH_DSCCDRB_CDRB_Pos       (0UL)          /*!< CDRB (Bit 0)                                          */
32243  #define R_DSMIF0_CH_DSCCDRB_CDRB_Msk       (0xffffUL)     /*!< CDRB (Bitfield-Mask: 0xffff)                          */
32244 /* ========================================================  DSOCDR  ========================================================= */
32245  #define R_DSMIF0_CH_DSOCDR_ODR_Pos         (0UL)          /*!< ODR (Bit 0)                                           */
32246  #define R_DSMIF0_CH_DSOCDR_ODR_Msk         (0xffffUL)     /*!< ODR (Bitfield-Mask: 0xffff)                           */
32247 /* ========================================================  DSCOCDR  ======================================================== */
32248  #define R_DSMIF0_CH_DSCOCDR_CODR_Pos       (0UL)          /*!< CODR (Bit 0)                                          */
32249  #define R_DSMIF0_CH_DSCOCDR_CODR_Msk       (0xffffUL)     /*!< CODR (Bitfield-Mask: 0xffff)                          */
32250 /* =========================================================  DSCSR  ========================================================= */
32251  #define R_DSMIF0_CH_DSCSR_DUF_Pos          (0UL)          /*!< DUF (Bit 0)                                           */
32252  #define R_DSMIF0_CH_DSCSR_DUF_Msk          (0x1UL)        /*!< DUF (Bitfield-Mask: 0x01)                             */
32253  #define R_DSMIF0_CH_DSCSR_OCFL_Pos         (1UL)          /*!< OCFL (Bit 1)                                          */
32254  #define R_DSMIF0_CH_DSCSR_OCFL_Msk         (0x2UL)        /*!< OCFL (Bitfield-Mask: 0x01)                            */
32255  #define R_DSMIF0_CH_DSCSR_OCFH_Pos         (2UL)          /*!< OCFH (Bit 2)                                          */
32256  #define R_DSMIF0_CH_DSCSR_OCFH_Msk         (0x4UL)        /*!< OCFH (Bitfield-Mask: 0x01)                            */
32257  #define R_DSMIF0_CH_DSCSR_SCF_Pos          (3UL)          /*!< SCF (Bit 3)                                           */
32258  #define R_DSMIF0_CH_DSCSR_SCF_Msk          (0x8UL)        /*!< SCF (Bitfield-Mask: 0x01)                             */
32259  #define R_DSMIF0_CH_DSCSR_CHSTATE_Pos      (16UL)         /*!< CHSTATE (Bit 16)                                      */
32260  #define R_DSMIF0_CH_DSCSR_CHSTATE_Msk      (0x10000UL)    /*!< CHSTATE (Bitfield-Mask: 0x01)                         */
32261 /* ========================================================  DSCSCR  ========================================================= */
32262  #define R_DSMIF0_CH_DSCSCR_CLRDUF_Pos      (0UL)          /*!< CLRDUF (Bit 0)                                        */
32263  #define R_DSMIF0_CH_DSCSCR_CLRDUF_Msk      (0x1UL)        /*!< CLRDUF (Bitfield-Mask: 0x01)                          */
32264  #define R_DSMIF0_CH_DSCSCR_CLROCFL_Pos     (1UL)          /*!< CLROCFL (Bit 1)                                       */
32265  #define R_DSMIF0_CH_DSCSCR_CLROCFL_Msk     (0x2UL)        /*!< CLROCFL (Bitfield-Mask: 0x01)                         */
32266  #define R_DSMIF0_CH_DSCSCR_CLROCFH_Pos     (2UL)          /*!< CLROCFH (Bit 2)                                       */
32267  #define R_DSMIF0_CH_DSCSCR_CLROCFH_Msk     (0x4UL)        /*!< CLROCFH (Bitfield-Mask: 0x01)                         */
32268  #define R_DSMIF0_CH_DSCSCR_CLRSCF_Pos      (3UL)          /*!< CLRSCF (Bit 3)                                        */
32269  #define R_DSMIF0_CH_DSCSCR_CLRSCF_Msk      (0x8UL)        /*!< CLRSCF (Bitfield-Mask: 0x01)                          */
32270 
32271 /** @} */ /* End of group PosMask_clusters */
32272 
32273 /* =========================================================================================================================== */
32274 /* ================                                Pos/Mask Peripheral Section                                ================ */
32275 /* =========================================================================================================================== */
32276 
32277 /** @addtogroup PosMask_peripherals
32278  * @{
32279  */
32280 
32281 /* =========================================================================================================================== */
32282 /* ================                                          R_GPT0                                           ================ */
32283 /* =========================================================================================================================== */
32284 
32285 /* =========================================================  GTWP  ========================================================== */
32286  #define R_GPT7_GTWP_WP_Pos              (0UL)          /*!< WP (Bit 0)                                            */
32287  #define R_GPT7_GTWP_WP_Msk              (0x1UL)        /*!< WP (Bitfield-Mask: 0x01)                              */
32288  #define R_GPT7_GTWP_STRWP_Pos           (1UL)          /*!< STRWP (Bit 1)                                         */
32289  #define R_GPT7_GTWP_STRWP_Msk           (0x2UL)        /*!< STRWP (Bitfield-Mask: 0x01)                           */
32290  #define R_GPT7_GTWP_STPWP_Pos           (2UL)          /*!< STPWP (Bit 2)                                         */
32291  #define R_GPT7_GTWP_STPWP_Msk           (0x4UL)        /*!< STPWP (Bitfield-Mask: 0x01)                           */
32292  #define R_GPT7_GTWP_CLRWP_Pos           (3UL)          /*!< CLRWP (Bit 3)                                         */
32293  #define R_GPT7_GTWP_CLRWP_Msk           (0x8UL)        /*!< CLRWP (Bitfield-Mask: 0x01)                           */
32294  #define R_GPT7_GTWP_CMNWP_Pos           (4UL)          /*!< CMNWP (Bit 4)                                         */
32295  #define R_GPT7_GTWP_CMNWP_Msk           (0x10UL)       /*!< CMNWP (Bitfield-Mask: 0x01)                           */
32296  #define R_GPT7_GTWP_PRKEY_Pos           (8UL)          /*!< PRKEY (Bit 8)                                         */
32297  #define R_GPT7_GTWP_PRKEY_Msk           (0xff00UL)     /*!< PRKEY (Bitfield-Mask: 0xff)                           */
32298 /* =========================================================  GTSTR  ========================================================= */
32299  #define R_GPT7_GTSTR_CSTRT0_Pos         (0UL)          /*!< CSTRT0 (Bit 0)                                        */
32300  #define R_GPT7_GTSTR_CSTRT0_Msk         (0x1UL)        /*!< CSTRT0 (Bitfield-Mask: 0x01)                          */
32301  #define R_GPT7_GTSTR_CSTRT1_Pos         (1UL)          /*!< CSTRT1 (Bit 1)                                        */
32302  #define R_GPT7_GTSTR_CSTRT1_Msk         (0x2UL)        /*!< CSTRT1 (Bitfield-Mask: 0x01)                          */
32303  #define R_GPT7_GTSTR_CSTRT2_Pos         (2UL)          /*!< CSTRT2 (Bit 2)                                        */
32304  #define R_GPT7_GTSTR_CSTRT2_Msk         (0x4UL)        /*!< CSTRT2 (Bitfield-Mask: 0x01)                          */
32305  #define R_GPT7_GTSTR_CSTRT3_Pos         (3UL)          /*!< CSTRT3 (Bit 3)                                        */
32306  #define R_GPT7_GTSTR_CSTRT3_Msk         (0x8UL)        /*!< CSTRT3 (Bitfield-Mask: 0x01)                          */
32307  #define R_GPT7_GTSTR_CSTRT4_Pos         (4UL)          /*!< CSTRT4 (Bit 4)                                        */
32308  #define R_GPT7_GTSTR_CSTRT4_Msk         (0x10UL)       /*!< CSTRT4 (Bitfield-Mask: 0x01)                          */
32309  #define R_GPT7_GTSTR_CSTRT5_Pos         (5UL)          /*!< CSTRT5 (Bit 5)                                        */
32310  #define R_GPT7_GTSTR_CSTRT5_Msk         (0x20UL)       /*!< CSTRT5 (Bitfield-Mask: 0x01)                          */
32311  #define R_GPT7_GTSTR_CSTRT6_Pos         (6UL)          /*!< CSTRT6 (Bit 6)                                        */
32312  #define R_GPT7_GTSTR_CSTRT6_Msk         (0x40UL)       /*!< CSTRT6 (Bitfield-Mask: 0x01)                          */
32313 /* =========================================================  GTSTP  ========================================================= */
32314  #define R_GPT7_GTSTP_CSTOP0_Pos         (0UL)          /*!< CSTOP0 (Bit 0)                                        */
32315  #define R_GPT7_GTSTP_CSTOP0_Msk         (0x1UL)        /*!< CSTOP0 (Bitfield-Mask: 0x01)                          */
32316  #define R_GPT7_GTSTP_CSTOP1_Pos         (1UL)          /*!< CSTOP1 (Bit 1)                                        */
32317  #define R_GPT7_GTSTP_CSTOP1_Msk         (0x2UL)        /*!< CSTOP1 (Bitfield-Mask: 0x01)                          */
32318  #define R_GPT7_GTSTP_CSTOP2_Pos         (2UL)          /*!< CSTOP2 (Bit 2)                                        */
32319  #define R_GPT7_GTSTP_CSTOP2_Msk         (0x4UL)        /*!< CSTOP2 (Bitfield-Mask: 0x01)                          */
32320  #define R_GPT7_GTSTP_CSTOP3_Pos         (3UL)          /*!< CSTOP3 (Bit 3)                                        */
32321  #define R_GPT7_GTSTP_CSTOP3_Msk         (0x8UL)        /*!< CSTOP3 (Bitfield-Mask: 0x01)                          */
32322  #define R_GPT7_GTSTP_CSTOP4_Pos         (4UL)          /*!< CSTOP4 (Bit 4)                                        */
32323  #define R_GPT7_GTSTP_CSTOP4_Msk         (0x10UL)       /*!< CSTOP4 (Bitfield-Mask: 0x01)                          */
32324  #define R_GPT7_GTSTP_CSTOP5_Pos         (5UL)          /*!< CSTOP5 (Bit 5)                                        */
32325  #define R_GPT7_GTSTP_CSTOP5_Msk         (0x20UL)       /*!< CSTOP5 (Bitfield-Mask: 0x01)                          */
32326  #define R_GPT7_GTSTP_CSTOP6_Pos         (6UL)          /*!< CSTOP6 (Bit 6)                                        */
32327  #define R_GPT7_GTSTP_CSTOP6_Msk         (0x40UL)       /*!< CSTOP6 (Bitfield-Mask: 0x01)                          */
32328 /* =========================================================  GTCLR  ========================================================= */
32329  #define R_GPT7_GTCLR_CCLR0_Pos          (0UL)          /*!< CCLR0 (Bit 0)                                         */
32330  #define R_GPT7_GTCLR_CCLR0_Msk          (0x1UL)        /*!< CCLR0 (Bitfield-Mask: 0x01)                           */
32331  #define R_GPT7_GTCLR_CCLR1_Pos          (1UL)          /*!< CCLR1 (Bit 1)                                         */
32332  #define R_GPT7_GTCLR_CCLR1_Msk          (0x2UL)        /*!< CCLR1 (Bitfield-Mask: 0x01)                           */
32333  #define R_GPT7_GTCLR_CCLR2_Pos          (2UL)          /*!< CCLR2 (Bit 2)                                         */
32334  #define R_GPT7_GTCLR_CCLR2_Msk          (0x4UL)        /*!< CCLR2 (Bitfield-Mask: 0x01)                           */
32335  #define R_GPT7_GTCLR_CCLR3_Pos          (3UL)          /*!< CCLR3 (Bit 3)                                         */
32336  #define R_GPT7_GTCLR_CCLR3_Msk          (0x8UL)        /*!< CCLR3 (Bitfield-Mask: 0x01)                           */
32337  #define R_GPT7_GTCLR_CCLR4_Pos          (4UL)          /*!< CCLR4 (Bit 4)                                         */
32338  #define R_GPT7_GTCLR_CCLR4_Msk          (0x10UL)       /*!< CCLR4 (Bitfield-Mask: 0x01)                           */
32339  #define R_GPT7_GTCLR_CCLR5_Pos          (5UL)          /*!< CCLR5 (Bit 5)                                         */
32340  #define R_GPT7_GTCLR_CCLR5_Msk          (0x20UL)       /*!< CCLR5 (Bitfield-Mask: 0x01)                           */
32341  #define R_GPT7_GTCLR_CCLR6_Pos          (6UL)          /*!< CCLR6 (Bit 6)                                         */
32342  #define R_GPT7_GTCLR_CCLR6_Msk          (0x40UL)       /*!< CCLR6 (Bitfield-Mask: 0x01)                           */
32343 /* =========================================================  GTSSR  ========================================================= */
32344  #define R_GPT7_GTSSR_SSGTRGAFR_Pos      (0UL)          /*!< SSGTRGAFR (Bit 0)                                     */
32345  #define R_GPT7_GTSSR_SSGTRGAFR_Msk      (0x3UL)        /*!< SSGTRGAFR (Bitfield-Mask: 0x03)                       */
32346  #define R_GPT7_GTSSR_SSGTRGBFR_Pos      (2UL)          /*!< SSGTRGBFR (Bit 2)                                     */
32347  #define R_GPT7_GTSSR_SSGTRGBFR_Msk      (0xcUL)        /*!< SSGTRGBFR (Bitfield-Mask: 0x03)                       */
32348  #define R_GPT7_GTSSR_SSGTRGCFR_Pos      (4UL)          /*!< SSGTRGCFR (Bit 4)                                     */
32349  #define R_GPT7_GTSSR_SSGTRGCFR_Msk      (0x30UL)       /*!< SSGTRGCFR (Bitfield-Mask: 0x03)                       */
32350  #define R_GPT7_GTSSR_SSGTRGDFR_Pos      (6UL)          /*!< SSGTRGDFR (Bit 6)                                     */
32351  #define R_GPT7_GTSSR_SSGTRGDFR_Msk      (0xc0UL)       /*!< SSGTRGDFR (Bitfield-Mask: 0x03)                       */
32352  #define R_GPT7_GTSSR_SSCARBHL_Pos       (8UL)          /*!< SSCARBHL (Bit 8)                                      */
32353  #define R_GPT7_GTSSR_SSCARBHL_Msk       (0x300UL)      /*!< SSCARBHL (Bitfield-Mask: 0x03)                        */
32354  #define R_GPT7_GTSSR_SSCAFBHL_Pos       (10UL)         /*!< SSCAFBHL (Bit 10)                                     */
32355  #define R_GPT7_GTSSR_SSCAFBHL_Msk       (0xc00UL)      /*!< SSCAFBHL (Bitfield-Mask: 0x03)                        */
32356  #define R_GPT7_GTSSR_SSCBRAHL_Pos       (12UL)         /*!< SSCBRAHL (Bit 12)                                     */
32357  #define R_GPT7_GTSSR_SSCBRAHL_Msk       (0x3000UL)     /*!< SSCBRAHL (Bitfield-Mask: 0x03)                        */
32358  #define R_GPT7_GTSSR_SSCBFAHL_Pos       (14UL)         /*!< SSCBFAHL (Bit 14)                                     */
32359  #define R_GPT7_GTSSR_SSCBFAHL_Msk       (0xc000UL)     /*!< SSCBFAHL (Bitfield-Mask: 0x03)                        */
32360  #define R_GPT7_GTSSR_SSELCA_Pos         (16UL)         /*!< SSELCA (Bit 16)                                       */
32361  #define R_GPT7_GTSSR_SSELCA_Msk         (0x10000UL)    /*!< SSELCA (Bitfield-Mask: 0x01)                          */
32362  #define R_GPT7_GTSSR_SSELCB_Pos         (17UL)         /*!< SSELCB (Bit 17)                                       */
32363  #define R_GPT7_GTSSR_SSELCB_Msk         (0x20000UL)    /*!< SSELCB (Bitfield-Mask: 0x01)                          */
32364  #define R_GPT7_GTSSR_SSELCC_Pos         (18UL)         /*!< SSELCC (Bit 18)                                       */
32365  #define R_GPT7_GTSSR_SSELCC_Msk         (0x40000UL)    /*!< SSELCC (Bitfield-Mask: 0x01)                          */
32366  #define R_GPT7_GTSSR_SSELCD_Pos         (19UL)         /*!< SSELCD (Bit 19)                                       */
32367  #define R_GPT7_GTSSR_SSELCD_Msk         (0x80000UL)    /*!< SSELCD (Bitfield-Mask: 0x01)                          */
32368  #define R_GPT7_GTSSR_SSELCE_Pos         (20UL)         /*!< SSELCE (Bit 20)                                       */
32369  #define R_GPT7_GTSSR_SSELCE_Msk         (0x100000UL)   /*!< SSELCE (Bitfield-Mask: 0x01)                          */
32370  #define R_GPT7_GTSSR_SSELCF_Pos         (21UL)         /*!< SSELCF (Bit 21)                                       */
32371  #define R_GPT7_GTSSR_SSELCF_Msk         (0x200000UL)   /*!< SSELCF (Bitfield-Mask: 0x01)                          */
32372  #define R_GPT7_GTSSR_SSELCG_Pos         (22UL)         /*!< SSELCG (Bit 22)                                       */
32373  #define R_GPT7_GTSSR_SSELCG_Msk         (0x400000UL)   /*!< SSELCG (Bitfield-Mask: 0x01)                          */
32374  #define R_GPT7_GTSSR_SSELCH_Pos         (23UL)         /*!< SSELCH (Bit 23)                                       */
32375  #define R_GPT7_GTSSR_SSELCH_Msk         (0x800000UL)   /*!< SSELCH (Bitfield-Mask: 0x01)                          */
32376  #define R_GPT7_GTSSR_CSTRT_Pos          (31UL)         /*!< CSTRT (Bit 31)                                        */
32377  #define R_GPT7_GTSSR_CSTRT_Msk          (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01)                           */
32378 /* =========================================================  GTPSR  ========================================================= */
32379  #define R_GPT7_GTPSR_PSGTRGAFR_Pos      (0UL)          /*!< PSGTRGAFR (Bit 0)                                     */
32380  #define R_GPT7_GTPSR_PSGTRGAFR_Msk      (0x3UL)        /*!< PSGTRGAFR (Bitfield-Mask: 0x03)                       */
32381  #define R_GPT7_GTPSR_PSGTRGBFR_Pos      (2UL)          /*!< PSGTRGBFR (Bit 2)                                     */
32382  #define R_GPT7_GTPSR_PSGTRGBFR_Msk      (0xcUL)        /*!< PSGTRGBFR (Bitfield-Mask: 0x03)                       */
32383  #define R_GPT7_GTPSR_PSGTRGCFR_Pos      (4UL)          /*!< PSGTRGCFR (Bit 4)                                     */
32384  #define R_GPT7_GTPSR_PSGTRGCFR_Msk      (0x30UL)       /*!< PSGTRGCFR (Bitfield-Mask: 0x03)                       */
32385  #define R_GPT7_GTPSR_PSGTRGDFR_Pos      (6UL)          /*!< PSGTRGDFR (Bit 6)                                     */
32386  #define R_GPT7_GTPSR_PSGTRGDFR_Msk      (0xc0UL)       /*!< PSGTRGDFR (Bitfield-Mask: 0x03)                       */
32387  #define R_GPT7_GTPSR_PSCARBHL_Pos       (8UL)          /*!< PSCARBHL (Bit 8)                                      */
32388  #define R_GPT7_GTPSR_PSCARBHL_Msk       (0x300UL)      /*!< PSCARBHL (Bitfield-Mask: 0x03)                        */
32389  #define R_GPT7_GTPSR_PSCAFBHL_Pos       (10UL)         /*!< PSCAFBHL (Bit 10)                                     */
32390  #define R_GPT7_GTPSR_PSCAFBHL_Msk       (0xc00UL)      /*!< PSCAFBHL (Bitfield-Mask: 0x03)                        */
32391  #define R_GPT7_GTPSR_PSCBRAHL_Pos       (12UL)         /*!< PSCBRAHL (Bit 12)                                     */
32392  #define R_GPT7_GTPSR_PSCBRAHL_Msk       (0x3000UL)     /*!< PSCBRAHL (Bitfield-Mask: 0x03)                        */
32393  #define R_GPT7_GTPSR_PSCBFAHL_Pos       (14UL)         /*!< PSCBFAHL (Bit 14)                                     */
32394  #define R_GPT7_GTPSR_PSCBFAHL_Msk       (0xc000UL)     /*!< PSCBFAHL (Bitfield-Mask: 0x03)                        */
32395  #define R_GPT7_GTPSR_PSELCA_Pos         (16UL)         /*!< PSELCA (Bit 16)                                       */
32396  #define R_GPT7_GTPSR_PSELCA_Msk         (0x10000UL)    /*!< PSELCA (Bitfield-Mask: 0x01)                          */
32397  #define R_GPT7_GTPSR_PSELCB_Pos         (17UL)         /*!< PSELCB (Bit 17)                                       */
32398  #define R_GPT7_GTPSR_PSELCB_Msk         (0x20000UL)    /*!< PSELCB (Bitfield-Mask: 0x01)                          */
32399  #define R_GPT7_GTPSR_PSELCC_Pos         (18UL)         /*!< PSELCC (Bit 18)                                       */
32400  #define R_GPT7_GTPSR_PSELCC_Msk         (0x40000UL)    /*!< PSELCC (Bitfield-Mask: 0x01)                          */
32401  #define R_GPT7_GTPSR_PSELCD_Pos         (19UL)         /*!< PSELCD (Bit 19)                                       */
32402  #define R_GPT7_GTPSR_PSELCD_Msk         (0x80000UL)    /*!< PSELCD (Bitfield-Mask: 0x01)                          */
32403  #define R_GPT7_GTPSR_PSELCE_Pos         (20UL)         /*!< PSELCE (Bit 20)                                       */
32404  #define R_GPT7_GTPSR_PSELCE_Msk         (0x100000UL)   /*!< PSELCE (Bitfield-Mask: 0x01)                          */
32405  #define R_GPT7_GTPSR_PSELCF_Pos         (21UL)         /*!< PSELCF (Bit 21)                                       */
32406  #define R_GPT7_GTPSR_PSELCF_Msk         (0x200000UL)   /*!< PSELCF (Bitfield-Mask: 0x01)                          */
32407  #define R_GPT7_GTPSR_PSELCG_Pos         (22UL)         /*!< PSELCG (Bit 22)                                       */
32408  #define R_GPT7_GTPSR_PSELCG_Msk         (0x400000UL)   /*!< PSELCG (Bitfield-Mask: 0x01)                          */
32409  #define R_GPT7_GTPSR_PSELCH_Pos         (23UL)         /*!< PSELCH (Bit 23)                                       */
32410  #define R_GPT7_GTPSR_PSELCH_Msk         (0x800000UL)   /*!< PSELCH (Bitfield-Mask: 0x01)                          */
32411  #define R_GPT7_GTPSR_CSTOP_Pos          (31UL)         /*!< CSTOP (Bit 31)                                        */
32412  #define R_GPT7_GTPSR_CSTOP_Msk          (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01)                           */
32413 /* =========================================================  GTCSR  ========================================================= */
32414  #define R_GPT7_GTCSR_CSGTRGAFR_Pos      (0UL)          /*!< CSGTRGAFR (Bit 0)                                     */
32415  #define R_GPT7_GTCSR_CSGTRGAFR_Msk      (0x3UL)        /*!< CSGTRGAFR (Bitfield-Mask: 0x03)                       */
32416  #define R_GPT7_GTCSR_CSGTRGBFR_Pos      (2UL)          /*!< CSGTRGBFR (Bit 2)                                     */
32417  #define R_GPT7_GTCSR_CSGTRGBFR_Msk      (0xcUL)        /*!< CSGTRGBFR (Bitfield-Mask: 0x03)                       */
32418  #define R_GPT7_GTCSR_CSGTRGCFR_Pos      (4UL)          /*!< CSGTRGCFR (Bit 4)                                     */
32419  #define R_GPT7_GTCSR_CSGTRGCFR_Msk      (0x30UL)       /*!< CSGTRGCFR (Bitfield-Mask: 0x03)                       */
32420  #define R_GPT7_GTCSR_CSGTRGDFR_Pos      (6UL)          /*!< CSGTRGDFR (Bit 6)                                     */
32421  #define R_GPT7_GTCSR_CSGTRGDFR_Msk      (0xc0UL)       /*!< CSGTRGDFR (Bitfield-Mask: 0x03)                       */
32422  #define R_GPT7_GTCSR_CSCARBHL_Pos       (8UL)          /*!< CSCARBHL (Bit 8)                                      */
32423  #define R_GPT7_GTCSR_CSCARBHL_Msk       (0x300UL)      /*!< CSCARBHL (Bitfield-Mask: 0x03)                        */
32424  #define R_GPT7_GTCSR_CSCAFBHL_Pos       (10UL)         /*!< CSCAFBHL (Bit 10)                                     */
32425  #define R_GPT7_GTCSR_CSCAFBHL_Msk       (0xc00UL)      /*!< CSCAFBHL (Bitfield-Mask: 0x03)                        */
32426  #define R_GPT7_GTCSR_CSCBRAHL_Pos       (12UL)         /*!< CSCBRAHL (Bit 12)                                     */
32427  #define R_GPT7_GTCSR_CSCBRAHL_Msk       (0x3000UL)     /*!< CSCBRAHL (Bitfield-Mask: 0x03)                        */
32428  #define R_GPT7_GTCSR_CSCBFAHL_Pos       (14UL)         /*!< CSCBFAHL (Bit 14)                                     */
32429  #define R_GPT7_GTCSR_CSCBFAHL_Msk       (0xc000UL)     /*!< CSCBFAHL (Bitfield-Mask: 0x03)                        */
32430  #define R_GPT7_GTCSR_CSELCA_Pos         (16UL)         /*!< CSELCA (Bit 16)                                       */
32431  #define R_GPT7_GTCSR_CSELCA_Msk         (0x10000UL)    /*!< CSELCA (Bitfield-Mask: 0x01)                          */
32432  #define R_GPT7_GTCSR_CSELCB_Pos         (17UL)         /*!< CSELCB (Bit 17)                                       */
32433  #define R_GPT7_GTCSR_CSELCB_Msk         (0x20000UL)    /*!< CSELCB (Bitfield-Mask: 0x01)                          */
32434  #define R_GPT7_GTCSR_CSELCC_Pos         (18UL)         /*!< CSELCC (Bit 18)                                       */
32435  #define R_GPT7_GTCSR_CSELCC_Msk         (0x40000UL)    /*!< CSELCC (Bitfield-Mask: 0x01)                          */
32436  #define R_GPT7_GTCSR_CSELCD_Pos         (19UL)         /*!< CSELCD (Bit 19)                                       */
32437  #define R_GPT7_GTCSR_CSELCD_Msk         (0x80000UL)    /*!< CSELCD (Bitfield-Mask: 0x01)                          */
32438  #define R_GPT7_GTCSR_CSELCE_Pos         (20UL)         /*!< CSELCE (Bit 20)                                       */
32439  #define R_GPT7_GTCSR_CSELCE_Msk         (0x100000UL)   /*!< CSELCE (Bitfield-Mask: 0x01)                          */
32440  #define R_GPT7_GTCSR_CSELCF_Pos         (21UL)         /*!< CSELCF (Bit 21)                                       */
32441  #define R_GPT7_GTCSR_CSELCF_Msk         (0x200000UL)   /*!< CSELCF (Bitfield-Mask: 0x01)                          */
32442  #define R_GPT7_GTCSR_CSELCG_Pos         (22UL)         /*!< CSELCG (Bit 22)                                       */
32443  #define R_GPT7_GTCSR_CSELCG_Msk         (0x400000UL)   /*!< CSELCG (Bitfield-Mask: 0x01)                          */
32444  #define R_GPT7_GTCSR_CSELCH_Pos         (23UL)         /*!< CSELCH (Bit 23)                                       */
32445  #define R_GPT7_GTCSR_CSELCH_Msk         (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
32446  #define R_GPT7_GTCSR_CCLR_Pos           (31UL)         /*!< CCLR (Bit 31)                                         */
32447  #define R_GPT7_GTCSR_CCLR_Msk           (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01)                            */
32448 /* ========================================================  GTUPSR  ========================================================= */
32449  #define R_GPT7_GTUPSR_USGTRGAFR_Pos     (0UL)          /*!< USGTRGAFR (Bit 0)                                     */
32450  #define R_GPT7_GTUPSR_USGTRGAFR_Msk     (0x3UL)        /*!< USGTRGAFR (Bitfield-Mask: 0x03)                       */
32451  #define R_GPT7_GTUPSR_USGTRGBFR_Pos     (2UL)          /*!< USGTRGBFR (Bit 2)                                     */
32452  #define R_GPT7_GTUPSR_USGTRGBFR_Msk     (0xcUL)        /*!< USGTRGBFR (Bitfield-Mask: 0x03)                       */
32453  #define R_GPT7_GTUPSR_USGTRGCFR_Pos     (4UL)          /*!< USGTRGCFR (Bit 4)                                     */
32454  #define R_GPT7_GTUPSR_USGTRGCFR_Msk     (0x30UL)       /*!< USGTRGCFR (Bitfield-Mask: 0x03)                       */
32455  #define R_GPT7_GTUPSR_USGTRGDFR_Pos     (6UL)          /*!< USGTRGDFR (Bit 6)                                     */
32456  #define R_GPT7_GTUPSR_USGTRGDFR_Msk     (0xc0UL)       /*!< USGTRGDFR (Bitfield-Mask: 0x03)                       */
32457  #define R_GPT7_GTUPSR_USCARBHL_Pos      (8UL)          /*!< USCARBHL (Bit 8)                                      */
32458  #define R_GPT7_GTUPSR_USCARBHL_Msk      (0x300UL)      /*!< USCARBHL (Bitfield-Mask: 0x03)                        */
32459  #define R_GPT7_GTUPSR_USCAFBHL_Pos      (10UL)         /*!< USCAFBHL (Bit 10)                                     */
32460  #define R_GPT7_GTUPSR_USCAFBHL_Msk      (0xc00UL)      /*!< USCAFBHL (Bitfield-Mask: 0x03)                        */
32461  #define R_GPT7_GTUPSR_USCBRAHL_Pos      (12UL)         /*!< USCBRAHL (Bit 12)                                     */
32462  #define R_GPT7_GTUPSR_USCBRAHL_Msk      (0x3000UL)     /*!< USCBRAHL (Bitfield-Mask: 0x03)                        */
32463  #define R_GPT7_GTUPSR_USCBFAHL_Pos      (14UL)         /*!< USCBFAHL (Bit 14)                                     */
32464  #define R_GPT7_GTUPSR_USCBFAHL_Msk      (0xc000UL)     /*!< USCBFAHL (Bitfield-Mask: 0x03)                        */
32465  #define R_GPT7_GTUPSR_USELCA_Pos        (16UL)         /*!< USELCA (Bit 16)                                       */
32466  #define R_GPT7_GTUPSR_USELCA_Msk        (0x10000UL)    /*!< USELCA (Bitfield-Mask: 0x01)                          */
32467  #define R_GPT7_GTUPSR_USELCB_Pos        (17UL)         /*!< USELCB (Bit 17)                                       */
32468  #define R_GPT7_GTUPSR_USELCB_Msk        (0x20000UL)    /*!< USELCB (Bitfield-Mask: 0x01)                          */
32469  #define R_GPT7_GTUPSR_USELCC_Pos        (18UL)         /*!< USELCC (Bit 18)                                       */
32470  #define R_GPT7_GTUPSR_USELCC_Msk        (0x40000UL)    /*!< USELCC (Bitfield-Mask: 0x01)                          */
32471  #define R_GPT7_GTUPSR_USELCD_Pos        (19UL)         /*!< USELCD (Bit 19)                                       */
32472  #define R_GPT7_GTUPSR_USELCD_Msk        (0x80000UL)    /*!< USELCD (Bitfield-Mask: 0x01)                          */
32473  #define R_GPT7_GTUPSR_USELCE_Pos        (20UL)         /*!< USELCE (Bit 20)                                       */
32474  #define R_GPT7_GTUPSR_USELCE_Msk        (0x100000UL)   /*!< USELCE (Bitfield-Mask: 0x01)                          */
32475  #define R_GPT7_GTUPSR_USELCF_Pos        (21UL)         /*!< USELCF (Bit 21)                                       */
32476  #define R_GPT7_GTUPSR_USELCF_Msk        (0x200000UL)   /*!< USELCF (Bitfield-Mask: 0x01)                          */
32477  #define R_GPT7_GTUPSR_USELCG_Pos        (22UL)         /*!< USELCG (Bit 22)                                       */
32478  #define R_GPT7_GTUPSR_USELCG_Msk        (0x400000UL)   /*!< USELCG (Bitfield-Mask: 0x01)                          */
32479  #define R_GPT7_GTUPSR_USELCH_Pos        (23UL)         /*!< USELCH (Bit 23)                                       */
32480  #define R_GPT7_GTUPSR_USELCH_Msk        (0x800000UL)   /*!< USELCH (Bitfield-Mask: 0x01)                          */
32481 /* ========================================================  GTDNSR  ========================================================= */
32482  #define R_GPT7_GTDNSR_DSGTRGAFR_Pos     (0UL)          /*!< DSGTRGAFR (Bit 0)                                     */
32483  #define R_GPT7_GTDNSR_DSGTRGAFR_Msk     (0x3UL)        /*!< DSGTRGAFR (Bitfield-Mask: 0x03)                       */
32484  #define R_GPT7_GTDNSR_DSGTRGBFR_Pos     (2UL)          /*!< DSGTRGBFR (Bit 2)                                     */
32485  #define R_GPT7_GTDNSR_DSGTRGBFR_Msk     (0xcUL)        /*!< DSGTRGBFR (Bitfield-Mask: 0x03)                       */
32486  #define R_GPT7_GTDNSR_DSGTRGCFR_Pos     (4UL)          /*!< DSGTRGCFR (Bit 4)                                     */
32487  #define R_GPT7_GTDNSR_DSGTRGCFR_Msk     (0x30UL)       /*!< DSGTRGCFR (Bitfield-Mask: 0x03)                       */
32488  #define R_GPT7_GTDNSR_DSGTRGDFR_Pos     (6UL)          /*!< DSGTRGDFR (Bit 6)                                     */
32489  #define R_GPT7_GTDNSR_DSGTRGDFR_Msk     (0xc0UL)       /*!< DSGTRGDFR (Bitfield-Mask: 0x03)                       */
32490  #define R_GPT7_GTDNSR_DSCARBHL_Pos      (8UL)          /*!< DSCARBHL (Bit 8)                                      */
32491  #define R_GPT7_GTDNSR_DSCARBHL_Msk      (0x300UL)      /*!< DSCARBHL (Bitfield-Mask: 0x03)                        */
32492  #define R_GPT7_GTDNSR_DSCAFBHL_Pos      (10UL)         /*!< DSCAFBHL (Bit 10)                                     */
32493  #define R_GPT7_GTDNSR_DSCAFBHL_Msk      (0xc00UL)      /*!< DSCAFBHL (Bitfield-Mask: 0x03)                        */
32494  #define R_GPT7_GTDNSR_DSCBRAHL_Pos      (12UL)         /*!< DSCBRAHL (Bit 12)                                     */
32495  #define R_GPT7_GTDNSR_DSCBRAHL_Msk      (0x3000UL)     /*!< DSCBRAHL (Bitfield-Mask: 0x03)                        */
32496  #define R_GPT7_GTDNSR_DSCBFAHL_Pos      (14UL)         /*!< DSCBFAHL (Bit 14)                                     */
32497  #define R_GPT7_GTDNSR_DSCBFAHL_Msk      (0xc000UL)     /*!< DSCBFAHL (Bitfield-Mask: 0x03)                        */
32498  #define R_GPT7_GTDNSR_DSELCA_Pos        (16UL)         /*!< DSELCA (Bit 16)                                       */
32499  #define R_GPT7_GTDNSR_DSELCA_Msk        (0x10000UL)    /*!< DSELCA (Bitfield-Mask: 0x01)                          */
32500  #define R_GPT7_GTDNSR_DSELCB_Pos        (17UL)         /*!< DSELCB (Bit 17)                                       */
32501  #define R_GPT7_GTDNSR_DSELCB_Msk        (0x20000UL)    /*!< DSELCB (Bitfield-Mask: 0x01)                          */
32502  #define R_GPT7_GTDNSR_DSELCC_Pos        (18UL)         /*!< DSELCC (Bit 18)                                       */
32503  #define R_GPT7_GTDNSR_DSELCC_Msk        (0x40000UL)    /*!< DSELCC (Bitfield-Mask: 0x01)                          */
32504  #define R_GPT7_GTDNSR_DSELCD_Pos        (19UL)         /*!< DSELCD (Bit 19)                                       */
32505  #define R_GPT7_GTDNSR_DSELCD_Msk        (0x80000UL)    /*!< DSELCD (Bitfield-Mask: 0x01)                          */
32506  #define R_GPT7_GTDNSR_DSELCE_Pos        (20UL)         /*!< DSELCE (Bit 20)                                       */
32507  #define R_GPT7_GTDNSR_DSELCE_Msk        (0x100000UL)   /*!< DSELCE (Bitfield-Mask: 0x01)                          */
32508  #define R_GPT7_GTDNSR_DSELCF_Pos        (21UL)         /*!< DSELCF (Bit 21)                                       */
32509  #define R_GPT7_GTDNSR_DSELCF_Msk        (0x200000UL)   /*!< DSELCF (Bitfield-Mask: 0x01)                          */
32510  #define R_GPT7_GTDNSR_DSELCG_Pos        (22UL)         /*!< DSELCG (Bit 22)                                       */
32511  #define R_GPT7_GTDNSR_DSELCG_Msk        (0x400000UL)   /*!< DSELCG (Bitfield-Mask: 0x01)                          */
32512  #define R_GPT7_GTDNSR_DSELCH_Pos        (23UL)         /*!< DSELCH (Bit 23)                                       */
32513  #define R_GPT7_GTDNSR_DSELCH_Msk        (0x800000UL)   /*!< DSELCH (Bitfield-Mask: 0x01)                          */
32514 /* ========================================================  GTICASR  ======================================================== */
32515  #define R_GPT7_GTICASR_ASGTRGAFR_Pos    (0UL)          /*!< ASGTRGAFR (Bit 0)                                     */
32516  #define R_GPT7_GTICASR_ASGTRGAFR_Msk    (0x3UL)        /*!< ASGTRGAFR (Bitfield-Mask: 0x03)                       */
32517  #define R_GPT7_GTICASR_ASGTRGBFR_Pos    (2UL)          /*!< ASGTRGBFR (Bit 2)                                     */
32518  #define R_GPT7_GTICASR_ASGTRGBFR_Msk    (0xcUL)        /*!< ASGTRGBFR (Bitfield-Mask: 0x03)                       */
32519  #define R_GPT7_GTICASR_ASGTRGCFR_Pos    (4UL)          /*!< ASGTRGCFR (Bit 4)                                     */
32520  #define R_GPT7_GTICASR_ASGTRGCFR_Msk    (0x30UL)       /*!< ASGTRGCFR (Bitfield-Mask: 0x03)                       */
32521  #define R_GPT7_GTICASR_ASGTRGDFR_Pos    (6UL)          /*!< ASGTRGDFR (Bit 6)                                     */
32522  #define R_GPT7_GTICASR_ASGTRGDFR_Msk    (0xc0UL)       /*!< ASGTRGDFR (Bitfield-Mask: 0x03)                       */
32523  #define R_GPT7_GTICASR_ASCARBHL_Pos     (8UL)          /*!< ASCARBHL (Bit 8)                                      */
32524  #define R_GPT7_GTICASR_ASCARBHL_Msk     (0x300UL)      /*!< ASCARBHL (Bitfield-Mask: 0x03)                        */
32525  #define R_GPT7_GTICASR_ASCAFBHL_Pos     (10UL)         /*!< ASCAFBHL (Bit 10)                                     */
32526  #define R_GPT7_GTICASR_ASCAFBHL_Msk     (0xc00UL)      /*!< ASCAFBHL (Bitfield-Mask: 0x03)                        */
32527  #define R_GPT7_GTICASR_ASCBRAHL_Pos     (12UL)         /*!< ASCBRAHL (Bit 12)                                     */
32528  #define R_GPT7_GTICASR_ASCBRAHL_Msk     (0x3000UL)     /*!< ASCBRAHL (Bitfield-Mask: 0x03)                        */
32529  #define R_GPT7_GTICASR_ASCBFAHL_Pos     (14UL)         /*!< ASCBFAHL (Bit 14)                                     */
32530  #define R_GPT7_GTICASR_ASCBFAHL_Msk     (0xc000UL)     /*!< ASCBFAHL (Bitfield-Mask: 0x03)                        */
32531  #define R_GPT7_GTICASR_ASELCA_Pos       (16UL)         /*!< ASELCA (Bit 16)                                       */
32532  #define R_GPT7_GTICASR_ASELCA_Msk       (0x10000UL)    /*!< ASELCA (Bitfield-Mask: 0x01)                          */
32533  #define R_GPT7_GTICASR_ASELCB_Pos       (17UL)         /*!< ASELCB (Bit 17)                                       */
32534  #define R_GPT7_GTICASR_ASELCB_Msk       (0x20000UL)    /*!< ASELCB (Bitfield-Mask: 0x01)                          */
32535  #define R_GPT7_GTICASR_ASELCC_Pos       (18UL)         /*!< ASELCC (Bit 18)                                       */
32536  #define R_GPT7_GTICASR_ASELCC_Msk       (0x40000UL)    /*!< ASELCC (Bitfield-Mask: 0x01)                          */
32537  #define R_GPT7_GTICASR_ASELCD_Pos       (19UL)         /*!< ASELCD (Bit 19)                                       */
32538  #define R_GPT7_GTICASR_ASELCD_Msk       (0x80000UL)    /*!< ASELCD (Bitfield-Mask: 0x01)                          */
32539  #define R_GPT7_GTICASR_ASELCE_Pos       (20UL)         /*!< ASELCE (Bit 20)                                       */
32540  #define R_GPT7_GTICASR_ASELCE_Msk       (0x100000UL)   /*!< ASELCE (Bitfield-Mask: 0x01)                          */
32541  #define R_GPT7_GTICASR_ASELCF_Pos       (21UL)         /*!< ASELCF (Bit 21)                                       */
32542  #define R_GPT7_GTICASR_ASELCF_Msk       (0x200000UL)   /*!< ASELCF (Bitfield-Mask: 0x01)                          */
32543  #define R_GPT7_GTICASR_ASELCG_Pos       (22UL)         /*!< ASELCG (Bit 22)                                       */
32544  #define R_GPT7_GTICASR_ASELCG_Msk       (0x400000UL)   /*!< ASELCG (Bitfield-Mask: 0x01)                          */
32545  #define R_GPT7_GTICASR_ASELCH_Pos       (23UL)         /*!< ASELCH (Bit 23)                                       */
32546  #define R_GPT7_GTICASR_ASELCH_Msk       (0x800000UL)   /*!< ASELCH (Bitfield-Mask: 0x01)                          */
32547 /* ========================================================  GTICBSR  ======================================================== */
32548  #define R_GPT7_GTICBSR_BSGTRGAFR_Pos    (0UL)          /*!< BSGTRGAFR (Bit 0)                                     */
32549  #define R_GPT7_GTICBSR_BSGTRGAFR_Msk    (0x3UL)        /*!< BSGTRGAFR (Bitfield-Mask: 0x03)                       */
32550  #define R_GPT7_GTICBSR_BSGTRGBFR_Pos    (2UL)          /*!< BSGTRGBFR (Bit 2)                                     */
32551  #define R_GPT7_GTICBSR_BSGTRGBFR_Msk    (0xcUL)        /*!< BSGTRGBFR (Bitfield-Mask: 0x03)                       */
32552  #define R_GPT7_GTICBSR_BSGTRGCFR_Pos    (4UL)          /*!< BSGTRGCFR (Bit 4)                                     */
32553  #define R_GPT7_GTICBSR_BSGTRGCFR_Msk    (0x30UL)       /*!< BSGTRGCFR (Bitfield-Mask: 0x03)                       */
32554  #define R_GPT7_GTICBSR_BSGTRGDFR_Pos    (6UL)          /*!< BSGTRGDFR (Bit 6)                                     */
32555  #define R_GPT7_GTICBSR_BSGTRGDFR_Msk    (0xc0UL)       /*!< BSGTRGDFR (Bitfield-Mask: 0x03)                       */
32556  #define R_GPT7_GTICBSR_BSCARBHL_Pos     (8UL)          /*!< BSCARBHL (Bit 8)                                      */
32557  #define R_GPT7_GTICBSR_BSCARBHL_Msk     (0x300UL)      /*!< BSCARBHL (Bitfield-Mask: 0x03)                        */
32558  #define R_GPT7_GTICBSR_BSCAFBHL_Pos     (10UL)         /*!< BSCAFBHL (Bit 10)                                     */
32559  #define R_GPT7_GTICBSR_BSCAFBHL_Msk     (0xc00UL)      /*!< BSCAFBHL (Bitfield-Mask: 0x03)                        */
32560  #define R_GPT7_GTICBSR_BSCBRAHL_Pos     (12UL)         /*!< BSCBRAHL (Bit 12)                                     */
32561  #define R_GPT7_GTICBSR_BSCBRAHL_Msk     (0x3000UL)     /*!< BSCBRAHL (Bitfield-Mask: 0x03)                        */
32562  #define R_GPT7_GTICBSR_BSCBFAHL_Pos     (14UL)         /*!< BSCBFAHL (Bit 14)                                     */
32563  #define R_GPT7_GTICBSR_BSCBFAHL_Msk     (0xc000UL)     /*!< BSCBFAHL (Bitfield-Mask: 0x03)                        */
32564  #define R_GPT7_GTICBSR_BSELCA_Pos       (16UL)         /*!< BSELCA (Bit 16)                                       */
32565  #define R_GPT7_GTICBSR_BSELCA_Msk       (0x10000UL)    /*!< BSELCA (Bitfield-Mask: 0x01)                          */
32566  #define R_GPT7_GTICBSR_BSELCB_Pos       (17UL)         /*!< BSELCB (Bit 17)                                       */
32567  #define R_GPT7_GTICBSR_BSELCB_Msk       (0x20000UL)    /*!< BSELCB (Bitfield-Mask: 0x01)                          */
32568  #define R_GPT7_GTICBSR_BSELCC_Pos       (18UL)         /*!< BSELCC (Bit 18)                                       */
32569  #define R_GPT7_GTICBSR_BSELCC_Msk       (0x40000UL)    /*!< BSELCC (Bitfield-Mask: 0x01)                          */
32570  #define R_GPT7_GTICBSR_BSELCD_Pos       (19UL)         /*!< BSELCD (Bit 19)                                       */
32571  #define R_GPT7_GTICBSR_BSELCD_Msk       (0x80000UL)    /*!< BSELCD (Bitfield-Mask: 0x01)                          */
32572  #define R_GPT7_GTICBSR_BSELCE_Pos       (20UL)         /*!< BSELCE (Bit 20)                                       */
32573  #define R_GPT7_GTICBSR_BSELCE_Msk       (0x100000UL)   /*!< BSELCE (Bitfield-Mask: 0x01)                          */
32574  #define R_GPT7_GTICBSR_BSELCF_Pos       (21UL)         /*!< BSELCF (Bit 21)                                       */
32575  #define R_GPT7_GTICBSR_BSELCF_Msk       (0x200000UL)   /*!< BSELCF (Bitfield-Mask: 0x01)                          */
32576  #define R_GPT7_GTICBSR_BSELCG_Pos       (22UL)         /*!< BSELCG (Bit 22)                                       */
32577  #define R_GPT7_GTICBSR_BSELCG_Msk       (0x400000UL)   /*!< BSELCG (Bitfield-Mask: 0x01)                          */
32578  #define R_GPT7_GTICBSR_BSELCH_Pos       (23UL)         /*!< BSELCH (Bit 23)                                       */
32579  #define R_GPT7_GTICBSR_BSELCH_Msk       (0x800000UL)   /*!< BSELCH (Bitfield-Mask: 0x01)                          */
32580 /* =========================================================  GTCR  ========================================================== */
32581  #define R_GPT7_GTCR_CST_Pos             (0UL)          /*!< CST (Bit 0)                                           */
32582  #define R_GPT7_GTCR_CST_Msk             (0x1UL)        /*!< CST (Bitfield-Mask: 0x01)                             */
32583  #define R_GPT7_GTCR_ICDS_Pos            (8UL)          /*!< ICDS (Bit 8)                                          */
32584  #define R_GPT7_GTCR_ICDS_Msk            (0x100UL)      /*!< ICDS (Bitfield-Mask: 0x01)                            */
32585  #define R_GPT7_GTCR_MD_Pos              (16UL)         /*!< MD (Bit 16)                                           */
32586  #define R_GPT7_GTCR_MD_Msk              (0x70000UL)    /*!< MD (Bitfield-Mask: 0x07)                              */
32587  #define R_GPT7_GTCR_TPCS_Pos            (23UL)         /*!< TPCS (Bit 23)                                         */
32588  #define R_GPT7_GTCR_TPCS_Msk            (0x7800000UL)  /*!< TPCS (Bitfield-Mask: 0x0f)                            */
32589  #define R_GPT7_GTCR_SWMD_Pos            (29UL)         /*!< SWMD (Bit 29)                                         */
32590  #define R_GPT7_GTCR_SWMD_Msk            (0xe0000000UL) /*!< SWMD (Bitfield-Mask: 0x07)                            */
32591 /* =======================================================  GTUDDTYC  ======================================================== */
32592  #define R_GPT7_GTUDDTYC_UD_Pos          (0UL)          /*!< UD (Bit 0)                                            */
32593  #define R_GPT7_GTUDDTYC_UD_Msk          (0x1UL)        /*!< UD (Bitfield-Mask: 0x01)                              */
32594  #define R_GPT7_GTUDDTYC_UDF_Pos         (1UL)          /*!< UDF (Bit 1)                                           */
32595  #define R_GPT7_GTUDDTYC_UDF_Msk         (0x2UL)        /*!< UDF (Bitfield-Mask: 0x01)                             */
32596  #define R_GPT7_GTUDDTYC_OADTY_Pos       (16UL)         /*!< OADTY (Bit 16)                                        */
32597  #define R_GPT7_GTUDDTYC_OADTY_Msk       (0x30000UL)    /*!< OADTY (Bitfield-Mask: 0x03)                           */
32598  #define R_GPT7_GTUDDTYC_OADTYF_Pos      (18UL)         /*!< OADTYF (Bit 18)                                       */
32599  #define R_GPT7_GTUDDTYC_OADTYF_Msk      (0x40000UL)    /*!< OADTYF (Bitfield-Mask: 0x01)                          */
32600  #define R_GPT7_GTUDDTYC_OADTYR_Pos      (19UL)         /*!< OADTYR (Bit 19)                                       */
32601  #define R_GPT7_GTUDDTYC_OADTYR_Msk      (0x80000UL)    /*!< OADTYR (Bitfield-Mask: 0x01)                          */
32602  #define R_GPT7_GTUDDTYC_OBDTY_Pos       (24UL)         /*!< OBDTY (Bit 24)                                        */
32603  #define R_GPT7_GTUDDTYC_OBDTY_Msk       (0x3000000UL)  /*!< OBDTY (Bitfield-Mask: 0x03)                           */
32604  #define R_GPT7_GTUDDTYC_OBDTYF_Pos      (26UL)         /*!< OBDTYF (Bit 26)                                       */
32605  #define R_GPT7_GTUDDTYC_OBDTYF_Msk      (0x4000000UL)  /*!< OBDTYF (Bitfield-Mask: 0x01)                          */
32606  #define R_GPT7_GTUDDTYC_OBDTYR_Pos      (27UL)         /*!< OBDTYR (Bit 27)                                       */
32607  #define R_GPT7_GTUDDTYC_OBDTYR_Msk      (0x8000000UL)  /*!< OBDTYR (Bitfield-Mask: 0x01)                          */
32608 /* =========================================================  GTIOR  ========================================================= */
32609  #define R_GPT7_GTIOR_GTIOA_Pos          (0UL)          /*!< GTIOA (Bit 0)                                         */
32610  #define R_GPT7_GTIOR_GTIOA_Msk          (0x1fUL)       /*!< GTIOA (Bitfield-Mask: 0x1f)                           */
32611  #define R_GPT7_GTIOR_OADFLT_Pos         (6UL)          /*!< OADFLT (Bit 6)                                        */
32612  #define R_GPT7_GTIOR_OADFLT_Msk         (0x40UL)       /*!< OADFLT (Bitfield-Mask: 0x01)                          */
32613  #define R_GPT7_GTIOR_OAHLD_Pos          (7UL)          /*!< OAHLD (Bit 7)                                         */
32614  #define R_GPT7_GTIOR_OAHLD_Msk          (0x80UL)       /*!< OAHLD (Bitfield-Mask: 0x01)                           */
32615  #define R_GPT7_GTIOR_OAE_Pos            (8UL)          /*!< OAE (Bit 8)                                           */
32616  #define R_GPT7_GTIOR_OAE_Msk            (0x100UL)      /*!< OAE (Bitfield-Mask: 0x01)                             */
32617  #define R_GPT7_GTIOR_OADF_Pos           (9UL)          /*!< OADF (Bit 9)                                          */
32618  #define R_GPT7_GTIOR_OADF_Msk           (0x600UL)      /*!< OADF (Bitfield-Mask: 0x03)                            */
32619  #define R_GPT7_GTIOR_NFAEN_Pos          (13UL)         /*!< NFAEN (Bit 13)                                        */
32620  #define R_GPT7_GTIOR_NFAEN_Msk          (0x2000UL)     /*!< NFAEN (Bitfield-Mask: 0x01)                           */
32621  #define R_GPT7_GTIOR_NFCSA_Pos          (14UL)         /*!< NFCSA (Bit 14)                                        */
32622  #define R_GPT7_GTIOR_NFCSA_Msk          (0xc000UL)     /*!< NFCSA (Bitfield-Mask: 0x03)                           */
32623  #define R_GPT7_GTIOR_GTIOB_Pos          (16UL)         /*!< GTIOB (Bit 16)                                        */
32624  #define R_GPT7_GTIOR_GTIOB_Msk          (0x1f0000UL)   /*!< GTIOB (Bitfield-Mask: 0x1f)                           */
32625  #define R_GPT7_GTIOR_OBDFLT_Pos         (22UL)         /*!< OBDFLT (Bit 22)                                       */
32626  #define R_GPT7_GTIOR_OBDFLT_Msk         (0x400000UL)   /*!< OBDFLT (Bitfield-Mask: 0x01)                          */
32627  #define R_GPT7_GTIOR_OBHLD_Pos          (23UL)         /*!< OBHLD (Bit 23)                                        */
32628  #define R_GPT7_GTIOR_OBHLD_Msk          (0x800000UL)   /*!< OBHLD (Bitfield-Mask: 0x01)                           */
32629  #define R_GPT7_GTIOR_OBE_Pos            (24UL)         /*!< OBE (Bit 24)                                          */
32630  #define R_GPT7_GTIOR_OBE_Msk            (0x1000000UL)  /*!< OBE (Bitfield-Mask: 0x01)                             */
32631  #define R_GPT7_GTIOR_OBDF_Pos           (25UL)         /*!< OBDF (Bit 25)                                         */
32632  #define R_GPT7_GTIOR_OBDF_Msk           (0x6000000UL)  /*!< OBDF (Bitfield-Mask: 0x03)                            */
32633  #define R_GPT7_GTIOR_NFBEN_Pos          (29UL)         /*!< NFBEN (Bit 29)                                        */
32634  #define R_GPT7_GTIOR_NFBEN_Msk          (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01)                           */
32635  #define R_GPT7_GTIOR_NFCSB_Pos          (30UL)         /*!< NFCSB (Bit 30)                                        */
32636  #define R_GPT7_GTIOR_NFCSB_Msk          (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03)                           */
32637 /* ========================================================  GTINTAD  ======================================================== */
32638  #define R_GPT7_GTINTAD_GTINTA_Pos       (0UL)          /*!< GTINTA (Bit 0)                                        */
32639  #define R_GPT7_GTINTAD_GTINTA_Msk       (0x1UL)        /*!< GTINTA (Bitfield-Mask: 0x01)                          */
32640  #define R_GPT7_GTINTAD_GTINTB_Pos       (1UL)          /*!< GTINTB (Bit 1)                                        */
32641  #define R_GPT7_GTINTAD_GTINTB_Msk       (0x2UL)        /*!< GTINTB (Bitfield-Mask: 0x01)                          */
32642  #define R_GPT7_GTINTAD_GTINTC_Pos       (2UL)          /*!< GTINTC (Bit 2)                                        */
32643  #define R_GPT7_GTINTAD_GTINTC_Msk       (0x4UL)        /*!< GTINTC (Bitfield-Mask: 0x01)                          */
32644  #define R_GPT7_GTINTAD_GTINTD_Pos       (3UL)          /*!< GTINTD (Bit 3)                                        */
32645  #define R_GPT7_GTINTAD_GTINTD_Msk       (0x8UL)        /*!< GTINTD (Bitfield-Mask: 0x01)                          */
32646  #define R_GPT7_GTINTAD_GTINTE_Pos       (4UL)          /*!< GTINTE (Bit 4)                                        */
32647  #define R_GPT7_GTINTAD_GTINTE_Msk       (0x10UL)       /*!< GTINTE (Bitfield-Mask: 0x01)                          */
32648  #define R_GPT7_GTINTAD_GTINTF_Pos       (5UL)          /*!< GTINTF (Bit 5)                                        */
32649  #define R_GPT7_GTINTAD_GTINTF_Msk       (0x20UL)       /*!< GTINTF (Bitfield-Mask: 0x01)                          */
32650  #define R_GPT7_GTINTAD_GTINTPR_Pos      (6UL)          /*!< GTINTPR (Bit 6)                                       */
32651  #define R_GPT7_GTINTAD_GTINTPR_Msk      (0xc0UL)       /*!< GTINTPR (Bitfield-Mask: 0x03)                         */
32652  #define R_GPT7_GTINTAD_ADTRAUEN_Pos     (16UL)         /*!< ADTRAUEN (Bit 16)                                     */
32653  #define R_GPT7_GTINTAD_ADTRAUEN_Msk     (0x10000UL)    /*!< ADTRAUEN (Bitfield-Mask: 0x01)                        */
32654  #define R_GPT7_GTINTAD_ADTRADEN_Pos     (17UL)         /*!< ADTRADEN (Bit 17)                                     */
32655  #define R_GPT7_GTINTAD_ADTRADEN_Msk     (0x20000UL)    /*!< ADTRADEN (Bitfield-Mask: 0x01)                        */
32656  #define R_GPT7_GTINTAD_ADTRBUEN_Pos     (18UL)         /*!< ADTRBUEN (Bit 18)                                     */
32657  #define R_GPT7_GTINTAD_ADTRBUEN_Msk     (0x40000UL)    /*!< ADTRBUEN (Bitfield-Mask: 0x01)                        */
32658  #define R_GPT7_GTINTAD_ADTRBDEN_Pos     (19UL)         /*!< ADTRBDEN (Bit 19)                                     */
32659  #define R_GPT7_GTINTAD_ADTRBDEN_Msk     (0x80000UL)    /*!< ADTRBDEN (Bitfield-Mask: 0x01)                        */
32660  #define R_GPT7_GTINTAD_GRP_Pos          (24UL)         /*!< GRP (Bit 24)                                          */
32661  #define R_GPT7_GTINTAD_GRP_Msk          (0x3000000UL)  /*!< GRP (Bitfield-Mask: 0x03)                             */
32662  #define R_GPT7_GTINTAD_GRPDTE_Pos       (28UL)         /*!< GRPDTE (Bit 28)                                       */
32663  #define R_GPT7_GTINTAD_GRPDTE_Msk       (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01)                          */
32664  #define R_GPT7_GTINTAD_GRPABH_Pos       (29UL)         /*!< GRPABH (Bit 29)                                       */
32665  #define R_GPT7_GTINTAD_GRPABH_Msk       (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01)                          */
32666  #define R_GPT7_GTINTAD_GRPABL_Pos       (30UL)         /*!< GRPABL (Bit 30)                                       */
32667  #define R_GPT7_GTINTAD_GRPABL_Msk       (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01)                          */
32668 /* =========================================================  GTST  ========================================================== */
32669  #define R_GPT7_GTST_ITCNT_Pos           (8UL)          /*!< ITCNT (Bit 8)                                         */
32670  #define R_GPT7_GTST_ITCNT_Msk           (0x700UL)      /*!< ITCNT (Bitfield-Mask: 0x07)                           */
32671  #define R_GPT7_GTST_TUCF_Pos            (15UL)         /*!< TUCF (Bit 15)                                         */
32672  #define R_GPT7_GTST_TUCF_Msk            (0x8000UL)     /*!< TUCF (Bitfield-Mask: 0x01)                            */
32673  #define R_GPT7_GTST_ADTRAUF_Pos         (16UL)         /*!< ADTRAUF (Bit 16)                                      */
32674  #define R_GPT7_GTST_ADTRAUF_Msk         (0x10000UL)    /*!< ADTRAUF (Bitfield-Mask: 0x01)                         */
32675  #define R_GPT7_GTST_ADTRADF_Pos         (17UL)         /*!< ADTRADF (Bit 17)                                      */
32676  #define R_GPT7_GTST_ADTRADF_Msk         (0x20000UL)    /*!< ADTRADF (Bitfield-Mask: 0x01)                         */
32677  #define R_GPT7_GTST_ADTRBUF_Pos         (18UL)         /*!< ADTRBUF (Bit 18)                                      */
32678  #define R_GPT7_GTST_ADTRBUF_Msk         (0x40000UL)    /*!< ADTRBUF (Bitfield-Mask: 0x01)                         */
32679  #define R_GPT7_GTST_ADTRBDF_Pos         (19UL)         /*!< ADTRBDF (Bit 19)                                      */
32680  #define R_GPT7_GTST_ADTRBDF_Msk         (0x80000UL)    /*!< ADTRBDF (Bitfield-Mask: 0x01)                         */
32681  #define R_GPT7_GTST_ODF_Pos             (24UL)         /*!< ODF (Bit 24)                                          */
32682  #define R_GPT7_GTST_ODF_Msk             (0x1000000UL)  /*!< ODF (Bitfield-Mask: 0x01)                             */
32683  #define R_GPT7_GTST_DTEF_Pos            (28UL)         /*!< DTEF (Bit 28)                                         */
32684  #define R_GPT7_GTST_DTEF_Msk            (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01)                            */
32685  #define R_GPT7_GTST_OABHF_Pos           (29UL)         /*!< OABHF (Bit 29)                                        */
32686  #define R_GPT7_GTST_OABHF_Msk           (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01)                           */
32687  #define R_GPT7_GTST_OABLF_Pos           (30UL)         /*!< OABLF (Bit 30)                                        */
32688  #define R_GPT7_GTST_OABLF_Msk           (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01)                           */
32689 /* =========================================================  GTBER  ========================================================= */
32690  #define R_GPT7_GTBER_BD0_Pos            (0UL)          /*!< BD0 (Bit 0)                                           */
32691  #define R_GPT7_GTBER_BD0_Msk            (0x1UL)        /*!< BD0 (Bitfield-Mask: 0x01)                             */
32692  #define R_GPT7_GTBER_BD1_Pos            (1UL)          /*!< BD1 (Bit 1)                                           */
32693  #define R_GPT7_GTBER_BD1_Msk            (0x2UL)        /*!< BD1 (Bitfield-Mask: 0x01)                             */
32694  #define R_GPT7_GTBER_BD2_Pos            (2UL)          /*!< BD2 (Bit 2)                                           */
32695  #define R_GPT7_GTBER_BD2_Msk            (0x4UL)        /*!< BD2 (Bitfield-Mask: 0x01)                             */
32696  #define R_GPT7_GTBER_BD3_Pos            (3UL)          /*!< BD3 (Bit 3)                                           */
32697  #define R_GPT7_GTBER_BD3_Msk            (0x8UL)        /*!< BD3 (Bitfield-Mask: 0x01)                             */
32698  #define R_GPT7_GTBER_DBRTECA_Pos        (8UL)          /*!< DBRTECA (Bit 8)                                       */
32699  #define R_GPT7_GTBER_DBRTECA_Msk        (0x100UL)      /*!< DBRTECA (Bitfield-Mask: 0x01)                         */
32700  #define R_GPT7_GTBER_DBRTECB_Pos        (10UL)         /*!< DBRTECB (Bit 10)                                      */
32701  #define R_GPT7_GTBER_DBRTECB_Msk        (0x400UL)      /*!< DBRTECB (Bitfield-Mask: 0x01)                         */
32702  #define R_GPT7_GTBER_CCRA_Pos           (16UL)         /*!< CCRA (Bit 16)                                         */
32703  #define R_GPT7_GTBER_CCRA_Msk           (0x30000UL)    /*!< CCRA (Bitfield-Mask: 0x03)                            */
32704  #define R_GPT7_GTBER_CCRB_Pos           (18UL)         /*!< CCRB (Bit 18)                                         */
32705  #define R_GPT7_GTBER_CCRB_Msk           (0xc0000UL)    /*!< CCRB (Bitfield-Mask: 0x03)                            */
32706  #define R_GPT7_GTBER_PR_Pos             (20UL)         /*!< PR (Bit 20)                                           */
32707  #define R_GPT7_GTBER_PR_Msk             (0x300000UL)   /*!< PR (Bitfield-Mask: 0x03)                              */
32708  #define R_GPT7_GTBER_CCRSWT_Pos         (22UL)         /*!< CCRSWT (Bit 22)                                       */
32709  #define R_GPT7_GTBER_CCRSWT_Msk         (0x400000UL)   /*!< CCRSWT (Bitfield-Mask: 0x01)                          */
32710  #define R_GPT7_GTBER_ADTTA_Pos          (24UL)         /*!< ADTTA (Bit 24)                                        */
32711  #define R_GPT7_GTBER_ADTTA_Msk          (0x3000000UL)  /*!< ADTTA (Bitfield-Mask: 0x03)                           */
32712  #define R_GPT7_GTBER_ADTDA_Pos          (26UL)         /*!< ADTDA (Bit 26)                                        */
32713  #define R_GPT7_GTBER_ADTDA_Msk          (0x4000000UL)  /*!< ADTDA (Bitfield-Mask: 0x01)                           */
32714  #define R_GPT7_GTBER_ADTTB_Pos          (28UL)         /*!< ADTTB (Bit 28)                                        */
32715  #define R_GPT7_GTBER_ADTTB_Msk          (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03)                           */
32716  #define R_GPT7_GTBER_ADTDB_Pos          (30UL)         /*!< ADTDB (Bit 30)                                        */
32717  #define R_GPT7_GTBER_ADTDB_Msk          (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01)                           */
32718 /* =========================================================  GTITC  ========================================================= */
32719  #define R_GPT7_GTITC_ITLA_Pos           (0UL)          /*!< ITLA (Bit 0)                                          */
32720  #define R_GPT7_GTITC_ITLA_Msk           (0x1UL)        /*!< ITLA (Bitfield-Mask: 0x01)                            */
32721  #define R_GPT7_GTITC_ITLB_Pos           (1UL)          /*!< ITLB (Bit 1)                                          */
32722  #define R_GPT7_GTITC_ITLB_Msk           (0x2UL)        /*!< ITLB (Bitfield-Mask: 0x01)                            */
32723  #define R_GPT7_GTITC_ITLC_Pos           (2UL)          /*!< ITLC (Bit 2)                                          */
32724  #define R_GPT7_GTITC_ITLC_Msk           (0x4UL)        /*!< ITLC (Bitfield-Mask: 0x01)                            */
32725  #define R_GPT7_GTITC_ITLD_Pos           (3UL)          /*!< ITLD (Bit 3)                                          */
32726  #define R_GPT7_GTITC_ITLD_Msk           (0x8UL)        /*!< ITLD (Bitfield-Mask: 0x01)                            */
32727  #define R_GPT7_GTITC_ITLE_Pos           (4UL)          /*!< ITLE (Bit 4)                                          */
32728  #define R_GPT7_GTITC_ITLE_Msk           (0x10UL)       /*!< ITLE (Bitfield-Mask: 0x01)                            */
32729  #define R_GPT7_GTITC_ITLF_Pos           (5UL)          /*!< ITLF (Bit 5)                                          */
32730  #define R_GPT7_GTITC_ITLF_Msk           (0x20UL)       /*!< ITLF (Bitfield-Mask: 0x01)                            */
32731  #define R_GPT7_GTITC_IVTC_Pos           (6UL)          /*!< IVTC (Bit 6)                                          */
32732  #define R_GPT7_GTITC_IVTC_Msk           (0xc0UL)       /*!< IVTC (Bitfield-Mask: 0x03)                            */
32733  #define R_GPT7_GTITC_IVTT_Pos           (8UL)          /*!< IVTT (Bit 8)                                          */
32734  #define R_GPT7_GTITC_IVTT_Msk           (0x700UL)      /*!< IVTT (Bitfield-Mask: 0x07)                            */
32735  #define R_GPT7_GTITC_ADTAL_Pos          (12UL)         /*!< ADTAL (Bit 12)                                        */
32736  #define R_GPT7_GTITC_ADTAL_Msk          (0x1000UL)     /*!< ADTAL (Bitfield-Mask: 0x01)                           */
32737  #define R_GPT7_GTITC_ADTBL_Pos          (14UL)         /*!< ADTBL (Bit 14)                                        */
32738  #define R_GPT7_GTITC_ADTBL_Msk          (0x4000UL)     /*!< ADTBL (Bitfield-Mask: 0x01)                           */
32739 /* =========================================================  GTCNT  ========================================================= */
32740 /* =========================================================  GTCCR  ========================================================= */
32741 /* =========================================================  GTPR  ========================================================== */
32742 /* =========================================================  GTPBR  ========================================================= */
32743 /* ========================================================  GTPDBR  ========================================================= */
32744 /* ========================================================  GTADTRA  ======================================================== */
32745 /* =======================================================  GTADTBRA  ======================================================== */
32746 /* =======================================================  GTADTDBRA  ======================================================= */
32747 /* ========================================================  GTADTRB  ======================================================== */
32748 /* =======================================================  GTADTBRB  ======================================================== */
32749 /* =======================================================  GTADTDBRB  ======================================================= */
32750 /* ========================================================  GTDTCR  ========================================================= */
32751  #define R_GPT7_GTDTCR_TDE_Pos      (0UL)     /*!< TDE (Bit 0)                                           */
32752  #define R_GPT7_GTDTCR_TDE_Msk      (0x1UL)   /*!< TDE (Bitfield-Mask: 0x01)                             */
32753  #define R_GPT7_GTDTCR_TDBUE_Pos    (4UL)     /*!< TDBUE (Bit 4)                                         */
32754  #define R_GPT7_GTDTCR_TDBUE_Msk    (0x10UL)  /*!< TDBUE (Bitfield-Mask: 0x01)                           */
32755  #define R_GPT7_GTDTCR_TDBDE_Pos    (5UL)     /*!< TDBDE (Bit 5)                                         */
32756  #define R_GPT7_GTDTCR_TDBDE_Msk    (0x20UL)  /*!< TDBDE (Bitfield-Mask: 0x01)                           */
32757  #define R_GPT7_GTDTCR_TDFER_Pos    (8UL)     /*!< TDFER (Bit 8)                                         */
32758  #define R_GPT7_GTDTCR_TDFER_Msk    (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01)                           */
32759 /* =========================================================  GTDVU  ========================================================= */
32760 /* =========================================================  GTDVD  ========================================================= */
32761 /* =========================================================  GTDBU  ========================================================= */
32762 /* =========================================================  GTDBD  ========================================================= */
32763 /* =========================================================  GTSOS  ========================================================= */
32764  #define R_GPT7_GTSOS_SOS_Pos           (0UL)          /*!< SOS (Bit 0)                                           */
32765  #define R_GPT7_GTSOS_SOS_Msk           (0x3UL)        /*!< SOS (Bitfield-Mask: 0x03)                             */
32766 /* ========================================================  GTSOTR  ========================================================= */
32767  #define R_GPT7_GTSOTR_SOTR_Pos         (0UL)          /*!< SOTR (Bit 0)                                          */
32768  #define R_GPT7_GTSOTR_SOTR_Msk         (0x1UL)        /*!< SOTR (Bitfield-Mask: 0x01)                            */
32769 /* ========================================================  GTADSMR  ======================================================== */
32770  #define R_GPT7_GTADSMR_ADSMS0_Pos      (0UL)          /*!< ADSMS0 (Bit 0)                                        */
32771  #define R_GPT7_GTADSMR_ADSMS0_Msk      (0x3UL)        /*!< ADSMS0 (Bitfield-Mask: 0x03)                          */
32772  #define R_GPT7_GTADSMR_ADSMEN0_Pos     (8UL)          /*!< ADSMEN0 (Bit 8)                                       */
32773  #define R_GPT7_GTADSMR_ADSMEN0_Msk     (0x100UL)      /*!< ADSMEN0 (Bitfield-Mask: 0x01)                         */
32774  #define R_GPT7_GTADSMR_ADSMS1_Pos      (16UL)         /*!< ADSMS1 (Bit 16)                                       */
32775  #define R_GPT7_GTADSMR_ADSMS1_Msk      (0x30000UL)    /*!< ADSMS1 (Bitfield-Mask: 0x03)                          */
32776  #define R_GPT7_GTADSMR_ADSMEN1_Pos     (24UL)         /*!< ADSMEN1 (Bit 24)                                      */
32777  #define R_GPT7_GTADSMR_ADSMEN1_Msk     (0x1000000UL)  /*!< ADSMEN1 (Bitfield-Mask: 0x01)                         */
32778 /* ========================================================  GTEITC  ========================================================= */
32779  #define R_GPT7_GTEITC_EIVTC1_Pos       (0UL)          /*!< EIVTC1 (Bit 0)                                        */
32780  #define R_GPT7_GTEITC_EIVTC1_Msk       (0x3UL)        /*!< EIVTC1 (Bitfield-Mask: 0x03)                          */
32781  #define R_GPT7_GTEITC_EIVTT1_Pos       (4UL)          /*!< EIVTT1 (Bit 4)                                        */
32782  #define R_GPT7_GTEITC_EIVTT1_Msk       (0xf0UL)       /*!< EIVTT1 (Bitfield-Mask: 0x0f)                          */
32783  #define R_GPT7_GTEITC_EITCNT1_Pos      (12UL)         /*!< EITCNT1 (Bit 12)                                      */
32784  #define R_GPT7_GTEITC_EITCNT1_Msk      (0xf000UL)     /*!< EITCNT1 (Bitfield-Mask: 0x0f)                         */
32785  #define R_GPT7_GTEITC_EIVTC2_Pos       (16UL)         /*!< EIVTC2 (Bit 16)                                       */
32786  #define R_GPT7_GTEITC_EIVTC2_Msk       (0x30000UL)    /*!< EIVTC2 (Bitfield-Mask: 0x03)                          */
32787  #define R_GPT7_GTEITC_EIVTT2_Pos       (20UL)         /*!< EIVTT2 (Bit 20)                                       */
32788  #define R_GPT7_GTEITC_EIVTT2_Msk       (0xf00000UL)   /*!< EIVTT2 (Bitfield-Mask: 0x0f)                          */
32789  #define R_GPT7_GTEITC_EITCNT2IV_Pos    (24UL)         /*!< EITCNT2IV (Bit 24)                                    */
32790  #define R_GPT7_GTEITC_EITCNT2IV_Msk    (0xf000000UL)  /*!< EITCNT2IV (Bitfield-Mask: 0x0f)                       */
32791  #define R_GPT7_GTEITC_EITCNT2_Pos      (28UL)         /*!< EITCNT2 (Bit 28)                                      */
32792  #define R_GPT7_GTEITC_EITCNT2_Msk      (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f)                         */
32793 /* =======================================================  GTEITLI1  ======================================================== */
32794  #define R_GPT7_GTEITLI1_EITLA_Pos      (0UL)          /*!< EITLA (Bit 0)                                         */
32795  #define R_GPT7_GTEITLI1_EITLA_Msk      (0x7UL)        /*!< EITLA (Bitfield-Mask: 0x07)                           */
32796  #define R_GPT7_GTEITLI1_EITLB_Pos      (4UL)          /*!< EITLB (Bit 4)                                         */
32797  #define R_GPT7_GTEITLI1_EITLB_Msk      (0x70UL)       /*!< EITLB (Bitfield-Mask: 0x07)                           */
32798  #define R_GPT7_GTEITLI1_EITLC_Pos      (8UL)          /*!< EITLC (Bit 8)                                         */
32799  #define R_GPT7_GTEITLI1_EITLC_Msk      (0x700UL)      /*!< EITLC (Bitfield-Mask: 0x07)                           */
32800  #define R_GPT7_GTEITLI1_EITLD_Pos      (12UL)         /*!< EITLD (Bit 12)                                        */
32801  #define R_GPT7_GTEITLI1_EITLD_Msk      (0x7000UL)     /*!< EITLD (Bitfield-Mask: 0x07)                           */
32802  #define R_GPT7_GTEITLI1_EITLE_Pos      (16UL)         /*!< EITLE (Bit 16)                                        */
32803  #define R_GPT7_GTEITLI1_EITLE_Msk      (0x70000UL)    /*!< EITLE (Bitfield-Mask: 0x07)                           */
32804  #define R_GPT7_GTEITLI1_EITLF_Pos      (20UL)         /*!< EITLF (Bit 20)                                        */
32805  #define R_GPT7_GTEITLI1_EITLF_Msk      (0x700000UL)   /*!< EITLF (Bitfield-Mask: 0x07)                           */
32806  #define R_GPT7_GTEITLI1_EITLV_Pos      (24UL)         /*!< EITLV (Bit 24)                                        */
32807  #define R_GPT7_GTEITLI1_EITLV_Msk      (0x7000000UL)  /*!< EITLV (Bitfield-Mask: 0x07)                           */
32808  #define R_GPT7_GTEITLI1_EITLU_Pos      (28UL)         /*!< EITLU (Bit 28)                                        */
32809  #define R_GPT7_GTEITLI1_EITLU_Msk      (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07)                           */
32810 /* =======================================================  GTEITLI2  ======================================================== */
32811  #define R_GPT7_GTEITLI2_EADTAL_Pos     (0UL)          /*!< EADTAL (Bit 0)                                        */
32812  #define R_GPT7_GTEITLI2_EADTAL_Msk     (0x7UL)        /*!< EADTAL (Bitfield-Mask: 0x07)                          */
32813  #define R_GPT7_GTEITLI2_EADTBL_Pos     (4UL)          /*!< EADTBL (Bit 4)                                        */
32814  #define R_GPT7_GTEITLI2_EADTBL_Msk     (0x70UL)       /*!< EADTBL (Bitfield-Mask: 0x07)                          */
32815 /* ========================================================  GTEITLB  ======================================================== */
32816  #define R_GPT7_GTEITLB_EBTLCA_Pos      (0UL)          /*!< EBTLCA (Bit 0)                                        */
32817  #define R_GPT7_GTEITLB_EBTLCA_Msk      (0x7UL)        /*!< EBTLCA (Bitfield-Mask: 0x07)                          */
32818  #define R_GPT7_GTEITLB_EBTLCB_Pos      (4UL)          /*!< EBTLCB (Bit 4)                                        */
32819  #define R_GPT7_GTEITLB_EBTLCB_Msk      (0x70UL)       /*!< EBTLCB (Bitfield-Mask: 0x07)                          */
32820  #define R_GPT7_GTEITLB_EBTLPR_Pos      (8UL)          /*!< EBTLPR (Bit 8)                                        */
32821  #define R_GPT7_GTEITLB_EBTLPR_Msk      (0x700UL)      /*!< EBTLPR (Bitfield-Mask: 0x07)                          */
32822  #define R_GPT7_GTEITLB_EBTLADA_Pos     (16UL)         /*!< EBTLADA (Bit 16)                                      */
32823  #define R_GPT7_GTEITLB_EBTLADA_Msk     (0x70000UL)    /*!< EBTLADA (Bitfield-Mask: 0x07)                         */
32824  #define R_GPT7_GTEITLB_EBTLADB_Pos     (20UL)         /*!< EBTLADB (Bit 20)                                      */
32825  #define R_GPT7_GTEITLB_EBTLADB_Msk     (0x700000UL)   /*!< EBTLADB (Bitfield-Mask: 0x07)                         */
32826  #define R_GPT7_GTEITLB_EBTLDVU_Pos     (24UL)         /*!< EBTLDVU (Bit 24)                                      */
32827  #define R_GPT7_GTEITLB_EBTLDVU_Msk     (0x7000000UL)  /*!< EBTLDVU (Bitfield-Mask: 0x07)                         */
32828  #define R_GPT7_GTEITLB_EBTLDVD_Pos     (28UL)         /*!< EBTLDVD (Bit 28)                                      */
32829  #define R_GPT7_GTEITLB_EBTLDVD_Msk     (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07)                         */
32830 /* ========================================================  GTSECSR  ======================================================== */
32831  #define R_GPT7_GTSECSR_SECSEL0_Pos     (0UL)          /*!< SECSEL0 (Bit 0)                                       */
32832  #define R_GPT7_GTSECSR_SECSEL0_Msk     (0x1UL)        /*!< SECSEL0 (Bitfield-Mask: 0x01)                         */
32833  #define R_GPT7_GTSECSR_SECSEL1_Pos     (1UL)          /*!< SECSEL1 (Bit 1)                                       */
32834  #define R_GPT7_GTSECSR_SECSEL1_Msk     (0x2UL)        /*!< SECSEL1 (Bitfield-Mask: 0x01)                         */
32835  #define R_GPT7_GTSECSR_SECSEL2_Pos     (2UL)          /*!< SECSEL2 (Bit 2)                                       */
32836  #define R_GPT7_GTSECSR_SECSEL2_Msk     (0x4UL)        /*!< SECSEL2 (Bitfield-Mask: 0x01)                         */
32837  #define R_GPT7_GTSECSR_SECSEL3_Pos     (3UL)          /*!< SECSEL3 (Bit 3)                                       */
32838  #define R_GPT7_GTSECSR_SECSEL3_Msk     (0x8UL)        /*!< SECSEL3 (Bitfield-Mask: 0x01)                         */
32839  #define R_GPT7_GTSECSR_SECSEL4_Pos     (4UL)          /*!< SECSEL4 (Bit 4)                                       */
32840  #define R_GPT7_GTSECSR_SECSEL4_Msk     (0x10UL)       /*!< SECSEL4 (Bitfield-Mask: 0x01)                         */
32841  #define R_GPT7_GTSECSR_SECSEL5_Pos     (5UL)          /*!< SECSEL5 (Bit 5)                                       */
32842  #define R_GPT7_GTSECSR_SECSEL5_Msk     (0x20UL)       /*!< SECSEL5 (Bitfield-Mask: 0x01)                         */
32843  #define R_GPT7_GTSECSR_SECSEL6_Pos     (6UL)          /*!< SECSEL6 (Bit 6)                                       */
32844  #define R_GPT7_GTSECSR_SECSEL6_Msk     (0x40UL)       /*!< SECSEL6 (Bitfield-Mask: 0x01)                         */
32845 /* ========================================================  GTSECR  ========================================================= */
32846  #define R_GPT7_GTSECR_SBDCE_Pos        (0UL)          /*!< SBDCE (Bit 0)                                         */
32847  #define R_GPT7_GTSECR_SBDCE_Msk        (0x1UL)        /*!< SBDCE (Bitfield-Mask: 0x01)                           */
32848  #define R_GPT7_GTSECR_SBDPE_Pos        (1UL)          /*!< SBDPE (Bit 1)                                         */
32849  #define R_GPT7_GTSECR_SBDPE_Msk        (0x2UL)        /*!< SBDPE (Bitfield-Mask: 0x01)                           */
32850  #define R_GPT7_GTSECR_SBDAE_Pos        (2UL)          /*!< SBDAE (Bit 2)                                         */
32851  #define R_GPT7_GTSECR_SBDAE_Msk        (0x4UL)        /*!< SBDAE (Bitfield-Mask: 0x01)                           */
32852  #define R_GPT7_GTSECR_SBDDE_Pos        (3UL)          /*!< SBDDE (Bit 3)                                         */
32853  #define R_GPT7_GTSECR_SBDDE_Msk        (0x8UL)        /*!< SBDDE (Bitfield-Mask: 0x01)                           */
32854  #define R_GPT7_GTSECR_SBDCD_Pos        (8UL)          /*!< SBDCD (Bit 8)                                         */
32855  #define R_GPT7_GTSECR_SBDCD_Msk        (0x100UL)      /*!< SBDCD (Bitfield-Mask: 0x01)                           */
32856  #define R_GPT7_GTSECR_SBDPD_Pos        (9UL)          /*!< SBDPD (Bit 9)                                         */
32857  #define R_GPT7_GTSECR_SBDPD_Msk        (0x200UL)      /*!< SBDPD (Bitfield-Mask: 0x01)                           */
32858  #define R_GPT7_GTSECR_SBDAD_Pos        (10UL)         /*!< SBDAD (Bit 10)                                        */
32859  #define R_GPT7_GTSECR_SBDAD_Msk        (0x400UL)      /*!< SBDAD (Bitfield-Mask: 0x01)                           */
32860  #define R_GPT7_GTSECR_SBDDD_Pos        (11UL)         /*!< SBDDD (Bit 11)                                        */
32861  #define R_GPT7_GTSECR_SBDDD_Msk        (0x800UL)      /*!< SBDDD (Bitfield-Mask: 0x01)                           */
32862 /* ========================================================  GTSWSR  ========================================================= */
32863  #define R_GPT7_GTSWSR_WSGTRGA_Pos      (0UL)          /*!< WSGTRGA (Bit 0)                                       */
32864  #define R_GPT7_GTSWSR_WSGTRGA_Msk      (0x3UL)        /*!< WSGTRGA (Bitfield-Mask: 0x03)                         */
32865  #define R_GPT7_GTSWSR_WSGTRGB_Pos      (2UL)          /*!< WSGTRGB (Bit 2)                                       */
32866  #define R_GPT7_GTSWSR_WSGTRGB_Msk      (0xcUL)        /*!< WSGTRGB (Bitfield-Mask: 0x03)                         */
32867  #define R_GPT7_GTSWSR_WSGTRGC_Pos      (4UL)          /*!< WSGTRGC (Bit 4)                                       */
32868  #define R_GPT7_GTSWSR_WSGTRGC_Msk      (0x30UL)       /*!< WSGTRGC (Bitfield-Mask: 0x03)                         */
32869  #define R_GPT7_GTSWSR_WSGTRGD_Pos      (6UL)          /*!< WSGTRGD (Bit 6)                                       */
32870  #define R_GPT7_GTSWSR_WSGTRGD_Msk      (0xc0UL)       /*!< WSGTRGD (Bitfield-Mask: 0x03)                         */
32871  #define R_GPT7_GTSWSR_WSELCA_Pos       (16UL)         /*!< WSELCA (Bit 16)                                       */
32872  #define R_GPT7_GTSWSR_WSELCA_Msk       (0x10000UL)    /*!< WSELCA (Bitfield-Mask: 0x01)                          */
32873  #define R_GPT7_GTSWSR_WSELCB_Pos       (17UL)         /*!< WSELCB (Bit 17)                                       */
32874  #define R_GPT7_GTSWSR_WSELCB_Msk       (0x20000UL)    /*!< WSELCB (Bitfield-Mask: 0x01)                          */
32875  #define R_GPT7_GTSWSR_WSELCC_Pos       (18UL)         /*!< WSELCC (Bit 18)                                       */
32876  #define R_GPT7_GTSWSR_WSELCC_Msk       (0x40000UL)    /*!< WSELCC (Bitfield-Mask: 0x01)                          */
32877  #define R_GPT7_GTSWSR_WSELCD_Pos       (19UL)         /*!< WSELCD (Bit 19)                                       */
32878  #define R_GPT7_GTSWSR_WSELCD_Msk       (0x80000UL)    /*!< WSELCD (Bitfield-Mask: 0x01)                          */
32879  #define R_GPT7_GTSWSR_WSELCE_Pos       (20UL)         /*!< WSELCE (Bit 20)                                       */
32880  #define R_GPT7_GTSWSR_WSELCE_Msk       (0x100000UL)   /*!< WSELCE (Bitfield-Mask: 0x01)                          */
32881  #define R_GPT7_GTSWSR_WSELCF_Pos       (21UL)         /*!< WSELCF (Bit 21)                                       */
32882  #define R_GPT7_GTSWSR_WSELCF_Msk       (0x200000UL)   /*!< WSELCF (Bitfield-Mask: 0x01)                          */
32883  #define R_GPT7_GTSWSR_WSELCG_Pos       (22UL)         /*!< WSELCG (Bit 22)                                       */
32884  #define R_GPT7_GTSWSR_WSELCG_Msk       (0x400000UL)   /*!< WSELCG (Bitfield-Mask: 0x01)                          */
32885  #define R_GPT7_GTSWSR_CSELCH_Pos       (23UL)         /*!< CSELCH (Bit 23)                                       */
32886  #define R_GPT7_GTSWSR_CSELCH_Msk       (0x800000UL)   /*!< CSELCH (Bitfield-Mask: 0x01)                          */
32887 /* ========================================================  GTSWOS  ========================================================= */
32888 
32889 /* =========================================================================================================================== */
32890 /* ================                                          R_SCI0                                           ================ */
32891 /* =========================================================================================================================== */
32892 
32893 /* ==========================================================  RDR  ========================================================== */
32894  #define R_SCI0_RDR_RDAT_Pos           (0UL)          /*!< RDAT (Bit 0)                                          */
32895  #define R_SCI0_RDR_RDAT_Msk           (0x1ffUL)      /*!< RDAT (Bitfield-Mask: 0x1ff)                           */
32896  #define R_SCI0_RDR_MPB_Pos            (9UL)          /*!< MPB (Bit 9)                                           */
32897  #define R_SCI0_RDR_MPB_Msk            (0x200UL)      /*!< MPB (Bitfield-Mask: 0x01)                             */
32898  #define R_SCI0_RDR_DR_Pos             (10UL)         /*!< DR (Bit 10)                                           */
32899  #define R_SCI0_RDR_DR_Msk             (0x400UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
32900  #define R_SCI0_RDR_FPER_Pos           (11UL)         /*!< FPER (Bit 11)                                         */
32901  #define R_SCI0_RDR_FPER_Msk           (0x800UL)      /*!< FPER (Bitfield-Mask: 0x01)                            */
32902  #define R_SCI0_RDR_FFER_Pos           (12UL)         /*!< FFER (Bit 12)                                         */
32903  #define R_SCI0_RDR_FFER_Msk           (0x1000UL)     /*!< FFER (Bitfield-Mask: 0x01)                            */
32904  #define R_SCI0_RDR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
32905  #define R_SCI0_RDR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
32906  #define R_SCI0_RDR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
32907  #define R_SCI0_RDR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
32908  #define R_SCI0_RDR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
32909  #define R_SCI0_RDR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
32910 /* ==========================================================  TDR  ========================================================== */
32911  #define R_SCI0_TDR_TDAT_Pos           (0UL)          /*!< TDAT (Bit 0)                                          */
32912  #define R_SCI0_TDR_TDAT_Msk           (0x1ffUL)      /*!< TDAT (Bitfield-Mask: 0x1ff)                           */
32913  #define R_SCI0_TDR_MPBT_Pos           (9UL)          /*!< MPBT (Bit 9)                                          */
32914  #define R_SCI0_TDR_MPBT_Msk           (0x200UL)      /*!< MPBT (Bitfield-Mask: 0x01)                            */
32915 /* =========================================================  CCR0  ========================================================== */
32916  #define R_SCI0_CCR0_RE_Pos            (0UL)          /*!< RE (Bit 0)                                            */
32917  #define R_SCI0_CCR0_RE_Msk            (0x1UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
32918  #define R_SCI0_CCR0_TE_Pos            (4UL)          /*!< TE (Bit 4)                                            */
32919  #define R_SCI0_CCR0_TE_Msk            (0x10UL)       /*!< TE (Bitfield-Mask: 0x01)                              */
32920  #define R_SCI0_CCR0_MPIE_Pos          (8UL)          /*!< MPIE (Bit 8)                                          */
32921  #define R_SCI0_CCR0_MPIE_Msk          (0x100UL)      /*!< MPIE (Bitfield-Mask: 0x01)                            */
32922  #define R_SCI0_CCR0_DCME_Pos          (9UL)          /*!< DCME (Bit 9)                                          */
32923  #define R_SCI0_CCR0_DCME_Msk          (0x200UL)      /*!< DCME (Bitfield-Mask: 0x01)                            */
32924  #define R_SCI0_CCR0_IDSEL_Pos         (10UL)         /*!< IDSEL (Bit 10)                                        */
32925  #define R_SCI0_CCR0_IDSEL_Msk         (0x400UL)      /*!< IDSEL (Bitfield-Mask: 0x01)                           */
32926  #define R_SCI0_CCR0_RIE_Pos           (16UL)         /*!< RIE (Bit 16)                                          */
32927  #define R_SCI0_CCR0_RIE_Msk           (0x10000UL)    /*!< RIE (Bitfield-Mask: 0x01)                             */
32928  #define R_SCI0_CCR0_TIE_Pos           (20UL)         /*!< TIE (Bit 20)                                          */
32929  #define R_SCI0_CCR0_TIE_Msk           (0x100000UL)   /*!< TIE (Bitfield-Mask: 0x01)                             */
32930  #define R_SCI0_CCR0_TEIE_Pos          (21UL)         /*!< TEIE (Bit 21)                                         */
32931  #define R_SCI0_CCR0_TEIE_Msk          (0x200000UL)   /*!< TEIE (Bitfield-Mask: 0x01)                            */
32932  #define R_SCI0_CCR0_SSE_Pos           (24UL)         /*!< SSE (Bit 24)                                          */
32933  #define R_SCI0_CCR0_SSE_Msk           (0x1000000UL)  /*!< SSE (Bitfield-Mask: 0x01)                             */
32934 /* =========================================================  CCR1  ========================================================== */
32935  #define R_SCI0_CCR1_CTSE_Pos          (0UL)          /*!< CTSE (Bit 0)                                          */
32936  #define R_SCI0_CCR1_CTSE_Msk          (0x1UL)        /*!< CTSE (Bitfield-Mask: 0x01)                            */
32937  #define R_SCI0_CCR1_CTSPEN_Pos        (1UL)          /*!< CTSPEN (Bit 1)                                        */
32938  #define R_SCI0_CCR1_CTSPEN_Msk        (0x2UL)        /*!< CTSPEN (Bitfield-Mask: 0x01)                          */
32939  #define R_SCI0_CCR1_SPB2DT_Pos        (4UL)          /*!< SPB2DT (Bit 4)                                        */
32940  #define R_SCI0_CCR1_SPB2DT_Msk        (0x10UL)       /*!< SPB2DT (Bitfield-Mask: 0x01)                          */
32941  #define R_SCI0_CCR1_SPB2IO_Pos        (5UL)          /*!< SPB2IO (Bit 5)                                        */
32942  #define R_SCI0_CCR1_SPB2IO_Msk        (0x20UL)       /*!< SPB2IO (Bitfield-Mask: 0x01)                          */
32943  #define R_SCI0_CCR1_PE_Pos            (8UL)          /*!< PE (Bit 8)                                            */
32944  #define R_SCI0_CCR1_PE_Msk            (0x100UL)      /*!< PE (Bitfield-Mask: 0x01)                              */
32945  #define R_SCI0_CCR1_PM_Pos            (9UL)          /*!< PM (Bit 9)                                            */
32946  #define R_SCI0_CCR1_PM_Msk            (0x200UL)      /*!< PM (Bitfield-Mask: 0x01)                              */
32947  #define R_SCI0_CCR1_TINV_Pos          (12UL)         /*!< TINV (Bit 12)                                         */
32948  #define R_SCI0_CCR1_TINV_Msk          (0x1000UL)     /*!< TINV (Bitfield-Mask: 0x01)                            */
32949  #define R_SCI0_CCR1_RINV_Pos          (13UL)         /*!< RINV (Bit 13)                                         */
32950  #define R_SCI0_CCR1_RINV_Msk          (0x2000UL)     /*!< RINV (Bitfield-Mask: 0x01)                            */
32951  #define R_SCI0_CCR1_SPLP_Pos          (16UL)         /*!< SPLP (Bit 16)                                         */
32952  #define R_SCI0_CCR1_SPLP_Msk          (0x10000UL)    /*!< SPLP (Bitfield-Mask: 0x01)                            */
32953  #define R_SCI0_CCR1_SHARPS_Pos        (20UL)         /*!< SHARPS (Bit 20)                                       */
32954  #define R_SCI0_CCR1_SHARPS_Msk        (0x100000UL)   /*!< SHARPS (Bitfield-Mask: 0x01)                          */
32955  #define R_SCI0_CCR1_NFCS_Pos          (24UL)         /*!< NFCS (Bit 24)                                         */
32956  #define R_SCI0_CCR1_NFCS_Msk          (0x7000000UL)  /*!< NFCS (Bitfield-Mask: 0x07)                            */
32957  #define R_SCI0_CCR1_NFEN_Pos          (28UL)         /*!< NFEN (Bit 28)                                         */
32958  #define R_SCI0_CCR1_NFEN_Msk          (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
32959 /* =========================================================  CCR2  ========================================================== */
32960  #define R_SCI0_CCR2_BCP_Pos           (0UL)          /*!< BCP (Bit 0)                                           */
32961  #define R_SCI0_CCR2_BCP_Msk           (0x7UL)        /*!< BCP (Bitfield-Mask: 0x07)                             */
32962  #define R_SCI0_CCR2_BGDM_Pos          (4UL)          /*!< BGDM (Bit 4)                                          */
32963  #define R_SCI0_CCR2_BGDM_Msk          (0x10UL)       /*!< BGDM (Bitfield-Mask: 0x01)                            */
32964  #define R_SCI0_CCR2_ABCS_Pos          (5UL)          /*!< ABCS (Bit 5)                                          */
32965  #define R_SCI0_CCR2_ABCS_Msk          (0x20UL)       /*!< ABCS (Bitfield-Mask: 0x01)                            */
32966  #define R_SCI0_CCR2_ABCSE_Pos         (6UL)          /*!< ABCSE (Bit 6)                                         */
32967  #define R_SCI0_CCR2_ABCSE_Msk         (0x40UL)       /*!< ABCSE (Bitfield-Mask: 0x01)                           */
32968  #define R_SCI0_CCR2_BRR_Pos           (8UL)          /*!< BRR (Bit 8)                                           */
32969  #define R_SCI0_CCR2_BRR_Msk           (0xff00UL)     /*!< BRR (Bitfield-Mask: 0xff)                             */
32970  #define R_SCI0_CCR2_BRME_Pos          (16UL)         /*!< BRME (Bit 16)                                         */
32971  #define R_SCI0_CCR2_BRME_Msk          (0x10000UL)    /*!< BRME (Bitfield-Mask: 0x01)                            */
32972  #define R_SCI0_CCR2_CKS_Pos           (20UL)         /*!< CKS (Bit 20)                                          */
32973  #define R_SCI0_CCR2_CKS_Msk           (0x300000UL)   /*!< CKS (Bitfield-Mask: 0x03)                             */
32974  #define R_SCI0_CCR2_MDDR_Pos          (24UL)         /*!< MDDR (Bit 24)                                         */
32975  #define R_SCI0_CCR2_MDDR_Msk          (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff)                            */
32976 /* =========================================================  CCR3  ========================================================== */
32977  #define R_SCI0_CCR3_CPHA_Pos          (0UL)          /*!< CPHA (Bit 0)                                          */
32978  #define R_SCI0_CCR3_CPHA_Msk          (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
32979  #define R_SCI0_CCR3_CPOL_Pos          (1UL)          /*!< CPOL (Bit 1)                                          */
32980  #define R_SCI0_CCR3_CPOL_Msk          (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
32981  #define R_SCI0_CCR3_BPEN_Pos          (7UL)          /*!< BPEN (Bit 7)                                          */
32982  #define R_SCI0_CCR3_BPEN_Msk          (0x80UL)       /*!< BPEN (Bitfield-Mask: 0x01)                            */
32983  #define R_SCI0_CCR3_CHR_Pos           (8UL)          /*!< CHR (Bit 8)                                           */
32984  #define R_SCI0_CCR3_CHR_Msk           (0x300UL)      /*!< CHR (Bitfield-Mask: 0x03)                             */
32985  #define R_SCI0_CCR3_LSBF_Pos          (12UL)         /*!< LSBF (Bit 12)                                         */
32986  #define R_SCI0_CCR3_LSBF_Msk          (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
32987  #define R_SCI0_CCR3_SINV_Pos          (13UL)         /*!< SINV (Bit 13)                                         */
32988  #define R_SCI0_CCR3_SINV_Msk          (0x2000UL)     /*!< SINV (Bitfield-Mask: 0x01)                            */
32989  #define R_SCI0_CCR3_STP_Pos           (14UL)         /*!< STP (Bit 14)                                          */
32990  #define R_SCI0_CCR3_STP_Msk           (0x4000UL)     /*!< STP (Bitfield-Mask: 0x01)                             */
32991  #define R_SCI0_CCR3_RXDESEL_Pos       (15UL)         /*!< RXDESEL (Bit 15)                                      */
32992  #define R_SCI0_CCR3_RXDESEL_Msk       (0x8000UL)     /*!< RXDESEL (Bitfield-Mask: 0x01)                         */
32993  #define R_SCI0_CCR3_MOD_Pos           (16UL)         /*!< MOD (Bit 16)                                          */
32994  #define R_SCI0_CCR3_MOD_Msk           (0x70000UL)    /*!< MOD (Bitfield-Mask: 0x07)                             */
32995  #define R_SCI0_CCR3_MP_Pos            (19UL)         /*!< MP (Bit 19)                                           */
32996  #define R_SCI0_CCR3_MP_Msk            (0x80000UL)    /*!< MP (Bitfield-Mask: 0x01)                              */
32997  #define R_SCI0_CCR3_FM_Pos            (20UL)         /*!< FM (Bit 20)                                           */
32998  #define R_SCI0_CCR3_FM_Msk            (0x100000UL)   /*!< FM (Bitfield-Mask: 0x01)                              */
32999  #define R_SCI0_CCR3_DEN_Pos           (21UL)         /*!< DEN (Bit 21)                                          */
33000  #define R_SCI0_CCR3_DEN_Msk           (0x200000UL)   /*!< DEN (Bitfield-Mask: 0x01)                             */
33001  #define R_SCI0_CCR3_CKE_Pos           (24UL)         /*!< CKE (Bit 24)                                          */
33002  #define R_SCI0_CCR3_CKE_Msk           (0x3000000UL)  /*!< CKE (Bitfield-Mask: 0x03)                             */
33003  #define R_SCI0_CCR3_GM_Pos            (28UL)         /*!< GM (Bit 28)                                           */
33004  #define R_SCI0_CCR3_GM_Msk            (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01)                              */
33005  #define R_SCI0_CCR3_BLK_Pos           (29UL)         /*!< BLK (Bit 29)                                          */
33006  #define R_SCI0_CCR3_BLK_Msk           (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01)                             */
33007 /* =========================================================  CCR4  ========================================================== */
33008  #define R_SCI0_CCR4_CMPD_Pos          (0UL)          /*!< CMPD (Bit 0)                                          */
33009  #define R_SCI0_CCR4_CMPD_Msk          (0x1ffUL)      /*!< CMPD (Bitfield-Mask: 0x1ff)                           */
33010  #define R_SCI0_CCR4_ASEN_Pos          (16UL)         /*!< ASEN (Bit 16)                                         */
33011  #define R_SCI0_CCR4_ASEN_Msk          (0x10000UL)    /*!< ASEN (Bitfield-Mask: 0x01)                            */
33012  #define R_SCI0_CCR4_ATEN_Pos          (17UL)         /*!< ATEN (Bit 17)                                         */
33013  #define R_SCI0_CCR4_ATEN_Msk          (0x20000UL)    /*!< ATEN (Bitfield-Mask: 0x01)                            */
33014  #define R_SCI0_CCR4_AST_Pos           (24UL)         /*!< AST (Bit 24)                                          */
33015  #define R_SCI0_CCR4_AST_Msk           (0x7000000UL)  /*!< AST (Bitfield-Mask: 0x07)                             */
33016  #define R_SCI0_CCR4_AJD_Pos           (27UL)         /*!< AJD (Bit 27)                                          */
33017  #define R_SCI0_CCR4_AJD_Msk           (0x8000000UL)  /*!< AJD (Bitfield-Mask: 0x01)                             */
33018  #define R_SCI0_CCR4_ATT_Pos           (28UL)         /*!< ATT (Bit 28)                                          */
33019  #define R_SCI0_CCR4_ATT_Msk           (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07)                             */
33020  #define R_SCI0_CCR4_AET_Pos           (31UL)         /*!< AET (Bit 31)                                          */
33021  #define R_SCI0_CCR4_AET_Msk           (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01)                             */
33022 /* ==========================================================  ICR  ========================================================== */
33023  #define R_SCI0_ICR_IICDL_Pos          (0UL)          /*!< IICDL (Bit 0)                                         */
33024  #define R_SCI0_ICR_IICDL_Msk          (0x1fUL)       /*!< IICDL (Bitfield-Mask: 0x1f)                           */
33025  #define R_SCI0_ICR_IICINTM_Pos        (8UL)          /*!< IICINTM (Bit 8)                                       */
33026  #define R_SCI0_ICR_IICINTM_Msk        (0x100UL)      /*!< IICINTM (Bitfield-Mask: 0x01)                         */
33027  #define R_SCI0_ICR_IICCSC_Pos         (9UL)          /*!< IICCSC (Bit 9)                                        */
33028  #define R_SCI0_ICR_IICCSC_Msk         (0x200UL)      /*!< IICCSC (Bitfield-Mask: 0x01)                          */
33029  #define R_SCI0_ICR_IICACKT_Pos        (13UL)         /*!< IICACKT (Bit 13)                                      */
33030  #define R_SCI0_ICR_IICACKT_Msk        (0x2000UL)     /*!< IICACKT (Bitfield-Mask: 0x01)                         */
33031  #define R_SCI0_ICR_IICSTAREQ_Pos      (16UL)         /*!< IICSTAREQ (Bit 16)                                    */
33032  #define R_SCI0_ICR_IICSTAREQ_Msk      (0x10000UL)    /*!< IICSTAREQ (Bitfield-Mask: 0x01)                       */
33033  #define R_SCI0_ICR_IICRSTAREQ_Pos     (17UL)         /*!< IICRSTAREQ (Bit 17)                                   */
33034  #define R_SCI0_ICR_IICRSTAREQ_Msk     (0x20000UL)    /*!< IICRSTAREQ (Bitfield-Mask: 0x01)                      */
33035  #define R_SCI0_ICR_IICSTPREQ_Pos      (18UL)         /*!< IICSTPREQ (Bit 18)                                    */
33036  #define R_SCI0_ICR_IICSTPREQ_Msk      (0x40000UL)    /*!< IICSTPREQ (Bitfield-Mask: 0x01)                       */
33037  #define R_SCI0_ICR_IICSDAS_Pos        (20UL)         /*!< IICSDAS (Bit 20)                                      */
33038  #define R_SCI0_ICR_IICSDAS_Msk        (0x300000UL)   /*!< IICSDAS (Bitfield-Mask: 0x03)                         */
33039  #define R_SCI0_ICR_IICSCLS_Pos        (22UL)         /*!< IICSCLS (Bit 22)                                      */
33040  #define R_SCI0_ICR_IICSCLS_Msk        (0xc00000UL)   /*!< IICSCLS (Bitfield-Mask: 0x03)                         */
33041 /* ==========================================================  FCR  ========================================================== */
33042  #define R_SCI0_FCR_DRES_Pos           (0UL)          /*!< DRES (Bit 0)                                          */
33043  #define R_SCI0_FCR_DRES_Msk           (0x1UL)        /*!< DRES (Bitfield-Mask: 0x01)                            */
33044  #define R_SCI0_FCR_TTRG_Pos           (8UL)          /*!< TTRG (Bit 8)                                          */
33045  #define R_SCI0_FCR_TTRG_Msk           (0x1f00UL)     /*!< TTRG (Bitfield-Mask: 0x1f)                            */
33046  #define R_SCI0_FCR_TFRST_Pos          (15UL)         /*!< TFRST (Bit 15)                                        */
33047  #define R_SCI0_FCR_TFRST_Msk          (0x8000UL)     /*!< TFRST (Bitfield-Mask: 0x01)                           */
33048  #define R_SCI0_FCR_RTRG_Pos           (16UL)         /*!< RTRG (Bit 16)                                         */
33049  #define R_SCI0_FCR_RTRG_Msk           (0x1f0000UL)   /*!< RTRG (Bitfield-Mask: 0x1f)                            */
33050  #define R_SCI0_FCR_RFRST_Pos          (23UL)         /*!< RFRST (Bit 23)                                        */
33051  #define R_SCI0_FCR_RFRST_Msk          (0x800000UL)   /*!< RFRST (Bitfield-Mask: 0x01)                           */
33052  #define R_SCI0_FCR_RSTRG_Pos          (24UL)         /*!< RSTRG (Bit 24)                                        */
33053  #define R_SCI0_FCR_RSTRG_Msk          (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f)                           */
33054 /* ==========================================================  DCR  ========================================================== */
33055  #define R_SCI0_DCR_DEPOL_Pos          (0UL)          /*!< DEPOL (Bit 0)                                         */
33056  #define R_SCI0_DCR_DEPOL_Msk          (0x1UL)        /*!< DEPOL (Bitfield-Mask: 0x01)                           */
33057  #define R_SCI0_DCR_DEAST_Pos          (8UL)          /*!< DEAST (Bit 8)                                         */
33058  #define R_SCI0_DCR_DEAST_Msk          (0x1f00UL)     /*!< DEAST (Bitfield-Mask: 0x1f)                           */
33059  #define R_SCI0_DCR_DENGT_Pos          (16UL)         /*!< DENGT (Bit 16)                                        */
33060  #define R_SCI0_DCR_DENGT_Msk          (0x1f0000UL)   /*!< DENGT (Bitfield-Mask: 0x1f)                           */
33061 /* ==========================================================  CSR  ========================================================== */
33062  #define R_SCI0_CSR_ERS_Pos            (4UL)          /*!< ERS (Bit 4)                                           */
33063  #define R_SCI0_CSR_ERS_Msk            (0x10UL)       /*!< ERS (Bitfield-Mask: 0x01)                             */
33064  #define R_SCI0_CSR_RXDMON_Pos         (15UL)         /*!< RXDMON (Bit 15)                                       */
33065  #define R_SCI0_CSR_RXDMON_Msk         (0x8000UL)     /*!< RXDMON (Bitfield-Mask: 0x01)                          */
33066  #define R_SCI0_CSR_DCMF_Pos           (16UL)         /*!< DCMF (Bit 16)                                         */
33067  #define R_SCI0_CSR_DCMF_Msk           (0x10000UL)    /*!< DCMF (Bitfield-Mask: 0x01)                            */
33068  #define R_SCI0_CSR_DPER_Pos           (17UL)         /*!< DPER (Bit 17)                                         */
33069  #define R_SCI0_CSR_DPER_Msk           (0x20000UL)    /*!< DPER (Bitfield-Mask: 0x01)                            */
33070  #define R_SCI0_CSR_DFER_Pos           (18UL)         /*!< DFER (Bit 18)                                         */
33071  #define R_SCI0_CSR_DFER_Msk           (0x40000UL)    /*!< DFER (Bitfield-Mask: 0x01)                            */
33072  #define R_SCI0_CSR_ORER_Pos           (24UL)         /*!< ORER (Bit 24)                                         */
33073  #define R_SCI0_CSR_ORER_Msk           (0x1000000UL)  /*!< ORER (Bitfield-Mask: 0x01)                            */
33074  #define R_SCI0_CSR_MFF_Pos            (26UL)         /*!< MFF (Bit 26)                                          */
33075  #define R_SCI0_CSR_MFF_Msk            (0x4000000UL)  /*!< MFF (Bitfield-Mask: 0x01)                             */
33076  #define R_SCI0_CSR_PER_Pos            (27UL)         /*!< PER (Bit 27)                                          */
33077  #define R_SCI0_CSR_PER_Msk            (0x8000000UL)  /*!< PER (Bitfield-Mask: 0x01)                             */
33078  #define R_SCI0_CSR_FER_Pos            (28UL)         /*!< FER (Bit 28)                                          */
33079  #define R_SCI0_CSR_FER_Msk            (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01)                             */
33080  #define R_SCI0_CSR_TDRE_Pos           (29UL)         /*!< TDRE (Bit 29)                                         */
33081  #define R_SCI0_CSR_TDRE_Msk           (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
33082  #define R_SCI0_CSR_TEND_Pos           (30UL)         /*!< TEND (Bit 30)                                         */
33083  #define R_SCI0_CSR_TEND_Msk           (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
33084  #define R_SCI0_CSR_RDRF_Pos           (31UL)         /*!< RDRF (Bit 31)                                         */
33085  #define R_SCI0_CSR_RDRF_Msk           (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
33086 /* ==========================================================  ISR  ========================================================== */
33087  #define R_SCI0_ISR_IICACKR_Pos        (0UL)          /*!< IICACKR (Bit 0)                                       */
33088  #define R_SCI0_ISR_IICACKR_Msk        (0x1UL)        /*!< IICACKR (Bitfield-Mask: 0x01)                         */
33089  #define R_SCI0_ISR_IICSTIF_Pos        (3UL)          /*!< IICSTIF (Bit 3)                                       */
33090  #define R_SCI0_ISR_IICSTIF_Msk        (0x8UL)        /*!< IICSTIF (Bitfield-Mask: 0x01)                         */
33091 /* =========================================================  FRSR  ========================================================== */
33092  #define R_SCI0_FRSR_DR_Pos            (0UL)          /*!< DR (Bit 0)                                            */
33093  #define R_SCI0_FRSR_DR_Msk            (0x1UL)        /*!< DR (Bitfield-Mask: 0x01)                              */
33094  #define R_SCI0_FRSR_R_Pos             (8UL)          /*!< R (Bit 8)                                             */
33095  #define R_SCI0_FRSR_R_Msk             (0x3f00UL)     /*!< R (Bitfield-Mask: 0x3f)                               */
33096  #define R_SCI0_FRSR_PNUM_Pos          (16UL)         /*!< PNUM (Bit 16)                                         */
33097  #define R_SCI0_FRSR_PNUM_Msk          (0x3f0000UL)   /*!< PNUM (Bitfield-Mask: 0x3f)                            */
33098  #define R_SCI0_FRSR_FNUM_Pos          (24UL)         /*!< FNUM (Bit 24)                                         */
33099  #define R_SCI0_FRSR_FNUM_Msk          (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f)                            */
33100 /* =========================================================  FTSR  ========================================================== */
33101  #define R_SCI0_FTSR_T_Pos             (0UL)          /*!< T (Bit 0)                                             */
33102  #define R_SCI0_FTSR_T_Msk             (0x3fUL)       /*!< T (Bitfield-Mask: 0x3f)                               */
33103 /* =========================================================  CFCLR  ========================================================= */
33104  #define R_SCI0_CFCLR_ERSC_Pos         (4UL)          /*!< ERSC (Bit 4)                                          */
33105  #define R_SCI0_CFCLR_ERSC_Msk         (0x10UL)       /*!< ERSC (Bitfield-Mask: 0x01)                            */
33106  #define R_SCI0_CFCLR_DCMFC_Pos        (16UL)         /*!< DCMFC (Bit 16)                                        */
33107  #define R_SCI0_CFCLR_DCMFC_Msk        (0x10000UL)    /*!< DCMFC (Bitfield-Mask: 0x01)                           */
33108  #define R_SCI0_CFCLR_DPERC_Pos        (17UL)         /*!< DPERC (Bit 17)                                        */
33109  #define R_SCI0_CFCLR_DPERC_Msk        (0x20000UL)    /*!< DPERC (Bitfield-Mask: 0x01)                           */
33110  #define R_SCI0_CFCLR_DFERC_Pos        (18UL)         /*!< DFERC (Bit 18)                                        */
33111  #define R_SCI0_CFCLR_DFERC_Msk        (0x40000UL)    /*!< DFERC (Bitfield-Mask: 0x01)                           */
33112  #define R_SCI0_CFCLR_ORERC_Pos        (24UL)         /*!< ORERC (Bit 24)                                        */
33113  #define R_SCI0_CFCLR_ORERC_Msk        (0x1000000UL)  /*!< ORERC (Bitfield-Mask: 0x01)                           */
33114  #define R_SCI0_CFCLR_MFFC_Pos         (26UL)         /*!< MFFC (Bit 26)                                         */
33115  #define R_SCI0_CFCLR_MFFC_Msk         (0x4000000UL)  /*!< MFFC (Bitfield-Mask: 0x01)                            */
33116  #define R_SCI0_CFCLR_PERC_Pos         (27UL)         /*!< PERC (Bit 27)                                         */
33117  #define R_SCI0_CFCLR_PERC_Msk         (0x8000000UL)  /*!< PERC (Bitfield-Mask: 0x01)                            */
33118  #define R_SCI0_CFCLR_FERC_Pos         (28UL)         /*!< FERC (Bit 28)                                         */
33119  #define R_SCI0_CFCLR_FERC_Msk         (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01)                            */
33120  #define R_SCI0_CFCLR_TDREC_Pos        (29UL)         /*!< TDREC (Bit 29)                                        */
33121  #define R_SCI0_CFCLR_TDREC_Msk        (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01)                           */
33122  #define R_SCI0_CFCLR_RDRFC_Pos        (31UL)         /*!< RDRFC (Bit 31)                                        */
33123  #define R_SCI0_CFCLR_RDRFC_Msk        (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01)                           */
33124 /* ========================================================  ICFCLR  ========================================================= */
33125  #define R_SCI0_ICFCLR_IICSTIFC_Pos    (3UL)          /*!< IICSTIFC (Bit 3)                                      */
33126  #define R_SCI0_ICFCLR_IICSTIFC_Msk    (0x8UL)        /*!< IICSTIFC (Bitfield-Mask: 0x01)                        */
33127 /* =========================================================  FFCLR  ========================================================= */
33128  #define R_SCI0_FFCLR_DRC_Pos          (0UL)          /*!< DRC (Bit 0)                                           */
33129  #define R_SCI0_FFCLR_DRC_Msk          (0x1UL)        /*!< DRC (Bitfield-Mask: 0x01)                             */
33130 
33131 /* =========================================================================================================================== */
33132 /* ================                                          R_SPI0                                           ================ */
33133 /* =========================================================================================================================== */
33134 
33135 /* =========================================================  SPDR  ========================================================== */
33136  #define R_SPI0_SPDR_SPD_Pos         (0UL)          /*!< SPD (Bit 0)                                           */
33137  #define R_SPI0_SPDR_SPD_Msk         (0xffffffffUL) /*!< SPD (Bitfield-Mask: 0xffffffff)                       */
33138 /* ========================================================  SPDR_HA  ======================================================== */
33139 /* ========================================================  SPDR_BY  ======================================================== */
33140 /* =========================================================  SPCKD  ========================================================= */
33141  #define R_SPI0_SPCKD_SCKDL_Pos      (0UL)          /*!< SCKDL (Bit 0)                                         */
33142  #define R_SPI0_SPCKD_SCKDL_Msk      (0x7UL)        /*!< SCKDL (Bitfield-Mask: 0x07)                           */
33143 /* =========================================================  SSLND  ========================================================= */
33144  #define R_SPI0_SSLND_SLNDL_Pos      (0UL)          /*!< SLNDL (Bit 0)                                         */
33145  #define R_SPI0_SSLND_SLNDL_Msk      (0x7UL)        /*!< SLNDL (Bitfield-Mask: 0x07)                           */
33146 /* =========================================================  SPND  ========================================================== */
33147  #define R_SPI0_SPND_SPNDL_Pos       (0UL)          /*!< SPNDL (Bit 0)                                         */
33148  #define R_SPI0_SPND_SPNDL_Msk       (0x7UL)        /*!< SPNDL (Bitfield-Mask: 0x07)                           */
33149 /* =========================================================  MRCKD  ========================================================= */
33150  #define R_SPI0_MRCKD_ARST_Pos       (0UL)          /*!< ARST (Bit 0)                                          */
33151  #define R_SPI0_MRCKD_ARST_Msk       (0x7UL)        /*!< ARST (Bitfield-Mask: 0x07)                            */
33152 /* =========================================================  SPCR  ========================================================== */
33153  #define R_SPI0_SPCR_SPE_Pos         (0UL)          /*!< SPE (Bit 0)                                           */
33154  #define R_SPI0_SPCR_SPE_Msk         (0x1UL)        /*!< SPE (Bitfield-Mask: 0x01)                             */
33155  #define R_SPI0_SPCR_SPSCKSEL_Pos    (7UL)          /*!< SPSCKSEL (Bit 7)                                      */
33156  #define R_SPI0_SPCR_SPSCKSEL_Msk    (0x80UL)       /*!< SPSCKSEL (Bitfield-Mask: 0x01)                        */
33157  #define R_SPI0_SPCR_SPPE_Pos        (8UL)          /*!< SPPE (Bit 8)                                          */
33158  #define R_SPI0_SPCR_SPPE_Msk        (0x100UL)      /*!< SPPE (Bitfield-Mask: 0x01)                            */
33159  #define R_SPI0_SPCR_SPOE_Pos        (9UL)          /*!< SPOE (Bit 9)                                          */
33160  #define R_SPI0_SPCR_SPOE_Msk        (0x200UL)      /*!< SPOE (Bitfield-Mask: 0x01)                            */
33161  #define R_SPI0_SPCR_PTE_Pos         (11UL)         /*!< PTE (Bit 11)                                          */
33162  #define R_SPI0_SPCR_PTE_Msk         (0x800UL)      /*!< PTE (Bitfield-Mask: 0x01)                             */
33163  #define R_SPI0_SPCR_SCKASE_Pos      (12UL)         /*!< SCKASE (Bit 12)                                       */
33164  #define R_SPI0_SPCR_SCKASE_Msk      (0x1000UL)     /*!< SCKASE (Bitfield-Mask: 0x01)                          */
33165  #define R_SPI0_SPCR_BFDS_Pos        (13UL)         /*!< BFDS (Bit 13)                                         */
33166  #define R_SPI0_SPCR_BFDS_Msk        (0x2000UL)     /*!< BFDS (Bitfield-Mask: 0x01)                            */
33167  #define R_SPI0_SPCR_MODFEN_Pos      (14UL)         /*!< MODFEN (Bit 14)                                       */
33168  #define R_SPI0_SPCR_MODFEN_Msk      (0x4000UL)     /*!< MODFEN (Bitfield-Mask: 0x01)                          */
33169  #define R_SPI0_SPCR_SPEIE_Pos       (16UL)         /*!< SPEIE (Bit 16)                                        */
33170  #define R_SPI0_SPCR_SPEIE_Msk       (0x10000UL)    /*!< SPEIE (Bitfield-Mask: 0x01)                           */
33171  #define R_SPI0_SPCR_SPRIE_Pos       (17UL)         /*!< SPRIE (Bit 17)                                        */
33172  #define R_SPI0_SPCR_SPRIE_Msk       (0x20000UL)    /*!< SPRIE (Bitfield-Mask: 0x01)                           */
33173  #define R_SPI0_SPCR_SPIIE_Pos       (18UL)         /*!< SPIIE (Bit 18)                                        */
33174  #define R_SPI0_SPCR_SPIIE_Msk       (0x40000UL)    /*!< SPIIE (Bitfield-Mask: 0x01)                           */
33175  #define R_SPI0_SPCR_SPDRES_Pos      (19UL)         /*!< SPDRES (Bit 19)                                       */
33176  #define R_SPI0_SPCR_SPDRES_Msk      (0x80000UL)    /*!< SPDRES (Bitfield-Mask: 0x01)                          */
33177  #define R_SPI0_SPCR_SPTIE_Pos       (20UL)         /*!< SPTIE (Bit 20)                                        */
33178  #define R_SPI0_SPCR_SPTIE_Msk       (0x100000UL)   /*!< SPTIE (Bitfield-Mask: 0x01)                           */
33179  #define R_SPI0_SPCR_CENDIE_Pos      (21UL)         /*!< CENDIE (Bit 21)                                       */
33180  #define R_SPI0_SPCR_CENDIE_Msk      (0x200000UL)   /*!< CENDIE (Bitfield-Mask: 0x01)                          */
33181  #define R_SPI0_SPCR_SPMS_Pos        (24UL)         /*!< SPMS (Bit 24)                                         */
33182  #define R_SPI0_SPCR_SPMS_Msk        (0x1000000UL)  /*!< SPMS (Bitfield-Mask: 0x01)                            */
33183  #define R_SPI0_SPCR_SPFRF_Pos       (25UL)         /*!< SPFRF (Bit 25)                                        */
33184  #define R_SPI0_SPCR_SPFRF_Msk       (0x2000000UL)  /*!< SPFRF (Bitfield-Mask: 0x01)                           */
33185  #define R_SPI0_SPCR_TXMD_Pos        (28UL)         /*!< TXMD (Bit 28)                                         */
33186  #define R_SPI0_SPCR_TXMD_Msk        (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03)                            */
33187  #define R_SPI0_SPCR_MSTR_Pos        (30UL)         /*!< MSTR (Bit 30)                                         */
33188  #define R_SPI0_SPCR_MSTR_Msk        (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01)                            */
33189  #define R_SPI0_SPCR_BPEN_Pos        (31UL)         /*!< BPEN (Bit 31)                                         */
33190  #define R_SPI0_SPCR_BPEN_Msk        (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01)                            */
33191 /* ========================================================  SPCRRM  ========================================================= */
33192  #define R_SPI0_SPCRRM_RMFM_Pos      (0UL)          /*!< RMFM (Bit 0)                                          */
33193  #define R_SPI0_SPCRRM_RMFM_Msk      (0x1fUL)       /*!< RMFM (Bitfield-Mask: 0x1f)                            */
33194  #define R_SPI0_SPCRRM_RMEDTG_Pos    (6UL)          /*!< RMEDTG (Bit 6)                                        */
33195  #define R_SPI0_SPCRRM_RMEDTG_Msk    (0x40UL)       /*!< RMEDTG (Bitfield-Mask: 0x01)                          */
33196  #define R_SPI0_SPCRRM_RMSTTG_Pos    (7UL)          /*!< RMSTTG (Bit 7)                                        */
33197  #define R_SPI0_SPCRRM_RMSTTG_Msk    (0x80UL)       /*!< RMSTTG (Bitfield-Mask: 0x01)                          */
33198 /* ========================================================  SPDRCR  ========================================================= */
33199  #define R_SPI0_SPDRCR_SPDRC_Pos     (0UL)          /*!< SPDRC (Bit 0)                                         */
33200  #define R_SPI0_SPDRCR_SPDRC_Msk     (0xffUL)       /*!< SPDRC (Bitfield-Mask: 0xff)                           */
33201 /* =========================================================  SPPCR  ========================================================= */
33202  #define R_SPI0_SPPCR_SPLP_Pos       (0UL)          /*!< SPLP (Bit 0)                                          */
33203  #define R_SPI0_SPPCR_SPLP_Msk       (0x1UL)        /*!< SPLP (Bitfield-Mask: 0x01)                            */
33204  #define R_SPI0_SPPCR_SPLP2_Pos      (1UL)          /*!< SPLP2 (Bit 1)                                         */
33205  #define R_SPI0_SPPCR_SPLP2_Msk      (0x2UL)        /*!< SPLP2 (Bitfield-Mask: 0x01)                           */
33206  #define R_SPI0_SPPCR_SPOM_Pos       (2UL)          /*!< SPOM (Bit 2)                                          */
33207  #define R_SPI0_SPPCR_SPOM_Msk       (0x4UL)        /*!< SPOM (Bitfield-Mask: 0x01)                            */
33208  #define R_SPI0_SPPCR_MOIFV_Pos      (4UL)          /*!< MOIFV (Bit 4)                                         */
33209  #define R_SPI0_SPPCR_MOIFV_Msk      (0x10UL)       /*!< MOIFV (Bitfield-Mask: 0x01)                           */
33210  #define R_SPI0_SPPCR_MOIFE_Pos      (5UL)          /*!< MOIFE (Bit 5)                                         */
33211  #define R_SPI0_SPPCR_MOIFE_Msk      (0x20UL)       /*!< MOIFE (Bitfield-Mask: 0x01)                           */
33212 /* =========================================================  SPCR2  ========================================================= */
33213  #define R_SPI0_SPCR2_SPSCKDL_Pos    (0UL)          /*!< SPSCKDL (Bit 0)                                       */
33214  #define R_SPI0_SPCR2_SPSCKDL_Msk    (0x7UL)        /*!< SPSCKDL (Bitfield-Mask: 0x07)                         */
33215 /* =========================================================  SSLP  ========================================================== */
33216  #define R_SPI0_SSLP_SSL0P_Pos       (0UL)          /*!< SSL0P (Bit 0)                                         */
33217  #define R_SPI0_SSLP_SSL0P_Msk       (0x1UL)        /*!< SSL0P (Bitfield-Mask: 0x01)                           */
33218  #define R_SPI0_SSLP_SSL1P_Pos       (1UL)          /*!< SSL1P (Bit 1)                                         */
33219  #define R_SPI0_SSLP_SSL1P_Msk       (0x2UL)        /*!< SSL1P (Bitfield-Mask: 0x01)                           */
33220  #define R_SPI0_SSLP_SSL2P_Pos       (2UL)          /*!< SSL2P (Bit 2)                                         */
33221  #define R_SPI0_SSLP_SSL2P_Msk       (0x4UL)        /*!< SSL2P (Bitfield-Mask: 0x01)                           */
33222  #define R_SPI0_SSLP_SSL3P_Pos       (3UL)          /*!< SSL3P (Bit 3)                                         */
33223  #define R_SPI0_SSLP_SSL3P_Msk       (0x8UL)        /*!< SSL3P (Bitfield-Mask: 0x01)                           */
33224 /* =========================================================  SPBR  ========================================================== */
33225  #define R_SPI0_SPBR_SPR_Pos         (0UL)          /*!< SPR (Bit 0)                                           */
33226  #define R_SPI0_SPBR_SPR_Msk         (0xffUL)       /*!< SPR (Bitfield-Mask: 0xff)                             */
33227 /* =========================================================  SPSCR  ========================================================= */
33228  #define R_SPI0_SPSCR_SPSLN_Pos      (0UL)          /*!< SPSLN (Bit 0)                                         */
33229  #define R_SPI0_SPSCR_SPSLN_Msk      (0x7UL)        /*!< SPSLN (Bitfield-Mask: 0x07)                           */
33230 /* =========================================================  SPCMD  ========================================================= */
33231  #define R_SPI0_SPCMD_CPHA_Pos       (0UL)          /*!< CPHA (Bit 0)                                          */
33232  #define R_SPI0_SPCMD_CPHA_Msk       (0x1UL)        /*!< CPHA (Bitfield-Mask: 0x01)                            */
33233  #define R_SPI0_SPCMD_CPOL_Pos       (1UL)          /*!< CPOL (Bit 1)                                          */
33234  #define R_SPI0_SPCMD_CPOL_Msk       (0x2UL)        /*!< CPOL (Bitfield-Mask: 0x01)                            */
33235  #define R_SPI0_SPCMD_BRDV_Pos       (2UL)          /*!< BRDV (Bit 2)                                          */
33236  #define R_SPI0_SPCMD_BRDV_Msk       (0xcUL)        /*!< BRDV (Bitfield-Mask: 0x03)                            */
33237  #define R_SPI0_SPCMD_SSLKP_Pos      (7UL)          /*!< SSLKP (Bit 7)                                         */
33238  #define R_SPI0_SPCMD_SSLKP_Msk      (0x80UL)       /*!< SSLKP (Bitfield-Mask: 0x01)                           */
33239  #define R_SPI0_SPCMD_LSBF_Pos       (12UL)         /*!< LSBF (Bit 12)                                         */
33240  #define R_SPI0_SPCMD_LSBF_Msk       (0x1000UL)     /*!< LSBF (Bitfield-Mask: 0x01)                            */
33241  #define R_SPI0_SPCMD_SPNDEN_Pos     (13UL)         /*!< SPNDEN (Bit 13)                                       */
33242  #define R_SPI0_SPCMD_SPNDEN_Msk     (0x2000UL)     /*!< SPNDEN (Bitfield-Mask: 0x01)                          */
33243  #define R_SPI0_SPCMD_SLNDEN_Pos     (14UL)         /*!< SLNDEN (Bit 14)                                       */
33244  #define R_SPI0_SPCMD_SLNDEN_Msk     (0x4000UL)     /*!< SLNDEN (Bitfield-Mask: 0x01)                          */
33245  #define R_SPI0_SPCMD_SCKDEN_Pos     (15UL)         /*!< SCKDEN (Bit 15)                                       */
33246  #define R_SPI0_SPCMD_SCKDEN_Msk     (0x8000UL)     /*!< SCKDEN (Bitfield-Mask: 0x01)                          */
33247  #define R_SPI0_SPCMD_SPB_Pos        (16UL)         /*!< SPB (Bit 16)                                          */
33248  #define R_SPI0_SPCMD_SPB_Msk        (0x1f0000UL)   /*!< SPB (Bitfield-Mask: 0x1f)                             */
33249  #define R_SPI0_SPCMD_SSLA_Pos       (24UL)         /*!< SSLA (Bit 24)                                         */
33250  #define R_SPI0_SPCMD_SSLA_Msk       (0x3000000UL)  /*!< SSLA (Bitfield-Mask: 0x03)                            */
33251 /* =========================================================  SPDCR  ========================================================= */
33252  #define R_SPI0_SPDCR_BYSW_Pos       (0UL)          /*!< BYSW (Bit 0)                                          */
33253  #define R_SPI0_SPDCR_BYSW_Msk       (0x1UL)        /*!< BYSW (Bitfield-Mask: 0x01)                            */
33254  #define R_SPI0_SPDCR_SLSEL_Pos      (1UL)          /*!< SLSEL (Bit 1)                                         */
33255  #define R_SPI0_SPDCR_SLSEL_Msk      (0x6UL)        /*!< SLSEL (Bitfield-Mask: 0x03)                           */
33256  #define R_SPI0_SPDCR_SPRDTD_Pos     (3UL)          /*!< SPRDTD (Bit 3)                                        */
33257  #define R_SPI0_SPDCR_SPRDTD_Msk     (0x8UL)        /*!< SPRDTD (Bitfield-Mask: 0x01)                          */
33258  #define R_SPI0_SPDCR_SINV_Pos       (4UL)          /*!< SINV (Bit 4)                                          */
33259  #define R_SPI0_SPDCR_SINV_Msk       (0x10UL)       /*!< SINV (Bitfield-Mask: 0x01)                            */
33260  #define R_SPI0_SPDCR_SPFC_Pos       (8UL)          /*!< SPFC (Bit 8)                                          */
33261  #define R_SPI0_SPDCR_SPFC_Msk       (0x300UL)      /*!< SPFC (Bitfield-Mask: 0x03)                            */
33262 /* ========================================================  SPDCR2  ========================================================= */
33263  #define R_SPI0_SPDCR2_RTRG_Pos      (0UL)          /*!< RTRG (Bit 0)                                          */
33264  #define R_SPI0_SPDCR2_RTRG_Msk      (0x3UL)        /*!< RTRG (Bitfield-Mask: 0x03)                            */
33265  #define R_SPI0_SPDCR2_TTRG_Pos      (8UL)          /*!< TTRG (Bit 8)                                          */
33266  #define R_SPI0_SPDCR2_TTRG_Msk      (0x300UL)      /*!< TTRG (Bitfield-Mask: 0x03)                            */
33267 /* =========================================================  SPSSR  ========================================================= */
33268  #define R_SPI0_SPSSR_SPCP_Pos       (0UL)          /*!< SPCP (Bit 0)                                          */
33269  #define R_SPI0_SPSSR_SPCP_Msk       (0x7UL)        /*!< SPCP (Bitfield-Mask: 0x07)                            */
33270  #define R_SPI0_SPSSR_SPECM_Pos      (4UL)          /*!< SPECM (Bit 4)                                         */
33271  #define R_SPI0_SPSSR_SPECM_Msk      (0x70UL)       /*!< SPECM (Bitfield-Mask: 0x07)                           */
33272 /* =========================================================  SPSR  ========================================================== */
33273  #define R_SPI0_SPSR_SPDRF_Pos       (7UL)          /*!< SPDRF (Bit 7)                                         */
33274  #define R_SPI0_SPSR_SPDRF_Msk       (0x80UL)       /*!< SPDRF (Bitfield-Mask: 0x01)                           */
33275  #define R_SPI0_SPSR_OVRF_Pos        (8UL)          /*!< OVRF (Bit 8)                                          */
33276  #define R_SPI0_SPSR_OVRF_Msk        (0x100UL)      /*!< OVRF (Bitfield-Mask: 0x01)                            */
33277  #define R_SPI0_SPSR_IDLNF_Pos       (9UL)          /*!< IDLNF (Bit 9)                                         */
33278  #define R_SPI0_SPSR_IDLNF_Msk       (0x200UL)      /*!< IDLNF (Bitfield-Mask: 0x01)                           */
33279  #define R_SPI0_SPSR_MODF_Pos        (10UL)         /*!< MODF (Bit 10)                                         */
33280  #define R_SPI0_SPSR_MODF_Msk        (0x400UL)      /*!< MODF (Bitfield-Mask: 0x01)                            */
33281  #define R_SPI0_SPSR_PERF_Pos        (11UL)         /*!< PERF (Bit 11)                                         */
33282  #define R_SPI0_SPSR_PERF_Msk        (0x800UL)      /*!< PERF (Bitfield-Mask: 0x01)                            */
33283  #define R_SPI0_SPSR_UDRF_Pos        (12UL)         /*!< UDRF (Bit 12)                                         */
33284  #define R_SPI0_SPSR_UDRF_Msk        (0x1000UL)     /*!< UDRF (Bitfield-Mask: 0x01)                            */
33285  #define R_SPI0_SPSR_SPTEF_Pos       (13UL)         /*!< SPTEF (Bit 13)                                        */
33286  #define R_SPI0_SPSR_SPTEF_Msk       (0x2000UL)     /*!< SPTEF (Bitfield-Mask: 0x01)                           */
33287  #define R_SPI0_SPSR_CENDF_Pos       (14UL)         /*!< CENDF (Bit 14)                                        */
33288  #define R_SPI0_SPSR_CENDF_Msk       (0x4000UL)     /*!< CENDF (Bitfield-Mask: 0x01)                           */
33289  #define R_SPI0_SPSR_SPRF_Pos        (15UL)         /*!< SPRF (Bit 15)                                         */
33290  #define R_SPI0_SPSR_SPRF_Msk        (0x8000UL)     /*!< SPRF (Bitfield-Mask: 0x01)                            */
33291 /* ========================================================  SPTFSR  ========================================================= */
33292  #define R_SPI0_SPTFSR_TFDN_Pos      (0UL)          /*!< TFDN (Bit 0)                                          */
33293  #define R_SPI0_SPTFSR_TFDN_Msk      (0x7UL)        /*!< TFDN (Bitfield-Mask: 0x07)                            */
33294 /* ========================================================  SPRFSR  ========================================================= */
33295  #define R_SPI0_SPRFSR_RFDN_Pos      (0UL)          /*!< RFDN (Bit 0)                                          */
33296  #define R_SPI0_SPRFSR_RFDN_Msk      (0x7UL)        /*!< RFDN (Bitfield-Mask: 0x07)                            */
33297 /* =========================================================  SPPSR  ========================================================= */
33298  #define R_SPI0_SPPSR_SPEPS_Pos      (0UL)          /*!< SPEPS (Bit 0)                                         */
33299  #define R_SPI0_SPPSR_SPEPS_Msk      (0x1UL)        /*!< SPEPS (Bitfield-Mask: 0x01)                           */
33300 /* =========================================================  SPSRC  ========================================================= */
33301  #define R_SPI0_SPSRC_SPDRFC_Pos     (7UL)          /*!< SPDRFC (Bit 7)                                        */
33302  #define R_SPI0_SPSRC_SPDRFC_Msk     (0x80UL)       /*!< SPDRFC (Bitfield-Mask: 0x01)                          */
33303  #define R_SPI0_SPSRC_OVRFC_Pos      (8UL)          /*!< OVRFC (Bit 8)                                         */
33304  #define R_SPI0_SPSRC_OVRFC_Msk      (0x100UL)      /*!< OVRFC (Bitfield-Mask: 0x01)                           */
33305  #define R_SPI0_SPSRC_MODFC_Pos      (10UL)         /*!< MODFC (Bit 10)                                        */
33306  #define R_SPI0_SPSRC_MODFC_Msk      (0x400UL)      /*!< MODFC (Bitfield-Mask: 0x01)                           */
33307  #define R_SPI0_SPSRC_PERFC_Pos      (11UL)         /*!< PERFC (Bit 11)                                        */
33308  #define R_SPI0_SPSRC_PERFC_Msk      (0x800UL)      /*!< PERFC (Bitfield-Mask: 0x01)                           */
33309  #define R_SPI0_SPSRC_UDRFC_Pos      (12UL)         /*!< UDRFC (Bit 12)                                        */
33310  #define R_SPI0_SPSRC_UDRFC_Msk      (0x1000UL)     /*!< UDRFC (Bitfield-Mask: 0x01)                           */
33311  #define R_SPI0_SPSRC_SPTEFC_Pos     (13UL)         /*!< SPTEFC (Bit 13)                                       */
33312  #define R_SPI0_SPSRC_SPTEFC_Msk     (0x2000UL)     /*!< SPTEFC (Bitfield-Mask: 0x01)                          */
33313  #define R_SPI0_SPSRC_CENDFC_Pos     (14UL)         /*!< CENDFC (Bit 14)                                       */
33314  #define R_SPI0_SPSRC_CENDFC_Msk     (0x4000UL)     /*!< CENDFC (Bitfield-Mask: 0x01)                          */
33315  #define R_SPI0_SPSRC_SPRFC_Pos      (15UL)         /*!< SPRFC (Bit 15)                                        */
33316  #define R_SPI0_SPSRC_SPRFC_Msk      (0x8000UL)     /*!< SPRFC (Bitfield-Mask: 0x01)                           */
33317 /* =========================================================  SPFCR  ========================================================= */
33318  #define R_SPI0_SPFCR_SPFRST_Pos     (0UL)          /*!< SPFRST (Bit 0)                                        */
33319  #define R_SPI0_SPFCR_SPFRST_Msk     (0x1UL)        /*!< SPFRST (Bitfield-Mask: 0x01)                          */
33320 
33321 /* =========================================================================================================================== */
33322 /* ================                                          R_CRC0                                           ================ */
33323 /* =========================================================================================================================== */
33324 
33325 /* ========================================================  CRCCR0  ========================================================= */
33326  #define R_CRC0_CRCCR0_GPS_Pos       (0UL)    /*!< GPS (Bit 0)                                           */
33327  #define R_CRC0_CRCCR0_GPS_Msk       (0x7UL)  /*!< GPS (Bitfield-Mask: 0x07)                             */
33328  #define R_CRC0_CRCCR0_LMS_Pos       (6UL)    /*!< LMS (Bit 6)                                           */
33329  #define R_CRC0_CRCCR0_LMS_Msk       (0x40UL) /*!< LMS (Bitfield-Mask: 0x01)                             */
33330  #define R_CRC0_CRCCR0_DORCLR_Pos    (7UL)    /*!< DORCLR (Bit 7)                                        */
33331  #define R_CRC0_CRCCR0_DORCLR_Msk    (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01)                          */
33332 /* ========================================================  CRCDIR  ========================================================= */
33333 /* =======================================================  CRCDIR_BY  ======================================================= */
33334 /* ========================================================  CRCDOR  ========================================================= */
33335 /* =======================================================  CRCDOR_HA  ======================================================= */
33336 /* =======================================================  CRCDOR_BY  ======================================================= */
33337 
33338 /* =========================================================================================================================== */
33339 /* ================                                          R_CANFD                                          ================ */
33340 /* =========================================================================================================================== */
33341 
33342 /* ========================================================  CFDGIPV  ======================================================== */
33343  #define R_CANFD_CFDGIPV_IPV_Pos                 (0UL)          /*!< IPV (Bit 0)                                           */
33344  #define R_CANFD_CFDGIPV_IPV_Msk                 (0xffUL)       /*!< IPV (Bitfield-Mask: 0xff)                             */
33345  #define R_CANFD_CFDGIPV_IPT_Pos                 (8UL)          /*!< IPT (Bit 8)                                           */
33346  #define R_CANFD_CFDGIPV_IPT_Msk                 (0x300UL)      /*!< IPT (Bitfield-Mask: 0x03)                             */
33347  #define R_CANFD_CFDGIPV_PSI_Pos                 (16UL)         /*!< PSI (Bit 16)                                          */
33348  #define R_CANFD_CFDGIPV_PSI_Msk                 (0x3fff0000UL) /*!< PSI (Bitfield-Mask: 0x3fff)                           */
33349 /* ========================================================  CFDGCFG  ======================================================== */
33350  #define R_CANFD_CFDGCFG_TPRI_Pos                (0UL)          /*!< TPRI (Bit 0)                                          */
33351  #define R_CANFD_CFDGCFG_TPRI_Msk                (0x1UL)        /*!< TPRI (Bitfield-Mask: 0x01)                            */
33352  #define R_CANFD_CFDGCFG_DCE_Pos                 (1UL)          /*!< DCE (Bit 1)                                           */
33353  #define R_CANFD_CFDGCFG_DCE_Msk                 (0x2UL)        /*!< DCE (Bitfield-Mask: 0x01)                             */
33354  #define R_CANFD_CFDGCFG_DRE_Pos                 (2UL)          /*!< DRE (Bit 2)                                           */
33355  #define R_CANFD_CFDGCFG_DRE_Msk                 (0x4UL)        /*!< DRE (Bitfield-Mask: 0x01)                             */
33356  #define R_CANFD_CFDGCFG_MME_Pos                 (3UL)          /*!< MME (Bit 3)                                           */
33357  #define R_CANFD_CFDGCFG_MME_Msk                 (0x8UL)        /*!< MME (Bitfield-Mask: 0x01)                             */
33358  #define R_CANFD_CFDGCFG_DCS_Pos                 (4UL)          /*!< DCS (Bit 4)                                           */
33359  #define R_CANFD_CFDGCFG_DCS_Msk                 (0x10UL)       /*!< DCS (Bitfield-Mask: 0x01)                             */
33360  #define R_CANFD_CFDGCFG_CMPOC_Pos               (5UL)          /*!< CMPOC (Bit 5)                                         */
33361  #define R_CANFD_CFDGCFG_CMPOC_Msk               (0x20UL)       /*!< CMPOC (Bitfield-Mask: 0x01)                           */
33362  #define R_CANFD_CFDGCFG_TSP_Pos                 (8UL)          /*!< TSP (Bit 8)                                           */
33363  #define R_CANFD_CFDGCFG_TSP_Msk                 (0xf00UL)      /*!< TSP (Bitfield-Mask: 0x0f)                             */
33364  #define R_CANFD_CFDGCFG_TSSS_Pos                (12UL)         /*!< TSSS (Bit 12)                                         */
33365  #define R_CANFD_CFDGCFG_TSSS_Msk                (0x1000UL)     /*!< TSSS (Bitfield-Mask: 0x01)                            */
33366  #define R_CANFD_CFDGCFG_TSBTCS_Pos              (13UL)         /*!< TSBTCS (Bit 13)                                       */
33367  #define R_CANFD_CFDGCFG_TSBTCS_Msk              (0xe000UL)     /*!< TSBTCS (Bitfield-Mask: 0x07)                          */
33368  #define R_CANFD_CFDGCFG_ITRCP_Pos               (16UL)         /*!< ITRCP (Bit 16)                                        */
33369  #define R_CANFD_CFDGCFG_ITRCP_Msk               (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff)                         */
33370 /* ========================================================  CFDGCTR  ======================================================== */
33371  #define R_CANFD_CFDGCTR_GMDC_Pos                (0UL)          /*!< GMDC (Bit 0)                                          */
33372  #define R_CANFD_CFDGCTR_GMDC_Msk                (0x3UL)        /*!< GMDC (Bitfield-Mask: 0x03)                            */
33373  #define R_CANFD_CFDGCTR_GSLPR_Pos               (2UL)          /*!< GSLPR (Bit 2)                                         */
33374  #define R_CANFD_CFDGCTR_GSLPR_Msk               (0x4UL)        /*!< GSLPR (Bitfield-Mask: 0x01)                           */
33375  #define R_CANFD_CFDGCTR_DEIE_Pos                (8UL)          /*!< DEIE (Bit 8)                                          */
33376  #define R_CANFD_CFDGCTR_DEIE_Msk                (0x100UL)      /*!< DEIE (Bitfield-Mask: 0x01)                            */
33377  #define R_CANFD_CFDGCTR_MEIE_Pos                (9UL)          /*!< MEIE (Bit 9)                                          */
33378  #define R_CANFD_CFDGCTR_MEIE_Msk                (0x200UL)      /*!< MEIE (Bitfield-Mask: 0x01)                            */
33379  #define R_CANFD_CFDGCTR_THLEIE_Pos              (10UL)         /*!< THLEIE (Bit 10)                                       */
33380  #define R_CANFD_CFDGCTR_THLEIE_Msk              (0x400UL)      /*!< THLEIE (Bitfield-Mask: 0x01)                          */
33381  #define R_CANFD_CFDGCTR_CMPOFIE_Pos             (11UL)         /*!< CMPOFIE (Bit 11)                                      */
33382  #define R_CANFD_CFDGCTR_CMPOFIE_Msk             (0x800UL)      /*!< CMPOFIE (Bitfield-Mask: 0x01)                         */
33383  #define R_CANFD_CFDGCTR_QOWEIE_Pos              (12UL)         /*!< QOWEIE (Bit 12)                                       */
33384  #define R_CANFD_CFDGCTR_QOWEIE_Msk              (0x1000UL)     /*!< QOWEIE (Bitfield-Mask: 0x01)                          */
33385  #define R_CANFD_CFDGCTR_QMEIE_Pos               (14UL)         /*!< QMEIE (Bit 14)                                        */
33386  #define R_CANFD_CFDGCTR_QMEIE_Msk               (0x4000UL)     /*!< QMEIE (Bitfield-Mask: 0x01)                           */
33387  #define R_CANFD_CFDGCTR_MOWEIE_Pos              (15UL)         /*!< MOWEIE (Bit 15)                                       */
33388  #define R_CANFD_CFDGCTR_MOWEIE_Msk              (0x8000UL)     /*!< MOWEIE (Bitfield-Mask: 0x01)                          */
33389  #define R_CANFD_CFDGCTR_TSRST_Pos               (16UL)         /*!< TSRST (Bit 16)                                        */
33390  #define R_CANFD_CFDGCTR_TSRST_Msk               (0x10000UL)    /*!< TSRST (Bitfield-Mask: 0x01)                           */
33391 /* ========================================================  CFDGSTS  ======================================================== */
33392  #define R_CANFD_CFDGSTS_GRSTSTS_Pos             (0UL)          /*!< GRSTSTS (Bit 0)                                       */
33393  #define R_CANFD_CFDGSTS_GRSTSTS_Msk             (0x1UL)        /*!< GRSTSTS (Bitfield-Mask: 0x01)                         */
33394  #define R_CANFD_CFDGSTS_GHLTSTS_Pos             (1UL)          /*!< GHLTSTS (Bit 1)                                       */
33395  #define R_CANFD_CFDGSTS_GHLTSTS_Msk             (0x2UL)        /*!< GHLTSTS (Bitfield-Mask: 0x01)                         */
33396  #define R_CANFD_CFDGSTS_GSLPSTS_Pos             (2UL)          /*!< GSLPSTS (Bit 2)                                       */
33397  #define R_CANFD_CFDGSTS_GSLPSTS_Msk             (0x4UL)        /*!< GSLPSTS (Bitfield-Mask: 0x01)                         */
33398  #define R_CANFD_CFDGSTS_GRAMINIT_Pos            (3UL)          /*!< GRAMINIT (Bit 3)                                      */
33399  #define R_CANFD_CFDGSTS_GRAMINIT_Msk            (0x8UL)        /*!< GRAMINIT (Bitfield-Mask: 0x01)                        */
33400 /* =======================================================  CFDGERFL  ======================================================== */
33401  #define R_CANFD_CFDGERFL_DEF_Pos                (0UL)          /*!< DEF (Bit 0)                                           */
33402  #define R_CANFD_CFDGERFL_DEF_Msk                (0x1UL)        /*!< DEF (Bitfield-Mask: 0x01)                             */
33403  #define R_CANFD_CFDGERFL_MES_Pos                (1UL)          /*!< MES (Bit 1)                                           */
33404  #define R_CANFD_CFDGERFL_MES_Msk                (0x2UL)        /*!< MES (Bitfield-Mask: 0x01)                             */
33405  #define R_CANFD_CFDGERFL_THLES_Pos              (2UL)          /*!< THLES (Bit 2)                                         */
33406  #define R_CANFD_CFDGERFL_THLES_Msk              (0x4UL)        /*!< THLES (Bitfield-Mask: 0x01)                           */
33407  #define R_CANFD_CFDGERFL_CMPOF_Pos              (3UL)          /*!< CMPOF (Bit 3)                                         */
33408  #define R_CANFD_CFDGERFL_CMPOF_Msk              (0x8UL)        /*!< CMPOF (Bitfield-Mask: 0x01)                           */
33409  #define R_CANFD_CFDGERFL_QOWES_Pos              (4UL)          /*!< QOWES (Bit 4)                                         */
33410  #define R_CANFD_CFDGERFL_QOWES_Msk              (0x10UL)       /*!< QOWES (Bitfield-Mask: 0x01)                           */
33411  #define R_CANFD_CFDGERFL_QMES_Pos               (6UL)          /*!< QMES (Bit 6)                                          */
33412  #define R_CANFD_CFDGERFL_QMES_Msk               (0x40UL)       /*!< QMES (Bitfield-Mask: 0x01)                            */
33413  #define R_CANFD_CFDGERFL_MOWES_Pos              (7UL)          /*!< MOWES (Bit 7)                                         */
33414  #define R_CANFD_CFDGERFL_MOWES_Msk              (0x80UL)       /*!< MOWES (Bitfield-Mask: 0x01)                           */
33415  #define R_CANFD_CFDGERFL_EEF0_Pos               (16UL)         /*!< EEF0 (Bit 16)                                         */
33416  #define R_CANFD_CFDGERFL_EEF0_Msk               (0x10000UL)    /*!< EEF0 (Bitfield-Mask: 0x01)                            */
33417  #define R_CANFD_CFDGERFL_EEF1_Pos               (17UL)         /*!< EEF1 (Bit 17)                                         */
33418  #define R_CANFD_CFDGERFL_EEF1_Msk               (0x20000UL)    /*!< EEF1 (Bitfield-Mask: 0x01)                            */
33419 /* ========================================================  CFDGTSC  ======================================================== */
33420  #define R_CANFD_CFDGTSC_TS_Pos                  (0UL)          /*!< TS (Bit 0)                                            */
33421  #define R_CANFD_CFDGTSC_TS_Msk                  (0xffffUL)     /*!< TS (Bitfield-Mask: 0xffff)                            */
33422 /* ======================================================  CFDGAFLECTR  ====================================================== */
33423  #define R_CANFD_CFDGAFLECTR_AFLPN_Pos           (0UL)          /*!< AFLPN (Bit 0)                                         */
33424  #define R_CANFD_CFDGAFLECTR_AFLPN_Msk           (0xfUL)        /*!< AFLPN (Bitfield-Mask: 0x0f)                           */
33425  #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos          (8UL)          /*!< AFLDAE (Bit 8)                                        */
33426  #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk          (0x100UL)      /*!< AFLDAE (Bitfield-Mask: 0x01)                          */
33427 /* ======================================================  CFDGAFLCFG0  ====================================================== */
33428  #define R_CANFD_CFDGAFLCFG0_RNC1_Pos            (0UL)          /*!< RNC1 (Bit 0)                                          */
33429  #define R_CANFD_CFDGAFLCFG0_RNC1_Msk            (0x1ffUL)      /*!< RNC1 (Bitfield-Mask: 0x1ff)                           */
33430  #define R_CANFD_CFDGAFLCFG0_RNC0_Pos            (16UL)         /*!< RNC0 (Bit 16)                                         */
33431  #define R_CANFD_CFDGAFLCFG0_RNC0_Msk            (0x1ff0000UL)  /*!< RNC0 (Bitfield-Mask: 0x1ff)                           */
33432 /* ========================================================  CFDRMNB  ======================================================== */
33433  #define R_CANFD_CFDRMNB_NRXMB_Pos               (0UL)          /*!< NRXMB (Bit 0)                                         */
33434  #define R_CANFD_CFDRMNB_NRXMB_Msk               (0xffUL)       /*!< NRXMB (Bitfield-Mask: 0xff)                           */
33435  #define R_CANFD_CFDRMNB_RMPLS_Pos               (8UL)          /*!< RMPLS (Bit 8)                                         */
33436  #define R_CANFD_CFDRMNB_RMPLS_Msk               (0x700UL)      /*!< RMPLS (Bitfield-Mask: 0x07)                           */
33437 /* =======================================================  CFDRMND0  ======================================================== */
33438  #define R_CANFD_CFDRMND0_RMNS_Pos               (0UL)          /*!< RMNS (Bit 0)                                          */
33439  #define R_CANFD_CFDRMND0_RMNS_Msk               (0xffffffffUL) /*!< RMNS (Bitfield-Mask: 0xffffffff)                      */
33440 /* ========================================================  CFDRFCC  ======================================================== */
33441  #define R_CANFD_CFDRFCC_RFE_Pos                 (0UL)          /*!< RFE (Bit 0)                                           */
33442  #define R_CANFD_CFDRFCC_RFE_Msk                 (0x1UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
33443  #define R_CANFD_CFDRFCC_RFIE_Pos                (1UL)          /*!< RFIE (Bit 1)                                          */
33444  #define R_CANFD_CFDRFCC_RFIE_Msk                (0x2UL)        /*!< RFIE (Bitfield-Mask: 0x01)                            */
33445  #define R_CANFD_CFDRFCC_RFPLS_Pos               (4UL)          /*!< RFPLS (Bit 4)                                         */
33446  #define R_CANFD_CFDRFCC_RFPLS_Msk               (0x70UL)       /*!< RFPLS (Bitfield-Mask: 0x07)                           */
33447  #define R_CANFD_CFDRFCC_RFDC_Pos                (8UL)          /*!< RFDC (Bit 8)                                          */
33448  #define R_CANFD_CFDRFCC_RFDC_Msk                (0x700UL)      /*!< RFDC (Bitfield-Mask: 0x07)                            */
33449  #define R_CANFD_CFDRFCC_RFIM_Pos                (12UL)         /*!< RFIM (Bit 12)                                         */
33450  #define R_CANFD_CFDRFCC_RFIM_Msk                (0x1000UL)     /*!< RFIM (Bitfield-Mask: 0x01)                            */
33451  #define R_CANFD_CFDRFCC_RFIGCV_Pos              (13UL)         /*!< RFIGCV (Bit 13)                                       */
33452  #define R_CANFD_CFDRFCC_RFIGCV_Msk              (0xe000UL)     /*!< RFIGCV (Bitfield-Mask: 0x07)                          */
33453  #define R_CANFD_CFDRFCC_RFFIE_Pos               (16UL)         /*!< RFFIE (Bit 16)                                        */
33454  #define R_CANFD_CFDRFCC_RFFIE_Msk               (0x10000UL)    /*!< RFFIE (Bitfield-Mask: 0x01)                           */
33455 /* =======================================================  CFDRFSTS  ======================================================== */
33456  #define R_CANFD_CFDRFSTS_RFEMP_Pos              (0UL)          /*!< RFEMP (Bit 0)                                         */
33457  #define R_CANFD_CFDRFSTS_RFEMP_Msk              (0x1UL)        /*!< RFEMP (Bitfield-Mask: 0x01)                           */
33458  #define R_CANFD_CFDRFSTS_RFFLL_Pos              (1UL)          /*!< RFFLL (Bit 1)                                         */
33459  #define R_CANFD_CFDRFSTS_RFFLL_Msk              (0x2UL)        /*!< RFFLL (Bitfield-Mask: 0x01)                           */
33460  #define R_CANFD_CFDRFSTS_RFMLT_Pos              (2UL)          /*!< RFMLT (Bit 2)                                         */
33461  #define R_CANFD_CFDRFSTS_RFMLT_Msk              (0x4UL)        /*!< RFMLT (Bitfield-Mask: 0x01)                           */
33462  #define R_CANFD_CFDRFSTS_RFIF_Pos               (3UL)          /*!< RFIF (Bit 3)                                          */
33463  #define R_CANFD_CFDRFSTS_RFIF_Msk               (0x8UL)        /*!< RFIF (Bitfield-Mask: 0x01)                            */
33464  #define R_CANFD_CFDRFSTS_RFMC_Pos               (8UL)          /*!< RFMC (Bit 8)                                          */
33465  #define R_CANFD_CFDRFSTS_RFMC_Msk               (0xff00UL)     /*!< RFMC (Bitfield-Mask: 0xff)                            */
33466  #define R_CANFD_CFDRFSTS_RFFIF_Pos              (16UL)         /*!< RFFIF (Bit 16)                                        */
33467  #define R_CANFD_CFDRFSTS_RFFIF_Msk              (0x10000UL)    /*!< RFFIF (Bitfield-Mask: 0x01)                           */
33468 /* =======================================================  CFDRFPCTR  ======================================================= */
33469  #define R_CANFD_CFDRFPCTR_RFPC_Pos              (0UL)          /*!< RFPC (Bit 0)                                          */
33470  #define R_CANFD_CFDRFPCTR_RFPC_Msk              (0xffUL)       /*!< RFPC (Bitfield-Mask: 0xff)                            */
33471 /* ========================================================  CFDCFCC  ======================================================== */
33472  #define R_CANFD_CFDCFCC_CFE_Pos                 (0UL)          /*!< CFE (Bit 0)                                           */
33473  #define R_CANFD_CFDCFCC_CFE_Msk                 (0x1UL)        /*!< CFE (Bitfield-Mask: 0x01)                             */
33474  #define R_CANFD_CFDCFCC_CFRXIE_Pos              (1UL)          /*!< CFRXIE (Bit 1)                                        */
33475  #define R_CANFD_CFDCFCC_CFRXIE_Msk              (0x2UL)        /*!< CFRXIE (Bitfield-Mask: 0x01)                          */
33476  #define R_CANFD_CFDCFCC_CFTXIE_Pos              (2UL)          /*!< CFTXIE (Bit 2)                                        */
33477  #define R_CANFD_CFDCFCC_CFTXIE_Msk              (0x4UL)        /*!< CFTXIE (Bitfield-Mask: 0x01)                          */
33478  #define R_CANFD_CFDCFCC_CFPLS_Pos               (4UL)          /*!< CFPLS (Bit 4)                                         */
33479  #define R_CANFD_CFDCFCC_CFPLS_Msk               (0x70UL)       /*!< CFPLS (Bitfield-Mask: 0x07)                           */
33480  #define R_CANFD_CFDCFCC_CFM_Pos                 (8UL)          /*!< CFM (Bit 8)                                           */
33481  #define R_CANFD_CFDCFCC_CFM_Msk                 (0x300UL)      /*!< CFM (Bitfield-Mask: 0x03)                             */
33482  #define R_CANFD_CFDCFCC_CFITSS_Pos              (10UL)         /*!< CFITSS (Bit 10)                                       */
33483  #define R_CANFD_CFDCFCC_CFITSS_Msk              (0x400UL)      /*!< CFITSS (Bitfield-Mask: 0x01)                          */
33484  #define R_CANFD_CFDCFCC_CFITR_Pos               (11UL)         /*!< CFITR (Bit 11)                                        */
33485  #define R_CANFD_CFDCFCC_CFITR_Msk               (0x800UL)      /*!< CFITR (Bitfield-Mask: 0x01)                           */
33486  #define R_CANFD_CFDCFCC_CFIM_Pos                (12UL)         /*!< CFIM (Bit 12)                                         */
33487  #define R_CANFD_CFDCFCC_CFIM_Msk                (0x1000UL)     /*!< CFIM (Bitfield-Mask: 0x01)                            */
33488  #define R_CANFD_CFDCFCC_CFIGCV_Pos              (13UL)         /*!< CFIGCV (Bit 13)                                       */
33489  #define R_CANFD_CFDCFCC_CFIGCV_Msk              (0xe000UL)     /*!< CFIGCV (Bitfield-Mask: 0x07)                          */
33490  #define R_CANFD_CFDCFCC_CFTML_Pos               (16UL)         /*!< CFTML (Bit 16)                                        */
33491  #define R_CANFD_CFDCFCC_CFTML_Msk               (0x1f0000UL)   /*!< CFTML (Bitfield-Mask: 0x1f)                           */
33492  #define R_CANFD_CFDCFCC_CFDC_Pos                (21UL)         /*!< CFDC (Bit 21)                                         */
33493  #define R_CANFD_CFDCFCC_CFDC_Msk                (0xe00000UL)   /*!< CFDC (Bitfield-Mask: 0x07)                            */
33494  #define R_CANFD_CFDCFCC_CFITT_Pos               (24UL)         /*!< CFITT (Bit 24)                                        */
33495  #define R_CANFD_CFDCFCC_CFITT_Msk               (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff)                           */
33496 /* =======================================================  CFDCFCCE  ======================================================== */
33497  #define R_CANFD_CFDCFCCE_CFFIE_Pos              (0UL)          /*!< CFFIE (Bit 0)                                         */
33498  #define R_CANFD_CFDCFCCE_CFFIE_Msk              (0x1UL)        /*!< CFFIE (Bitfield-Mask: 0x01)                           */
33499  #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos           (1UL)          /*!< CFOFRXIE (Bit 1)                                      */
33500  #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk           (0x2UL)        /*!< CFOFRXIE (Bitfield-Mask: 0x01)                        */
33501  #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos           (2UL)          /*!< CFOFTXIE (Bit 2)                                      */
33502  #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk           (0x4UL)        /*!< CFOFTXIE (Bitfield-Mask: 0x01)                        */
33503  #define R_CANFD_CFDCFCCE_CFMOWM_Pos             (8UL)          /*!< CFMOWM (Bit 8)                                        */
33504  #define R_CANFD_CFDCFCCE_CFMOWM_Msk             (0x100UL)      /*!< CFMOWM (Bitfield-Mask: 0x01)                          */
33505  #define R_CANFD_CFDCFCCE_CFBME_Pos              (16UL)         /*!< CFBME (Bit 16)                                        */
33506  #define R_CANFD_CFDCFCCE_CFBME_Msk              (0x10000UL)    /*!< CFBME (Bitfield-Mask: 0x01)                           */
33507 /* =======================================================  CFDCFSTS  ======================================================== */
33508  #define R_CANFD_CFDCFSTS_CFEMP_Pos              (0UL)          /*!< CFEMP (Bit 0)                                         */
33509  #define R_CANFD_CFDCFSTS_CFEMP_Msk              (0x1UL)        /*!< CFEMP (Bitfield-Mask: 0x01)                           */
33510  #define R_CANFD_CFDCFSTS_CFFLL_Pos              (1UL)          /*!< CFFLL (Bit 1)                                         */
33511  #define R_CANFD_CFDCFSTS_CFFLL_Msk              (0x2UL)        /*!< CFFLL (Bitfield-Mask: 0x01)                           */
33512  #define R_CANFD_CFDCFSTS_CFMLT_Pos              (2UL)          /*!< CFMLT (Bit 2)                                         */
33513  #define R_CANFD_CFDCFSTS_CFMLT_Msk              (0x4UL)        /*!< CFMLT (Bitfield-Mask: 0x01)                           */
33514  #define R_CANFD_CFDCFSTS_CFRXIF_Pos             (3UL)          /*!< CFRXIF (Bit 3)                                        */
33515  #define R_CANFD_CFDCFSTS_CFRXIF_Msk             (0x8UL)        /*!< CFRXIF (Bitfield-Mask: 0x01)                          */
33516  #define R_CANFD_CFDCFSTS_CFTXIF_Pos             (4UL)          /*!< CFTXIF (Bit 4)                                        */
33517  #define R_CANFD_CFDCFSTS_CFTXIF_Msk             (0x10UL)       /*!< CFTXIF (Bitfield-Mask: 0x01)                          */
33518  #define R_CANFD_CFDCFSTS_CFMC_Pos               (8UL)          /*!< CFMC (Bit 8)                                          */
33519  #define R_CANFD_CFDCFSTS_CFMC_Msk               (0xff00UL)     /*!< CFMC (Bitfield-Mask: 0xff)                            */
33520  #define R_CANFD_CFDCFSTS_CFFIF_Pos              (16UL)         /*!< CFFIF (Bit 16)                                        */
33521  #define R_CANFD_CFDCFSTS_CFFIF_Msk              (0x10000UL)    /*!< CFFIF (Bitfield-Mask: 0x01)                           */
33522  #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos           (17UL)         /*!< CFOFRXIF (Bit 17)                                     */
33523  #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk           (0x20000UL)    /*!< CFOFRXIF (Bitfield-Mask: 0x01)                        */
33524  #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos           (18UL)         /*!< CFOFTXIF (Bit 18)                                     */
33525  #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk           (0x40000UL)    /*!< CFOFTXIF (Bitfield-Mask: 0x01)                        */
33526  #define R_CANFD_CFDCFSTS_CFMOW_Pos              (24UL)         /*!< CFMOW (Bit 24)                                        */
33527  #define R_CANFD_CFDCFSTS_CFMOW_Msk              (0x1000000UL)  /*!< CFMOW (Bitfield-Mask: 0x01)                           */
33528 /* =======================================================  CFDCFPCTR  ======================================================= */
33529  #define R_CANFD_CFDCFPCTR_CFPC_Pos              (0UL)          /*!< CFPC (Bit 0)                                          */
33530  #define R_CANFD_CFDCFPCTR_CFPC_Msk              (0xffUL)       /*!< CFPC (Bitfield-Mask: 0xff)                            */
33531 /* =======================================================  CFDFESTS  ======================================================== */
33532  #define R_CANFD_CFDFESTS_RFXEMP_Pos             (0UL)          /*!< RFXEMP (Bit 0)                                        */
33533  #define R_CANFD_CFDFESTS_RFXEMP_Msk             (0xffUL)       /*!< RFXEMP (Bitfield-Mask: 0xff)                          */
33534  #define R_CANFD_CFDFESTS_CFXEMP_Pos             (8UL)          /*!< CFXEMP (Bit 8)                                        */
33535  #define R_CANFD_CFDFESTS_CFXEMP_Msk             (0x3f00UL)     /*!< CFXEMP (Bitfield-Mask: 0x3f)                          */
33536 /* =======================================================  CFDFFSTS  ======================================================== */
33537  #define R_CANFD_CFDFFSTS_RFXFLL_Pos             (0UL)          /*!< RFXFLL (Bit 0)                                        */
33538  #define R_CANFD_CFDFFSTS_RFXFLL_Msk             (0xffUL)       /*!< RFXFLL (Bitfield-Mask: 0xff)                          */
33539  #define R_CANFD_CFDFFSTS_CFXFLL_Pos             (8UL)          /*!< CFXFLL (Bit 8)                                        */
33540  #define R_CANFD_CFDFFSTS_CFXFLL_Msk             (0x3f00UL)     /*!< CFXFLL (Bitfield-Mask: 0x3f)                          */
33541 /* =======================================================  CFDFMSTS  ======================================================== */
33542  #define R_CANFD_CFDFMSTS_RFXMLT_Pos             (0UL)          /*!< RFXMLT (Bit 0)                                        */
33543  #define R_CANFD_CFDFMSTS_RFXMLT_Msk             (0xffUL)       /*!< RFXMLT (Bitfield-Mask: 0xff)                          */
33544  #define R_CANFD_CFDFMSTS_CFXMLT_Pos             (8UL)          /*!< CFXMLT (Bit 8)                                        */
33545  #define R_CANFD_CFDFMSTS_CFXMLT_Msk             (0x3f00UL)     /*!< CFXMLT (Bitfield-Mask: 0x3f)                          */
33546 /* =======================================================  CFDRFISTS  ======================================================= */
33547  #define R_CANFD_CFDRFISTS_RFXIF_Pos             (0UL)          /*!< RFXIF (Bit 0)                                         */
33548  #define R_CANFD_CFDRFISTS_RFXIF_Msk             (0xffUL)       /*!< RFXIF (Bitfield-Mask: 0xff)                           */
33549  #define R_CANFD_CFDRFISTS_RFXFFLL_Pos           (16UL)         /*!< RFXFFLL (Bit 16)                                      */
33550  #define R_CANFD_CFDRFISTS_RFXFFLL_Msk           (0xff0000UL)   /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
33551 /* ======================================================  CFDCFRISTS  ======================================================= */
33552  #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos          (0UL)          /*!< CFXRXIF (Bit 0)                                       */
33553  #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk          (0x3fUL)       /*!< CFXRXIF (Bitfield-Mask: 0x3f)                         */
33554 /* ======================================================  CFDCFTISTS  ======================================================= */
33555  #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos          (0UL)          /*!< CFXTXIF (Bit 0)                                       */
33556  #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk          (0x3fUL)       /*!< CFXTXIF (Bitfield-Mask: 0x3f)                         */
33557 /* =====================================================  CFDCFOFRISTS  ====================================================== */
33558  #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos      (0UL)          /*!< CFXOFRXIF (Bit 0)                                     */
33559  #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk      (0x3fUL)       /*!< CFXOFRXIF (Bitfield-Mask: 0x3f)                       */
33560 /* =====================================================  CFDCFOFTISTS  ====================================================== */
33561  #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos      (0UL)          /*!< CFXOFTXIF (Bit 0)                                     */
33562  #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk      (0x3fUL)       /*!< CFXOFTXIF (Bitfield-Mask: 0x3f)                       */
33563 /* ======================================================  CFDCFMOWSTS  ====================================================== */
33564  #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos          (0UL)          /*!< CFXMOW (Bit 0)                                        */
33565  #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk          (0x3fUL)       /*!< CFXMOW (Bitfield-Mask: 0x3f)                          */
33566 /* =======================================================  CFDFFFSTS  ======================================================= */
33567  #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos           (0UL)          /*!< RFXFFLL (Bit 0)                                       */
33568  #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk           (0xffUL)       /*!< RFXFFLL (Bitfield-Mask: 0xff)                         */
33569  #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos           (8UL)          /*!< CFXFFLL (Bit 8)                                       */
33570  #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk           (0x3f00UL)     /*!< CFXFFLL (Bitfield-Mask: 0x3f)                         */
33571 /* ========================================================  CFDTMC  ========================================================= */
33572  #define R_CANFD_CFDTMC_TMTR_Pos                 (0UL)          /*!< TMTR (Bit 0)                                          */
33573  #define R_CANFD_CFDTMC_TMTR_Msk                 (0x1UL)        /*!< TMTR (Bitfield-Mask: 0x01)                            */
33574  #define R_CANFD_CFDTMC_TMTAR_Pos                (1UL)          /*!< TMTAR (Bit 1)                                         */
33575  #define R_CANFD_CFDTMC_TMTAR_Msk                (0x2UL)        /*!< TMTAR (Bitfield-Mask: 0x01)                           */
33576  #define R_CANFD_CFDTMC_TMOM_Pos                 (2UL)          /*!< TMOM (Bit 2)                                          */
33577  #define R_CANFD_CFDTMC_TMOM_Msk                 (0x4UL)        /*!< TMOM (Bitfield-Mask: 0x01)                            */
33578 /* =======================================================  CFDTMSTS  ======================================================== */
33579  #define R_CANFD_CFDTMSTS_TMTSTS_Pos             (0UL)          /*!< TMTSTS (Bit 0)                                        */
33580  #define R_CANFD_CFDTMSTS_TMTSTS_Msk             (0x1UL)        /*!< TMTSTS (Bitfield-Mask: 0x01)                          */
33581  #define R_CANFD_CFDTMSTS_TMTRF_Pos              (1UL)          /*!< TMTRF (Bit 1)                                         */
33582  #define R_CANFD_CFDTMSTS_TMTRF_Msk              (0x6UL)        /*!< TMTRF (Bitfield-Mask: 0x03)                           */
33583  #define R_CANFD_CFDTMSTS_TMTRM_Pos              (3UL)          /*!< TMTRM (Bit 3)                                         */
33584  #define R_CANFD_CFDTMSTS_TMTRM_Msk              (0x8UL)        /*!< TMTRM (Bitfield-Mask: 0x01)                           */
33585  #define R_CANFD_CFDTMSTS_TMTARM_Pos             (4UL)          /*!< TMTARM (Bit 4)                                        */
33586  #define R_CANFD_CFDTMSTS_TMTARM_Msk             (0x10UL)       /*!< TMTARM (Bitfield-Mask: 0x01)                          */
33587 /* ======================================================  CFDTMTRSTS  ======================================================= */
33588  #define R_CANFD_CFDTMTRSTS_TMTRSTS_Pos          (0UL)          /*!< TMTRSTS (Bit 0)                                       */
33589  #define R_CANFD_CFDTMTRSTS_TMTRSTS_Msk          (0xffffUL)     /*!< TMTRSTS (Bitfield-Mask: 0xffff)                       */
33590 /* ======================================================  CFDTMTARSTS  ====================================================== */
33591  #define R_CANFD_CFDTMTARSTS_TMTARSTS_Pos        (0UL)          /*!< TMTARSTS (Bit 0)                                      */
33592  #define R_CANFD_CFDTMTARSTS_TMTARSTS_Msk        (0xffffUL)     /*!< TMTARSTS (Bitfield-Mask: 0xffff)                      */
33593 /* ======================================================  CFDTMTCSTS  ======================================================= */
33594  #define R_CANFD_CFDTMTCSTS_TMTCSTS_Pos          (0UL)          /*!< TMTCSTS (Bit 0)                                       */
33595  #define R_CANFD_CFDTMTCSTS_TMTCSTS_Msk          (0xffffUL)     /*!< TMTCSTS (Bitfield-Mask: 0xffff)                       */
33596 /* ======================================================  CFDTMTASTS  ======================================================= */
33597  #define R_CANFD_CFDTMTASTS_TMTASTS_Pos          (0UL)          /*!< TMTASTS (Bit 0)                                       */
33598  #define R_CANFD_CFDTMTASTS_TMTASTS_Msk          (0xffffUL)     /*!< TMTASTS (Bitfield-Mask: 0xffff)                       */
33599 /* =======================================================  CFDTMIEC  ======================================================== */
33600  #define R_CANFD_CFDTMIEC_TMIE_Pos               (0UL)          /*!< TMIE (Bit 0)                                          */
33601  #define R_CANFD_CFDTMIEC_TMIE_Msk               (0xffffUL)     /*!< TMIE (Bitfield-Mask: 0xffff)                          */
33602 /* =======================================================  CFDTXQCC0  ======================================================= */
33603  #define R_CANFD_CFDTXQCC0_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
33604  #define R_CANFD_CFDTXQCC0_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
33605  #define R_CANFD_CFDTXQCC0_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
33606  #define R_CANFD_CFDTXQCC0_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
33607  #define R_CANFD_CFDTXQCC0_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
33608  #define R_CANFD_CFDTXQCC0_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
33609  #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
33610  #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
33611  #define R_CANFD_CFDTXQCC0_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
33612  #define R_CANFD_CFDTXQCC0_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
33613  #define R_CANFD_CFDTXQCC0_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
33614  #define R_CANFD_CFDTXQCC0_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
33615  #define R_CANFD_CFDTXQCC0_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
33616  #define R_CANFD_CFDTXQCC0_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
33617  #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
33618  #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
33619  #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
33620  #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
33621 /* ======================================================  CFDTXQSTS0  ======================================================= */
33622  #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
33623  #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
33624  #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
33625  #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
33626  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
33627  #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
33628  #define R_CANFD_CFDTXQSTS0_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
33629  #define R_CANFD_CFDTXQSTS0_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
33630  #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
33631  #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
33632  #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
33633  #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
33634  #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
33635  #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
33636  #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
33637  #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
33638  #define R_CANFD_CFDTXQSTS0_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
33639  #define R_CANFD_CFDTXQSTS0_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
33640 /* ======================================================  CFDTXQPCTR0  ====================================================== */
33641  #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
33642  #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
33643 /* =======================================================  CFDTXQCC1  ======================================================= */
33644  #define R_CANFD_CFDTXQCC1_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
33645  #define R_CANFD_CFDTXQCC1_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
33646  #define R_CANFD_CFDTXQCC1_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
33647  #define R_CANFD_CFDTXQCC1_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
33648  #define R_CANFD_CFDTXQCC1_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
33649  #define R_CANFD_CFDTXQCC1_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
33650  #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
33651  #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
33652  #define R_CANFD_CFDTXQCC1_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
33653  #define R_CANFD_CFDTXQCC1_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
33654  #define R_CANFD_CFDTXQCC1_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
33655  #define R_CANFD_CFDTXQCC1_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
33656  #define R_CANFD_CFDTXQCC1_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
33657  #define R_CANFD_CFDTXQCC1_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
33658  #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
33659  #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
33660  #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
33661  #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
33662 /* ======================================================  CFDTXQSTS1  ======================================================= */
33663  #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
33664  #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
33665  #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
33666  #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
33667  #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
33668  #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
33669  #define R_CANFD_CFDTXQSTS1_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
33670  #define R_CANFD_CFDTXQSTS1_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
33671  #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
33672  #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
33673  #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
33674  #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
33675  #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
33676  #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
33677  #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
33678  #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
33679  #define R_CANFD_CFDTXQSTS1_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
33680  #define R_CANFD_CFDTXQSTS1_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
33681 /* ======================================================  CFDTXQPCTR1  ====================================================== */
33682  #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
33683  #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
33684 /* =======================================================  CFDTXQCC2  ======================================================= */
33685  #define R_CANFD_CFDTXQCC2_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
33686  #define R_CANFD_CFDTXQCC2_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
33687  #define R_CANFD_CFDTXQCC2_TXQGWE_Pos            (1UL)          /*!< TXQGWE (Bit 1)                                        */
33688  #define R_CANFD_CFDTXQCC2_TXQGWE_Msk            (0x2UL)        /*!< TXQGWE (Bitfield-Mask: 0x01)                          */
33689  #define R_CANFD_CFDTXQCC2_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
33690  #define R_CANFD_CFDTXQCC2_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
33691  #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
33692  #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
33693  #define R_CANFD_CFDTXQCC2_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
33694  #define R_CANFD_CFDTXQCC2_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
33695  #define R_CANFD_CFDTXQCC2_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
33696  #define R_CANFD_CFDTXQCC2_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
33697  #define R_CANFD_CFDTXQCC2_TXQFIE_Pos            (16UL)         /*!< TXQFIE (Bit 16)                                       */
33698  #define R_CANFD_CFDTXQCC2_TXQFIE_Msk            (0x10000UL)    /*!< TXQFIE (Bitfield-Mask: 0x01)                          */
33699  #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos         (17UL)         /*!< TXQOFRXIE (Bit 17)                                    */
33700  #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk         (0x20000UL)    /*!< TXQOFRXIE (Bitfield-Mask: 0x01)                       */
33701  #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
33702  #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
33703 /* ======================================================  CFDTXQSTS2  ======================================================= */
33704  #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
33705  #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
33706  #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
33707  #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
33708  #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
33709  #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
33710  #define R_CANFD_CFDTXQSTS2_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
33711  #define R_CANFD_CFDTXQSTS2_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
33712  #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos           (16UL)         /*!< TXQFIF (Bit 16)                                       */
33713  #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk           (0x10000UL)    /*!< TXQFIF (Bitfield-Mask: 0x01)                          */
33714  #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos        (17UL)         /*!< TXQOFRXIF (Bit 17)                                    */
33715  #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk        (0x20000UL)    /*!< TXQOFRXIF (Bitfield-Mask: 0x01)                       */
33716  #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
33717  #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
33718  #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos           (19UL)         /*!< TXQMLT (Bit 19)                                       */
33719  #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk           (0x80000UL)    /*!< TXQMLT (Bitfield-Mask: 0x01)                          */
33720  #define R_CANFD_CFDTXQSTS2_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
33721  #define R_CANFD_CFDTXQSTS2_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
33722 /* ======================================================  CFDTXQPCTR2  ====================================================== */
33723  #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
33724  #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
33725 /* =======================================================  CFDTXQCC3  ======================================================= */
33726  #define R_CANFD_CFDTXQCC3_TXQE_Pos              (0UL)          /*!< TXQE (Bit 0)                                          */
33727  #define R_CANFD_CFDTXQCC3_TXQE_Msk              (0x1UL)        /*!< TXQE (Bitfield-Mask: 0x01)                            */
33728  #define R_CANFD_CFDTXQCC3_TXQOWE_Pos            (2UL)          /*!< TXQOWE (Bit 2)                                        */
33729  #define R_CANFD_CFDTXQCC3_TXQOWE_Msk            (0x4UL)        /*!< TXQOWE (Bitfield-Mask: 0x01)                          */
33730  #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos           (5UL)          /*!< TXQTXIE (Bit 5)                                       */
33731  #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk           (0x20UL)       /*!< TXQTXIE (Bitfield-Mask: 0x01)                         */
33732  #define R_CANFD_CFDTXQCC3_TXQIM_Pos             (7UL)          /*!< TXQIM (Bit 7)                                         */
33733  #define R_CANFD_CFDTXQCC3_TXQIM_Msk             (0x80UL)       /*!< TXQIM (Bitfield-Mask: 0x01)                           */
33734  #define R_CANFD_CFDTXQCC3_TXQDC_Pos             (8UL)          /*!< TXQDC (Bit 8)                                         */
33735  #define R_CANFD_CFDTXQCC3_TXQDC_Msk             (0x1f00UL)     /*!< TXQDC (Bitfield-Mask: 0x1f)                           */
33736  #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos         (18UL)         /*!< TXQOFTXIE (Bit 18)                                    */
33737  #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk         (0x40000UL)    /*!< TXQOFTXIE (Bitfield-Mask: 0x01)                       */
33738 /* ======================================================  CFDTXQSTS3  ======================================================= */
33739  #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos           (0UL)          /*!< TXQEMP (Bit 0)                                        */
33740  #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk           (0x1UL)        /*!< TXQEMP (Bitfield-Mask: 0x01)                          */
33741  #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos           (1UL)          /*!< TXQFLL (Bit 1)                                        */
33742  #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk           (0x2UL)        /*!< TXQFLL (Bitfield-Mask: 0x01)                          */
33743  #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos          (2UL)          /*!< TXQTXIF (Bit 2)                                       */
33744  #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk          (0x4UL)        /*!< TXQTXIF (Bitfield-Mask: 0x01)                         */
33745  #define R_CANFD_CFDTXQSTS3_TXQMC_Pos            (8UL)          /*!< TXQMC (Bit 8)                                         */
33746  #define R_CANFD_CFDTXQSTS3_TXQMC_Msk            (0x3f00UL)     /*!< TXQMC (Bitfield-Mask: 0x3f)                           */
33747  #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos        (18UL)         /*!< TXQOFTXIF (Bit 18)                                    */
33748  #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk        (0x40000UL)    /*!< TXQOFTXIF (Bitfield-Mask: 0x01)                       */
33749  #define R_CANFD_CFDTXQSTS3_TXQMOW_Pos           (20UL)         /*!< TXQMOW (Bit 20)                                       */
33750  #define R_CANFD_CFDTXQSTS3_TXQMOW_Msk           (0x100000UL)   /*!< TXQMOW (Bitfield-Mask: 0x01)                          */
33751 /* ======================================================  CFDTXQPCTR3  ====================================================== */
33752  #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos           (0UL)          /*!< TXQPC (Bit 0)                                         */
33753  #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk           (0xffUL)       /*!< TXQPC (Bitfield-Mask: 0xff)                           */
33754 /* ======================================================  CFDTXQESTS  ======================================================= */
33755  #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos          (0UL)          /*!< TXQxEMP (Bit 0)                                       */
33756  #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk          (0xffUL)       /*!< TXQxEMP (Bitfield-Mask: 0xff)                         */
33757 /* ======================================================  CFDTXQFISTS  ====================================================== */
33758  #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos        (0UL)          /*!< TXQ0FULL (Bit 0)                                      */
33759  #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk        (0x7UL)        /*!< TXQ0FULL (Bitfield-Mask: 0x07)                        */
33760  #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos        (4UL)          /*!< TXQ1FULL (Bit 4)                                      */
33761  #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk        (0x70UL)       /*!< TXQ1FULL (Bitfield-Mask: 0x07)                        */
33762 /* ======================================================  CFDTXQMSTS  ======================================================= */
33763  #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos           (0UL)          /*!< TXQ0ML (Bit 0)                                        */
33764  #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk           (0x7UL)        /*!< TXQ0ML (Bitfield-Mask: 0x07)                          */
33765  #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos           (4UL)          /*!< TXQ1ML (Bit 4)                                        */
33766  #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk           (0x70UL)       /*!< TXQ1ML (Bitfield-Mask: 0x07)                          */
33767 /* ======================================================  CFDTXQISTS  ======================================================= */
33768  #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos          (0UL)          /*!< TXQ0ISF (Bit 0)                                       */
33769  #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk          (0xfUL)        /*!< TXQ0ISF (Bitfield-Mask: 0x0f)                         */
33770  #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos          (4UL)          /*!< TXQ1ISF (Bit 4)                                       */
33771  #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk          (0xf0UL)       /*!< TXQ1ISF (Bitfield-Mask: 0x0f)                         */
33772 /* =====================================================  CFDTXQOFTISTS  ===================================================== */
33773  #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos    (0UL)          /*!< TXQ0OFTISF (Bit 0)                                    */
33774  #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk    (0xfUL)        /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f)                      */
33775  #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos    (4UL)          /*!< TXQ1OFTISF (Bit 4)                                    */
33776  #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk    (0xf0UL)       /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f)                      */
33777 /* =====================================================  CFDTXQOFRISTS  ===================================================== */
33778  #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos    (0UL)          /*!< TXQ0OFRISF (Bit 0)                                    */
33779  #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk    (0x7UL)        /*!< TXQ0OFRISF (Bitfield-Mask: 0x07)                      */
33780  #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos    (4UL)          /*!< TXQ1OFRISF (Bit 4)                                    */
33781  #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk    (0x70UL)       /*!< TXQ1OFRISF (Bitfield-Mask: 0x07)                      */
33782 /* ======================================================  CFDTXQFSTS  ======================================================= */
33783  #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos          (0UL)          /*!< TXQ0FSF (Bit 0)                                       */
33784  #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk          (0xfUL)        /*!< TXQ0FSF (Bitfield-Mask: 0x0f)                         */
33785  #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos          (4UL)          /*!< TXQ1FSF (Bit 4)                                       */
33786  #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk          (0xf0UL)       /*!< TXQ1FSF (Bitfield-Mask: 0x0f)                         */
33787 /* =======================================================  CFDTHLCC  ======================================================== */
33788  #define R_CANFD_CFDTHLCC_THLE_Pos               (0UL)          /*!< THLE (Bit 0)                                          */
33789  #define R_CANFD_CFDTHLCC_THLE_Msk               (0x1UL)        /*!< THLE (Bitfield-Mask: 0x01)                            */
33790  #define R_CANFD_CFDTHLCC_THLIE_Pos              (8UL)          /*!< THLIE (Bit 8)                                         */
33791  #define R_CANFD_CFDTHLCC_THLIE_Msk              (0x100UL)      /*!< THLIE (Bitfield-Mask: 0x01)                           */
33792  #define R_CANFD_CFDTHLCC_THLIM_Pos              (9UL)          /*!< THLIM (Bit 9)                                         */
33793  #define R_CANFD_CFDTHLCC_THLIM_Msk              (0x200UL)      /*!< THLIM (Bitfield-Mask: 0x01)                           */
33794  #define R_CANFD_CFDTHLCC_THLDTE_Pos             (10UL)         /*!< THLDTE (Bit 10)                                       */
33795  #define R_CANFD_CFDTHLCC_THLDTE_Msk             (0x400UL)      /*!< THLDTE (Bitfield-Mask: 0x01)                          */
33796  #define R_CANFD_CFDTHLCC_THLDGE_Pos             (11UL)         /*!< THLDGE (Bit 11)                                       */
33797  #define R_CANFD_CFDTHLCC_THLDGE_Msk             (0x800UL)      /*!< THLDGE (Bitfield-Mask: 0x01)                          */
33798 /* =======================================================  CFDTHLSTS  ======================================================= */
33799  #define R_CANFD_CFDTHLSTS_THLEMP_Pos            (0UL)          /*!< THLEMP (Bit 0)                                        */
33800  #define R_CANFD_CFDTHLSTS_THLEMP_Msk            (0x1UL)        /*!< THLEMP (Bitfield-Mask: 0x01)                          */
33801  #define R_CANFD_CFDTHLSTS_THLFLL_Pos            (1UL)          /*!< THLFLL (Bit 1)                                        */
33802  #define R_CANFD_CFDTHLSTS_THLFLL_Msk            (0x2UL)        /*!< THLFLL (Bitfield-Mask: 0x01)                          */
33803  #define R_CANFD_CFDTHLSTS_THLELT_Pos            (2UL)          /*!< THLELT (Bit 2)                                        */
33804  #define R_CANFD_CFDTHLSTS_THLELT_Msk            (0x4UL)        /*!< THLELT (Bitfield-Mask: 0x01)                          */
33805  #define R_CANFD_CFDTHLSTS_THLIF_Pos             (3UL)          /*!< THLIF (Bit 3)                                         */
33806  #define R_CANFD_CFDTHLSTS_THLIF_Msk             (0x8UL)        /*!< THLIF (Bitfield-Mask: 0x01)                           */
33807  #define R_CANFD_CFDTHLSTS_THLMC_Pos             (8UL)          /*!< THLMC (Bit 8)                                         */
33808  #define R_CANFD_CFDTHLSTS_THLMC_Msk             (0x3f00UL)     /*!< THLMC (Bitfield-Mask: 0x3f)                           */
33809 /* ======================================================  CFDTHLPCTR  ======================================================= */
33810  #define R_CANFD_CFDTHLPCTR_THLPC_Pos            (0UL)          /*!< THLPC (Bit 0)                                         */
33811  #define R_CANFD_CFDTHLPCTR_THLPC_Msk            (0xffUL)       /*!< THLPC (Bitfield-Mask: 0xff)                           */
33812 /* =====================================================  CFDGTINTSTS0  ====================================================== */
33813  #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos          (0UL)          /*!< TSIF0 (Bit 0)                                         */
33814  #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk          (0x1UL)        /*!< TSIF0 (Bitfield-Mask: 0x01)                           */
33815  #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos          (1UL)          /*!< TAIF0 (Bit 1)                                         */
33816  #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk          (0x2UL)        /*!< TAIF0 (Bitfield-Mask: 0x01)                           */
33817  #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos          (2UL)          /*!< TQIF0 (Bit 2)                                         */
33818  #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk          (0x4UL)        /*!< TQIF0 (Bitfield-Mask: 0x01)                           */
33819  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos         (3UL)          /*!< CFTIF0 (Bit 3)                                        */
33820  #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk         (0x8UL)        /*!< CFTIF0 (Bitfield-Mask: 0x01)                          */
33821  #define R_CANFD_CFDGTINTSTS0_THIF0_Pos          (4UL)          /*!< THIF0 (Bit 4)                                         */
33822  #define R_CANFD_CFDGTINTSTS0_THIF0_Msk          (0x10UL)       /*!< THIF0 (Bitfield-Mask: 0x01)                           */
33823  #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos        (5UL)          /*!< TQOFIF0 (Bit 5)                                       */
33824  #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk        (0x20UL)       /*!< TQOFIF0 (Bitfield-Mask: 0x01)                         */
33825  #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos        (6UL)          /*!< CFOTIF0 (Bit 6)                                       */
33826  #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk        (0x40UL)       /*!< CFOTIF0 (Bitfield-Mask: 0x01)                         */
33827  #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos          (8UL)          /*!< TSIF1 (Bit 8)                                         */
33828  #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk          (0x100UL)      /*!< TSIF1 (Bitfield-Mask: 0x01)                           */
33829  #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos          (9UL)          /*!< TAIF1 (Bit 9)                                         */
33830  #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk          (0x200UL)      /*!< TAIF1 (Bitfield-Mask: 0x01)                           */
33831  #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos          (10UL)         /*!< TQIF1 (Bit 10)                                        */
33832  #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk          (0x400UL)      /*!< TQIF1 (Bitfield-Mask: 0x01)                           */
33833  #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos         (11UL)         /*!< CFTIF1 (Bit 11)                                       */
33834  #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk         (0x800UL)      /*!< CFTIF1 (Bitfield-Mask: 0x01)                          */
33835  #define R_CANFD_CFDGTINTSTS0_THIF1_Pos          (12UL)         /*!< THIF1 (Bit 12)                                        */
33836  #define R_CANFD_CFDGTINTSTS0_THIF1_Msk          (0x1000UL)     /*!< THIF1 (Bitfield-Mask: 0x01)                           */
33837  #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos        (13UL)         /*!< TQOFIF1 (Bit 13)                                      */
33838  #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk        (0x2000UL)     /*!< TQOFIF1 (Bitfield-Mask: 0x01)                         */
33839  #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos        (14UL)         /*!< CFOTIF1 (Bit 14)                                      */
33840  #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk        (0x4000UL)     /*!< CFOTIF1 (Bitfield-Mask: 0x01)                         */
33841 /* ======================================================  CFDGTSTCFG  ======================================================= */
33842  #define R_CANFD_CFDGTSTCFG_C0ICBCE_Pos          (0UL)          /*!< C0ICBCE (Bit 0)                                       */
33843  #define R_CANFD_CFDGTSTCFG_C0ICBCE_Msk          (0x1UL)        /*!< C0ICBCE (Bitfield-Mask: 0x01)                         */
33844  #define R_CANFD_CFDGTSTCFG_C1ICBCE_Pos          (1UL)          /*!< C1ICBCE (Bit 1)                                       */
33845  #define R_CANFD_CFDGTSTCFG_C1ICBCE_Msk          (0x2UL)        /*!< C1ICBCE (Bitfield-Mask: 0x01)                         */
33846  #define R_CANFD_CFDGTSTCFG_RTMPS_Pos            (16UL)         /*!< RTMPS (Bit 16)                                        */
33847  #define R_CANFD_CFDGTSTCFG_RTMPS_Msk            (0x3ff0000UL)  /*!< RTMPS (Bitfield-Mask: 0x3ff)                          */
33848 /* ======================================================  CFDGTSTCTR  ======================================================= */
33849  #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos          (0UL)          /*!< ICBCTME (Bit 0)                                       */
33850  #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk          (0x1UL)        /*!< ICBCTME (Bitfield-Mask: 0x01)                         */
33851  #define R_CANFD_CFDGTSTCTR_RTME_Pos             (2UL)          /*!< RTME (Bit 2)                                          */
33852  #define R_CANFD_CFDGTSTCTR_RTME_Msk             (0x4UL)        /*!< RTME (Bitfield-Mask: 0x01)                            */
33853 /* =======================================================  CFDGFDCFG  ======================================================= */
33854  #define R_CANFD_CFDGFDCFG_RPED_Pos              (0UL)          /*!< RPED (Bit 0)                                          */
33855  #define R_CANFD_CFDGFDCFG_RPED_Msk              (0x1UL)        /*!< RPED (Bitfield-Mask: 0x01)                            */
33856  #define R_CANFD_CFDGFDCFG_TSCCFG_Pos            (8UL)          /*!< TSCCFG (Bit 8)                                        */
33857  #define R_CANFD_CFDGFDCFG_TSCCFG_Msk            (0x300UL)      /*!< TSCCFG (Bitfield-Mask: 0x03)                          */
33858 /* =======================================================  CFDGLOCKK  ======================================================= */
33859  #define R_CANFD_CFDGLOCKK_LOCK_Pos              (0UL)          /*!< LOCK (Bit 0)                                          */
33860  #define R_CANFD_CFDGLOCKK_LOCK_Msk              (0xffffUL)     /*!< LOCK (Bitfield-Mask: 0xffff)                          */
33861 /* =======================================================  CFDCDTCT  ======================================================== */
33862  #define R_CANFD_CFDCDTCT_RFDMAE0_Pos            (0UL)          /*!< RFDMAE0 (Bit 0)                                       */
33863  #define R_CANFD_CFDCDTCT_RFDMAE0_Msk            (0x1UL)        /*!< RFDMAE0 (Bitfield-Mask: 0x01)                         */
33864  #define R_CANFD_CFDCDTCT_RFDMAE1_Pos            (1UL)          /*!< RFDMAE1 (Bit 1)                                       */
33865  #define R_CANFD_CFDCDTCT_RFDMAE1_Msk            (0x2UL)        /*!< RFDMAE1 (Bitfield-Mask: 0x01)                         */
33866  #define R_CANFD_CFDCDTCT_RFDMAE2_Pos            (2UL)          /*!< RFDMAE2 (Bit 2)                                       */
33867  #define R_CANFD_CFDCDTCT_RFDMAE2_Msk            (0x4UL)        /*!< RFDMAE2 (Bitfield-Mask: 0x01)                         */
33868  #define R_CANFD_CFDCDTCT_RFDMAE3_Pos            (3UL)          /*!< RFDMAE3 (Bit 3)                                       */
33869  #define R_CANFD_CFDCDTCT_RFDMAE3_Msk            (0x8UL)        /*!< RFDMAE3 (Bitfield-Mask: 0x01)                         */
33870  #define R_CANFD_CFDCDTCT_RFDMAE4_Pos            (4UL)          /*!< RFDMAE4 (Bit 4)                                       */
33871  #define R_CANFD_CFDCDTCT_RFDMAE4_Msk            (0x10UL)       /*!< RFDMAE4 (Bitfield-Mask: 0x01)                         */
33872  #define R_CANFD_CFDCDTCT_RFDMAE5_Pos            (5UL)          /*!< RFDMAE5 (Bit 5)                                       */
33873  #define R_CANFD_CFDCDTCT_RFDMAE5_Msk            (0x20UL)       /*!< RFDMAE5 (Bitfield-Mask: 0x01)                         */
33874  #define R_CANFD_CFDCDTCT_RFDMAE6_Pos            (6UL)          /*!< RFDMAE6 (Bit 6)                                       */
33875  #define R_CANFD_CFDCDTCT_RFDMAE6_Msk            (0x40UL)       /*!< RFDMAE6 (Bitfield-Mask: 0x01)                         */
33876  #define R_CANFD_CFDCDTCT_RFDMAE7_Pos            (7UL)          /*!< RFDMAE7 (Bit 7)                                       */
33877  #define R_CANFD_CFDCDTCT_RFDMAE7_Msk            (0x80UL)       /*!< RFDMAE7 (Bitfield-Mask: 0x01)                         */
33878  #define R_CANFD_CFDCDTCT_CFDMAE0_Pos            (8UL)          /*!< CFDMAE0 (Bit 8)                                       */
33879  #define R_CANFD_CFDCDTCT_CFDMAE0_Msk            (0x100UL)      /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
33880  #define R_CANFD_CFDCDTCT_CFDMAE1_Pos            (9UL)          /*!< CFDMAE1 (Bit 9)                                       */
33881  #define R_CANFD_CFDCDTCT_CFDMAE1_Msk            (0x200UL)      /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
33882 /* =======================================================  CFDCDTSTS  ======================================================= */
33883  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos         (0UL)          /*!< RFDMASTS0 (Bit 0)                                     */
33884  #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk         (0x1UL)        /*!< RFDMASTS0 (Bitfield-Mask: 0x01)                       */
33885  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos         (1UL)          /*!< RFDMASTS1 (Bit 1)                                     */
33886  #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk         (0x2UL)        /*!< RFDMASTS1 (Bitfield-Mask: 0x01)                       */
33887  #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos         (2UL)          /*!< RFDMASTS2 (Bit 2)                                     */
33888  #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk         (0x4UL)        /*!< RFDMASTS2 (Bitfield-Mask: 0x01)                       */
33889  #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos         (3UL)          /*!< RFDMASTS3 (Bit 3)                                     */
33890  #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk         (0x8UL)        /*!< RFDMASTS3 (Bitfield-Mask: 0x01)                       */
33891  #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos         (4UL)          /*!< RFDMASTS4 (Bit 4)                                     */
33892  #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk         (0x10UL)       /*!< RFDMASTS4 (Bitfield-Mask: 0x01)                       */
33893  #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos         (5UL)          /*!< RFDMASTS5 (Bit 5)                                     */
33894  #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk         (0x20UL)       /*!< RFDMASTS5 (Bitfield-Mask: 0x01)                       */
33895  #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos         (6UL)          /*!< RFDMASTS6 (Bit 6)                                     */
33896  #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk         (0x40UL)       /*!< RFDMASTS6 (Bitfield-Mask: 0x01)                       */
33897  #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos         (7UL)          /*!< RFDMASTS7 (Bit 7)                                     */
33898  #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk         (0x80UL)       /*!< RFDMASTS7 (Bitfield-Mask: 0x01)                       */
33899  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos         (8UL)          /*!< CFDMASTS0 (Bit 8)                                     */
33900  #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk         (0x100UL)      /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
33901  #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos         (9UL)          /*!< CFDMASTS1 (Bit 9)                                     */
33902  #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk         (0x200UL)      /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
33903 /* =======================================================  CFDCDTTCT  ======================================================= */
33904  #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos          (0UL)          /*!< TQ0DMAE0 (Bit 0)                                      */
33905  #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk          (0x1UL)        /*!< TQ0DMAE0 (Bitfield-Mask: 0x01)                        */
33906  #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos          (1UL)          /*!< TQ0DMAE1 (Bit 1)                                      */
33907  #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk          (0x2UL)        /*!< TQ0DMAE1 (Bitfield-Mask: 0x01)                        */
33908  #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos          (8UL)          /*!< TQ3DMAE0 (Bit 8)                                      */
33909  #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk          (0x100UL)      /*!< TQ3DMAE0 (Bitfield-Mask: 0x01)                        */
33910  #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos          (9UL)          /*!< TQ3DMAE1 (Bit 9)                                      */
33911  #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk          (0x200UL)      /*!< TQ3DMAE1 (Bitfield-Mask: 0x01)                        */
33912  #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos           (16UL)         /*!< CFDMAE0 (Bit 16)                                      */
33913  #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk           (0x10000UL)    /*!< CFDMAE0 (Bitfield-Mask: 0x01)                         */
33914  #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos           (17UL)         /*!< CFDMAE1 (Bit 17)                                      */
33915  #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk           (0x20000UL)    /*!< CFDMAE1 (Bitfield-Mask: 0x01)                         */
33916 /* ======================================================  CFDCDTTSTS  ======================================================= */
33917  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos       (0UL)          /*!< TQ0DMASTS0 (Bit 0)                                    */
33918  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk       (0x1UL)        /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01)                      */
33919  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos       (1UL)          /*!< TQ0DMASTS1 (Bit 1)                                    */
33920  #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk       (0x2UL)        /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01)                      */
33921  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos       (8UL)          /*!< TQ3DMASTS0 (Bit 8)                                    */
33922  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk       (0x100UL)      /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01)                      */
33923  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos       (9UL)          /*!< TQ3DMASTS1 (Bit 9)                                    */
33924  #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk       (0x200UL)      /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01)                      */
33925  #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos        (16UL)         /*!< CFDMASTS0 (Bit 16)                                    */
33926  #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk        (0x10000UL)    /*!< CFDMASTS0 (Bitfield-Mask: 0x01)                       */
33927  #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos        (17UL)         /*!< CFDMASTS1 (Bit 17)                                    */
33928  #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk        (0x20000UL)    /*!< CFDMASTS1 (Bitfield-Mask: 0x01)                       */
33929 /* ======================================================  CFDGRINTSTS  ====================================================== */
33930  #define R_CANFD_CFDGRINTSTS_QFIF_Pos            (0UL)          /*!< QFIF (Bit 0)                                          */
33931  #define R_CANFD_CFDGRINTSTS_QFIF_Msk            (0x7UL)        /*!< QFIF (Bitfield-Mask: 0x07)                            */
33932  #define R_CANFD_CFDGRINTSTS_BQFIF_Pos           (4UL)          /*!< BQFIF (Bit 4)                                         */
33933  #define R_CANFD_CFDGRINTSTS_BQFIF_Msk           (0x30UL)       /*!< BQFIF (Bitfield-Mask: 0x03)                           */
33934  #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos          (8UL)          /*!< QOFRIF (Bit 8)                                        */
33935  #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk          (0x700UL)      /*!< QOFRIF (Bitfield-Mask: 0x07)                          */
33936  #define R_CANFD_CFDGRINTSTS_BQOFRIF_Pos         (12UL)         /*!< BQOFRIF (Bit 12)                                      */
33937  #define R_CANFD_CFDGRINTSTS_BQOFRIF_Msk         (0x3000UL)     /*!< BQOFRIF (Bitfield-Mask: 0x03)                         */
33938  #define R_CANFD_CFDGRINTSTS_CFRIF_Pos           (16UL)         /*!< CFRIF (Bit 16)                                        */
33939  #define R_CANFD_CFDGRINTSTS_CFRIF_Msk           (0x70000UL)    /*!< CFRIF (Bitfield-Mask: 0x07)                           */
33940  #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos          (24UL)         /*!< CFRFIF (Bit 24)                                       */
33941  #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk          (0x7000000UL)  /*!< CFRFIF (Bitfield-Mask: 0x07)                          */
33942  #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos         (28UL)         /*!< CFOFRIF (Bit 28)                                      */
33943  #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk         (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07)                         */
33944 /* =======================================================  CFDGRSTC  ======================================================== */
33945  #define R_CANFD_CFDGRSTC_SRST_Pos               (0UL)          /*!< SRST (Bit 0)                                          */
33946  #define R_CANFD_CFDGRSTC_SRST_Msk               (0x1UL)        /*!< SRST (Bitfield-Mask: 0x01)                            */
33947  #define R_CANFD_CFDGRSTC_KEY_Pos                (8UL)          /*!< KEY (Bit 8)                                           */
33948  #define R_CANFD_CFDGRSTC_KEY_Msk                (0xff00UL)     /*!< KEY (Bitfield-Mask: 0xff)                             */
33949 /* =======================================================  CFDGFCMC  ======================================================== */
33950  #define R_CANFD_CFDGFCMC_FLXC0_Pos              (0UL)          /*!< FLXC0 (Bit 0)                                         */
33951  #define R_CANFD_CFDGFCMC_FLXC0_Msk              (0x1UL)        /*!< FLXC0 (Bitfield-Mask: 0x01)                           */
33952 /* =======================================================  CFDGFTBAC  ======================================================= */
33953  #define R_CANFD_CFDGFTBAC_FLXMB0_Pos            (0UL)          /*!< FLXMB0 (Bit 0)                                        */
33954  #define R_CANFD_CFDGFTBAC_FLXMB0_Msk            (0xfUL)        /*!< FLXMB0 (Bitfield-Mask: 0x0f)                          */
33955 /* =======================================================  CFDRPGACC  ======================================================= */
33956  #define R_CANFD_CFDRPGACC_RDTA_Pos              (0UL)          /*!< RDTA (Bit 0)                                          */
33957  #define R_CANFD_CFDRPGACC_RDTA_Msk              (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff)                      */
33958 
33959 /* =========================================================================================================================== */
33960 /* ================                                           R_CMT                                           ================ */
33961 /* =========================================================================================================================== */
33962 
33963 /* =========================================================================================================================== */
33964 /* ================                                          R_CMTW0                                          ================ */
33965 /* =========================================================================================================================== */
33966 
33967 /* ========================================================  CMWSTR  ========================================================= */
33968  #define R_CMTW0_CMWSTR_STR_Pos     (0UL)      /*!< STR (Bit 0)                                           */
33969  #define R_CMTW0_CMWSTR_STR_Msk     (0x1UL)    /*!< STR (Bitfield-Mask: 0x01)                             */
33970 /* =========================================================  CMWCR  ========================================================= */
33971  #define R_CMTW0_CMWCR_CKS_Pos      (0UL)      /*!< CKS (Bit 0)                                           */
33972  #define R_CMTW0_CMWCR_CKS_Msk      (0x3UL)    /*!< CKS (Bitfield-Mask: 0x03)                             */
33973  #define R_CMTW0_CMWCR_CMWIE_Pos    (3UL)      /*!< CMWIE (Bit 3)                                         */
33974  #define R_CMTW0_CMWCR_CMWIE_Msk    (0x8UL)    /*!< CMWIE (Bitfield-Mask: 0x01)                           */
33975  #define R_CMTW0_CMWCR_IC0IE_Pos    (4UL)      /*!< IC0IE (Bit 4)                                         */
33976  #define R_CMTW0_CMWCR_IC0IE_Msk    (0x10UL)   /*!< IC0IE (Bitfield-Mask: 0x01)                           */
33977  #define R_CMTW0_CMWCR_IC1IE_Pos    (5UL)      /*!< IC1IE (Bit 5)                                         */
33978  #define R_CMTW0_CMWCR_IC1IE_Msk    (0x20UL)   /*!< IC1IE (Bitfield-Mask: 0x01)                           */
33979  #define R_CMTW0_CMWCR_OC0IE_Pos    (6UL)      /*!< OC0IE (Bit 6)                                         */
33980  #define R_CMTW0_CMWCR_OC0IE_Msk    (0x40UL)   /*!< OC0IE (Bitfield-Mask: 0x01)                           */
33981  #define R_CMTW0_CMWCR_OC1IE_Pos    (7UL)      /*!< OC1IE (Bit 7)                                         */
33982  #define R_CMTW0_CMWCR_OC1IE_Msk    (0x80UL)   /*!< OC1IE (Bitfield-Mask: 0x01)                           */
33983  #define R_CMTW0_CMWCR_CMS_Pos      (9UL)      /*!< CMS (Bit 9)                                           */
33984  #define R_CMTW0_CMWCR_CMS_Msk      (0x200UL)  /*!< CMS (Bitfield-Mask: 0x01)                             */
33985  #define R_CMTW0_CMWCR_CCLR_Pos     (13UL)     /*!< CCLR (Bit 13)                                         */
33986  #define R_CMTW0_CMWCR_CCLR_Msk     (0xe000UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
33987 /* ========================================================  CMWIOR  ========================================================= */
33988  #define R_CMTW0_CMWIOR_IC0_Pos     (0UL)      /*!< IC0 (Bit 0)                                           */
33989  #define R_CMTW0_CMWIOR_IC0_Msk     (0x3UL)    /*!< IC0 (Bitfield-Mask: 0x03)                             */
33990  #define R_CMTW0_CMWIOR_IC1_Pos     (2UL)      /*!< IC1 (Bit 2)                                           */
33991  #define R_CMTW0_CMWIOR_IC1_Msk     (0xcUL)    /*!< IC1 (Bitfield-Mask: 0x03)                             */
33992  #define R_CMTW0_CMWIOR_IC0E_Pos    (4UL)      /*!< IC0E (Bit 4)                                          */
33993  #define R_CMTW0_CMWIOR_IC0E_Msk    (0x10UL)   /*!< IC0E (Bitfield-Mask: 0x01)                            */
33994  #define R_CMTW0_CMWIOR_IC1E_Pos    (5UL)      /*!< IC1E (Bit 5)                                          */
33995  #define R_CMTW0_CMWIOR_IC1E_Msk    (0x20UL)   /*!< IC1E (Bitfield-Mask: 0x01)                            */
33996  #define R_CMTW0_CMWIOR_OC0_Pos     (8UL)      /*!< OC0 (Bit 8)                                           */
33997  #define R_CMTW0_CMWIOR_OC0_Msk     (0x300UL)  /*!< OC0 (Bitfield-Mask: 0x03)                             */
33998  #define R_CMTW0_CMWIOR_OC1_Pos     (10UL)     /*!< OC1 (Bit 10)                                          */
33999  #define R_CMTW0_CMWIOR_OC1_Msk     (0xc00UL)  /*!< OC1 (Bitfield-Mask: 0x03)                             */
34000  #define R_CMTW0_CMWIOR_OC0E_Pos    (12UL)     /*!< OC0E (Bit 12)                                         */
34001  #define R_CMTW0_CMWIOR_OC0E_Msk    (0x1000UL) /*!< OC0E (Bitfield-Mask: 0x01)                            */
34002  #define R_CMTW0_CMWIOR_OC1E_Pos    (13UL)     /*!< OC1E (Bit 13)                                         */
34003  #define R_CMTW0_CMWIOR_OC1E_Msk    (0x2000UL) /*!< OC1E (Bitfield-Mask: 0x01)                            */
34004  #define R_CMTW0_CMWIOR_CMWE_Pos    (15UL)     /*!< CMWE (Bit 15)                                         */
34005  #define R_CMTW0_CMWIOR_CMWE_Msk    (0x8000UL) /*!< CMWE (Bitfield-Mask: 0x01)                            */
34006 /* ========================================================  CMWCNT  ========================================================= */
34007 /* ========================================================  CMWCOR  ========================================================= */
34008 /* ========================================================  CMWICR0  ======================================================== */
34009 /* ========================================================  CMWICR1  ======================================================== */
34010 /* ========================================================  CMWOCR0  ======================================================== */
34011 /* ========================================================  CMWOCR1  ======================================================== */
34012 
34013 /* =========================================================================================================================== */
34014 /* ================                                          R_WDT0                                           ================ */
34015 /* =========================================================================================================================== */
34016 
34017 /* =========================================================  WDTRR  ========================================================= */
34018 /* =========================================================  WDTCR  ========================================================= */
34019  #define R_WDT0_WDTCR_TOPS_Pos        (0UL)      /*!< TOPS (Bit 0)                                          */
34020  #define R_WDT0_WDTCR_TOPS_Msk        (0x3UL)    /*!< TOPS (Bitfield-Mask: 0x03)                            */
34021  #define R_WDT0_WDTCR_CKS_Pos         (4UL)      /*!< CKS (Bit 4)                                           */
34022  #define R_WDT0_WDTCR_CKS_Msk         (0xf0UL)   /*!< CKS (Bitfield-Mask: 0x0f)                             */
34023  #define R_WDT0_WDTCR_RPES_Pos        (8UL)      /*!< RPES (Bit 8)                                          */
34024  #define R_WDT0_WDTCR_RPES_Msk        (0x300UL)  /*!< RPES (Bitfield-Mask: 0x03)                            */
34025  #define R_WDT0_WDTCR_RPSS_Pos        (12UL)     /*!< RPSS (Bit 12)                                         */
34026  #define R_WDT0_WDTCR_RPSS_Msk        (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03)                            */
34027 /* =========================================================  WDTSR  ========================================================= */
34028  #define R_WDT0_WDTSR_CNTVAL_Pos      (0UL)      /*!< CNTVAL (Bit 0)                                        */
34029  #define R_WDT0_WDTSR_CNTVAL_Msk      (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff)                        */
34030  #define R_WDT0_WDTSR_UNDFF_Pos       (14UL)     /*!< UNDFF (Bit 14)                                        */
34031  #define R_WDT0_WDTSR_UNDFF_Msk       (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01)                           */
34032  #define R_WDT0_WDTSR_REFEF_Pos       (15UL)     /*!< REFEF (Bit 15)                                        */
34033  #define R_WDT0_WDTSR_REFEF_Msk       (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01)                           */
34034 /* ========================================================  WDTRCR  ========================================================= */
34035  #define R_WDT0_WDTRCR_RSTIRQS_Pos    (7UL)      /*!< RSTIRQS (Bit 7)                                       */
34036  #define R_WDT0_WDTRCR_RSTIRQS_Msk    (0x80UL)   /*!< RSTIRQS (Bitfield-Mask: 0x01)                         */
34037 
34038 /* =========================================================================================================================== */
34039 /* ================                                          R_IIC0                                           ================ */
34040 /* =========================================================================================================================== */
34041 
34042 /* =========================================================  ICCR1  ========================================================= */
34043  #define R_IIC0_ICCR1_SDAI_Pos      (0UL)    /*!< SDAI (Bit 0)                                          */
34044  #define R_IIC0_ICCR1_SDAI_Msk      (0x1UL)  /*!< SDAI (Bitfield-Mask: 0x01)                            */
34045  #define R_IIC0_ICCR1_SCLI_Pos      (1UL)    /*!< SCLI (Bit 1)                                          */
34046  #define R_IIC0_ICCR1_SCLI_Msk      (0x2UL)  /*!< SCLI (Bitfield-Mask: 0x01)                            */
34047  #define R_IIC0_ICCR1_SDAO_Pos      (2UL)    /*!< SDAO (Bit 2)                                          */
34048  #define R_IIC0_ICCR1_SDAO_Msk      (0x4UL)  /*!< SDAO (Bitfield-Mask: 0x01)                            */
34049  #define R_IIC0_ICCR1_SCLO_Pos      (3UL)    /*!< SCLO (Bit 3)                                          */
34050  #define R_IIC0_ICCR1_SCLO_Msk      (0x8UL)  /*!< SCLO (Bitfield-Mask: 0x01)                            */
34051  #define R_IIC0_ICCR1_SOWP_Pos      (4UL)    /*!< SOWP (Bit 4)                                          */
34052  #define R_IIC0_ICCR1_SOWP_Msk      (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01)                            */
34053  #define R_IIC0_ICCR1_CLO_Pos       (5UL)    /*!< CLO (Bit 5)                                           */
34054  #define R_IIC0_ICCR1_CLO_Msk       (0x20UL) /*!< CLO (Bitfield-Mask: 0x01)                             */
34055  #define R_IIC0_ICCR1_IICRST_Pos    (6UL)    /*!< IICRST (Bit 6)                                        */
34056  #define R_IIC0_ICCR1_IICRST_Msk    (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01)                          */
34057  #define R_IIC0_ICCR1_ICE_Pos       (7UL)    /*!< ICE (Bit 7)                                           */
34058  #define R_IIC0_ICCR1_ICE_Msk       (0x80UL) /*!< ICE (Bitfield-Mask: 0x01)                             */
34059 /* =========================================================  ICCR2  ========================================================= */
34060  #define R_IIC0_ICCR2_ST_Pos        (1UL)    /*!< ST (Bit 1)                                            */
34061  #define R_IIC0_ICCR2_ST_Msk        (0x2UL)  /*!< ST (Bitfield-Mask: 0x01)                              */
34062  #define R_IIC0_ICCR2_RS_Pos        (2UL)    /*!< RS (Bit 2)                                            */
34063  #define R_IIC0_ICCR2_RS_Msk        (0x4UL)  /*!< RS (Bitfield-Mask: 0x01)                              */
34064  #define R_IIC0_ICCR2_SP_Pos        (3UL)    /*!< SP (Bit 3)                                            */
34065  #define R_IIC0_ICCR2_SP_Msk        (0x8UL)  /*!< SP (Bitfield-Mask: 0x01)                              */
34066  #define R_IIC0_ICCR2_TRS_Pos       (5UL)    /*!< TRS (Bit 5)                                           */
34067  #define R_IIC0_ICCR2_TRS_Msk       (0x20UL) /*!< TRS (Bitfield-Mask: 0x01)                             */
34068  #define R_IIC0_ICCR2_MST_Pos       (6UL)    /*!< MST (Bit 6)                                           */
34069  #define R_IIC0_ICCR2_MST_Msk       (0x40UL) /*!< MST (Bitfield-Mask: 0x01)                             */
34070  #define R_IIC0_ICCR2_BBSY_Pos      (7UL)    /*!< BBSY (Bit 7)                                          */
34071  #define R_IIC0_ICCR2_BBSY_Msk      (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01)                            */
34072 /* =========================================================  ICMR1  ========================================================= */
34073  #define R_IIC0_ICMR1_BC_Pos        (0UL)    /*!< BC (Bit 0)                                            */
34074  #define R_IIC0_ICMR1_BC_Msk        (0x7UL)  /*!< BC (Bitfield-Mask: 0x07)                              */
34075  #define R_IIC0_ICMR1_BCWP_Pos      (3UL)    /*!< BCWP (Bit 3)                                          */
34076  #define R_IIC0_ICMR1_BCWP_Msk      (0x8UL)  /*!< BCWP (Bitfield-Mask: 0x01)                            */
34077  #define R_IIC0_ICMR1_CKS_Pos       (4UL)    /*!< CKS (Bit 4)                                           */
34078  #define R_IIC0_ICMR1_CKS_Msk       (0x70UL) /*!< CKS (Bitfield-Mask: 0x07)                             */
34079  #define R_IIC0_ICMR1_MTWP_Pos      (7UL)    /*!< MTWP (Bit 7)                                          */
34080  #define R_IIC0_ICMR1_MTWP_Msk      (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01)                            */
34081 /* =========================================================  ICMR2  ========================================================= */
34082  #define R_IIC0_ICMR2_TMOS_Pos      (0UL)    /*!< TMOS (Bit 0)                                          */
34083  #define R_IIC0_ICMR2_TMOS_Msk      (0x1UL)  /*!< TMOS (Bitfield-Mask: 0x01)                            */
34084  #define R_IIC0_ICMR2_TMOL_Pos      (1UL)    /*!< TMOL (Bit 1)                                          */
34085  #define R_IIC0_ICMR2_TMOL_Msk      (0x2UL)  /*!< TMOL (Bitfield-Mask: 0x01)                            */
34086  #define R_IIC0_ICMR2_TMOH_Pos      (2UL)    /*!< TMOH (Bit 2)                                          */
34087  #define R_IIC0_ICMR2_TMOH_Msk      (0x4UL)  /*!< TMOH (Bitfield-Mask: 0x01)                            */
34088  #define R_IIC0_ICMR2_SDDL_Pos      (4UL)    /*!< SDDL (Bit 4)                                          */
34089  #define R_IIC0_ICMR2_SDDL_Msk      (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07)                            */
34090  #define R_IIC0_ICMR2_DLCS_Pos      (7UL)    /*!< DLCS (Bit 7)                                          */
34091  #define R_IIC0_ICMR2_DLCS_Msk      (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01)                            */
34092 /* =========================================================  ICMR3  ========================================================= */
34093  #define R_IIC0_ICMR3_NF_Pos        (0UL)    /*!< NF (Bit 0)                                            */
34094  #define R_IIC0_ICMR3_NF_Msk        (0x3UL)  /*!< NF (Bitfield-Mask: 0x03)                              */
34095  #define R_IIC0_ICMR3_ACKBR_Pos     (2UL)    /*!< ACKBR (Bit 2)                                         */
34096  #define R_IIC0_ICMR3_ACKBR_Msk     (0x4UL)  /*!< ACKBR (Bitfield-Mask: 0x01)                           */
34097  #define R_IIC0_ICMR3_ACKBT_Pos     (3UL)    /*!< ACKBT (Bit 3)                                         */
34098  #define R_IIC0_ICMR3_ACKBT_Msk     (0x8UL)  /*!< ACKBT (Bitfield-Mask: 0x01)                           */
34099  #define R_IIC0_ICMR3_ACKWP_Pos     (4UL)    /*!< ACKWP (Bit 4)                                         */
34100  #define R_IIC0_ICMR3_ACKWP_Msk     (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01)                           */
34101  #define R_IIC0_ICMR3_RDRFS_Pos     (5UL)    /*!< RDRFS (Bit 5)                                         */
34102  #define R_IIC0_ICMR3_RDRFS_Msk     (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01)                           */
34103  #define R_IIC0_ICMR3_WAIT_Pos      (6UL)    /*!< WAIT (Bit 6)                                          */
34104  #define R_IIC0_ICMR3_WAIT_Msk      (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01)                            */
34105  #define R_IIC0_ICMR3_SMBS_Pos      (7UL)    /*!< SMBS (Bit 7)                                          */
34106  #define R_IIC0_ICMR3_SMBS_Msk      (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01)                            */
34107 /* =========================================================  ICFER  ========================================================= */
34108  #define R_IIC0_ICFER_TMOE_Pos      (0UL)    /*!< TMOE (Bit 0)                                          */
34109  #define R_IIC0_ICFER_TMOE_Msk      (0x1UL)  /*!< TMOE (Bitfield-Mask: 0x01)                            */
34110  #define R_IIC0_ICFER_MALE_Pos      (1UL)    /*!< MALE (Bit 1)                                          */
34111  #define R_IIC0_ICFER_MALE_Msk      (0x2UL)  /*!< MALE (Bitfield-Mask: 0x01)                            */
34112  #define R_IIC0_ICFER_NALE_Pos      (2UL)    /*!< NALE (Bit 2)                                          */
34113  #define R_IIC0_ICFER_NALE_Msk      (0x4UL)  /*!< NALE (Bitfield-Mask: 0x01)                            */
34114  #define R_IIC0_ICFER_SALE_Pos      (3UL)    /*!< SALE (Bit 3)                                          */
34115  #define R_IIC0_ICFER_SALE_Msk      (0x8UL)  /*!< SALE (Bitfield-Mask: 0x01)                            */
34116  #define R_IIC0_ICFER_NACKE_Pos     (4UL)    /*!< NACKE (Bit 4)                                         */
34117  #define R_IIC0_ICFER_NACKE_Msk     (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01)                           */
34118  #define R_IIC0_ICFER_NFE_Pos       (5UL)    /*!< NFE (Bit 5)                                           */
34119  #define R_IIC0_ICFER_NFE_Msk       (0x20UL) /*!< NFE (Bitfield-Mask: 0x01)                             */
34120  #define R_IIC0_ICFER_SCLE_Pos      (6UL)    /*!< SCLE (Bit 6)                                          */
34121  #define R_IIC0_ICFER_SCLE_Msk      (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01)                            */
34122 /* =========================================================  ICSER  ========================================================= */
34123  #define R_IIC0_ICSER_SAR0E_Pos     (0UL)    /*!< SAR0E (Bit 0)                                         */
34124  #define R_IIC0_ICSER_SAR0E_Msk     (0x1UL)  /*!< SAR0E (Bitfield-Mask: 0x01)                           */
34125  #define R_IIC0_ICSER_SAR1E_Pos     (1UL)    /*!< SAR1E (Bit 1)                                         */
34126  #define R_IIC0_ICSER_SAR1E_Msk     (0x2UL)  /*!< SAR1E (Bitfield-Mask: 0x01)                           */
34127  #define R_IIC0_ICSER_SAR2E_Pos     (2UL)    /*!< SAR2E (Bit 2)                                         */
34128  #define R_IIC0_ICSER_SAR2E_Msk     (0x4UL)  /*!< SAR2E (Bitfield-Mask: 0x01)                           */
34129  #define R_IIC0_ICSER_GCAE_Pos      (3UL)    /*!< GCAE (Bit 3)                                          */
34130  #define R_IIC0_ICSER_GCAE_Msk      (0x8UL)  /*!< GCAE (Bitfield-Mask: 0x01)                            */
34131  #define R_IIC0_ICSER_DIDE_Pos      (5UL)    /*!< DIDE (Bit 5)                                          */
34132  #define R_IIC0_ICSER_DIDE_Msk      (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01)                            */
34133  #define R_IIC0_ICSER_HOAE_Pos      (7UL)    /*!< HOAE (Bit 7)                                          */
34134  #define R_IIC0_ICSER_HOAE_Msk      (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01)                            */
34135 /* =========================================================  ICIER  ========================================================= */
34136  #define R_IIC0_ICIER_TMOIE_Pos     (0UL)    /*!< TMOIE (Bit 0)                                         */
34137  #define R_IIC0_ICIER_TMOIE_Msk     (0x1UL)  /*!< TMOIE (Bitfield-Mask: 0x01)                           */
34138  #define R_IIC0_ICIER_ALIE_Pos      (1UL)    /*!< ALIE (Bit 1)                                          */
34139  #define R_IIC0_ICIER_ALIE_Msk      (0x2UL)  /*!< ALIE (Bitfield-Mask: 0x01)                            */
34140  #define R_IIC0_ICIER_STIE_Pos      (2UL)    /*!< STIE (Bit 2)                                          */
34141  #define R_IIC0_ICIER_STIE_Msk      (0x4UL)  /*!< STIE (Bitfield-Mask: 0x01)                            */
34142  #define R_IIC0_ICIER_SPIE_Pos      (3UL)    /*!< SPIE (Bit 3)                                          */
34143  #define R_IIC0_ICIER_SPIE_Msk      (0x8UL)  /*!< SPIE (Bitfield-Mask: 0x01)                            */
34144  #define R_IIC0_ICIER_NAKIE_Pos     (4UL)    /*!< NAKIE (Bit 4)                                         */
34145  #define R_IIC0_ICIER_NAKIE_Msk     (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01)                           */
34146  #define R_IIC0_ICIER_RIE_Pos       (5UL)    /*!< RIE (Bit 5)                                           */
34147  #define R_IIC0_ICIER_RIE_Msk       (0x20UL) /*!< RIE (Bitfield-Mask: 0x01)                             */
34148  #define R_IIC0_ICIER_TEIE_Pos      (6UL)    /*!< TEIE (Bit 6)                                          */
34149  #define R_IIC0_ICIER_TEIE_Msk      (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01)                            */
34150  #define R_IIC0_ICIER_TIE_Pos       (7UL)    /*!< TIE (Bit 7)                                           */
34151  #define R_IIC0_ICIER_TIE_Msk       (0x80UL) /*!< TIE (Bitfield-Mask: 0x01)                             */
34152 /* =========================================================  ICSR1  ========================================================= */
34153  #define R_IIC0_ICSR1_AAS0_Pos      (0UL)    /*!< AAS0 (Bit 0)                                          */
34154  #define R_IIC0_ICSR1_AAS0_Msk      (0x1UL)  /*!< AAS0 (Bitfield-Mask: 0x01)                            */
34155  #define R_IIC0_ICSR1_AAS1_Pos      (1UL)    /*!< AAS1 (Bit 1)                                          */
34156  #define R_IIC0_ICSR1_AAS1_Msk      (0x2UL)  /*!< AAS1 (Bitfield-Mask: 0x01)                            */
34157  #define R_IIC0_ICSR1_AAS2_Pos      (2UL)    /*!< AAS2 (Bit 2)                                          */
34158  #define R_IIC0_ICSR1_AAS2_Msk      (0x4UL)  /*!< AAS2 (Bitfield-Mask: 0x01)                            */
34159  #define R_IIC0_ICSR1_GCA_Pos       (3UL)    /*!< GCA (Bit 3)                                           */
34160  #define R_IIC0_ICSR1_GCA_Msk       (0x8UL)  /*!< GCA (Bitfield-Mask: 0x01)                             */
34161  #define R_IIC0_ICSR1_DID_Pos       (5UL)    /*!< DID (Bit 5)                                           */
34162  #define R_IIC0_ICSR1_DID_Msk       (0x20UL) /*!< DID (Bitfield-Mask: 0x01)                             */
34163  #define R_IIC0_ICSR1_HOA_Pos       (7UL)    /*!< HOA (Bit 7)                                           */
34164  #define R_IIC0_ICSR1_HOA_Msk       (0x80UL) /*!< HOA (Bitfield-Mask: 0x01)                             */
34165 /* =========================================================  ICSR2  ========================================================= */
34166  #define R_IIC0_ICSR2_TMOF_Pos      (0UL)    /*!< TMOF (Bit 0)                                          */
34167  #define R_IIC0_ICSR2_TMOF_Msk      (0x1UL)  /*!< TMOF (Bitfield-Mask: 0x01)                            */
34168  #define R_IIC0_ICSR2_AL_Pos        (1UL)    /*!< AL (Bit 1)                                            */
34169  #define R_IIC0_ICSR2_AL_Msk        (0x2UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
34170  #define R_IIC0_ICSR2_START_Pos     (2UL)    /*!< START (Bit 2)                                         */
34171  #define R_IIC0_ICSR2_START_Msk     (0x4UL)  /*!< START (Bitfield-Mask: 0x01)                           */
34172  #define R_IIC0_ICSR2_STOP_Pos      (3UL)    /*!< STOP (Bit 3)                                          */
34173  #define R_IIC0_ICSR2_STOP_Msk      (0x8UL)  /*!< STOP (Bitfield-Mask: 0x01)                            */
34174  #define R_IIC0_ICSR2_NACKF_Pos     (4UL)    /*!< NACKF (Bit 4)                                         */
34175  #define R_IIC0_ICSR2_NACKF_Msk     (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01)                           */
34176  #define R_IIC0_ICSR2_RDRF_Pos      (5UL)    /*!< RDRF (Bit 5)                                          */
34177  #define R_IIC0_ICSR2_RDRF_Msk      (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01)                            */
34178  #define R_IIC0_ICSR2_TEND_Pos      (6UL)    /*!< TEND (Bit 6)                                          */
34179  #define R_IIC0_ICSR2_TEND_Msk      (0x40UL) /*!< TEND (Bitfield-Mask: 0x01)                            */
34180  #define R_IIC0_ICSR2_TDRE_Pos      (7UL)    /*!< TDRE (Bit 7)                                          */
34181  #define R_IIC0_ICSR2_TDRE_Msk      (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01)                            */
34182 /* =========================================================  ICBRL  ========================================================= */
34183  #define R_IIC0_ICBRL_BRL_Pos       (0UL)    /*!< BRL (Bit 0)                                           */
34184  #define R_IIC0_ICBRL_BRL_Msk       (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f)                             */
34185 /* =========================================================  ICBRH  ========================================================= */
34186  #define R_IIC0_ICBRH_BRH_Pos       (0UL)    /*!< BRH (Bit 0)                                           */
34187  #define R_IIC0_ICBRH_BRH_Msk       (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f)                             */
34188 /* =========================================================  ICDRT  ========================================================= */
34189 /* =========================================================  ICDRR  ========================================================= */
34190 
34191 /* =========================================================================================================================== */
34192 /* ================                                           R_DOC                                           ================ */
34193 /* =========================================================================================================================== */
34194 
34195 /* =========================================================  DOCR  ========================================================== */
34196  #define R_DOC_DOCR_OMS_Pos        (0UL)    /*!< OMS (Bit 0)                                           */
34197  #define R_DOC_DOCR_OMS_Msk        (0x3UL)  /*!< OMS (Bitfield-Mask: 0x03)                             */
34198  #define R_DOC_DOCR_DCSEL_Pos      (2UL)    /*!< DCSEL (Bit 2)                                         */
34199  #define R_DOC_DOCR_DCSEL_Msk      (0x4UL)  /*!< DCSEL (Bitfield-Mask: 0x01)                           */
34200  #define R_DOC_DOCR_DOPCIE_Pos     (4UL)    /*!< DOPCIE (Bit 4)                                        */
34201  #define R_DOC_DOCR_DOPCIE_Msk     (0x10UL) /*!< DOPCIE (Bitfield-Mask: 0x01)                          */
34202  #define R_DOC_DOCR_DOPCF_Pos      (5UL)    /*!< DOPCF (Bit 5)                                         */
34203  #define R_DOC_DOCR_DOPCF_Msk      (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01)                           */
34204  #define R_DOC_DOCR_DOPCFCL_Pos    (6UL)    /*!< DOPCFCL (Bit 6)                                       */
34205  #define R_DOC_DOCR_DOPCFCL_Msk    (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01)                         */
34206 /* =========================================================  DODIR  ========================================================= */
34207 /* =========================================================  DODSR  ========================================================= */
34208 
34209 /* =========================================================================================================================== */
34210 /* ================                                         R_ADC121                                          ================ */
34211 /* =========================================================================================================================== */
34212 
34213 /* =========================================================  ADCSR  ========================================================= */
34214  #define R_ADC121_ADCSR_DBLANS_Pos          (0UL)      /*!< DBLANS (Bit 0)                                        */
34215  #define R_ADC121_ADCSR_DBLANS_Msk          (0x1fUL)   /*!< DBLANS (Bitfield-Mask: 0x1f)                          */
34216  #define R_ADC121_ADCSR_GBADIE_Pos          (6UL)      /*!< GBADIE (Bit 6)                                        */
34217  #define R_ADC121_ADCSR_GBADIE_Msk          (0x40UL)   /*!< GBADIE (Bitfield-Mask: 0x01)                          */
34218  #define R_ADC121_ADCSR_DBLE_Pos            (7UL)      /*!< DBLE (Bit 7)                                          */
34219  #define R_ADC121_ADCSR_DBLE_Msk            (0x80UL)   /*!< DBLE (Bitfield-Mask: 0x01)                            */
34220  #define R_ADC121_ADCSR_EXTRG_Pos           (8UL)      /*!< EXTRG (Bit 8)                                         */
34221  #define R_ADC121_ADCSR_EXTRG_Msk           (0x100UL)  /*!< EXTRG (Bitfield-Mask: 0x01)                           */
34222  #define R_ADC121_ADCSR_TRGE_Pos            (9UL)      /*!< TRGE (Bit 9)                                          */
34223  #define R_ADC121_ADCSR_TRGE_Msk            (0x200UL)  /*!< TRGE (Bitfield-Mask: 0x01)                            */
34224  #define R_ADC121_ADCSR_ADIE_Pos            (12UL)     /*!< ADIE (Bit 12)                                         */
34225  #define R_ADC121_ADCSR_ADIE_Msk            (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01)                            */
34226  #define R_ADC121_ADCSR_ADCS_Pos            (13UL)     /*!< ADCS (Bit 13)                                         */
34227  #define R_ADC121_ADCSR_ADCS_Msk            (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03)                            */
34228  #define R_ADC121_ADCSR_ADST_Pos            (15UL)     /*!< ADST (Bit 15)                                         */
34229  #define R_ADC121_ADCSR_ADST_Msk            (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01)                            */
34230 /* ========================================================  ADANSA0  ======================================================== */
34231  #define R_ADC121_ADANSA0_ANSA0_Pos         (0UL)      /*!< ANSA0 (Bit 0)                                         */
34232  #define R_ADC121_ADANSA0_ANSA0_Msk         (0xffUL)   /*!< ANSA0 (Bitfield-Mask: 0xff)                           */
34233 /* ========================================================  ADADS0  ========================================================= */
34234  #define R_ADC121_ADADS0_ADS0_Pos           (0UL)      /*!< ADS0 (Bit 0)                                          */
34235  #define R_ADC121_ADADS0_ADS0_Msk           (0xffUL)   /*!< ADS0 (Bitfield-Mask: 0xff)                            */
34236 /* =========================================================  ADADC  ========================================================= */
34237  #define R_ADC121_ADADC_ADC_Pos             (0UL)      /*!< ADC (Bit 0)                                           */
34238  #define R_ADC121_ADADC_ADC_Msk             (0x7UL)    /*!< ADC (Bitfield-Mask: 0x07)                             */
34239  #define R_ADC121_ADADC_AVEE_Pos            (7UL)      /*!< AVEE (Bit 7)                                          */
34240  #define R_ADC121_ADADC_AVEE_Msk            (0x80UL)   /*!< AVEE (Bitfield-Mask: 0x01)                            */
34241 /* =========================================================  ADCER  ========================================================= */
34242  #define R_ADC121_ADCER_ADPRC_Pos           (1UL)      /*!< ADPRC (Bit 1)                                         */
34243  #define R_ADC121_ADCER_ADPRC_Msk           (0x6UL)    /*!< ADPRC (Bitfield-Mask: 0x03)                           */
34244  #define R_ADC121_ADCER_ACE_Pos             (5UL)      /*!< ACE (Bit 5)                                           */
34245  #define R_ADC121_ADCER_ACE_Msk             (0x20UL)   /*!< ACE (Bitfield-Mask: 0x01)                             */
34246  #define R_ADC121_ADCER_ADRFMT_Pos          (15UL)     /*!< ADRFMT (Bit 15)                                       */
34247  #define R_ADC121_ADCER_ADRFMT_Msk          (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01)                          */
34248 /* ========================================================  ADSTRGR  ======================================================== */
34249  #define R_ADC121_ADSTRGR_TRSB_Pos          (0UL)      /*!< TRSB (Bit 0)                                          */
34250  #define R_ADC121_ADSTRGR_TRSB_Msk          (0x3fUL)   /*!< TRSB (Bitfield-Mask: 0x3f)                            */
34251  #define R_ADC121_ADSTRGR_TRSA_Pos          (8UL)      /*!< TRSA (Bit 8)                                          */
34252  #define R_ADC121_ADSTRGR_TRSA_Msk          (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f)                            */
34253 /* ========================================================  ADANSB0  ======================================================== */
34254  #define R_ADC121_ADANSB0_ANSB0_Pos         (0UL)      /*!< ANSB0 (Bit 0)                                         */
34255  #define R_ADC121_ADANSB0_ANSB0_Msk         (0xffUL)   /*!< ANSB0 (Bitfield-Mask: 0xff)                           */
34256 /* ========================================================  ADDBLDR  ======================================================== */
34257  #define R_ADC121_ADDBLDR_DBLDR_Pos         (0UL)      /*!< DBLDR (Bit 0)                                         */
34258  #define R_ADC121_ADDBLDR_DBLDR_Msk         (0xffffUL) /*!< DBLDR (Bitfield-Mask: 0xffff)                         */
34259 /* =========================================================  ADDR  ========================================================== */
34260  #define R_ADC121_ADDR_DR_Pos               (0UL)      /*!< DR (Bit 0)                                            */
34261  #define R_ADC121_ADDR_DR_Msk               (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff)                            */
34262 /* ========================================================  ADSHCR  ========================================================= */
34263  #define R_ADC121_ADSHCR_SSTSH_Pos          (0UL)      /*!< SSTSH (Bit 0)                                         */
34264  #define R_ADC121_ADSHCR_SSTSH_Msk          (0xffUL)   /*!< SSTSH (Bitfield-Mask: 0xff)                           */
34265  #define R_ADC121_ADSHCR_SHANS_Pos          (8UL)      /*!< SHANS (Bit 8)                                         */
34266  #define R_ADC121_ADSHCR_SHANS_Msk          (0x700UL)  /*!< SHANS (Bitfield-Mask: 0x07)                           */
34267 /* ========================================================  ADELCCR  ======================================================== */
34268  #define R_ADC121_ADELCCR_ELCC_Pos          (0UL)      /*!< ELCC (Bit 0)                                          */
34269  #define R_ADC121_ADELCCR_ELCC_Msk          (0x3UL)    /*!< ELCC (Bitfield-Mask: 0x03)                            */
34270  #define R_ADC121_ADELCCR_GCELC_Pos         (2UL)      /*!< GCELC (Bit 2)                                         */
34271  #define R_ADC121_ADELCCR_GCELC_Msk         (0x4UL)    /*!< GCELC (Bitfield-Mask: 0x01)                           */
34272 /* ========================================================  ADGSPCR  ======================================================== */
34273  #define R_ADC121_ADGSPCR_PGS_Pos           (0UL)      /*!< PGS (Bit 0)                                           */
34274  #define R_ADC121_ADGSPCR_PGS_Msk           (0x1UL)    /*!< PGS (Bitfield-Mask: 0x01)                             */
34275  #define R_ADC121_ADGSPCR_GBRSCN_Pos        (1UL)      /*!< GBRSCN (Bit 1)                                        */
34276  #define R_ADC121_ADGSPCR_GBRSCN_Msk        (0x2UL)    /*!< GBRSCN (Bitfield-Mask: 0x01)                          */
34277  #define R_ADC121_ADGSPCR_LGRRS_Pos         (14UL)     /*!< LGRRS (Bit 14)                                        */
34278  #define R_ADC121_ADGSPCR_LGRRS_Msk         (0x4000UL) /*!< LGRRS (Bitfield-Mask: 0x01)                           */
34279  #define R_ADC121_ADGSPCR_GBRP_Pos          (15UL)     /*!< GBRP (Bit 15)                                         */
34280  #define R_ADC121_ADGSPCR_GBRP_Msk          (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01)                            */
34281 /* =======================================================  ADDBLDRA  ======================================================== */
34282  #define R_ADC121_ADDBLDRA_DBLDRA_Pos       (0UL)      /*!< DBLDRA (Bit 0)                                        */
34283  #define R_ADC121_ADDBLDRA_DBLDRA_Msk       (0xffffUL) /*!< DBLDRA (Bitfield-Mask: 0xffff)                        */
34284 /* =======================================================  ADDBLDRB  ======================================================== */
34285  #define R_ADC121_ADDBLDRB_DBLDRB_Pos       (0UL)      /*!< DBLDRB (Bit 0)                                        */
34286  #define R_ADC121_ADDBLDRB_DBLDRB_Msk       (0xffffUL) /*!< DBLDRB (Bitfield-Mask: 0xffff)                        */
34287 /* =======================================================  ADWINMON  ======================================================== */
34288  #define R_ADC121_ADWINMON_MONCOMB_Pos      (0UL)      /*!< MONCOMB (Bit 0)                                       */
34289  #define R_ADC121_ADWINMON_MONCOMB_Msk      (0x1UL)    /*!< MONCOMB (Bitfield-Mask: 0x01)                         */
34290  #define R_ADC121_ADWINMON_MONCMPA_Pos      (4UL)      /*!< MONCMPA (Bit 4)                                       */
34291  #define R_ADC121_ADWINMON_MONCMPA_Msk      (0x10UL)   /*!< MONCMPA (Bitfield-Mask: 0x01)                         */
34292  #define R_ADC121_ADWINMON_MONCMPB_Pos      (5UL)      /*!< MONCMPB (Bit 5)                                       */
34293  #define R_ADC121_ADWINMON_MONCMPB_Msk      (0x20UL)   /*!< MONCMPB (Bitfield-Mask: 0x01)                         */
34294 /* ========================================================  ADCMPCR  ======================================================== */
34295  #define R_ADC121_ADCMPCR_CMPAB_Pos         (0UL)      /*!< CMPAB (Bit 0)                                         */
34296  #define R_ADC121_ADCMPCR_CMPAB_Msk         (0x3UL)    /*!< CMPAB (Bitfield-Mask: 0x03)                           */
34297  #define R_ADC121_ADCMPCR_CMPBE_Pos         (9UL)      /*!< CMPBE (Bit 9)                                         */
34298  #define R_ADC121_ADCMPCR_CMPBE_Msk         (0x200UL)  /*!< CMPBE (Bitfield-Mask: 0x01)                           */
34299  #define R_ADC121_ADCMPCR_CMPAE_Pos         (11UL)     /*!< CMPAE (Bit 11)                                        */
34300  #define R_ADC121_ADCMPCR_CMPAE_Msk         (0x800UL)  /*!< CMPAE (Bitfield-Mask: 0x01)                           */
34301  #define R_ADC121_ADCMPCR_CMPBIE_Pos        (13UL)     /*!< CMPBIE (Bit 13)                                       */
34302  #define R_ADC121_ADCMPCR_CMPBIE_Msk        (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01)                          */
34303  #define R_ADC121_ADCMPCR_WCMPE_Pos         (14UL)     /*!< WCMPE (Bit 14)                                        */
34304  #define R_ADC121_ADCMPCR_WCMPE_Msk         (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01)                           */
34305  #define R_ADC121_ADCMPCR_CMPAIE_Pos        (15UL)     /*!< CMPAIE (Bit 15)                                       */
34306  #define R_ADC121_ADCMPCR_CMPAIE_Msk        (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01)                          */
34307 /* ======================================================  ADCMPANSR0  ======================================================= */
34308  #define R_ADC121_ADCMPANSR0_CMPCHA0_Pos    (0UL)      /*!< CMPCHA0 (Bit 0)                                       */
34309  #define R_ADC121_ADCMPANSR0_CMPCHA0_Msk    (0xffUL)   /*!< CMPCHA0 (Bitfield-Mask: 0xff)                         */
34310 /* =======================================================  ADCMPLR0  ======================================================== */
34311  #define R_ADC121_ADCMPLR0_CMPLCHA0_Pos     (0UL)      /*!< CMPLCHA0 (Bit 0)                                      */
34312  #define R_ADC121_ADCMPLR0_CMPLCHA0_Msk     (0xffUL)   /*!< CMPLCHA0 (Bitfield-Mask: 0xff)                        */
34313 /* =======================================================  ADCMPDR0  ======================================================== */
34314  #define R_ADC121_ADCMPDR0_CMPLLA_Pos       (0UL)      /*!< CMPLLA (Bit 0)                                        */
34315  #define R_ADC121_ADCMPDR0_CMPLLA_Msk       (0xffffUL) /*!< CMPLLA (Bitfield-Mask: 0xffff)                        */
34316 /* =======================================================  ADCMPDR1  ======================================================== */
34317  #define R_ADC121_ADCMPDR1_CMPULA_Pos       (0UL)      /*!< CMPULA (Bit 0)                                        */
34318  #define R_ADC121_ADCMPDR1_CMPULA_Msk       (0xffffUL) /*!< CMPULA (Bitfield-Mask: 0xffff)                        */
34319 /* =======================================================  ADCMPSR0  ======================================================== */
34320  #define R_ADC121_ADCMPSR0_CMPSTCHA0_Pos    (0UL)      /*!< CMPSTCHA0 (Bit 0)                                     */
34321  #define R_ADC121_ADCMPSR0_CMPSTCHA0_Msk    (0xffUL)   /*!< CMPSTCHA0 (Bitfield-Mask: 0xff)                       */
34322 /* =======================================================  ADCMPBNSR  ======================================================= */
34323  #define R_ADC121_ADCMPBNSR_CMPCHB_Pos      (0UL)      /*!< CMPCHB (Bit 0)                                        */
34324  #define R_ADC121_ADCMPBNSR_CMPCHB_Msk      (0x3fUL)   /*!< CMPCHB (Bitfield-Mask: 0x3f)                          */
34325  #define R_ADC121_ADCMPBNSR_CMPLB_Pos       (7UL)      /*!< CMPLB (Bit 7)                                         */
34326  #define R_ADC121_ADCMPBNSR_CMPLB_Msk       (0x80UL)   /*!< CMPLB (Bitfield-Mask: 0x01)                           */
34327 /* =======================================================  ADWINLLB  ======================================================== */
34328  #define R_ADC121_ADWINLLB_CMPLLB_Pos       (0UL)      /*!< CMPLLB (Bit 0)                                        */
34329  #define R_ADC121_ADWINLLB_CMPLLB_Msk       (0xffffUL) /*!< CMPLLB (Bitfield-Mask: 0xffff)                        */
34330 /* =======================================================  ADWINULB  ======================================================== */
34331  #define R_ADC121_ADWINULB_CMPULB_Pos       (0UL)      /*!< CMPULB (Bit 0)                                        */
34332  #define R_ADC121_ADWINULB_CMPULB_Msk       (0xffffUL) /*!< CMPULB (Bitfield-Mask: 0xffff)                        */
34333 /* =======================================================  ADCMPBSR  ======================================================== */
34334  #define R_ADC121_ADCMPBSR_CMPSTB_Pos       (0UL)      /*!< CMPSTB (Bit 0)                                        */
34335  #define R_ADC121_ADCMPBSR_CMPSTB_Msk       (0x1UL)    /*!< CMPSTB (Bitfield-Mask: 0x01)                          */
34336 /* ========================================================  ADANSC0  ======================================================== */
34337  #define R_ADC121_ADANSC0_ANSC0_Pos         (0UL)      /*!< ANSC0 (Bit 0)                                         */
34338  #define R_ADC121_ADANSC0_ANSC0_Msk         (0xffUL)   /*!< ANSC0 (Bitfield-Mask: 0xff)                           */
34339 /* =======================================================  ADGCTRGR  ======================================================== */
34340  #define R_ADC121_ADGCTRGR_TRSC_Pos         (0UL)      /*!< TRSC (Bit 0)                                          */
34341  #define R_ADC121_ADGCTRGR_TRSC_Msk         (0x3fUL)   /*!< TRSC (Bitfield-Mask: 0x3f)                            */
34342  #define R_ADC121_ADGCTRGR_GCADIE_Pos       (6UL)      /*!< GCADIE (Bit 6)                                        */
34343  #define R_ADC121_ADGCTRGR_GCADIE_Msk       (0x40UL)   /*!< GCADIE (Bitfield-Mask: 0x01)                          */
34344  #define R_ADC121_ADGCTRGR_GRCE_Pos         (7UL)      /*!< GRCE (Bit 7)                                          */
34345  #define R_ADC121_ADGCTRGR_GRCE_Msk         (0x80UL)   /*!< GRCE (Bitfield-Mask: 0x01)                            */
34346 /* ========================================================  ADSSTR  ========================================================= */
34347  #define R_ADC121_ADSSTR_SST_Pos            (0UL)      /*!< SST (Bit 0)                                           */
34348  #define R_ADC121_ADSSTR_SST_Msk            (0xffUL)   /*!< SST (Bitfield-Mask: 0xff)                             */
34349 
34350 /* =========================================================================================================================== */
34351 /* ================                                           R_TSU                                           ================ */
34352 /* =========================================================================================================================== */
34353 
34354 /* =========================================================  TSUSM  ========================================================= */
34355  #define R_TSU_TSUSM_TSEN_Pos      (0UL)     /*!< TSEN (Bit 0)                                          */
34356  #define R_TSU_TSUSM_TSEN_Msk      (0x1UL)   /*!< TSEN (Bitfield-Mask: 0x01)                            */
34357  #define R_TSU_TSUSM_ADCEN_Pos     (1UL)     /*!< ADCEN (Bit 1)                                         */
34358  #define R_TSU_TSUSM_ADCEN_Msk     (0x2UL)   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
34359 /* =========================================================  TSUST  ========================================================= */
34360  #define R_TSU_TSUST_START_Pos     (0UL)     /*!< START (Bit 0)                                         */
34361  #define R_TSU_TSUST_START_Msk     (0x1UL)   /*!< START (Bitfield-Mask: 0x01)                           */
34362 /* ========================================================  TSUSCS  ========================================================= */
34363  #define R_TSU_TSUSCS_CKDIV_Pos    (3UL)     /*!< CKDIV (Bit 3)                                         */
34364  #define R_TSU_TSUSCS_CKDIV_Msk    (0x8UL)   /*!< CKDIV (Bitfield-Mask: 0x01)                           */
34365 /* ========================================================  TSUSAD  ========================================================= */
34366  #define R_TSU_TSUSAD_DOUT_Pos     (0UL)     /*!< DOUT (Bit 0)                                          */
34367  #define R_TSU_TSUSAD_DOUT_Msk     (0xfffUL) /*!< DOUT (Bitfield-Mask: 0xfff)                           */
34368 /* =========================================================  TSUSS  ========================================================= */
34369  #define R_TSU_TSUSS_CONV_Pos      (0UL)     /*!< CONV (Bit 0)                                          */
34370  #define R_TSU_TSUSS_CONV_Msk      (0x1UL)   /*!< CONV (Bitfield-Mask: 0x01)                            */
34371 
34372 /* =========================================================================================================================== */
34373 /* ================                                          R_POEG1                                          ================ */
34374 /* =========================================================================================================================== */
34375 
34376 /* ========================================================  POEG1GA  ======================================================== */
34377  #define R_POEG1_POEG1GA_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
34378  #define R_POEG1_POEG1GA_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
34379  #define R_POEG1_POEG1GA_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
34380  #define R_POEG1_POEG1GA_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
34381  #define R_POEG1_POEG1GA_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
34382  #define R_POEG1_POEG1GA_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
34383  #define R_POEG1_POEG1GA_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
34384  #define R_POEG1_POEG1GA_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
34385  #define R_POEG1_POEG1GA_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
34386  #define R_POEG1_POEG1GA_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
34387  #define R_POEG1_POEG1GA_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
34388  #define R_POEG1_POEG1GA_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
34389  #define R_POEG1_POEG1GA_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
34390  #define R_POEG1_POEG1GA_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
34391  #define R_POEG1_POEG1GA_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
34392  #define R_POEG1_POEG1GA_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
34393  #define R_POEG1_POEG1GA_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
34394  #define R_POEG1_POEG1GA_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
34395  #define R_POEG1_POEG1GA_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
34396  #define R_POEG1_POEG1GA_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
34397  #define R_POEG1_POEG1GA_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
34398  #define R_POEG1_POEG1GA_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
34399 /* ========================================================  POEG1GB  ======================================================== */
34400  #define R_POEG1_POEG1GB_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
34401  #define R_POEG1_POEG1GB_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
34402  #define R_POEG1_POEG1GB_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
34403  #define R_POEG1_POEG1GB_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
34404  #define R_POEG1_POEG1GB_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
34405  #define R_POEG1_POEG1GB_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
34406  #define R_POEG1_POEG1GB_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
34407  #define R_POEG1_POEG1GB_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
34408  #define R_POEG1_POEG1GB_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
34409  #define R_POEG1_POEG1GB_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
34410  #define R_POEG1_POEG1GB_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
34411  #define R_POEG1_POEG1GB_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
34412  #define R_POEG1_POEG1GB_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
34413  #define R_POEG1_POEG1GB_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
34414  #define R_POEG1_POEG1GB_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
34415  #define R_POEG1_POEG1GB_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
34416  #define R_POEG1_POEG1GB_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
34417  #define R_POEG1_POEG1GB_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
34418  #define R_POEG1_POEG1GB_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
34419  #define R_POEG1_POEG1GB_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
34420  #define R_POEG1_POEG1GB_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
34421  #define R_POEG1_POEG1GB_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
34422 /* ========================================================  POEG1GC  ======================================================== */
34423  #define R_POEG1_POEG1GC_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
34424  #define R_POEG1_POEG1GC_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
34425  #define R_POEG1_POEG1GC_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
34426  #define R_POEG1_POEG1GC_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
34427  #define R_POEG1_POEG1GC_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
34428  #define R_POEG1_POEG1GC_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
34429  #define R_POEG1_POEG1GC_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
34430  #define R_POEG1_POEG1GC_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
34431  #define R_POEG1_POEG1GC_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
34432  #define R_POEG1_POEG1GC_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
34433  #define R_POEG1_POEG1GC_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
34434  #define R_POEG1_POEG1GC_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
34435  #define R_POEG1_POEG1GC_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
34436  #define R_POEG1_POEG1GC_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
34437  #define R_POEG1_POEG1GC_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
34438  #define R_POEG1_POEG1GC_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
34439  #define R_POEG1_POEG1GC_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
34440  #define R_POEG1_POEG1GC_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
34441  #define R_POEG1_POEG1GC_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
34442  #define R_POEG1_POEG1GC_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
34443  #define R_POEG1_POEG1GC_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
34444  #define R_POEG1_POEG1GC_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
34445 /* ========================================================  POEG1GD  ======================================================== */
34446  #define R_POEG1_POEG1GD_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
34447  #define R_POEG1_POEG1GD_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
34448  #define R_POEG1_POEG1GD_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
34449  #define R_POEG1_POEG1GD_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
34450  #define R_POEG1_POEG1GD_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
34451  #define R_POEG1_POEG1GD_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
34452  #define R_POEG1_POEG1GD_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
34453  #define R_POEG1_POEG1GD_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
34454  #define R_POEG1_POEG1GD_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
34455  #define R_POEG1_POEG1GD_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
34456  #define R_POEG1_POEG1GD_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
34457  #define R_POEG1_POEG1GD_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
34458  #define R_POEG1_POEG1GD_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
34459  #define R_POEG1_POEG1GD_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
34460  #define R_POEG1_POEG1GD_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
34461  #define R_POEG1_POEG1GD_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
34462  #define R_POEG1_POEG1GD_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
34463  #define R_POEG1_POEG1GD_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
34464  #define R_POEG1_POEG1GD_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
34465  #define R_POEG1_POEG1GD_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
34466  #define R_POEG1_POEG1GD_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
34467  #define R_POEG1_POEG1GD_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
34468 
34469 /* =========================================================================================================================== */
34470 /* ================                                          R_DMAC0                                          ================ */
34471 /* =========================================================================================================================== */
34472 
34473 /* =========================================================================================================================== */
34474 /* ================                                         R_ICU_NS                                          ================ */
34475 /* =========================================================================================================================== */
34476 
34477 /* =======================================================  NS_SWINT  ======================================================== */
34478  #define R_ICU_NS_NS_SWINT_IC0_Pos                  (0UL)          /*!< IC0 (Bit 0)                                           */
34479  #define R_ICU_NS_NS_SWINT_IC0_Msk                  (0x1UL)        /*!< IC0 (Bitfield-Mask: 0x01)                             */
34480  #define R_ICU_NS_NS_SWINT_IC1_Pos                  (1UL)          /*!< IC1 (Bit 1)                                           */
34481  #define R_ICU_NS_NS_SWINT_IC1_Msk                  (0x2UL)        /*!< IC1 (Bitfield-Mask: 0x01)                             */
34482  #define R_ICU_NS_NS_SWINT_IC2_Pos                  (2UL)          /*!< IC2 (Bit 2)                                           */
34483  #define R_ICU_NS_NS_SWINT_IC2_Msk                  (0x4UL)        /*!< IC2 (Bitfield-Mask: 0x01)                             */
34484  #define R_ICU_NS_NS_SWINT_IC3_Pos                  (3UL)          /*!< IC3 (Bit 3)                                           */
34485  #define R_ICU_NS_NS_SWINT_IC3_Msk                  (0x8UL)        /*!< IC3 (Bitfield-Mask: 0x01)                             */
34486  #define R_ICU_NS_NS_SWINT_IC4_Pos                  (4UL)          /*!< IC4 (Bit 4)                                           */
34487  #define R_ICU_NS_NS_SWINT_IC4_Msk                  (0x10UL)       /*!< IC4 (Bitfield-Mask: 0x01)                             */
34488  #define R_ICU_NS_NS_SWINT_IC5_Pos                  (5UL)          /*!< IC5 (Bit 5)                                           */
34489  #define R_ICU_NS_NS_SWINT_IC5_Msk                  (0x20UL)       /*!< IC5 (Bitfield-Mask: 0x01)                             */
34490 /* ===================================================  NS_PORTNF_FLTSEL  ==================================================== */
34491  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Pos         (0UL)          /*!< FLT0 (Bit 0)                                          */
34492  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Msk         (0x1UL)        /*!< FLT0 (Bitfield-Mask: 0x01)                            */
34493  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Pos         (1UL)          /*!< FLT1 (Bit 1)                                          */
34494  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Msk         (0x2UL)        /*!< FLT1 (Bitfield-Mask: 0x01)                            */
34495  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Pos         (2UL)          /*!< FLT2 (Bit 2)                                          */
34496  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Msk         (0x4UL)        /*!< FLT2 (Bitfield-Mask: 0x01)                            */
34497  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Pos         (3UL)          /*!< FLT3 (Bit 3)                                          */
34498  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Msk         (0x8UL)        /*!< FLT3 (Bitfield-Mask: 0x01)                            */
34499  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Pos         (4UL)          /*!< FLT4 (Bit 4)                                          */
34500  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Msk         (0x10UL)       /*!< FLT4 (Bitfield-Mask: 0x01)                            */
34501  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Pos         (5UL)          /*!< FLT5 (Bit 5)                                          */
34502  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Msk         (0x20UL)       /*!< FLT5 (Bitfield-Mask: 0x01)                            */
34503  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Pos         (6UL)          /*!< FLT6 (Bit 6)                                          */
34504  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Msk         (0x40UL)       /*!< FLT6 (Bitfield-Mask: 0x01)                            */
34505  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Pos         (7UL)          /*!< FLT7 (Bit 7)                                          */
34506  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Msk         (0x80UL)       /*!< FLT7 (Bitfield-Mask: 0x01)                            */
34507  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Pos         (8UL)          /*!< FLT8 (Bit 8)                                          */
34508  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Msk         (0x100UL)      /*!< FLT8 (Bitfield-Mask: 0x01)                            */
34509  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Pos         (9UL)          /*!< FLT9 (Bit 9)                                          */
34510  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Msk         (0x200UL)      /*!< FLT9 (Bitfield-Mask: 0x01)                            */
34511  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Pos        (10UL)         /*!< FLT10 (Bit 10)                                        */
34512  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Msk        (0x400UL)      /*!< FLT10 (Bitfield-Mask: 0x01)                           */
34513  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Pos        (11UL)         /*!< FLT11 (Bit 11)                                        */
34514  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Msk        (0x800UL)      /*!< FLT11 (Bitfield-Mask: 0x01)                           */
34515  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Pos        (12UL)         /*!< FLT12 (Bit 12)                                        */
34516  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Msk        (0x1000UL)     /*!< FLT12 (Bitfield-Mask: 0x01)                           */
34517  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Pos        (13UL)         /*!< FLT13 (Bit 13)                                        */
34518  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Msk        (0x2000UL)     /*!< FLT13 (Bitfield-Mask: 0x01)                           */
34519  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Pos       (14UL)         /*!< FLTDRQ (Bit 14)                                       */
34520  #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Msk       (0x4000UL)     /*!< FLTDRQ (Bitfield-Mask: 0x01)                          */
34521 /* ===================================================  NS_PORTNF_CLKSEL  ==================================================== */
34522  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Pos       (0UL)          /*!< CKSEL0 (Bit 0)                                        */
34523  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Msk       (0x3UL)        /*!< CKSEL0 (Bitfield-Mask: 0x03)                          */
34524  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Pos       (2UL)          /*!< CKSEL1 (Bit 2)                                        */
34525  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Msk       (0xcUL)        /*!< CKSEL1 (Bitfield-Mask: 0x03)                          */
34526  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Pos       (4UL)          /*!< CKSEL2 (Bit 4)                                        */
34527  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Msk       (0x30UL)       /*!< CKSEL2 (Bitfield-Mask: 0x03)                          */
34528  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Pos       (6UL)          /*!< CKSEL3 (Bit 6)                                        */
34529  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Msk       (0xc0UL)       /*!< CKSEL3 (Bitfield-Mask: 0x03)                          */
34530  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Pos       (8UL)          /*!< CKSEL4 (Bit 8)                                        */
34531  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Msk       (0x300UL)      /*!< CKSEL4 (Bitfield-Mask: 0x03)                          */
34532  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Pos       (10UL)         /*!< CKSEL5 (Bit 10)                                       */
34533  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Msk       (0xc00UL)      /*!< CKSEL5 (Bitfield-Mask: 0x03)                          */
34534  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Pos       (12UL)         /*!< CKSEL6 (Bit 12)                                       */
34535  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Msk       (0x3000UL)     /*!< CKSEL6 (Bitfield-Mask: 0x03)                          */
34536  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Pos       (14UL)         /*!< CKSEL7 (Bit 14)                                       */
34537  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Msk       (0xc000UL)     /*!< CKSEL7 (Bitfield-Mask: 0x03)                          */
34538  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Pos       (16UL)         /*!< CKSEL8 (Bit 16)                                       */
34539  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Msk       (0x30000UL)    /*!< CKSEL8 (Bitfield-Mask: 0x03)                          */
34540  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Pos       (18UL)         /*!< CKSEL9 (Bit 18)                                       */
34541  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Msk       (0xc0000UL)    /*!< CKSEL9 (Bitfield-Mask: 0x03)                          */
34542  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Pos      (20UL)         /*!< CKSEL10 (Bit 20)                                      */
34543  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Msk      (0x300000UL)   /*!< CKSEL10 (Bitfield-Mask: 0x03)                         */
34544  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Pos      (22UL)         /*!< CKSEL11 (Bit 22)                                      */
34545  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Msk      (0xc00000UL)   /*!< CKSEL11 (Bitfield-Mask: 0x03)                         */
34546  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Pos      (24UL)         /*!< CKSEL12 (Bit 24)                                      */
34547  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Msk      (0x3000000UL)  /*!< CKSEL12 (Bitfield-Mask: 0x03)                         */
34548  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Pos      (26UL)         /*!< CKSEL13 (Bit 26)                                      */
34549  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Msk      (0xc000000UL)  /*!< CKSEL13 (Bitfield-Mask: 0x03)                         */
34550  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Pos    (28UL)         /*!< CKSELDREQ (Bit 28)                                    */
34551  #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Msk    (0x30000000UL) /*!< CKSELDREQ (Bitfield-Mask: 0x03)                       */
34552 /* =====================================================  NS_PORTNF_MD  ====================================================== */
34553  #define R_ICU_NS_NS_PORTNF_MD_MD0_Pos              (0UL)          /*!< MD0 (Bit 0)                                           */
34554  #define R_ICU_NS_NS_PORTNF_MD_MD0_Msk              (0x3UL)        /*!< MD0 (Bitfield-Mask: 0x03)                             */
34555  #define R_ICU_NS_NS_PORTNF_MD_MD1_Pos              (2UL)          /*!< MD1 (Bit 2)                                           */
34556  #define R_ICU_NS_NS_PORTNF_MD_MD1_Msk              (0xcUL)        /*!< MD1 (Bitfield-Mask: 0x03)                             */
34557  #define R_ICU_NS_NS_PORTNF_MD_MD2_Pos              (4UL)          /*!< MD2 (Bit 4)                                           */
34558  #define R_ICU_NS_NS_PORTNF_MD_MD2_Msk              (0x30UL)       /*!< MD2 (Bitfield-Mask: 0x03)                             */
34559  #define R_ICU_NS_NS_PORTNF_MD_MD3_Pos              (6UL)          /*!< MD3 (Bit 6)                                           */
34560  #define R_ICU_NS_NS_PORTNF_MD_MD3_Msk              (0xc0UL)       /*!< MD3 (Bitfield-Mask: 0x03)                             */
34561  #define R_ICU_NS_NS_PORTNF_MD_MD4_Pos              (8UL)          /*!< MD4 (Bit 8)                                           */
34562  #define R_ICU_NS_NS_PORTNF_MD_MD4_Msk              (0x300UL)      /*!< MD4 (Bitfield-Mask: 0x03)                             */
34563  #define R_ICU_NS_NS_PORTNF_MD_MD5_Pos              (10UL)         /*!< MD5 (Bit 10)                                          */
34564  #define R_ICU_NS_NS_PORTNF_MD_MD5_Msk              (0xc00UL)      /*!< MD5 (Bitfield-Mask: 0x03)                             */
34565  #define R_ICU_NS_NS_PORTNF_MD_MD6_Pos              (12UL)         /*!< MD6 (Bit 12)                                          */
34566  #define R_ICU_NS_NS_PORTNF_MD_MD6_Msk              (0x3000UL)     /*!< MD6 (Bitfield-Mask: 0x03)                             */
34567  #define R_ICU_NS_NS_PORTNF_MD_MD7_Pos              (14UL)         /*!< MD7 (Bit 14)                                          */
34568  #define R_ICU_NS_NS_PORTNF_MD_MD7_Msk              (0xc000UL)     /*!< MD7 (Bitfield-Mask: 0x03)                             */
34569  #define R_ICU_NS_NS_PORTNF_MD_MD8_Pos              (16UL)         /*!< MD8 (Bit 16)                                          */
34570  #define R_ICU_NS_NS_PORTNF_MD_MD8_Msk              (0x30000UL)    /*!< MD8 (Bitfield-Mask: 0x03)                             */
34571  #define R_ICU_NS_NS_PORTNF_MD_MD9_Pos              (18UL)         /*!< MD9 (Bit 18)                                          */
34572  #define R_ICU_NS_NS_PORTNF_MD_MD9_Msk              (0xc0000UL)    /*!< MD9 (Bitfield-Mask: 0x03)                             */
34573  #define R_ICU_NS_NS_PORTNF_MD_MD10_Pos             (20UL)         /*!< MD10 (Bit 20)                                         */
34574  #define R_ICU_NS_NS_PORTNF_MD_MD10_Msk             (0x300000UL)   /*!< MD10 (Bitfield-Mask: 0x03)                            */
34575  #define R_ICU_NS_NS_PORTNF_MD_MD11_Pos             (22UL)         /*!< MD11 (Bit 22)                                         */
34576  #define R_ICU_NS_NS_PORTNF_MD_MD11_Msk             (0xc00000UL)   /*!< MD11 (Bitfield-Mask: 0x03)                            */
34577  #define R_ICU_NS_NS_PORTNF_MD_MD12_Pos             (24UL)         /*!< MD12 (Bit 24)                                         */
34578  #define R_ICU_NS_NS_PORTNF_MD_MD12_Msk             (0x3000000UL)  /*!< MD12 (Bitfield-Mask: 0x03)                            */
34579  #define R_ICU_NS_NS_PORTNF_MD_MD13_Pos             (26UL)         /*!< MD13 (Bit 26)                                         */
34580  #define R_ICU_NS_NS_PORTNF_MD_MD13_Msk             (0xc000000UL)  /*!< MD13 (Bitfield-Mask: 0x03)                            */
34581  #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Pos            (28UL)         /*!< MDDRQ (Bit 28)                                        */
34582  #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Msk            (0x30000000UL) /*!< MDDRQ (Bitfield-Mask: 0x03)                           */
34583 
34584 /* =========================================================================================================================== */
34585 /* ================                                           R_ELC                                           ================ */
34586 /* =========================================================================================================================== */
34587 
34588 /* =======================================================  ELC_SSEL  ======================================================== */
34589  #define R_ELC_ELC_SSEL_ELC_SEL0_Pos    (0UL)          /*!< ELC_SEL0 (Bit 0)                                      */
34590  #define R_ELC_ELC_SSEL_ELC_SEL0_Msk    (0x3ffUL)      /*!< ELC_SEL0 (Bitfield-Mask: 0x3ff)                       */
34591  #define R_ELC_ELC_SSEL_ELC_SEL1_Pos    (10UL)         /*!< ELC_SEL1 (Bit 10)                                     */
34592  #define R_ELC_ELC_SSEL_ELC_SEL1_Msk    (0xffc00UL)    /*!< ELC_SEL1 (Bitfield-Mask: 0x3ff)                       */
34593  #define R_ELC_ELC_SSEL_ELC_SEL2_Pos    (20UL)         /*!< ELC_SEL2 (Bit 20)                                     */
34594  #define R_ELC_ELC_SSEL_ELC_SEL2_Msk    (0x3ff00000UL) /*!< ELC_SEL2 (Bitfield-Mask: 0x3ff)                       */
34595 
34596 /* =========================================================================================================================== */
34597 /* ================                                           R_DMA                                           ================ */
34598 /* =========================================================================================================================== */
34599 
34600 /* ======================================================  DMAC0_RSSEL  ====================================================== */
34601  #define R_DMA_DMAC0_RSSEL_REQ_SELA_Pos    (0UL)          /*!< REQ_SELA (Bit 0)                                      */
34602  #define R_DMA_DMAC0_RSSEL_REQ_SELA_Msk    (0x1ffUL)      /*!< REQ_SELA (Bitfield-Mask: 0x1ff)                       */
34603  #define R_DMA_DMAC0_RSSEL_REQ_SELB_Pos    (10UL)         /*!< REQ_SELB (Bit 10)                                     */
34604  #define R_DMA_DMAC0_RSSEL_REQ_SELB_Msk    (0x7fc00UL)    /*!< REQ_SELB (Bitfield-Mask: 0x1ff)                       */
34605  #define R_DMA_DMAC0_RSSEL_REQ_SELC_Pos    (20UL)         /*!< REQ_SELC (Bit 20)                                     */
34606  #define R_DMA_DMAC0_RSSEL_REQ_SELC_Msk    (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff)                       */
34607 /* ======================================================  DMAC1_RSSEL  ====================================================== */
34608  #define R_DMA_DMAC1_RSSEL_REQ_SELA_Pos    (0UL)          /*!< REQ_SELA (Bit 0)                                      */
34609  #define R_DMA_DMAC1_RSSEL_REQ_SELA_Msk    (0x1ffUL)      /*!< REQ_SELA (Bitfield-Mask: 0x1ff)                       */
34610  #define R_DMA_DMAC1_RSSEL_REQ_SELB_Pos    (10UL)         /*!< REQ_SELB (Bit 10)                                     */
34611  #define R_DMA_DMAC1_RSSEL_REQ_SELB_Msk    (0x7fc00UL)    /*!< REQ_SELB (Bitfield-Mask: 0x1ff)                       */
34612  #define R_DMA_DMAC1_RSSEL_REQ_SELC_Pos    (20UL)         /*!< REQ_SELC (Bit 20)                                     */
34613  #define R_DMA_DMAC1_RSSEL_REQ_SELC_Msk    (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff)                       */
34614 
34615 /* =========================================================================================================================== */
34616 /* ================                                       R_PORT_COMMON                                       ================ */
34617 /* =========================================================================================================================== */
34618 
34619 /* ===========================================================  P  =========================================================== */
34620  #define R_PORT_NSR_P_POUT_0_Pos          (0UL)          /*!< POUT_0 (Bit 0)                                        */
34621  #define R_PORT_NSR_P_POUT_0_Msk          (0x1UL)        /*!< POUT_0 (Bitfield-Mask: 0x01)                          */
34622  #define R_PORT_NSR_P_POUT_1_Pos          (1UL)          /*!< POUT_1 (Bit 1)                                        */
34623  #define R_PORT_NSR_P_POUT_1_Msk          (0x2UL)        /*!< POUT_1 (Bitfield-Mask: 0x01)                          */
34624  #define R_PORT_NSR_P_POUT_2_Pos          (2UL)          /*!< POUT_2 (Bit 2)                                        */
34625  #define R_PORT_NSR_P_POUT_2_Msk          (0x4UL)        /*!< POUT_2 (Bitfield-Mask: 0x01)                          */
34626  #define R_PORT_NSR_P_POUT_3_Pos          (3UL)          /*!< POUT_3 (Bit 3)                                        */
34627  #define R_PORT_NSR_P_POUT_3_Msk          (0x8UL)        /*!< POUT_3 (Bitfield-Mask: 0x01)                          */
34628  #define R_PORT_NSR_P_POUT_4_Pos          (4UL)          /*!< POUT_4 (Bit 4)                                        */
34629  #define R_PORT_NSR_P_POUT_4_Msk          (0x10UL)       /*!< POUT_4 (Bitfield-Mask: 0x01)                          */
34630  #define R_PORT_NSR_P_POUT_5_Pos          (5UL)          /*!< POUT_5 (Bit 5)                                        */
34631  #define R_PORT_NSR_P_POUT_5_Msk          (0x20UL)       /*!< POUT_5 (Bitfield-Mask: 0x01)                          */
34632  #define R_PORT_NSR_P_POUT_6_Pos          (6UL)          /*!< POUT_6 (Bit 6)                                        */
34633  #define R_PORT_NSR_P_POUT_6_Msk          (0x40UL)       /*!< POUT_6 (Bitfield-Mask: 0x01)                          */
34634  #define R_PORT_NSR_P_POUT_7_Pos          (7UL)          /*!< POUT_7 (Bit 7)                                        */
34635  #define R_PORT_NSR_P_POUT_7_Msk          (0x80UL)       /*!< POUT_7 (Bitfield-Mask: 0x01)                          */
34636 /* ==========================================================  PM  =========================================================== */
34637  #define R_PORT_NSR_PM_PM0_Pos            (0UL)          /*!< PM0 (Bit 0)                                           */
34638  #define R_PORT_NSR_PM_PM0_Msk            (0x3UL)        /*!< PM0 (Bitfield-Mask: 0x03)                             */
34639  #define R_PORT_NSR_PM_PM1_Pos            (2UL)          /*!< PM1 (Bit 2)                                           */
34640  #define R_PORT_NSR_PM_PM1_Msk            (0xcUL)        /*!< PM1 (Bitfield-Mask: 0x03)                             */
34641  #define R_PORT_NSR_PM_PM2_Pos            (4UL)          /*!< PM2 (Bit 4)                                           */
34642  #define R_PORT_NSR_PM_PM2_Msk            (0x30UL)       /*!< PM2 (Bitfield-Mask: 0x03)                             */
34643  #define R_PORT_NSR_PM_PM3_Pos            (6UL)          /*!< PM3 (Bit 6)                                           */
34644  #define R_PORT_NSR_PM_PM3_Msk            (0xc0UL)       /*!< PM3 (Bitfield-Mask: 0x03)                             */
34645  #define R_PORT_NSR_PM_PM4_Pos            (8UL)          /*!< PM4 (Bit 8)                                           */
34646  #define R_PORT_NSR_PM_PM4_Msk            (0x300UL)      /*!< PM4 (Bitfield-Mask: 0x03)                             */
34647  #define R_PORT_NSR_PM_PM5_Pos            (10UL)         /*!< PM5 (Bit 10)                                          */
34648  #define R_PORT_NSR_PM_PM5_Msk            (0xc00UL)      /*!< PM5 (Bitfield-Mask: 0x03)                             */
34649  #define R_PORT_NSR_PM_PM6_Pos            (12UL)         /*!< PM6 (Bit 12)                                          */
34650  #define R_PORT_NSR_PM_PM6_Msk            (0x3000UL)     /*!< PM6 (Bitfield-Mask: 0x03)                             */
34651  #define R_PORT_NSR_PM_PM7_Pos            (14UL)         /*!< PM7 (Bit 14)                                          */
34652  #define R_PORT_NSR_PM_PM7_Msk            (0xc000UL)     /*!< PM7 (Bitfield-Mask: 0x03)                             */
34653 /* ==========================================================  PMC  ========================================================== */
34654  #define R_PORT_NSR_PMC_PMC0_Pos          (0UL)          /*!< PMC0 (Bit 0)                                          */
34655  #define R_PORT_NSR_PMC_PMC0_Msk          (0x1UL)        /*!< PMC0 (Bitfield-Mask: 0x01)                            */
34656  #define R_PORT_NSR_PMC_PMC1_Pos          (1UL)          /*!< PMC1 (Bit 1)                                          */
34657  #define R_PORT_NSR_PMC_PMC1_Msk          (0x2UL)        /*!< PMC1 (Bitfield-Mask: 0x01)                            */
34658  #define R_PORT_NSR_PMC_PMC2_Pos          (2UL)          /*!< PMC2 (Bit 2)                                          */
34659  #define R_PORT_NSR_PMC_PMC2_Msk          (0x4UL)        /*!< PMC2 (Bitfield-Mask: 0x01)                            */
34660  #define R_PORT_NSR_PMC_PMC3_Pos          (3UL)          /*!< PMC3 (Bit 3)                                          */
34661  #define R_PORT_NSR_PMC_PMC3_Msk          (0x8UL)        /*!< PMC3 (Bitfield-Mask: 0x01)                            */
34662  #define R_PORT_NSR_PMC_PMC4_Pos          (4UL)          /*!< PMC4 (Bit 4)                                          */
34663  #define R_PORT_NSR_PMC_PMC4_Msk          (0x10UL)       /*!< PMC4 (Bitfield-Mask: 0x01)                            */
34664  #define R_PORT_NSR_PMC_PMC5_Pos          (5UL)          /*!< PMC5 (Bit 5)                                          */
34665  #define R_PORT_NSR_PMC_PMC5_Msk          (0x20UL)       /*!< PMC5 (Bitfield-Mask: 0x01)                            */
34666  #define R_PORT_NSR_PMC_PMC6_Pos          (6UL)          /*!< PMC6 (Bit 6)                                          */
34667  #define R_PORT_NSR_PMC_PMC6_Msk          (0x40UL)       /*!< PMC6 (Bitfield-Mask: 0x01)                            */
34668  #define R_PORT_NSR_PMC_PMC7_Pos          (7UL)          /*!< PMC7 (Bit 7)                                          */
34669  #define R_PORT_NSR_PMC_PMC7_Msk          (0x80UL)       /*!< PMC7 (Bitfield-Mask: 0x01)                            */
34670 /* ==========================================================  PFC  ========================================================== */
34671  #define R_PORT_NSR_PFC_PFC0_Pos          (0UL)          /*!< PFC0 (Bit 0)                                          */
34672  #define R_PORT_NSR_PFC_PFC0_Msk          (0xfUL)        /*!< PFC0 (Bitfield-Mask: 0x0f)                            */
34673  #define R_PORT_NSR_PFC_PFC1_Pos          (4UL)          /*!< PFC1 (Bit 4)                                          */
34674  #define R_PORT_NSR_PFC_PFC1_Msk          (0xf0UL)       /*!< PFC1 (Bitfield-Mask: 0x0f)                            */
34675  #define R_PORT_NSR_PFC_PFC2_Pos          (8UL)          /*!< PFC2 (Bit 8)                                          */
34676  #define R_PORT_NSR_PFC_PFC2_Msk          (0xf00UL)      /*!< PFC2 (Bitfield-Mask: 0x0f)                            */
34677  #define R_PORT_NSR_PFC_PFC3_Pos          (12UL)         /*!< PFC3 (Bit 12)                                         */
34678  #define R_PORT_NSR_PFC_PFC3_Msk          (0xf000UL)     /*!< PFC3 (Bitfield-Mask: 0x0f)                            */
34679  #define R_PORT_NSR_PFC_PFC4_Pos          (16UL)         /*!< PFC4 (Bit 16)                                         */
34680  #define R_PORT_NSR_PFC_PFC4_Msk          (0xf0000UL)    /*!< PFC4 (Bitfield-Mask: 0x0f)                            */
34681  #define R_PORT_NSR_PFC_PFC5_Pos          (20UL)         /*!< PFC5 (Bit 20)                                         */
34682  #define R_PORT_NSR_PFC_PFC5_Msk          (0xf00000UL)   /*!< PFC5 (Bitfield-Mask: 0x0f)                            */
34683  #define R_PORT_NSR_PFC_PFC6_Pos          (24UL)         /*!< PFC6 (Bit 24)                                         */
34684  #define R_PORT_NSR_PFC_PFC6_Msk          (0xf000000UL)  /*!< PFC6 (Bitfield-Mask: 0x0f)                            */
34685  #define R_PORT_NSR_PFC_PFC7_Pos          (28UL)         /*!< PFC7 (Bit 28)                                         */
34686  #define R_PORT_NSR_PFC_PFC7_Msk          (0xf0000000UL) /*!< PFC7 (Bitfield-Mask: 0x0f)                            */
34687 /* ==========================================================  PIN  ========================================================== */
34688  #define R_PORT_NSR_PIN_PIN0_Pos          (0UL)          /*!< PIN0 (Bit 0)                                          */
34689  #define R_PORT_NSR_PIN_PIN0_Msk          (0x1UL)        /*!< PIN0 (Bitfield-Mask: 0x01)                            */
34690  #define R_PORT_NSR_PIN_PIN1_Pos          (1UL)          /*!< PIN1 (Bit 1)                                          */
34691  #define R_PORT_NSR_PIN_PIN1_Msk          (0x2UL)        /*!< PIN1 (Bitfield-Mask: 0x01)                            */
34692  #define R_PORT_NSR_PIN_PIN2_Pos          (2UL)          /*!< PIN2 (Bit 2)                                          */
34693  #define R_PORT_NSR_PIN_PIN2_Msk          (0x4UL)        /*!< PIN2 (Bitfield-Mask: 0x01)                            */
34694  #define R_PORT_NSR_PIN_PIN3_Pos          (3UL)          /*!< PIN3 (Bit 3)                                          */
34695  #define R_PORT_NSR_PIN_PIN3_Msk          (0x8UL)        /*!< PIN3 (Bitfield-Mask: 0x01)                            */
34696  #define R_PORT_NSR_PIN_PIN4_Pos          (4UL)          /*!< PIN4 (Bit 4)                                          */
34697  #define R_PORT_NSR_PIN_PIN4_Msk          (0x10UL)       /*!< PIN4 (Bitfield-Mask: 0x01)                            */
34698  #define R_PORT_NSR_PIN_PIN5_Pos          (5UL)          /*!< PIN5 (Bit 5)                                          */
34699  #define R_PORT_NSR_PIN_PIN5_Msk          (0x20UL)       /*!< PIN5 (Bitfield-Mask: 0x01)                            */
34700  #define R_PORT_NSR_PIN_PIN6_Pos          (6UL)          /*!< PIN6 (Bit 6)                                          */
34701  #define R_PORT_NSR_PIN_PIN6_Msk          (0x40UL)       /*!< PIN6 (Bitfield-Mask: 0x01)                            */
34702  #define R_PORT_NSR_PIN_PIN7_Pos          (7UL)          /*!< PIN7 (Bit 7)                                          */
34703  #define R_PORT_NSR_PIN_PIN7_Msk          (0x80UL)       /*!< PIN7 (Bitfield-Mask: 0x01)                            */
34704 /* ========================================================  ELC_PGR  ======================================================== */
34705  #define R_PORT_NSR_ELC_PGR_PG0_Pos       (0UL)          /*!< PG0 (Bit 0)                                           */
34706  #define R_PORT_NSR_ELC_PGR_PG0_Msk       (0x1UL)        /*!< PG0 (Bitfield-Mask: 0x01)                             */
34707  #define R_PORT_NSR_ELC_PGR_PG1_Pos       (1UL)          /*!< PG1 (Bit 1)                                           */
34708  #define R_PORT_NSR_ELC_PGR_PG1_Msk       (0x2UL)        /*!< PG1 (Bitfield-Mask: 0x01)                             */
34709  #define R_PORT_NSR_ELC_PGR_PG2_Pos       (2UL)          /*!< PG2 (Bit 2)                                           */
34710  #define R_PORT_NSR_ELC_PGR_PG2_Msk       (0x4UL)        /*!< PG2 (Bitfield-Mask: 0x01)                             */
34711  #define R_PORT_NSR_ELC_PGR_PG3_Pos       (3UL)          /*!< PG3 (Bit 3)                                           */
34712  #define R_PORT_NSR_ELC_PGR_PG3_Msk       (0x8UL)        /*!< PG3 (Bitfield-Mask: 0x01)                             */
34713  #define R_PORT_NSR_ELC_PGR_PG4_Pos       (4UL)          /*!< PG4 (Bit 4)                                           */
34714  #define R_PORT_NSR_ELC_PGR_PG4_Msk       (0x10UL)       /*!< PG4 (Bitfield-Mask: 0x01)                             */
34715  #define R_PORT_NSR_ELC_PGR_PG5_Pos       (5UL)          /*!< PG5 (Bit 5)                                           */
34716  #define R_PORT_NSR_ELC_PGR_PG5_Msk       (0x20UL)       /*!< PG5 (Bitfield-Mask: 0x01)                             */
34717  #define R_PORT_NSR_ELC_PGR_PG6_Pos       (6UL)          /*!< PG6 (Bit 6)                                           */
34718  #define R_PORT_NSR_ELC_PGR_PG6_Msk       (0x40UL)       /*!< PG6 (Bitfield-Mask: 0x01)                             */
34719  #define R_PORT_NSR_ELC_PGR_PG7_Pos       (7UL)          /*!< PG7 (Bit 7)                                           */
34720  #define R_PORT_NSR_ELC_PGR_PG7_Msk       (0x80UL)       /*!< PG7 (Bitfield-Mask: 0x01)                             */
34721 /* ========================================================  ELC_PGC  ======================================================== */
34722  #define R_PORT_NSR_ELC_PGC_PGCI_Pos      (0UL)          /*!< PGCI (Bit 0)                                          */
34723  #define R_PORT_NSR_ELC_PGC_PGCI_Msk      (0x3UL)        /*!< PGCI (Bitfield-Mask: 0x03)                            */
34724  #define R_PORT_NSR_ELC_PGC_PGCOVE_Pos    (2UL)          /*!< PGCOVE (Bit 2)                                        */
34725  #define R_PORT_NSR_ELC_PGC_PGCOVE_Msk    (0x4UL)        /*!< PGCOVE (Bitfield-Mask: 0x01)                          */
34726  #define R_PORT_NSR_ELC_PGC_PGCO_Pos      (4UL)          /*!< PGCO (Bit 4)                                          */
34727  #define R_PORT_NSR_ELC_PGC_PGCO_Msk      (0x70UL)       /*!< PGCO (Bitfield-Mask: 0x07)                            */
34728 /* ========================================================  ELC_PEL  ======================================================== */
34729  #define R_PORT_NSR_ELC_PEL_PSB_Pos       (0UL)          /*!< PSB (Bit 0)                                           */
34730  #define R_PORT_NSR_ELC_PEL_PSB_Msk       (0x7UL)        /*!< PSB (Bitfield-Mask: 0x07)                             */
34731  #define R_PORT_NSR_ELC_PEL_PSP_Pos       (3UL)          /*!< PSP (Bit 3)                                           */
34732  #define R_PORT_NSR_ELC_PEL_PSP_Msk       (0x18UL)       /*!< PSP (Bitfield-Mask: 0x03)                             */
34733  #define R_PORT_NSR_ELC_PEL_PSM_Pos       (5UL)          /*!< PSM (Bit 5)                                           */
34734  #define R_PORT_NSR_ELC_PEL_PSM_Msk       (0x60UL)       /*!< PSM (Bitfield-Mask: 0x03)                             */
34735 /* =======================================================  ELC_DPTC  ======================================================== */
34736  #define R_PORT_NSR_ELC_DPTC_PTC0_Pos     (0UL)          /*!< PTC0 (Bit 0)                                          */
34737  #define R_PORT_NSR_ELC_DPTC_PTC0_Msk     (0x1UL)        /*!< PTC0 (Bitfield-Mask: 0x01)                            */
34738  #define R_PORT_NSR_ELC_DPTC_PTC1_Pos     (1UL)          /*!< PTC1 (Bit 1)                                          */
34739  #define R_PORT_NSR_ELC_DPTC_PTC1_Msk     (0x2UL)        /*!< PTC1 (Bitfield-Mask: 0x01)                            */
34740  #define R_PORT_NSR_ELC_DPTC_PTC2_Pos     (2UL)          /*!< PTC2 (Bit 2)                                          */
34741  #define R_PORT_NSR_ELC_DPTC_PTC2_Msk     (0x4UL)        /*!< PTC2 (Bitfield-Mask: 0x01)                            */
34742  #define R_PORT_NSR_ELC_DPTC_PTC3_Pos     (3UL)          /*!< PTC3 (Bit 3)                                          */
34743  #define R_PORT_NSR_ELC_DPTC_PTC3_Msk     (0x8UL)        /*!< PTC3 (Bitfield-Mask: 0x01)                            */
34744 /* =======================================================  ELC_ELSR2  ======================================================= */
34745  #define R_PORT_NSR_ELC_ELSR2_PEG1_Pos    (2UL)          /*!< PEG1 (Bit 2)                                          */
34746  #define R_PORT_NSR_ELC_ELSR2_PEG1_Msk    (0x4UL)        /*!< PEG1 (Bitfield-Mask: 0x01)                            */
34747  #define R_PORT_NSR_ELC_ELSR2_PEG2_Pos    (3UL)          /*!< PEG2 (Bit 3)                                          */
34748  #define R_PORT_NSR_ELC_ELSR2_PEG2_Msk    (0x8UL)        /*!< PEG2 (Bitfield-Mask: 0x01)                            */
34749  #define R_PORT_NSR_ELC_ELSR2_PES0_Pos    (4UL)          /*!< PES0 (Bit 4)                                          */
34750  #define R_PORT_NSR_ELC_ELSR2_PES0_Msk    (0x10UL)       /*!< PES0 (Bitfield-Mask: 0x01)                            */
34751  #define R_PORT_NSR_ELC_ELSR2_PES1_Pos    (5UL)          /*!< PES1 (Bit 5)                                          */
34752  #define R_PORT_NSR_ELC_ELSR2_PES1_Msk    (0x20UL)       /*!< PES1 (Bitfield-Mask: 0x01)                            */
34753  #define R_PORT_NSR_ELC_ELSR2_PES2_Pos    (6UL)          /*!< PES2 (Bit 6)                                          */
34754  #define R_PORT_NSR_ELC_ELSR2_PES2_Msk    (0x40UL)       /*!< PES2 (Bitfield-Mask: 0x01)                            */
34755  #define R_PORT_NSR_ELC_ELSR2_PES3_Pos    (7UL)          /*!< PES3 (Bit 7)                                          */
34756  #define R_PORT_NSR_ELC_ELSR2_PES3_Msk    (0x80UL)       /*!< PES3 (Bitfield-Mask: 0x01)                            */
34757 
34758 /* =========================================================================================================================== */
34759 /* ================                                          R_GMAC                                           ================ */
34760 /* =========================================================================================================================== */
34761 
34762 /* ===================================================  MAC_Configuration  =================================================== */
34763  #define R_GMAC_MAC_Configuration_PRELEN_Pos                              (0UL)          /*!< PRELEN (Bit 0)                                        */
34764  #define R_GMAC_MAC_Configuration_PRELEN_Msk                              (0x3UL)        /*!< PRELEN (Bitfield-Mask: 0x03)                          */
34765  #define R_GMAC_MAC_Configuration_RE_Pos                                  (2UL)          /*!< RE (Bit 2)                                            */
34766  #define R_GMAC_MAC_Configuration_RE_Msk                                  (0x4UL)        /*!< RE (Bitfield-Mask: 0x01)                              */
34767  #define R_GMAC_MAC_Configuration_TE_Pos                                  (3UL)          /*!< TE (Bit 3)                                            */
34768  #define R_GMAC_MAC_Configuration_TE_Msk                                  (0x8UL)        /*!< TE (Bitfield-Mask: 0x01)                              */
34769  #define R_GMAC_MAC_Configuration_DC_Pos                                  (4UL)          /*!< DC (Bit 4)                                            */
34770  #define R_GMAC_MAC_Configuration_DC_Msk                                  (0x10UL)       /*!< DC (Bitfield-Mask: 0x01)                              */
34771  #define R_GMAC_MAC_Configuration_BL_Pos                                  (5UL)          /*!< BL (Bit 5)                                            */
34772  #define R_GMAC_MAC_Configuration_BL_Msk                                  (0x60UL)       /*!< BL (Bitfield-Mask: 0x03)                              */
34773  #define R_GMAC_MAC_Configuration_ACS_Pos                                 (7UL)          /*!< ACS (Bit 7)                                           */
34774  #define R_GMAC_MAC_Configuration_ACS_Msk                                 (0x80UL)       /*!< ACS (Bitfield-Mask: 0x01)                             */
34775  #define R_GMAC_MAC_Configuration_DR_Pos                                  (9UL)          /*!< DR (Bit 9)                                            */
34776  #define R_GMAC_MAC_Configuration_DR_Msk                                  (0x200UL)      /*!< DR (Bitfield-Mask: 0x01)                              */
34777  #define R_GMAC_MAC_Configuration_IPC_Pos                                 (10UL)         /*!< IPC (Bit 10)                                          */
34778  #define R_GMAC_MAC_Configuration_IPC_Msk                                 (0x400UL)      /*!< IPC (Bitfield-Mask: 0x01)                             */
34779  #define R_GMAC_MAC_Configuration_DM_Pos                                  (11UL)         /*!< DM (Bit 11)                                           */
34780  #define R_GMAC_MAC_Configuration_DM_Msk                                  (0x800UL)      /*!< DM (Bitfield-Mask: 0x01)                              */
34781  #define R_GMAC_MAC_Configuration_LM_Pos                                  (12UL)         /*!< LM (Bit 12)                                           */
34782  #define R_GMAC_MAC_Configuration_LM_Msk                                  (0x1000UL)     /*!< LM (Bitfield-Mask: 0x01)                              */
34783  #define R_GMAC_MAC_Configuration_DO_Pos                                  (13UL)         /*!< DO (Bit 13)                                           */
34784  #define R_GMAC_MAC_Configuration_DO_Msk                                  (0x2000UL)     /*!< DO (Bitfield-Mask: 0x01)                              */
34785  #define R_GMAC_MAC_Configuration_FES_Pos                                 (14UL)         /*!< FES (Bit 14)                                          */
34786  #define R_GMAC_MAC_Configuration_FES_Msk                                 (0x4000UL)     /*!< FES (Bitfield-Mask: 0x01)                             */
34787  #define R_GMAC_MAC_Configuration_PS_Pos                                  (15UL)         /*!< PS (Bit 15)                                           */
34788  #define R_GMAC_MAC_Configuration_PS_Msk                                  (0x8000UL)     /*!< PS (Bitfield-Mask: 0x01)                              */
34789  #define R_GMAC_MAC_Configuration_DCRS_Pos                                (16UL)         /*!< DCRS (Bit 16)                                         */
34790  #define R_GMAC_MAC_Configuration_DCRS_Msk                                (0x10000UL)    /*!< DCRS (Bitfield-Mask: 0x01)                            */
34791  #define R_GMAC_MAC_Configuration_IFG_Pos                                 (17UL)         /*!< IFG (Bit 17)                                          */
34792  #define R_GMAC_MAC_Configuration_IFG_Msk                                 (0xe0000UL)    /*!< IFG (Bitfield-Mask: 0x07)                             */
34793  #define R_GMAC_MAC_Configuration_JE_Pos                                  (20UL)         /*!< JE (Bit 20)                                           */
34794  #define R_GMAC_MAC_Configuration_JE_Msk                                  (0x100000UL)   /*!< JE (Bitfield-Mask: 0x01)                              */
34795  #define R_GMAC_MAC_Configuration_BE_Pos                                  (21UL)         /*!< BE (Bit 21)                                           */
34796  #define R_GMAC_MAC_Configuration_BE_Msk                                  (0x200000UL)   /*!< BE (Bitfield-Mask: 0x01)                              */
34797  #define R_GMAC_MAC_Configuration_JD_Pos                                  (22UL)         /*!< JD (Bit 22)                                           */
34798  #define R_GMAC_MAC_Configuration_JD_Msk                                  (0x400000UL)   /*!< JD (Bitfield-Mask: 0x01)                              */
34799  #define R_GMAC_MAC_Configuration_WD_Pos                                  (23UL)         /*!< WD (Bit 23)                                           */
34800  #define R_GMAC_MAC_Configuration_WD_Msk                                  (0x800000UL)   /*!< WD (Bitfield-Mask: 0x01)                              */
34801  #define R_GMAC_MAC_Configuration_CST_Pos                                 (25UL)         /*!< CST (Bit 25)                                          */
34802  #define R_GMAC_MAC_Configuration_CST_Msk                                 (0x2000000UL)  /*!< CST (Bitfield-Mask: 0x01)                             */
34803  #define R_GMAC_MAC_Configuration_TWOKPE_Pos                              (27UL)         /*!< TWOKPE (Bit 27)                                       */
34804  #define R_GMAC_MAC_Configuration_TWOKPE_Msk                              (0x8000000UL)  /*!< TWOKPE (Bitfield-Mask: 0x01)                          */
34805 /* ===================================================  MAC_Frame_Filter  ==================================================== */
34806  #define R_GMAC_MAC_Frame_Filter_PR_Pos                                   (0UL)          /*!< PR (Bit 0)                                            */
34807  #define R_GMAC_MAC_Frame_Filter_PR_Msk                                   (0x1UL)        /*!< PR (Bitfield-Mask: 0x01)                              */
34808  #define R_GMAC_MAC_Frame_Filter_HUC_Pos                                  (1UL)          /*!< HUC (Bit 1)                                           */
34809  #define R_GMAC_MAC_Frame_Filter_HUC_Msk                                  (0x2UL)        /*!< HUC (Bitfield-Mask: 0x01)                             */
34810  #define R_GMAC_MAC_Frame_Filter_HMC_Pos                                  (2UL)          /*!< HMC (Bit 2)                                           */
34811  #define R_GMAC_MAC_Frame_Filter_HMC_Msk                                  (0x4UL)        /*!< HMC (Bitfield-Mask: 0x01)                             */
34812  #define R_GMAC_MAC_Frame_Filter_DAIF_Pos                                 (3UL)          /*!< DAIF (Bit 3)                                          */
34813  #define R_GMAC_MAC_Frame_Filter_DAIF_Msk                                 (0x8UL)        /*!< DAIF (Bitfield-Mask: 0x01)                            */
34814  #define R_GMAC_MAC_Frame_Filter_PM_Pos                                   (4UL)          /*!< PM (Bit 4)                                            */
34815  #define R_GMAC_MAC_Frame_Filter_PM_Msk                                   (0x10UL)       /*!< PM (Bitfield-Mask: 0x01)                              */
34816  #define R_GMAC_MAC_Frame_Filter_DBF_Pos                                  (5UL)          /*!< DBF (Bit 5)                                           */
34817  #define R_GMAC_MAC_Frame_Filter_DBF_Msk                                  (0x20UL)       /*!< DBF (Bitfield-Mask: 0x01)                             */
34818  #define R_GMAC_MAC_Frame_Filter_PCF_Pos                                  (6UL)          /*!< PCF (Bit 6)                                           */
34819  #define R_GMAC_MAC_Frame_Filter_PCF_Msk                                  (0xc0UL)       /*!< PCF (Bitfield-Mask: 0x03)                             */
34820  #define R_GMAC_MAC_Frame_Filter_SAIF_Pos                                 (8UL)          /*!< SAIF (Bit 8)                                          */
34821  #define R_GMAC_MAC_Frame_Filter_SAIF_Msk                                 (0x100UL)      /*!< SAIF (Bitfield-Mask: 0x01)                            */
34822  #define R_GMAC_MAC_Frame_Filter_SAF_Pos                                  (9UL)          /*!< SAF (Bit 9)                                           */
34823  #define R_GMAC_MAC_Frame_Filter_SAF_Msk                                  (0x200UL)      /*!< SAF (Bitfield-Mask: 0x01)                             */
34824  #define R_GMAC_MAC_Frame_Filter_HPF_Pos                                  (10UL)         /*!< HPF (Bit 10)                                          */
34825  #define R_GMAC_MAC_Frame_Filter_HPF_Msk                                  (0x400UL)      /*!< HPF (Bitfield-Mask: 0x01)                             */
34826  #define R_GMAC_MAC_Frame_Filter_VTFE_Pos                                 (16UL)         /*!< VTFE (Bit 16)                                         */
34827  #define R_GMAC_MAC_Frame_Filter_VTFE_Msk                                 (0x10000UL)    /*!< VTFE (Bitfield-Mask: 0x01)                            */
34828  #define R_GMAC_MAC_Frame_Filter_RA_Pos                                   (31UL)         /*!< RA (Bit 31)                                           */
34829  #define R_GMAC_MAC_Frame_Filter_RA_Msk                                   (0x80000000UL) /*!< RA (Bitfield-Mask: 0x01)                              */
34830 /* =====================================================  GMII_Address  ====================================================== */
34831  #define R_GMAC_GMII_Address_GB_Pos                                       (0UL)          /*!< GB (Bit 0)                                            */
34832  #define R_GMAC_GMII_Address_GB_Msk                                       (0x1UL)        /*!< GB (Bitfield-Mask: 0x01)                              */
34833  #define R_GMAC_GMII_Address_GW_Pos                                       (1UL)          /*!< GW (Bit 1)                                            */
34834  #define R_GMAC_GMII_Address_GW_Msk                                       (0x2UL)        /*!< GW (Bitfield-Mask: 0x01)                              */
34835  #define R_GMAC_GMII_Address_CR_Pos                                       (2UL)          /*!< CR (Bit 2)                                            */
34836  #define R_GMAC_GMII_Address_CR_Msk                                       (0x3cUL)       /*!< CR (Bitfield-Mask: 0x0f)                              */
34837  #define R_GMAC_GMII_Address_GR_Pos                                       (6UL)          /*!< GR (Bit 6)                                            */
34838  #define R_GMAC_GMII_Address_GR_Msk                                       (0x7c0UL)      /*!< GR (Bitfield-Mask: 0x1f)                              */
34839  #define R_GMAC_GMII_Address_PA_Pos                                       (11UL)         /*!< PA (Bit 11)                                           */
34840  #define R_GMAC_GMII_Address_PA_Msk                                       (0xf800UL)     /*!< PA (Bitfield-Mask: 0x1f)                              */
34841 /* =======================================================  GMII_Data  ======================================================= */
34842  #define R_GMAC_GMII_Data_GD_Pos                                          (0UL)          /*!< GD (Bit 0)                                            */
34843  #define R_GMAC_GMII_Data_GD_Msk                                          (0xffffUL)     /*!< GD (Bitfield-Mask: 0xffff)                            */
34844 /* =====================================================  Flow_Control  ====================================================== */
34845  #define R_GMAC_Flow_Control_FCA_BPA_Pos                                  (0UL)          /*!< FCA_BPA (Bit 0)                                       */
34846  #define R_GMAC_Flow_Control_FCA_BPA_Msk                                  (0x1UL)        /*!< FCA_BPA (Bitfield-Mask: 0x01)                         */
34847  #define R_GMAC_Flow_Control_TFE_Pos                                      (1UL)          /*!< TFE (Bit 1)                                           */
34848  #define R_GMAC_Flow_Control_TFE_Msk                                      (0x2UL)        /*!< TFE (Bitfield-Mask: 0x01)                             */
34849  #define R_GMAC_Flow_Control_RFE_Pos                                      (2UL)          /*!< RFE (Bit 2)                                           */
34850  #define R_GMAC_Flow_Control_RFE_Msk                                      (0x4UL)        /*!< RFE (Bitfield-Mask: 0x01)                             */
34851  #define R_GMAC_Flow_Control_UP_Pos                                       (3UL)          /*!< UP (Bit 3)                                            */
34852  #define R_GMAC_Flow_Control_UP_Msk                                       (0x8UL)        /*!< UP (Bitfield-Mask: 0x01)                              */
34853  #define R_GMAC_Flow_Control_PLT_Pos                                      (4UL)          /*!< PLT (Bit 4)                                           */
34854  #define R_GMAC_Flow_Control_PLT_Msk                                      (0x30UL)       /*!< PLT (Bitfield-Mask: 0x03)                             */
34855  #define R_GMAC_Flow_Control_DZPQ_Pos                                     (7UL)          /*!< DZPQ (Bit 7)                                          */
34856  #define R_GMAC_Flow_Control_DZPQ_Msk                                     (0x80UL)       /*!< DZPQ (Bitfield-Mask: 0x01)                            */
34857  #define R_GMAC_Flow_Control_PT_Pos                                       (16UL)         /*!< PT (Bit 16)                                           */
34858  #define R_GMAC_Flow_Control_PT_Msk                                       (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff)                            */
34859 /* =======================================================  VLAN_Tag  ======================================================== */
34860  #define R_GMAC_VLAN_Tag_VL_Pos                                           (0UL)          /*!< VL (Bit 0)                                            */
34861  #define R_GMAC_VLAN_Tag_VL_Msk                                           (0xffffUL)     /*!< VL (Bitfield-Mask: 0xffff)                            */
34862  #define R_GMAC_VLAN_Tag_ETV_Pos                                          (16UL)         /*!< ETV (Bit 16)                                          */
34863  #define R_GMAC_VLAN_Tag_ETV_Msk                                          (0x10000UL)    /*!< ETV (Bitfield-Mask: 0x01)                             */
34864  #define R_GMAC_VLAN_Tag_VTIM_Pos                                         (17UL)         /*!< VTIM (Bit 17)                                         */
34865  #define R_GMAC_VLAN_Tag_VTIM_Msk                                         (0x20000UL)    /*!< VTIM (Bitfield-Mask: 0x01)                            */
34866  #define R_GMAC_VLAN_Tag_ESVL_Pos                                         (18UL)         /*!< ESVL (Bit 18)                                         */
34867  #define R_GMAC_VLAN_Tag_ESVL_Msk                                         (0x40000UL)    /*!< ESVL (Bitfield-Mask: 0x01)                            */
34868  #define R_GMAC_VLAN_Tag_VTHM_Pos                                         (19UL)         /*!< VTHM (Bit 19)                                         */
34869  #define R_GMAC_VLAN_Tag_VTHM_Msk                                         (0x80000UL)    /*!< VTHM (Bitfield-Mask: 0x01)                            */
34870 /* ========================================================  Version  ======================================================== */
34871  #define R_GMAC_Version_VER_Pos                                           (0UL)          /*!< VER (Bit 0)                                           */
34872  #define R_GMAC_Version_VER_Msk                                           (0xffffUL)     /*!< VER (Bitfield-Mask: 0xffff)                           */
34873 /* =========================================================  Debug  ========================================================= */
34874  #define R_GMAC_Debug_RPESTS_Pos                                          (0UL)          /*!< RPESTS (Bit 0)                                        */
34875  #define R_GMAC_Debug_RPESTS_Msk                                          (0x1UL)        /*!< RPESTS (Bitfield-Mask: 0x01)                          */
34876  #define R_GMAC_Debug_RFCFCSTS_Pos                                        (1UL)          /*!< RFCFCSTS (Bit 1)                                      */
34877  #define R_GMAC_Debug_RFCFCSTS_Msk                                        (0x6UL)        /*!< RFCFCSTS (Bitfield-Mask: 0x03)                        */
34878  #define R_GMAC_Debug_RWCSTS_Pos                                          (4UL)          /*!< RWCSTS (Bit 4)                                        */
34879  #define R_GMAC_Debug_RWCSTS_Msk                                          (0x10UL)       /*!< RWCSTS (Bitfield-Mask: 0x01)                          */
34880  #define R_GMAC_Debug_RRCSTS_Pos                                          (5UL)          /*!< RRCSTS (Bit 5)                                        */
34881  #define R_GMAC_Debug_RRCSTS_Msk                                          (0x60UL)       /*!< RRCSTS (Bitfield-Mask: 0x03)                          */
34882  #define R_GMAC_Debug_RXFSTS_Pos                                          (8UL)          /*!< RXFSTS (Bit 8)                                        */
34883  #define R_GMAC_Debug_RXFSTS_Msk                                          (0x300UL)      /*!< RXFSTS (Bitfield-Mask: 0x03)                          */
34884  #define R_GMAC_Debug_TPESTS_Pos                                          (16UL)         /*!< TPESTS (Bit 16)                                       */
34885  #define R_GMAC_Debug_TPESTS_Msk                                          (0x10000UL)    /*!< TPESTS (Bitfield-Mask: 0x01)                          */
34886  #define R_GMAC_Debug_TFCSTS_Pos                                          (17UL)         /*!< TFCSTS (Bit 17)                                       */
34887  #define R_GMAC_Debug_TFCSTS_Msk                                          (0x60000UL)    /*!< TFCSTS (Bitfield-Mask: 0x03)                          */
34888  #define R_GMAC_Debug_TXPAUSED_Pos                                        (19UL)         /*!< TXPAUSED (Bit 19)                                     */
34889  #define R_GMAC_Debug_TXPAUSED_Msk                                        (0x80000UL)    /*!< TXPAUSED (Bitfield-Mask: 0x01)                        */
34890  #define R_GMAC_Debug_TRCSTS_Pos                                          (20UL)         /*!< TRCSTS (Bit 20)                                       */
34891  #define R_GMAC_Debug_TRCSTS_Msk                                          (0x300000UL)   /*!< TRCSTS (Bitfield-Mask: 0x03)                          */
34892  #define R_GMAC_Debug_TWCSTS_Pos                                          (22UL)         /*!< TWCSTS (Bit 22)                                       */
34893  #define R_GMAC_Debug_TWCSTS_Msk                                          (0x400000UL)   /*!< TWCSTS (Bitfield-Mask: 0x01)                          */
34894  #define R_GMAC_Debug_TXFSTS_Pos                                          (24UL)         /*!< TXFSTS (Bit 24)                                       */
34895  #define R_GMAC_Debug_TXFSTS_Msk                                          (0x1000000UL)  /*!< TXFSTS (Bitfield-Mask: 0x01)                          */
34896  #define R_GMAC_Debug_TXSTSFSTS_Pos                                       (25UL)         /*!< TXSTSFSTS (Bit 25)                                    */
34897  #define R_GMAC_Debug_TXSTSFSTS_Msk                                       (0x2000000UL)  /*!< TXSTSFSTS (Bitfield-Mask: 0x01)                       */
34898 /* ==============================================  Remote_Wake_Up_Frame_Filter  ============================================== */
34899  #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Pos                (0UL)          /*!< WKUPFRMFTR (Bit 0)                                    */
34900  #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Msk                (0xffffffffUL) /*!< WKUPFRMFTR (Bitfield-Mask: 0xffffffff)           */
34901 /* ==================================================  PMT_Control_Status  =================================================== */
34902  #define R_GMAC_PMT_Control_Status_PWRDWN_Pos                             (0UL)          /*!< PWRDWN (Bit 0)                                        */
34903  #define R_GMAC_PMT_Control_Status_PWRDWN_Msk                             (0x1UL)        /*!< PWRDWN (Bitfield-Mask: 0x01)                          */
34904  #define R_GMAC_PMT_Control_Status_MGKPKTEN_Pos                           (1UL)          /*!< MGKPKTEN (Bit 1)                                      */
34905  #define R_GMAC_PMT_Control_Status_MGKPKTEN_Msk                           (0x2UL)        /*!< MGKPKTEN (Bitfield-Mask: 0x01)                        */
34906  #define R_GMAC_PMT_Control_Status_RWKPKTEN_Pos                           (2UL)          /*!< RWKPKTEN (Bit 2)                                      */
34907  #define R_GMAC_PMT_Control_Status_RWKPKTEN_Msk                           (0x4UL)        /*!< RWKPKTEN (Bitfield-Mask: 0x01)                        */
34908  #define R_GMAC_PMT_Control_Status_MGKPRCVD_Pos                           (5UL)          /*!< MGKPRCVD (Bit 5)                                      */
34909  #define R_GMAC_PMT_Control_Status_MGKPRCVD_Msk                           (0x20UL)       /*!< MGKPRCVD (Bitfield-Mask: 0x01)                        */
34910  #define R_GMAC_PMT_Control_Status_RWKPRCVD_Pos                           (6UL)          /*!< RWKPRCVD (Bit 6)                                      */
34911  #define R_GMAC_PMT_Control_Status_RWKPRCVD_Msk                           (0x40UL)       /*!< RWKPRCVD (Bitfield-Mask: 0x01)                        */
34912  #define R_GMAC_PMT_Control_Status_GLBLUCAST_Pos                          (9UL)          /*!< GLBLUCAST (Bit 9)                                     */
34913  #define R_GMAC_PMT_Control_Status_GLBLUCAST_Msk                          (0x200UL)      /*!< GLBLUCAST (Bitfield-Mask: 0x01)                       */
34914  #define R_GMAC_PMT_Control_Status_RWKPTR_Pos                             (24UL)         /*!< RWKPTR (Bit 24)                                       */
34915  #define R_GMAC_PMT_Control_Status_RWKPTR_Msk                             (0x7000000UL)  /*!< RWKPTR (Bitfield-Mask: 0x07)                          */
34916  #define R_GMAC_PMT_Control_Status_RWKFILTRST_Pos                         (31UL)         /*!< RWKFILTRST (Bit 31)                                   */
34917  #define R_GMAC_PMT_Control_Status_RWKFILTRST_Msk                         (0x80000000UL) /*!< RWKFILTRST (Bitfield-Mask: 0x01)                      */
34918 /* ==================================================  LPI_Control_Status  =================================================== */
34919  #define R_GMAC_LPI_Control_Status_TLPIEN_Pos                             (0UL)          /*!< TLPIEN (Bit 0)                                        */
34920  #define R_GMAC_LPI_Control_Status_TLPIEN_Msk                             (0x1UL)        /*!< TLPIEN (Bitfield-Mask: 0x01)                          */
34921  #define R_GMAC_LPI_Control_Status_TLPIEX_Pos                             (1UL)          /*!< TLPIEX (Bit 1)                                        */
34922  #define R_GMAC_LPI_Control_Status_TLPIEX_Msk                             (0x2UL)        /*!< TLPIEX (Bitfield-Mask: 0x01)                          */
34923  #define R_GMAC_LPI_Control_Status_RLPIEN_Pos                             (2UL)          /*!< RLPIEN (Bit 2)                                        */
34924  #define R_GMAC_LPI_Control_Status_RLPIEN_Msk                             (0x4UL)        /*!< RLPIEN (Bitfield-Mask: 0x01)                          */
34925  #define R_GMAC_LPI_Control_Status_RLPIEX_Pos                             (3UL)          /*!< RLPIEX (Bit 3)                                        */
34926  #define R_GMAC_LPI_Control_Status_RLPIEX_Msk                             (0x8UL)        /*!< RLPIEX (Bitfield-Mask: 0x01)                          */
34927  #define R_GMAC_LPI_Control_Status_TLPIST_Pos                             (8UL)          /*!< TLPIST (Bit 8)                                        */
34928  #define R_GMAC_LPI_Control_Status_TLPIST_Msk                             (0x100UL)      /*!< TLPIST (Bitfield-Mask: 0x01)                          */
34929  #define R_GMAC_LPI_Control_Status_RLPIST_Pos                             (9UL)          /*!< RLPIST (Bit 9)                                        */
34930  #define R_GMAC_LPI_Control_Status_RLPIST_Msk                             (0x200UL)      /*!< RLPIST (Bitfield-Mask: 0x01)                          */
34931  #define R_GMAC_LPI_Control_Status_LPIEN_Pos                              (16UL)         /*!< LPIEN (Bit 16)                                        */
34932  #define R_GMAC_LPI_Control_Status_LPIEN_Msk                              (0x10000UL)    /*!< LPIEN (Bitfield-Mask: 0x01)                           */
34933  #define R_GMAC_LPI_Control_Status_PLS_Pos                                (17UL)         /*!< PLS (Bit 17)                                          */
34934  #define R_GMAC_LPI_Control_Status_PLS_Msk                                (0x20000UL)    /*!< PLS (Bitfield-Mask: 0x01)                             */
34935  #define R_GMAC_LPI_Control_Status_LPITXA_Pos                             (19UL)         /*!< LPITXA (Bit 19)                                       */
34936  #define R_GMAC_LPI_Control_Status_LPITXA_Msk                             (0x80000UL)    /*!< LPITXA (Bitfield-Mask: 0x01)                          */
34937 /* ==================================================  LPI_Timers_Control  =================================================== */
34938  #define R_GMAC_LPI_Timers_Control_TWT_Pos                                (0UL)          /*!< TWT (Bit 0)                                           */
34939  #define R_GMAC_LPI_Timers_Control_TWT_Msk                                (0xffffUL)     /*!< TWT (Bitfield-Mask: 0xffff)                           */
34940  #define R_GMAC_LPI_Timers_Control_LST_Pos                                (16UL)         /*!< LST (Bit 16)                                          */
34941  #define R_GMAC_LPI_Timers_Control_LST_Msk                                (0x3ff0000UL)  /*!< LST (Bitfield-Mask: 0x3ff)                            */
34942 /* ===================================================  Interrupt_Status  ==================================================== */
34943  #define R_GMAC_Interrupt_Status_PMTIS_Pos                                (3UL)          /*!< PMTIS (Bit 3)                                         */
34944  #define R_GMAC_Interrupt_Status_PMTIS_Msk                                (0x8UL)        /*!< PMTIS (Bitfield-Mask: 0x01)                           */
34945  #define R_GMAC_Interrupt_Status_MMCIS_Pos                                (4UL)          /*!< MMCIS (Bit 4)                                         */
34946  #define R_GMAC_Interrupt_Status_MMCIS_Msk                                (0x10UL)       /*!< MMCIS (Bitfield-Mask: 0x01)                           */
34947  #define R_GMAC_Interrupt_Status_MMCRXIS_Pos                              (5UL)          /*!< MMCRXIS (Bit 5)                                       */
34948  #define R_GMAC_Interrupt_Status_MMCRXIS_Msk                              (0x20UL)       /*!< MMCRXIS (Bitfield-Mask: 0x01)                         */
34949  #define R_GMAC_Interrupt_Status_MMCTXIS_Pos                              (6UL)          /*!< MMCTXIS (Bit 6)                                       */
34950  #define R_GMAC_Interrupt_Status_MMCTXIS_Msk                              (0x40UL)       /*!< MMCTXIS (Bitfield-Mask: 0x01)                         */
34951  #define R_GMAC_Interrupt_Status_MMCRXIPIS_Pos                            (7UL)          /*!< MMCRXIPIS (Bit 7)                                     */
34952  #define R_GMAC_Interrupt_Status_MMCRXIPIS_Msk                            (0x80UL)       /*!< MMCRXIPIS (Bitfield-Mask: 0x01)                       */
34953  #define R_GMAC_Interrupt_Status_TSIS_Pos                                 (9UL)          /*!< TSIS (Bit 9)                                          */
34954  #define R_GMAC_Interrupt_Status_TSIS_Msk                                 (0x200UL)      /*!< TSIS (Bitfield-Mask: 0x01)                            */
34955  #define R_GMAC_Interrupt_Status_LPIIS_Pos                                (10UL)         /*!< LPIIS (Bit 10)                                        */
34956  #define R_GMAC_Interrupt_Status_LPIIS_Msk                                (0x400UL)      /*!< LPIIS (Bitfield-Mask: 0x01)                           */
34957 /* ====================================================  Interrupt_Mask  ===================================================== */
34958  #define R_GMAC_Interrupt_Mask_PMTIM_Pos                                  (3UL)          /*!< PMTIM (Bit 3)                                         */
34959  #define R_GMAC_Interrupt_Mask_PMTIM_Msk                                  (0x8UL)        /*!< PMTIM (Bitfield-Mask: 0x01)                           */
34960  #define R_GMAC_Interrupt_Mask_TSIM_Pos                                   (9UL)          /*!< TSIM (Bit 9)                                          */
34961  #define R_GMAC_Interrupt_Mask_TSIM_Msk                                   (0x200UL)      /*!< TSIM (Bitfield-Mask: 0x01)                            */
34962  #define R_GMAC_Interrupt_Mask_LPIIM_Pos                                  (10UL)         /*!< LPIIM (Bit 10)                                        */
34963  #define R_GMAC_Interrupt_Mask_LPIIM_Msk                                  (0x400UL)      /*!< LPIIM (Bitfield-Mask: 0x01)                           */
34964 /* ========================================================  MAR0_H  ========================================================= */
34965  #define R_GMAC_MAR0_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
34966  #define R_GMAC_MAR0_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
34967  #define R_GMAC_MAR0_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
34968  #define R_GMAC_MAR0_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
34969 /* ========================================================  MAR0_L  ========================================================= */
34970  #define R_GMAC_MAR0_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
34971  #define R_GMAC_MAR0_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
34972 /* ========================================================  MAR1_H  ========================================================= */
34973  #define R_GMAC_MAR1_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
34974  #define R_GMAC_MAR1_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
34975  #define R_GMAC_MAR1_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
34976  #define R_GMAC_MAR1_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
34977  #define R_GMAC_MAR1_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
34978  #define R_GMAC_MAR1_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
34979  #define R_GMAC_MAR1_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
34980  #define R_GMAC_MAR1_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
34981 /* ========================================================  MAR2_H  ========================================================= */
34982  #define R_GMAC_MAR2_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
34983  #define R_GMAC_MAR2_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
34984  #define R_GMAC_MAR2_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
34985  #define R_GMAC_MAR2_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
34986  #define R_GMAC_MAR2_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
34987  #define R_GMAC_MAR2_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
34988  #define R_GMAC_MAR2_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
34989  #define R_GMAC_MAR2_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
34990 /* ========================================================  MAR3_H  ========================================================= */
34991  #define R_GMAC_MAR3_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
34992  #define R_GMAC_MAR3_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
34993  #define R_GMAC_MAR3_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
34994  #define R_GMAC_MAR3_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
34995  #define R_GMAC_MAR3_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
34996  #define R_GMAC_MAR3_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
34997  #define R_GMAC_MAR3_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
34998  #define R_GMAC_MAR3_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
34999 /* ========================================================  MAR4_H  ========================================================= */
35000  #define R_GMAC_MAR4_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
35001  #define R_GMAC_MAR4_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35002  #define R_GMAC_MAR4_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
35003  #define R_GMAC_MAR4_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35004  #define R_GMAC_MAR4_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
35005  #define R_GMAC_MAR4_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35006  #define R_GMAC_MAR4_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
35007  #define R_GMAC_MAR4_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35008 /* ========================================================  MAR5_H  ========================================================= */
35009  #define R_GMAC_MAR5_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
35010  #define R_GMAC_MAR5_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35011  #define R_GMAC_MAR5_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
35012  #define R_GMAC_MAR5_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35013  #define R_GMAC_MAR5_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
35014  #define R_GMAC_MAR5_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35015  #define R_GMAC_MAR5_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
35016  #define R_GMAC_MAR5_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35017 /* ========================================================  MAR6_H  ========================================================= */
35018  #define R_GMAC_MAR6_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
35019  #define R_GMAC_MAR6_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35020  #define R_GMAC_MAR6_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
35021  #define R_GMAC_MAR6_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35022  #define R_GMAC_MAR6_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
35023  #define R_GMAC_MAR6_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35024  #define R_GMAC_MAR6_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
35025  #define R_GMAC_MAR6_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35026 /* ========================================================  MAR7_H  ========================================================= */
35027  #define R_GMAC_MAR7_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
35028  #define R_GMAC_MAR7_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35029  #define R_GMAC_MAR7_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
35030  #define R_GMAC_MAR7_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35031  #define R_GMAC_MAR7_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
35032  #define R_GMAC_MAR7_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35033  #define R_GMAC_MAR7_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
35034  #define R_GMAC_MAR7_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35035 /* ========================================================  MAR8_H  ========================================================= */
35036  #define R_GMAC_MAR8_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
35037  #define R_GMAC_MAR8_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35038  #define R_GMAC_MAR8_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
35039  #define R_GMAC_MAR8_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35040  #define R_GMAC_MAR8_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
35041  #define R_GMAC_MAR8_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35042  #define R_GMAC_MAR8_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
35043  #define R_GMAC_MAR8_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35044 /* ========================================================  MAR9_H  ========================================================= */
35045  #define R_GMAC_MAR9_H_ADDRHI_Pos                                         (0UL)          /*!< ADDRHI (Bit 0)                                        */
35046  #define R_GMAC_MAR9_H_ADDRHI_Msk                                         (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35047  #define R_GMAC_MAR9_H_MBC_Pos                                            (24UL)         /*!< MBC (Bit 24)                                          */
35048  #define R_GMAC_MAR9_H_MBC_Msk                                            (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35049  #define R_GMAC_MAR9_H_SA_Pos                                             (30UL)         /*!< SA (Bit 30)                                           */
35050  #define R_GMAC_MAR9_H_SA_Msk                                             (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35051  #define R_GMAC_MAR9_H_AE_Pos                                             (31UL)         /*!< AE (Bit 31)                                           */
35052  #define R_GMAC_MAR9_H_AE_Msk                                             (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35053 /* ========================================================  MAR10_H  ======================================================== */
35054  #define R_GMAC_MAR10_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35055  #define R_GMAC_MAR10_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35056  #define R_GMAC_MAR10_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35057  #define R_GMAC_MAR10_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35058  #define R_GMAC_MAR10_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35059  #define R_GMAC_MAR10_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35060  #define R_GMAC_MAR10_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35061  #define R_GMAC_MAR10_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35062 /* ========================================================  MAR11_H  ======================================================== */
35063  #define R_GMAC_MAR11_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35064  #define R_GMAC_MAR11_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35065  #define R_GMAC_MAR11_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35066  #define R_GMAC_MAR11_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35067  #define R_GMAC_MAR11_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35068  #define R_GMAC_MAR11_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35069  #define R_GMAC_MAR11_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35070  #define R_GMAC_MAR11_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35071 /* ========================================================  MAR12_H  ======================================================== */
35072  #define R_GMAC_MAR12_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35073  #define R_GMAC_MAR12_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35074  #define R_GMAC_MAR12_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35075  #define R_GMAC_MAR12_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35076  #define R_GMAC_MAR12_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35077  #define R_GMAC_MAR12_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35078  #define R_GMAC_MAR12_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35079  #define R_GMAC_MAR12_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35080 /* ========================================================  MAR13_H  ======================================================== */
35081  #define R_GMAC_MAR13_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35082  #define R_GMAC_MAR13_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35083  #define R_GMAC_MAR13_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35084  #define R_GMAC_MAR13_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35085  #define R_GMAC_MAR13_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35086  #define R_GMAC_MAR13_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35087  #define R_GMAC_MAR13_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35088  #define R_GMAC_MAR13_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35089 /* ========================================================  MAR14_H  ======================================================== */
35090  #define R_GMAC_MAR14_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35091  #define R_GMAC_MAR14_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35092  #define R_GMAC_MAR14_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35093  #define R_GMAC_MAR14_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35094  #define R_GMAC_MAR14_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35095  #define R_GMAC_MAR14_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35096  #define R_GMAC_MAR14_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35097  #define R_GMAC_MAR14_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35098 /* ========================================================  MAR15_H  ======================================================== */
35099  #define R_GMAC_MAR15_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35100  #define R_GMAC_MAR15_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35101  #define R_GMAC_MAR15_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35102  #define R_GMAC_MAR15_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35103  #define R_GMAC_MAR15_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35104  #define R_GMAC_MAR15_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35105  #define R_GMAC_MAR15_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35106  #define R_GMAC_MAR15_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35107 /* ========================================================  MAR1_L  ========================================================= */
35108  #define R_GMAC_MAR1_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35109  #define R_GMAC_MAR1_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35110 /* ========================================================  MAR2_L  ========================================================= */
35111  #define R_GMAC_MAR2_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35112  #define R_GMAC_MAR2_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35113 /* ========================================================  MAR3_L  ========================================================= */
35114  #define R_GMAC_MAR3_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35115  #define R_GMAC_MAR3_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35116 /* ========================================================  MAR4_L  ========================================================= */
35117  #define R_GMAC_MAR4_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35118  #define R_GMAC_MAR4_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35119 /* ========================================================  MAR5_L  ========================================================= */
35120  #define R_GMAC_MAR5_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35121  #define R_GMAC_MAR5_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35122 /* ========================================================  MAR6_L  ========================================================= */
35123  #define R_GMAC_MAR6_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35124  #define R_GMAC_MAR6_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35125 /* ========================================================  MAR7_L  ========================================================= */
35126  #define R_GMAC_MAR7_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35127  #define R_GMAC_MAR7_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35128 /* ========================================================  MAR8_L  ========================================================= */
35129  #define R_GMAC_MAR8_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35130  #define R_GMAC_MAR8_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35131 /* ========================================================  MAR9_L  ========================================================= */
35132  #define R_GMAC_MAR9_L_ADDRLO_Pos                                         (0UL)          /*!< ADDRLO (Bit 0)                                        */
35133  #define R_GMAC_MAR9_L_ADDRLO_Msk                                         (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35134 /* ========================================================  MAR10_L  ======================================================== */
35135  #define R_GMAC_MAR10_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35136  #define R_GMAC_MAR10_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35137 /* ========================================================  MAR11_L  ======================================================== */
35138  #define R_GMAC_MAR11_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35139  #define R_GMAC_MAR11_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35140 /* ========================================================  MAR12_L  ======================================================== */
35141  #define R_GMAC_MAR12_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35142  #define R_GMAC_MAR12_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35143 /* ========================================================  MAR13_L  ======================================================== */
35144  #define R_GMAC_MAR13_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35145  #define R_GMAC_MAR13_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35146 /* ========================================================  MAR14_L  ======================================================== */
35147  #define R_GMAC_MAR14_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35148  #define R_GMAC_MAR14_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35149 /* ========================================================  MAR15_L  ======================================================== */
35150  #define R_GMAC_MAR15_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35151  #define R_GMAC_MAR15_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35152 /* =====================================================  WDog_Timeout  ====================================================== */
35153  #define R_GMAC_WDog_Timeout_WTO_Pos                                      (0UL)          /*!< WTO (Bit 0)                                           */
35154  #define R_GMAC_WDog_Timeout_WTO_Msk                                      (0x3fffUL)     /*!< WTO (Bitfield-Mask: 0x3fff)                           */
35155  #define R_GMAC_WDog_Timeout_PWE_Pos                                      (16UL)         /*!< PWE (Bit 16)                                          */
35156  #define R_GMAC_WDog_Timeout_PWE_Msk                                      (0x10000UL)    /*!< PWE (Bitfield-Mask: 0x01)                             */
35157 /* ======================================================  MMC_Control  ====================================================== */
35158  #define R_GMAC_MMC_Control_CNTRST_Pos                                    (0UL)          /*!< CNTRST (Bit 0)                                        */
35159  #define R_GMAC_MMC_Control_CNTRST_Msk                                    (0x1UL)        /*!< CNTRST (Bitfield-Mask: 0x01)                          */
35160  #define R_GMAC_MMC_Control_CNTSTOPRO_Pos                                 (1UL)          /*!< CNTSTOPRO (Bit 1)                                     */
35161  #define R_GMAC_MMC_Control_CNTSTOPRO_Msk                                 (0x2UL)        /*!< CNTSTOPRO (Bitfield-Mask: 0x01)                       */
35162  #define R_GMAC_MMC_Control_RSTONRD_Pos                                   (2UL)          /*!< RSTONRD (Bit 2)                                       */
35163  #define R_GMAC_MMC_Control_RSTONRD_Msk                                   (0x4UL)        /*!< RSTONRD (Bitfield-Mask: 0x01)                         */
35164  #define R_GMAC_MMC_Control_CNTFREEZ_Pos                                  (3UL)          /*!< CNTFREEZ (Bit 3)                                      */
35165  #define R_GMAC_MMC_Control_CNTFREEZ_Msk                                  (0x8UL)        /*!< CNTFREEZ (Bitfield-Mask: 0x01)                        */
35166  #define R_GMAC_MMC_Control_CNTPRST_Pos                                   (4UL)          /*!< CNTPRST (Bit 4)                                       */
35167  #define R_GMAC_MMC_Control_CNTPRST_Msk                                   (0x10UL)       /*!< CNTPRST (Bitfield-Mask: 0x01)                         */
35168  #define R_GMAC_MMC_Control_CNTPRSTLVL_Pos                                (5UL)          /*!< CNTPRSTLVL (Bit 5)                                    */
35169  #define R_GMAC_MMC_Control_CNTPRSTLVL_Msk                                (0x20UL)       /*!< CNTPRSTLVL (Bitfield-Mask: 0x01)                      */
35170  #define R_GMAC_MMC_Control_UCDBC_Pos                                     (8UL)          /*!< UCDBC (Bit 8)                                         */
35171  #define R_GMAC_MMC_Control_UCDBC_Msk                                     (0x100UL)      /*!< UCDBC (Bitfield-Mask: 0x01)                           */
35172 /* =================================================  MMC_Receive_Interrupt  ================================================= */
35173  #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Pos                       (0UL)          /*!< RXGBFRMIS (Bit 0)                                     */
35174  #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Msk                       (0x1UL)        /*!< RXGBFRMIS (Bitfield-Mask: 0x01)                       */
35175  #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Pos                       (1UL)          /*!< RXGBOCTIS (Bit 1)                                     */
35176  #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Msk                       (0x2UL)        /*!< RXGBOCTIS (Bitfield-Mask: 0x01)                       */
35177  #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Pos                        (2UL)          /*!< RXGOCTIS (Bit 2)                                      */
35178  #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Msk                        (0x4UL)        /*!< RXGOCTIS (Bitfield-Mask: 0x01)                        */
35179  #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Pos                        (3UL)          /*!< RXBCGFIS (Bit 3)                                      */
35180  #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Msk                        (0x8UL)        /*!< RXBCGFIS (Bitfield-Mask: 0x01)                        */
35181  #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Pos                        (4UL)          /*!< RXMCGFIS (Bit 4)                                      */
35182  #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Msk                        (0x10UL)       /*!< RXMCGFIS (Bitfield-Mask: 0x01)                        */
35183  #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Pos                      (5UL)          /*!< RXCRCERFIS (Bit 5)                                    */
35184  #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Msk                      (0x20UL)       /*!< RXCRCERFIS (Bitfield-Mask: 0x01)                      */
35185  #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Pos                     (6UL)          /*!< RXALGNERFIS (Bit 6)                                   */
35186  #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Msk                     (0x40UL)       /*!< RXALGNERFIS (Bitfield-Mask: 0x01)                     */
35187  #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Pos                       (7UL)          /*!< RXRUNTFIS (Bit 7)                                     */
35188  #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Msk                       (0x80UL)       /*!< RXRUNTFIS (Bitfield-Mask: 0x01)                       */
35189  #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Pos                      (8UL)          /*!< RXJABERFIS (Bit 8)                                    */
35190  #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Msk                      (0x100UL)      /*!< RXJABERFIS (Bitfield-Mask: 0x01)                      */
35191  #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Pos                     (9UL)          /*!< RXUSIZEGFIS (Bit 9)                                   */
35192  #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Msk                     (0x200UL)      /*!< RXUSIZEGFIS (Bitfield-Mask: 0x01)                     */
35193  #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Pos                     (10UL)         /*!< RXOSIZEGFIS (Bit 10)                                  */
35194  #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Msk                     (0x400UL)      /*!< RXOSIZEGFIS (Bitfield-Mask: 0x01)                     */
35195  #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Pos                    (11UL)         /*!< RX64OCTGBFIS (Bit 11)                                 */
35196  #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Msk                    (0x800UL)      /*!< RX64OCTGBFIS (Bitfield-Mask: 0x01)                    */
35197  #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Pos                (12UL)         /*!< RX65T127OCTGBFIS (Bit 12)                             */
35198  #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Msk                (0x1000UL)     /*!< RX65T127OCTGBFIS (Bitfield-Mask: 0x01)               */
35199  #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Pos               (13UL)         /*!< RX128T255OCTGBFIS (Bit 13)                            */
35200  #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Msk               (0x2000UL)     /*!< RX128T255OCTGBFIS (Bitfield-Mask: 0x01)             */
35201  #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Pos               (14UL)         /*!< RX256T511OCTGBFIS (Bit 14)                            */
35202  #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Msk               (0x4000UL)     /*!< RX256T511OCTGBFIS (Bitfield-Mask: 0x01)             */
35203  #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Pos              (15UL)         /*!< RX512T1023OCTGBFIS (Bit 15)                           */
35204  #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Msk              (0x8000UL)     /*!< RX512T1023OCTGBFIS (Bitfield-Mask: 0x01)           */
35205  #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Pos              (16UL)         /*!< RX1024TMAXOCTGBFIS (Bit 16)                           */
35206  #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Msk              (0x10000UL)    /*!< RX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01)          */
35207  #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Pos                        (17UL)         /*!< RXUCGFIS (Bit 17)                                     */
35208  #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Msk                        (0x20000UL)    /*!< RXUCGFIS (Bitfield-Mask: 0x01)                        */
35209  #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Pos                      (18UL)         /*!< RXLENERFIS (Bit 18)                                   */
35210  #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Msk                      (0x40000UL)    /*!< RXLENERFIS (Bitfield-Mask: 0x01)                      */
35211  #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Pos                     (19UL)         /*!< RXORANGEFIS (Bit 19)                                  */
35212  #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Msk                     (0x80000UL)    /*!< RXORANGEFIS (Bitfield-Mask: 0x01)                     */
35213  #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Pos                       (20UL)         /*!< RXPAUSFIS (Bit 20)                                    */
35214  #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Msk                       (0x100000UL)   /*!< RXPAUSFIS (Bitfield-Mask: 0x01)                       */
35215  #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Pos                        (21UL)         /*!< RXFOVFIS (Bit 21)                                     */
35216  #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Msk                        (0x200000UL)   /*!< RXFOVFIS (Bitfield-Mask: 0x01)                        */
35217  #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Pos                     (22UL)         /*!< RXVLANGBFIS (Bit 22)                                  */
35218  #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Msk                     (0x400000UL)   /*!< RXVLANGBFIS (Bitfield-Mask: 0x01)                     */
35219  #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Pos                       (23UL)         /*!< RXWDOGFIS (Bit 23)                                    */
35220  #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Msk                       (0x800000UL)   /*!< RXWDOGFIS (Bitfield-Mask: 0x01)                       */
35221  #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Pos                     (24UL)         /*!< RXRCVERRFIS (Bit 24)                                  */
35222  #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Msk                     (0x1000000UL)  /*!< RXRCVERRFIS (Bitfield-Mask: 0x01)                     */
35223  #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Pos                       (25UL)         /*!< RXCTRLFIS (Bit 25)                                    */
35224  #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Msk                       (0x2000000UL)  /*!< RXCTRLFIS (Bitfield-Mask: 0x01)                       */
35225 /* ================================================  MMC_Transmit_Interrupt  ================================================= */
35226  #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Pos                      (0UL)          /*!< TXGBOCTIS (Bit 0)                                     */
35227  #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Msk                      (0x1UL)        /*!< TXGBOCTIS (Bitfield-Mask: 0x01)                       */
35228  #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Pos                      (1UL)          /*!< TXGBFRMIS (Bit 1)                                     */
35229  #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Msk                      (0x2UL)        /*!< TXGBFRMIS (Bitfield-Mask: 0x01)                       */
35230  #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Pos                       (2UL)          /*!< TXBCGFIS (Bit 2)                                      */
35231  #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Msk                       (0x4UL)        /*!< TXBCGFIS (Bitfield-Mask: 0x01)                        */
35232  #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Pos                       (3UL)          /*!< TXMCGFIS (Bit 3)                                      */
35233  #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Msk                       (0x8UL)        /*!< TXMCGFIS (Bitfield-Mask: 0x01)                        */
35234  #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Pos                   (4UL)          /*!< TX64OCTGBFIS (Bit 4)                                  */
35235  #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Msk                   (0x10UL)       /*!< TX64OCTGBFIS (Bitfield-Mask: 0x01)                    */
35236  #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Pos               (5UL)          /*!< TX65T127OCTGBFIS (Bit 5)                              */
35237  #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Msk               (0x20UL)       /*!< TX65T127OCTGBFIS (Bitfield-Mask: 0x01)                */
35238  #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Pos              (6UL)          /*!< TX128T255OCTGBFIS (Bit 6)                             */
35239  #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Msk              (0x40UL)       /*!< TX128T255OCTGBFIS (Bitfield-Mask: 0x01)              */
35240  #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Pos              (7UL)          /*!< TX256T511OCTGBFIS (Bit 7)                             */
35241  #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Msk              (0x80UL)       /*!< TX256T511OCTGBFIS (Bitfield-Mask: 0x01)              */
35242  #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Pos             (8UL)          /*!< TX512T1023OCTGBFIS (Bit 8)                            */
35243  #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Msk             (0x100UL)      /*!< TX512T1023OCTGBFIS (Bitfield-Mask: 0x01)           */
35244  #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Pos             (9UL)          /*!< TX1024TMAXOCTGBFIS (Bit 9)                            */
35245  #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Msk             (0x200UL)      /*!< TX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01)           */
35246  #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Pos                      (10UL)         /*!< TXUCGBFIS (Bit 10)                                    */
35247  #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Msk                      (0x400UL)      /*!< TXUCGBFIS (Bitfield-Mask: 0x01)                       */
35248  #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Pos                      (11UL)         /*!< TXMCGBFIS (Bit 11)                                    */
35249  #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Msk                      (0x800UL)      /*!< TXMCGBFIS (Bitfield-Mask: 0x01)                       */
35250  #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Pos                      (12UL)         /*!< TXBCGBFIS (Bit 12)                                    */
35251  #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Msk                      (0x1000UL)     /*!< TXBCGBFIS (Bitfield-Mask: 0x01)                       */
35252  #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Pos                   (13UL)         /*!< TXUFLOWERFIS (Bit 13)                                 */
35253  #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Msk                   (0x2000UL)     /*!< TXUFLOWERFIS (Bitfield-Mask: 0x01)                    */
35254  #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Pos                     (14UL)         /*!< TXSCOLGFIS (Bit 14)                                   */
35255  #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Msk                     (0x4000UL)     /*!< TXSCOLGFIS (Bitfield-Mask: 0x01)                      */
35256  #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Pos                     (15UL)         /*!< TXMCOLGFIS (Bit 15)                                   */
35257  #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Msk                     (0x8000UL)     /*!< TXMCOLGFIS (Bitfield-Mask: 0x01)                      */
35258  #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Pos                       (16UL)         /*!< TXDEFFIS (Bit 16)                                     */
35259  #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Msk                       (0x10000UL)    /*!< TXDEFFIS (Bitfield-Mask: 0x01)                        */
35260  #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Pos                    (17UL)         /*!< TXLATCOLFIS (Bit 17)                                  */
35261  #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Msk                    (0x20000UL)    /*!< TXLATCOLFIS (Bitfield-Mask: 0x01)                     */
35262  #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Pos                     (18UL)         /*!< TXEXCOLFIS (Bit 18)                                   */
35263  #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Msk                     (0x40000UL)    /*!< TXEXCOLFIS (Bitfield-Mask: 0x01)                      */
35264  #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Pos                     (19UL)         /*!< TXCARERFIS (Bit 19)                                   */
35265  #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Msk                     (0x80000UL)    /*!< TXCARERFIS (Bitfield-Mask: 0x01)                      */
35266  #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Pos                       (20UL)         /*!< TXGOCTIS (Bit 20)                                     */
35267  #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Msk                       (0x100000UL)   /*!< TXGOCTIS (Bitfield-Mask: 0x01)                        */
35268  #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Pos                       (21UL)         /*!< TXGFRMIS (Bit 21)                                     */
35269  #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Msk                       (0x200000UL)   /*!< TXGFRMIS (Bitfield-Mask: 0x01)                        */
35270  #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Pos                     (22UL)         /*!< TXEXDEFFIS (Bit 22)                                   */
35271  #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Msk                     (0x400000UL)   /*!< TXEXDEFFIS (Bitfield-Mask: 0x01)                      */
35272  #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Pos                      (23UL)         /*!< TXPAUSFIS (Bit 23)                                    */
35273  #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Msk                      (0x800000UL)   /*!< TXPAUSFIS (Bitfield-Mask: 0x01)                       */
35274  #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Pos                     (24UL)         /*!< TXVLANGFIS (Bit 24)                                   */
35275  #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Msk                     (0x1000000UL)  /*!< TXVLANGFIS (Bitfield-Mask: 0x01)                      */
35276  #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Pos                    (25UL)         /*!< TXOSIZEGFIS (Bit 25)                                  */
35277  #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Msk                    (0x2000000UL)  /*!< TXOSIZEGFIS (Bitfield-Mask: 0x01)                     */
35278 /* ==============================================  MMC_Receive_Interrupt_Mask  =============================================== */
35279  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Pos                  (0UL)          /*!< RXGBFRMIM (Bit 0)                                     */
35280  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Msk                  (0x1UL)        /*!< RXGBFRMIM (Bitfield-Mask: 0x01)                       */
35281  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Pos                  (1UL)          /*!< RXGBOCTIM (Bit 1)                                     */
35282  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Msk                  (0x2UL)        /*!< RXGBOCTIM (Bitfield-Mask: 0x01)                       */
35283  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Pos                   (2UL)          /*!< RXGOCTIM (Bit 2)                                      */
35284  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Msk                   (0x4UL)        /*!< RXGOCTIM (Bitfield-Mask: 0x01)                        */
35285  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Pos                   (3UL)          /*!< RXBCGFIM (Bit 3)                                      */
35286  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Msk                   (0x8UL)        /*!< RXBCGFIM (Bitfield-Mask: 0x01)                        */
35287  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Pos                   (4UL)          /*!< RXMCGFIM (Bit 4)                                      */
35288  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Msk                   (0x10UL)       /*!< RXMCGFIM (Bitfield-Mask: 0x01)                        */
35289  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Pos                 (5UL)          /*!< RXCRCERFIM (Bit 5)                                    */
35290  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Msk                 (0x20UL)       /*!< RXCRCERFIM (Bitfield-Mask: 0x01)                      */
35291  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Pos                (6UL)          /*!< RXALGNERFIM (Bit 6)                                   */
35292  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Msk                (0x40UL)       /*!< RXALGNERFIM (Bitfield-Mask: 0x01)                     */
35293  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Pos                  (7UL)          /*!< RXRUNTFIM (Bit 7)                                     */
35294  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Msk                  (0x80UL)       /*!< RXRUNTFIM (Bitfield-Mask: 0x01)                       */
35295  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Pos                 (8UL)          /*!< RXJABERFIM (Bit 8)                                    */
35296  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Msk                 (0x100UL)      /*!< RXJABERFIM (Bitfield-Mask: 0x01)                      */
35297  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Pos                (9UL)          /*!< RXUSIZEGFIM (Bit 9)                                   */
35298  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Msk                (0x200UL)      /*!< RXUSIZEGFIM (Bitfield-Mask: 0x01)                     */
35299  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Pos                (10UL)         /*!< RXOSIZEGFIM (Bit 10)                                  */
35300  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Msk                (0x400UL)      /*!< RXOSIZEGFIM (Bitfield-Mask: 0x01)                     */
35301  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Pos               (11UL)         /*!< RX64OCTGBFIM (Bit 11)                                 */
35302  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Msk               (0x800UL)      /*!< RX64OCTGBFIM (Bitfield-Mask: 0x01)                   */
35303  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Pos           (12UL)         /*!< RX65T127OCTGBFIM (Bit 12)                           */
35304  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Msk           (0x1000UL)     /*!< RX65T127OCTGBFIM (Bitfield-Mask: 0x01)          */
35305  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Pos          (13UL)         /*!< RX128T255OCTGBFIM (Bit 13)                         */
35306  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Msk          (0x2000UL)     /*!< RX128T255OCTGBFIM (Bitfield-Mask: 0x01)        */
35307  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Pos          (14UL)         /*!< RX256T511OCTGBFIM (Bit 14)                         */
35308  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Msk          (0x4000UL)     /*!< RX256T511OCTGBFIM (Bitfield-Mask: 0x01)        */
35309  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Pos         (15UL)         /*!< RX512T1023OCTGBFIM (Bit 15)                       */
35310  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Msk         (0x8000UL)     /*!< RX512T1023OCTGBFIM (Bitfield-Mask: 0x01)      */
35311  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Pos         (16UL)         /*!< RX1024TMAXOCTGBFIM (Bit 16)                       */
35312  #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Msk         (0x10000UL)    /*!< RX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01)     */
35313  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Pos                   (17UL)         /*!< RXUCGFIM (Bit 17)                                     */
35314  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Msk                   (0x20000UL)    /*!< RXUCGFIM (Bitfield-Mask: 0x01)                        */
35315  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Pos                 (18UL)         /*!< RXLENERFIM (Bit 18)                                   */
35316  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Msk                 (0x40000UL)    /*!< RXLENERFIM (Bitfield-Mask: 0x01)                     */
35317  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Pos                (19UL)         /*!< RXORANGEFIM (Bit 19)                                  */
35318  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Msk                (0x80000UL)    /*!< RXORANGEFIM (Bitfield-Mask: 0x01)                   */
35319  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Pos                  (20UL)         /*!< RXPAUSFIM (Bit 20)                                    */
35320  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Msk                  (0x100000UL)   /*!< RXPAUSFIM (Bitfield-Mask: 0x01)                      */
35321  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Pos                   (21UL)         /*!< RXFOVFIM (Bit 21)                                     */
35322  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Msk                   (0x200000UL)   /*!< RXFOVFIM (Bitfield-Mask: 0x01)                        */
35323  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Pos                (22UL)         /*!< RXVLANGBFIM (Bit 22)                                  */
35324  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Msk                (0x400000UL)   /*!< RXVLANGBFIM (Bitfield-Mask: 0x01)                  */
35325  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Pos                  (23UL)         /*!< RXWDOGFIM (Bit 23)                                    */
35326  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Msk                  (0x800000UL)   /*!< RXWDOGFIM (Bitfield-Mask: 0x01)                      */
35327  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Pos                (24UL)         /*!< RXRCVERRFIM (Bit 24)                                  */
35328  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Msk                (0x1000000UL)  /*!< RXRCVERRFIM (Bitfield-Mask: 0x01)                 */
35329  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Pos                  (25UL)         /*!< RXCTRLFIM (Bit 25)                                    */
35330  #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Msk                  (0x2000000UL)  /*!< RXCTRLFIM (Bitfield-Mask: 0x01)                     */
35331 /* ==============================================  MMC_Transmit_Interrupt_Mask  ============================================== */
35332  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Pos                 (0UL)          /*!< TXGBOCTIM (Bit 0)                                     */
35333  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Msk                 (0x1UL)        /*!< TXGBOCTIM (Bitfield-Mask: 0x01)                       */
35334  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Pos                 (1UL)          /*!< TXGBFRMIM (Bit 1)                                     */
35335  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Msk                 (0x2UL)        /*!< TXGBFRMIM (Bitfield-Mask: 0x01)                       */
35336  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Pos                  (2UL)          /*!< TXBCGFIM (Bit 2)                                      */
35337  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Msk                  (0x4UL)        /*!< TXBCGFIM (Bitfield-Mask: 0x01)                        */
35338  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Pos                  (3UL)          /*!< TXMCGFIM (Bit 3)                                      */
35339  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Msk                  (0x8UL)        /*!< TXMCGFIM (Bitfield-Mask: 0x01)                        */
35340  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Pos              (4UL)          /*!< TX64OCTGBFIM (Bit 4)                                  */
35341  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Msk              (0x10UL)       /*!< TX64OCTGBFIM (Bitfield-Mask: 0x01)                   */
35342  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Pos          (5UL)          /*!< TX65T127OCTGBFIM (Bit 5)                            */
35343  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Msk          (0x20UL)       /*!< TX65T127OCTGBFIM (Bitfield-Mask: 0x01)           */
35344  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Pos         (6UL)          /*!< TX128T255OCTGBFIM (Bit 6)                          */
35345  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Msk         (0x40UL)       /*!< TX128T255OCTGBFIM (Bitfield-Mask: 0x01)         */
35346  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Pos         (7UL)          /*!< TX256T511OCTGBFIM (Bit 7)                          */
35347  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Msk         (0x80UL)       /*!< TX256T511OCTGBFIM (Bitfield-Mask: 0x01)         */
35348  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Pos        (8UL)          /*!< TX512T1023OCTGBFIM (Bit 8)                        */
35349  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Msk        (0x100UL)      /*!< TX512T1023OCTGBFIM (Bitfield-Mask: 0x01)      */
35350  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Pos        (9UL)          /*!< TX1024TMAXOCTGBFIM (Bit 9)                        */
35351  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Msk        (0x200UL)      /*!< TX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01)      */
35352  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Pos                 (10UL)         /*!< TXUCGBFIM (Bit 10)                                    */
35353  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Msk                 (0x400UL)      /*!< TXUCGBFIM (Bitfield-Mask: 0x01)                       */
35354  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Pos                 (11UL)         /*!< TXMCGBFIM (Bit 11)                                    */
35355  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Msk                 (0x800UL)      /*!< TXMCGBFIM (Bitfield-Mask: 0x01)                       */
35356  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Pos                 (12UL)         /*!< TXBCGBFIM (Bit 12)                                    */
35357  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Msk                 (0x1000UL)     /*!< TXBCGBFIM (Bitfield-Mask: 0x01)                       */
35358  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Pos              (13UL)         /*!< TXUFLOWERFIM (Bit 13)                                 */
35359  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Msk              (0x2000UL)     /*!< TXUFLOWERFIM (Bitfield-Mask: 0x01)                 */
35360  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Pos                (14UL)         /*!< TXSCOLGFIM (Bit 14)                                   */
35361  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Msk                (0x4000UL)     /*!< TXSCOLGFIM (Bitfield-Mask: 0x01)                     */
35362  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Pos                (15UL)         /*!< TXMCOLGFIM (Bit 15)                                   */
35363  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Msk                (0x8000UL)     /*!< TXMCOLGFIM (Bitfield-Mask: 0x01)                     */
35364  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Pos                  (16UL)         /*!< TXDEFFIM (Bit 16)                                     */
35365  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Msk                  (0x10000UL)    /*!< TXDEFFIM (Bitfield-Mask: 0x01)                        */
35366  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Pos               (17UL)         /*!< TXLATCOLFIM (Bit 17)                                  */
35367  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Msk               (0x20000UL)    /*!< TXLATCOLFIM (Bitfield-Mask: 0x01)                  */
35368  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Pos                (18UL)         /*!< TXEXCOLFIM (Bit 18)                                   */
35369  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Msk                (0x40000UL)    /*!< TXEXCOLFIM (Bitfield-Mask: 0x01)                    */
35370  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Pos                (19UL)         /*!< TXCARERFIM (Bit 19)                                   */
35371  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Msk                (0x80000UL)    /*!< TXCARERFIM (Bitfield-Mask: 0x01)                    */
35372  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Pos                  (20UL)         /*!< TXGOCTIM (Bit 20)                                     */
35373  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Msk                  (0x100000UL)   /*!< TXGOCTIM (Bitfield-Mask: 0x01)                       */
35374  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Pos                  (21UL)         /*!< TXGFRMIM (Bit 21)                                     */
35375  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Msk                  (0x200000UL)   /*!< TXGFRMIM (Bitfield-Mask: 0x01)                       */
35376  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Pos                (22UL)         /*!< TXEXDEFFIM (Bit 22)                                   */
35377  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Msk                (0x400000UL)   /*!< TXEXDEFFIM (Bitfield-Mask: 0x01)                   */
35378  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Pos                 (23UL)         /*!< TXPAUSFIM (Bit 23)                                    */
35379  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Msk                 (0x800000UL)   /*!< TXPAUSFIM (Bitfield-Mask: 0x01)                     */
35380  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Pos                (24UL)         /*!< TXVLANGFIM (Bit 24)                                   */
35381  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Msk                (0x1000000UL)  /*!< TXVLANGFIM (Bitfield-Mask: 0x01)                  */
35382  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Pos               (25UL)         /*!< TXOSIZEGFIM (Bit 25)                                  */
35383  #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Msk               (0x2000000UL)  /*!< TXOSIZEGFIM (Bitfield-Mask: 0x01)                */
35384 /* ================================================  Tx_Octet_Count_Good_Bad  ================================================ */
35385  #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Pos                       (0UL)          /*!< TXOCTGB (Bit 0)                                       */
35386  #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Msk                       (0xffffffffUL) /*!< TXOCTGB (Bitfield-Mask: 0xffffffff)                   */
35387 /* ================================================  Tx_Frame_Count_Good_Bad  ================================================ */
35388  #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Pos                       (0UL)          /*!< TXFRMGB (Bit 0)                                       */
35389  #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Msk                       (0xffffffffUL) /*!< TXFRMGB (Bitfield-Mask: 0xffffffff)                   */
35390 /* ===============================================  Tx_Broadcast_Frames_Good  ================================================ */
35391  #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Pos                     (0UL)          /*!< TXBCASTG (Bit 0)                                      */
35392  #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Msk                     (0xffffffffUL) /*!< TXBCASTG (Bitfield-Mask: 0xffffffff)                  */
35393 /* ===============================================  Tx_Multicast_Frames_Good  ================================================ */
35394  #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Pos                     (0UL)          /*!< TXMCASTG (Bit 0)                                      */
35395  #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Msk                     (0xffffffffUL) /*!< TXMCASTG (Bitfield-Mask: 0xffffffff)                  */
35396 /* ==============================================  Tx_64Octets_Frames_Good_Bad  ============================================== */
35397  #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Pos                 (0UL)          /*!< TX64OCTGB (Bit 0)                                     */
35398  #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Msk                 (0xffffffffUL) /*!< TX64OCTGB (Bitfield-Mask: 0xffffffff)             */
35399 /* ===========================================  Tx_65To127Octets_Frames_Good_Bad  ============================================ */
35400  #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Pos        (0UL)          /*!< TX65_127OCTGB (Bit 0)                             */
35401  #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Msk        (0xffffffffUL) /*!< TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
35402 /* ===========================================  Tx_128To255Octets_Frames_Good_Bad  =========================================== */
35403  #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Pos      (0UL)          /*!< TX128_255OCTGB (Bit 0)                          */
35404  #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Msk      (0xffffffffUL) /*!< TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
35405 /* ===========================================  Tx_256To511Octets_Frames_Good_Bad  =========================================== */
35406  #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Pos      (0UL)          /*!< TX256_511OCTGB (Bit 0)                          */
35407  #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Msk      (0xffffffffUL) /*!< TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
35408 /* ==========================================  Tx_512To1023Octets_Frames_Good_Bad  =========================================== */
35409  #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Pos    (0UL)          /*!< TX512_1023OCTGB (Bit 0)                       */
35410  #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Msk    (0xffffffffUL) /*!< TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
35411 /* ==========================================  Tx_1024ToMaxOctets_Frames_Good_Bad  =========================================== */
35412  #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Pos    (0UL)          /*!< TX1024_MAXOCTGB (Bit 0)                       */
35413  #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
35414 /* ==============================================  Tx_Unicast_Frames_Good_Bad  =============================================== */
35415  #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Pos                  (0UL)          /*!< TXUCASTGB (Bit 0)                                     */
35416  #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Msk                  (0xffffffffUL) /*!< TXUCASTGB (Bitfield-Mask: 0xffffffff)              */
35417 /* =============================================  Tx_Multicast_Frames_Good_Bad  ============================================== */
35418  #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Pos                (0UL)          /*!< TXMCASTGB (Bit 0)                                     */
35419  #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Msk                (0xffffffffUL) /*!< TXMCASTGB (Bitfield-Mask: 0xffffffff)            */
35420 /* =============================================  Tx_Broadcast_Frames_Good_Bad  ============================================== */
35421  #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Pos                (0UL)          /*!< TXBCASTGB (Bit 0)                                     */
35422  #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Msk                (0xffffffffUL) /*!< TXBCASTGB (Bitfield-Mask: 0xffffffff)            */
35423 /* ===============================================  Tx_Underflow_Error_Frames  =============================================== */
35424  #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Pos                   (0UL)          /*!< TXUNDRFLW (Bit 0)                                     */
35425  #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Msk                   (0xffffUL)     /*!< TXUNDRFLW (Bitfield-Mask: 0xffff)                     */
35426 /* ============================================  Tx_Single_Collision_Good_Frames  ============================================ */
35427  #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Pos            (0UL)          /*!< TXSNGLCOLG (Bit 0)                                    */
35428  #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Msk            (0xffffUL)     /*!< TXSNGLCOLG (Bitfield-Mask: 0xffff)               */
35429 /* ===========================================  Tx_Multiple_Collision_Good_Frames  =========================================== */
35430  #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Pos          (0UL)          /*!< TXMULTCOLG (Bit 0)                                  */
35431  #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Msk          (0xffffUL)     /*!< TXMULTCOLG (Bitfield-Mask: 0xffff)             */
35432 /* ==================================================  Tx_Deferred_Frames  =================================================== */
35433  #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Pos                            (0UL)          /*!< TXDEFRD (Bit 0)                                       */
35434  #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Msk                            (0xffffUL)     /*!< TXDEFRD (Bitfield-Mask: 0xffff)                       */
35435 /* ===============================================  Tx_Late_Collision_Frames  ================================================ */
35436  #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Pos                    (0UL)          /*!< TXLATECOL (Bit 0)                                     */
35437  #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Msk                    (0xffffUL)     /*!< TXLATECOL (Bitfield-Mask: 0xffff)                     */
35438 /* =============================================  Tx_Excessive_Collision_Frames  ============================================= */
35439  #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Pos                (0UL)          /*!< TXEXSCOL (Bit 0)                                      */
35440  #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Msk                (0xffffUL)     /*!< TXEXSCOL (Bitfield-Mask: 0xffff)                     */
35441 /* ================================================  Tx_Carrier_Error_Frames  ================================================ */
35442  #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Pos                        (0UL)          /*!< TXCARR (Bit 0)                                        */
35443  #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Msk                        (0xffffUL)     /*!< TXCARR (Bitfield-Mask: 0xffff)                        */
35444 /* ==================================================  Tx_Octet_Count_Good  ================================================== */
35445  #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Pos                            (0UL)          /*!< TXOCTG (Bit 0)                                        */
35446  #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Msk                            (0xffffffffUL) /*!< TXOCTG (Bitfield-Mask: 0xffffffff)                    */
35447 /* ==================================================  Tx_Frame_Count_Good  ================================================== */
35448  #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Pos                            (0UL)          /*!< TXFRMG (Bit 0)                                        */
35449  #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Msk                            (0xffffffffUL) /*!< TXFRMG (Bitfield-Mask: 0xffffffff)                    */
35450 /* ==============================================  Tx_Excessive_Deferral_Error  ============================================== */
35451  #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Pos                  (0UL)          /*!< TXEXSDEF (Bit 0)                                      */
35452  #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Msk                  (0xffffUL)     /*!< TXEXSDEF (Bitfield-Mask: 0xffff)                      */
35453 /* ====================================================  Tx_Pause_Frames  ==================================================== */
35454  #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Pos                               (0UL)          /*!< TXPAUSE (Bit 0)                                       */
35455  #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Msk                               (0xffffUL)     /*!< TXPAUSE (Bitfield-Mask: 0xffff)                       */
35456 /* ==================================================  Tx_VLAN_Frames_Good  ================================================== */
35457  #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Pos                           (0UL)          /*!< TXVLANG (Bit 0)                                       */
35458  #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Msk                           (0xffffffffUL) /*!< TXVLANG (Bitfield-Mask: 0xffffffff)                   */
35459 /* =================================================  Tx_OSize_Frames_Good  ================================================== */
35460  #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Pos                          (0UL)          /*!< TXOSIZG (Bit 0)                                       */
35461  #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Msk                          (0xffffUL)     /*!< TXOSIZG (Bitfield-Mask: 0xffff)                       */
35462 /* ===============================================  Rx_Frames_Count_Good_Bad  ================================================ */
35463  #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Pos                      (0UL)          /*!< RXFRMGB (Bit 0)                                       */
35464  #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Msk                      (0xffffffffUL) /*!< RXFRMGB (Bitfield-Mask: 0xffffffff)                   */
35465 /* ================================================  Rx_Octet_Count_Good_Bad  ================================================ */
35466  #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Pos                       (0UL)          /*!< RXOCTGB (Bit 0)                                       */
35467  #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Msk                       (0xffffffffUL) /*!< RXOCTGB (Bitfield-Mask: 0xffffffff)                   */
35468 /* ==================================================  Rx_Octet_Count_Good  ================================================== */
35469  #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Pos                            (0UL)          /*!< RXOCTG (Bit 0)                                        */
35470  #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Msk                            (0xffffffffUL) /*!< RXOCTG (Bitfield-Mask: 0xffffffff)                    */
35471 /* ===============================================  Rx_Broadcast_Frames_Good  ================================================ */
35472  #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Pos                     (0UL)          /*!< RXBCASTG (Bit 0)                                      */
35473  #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Msk                     (0xffffffffUL) /*!< RXBCASTG (Bitfield-Mask: 0xffffffff)                  */
35474 /* ===============================================  Rx_Multicast_Frames_Good  ================================================ */
35475  #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Pos                     (0UL)          /*!< RXMCASTG (Bit 0)                                      */
35476  #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Msk                     (0xffffffffUL) /*!< RXMCASTG (Bitfield-Mask: 0xffffffff)                  */
35477 /* ==================================================  Rx_CRC_Error_Frames  ================================================== */
35478  #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Pos                          (0UL)          /*!< RXCRCERR (Bit 0)                                      */
35479  #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Msk                          (0xffffUL)     /*!< RXCRCERR (Bitfield-Mask: 0xffff)                      */
35480 /* ===============================================  Rx_Alignment_Error_Frames  =============================================== */
35481  #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Pos                   (0UL)          /*!< RXALGNERR (Bit 0)                                     */
35482  #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Msk                   (0xffffUL)     /*!< RXALGNERR (Bitfield-Mask: 0xffff)                     */
35483 /* =================================================  Rx_Runt_Error_Frames  ================================================== */
35484  #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Pos                        (0UL)          /*!< RXRUNTERR (Bit 0)                                     */
35485  #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Msk                        (0xffffUL)     /*!< RXRUNTERR (Bitfield-Mask: 0xffff)                     */
35486 /* ================================================  Rx_Jabber_Error_Frames  ================================================= */
35487  #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Pos                       (0UL)          /*!< RXJABERR (Bit 0)                                      */
35488  #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Msk                       (0xffffUL)     /*!< RXJABERR (Bitfield-Mask: 0xffff)                      */
35489 /* ===============================================  Rx_Undersize_Frames_Good  ================================================ */
35490  #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Pos                   (0UL)          /*!< RXUNDERSZG (Bit 0)                                    */
35491  #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Msk                   (0xffffUL)     /*!< RXUNDERSZG (Bitfield-Mask: 0xffff)                    */
35492 /* ================================================  Rx_Oversize_Frames_Good  ================================================ */
35493  #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Pos                     (0UL)          /*!< RXOVERSZG (Bit 0)                                     */
35494  #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Msk                     (0xffffUL)     /*!< RXOVERSZG (Bitfield-Mask: 0xffff)                     */
35495 /* ==============================================  Rx_64Octets_Frames_Good_Bad  ============================================== */
35496  #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Pos                 (0UL)          /*!< RX64OCTGB (Bit 0)                                     */
35497  #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Msk                 (0xffffffffUL) /*!< RX64OCTGB (Bitfield-Mask: 0xffffffff)             */
35498 /* ===========================================  Rx_65To127Octets_Frames_Good_Bad  ============================================ */
35499  #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Pos        (0UL)          /*!< RX65_127OCTGB (Bit 0)                             */
35500  #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Msk        (0xffffffffUL) /*!< RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */
35501 /* ===========================================  Rx_128To255Octets_Frames_Good_Bad  =========================================== */
35502  #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Pos      (0UL)          /*!< RX128_255OCTGB (Bit 0)                          */
35503  #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Msk      (0xffffffffUL) /*!< RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */
35504 /* ===========================================  Rx_256To511Octets_Frames_Good_Bad  =========================================== */
35505  #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Pos      (0UL)          /*!< RX256_511OCTGB (Bit 0)                          */
35506  #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Msk      (0xffffffffUL) /*!< RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */
35507 /* ==========================================  Rx_512To1023Octets_Frames_Good_Bad  =========================================== */
35508  #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Pos    (0UL)          /*!< RX512_1023OCTGB (Bit 0)                       */
35509  #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Msk    (0xffffffffUL) /*!< RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */
35510 /* ==========================================  Rx_1024ToMaxOctets_Frames_Good_Bad  =========================================== */
35511  #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Pos    (0UL)          /*!< RX1024_MAXOCTGB (Bit 0)                       */
35512  #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Msk    (0xffffffffUL) /*!< RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */
35513 /* ================================================  Rx_Unicast_Frames_Good  ================================================= */
35514  #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Pos                       (0UL)          /*!< RXUCASTG (Bit 0)                                      */
35515  #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Msk                       (0xffffffffUL) /*!< RXUCASTG (Bitfield-Mask: 0xffffffff)                  */
35516 /* ================================================  Rx_Length_Error_Frames  ================================================= */
35517  #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Pos                       (0UL)          /*!< RXLENERR (Bit 0)                                      */
35518  #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Msk                       (0xffffUL)     /*!< RXLENERR (Bitfield-Mask: 0xffff)                      */
35519 /* ==============================================  Rx_Out_Of_Range_Type_Frames  ============================================== */
35520  #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Pos                (0UL)          /*!< RXOUTOFRNG (Bit 0)                                    */
35521  #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Msk                (0xffffUL)     /*!< RXOUTOFRNG (Bitfield-Mask: 0xffff)                   */
35522 /* ====================================================  Rx_Pause_Frames  ==================================================== */
35523  #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Pos                            (0UL)          /*!< RXPAUSEFRM (Bit 0)                                    */
35524  #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Msk                            (0xffffUL)     /*!< RXPAUSEFRM (Bitfield-Mask: 0xffff)                    */
35525 /* ================================================  Rx_FIFO_Overflow_Frames  ================================================ */
35526  #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Pos                    (0UL)          /*!< RXFIFOOVFL (Bit 0)                                    */
35527  #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Msk                    (0xffffUL)     /*!< RXFIFOOVFL (Bitfield-Mask: 0xffff)                    */
35528 /* ================================================  Rx_VLAN_Frames_Good_Bad  ================================================ */
35529  #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Pos                    (0UL)          /*!< RXVLANFRGB (Bit 0)                                    */
35530  #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Msk                    (0xffffffffUL) /*!< RXVLANFRGB (Bitfield-Mask: 0xffffffff)               */
35531 /* ===============================================  Rx_Watchdog_Error_Frames  ================================================ */
35532  #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Pos                     (0UL)          /*!< RXWDGERR (Bit 0)                                      */
35533  #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Msk                     (0xffffUL)     /*!< RXWDGERR (Bitfield-Mask: 0xffff)                      */
35534 /* ================================================  Rx_Receive_Error_Frames  ================================================ */
35535  #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Pos                      (0UL)          /*!< RXRCVERR (Bit 0)                                      */
35536  #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Msk                      (0xffffUL)     /*!< RXRCVERR (Bitfield-Mask: 0xffff)                      */
35537 /* ================================================  Rx_Control_Frames_Good  ================================================= */
35538  #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Pos                        (0UL)          /*!< RXCTRLG (Bit 0)                                       */
35539  #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Msk                        (0xffffffffUL) /*!< RXCTRLG (Bitfield-Mask: 0xffffffff)                   */
35540 /* ======================================================  GMACTRGSEL  ======================================================= */
35541  #define R_GMAC_GMACTRGSEL_TRGSEL_Pos                                     (0UL)          /*!< TRGSEL (Bit 0)                                        */
35542  #define R_GMAC_GMACTRGSEL_TRGSEL_Msk                                     (0x3UL)        /*!< TRGSEL (Bitfield-Mask: 0x03)                          */
35543 /* ====================================================  HASH_TABLE_REG  ===================================================== */
35544  #define R_GMAC_HASH_TABLE_REG_HT_Pos                                     (0UL)          /*!< HT (Bit 0)                                            */
35545  #define R_GMAC_HASH_TABLE_REG_HT_Msk                                     (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff)                        */
35546 /* ==================================================  VLAN_Hash_Table_Reg  ================================================== */
35547  #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Pos                              (0UL)          /*!< VLHT (Bit 0)                                          */
35548  #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Msk                              (0xffffUL)     /*!< VLHT (Bitfield-Mask: 0xffff)                          */
35549 /* ===================================================  Timestamp_Control  =================================================== */
35550  #define R_GMAC_Timestamp_Control_TSENA_Pos                               (0UL)          /*!< TSENA (Bit 0)                                         */
35551  #define R_GMAC_Timestamp_Control_TSENA_Msk                               (0x1UL)        /*!< TSENA (Bitfield-Mask: 0x01)                           */
35552  #define R_GMAC_Timestamp_Control_TSENALL_Pos                             (8UL)          /*!< TSENALL (Bit 8)                                       */
35553  #define R_GMAC_Timestamp_Control_TSENALL_Msk                             (0x100UL)      /*!< TSENALL (Bitfield-Mask: 0x01)                         */
35554  #define R_GMAC_Timestamp_Control_TSCTRLSSR_Pos                           (9UL)          /*!< TSCTRLSSR (Bit 9)                                     */
35555  #define R_GMAC_Timestamp_Control_TSCTRLSSR_Msk                           (0x200UL)      /*!< TSCTRLSSR (Bitfield-Mask: 0x01)                       */
35556  #define R_GMAC_Timestamp_Control_TSVER2ENA_Pos                           (10UL)         /*!< TSVER2ENA (Bit 10)                                    */
35557  #define R_GMAC_Timestamp_Control_TSVER2ENA_Msk                           (0x400UL)      /*!< TSVER2ENA (Bitfield-Mask: 0x01)                       */
35558  #define R_GMAC_Timestamp_Control_TSIPENA_Pos                             (11UL)         /*!< TSIPENA (Bit 11)                                      */
35559  #define R_GMAC_Timestamp_Control_TSIPENA_Msk                             (0x800UL)      /*!< TSIPENA (Bitfield-Mask: 0x01)                         */
35560  #define R_GMAC_Timestamp_Control_TSIPV6ENA_Pos                           (12UL)         /*!< TSIPV6ENA (Bit 12)                                    */
35561  #define R_GMAC_Timestamp_Control_TSIPV6ENA_Msk                           (0x1000UL)     /*!< TSIPV6ENA (Bitfield-Mask: 0x01)                       */
35562  #define R_GMAC_Timestamp_Control_TSIPV4ENA_Pos                           (13UL)         /*!< TSIPV4ENA (Bit 13)                                    */
35563  #define R_GMAC_Timestamp_Control_TSIPV4ENA_Msk                           (0x2000UL)     /*!< TSIPV4ENA (Bitfield-Mask: 0x01)                       */
35564  #define R_GMAC_Timestamp_Control_TSEVNTENA_Pos                           (14UL)         /*!< TSEVNTENA (Bit 14)                                    */
35565  #define R_GMAC_Timestamp_Control_TSEVNTENA_Msk                           (0x4000UL)     /*!< TSEVNTENA (Bitfield-Mask: 0x01)                       */
35566  #define R_GMAC_Timestamp_Control_TSMSTRENA_Pos                           (15UL)         /*!< TSMSTRENA (Bit 15)                                    */
35567  #define R_GMAC_Timestamp_Control_TSMSTRENA_Msk                           (0x8000UL)     /*!< TSMSTRENA (Bitfield-Mask: 0x01)                       */
35568  #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Pos                          (16UL)         /*!< SNAPTYPSEL (Bit 16)                                   */
35569  #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Msk                          (0x30000UL)    /*!< SNAPTYPSEL (Bitfield-Mask: 0x03)                      */
35570  #define R_GMAC_Timestamp_Control_TSENMACADDR_Pos                         (18UL)         /*!< TSENMACADDR (Bit 18)                                  */
35571  #define R_GMAC_Timestamp_Control_TSENMACADDR_Msk                         (0x40000UL)    /*!< TSENMACADDR (Bitfield-Mask: 0x01)                     */
35572  #define R_GMAC_Timestamp_Control_ATSFC_Pos                               (24UL)         /*!< ATSFC (Bit 24)                                        */
35573  #define R_GMAC_Timestamp_Control_ATSFC_Msk                               (0x1000000UL)  /*!< ATSFC (Bitfield-Mask: 0x01)                           */
35574  #define R_GMAC_Timestamp_Control_ATSEN0_Pos                              (25UL)         /*!< ATSEN0 (Bit 25)                                       */
35575  #define R_GMAC_Timestamp_Control_ATSEN0_Msk                              (0x2000000UL)  /*!< ATSEN0 (Bitfield-Mask: 0x01)                          */
35576  #define R_GMAC_Timestamp_Control_ATSEN1_Pos                              (26UL)         /*!< ATSEN1 (Bit 26)                                       */
35577  #define R_GMAC_Timestamp_Control_ATSEN1_Msk                              (0x4000000UL)  /*!< ATSEN1 (Bitfield-Mask: 0x01)                          */
35578 /* ===================================================  Timestamp_Status  ==================================================== */
35579  #define R_GMAC_Timestamp_Status_AUXTSTRIG_Pos                            (2UL)          /*!< AUXTSTRIG (Bit 2)                                     */
35580  #define R_GMAC_Timestamp_Status_AUXTSTRIG_Msk                            (0x4UL)        /*!< AUXTSTRIG (Bitfield-Mask: 0x01)                       */
35581  #define R_GMAC_Timestamp_Status_ATSSTN_Pos                               (16UL)         /*!< ATSSTN (Bit 16)                                       */
35582  #define R_GMAC_Timestamp_Status_ATSSTN_Msk                               (0xf0000UL)    /*!< ATSSTN (Bitfield-Mask: 0x0f)                          */
35583  #define R_GMAC_Timestamp_Status_ATSSTM_Pos                               (24UL)         /*!< ATSSTM (Bit 24)                                       */
35584  #define R_GMAC_Timestamp_Status_ATSSTM_Msk                               (0x1000000UL)  /*!< ATSSTM (Bitfield-Mask: 0x01)                          */
35585  #define R_GMAC_Timestamp_Status_ATSNS_Pos                                (25UL)         /*!< ATSNS (Bit 25)                                        */
35586  #define R_GMAC_Timestamp_Status_ATSNS_Msk                                (0x3e000000UL) /*!< ATSNS (Bitfield-Mask: 0x1f)                           */
35587 /* ============================================  Auxiliary_Timestamp_Nanoseconds  ============================================ */
35588  #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Pos               (0UL)          /*!< AUXTSLO (Bit 0)                                       */
35589  #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Msk               (0x7fffffffUL) /*!< AUXTSLO (Bitfield-Mask: 0x7fffffff)             */
35590 /* ==============================================  Auxiliary_Timestamp_Seconds  ============================================== */
35591  #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Pos                   (0UL)          /*!< AUXTSHI (Bit 0)                                       */
35592  #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Msk                   (0xffffffffUL) /*!< AUXTSHI (Bitfield-Mask: 0xffffffff)                 */
35593 /* ========================================================  MAR16_H  ======================================================== */
35594  #define R_GMAC_MAR16_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35595  #define R_GMAC_MAR16_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35596  #define R_GMAC_MAR16_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35597  #define R_GMAC_MAR16_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35598  #define R_GMAC_MAR16_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35599  #define R_GMAC_MAR16_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35600  #define R_GMAC_MAR16_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35601  #define R_GMAC_MAR16_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35602 /* ========================================================  MAR16_L  ======================================================== */
35603  #define R_GMAC_MAR16_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35604  #define R_GMAC_MAR16_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35605 /* ========================================================  MAR17_H  ======================================================== */
35606  #define R_GMAC_MAR17_H_ADDRHI_Pos                                        (0UL)          /*!< ADDRHI (Bit 0)                                        */
35607  #define R_GMAC_MAR17_H_ADDRHI_Msk                                        (0xffffUL)     /*!< ADDRHI (Bitfield-Mask: 0xffff)                        */
35608  #define R_GMAC_MAR17_H_MBC_Pos                                           (24UL)         /*!< MBC (Bit 24)                                          */
35609  #define R_GMAC_MAR17_H_MBC_Msk                                           (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f)                             */
35610  #define R_GMAC_MAR17_H_SA_Pos                                            (30UL)         /*!< SA (Bit 30)                                           */
35611  #define R_GMAC_MAR17_H_SA_Msk                                            (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01)                              */
35612  #define R_GMAC_MAR17_H_AE_Pos                                            (31UL)         /*!< AE (Bit 31)                                           */
35613  #define R_GMAC_MAR17_H_AE_Msk                                            (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01)                              */
35614 /* ========================================================  MAR17_L  ======================================================== */
35615  #define R_GMAC_MAR17_L_ADDRLO_Pos                                        (0UL)          /*!< ADDRLO (Bit 0)                                        */
35616  #define R_GMAC_MAR17_L_ADDRLO_Msk                                        (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff)                    */
35617 /* =======================================================  Bus_Mode  ======================================================== */
35618  #define R_GMAC_Bus_Mode_SWR_Pos                                          (0UL)          /*!< SWR (Bit 0)                                           */
35619  #define R_GMAC_Bus_Mode_SWR_Msk                                          (0x1UL)        /*!< SWR (Bitfield-Mask: 0x01)                             */
35620  #define R_GMAC_Bus_Mode_DA_Pos                                           (1UL)          /*!< DA (Bit 1)                                            */
35621  #define R_GMAC_Bus_Mode_DA_Msk                                           (0x2UL)        /*!< DA (Bitfield-Mask: 0x01)                              */
35622  #define R_GMAC_Bus_Mode_DSL_Pos                                          (2UL)          /*!< DSL (Bit 2)                                           */
35623  #define R_GMAC_Bus_Mode_DSL_Msk                                          (0x7cUL)       /*!< DSL (Bitfield-Mask: 0x1f)                             */
35624  #define R_GMAC_Bus_Mode_ATDS_Pos                                         (7UL)          /*!< ATDS (Bit 7)                                          */
35625  #define R_GMAC_Bus_Mode_ATDS_Msk                                         (0x80UL)       /*!< ATDS (Bitfield-Mask: 0x01)                            */
35626  #define R_GMAC_Bus_Mode_PBL_Pos                                          (8UL)          /*!< PBL (Bit 8)                                           */
35627  #define R_GMAC_Bus_Mode_PBL_Msk                                          (0x3f00UL)     /*!< PBL (Bitfield-Mask: 0x3f)                             */
35628  #define R_GMAC_Bus_Mode_PR_Pos                                           (14UL)         /*!< PR (Bit 14)                                           */
35629  #define R_GMAC_Bus_Mode_PR_Msk                                           (0xc000UL)     /*!< PR (Bitfield-Mask: 0x03)                              */
35630  #define R_GMAC_Bus_Mode_FB_Pos                                           (16UL)         /*!< FB (Bit 16)                                           */
35631  #define R_GMAC_Bus_Mode_FB_Msk                                           (0x10000UL)    /*!< FB (Bitfield-Mask: 0x01)                              */
35632  #define R_GMAC_Bus_Mode_RPBL_Pos                                         (17UL)         /*!< RPBL (Bit 17)                                         */
35633  #define R_GMAC_Bus_Mode_RPBL_Msk                                         (0x7e0000UL)   /*!< RPBL (Bitfield-Mask: 0x3f)                            */
35634  #define R_GMAC_Bus_Mode_USP_Pos                                          (23UL)         /*!< USP (Bit 23)                                          */
35635  #define R_GMAC_Bus_Mode_USP_Msk                                          (0x800000UL)   /*!< USP (Bitfield-Mask: 0x01)                             */
35636  #define R_GMAC_Bus_Mode_PBLx8_Pos                                        (24UL)         /*!< PBLx8 (Bit 24)                                        */
35637  #define R_GMAC_Bus_Mode_PBLx8_Msk                                        (0x1000000UL)  /*!< PBLx8 (Bitfield-Mask: 0x01)                           */
35638  #define R_GMAC_Bus_Mode_AAL_Pos                                          (25UL)         /*!< AAL (Bit 25)                                          */
35639  #define R_GMAC_Bus_Mode_AAL_Msk                                          (0x2000000UL)  /*!< AAL (Bitfield-Mask: 0x01)                             */
35640  #define R_GMAC_Bus_Mode_MB_Pos                                           (26UL)         /*!< MB (Bit 26)                                           */
35641  #define R_GMAC_Bus_Mode_MB_Msk                                           (0x4000000UL)  /*!< MB (Bitfield-Mask: 0x01)                              */
35642  #define R_GMAC_Bus_Mode_TXPR_Pos                                         (27UL)         /*!< TXPR (Bit 27)                                         */
35643  #define R_GMAC_Bus_Mode_TXPR_Msk                                         (0x8000000UL)  /*!< TXPR (Bitfield-Mask: 0x01)                            */
35644  #define R_GMAC_Bus_Mode_PRWG_Pos                                         (28UL)         /*!< PRWG (Bit 28)                                         */
35645  #define R_GMAC_Bus_Mode_PRWG_Msk                                         (0x30000000UL) /*!< PRWG (Bitfield-Mask: 0x03)                            */
35646  #define R_GMAC_Bus_Mode_RIB_Pos                                          (31UL)         /*!< RIB (Bit 31)                                          */
35647  #define R_GMAC_Bus_Mode_RIB_Msk                                          (0x80000000UL) /*!< RIB (Bitfield-Mask: 0x01)                             */
35648 /* =================================================  Transmit_Poll_Demand  ================================================== */
35649  #define R_GMAC_Transmit_Poll_Demand_TPD_Pos                              (0UL)          /*!< TPD (Bit 0)                                           */
35650  #define R_GMAC_Transmit_Poll_Demand_TPD_Msk                              (0xffffffffUL) /*!< TPD (Bitfield-Mask: 0xffffffff)                       */
35651 /* ==================================================  Receive_Poll_Demand  ================================================== */
35652  #define R_GMAC_Receive_Poll_Demand_RPD_Pos                               (0UL)          /*!< RPD (Bit 0)                                           */
35653  #define R_GMAC_Receive_Poll_Demand_RPD_Msk                               (0xffffffffUL) /*!< RPD (Bitfield-Mask: 0xffffffff)                       */
35654 /* ============================================  Receive_Descriptor_List_Address  ============================================ */
35655  #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Pos          (2UL)          /*!< RDESLA_32bit (Bit 2)                                */
35656  #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Msk          (0xfffffffcUL) /*!< RDESLA_32bit (Bitfield-Mask: 0x3fffffff)   */
35657 /* ===========================================  Transmit_Descriptor_List_Address  ============================================ */
35658  #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Pos         (2UL)          /*!< TDESLA_32bit (Bit 2)                               */
35659  #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Msk         (0xfffffffcUL) /*!< TDESLA_32bit (Bitfield-Mask: 0x3fffffff)  */
35660 /* ========================================================  Status  ========================================================= */
35661  #define R_GMAC_Status_TI_Pos                                             (0UL)          /*!< TI (Bit 0)                                            */
35662  #define R_GMAC_Status_TI_Msk                                             (0x1UL)        /*!< TI (Bitfield-Mask: 0x01)                              */
35663  #define R_GMAC_Status_TPS_Pos                                            (1UL)          /*!< TPS (Bit 1)                                           */
35664  #define R_GMAC_Status_TPS_Msk                                            (0x2UL)        /*!< TPS (Bitfield-Mask: 0x01)                             */
35665  #define R_GMAC_Status_TU_Pos                                             (2UL)          /*!< TU (Bit 2)                                            */
35666  #define R_GMAC_Status_TU_Msk                                             (0x4UL)        /*!< TU (Bitfield-Mask: 0x01)                              */
35667  #define R_GMAC_Status_TJT_Pos                                            (3UL)          /*!< TJT (Bit 3)                                           */
35668  #define R_GMAC_Status_TJT_Msk                                            (0x8UL)        /*!< TJT (Bitfield-Mask: 0x01)                             */
35669  #define R_GMAC_Status_OVF_Pos                                            (4UL)          /*!< OVF (Bit 4)                                           */
35670  #define R_GMAC_Status_OVF_Msk                                            (0x10UL)       /*!< OVF (Bitfield-Mask: 0x01)                             */
35671  #define R_GMAC_Status_UNF_Pos                                            (5UL)          /*!< UNF (Bit 5)                                           */
35672  #define R_GMAC_Status_UNF_Msk                                            (0x20UL)       /*!< UNF (Bitfield-Mask: 0x01)                             */
35673  #define R_GMAC_Status_RI_Pos                                             (6UL)          /*!< RI (Bit 6)                                            */
35674  #define R_GMAC_Status_RI_Msk                                             (0x40UL)       /*!< RI (Bitfield-Mask: 0x01)                              */
35675  #define R_GMAC_Status_RU_Pos                                             (7UL)          /*!< RU (Bit 7)                                            */
35676  #define R_GMAC_Status_RU_Msk                                             (0x80UL)       /*!< RU (Bitfield-Mask: 0x01)                              */
35677  #define R_GMAC_Status_RPS_Pos                                            (8UL)          /*!< RPS (Bit 8)                                           */
35678  #define R_GMAC_Status_RPS_Msk                                            (0x100UL)      /*!< RPS (Bitfield-Mask: 0x01)                             */
35679  #define R_GMAC_Status_RWT_Pos                                            (9UL)          /*!< RWT (Bit 9)                                           */
35680  #define R_GMAC_Status_RWT_Msk                                            (0x200UL)      /*!< RWT (Bitfield-Mask: 0x01)                             */
35681  #define R_GMAC_Status_ETI_Pos                                            (10UL)         /*!< ETI (Bit 10)                                          */
35682  #define R_GMAC_Status_ETI_Msk                                            (0x400UL)      /*!< ETI (Bitfield-Mask: 0x01)                             */
35683  #define R_GMAC_Status_FBI_Pos                                            (13UL)         /*!< FBI (Bit 13)                                          */
35684  #define R_GMAC_Status_FBI_Msk                                            (0x2000UL)     /*!< FBI (Bitfield-Mask: 0x01)                             */
35685  #define R_GMAC_Status_ERI_Pos                                            (14UL)         /*!< ERI (Bit 14)                                          */
35686  #define R_GMAC_Status_ERI_Msk                                            (0x4000UL)     /*!< ERI (Bitfield-Mask: 0x01)                             */
35687  #define R_GMAC_Status_AIS_Pos                                            (15UL)         /*!< AIS (Bit 15)                                          */
35688  #define R_GMAC_Status_AIS_Msk                                            (0x8000UL)     /*!< AIS (Bitfield-Mask: 0x01)                             */
35689  #define R_GMAC_Status_NIS_Pos                                            (16UL)         /*!< NIS (Bit 16)                                          */
35690  #define R_GMAC_Status_NIS_Msk                                            (0x10000UL)    /*!< NIS (Bitfield-Mask: 0x01)                             */
35691  #define R_GMAC_Status_RS_Pos                                             (17UL)         /*!< RS (Bit 17)                                           */
35692  #define R_GMAC_Status_RS_Msk                                             (0xe0000UL)    /*!< RS (Bitfield-Mask: 0x07)                              */
35693  #define R_GMAC_Status_TS_Pos                                             (20UL)         /*!< TS (Bit 20)                                           */
35694  #define R_GMAC_Status_TS_Msk                                             (0x700000UL)   /*!< TS (Bitfield-Mask: 0x07)                              */
35695  #define R_GMAC_Status_EB_Pos                                             (23UL)         /*!< EB (Bit 23)                                           */
35696  #define R_GMAC_Status_EB_Msk                                             (0x3800000UL)  /*!< EB (Bitfield-Mask: 0x07)                              */
35697  #define R_GMAC_Status_GMI_Pos                                            (27UL)         /*!< GMI (Bit 27)                                          */
35698  #define R_GMAC_Status_GMI_Msk                                            (0x8000000UL)  /*!< GMI (Bitfield-Mask: 0x01)                             */
35699  #define R_GMAC_Status_GPI_Pos                                            (28UL)         /*!< GPI (Bit 28)                                          */
35700  #define R_GMAC_Status_GPI_Msk                                            (0x10000000UL) /*!< GPI (Bitfield-Mask: 0x01)                             */
35701  #define R_GMAC_Status_TTI_Pos                                            (29UL)         /*!< TTI (Bit 29)                                          */
35702  #define R_GMAC_Status_TTI_Msk                                            (0x20000000UL) /*!< TTI (Bitfield-Mask: 0x01)                             */
35703  #define R_GMAC_Status_GLPII_Pos                                          (30UL)         /*!< GLPII (Bit 30)                                        */
35704  #define R_GMAC_Status_GLPII_Msk                                          (0x40000000UL) /*!< GLPII (Bitfield-Mask: 0x01)                           */
35705 /* ====================================================  Operation_Mode  ===================================================== */
35706  #define R_GMAC_Operation_Mode_SR_Pos                                     (1UL)          /*!< SR (Bit 1)                                            */
35707  #define R_GMAC_Operation_Mode_SR_Msk                                     (0x2UL)        /*!< SR (Bitfield-Mask: 0x01)                              */
35708  #define R_GMAC_Operation_Mode_OSF_Pos                                    (2UL)          /*!< OSF (Bit 2)                                           */
35709  #define R_GMAC_Operation_Mode_OSF_Msk                                    (0x4UL)        /*!< OSF (Bitfield-Mask: 0x01)                             */
35710  #define R_GMAC_Operation_Mode_RTC_Pos                                    (3UL)          /*!< RTC (Bit 3)                                           */
35711  #define R_GMAC_Operation_Mode_RTC_Msk                                    (0x18UL)       /*!< RTC (Bitfield-Mask: 0x03)                             */
35712  #define R_GMAC_Operation_Mode_DGF_Pos                                    (5UL)          /*!< DGF (Bit 5)                                           */
35713  #define R_GMAC_Operation_Mode_DGF_Msk                                    (0x20UL)       /*!< DGF (Bitfield-Mask: 0x01)                             */
35714  #define R_GMAC_Operation_Mode_FUF_Pos                                    (6UL)          /*!< FUF (Bit 6)                                           */
35715  #define R_GMAC_Operation_Mode_FUF_Msk                                    (0x40UL)       /*!< FUF (Bitfield-Mask: 0x01)                             */
35716  #define R_GMAC_Operation_Mode_FEF_Pos                                    (7UL)          /*!< FEF (Bit 7)                                           */
35717  #define R_GMAC_Operation_Mode_FEF_Msk                                    (0x80UL)       /*!< FEF (Bitfield-Mask: 0x01)                             */
35718  #define R_GMAC_Operation_Mode_EFC_Pos                                    (8UL)          /*!< EFC (Bit 8)                                           */
35719  #define R_GMAC_Operation_Mode_EFC_Msk                                    (0x100UL)      /*!< EFC (Bitfield-Mask: 0x01)                             */
35720  #define R_GMAC_Operation_Mode_RFA_Pos                                    (9UL)          /*!< RFA (Bit 9)                                           */
35721  #define R_GMAC_Operation_Mode_RFA_Msk                                    (0x600UL)      /*!< RFA (Bitfield-Mask: 0x03)                             */
35722  #define R_GMAC_Operation_Mode_RFD_Pos                                    (11UL)         /*!< RFD (Bit 11)                                          */
35723  #define R_GMAC_Operation_Mode_RFD_Msk                                    (0x1800UL)     /*!< RFD (Bitfield-Mask: 0x03)                             */
35724  #define R_GMAC_Operation_Mode_ST_Pos                                     (13UL)         /*!< ST (Bit 13)                                           */
35725  #define R_GMAC_Operation_Mode_ST_Msk                                     (0x2000UL)     /*!< ST (Bitfield-Mask: 0x01)                              */
35726  #define R_GMAC_Operation_Mode_TTC_Pos                                    (14UL)         /*!< TTC (Bit 14)                                          */
35727  #define R_GMAC_Operation_Mode_TTC_Msk                                    (0x1c000UL)    /*!< TTC (Bitfield-Mask: 0x07)                             */
35728  #define R_GMAC_Operation_Mode_FTF_Pos                                    (20UL)         /*!< FTF (Bit 20)                                          */
35729  #define R_GMAC_Operation_Mode_FTF_Msk                                    (0x100000UL)   /*!< FTF (Bitfield-Mask: 0x01)                             */
35730  #define R_GMAC_Operation_Mode_TSF_Pos                                    (21UL)         /*!< TSF (Bit 21)                                          */
35731  #define R_GMAC_Operation_Mode_TSF_Msk                                    (0x200000UL)   /*!< TSF (Bitfield-Mask: 0x01)                             */
35732  #define R_GMAC_Operation_Mode_RSF_Pos                                    (25UL)         /*!< RSF (Bit 25)                                          */
35733  #define R_GMAC_Operation_Mode_RSF_Msk                                    (0x2000000UL)  /*!< RSF (Bitfield-Mask: 0x01)                             */
35734  #define R_GMAC_Operation_Mode_DT_Pos                                     (26UL)         /*!< DT (Bit 26)                                           */
35735  #define R_GMAC_Operation_Mode_DT_Msk                                     (0x4000000UL)  /*!< DT (Bitfield-Mask: 0x01)                              */
35736 /* ===================================================  Interrupt_Enable  ==================================================== */
35737  #define R_GMAC_Interrupt_Enable_TIE_Pos                                  (0UL)          /*!< TIE (Bit 0)                                           */
35738  #define R_GMAC_Interrupt_Enable_TIE_Msk                                  (0x1UL)        /*!< TIE (Bitfield-Mask: 0x01)                             */
35739  #define R_GMAC_Interrupt_Enable_TSE_Pos                                  (1UL)          /*!< TSE (Bit 1)                                           */
35740  #define R_GMAC_Interrupt_Enable_TSE_Msk                                  (0x2UL)        /*!< TSE (Bitfield-Mask: 0x01)                             */
35741  #define R_GMAC_Interrupt_Enable_TUE_Pos                                  (2UL)          /*!< TUE (Bit 2)                                           */
35742  #define R_GMAC_Interrupt_Enable_TUE_Msk                                  (0x4UL)        /*!< TUE (Bitfield-Mask: 0x01)                             */
35743  #define R_GMAC_Interrupt_Enable_TJE_Pos                                  (3UL)          /*!< TJE (Bit 3)                                           */
35744  #define R_GMAC_Interrupt_Enable_TJE_Msk                                  (0x8UL)        /*!< TJE (Bitfield-Mask: 0x01)                             */
35745  #define R_GMAC_Interrupt_Enable_OVE_Pos                                  (4UL)          /*!< OVE (Bit 4)                                           */
35746  #define R_GMAC_Interrupt_Enable_OVE_Msk                                  (0x10UL)       /*!< OVE (Bitfield-Mask: 0x01)                             */
35747  #define R_GMAC_Interrupt_Enable_UNE_Pos                                  (5UL)          /*!< UNE (Bit 5)                                           */
35748  #define R_GMAC_Interrupt_Enable_UNE_Msk                                  (0x20UL)       /*!< UNE (Bitfield-Mask: 0x01)                             */
35749  #define R_GMAC_Interrupt_Enable_RIE_Pos                                  (6UL)          /*!< RIE (Bit 6)                                           */
35750  #define R_GMAC_Interrupt_Enable_RIE_Msk                                  (0x40UL)       /*!< RIE (Bitfield-Mask: 0x01)                             */
35751  #define R_GMAC_Interrupt_Enable_RUE_Pos                                  (7UL)          /*!< RUE (Bit 7)                                           */
35752  #define R_GMAC_Interrupt_Enable_RUE_Msk                                  (0x80UL)       /*!< RUE (Bitfield-Mask: 0x01)                             */
35753  #define R_GMAC_Interrupt_Enable_RSE_Pos                                  (8UL)          /*!< RSE (Bit 8)                                           */
35754  #define R_GMAC_Interrupt_Enable_RSE_Msk                                  (0x100UL)      /*!< RSE (Bitfield-Mask: 0x01)                             */
35755  #define R_GMAC_Interrupt_Enable_RWE_Pos                                  (9UL)          /*!< RWE (Bit 9)                                           */
35756  #define R_GMAC_Interrupt_Enable_RWE_Msk                                  (0x200UL)      /*!< RWE (Bitfield-Mask: 0x01)                             */
35757  #define R_GMAC_Interrupt_Enable_ETE_Pos                                  (10UL)         /*!< ETE (Bit 10)                                          */
35758  #define R_GMAC_Interrupt_Enable_ETE_Msk                                  (0x400UL)      /*!< ETE (Bitfield-Mask: 0x01)                             */
35759  #define R_GMAC_Interrupt_Enable_FBE_Pos                                  (13UL)         /*!< FBE (Bit 13)                                          */
35760  #define R_GMAC_Interrupt_Enable_FBE_Msk                                  (0x2000UL)     /*!< FBE (Bitfield-Mask: 0x01)                             */
35761  #define R_GMAC_Interrupt_Enable_ERE_Pos                                  (14UL)         /*!< ERE (Bit 14)                                          */
35762  #define R_GMAC_Interrupt_Enable_ERE_Msk                                  (0x4000UL)     /*!< ERE (Bitfield-Mask: 0x01)                             */
35763  #define R_GMAC_Interrupt_Enable_AIE_Pos                                  (15UL)         /*!< AIE (Bit 15)                                          */
35764  #define R_GMAC_Interrupt_Enable_AIE_Msk                                  (0x8000UL)     /*!< AIE (Bitfield-Mask: 0x01)                             */
35765  #define R_GMAC_Interrupt_Enable_NIE_Pos                                  (16UL)         /*!< NIE (Bit 16)                                          */
35766  #define R_GMAC_Interrupt_Enable_NIE_Msk                                  (0x10000UL)    /*!< NIE (Bitfield-Mask: 0x01)                             */
35767 /* =======================================  Missed_Frame_And_Buffer_Overflow_Counter  ======================================== */
35768  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Pos    (0UL)          /*!< MISFRMCNT (Bit 0)                             */
35769  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Msk    (0xffffUL)     /*!< MISFRMCNT (Bitfield-Mask: 0xffff)        */
35770  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Pos    (16UL)         /*!< MISCNTOVF (Bit 16)                           */
35771  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Msk    (0x10000UL)    /*!< MISCNTOVF (Bitfield-Mask: 0x01)         */
35772  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Pos    (17UL)         /*!< OVFFRMCNT (Bit 17)                           */
35773  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Msk    (0xffe0000UL)  /*!< OVFFRMCNT (Bitfield-Mask: 0x7ff)      */
35774  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Pos    (28UL)         /*!< OVFCNTOVF (Bit 28)                           */
35775  #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Msk    (0x10000000UL) /*!< OVFCNTOVF (Bitfield-Mask: 0x01)      */
35776 /* ===========================================  Receive_Interrupt_Watchdog_Timer  ============================================ */
35777  #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Pos                 (0UL)          /*!< RIWT (Bit 0)                                          */
35778  #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Msk                 (0xffUL)       /*!< RIWT (Bitfield-Mask: 0xff)                            */
35779 /* =====================================================  AXI_Bus_Mode  ====================================================== */
35780  #define R_GMAC_AXI_Bus_Mode_UNDEF_Pos                                    (0UL)          /*!< UNDEF (Bit 0)                                         */
35781  #define R_GMAC_AXI_Bus_Mode_UNDEF_Msk                                    (0x1UL)        /*!< UNDEF (Bitfield-Mask: 0x01)                           */
35782  #define R_GMAC_AXI_Bus_Mode_BLEN4_Pos                                    (1UL)          /*!< BLEN4 (Bit 1)                                         */
35783  #define R_GMAC_AXI_Bus_Mode_BLEN4_Msk                                    (0x2UL)        /*!< BLEN4 (Bitfield-Mask: 0x01)                           */
35784  #define R_GMAC_AXI_Bus_Mode_BLEN8_Pos                                    (2UL)          /*!< BLEN8 (Bit 2)                                         */
35785  #define R_GMAC_AXI_Bus_Mode_BLEN8_Msk                                    (0x4UL)        /*!< BLEN8 (Bitfield-Mask: 0x01)                           */
35786  #define R_GMAC_AXI_Bus_Mode_BLEN16_Pos                                   (3UL)          /*!< BLEN16 (Bit 3)                                        */
35787  #define R_GMAC_AXI_Bus_Mode_BLEN16_Msk                                   (0x8UL)        /*!< BLEN16 (Bitfield-Mask: 0x01)                          */
35788  #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Pos                                  (12UL)         /*!< AXI_AAL (Bit 12)                                      */
35789  #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Msk                                  (0x1000UL)     /*!< AXI_AAL (Bitfield-Mask: 0x01)                         */
35790  #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Pos                                  (13UL)         /*!< ONEKBBE (Bit 13)                                      */
35791  #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Msk                                  (0x2000UL)     /*!< ONEKBBE (Bitfield-Mask: 0x01)                         */
35792  #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Pos                               (16UL)         /*!< RD_OSR_LMT (Bit 16)                                   */
35793  #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Msk                               (0x30000UL)    /*!< RD_OSR_LMT (Bitfield-Mask: 0x03)                      */
35794  #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Pos                               (20UL)         /*!< WR_OSR_LMT (Bit 20)                                   */
35795  #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Msk                               (0x300000UL)   /*!< WR_OSR_LMT (Bitfield-Mask: 0x03)                      */
35796  #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Pos                              (30UL)         /*!< LPI_XIT_FRM (Bit 30)                                  */
35797  #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Msk                              (0x40000000UL) /*!< LPI_XIT_FRM (Bitfield-Mask: 0x01)                     */
35798  #define R_GMAC_AXI_Bus_Mode_EN_LPI_Pos                                   (31UL)         /*!< EN_LPI (Bit 31)                                       */
35799  #define R_GMAC_AXI_Bus_Mode_EN_LPI_Msk                                   (0x80000000UL) /*!< EN_LPI (Bitfield-Mask: 0x01)                          */
35800 /* ======================================================  AXI_Status  ======================================================= */
35801  #define R_GMAC_AXI_Status_AXWHSTS_Pos                                    (0UL)          /*!< AXWHSTS (Bit 0)                                       */
35802  #define R_GMAC_AXI_Status_AXWHSTS_Msk                                    (0x1UL)        /*!< AXWHSTS (Bitfield-Mask: 0x01)                         */
35803  #define R_GMAC_AXI_Status_AXIRDSTS_Pos                                   (1UL)          /*!< AXIRDSTS (Bit 1)                                      */
35804  #define R_GMAC_AXI_Status_AXIRDSTS_Msk                                   (0x2UL)        /*!< AXIRDSTS (Bitfield-Mask: 0x01)                        */
35805 /* ===========================================  Current_Host_Transmit_Descriptor  ============================================ */
35806  #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Pos          (0UL)          /*!< CURTDESAPTR (Bit 0)                                 */
35807  #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Msk          (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff)    */
35808 /* ============================================  Current_Host_Receive_Descriptor  ============================================ */
35809  #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Pos           (0UL)          /*!< CURRDESAPTR (Bit 0)                                  */
35810  #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Msk           (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff)     */
35811 /* =========================================  Current_Host_Transmit_Buffer_Address  ========================================== */
35812  #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Pos      (0UL)          /*!< CURTBUFAPTR (Bit 0)                             */
35813  #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Msk      (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff) */
35814 /* ==========================================  Current_Host_Receive_Buffer_Address  ========================================== */
35815  #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Pos       (0UL)          /*!< CURRBUFAPTR (Bit 0)                              */
35816  #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Msk       (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff) */
35817 /* ======================================================  HW_Feature  ======================================================= */
35818  #define R_GMAC_HW_Feature_MIISEL_Pos                                     (0UL)          /*!< MIISEL (Bit 0)                                        */
35819  #define R_GMAC_HW_Feature_MIISEL_Msk                                     (0x1UL)        /*!< MIISEL (Bitfield-Mask: 0x01)                          */
35820  #define R_GMAC_HW_Feature_GMIISEL_Pos                                    (1UL)          /*!< GMIISEL (Bit 1)                                       */
35821  #define R_GMAC_HW_Feature_GMIISEL_Msk                                    (0x2UL)        /*!< GMIISEL (Bitfield-Mask: 0x01)                         */
35822  #define R_GMAC_HW_Feature_HDSEL_Pos                                      (2UL)          /*!< HDSEL (Bit 2)                                         */
35823  #define R_GMAC_HW_Feature_HDSEL_Msk                                      (0x4UL)        /*!< HDSEL (Bitfield-Mask: 0x01)                           */
35824  #define R_GMAC_HW_Feature_EXTHASHEN_Pos                                  (3UL)          /*!< EXTHASHEN (Bit 3)                                     */
35825  #define R_GMAC_HW_Feature_EXTHASHEN_Msk                                  (0x8UL)        /*!< EXTHASHEN (Bitfield-Mask: 0x01)                       */
35826  #define R_GMAC_HW_Feature_HASHSEL_Pos                                    (4UL)          /*!< HASHSEL (Bit 4)                                       */
35827  #define R_GMAC_HW_Feature_HASHSEL_Msk                                    (0x10UL)       /*!< HASHSEL (Bitfield-Mask: 0x01)                         */
35828  #define R_GMAC_HW_Feature_ADDMACADRSEL_Pos                               (5UL)          /*!< ADDMACADRSEL (Bit 5)                                  */
35829  #define R_GMAC_HW_Feature_ADDMACADRSEL_Msk                               (0x20UL)       /*!< ADDMACADRSEL (Bitfield-Mask: 0x01)                    */
35830  #define R_GMAC_HW_Feature_L3L4FLTREN_Pos                                 (7UL)          /*!< L3L4FLTREN (Bit 7)                                    */
35831  #define R_GMAC_HW_Feature_L3L4FLTREN_Msk                                 (0x80UL)       /*!< L3L4FLTREN (Bitfield-Mask: 0x01)                      */
35832  #define R_GMAC_HW_Feature_SMASEL_Pos                                     (8UL)          /*!< SMASEL (Bit 8)                                        */
35833  #define R_GMAC_HW_Feature_SMASEL_Msk                                     (0x100UL)      /*!< SMASEL (Bitfield-Mask: 0x01)                          */
35834  #define R_GMAC_HW_Feature_RWKSEL_Pos                                     (9UL)          /*!< RWKSEL (Bit 9)                                        */
35835  #define R_GMAC_HW_Feature_RWKSEL_Msk                                     (0x200UL)      /*!< RWKSEL (Bitfield-Mask: 0x01)                          */
35836  #define R_GMAC_HW_Feature_MGKSEL_Pos                                     (10UL)         /*!< MGKSEL (Bit 10)                                       */
35837  #define R_GMAC_HW_Feature_MGKSEL_Msk                                     (0x400UL)      /*!< MGKSEL (Bitfield-Mask: 0x01)                          */
35838  #define R_GMAC_HW_Feature_MMCSEL_Pos                                     (11UL)         /*!< MMCSEL (Bit 11)                                       */
35839  #define R_GMAC_HW_Feature_MMCSEL_Msk                                     (0x800UL)      /*!< MMCSEL (Bitfield-Mask: 0x01)                          */
35840  #define R_GMAC_HW_Feature_TSVER1SEL_Pos                                  (12UL)         /*!< TSVER1SEL (Bit 12)                                    */
35841  #define R_GMAC_HW_Feature_TSVER1SEL_Msk                                  (0x1000UL)     /*!< TSVER1SEL (Bitfield-Mask: 0x01)                       */
35842  #define R_GMAC_HW_Feature_TSVER2SEL_Pos                                  (13UL)         /*!< TSVER2SEL (Bit 13)                                    */
35843  #define R_GMAC_HW_Feature_TSVER2SEL_Msk                                  (0x2000UL)     /*!< TSVER2SEL (Bitfield-Mask: 0x01)                       */
35844  #define R_GMAC_HW_Feature_EEESEL_Pos                                     (14UL)         /*!< EEESEL (Bit 14)                                       */
35845  #define R_GMAC_HW_Feature_EEESEL_Msk                                     (0x4000UL)     /*!< EEESEL (Bitfield-Mask: 0x01)                          */
35846  #define R_GMAC_HW_Feature_AVSEL_Pos                                      (15UL)         /*!< AVSEL (Bit 15)                                        */
35847  #define R_GMAC_HW_Feature_AVSEL_Msk                                      (0x8000UL)     /*!< AVSEL (Bitfield-Mask: 0x01)                           */
35848  #define R_GMAC_HW_Feature_TXCOESEL_Pos                                   (16UL)         /*!< TXCOESEL (Bit 16)                                     */
35849  #define R_GMAC_HW_Feature_TXCOESEL_Msk                                   (0x10000UL)    /*!< TXCOESEL (Bitfield-Mask: 0x01)                        */
35850  #define R_GMAC_HW_Feature_RXTYP1COE_Pos                                  (17UL)         /*!< RXTYP1COE (Bit 17)                                    */
35851  #define R_GMAC_HW_Feature_RXTYP1COE_Msk                                  (0x20000UL)    /*!< RXTYP1COE (Bitfield-Mask: 0x01)                       */
35852  #define R_GMAC_HW_Feature_RXTYP2COE_Pos                                  (18UL)         /*!< RXTYP2COE (Bit 18)                                    */
35853  #define R_GMAC_HW_Feature_RXTYP2COE_Msk                                  (0x40000UL)    /*!< RXTYP2COE (Bitfield-Mask: 0x01)                       */
35854  #define R_GMAC_HW_Feature_RXFIFOSIZE_Pos                                 (19UL)         /*!< RXFIFOSIZE (Bit 19)                                   */
35855  #define R_GMAC_HW_Feature_RXFIFOSIZE_Msk                                 (0x80000UL)    /*!< RXFIFOSIZE (Bitfield-Mask: 0x01)                      */
35856  #define R_GMAC_HW_Feature_RXCHCNT_Pos                                    (20UL)         /*!< RXCHCNT (Bit 20)                                      */
35857  #define R_GMAC_HW_Feature_RXCHCNT_Msk                                    (0x300000UL)   /*!< RXCHCNT (Bitfield-Mask: 0x03)                         */
35858  #define R_GMAC_HW_Feature_TXCHCNT_Pos                                    (22UL)         /*!< TXCHCNT (Bit 22)                                      */
35859  #define R_GMAC_HW_Feature_TXCHCNT_Msk                                    (0xc00000UL)   /*!< TXCHCNT (Bitfield-Mask: 0x03)                         */
35860  #define R_GMAC_HW_Feature_ENHDESSEL_Pos                                  (24UL)         /*!< ENHDESSEL (Bit 24)                                    */
35861  #define R_GMAC_HW_Feature_ENHDESSEL_Msk                                  (0x1000000UL)  /*!< ENHDESSEL (Bitfield-Mask: 0x01)                       */
35862  #define R_GMAC_HW_Feature_INTTSEN_Pos                                    (25UL)         /*!< INTTSEN (Bit 25)                                      */
35863  #define R_GMAC_HW_Feature_INTTSEN_Msk                                    (0x2000000UL)  /*!< INTTSEN (Bitfield-Mask: 0x01)                         */
35864  #define R_GMAC_HW_Feature_FLEXIPPSEN_Pos                                 (26UL)         /*!< FLEXIPPSEN (Bit 26)                                   */
35865  #define R_GMAC_HW_Feature_FLEXIPPSEN_Msk                                 (0x4000000UL)  /*!< FLEXIPPSEN (Bitfield-Mask: 0x01)                      */
35866  #define R_GMAC_HW_Feature_SAVLANINS_Pos                                  (27UL)         /*!< SAVLANINS (Bit 27)                                    */
35867  #define R_GMAC_HW_Feature_SAVLANINS_Msk                                  (0x8000000UL)  /*!< SAVLANINS (Bitfield-Mask: 0x01)                       */
35868  #define R_GMAC_HW_Feature_ACTPHYIF_Pos                                   (28UL)         /*!< ACTPHYIF (Bit 28)                                     */
35869  #define R_GMAC_HW_Feature_ACTPHYIF_Msk                                   (0x70000000UL) /*!< ACTPHYIF (Bitfield-Mask: 0x07)                        */
35870 
35871 /* =========================================================================================================================== */
35872 /* ================                                          R_ETHSS                                          ================ */
35873 /* =========================================================================================================================== */
35874 
35875 /* =========================================================  PRCMD  ========================================================= */
35876 /* ========================================================  MODCTRL  ======================================================== */
35877  #define R_ETHSS_MODCTRL_SW_MODE_Pos           (0UL)       /*!< SW_MODE (Bit 0)                                       */
35878  #define R_ETHSS_MODCTRL_SW_MODE_Msk           (0x7UL)     /*!< SW_MODE (Bitfield-Mask: 0x07)                         */
35879 /* =======================================================  PTPMCTRL  ======================================================== */
35880  #define R_ETHSS_PTPMCTRL_PTP_MODE_Pos         (0UL)       /*!< PTP_MODE (Bit 0)                                      */
35881  #define R_ETHSS_PTPMCTRL_PTP_MODE_Msk         (0x1UL)     /*!< PTP_MODE (Bitfield-Mask: 0x01)                        */
35882  #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Pos     (16UL)      /*!< PTP_PLS_RSTn (Bit 16)                                 */
35883  #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Msk     (0x10000UL) /*!< PTP_PLS_RSTn (Bitfield-Mask: 0x01)                    */
35884 /* ========================================================  PHYLNK  ========================================================= */
35885  #define R_ETHSS_PHYLNK_SWLINK_Pos             (0UL)       /*!< SWLINK (Bit 0)                                        */
35886  #define R_ETHSS_PHYLNK_SWLINK_Msk             (0x7UL)     /*!< SWLINK (Bitfield-Mask: 0x07)                          */
35887  #define R_ETHSS_PHYLNK_CATLNK_Pos             (4UL)       /*!< CATLNK (Bit 4)                                        */
35888  #define R_ETHSS_PHYLNK_CATLNK_Msk             (0x70UL)    /*!< CATLNK (Bitfield-Mask: 0x07)                          */
35889 /* =======================================================  CONVCTRL  ======================================================== */
35890  #define R_ETHSS_CONVCTRL_CONV_MODE_Pos        (0UL)       /*!< CONV_MODE (Bit 0)                                     */
35891  #define R_ETHSS_CONVCTRL_CONV_MODE_Msk        (0x1fUL)    /*!< CONV_MODE (Bitfield-Mask: 0x1f)                       */
35892  #define R_ETHSS_CONVCTRL_FULLD_Pos            (8UL)       /*!< FULLD (Bit 8)                                         */
35893  #define R_ETHSS_CONVCTRL_FULLD_Msk            (0x100UL)   /*!< FULLD (Bitfield-Mask: 0x01)                           */
35894  #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Pos    (9UL)       /*!< RMII_RX_ER_EN (Bit 9)                                 */
35895  #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Msk    (0x200UL)   /*!< RMII_RX_ER_EN (Bitfield-Mask: 0x01)                   */
35896  #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Pos    (10UL)      /*!< RMII_CRS_MODE (Bit 10)                                */
35897  #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Msk    (0x400UL)   /*!< RMII_CRS_MODE (Bitfield-Mask: 0x01)                   */
35898  #define R_ETHSS_CONVCTRL_RGMII_LINK_Pos       (12UL)      /*!< RGMII_LINK (Bit 12)                                   */
35899  #define R_ETHSS_CONVCTRL_RGMII_LINK_Msk       (0x1000UL)  /*!< RGMII_LINK (Bitfield-Mask: 0x01)                      */
35900  #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Pos     (13UL)      /*!< RGMII_DUPLEX (Bit 13)                                 */
35901  #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Msk     (0x2000UL)  /*!< RGMII_DUPLEX (Bitfield-Mask: 0x01)                    */
35902  #define R_ETHSS_CONVCTRL_RGMII_SPEED_Pos      (14UL)      /*!< RGMII_SPEED (Bit 14)                                  */
35903  #define R_ETHSS_CONVCTRL_RGMII_SPEED_Msk      (0xc000UL)  /*!< RGMII_SPEED (Bitfield-Mask: 0x03)                     */
35904 /* ========================================================  CONVRST  ======================================================== */
35905  #define R_ETHSS_CONVRST_PHYIR_Pos             (0UL)       /*!< PHYIR (Bit 0)                                         */
35906  #define R_ETHSS_CONVRST_PHYIR_Msk             (0x7UL)     /*!< PHYIR (Bitfield-Mask: 0x07)                           */
35907 /* ========================================================  SWCTRL  ========================================================= */
35908  #define R_ETHSS_SWCTRL_SET10_Pos              (0UL)       /*!< SET10 (Bit 0)                                         */
35909  #define R_ETHSS_SWCTRL_SET10_Msk              (0x7UL)     /*!< SET10 (Bitfield-Mask: 0x07)                           */
35910  #define R_ETHSS_SWCTRL_SET1000_Pos            (4UL)       /*!< SET1000 (Bit 4)                                       */
35911  #define R_ETHSS_SWCTRL_SET1000_Msk            (0x70UL)    /*!< SET1000 (Bitfield-Mask: 0x07)                         */
35912  #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Pos       (16UL)      /*!< STRAP_SX_ENB (Bit 16)                                 */
35913  #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Msk       (0x10000UL) /*!< STRAP_SX_ENB (Bitfield-Mask: 0x01)                    */
35914  #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Pos      (17UL)      /*!< STRAP_HUB_ENB (Bit 17)                                */
35915  #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Msk      (0x20000UL) /*!< STRAP_HUB_ENB (Bitfield-Mask: 0x01)                   */
35916 /* ========================================================  SWDUPC  ========================================================= */
35917  #define R_ETHSS_SWDUPC_PHY_DUPLEX_Pos         (0UL)       /*!< PHY_DUPLEX (Bit 0)                                    */
35918  #define R_ETHSS_SWDUPC_PHY_DUPLEX_Msk         (0x7UL)     /*!< PHY_DUPLEX (Bitfield-Mask: 0x07)                      */
35919 /* =========================================================  CDCR  ========================================================== */
35920  #define R_ETHSS_CDCR_RXDLYEN_Pos              (0UL)       /*!< RXDLYEN (Bit 0)                                       */
35921  #define R_ETHSS_CDCR_RXDLYEN_Msk              (0x1UL)     /*!< RXDLYEN (Bitfield-Mask: 0x01)                         */
35922  #define R_ETHSS_CDCR_TXDLYEN_Pos              (1UL)       /*!< TXDLYEN (Bit 1)                                       */
35923  #define R_ETHSS_CDCR_TXDLYEN_Msk              (0x2UL)     /*!< TXDLYEN (Bitfield-Mask: 0x01)                         */
35924  #define R_ETHSS_CDCR_OSCCLKEN_Pos             (2UL)       /*!< OSCCLKEN (Bit 2)                                      */
35925  #define R_ETHSS_CDCR_OSCCLKEN_Msk             (0x4UL)     /*!< OSCCLKEN (Bitfield-Mask: 0x01)                        */
35926  #define R_ETHSS_CDCR_CLKINEN_Pos              (3UL)       /*!< CLKINEN (Bit 3)                                       */
35927  #define R_ETHSS_CDCR_CLKINEN_Msk              (0x8UL)     /*!< CLKINEN (Bitfield-Mask: 0x01)                         */
35928 /* ========================================================  RXFCNT  ========================================================= */
35929  #define R_ETHSS_RXFCNT_RXFCNT_Pos             (0UL)       /*!< RXFCNT (Bit 0)                                        */
35930  #define R_ETHSS_RXFCNT_RXFCNT_Msk             (0xffffUL)  /*!< RXFCNT (Bitfield-Mask: 0xffff)                        */
35931 /* ========================================================  TXFCNT  ========================================================= */
35932  #define R_ETHSS_TXFCNT_TXFCNT_Pos             (0UL)       /*!< TXFCNT (Bit 0)                                        */
35933  #define R_ETHSS_TXFCNT_TXFCNT_Msk             (0xffffUL)  /*!< TXFCNT (Bitfield-Mask: 0xffff)                        */
35934 /* =======================================================  RXTAPSEL  ======================================================== */
35935  #define R_ETHSS_RXTAPSEL_RXTAPSEL_Pos         (0UL)       /*!< RXTAPSEL (Bit 0)                                      */
35936  #define R_ETHSS_RXTAPSEL_RXTAPSEL_Msk         (0x7fUL)    /*!< RXTAPSEL (Bitfield-Mask: 0x7f)                        */
35937 /* =======================================================  TXTAPSEL  ======================================================== */
35938  #define R_ETHSS_TXTAPSEL_TXTAPSEL_Pos         (0UL)       /*!< TXTAPSEL (Bit 0)                                      */
35939  #define R_ETHSS_TXTAPSEL_TXTAPSEL_Msk         (0x7fUL)    /*!< TXTAPSEL (Bitfield-Mask: 0x7f)                        */
35940 /* ========================================================  MIIMCR  ========================================================= */
35941  #define R_ETHSS_MIIMCR_MIIM2MEN_Pos           (0UL)       /*!< MIIM2MEN (Bit 0)                                      */
35942  #define R_ETHSS_MIIMCR_MIIM2MEN_Msk           (0x1UL)     /*!< MIIM2MEN (Bitfield-Mask: 0x01)                        */
35943 
35944 /* =========================================================================================================================== */
35945 /* ================                                         R_ESC_INI                                         ================ */
35946 /* =========================================================================================================================== */
35947 
35948 /* ======================================================  ECATOFFADR  ======================================================= */
35949  #define R_ESC_INI_ECATOFFADR_OADD_Pos         (0UL)    /*!< OADD (Bit 0)                                          */
35950  #define R_ESC_INI_ECATOFFADR_OADD_Msk         (0x1fUL) /*!< OADD (Bitfield-Mask: 0x1f)                            */
35951 /* =======================================================  ECATOPMOD  ======================================================= */
35952  #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Pos    (0UL)    /*!< EEPROMSIZE (Bit 0)                                    */
35953  #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Msk    (0x1UL)  /*!< EEPROMSIZE (Bitfield-Mask: 0x01)                      */
35954 /* =======================================================  ECATDBGC  ======================================================== */
35955  #define R_ESC_INI_ECATDBGC_TXSFT0_Pos         (0UL)    /*!< TXSFT0 (Bit 0)                                        */
35956  #define R_ESC_INI_ECATDBGC_TXSFT0_Msk         (0x3UL)  /*!< TXSFT0 (Bitfield-Mask: 0x03)                          */
35957  #define R_ESC_INI_ECATDBGC_TXSFT1_Pos         (2UL)    /*!< TXSFT1 (Bit 2)                                        */
35958  #define R_ESC_INI_ECATDBGC_TXSFT1_Msk         (0xcUL)  /*!< TXSFT1 (Bitfield-Mask: 0x03)                          */
35959  #define R_ESC_INI_ECATDBGC_TXSFT2_Pos         (4UL)    /*!< TXSFT2 (Bit 4)                                        */
35960  #define R_ESC_INI_ECATDBGC_TXSFT2_Msk         (0x30UL) /*!< TXSFT2 (Bitfield-Mask: 0x03)                          */
35961 /* ======================================================  ECATTRGSEL  ======================================================= */
35962  #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Pos      (0UL)    /*!< TRGSEL0 (Bit 0)                                       */
35963  #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Msk      (0x1UL)  /*!< TRGSEL0 (Bitfield-Mask: 0x01)                         */
35964  #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Pos      (1UL)    /*!< TRGSEL1 (Bit 1)                                       */
35965  #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Msk      (0x2UL)  /*!< TRGSEL1 (Bitfield-Mask: 0x01)                         */
35966 
35967 /* =========================================================================================================================== */
35968 /* ================                                        R_ETHSW_PTP                                        ================ */
35969 /* =========================================================================================================================== */
35970 
35971 /* ======================================================  SWPTPOUTSEL  ====================================================== */
35972  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Pos     (0UL)    /*!< IOSEL0 (Bit 0)                                        */
35973  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Msk     (0x1UL)  /*!< IOSEL0 (Bitfield-Mask: 0x01)                          */
35974  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Pos     (1UL)    /*!< IOSEL1 (Bit 1)                                        */
35975  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Msk     (0x2UL)  /*!< IOSEL1 (Bitfield-Mask: 0x01)                          */
35976  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Pos     (2UL)    /*!< IOSEL2 (Bit 2)                                        */
35977  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Msk     (0x4UL)  /*!< IOSEL2 (Bitfield-Mask: 0x01)                          */
35978  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Pos     (3UL)    /*!< IOSEL3 (Bit 3)                                        */
35979  #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Msk     (0x8UL)  /*!< IOSEL3 (Bitfield-Mask: 0x01)                          */
35980  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Pos    (4UL)    /*!< EVTSEL0 (Bit 4)                                       */
35981  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Msk    (0x10UL) /*!< EVTSEL0 (Bitfield-Mask: 0x01)                         */
35982  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Pos    (5UL)    /*!< EVTSEL1 (Bit 5)                                       */
35983  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Msk    (0x20UL) /*!< EVTSEL1 (Bitfield-Mask: 0x01)                         */
35984  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Pos    (6UL)    /*!< EVTSEL2 (Bit 6)                                       */
35985  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Msk    (0x40UL) /*!< EVTSEL2 (Bitfield-Mask: 0x01)                         */
35986  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Pos    (7UL)    /*!< EVTSEL3 (Bit 7)                                       */
35987  #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Msk    (0x80UL) /*!< EVTSEL3 (Bitfield-Mask: 0x01)                         */
35988 
35989 /* =========================================================================================================================== */
35990 /* ================                                          R_ETHSW                                          ================ */
35991 /* =========================================================================================================================== */
35992 
35993 /* =======================================================  REVISION  ======================================================== */
35994  #define R_ETHSW_REVISION_REV_Pos                                         (0UL)          /*!< REV (Bit 0)                                           */
35995  #define R_ETHSW_REVISION_REV_Msk                                         (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
35996 /* ========================================================  SCRATCH  ======================================================== */
35997  #define R_ETHSW_SCRATCH_SCRATCH_Pos                                      (0UL)          /*!< SCRATCH (Bit 0)                                       */
35998  #define R_ETHSW_SCRATCH_SCRATCH_Msk                                      (0xffffffffUL) /*!< SCRATCH (Bitfield-Mask: 0xffffffff)                   */
35999 /* =======================================================  PORT_ENA  ======================================================== */
36000  #define R_ETHSW_PORT_ENA_TXENA_Pos                                       (0UL)          /*!< TXENA (Bit 0)                                         */
36001  #define R_ETHSW_PORT_ENA_TXENA_Msk                                       (0xfUL)        /*!< TXENA (Bitfield-Mask: 0x0f)                           */
36002  #define R_ETHSW_PORT_ENA_RXENA_Pos                                       (16UL)         /*!< RXENA (Bit 16)                                        */
36003  #define R_ETHSW_PORT_ENA_RXENA_Msk                                       (0xf0000UL)    /*!< RXENA (Bitfield-Mask: 0x0f)                           */
36004 /* ==================================================  UCAST_DEFAULT_MASK0  ================================================== */
36005  #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Pos                          (0UL)          /*!< UCASTDM (Bit 0)                                       */
36006  #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Msk                          (0xfUL)        /*!< UCASTDM (Bitfield-Mask: 0x0f)                         */
36007 /* ======================================================  VLAN_VERIFY  ====================================================== */
36008  #define R_ETHSW_VLAN_VERIFY_VLANVERI_Pos                                 (0UL)          /*!< VLANVERI (Bit 0)                                      */
36009  #define R_ETHSW_VLAN_VERIFY_VLANVERI_Msk                                 (0xfUL)        /*!< VLANVERI (Bitfield-Mask: 0x0f)                        */
36010  #define R_ETHSW_VLAN_VERIFY_VLANDISC_Pos                                 (16UL)         /*!< VLANDISC (Bit 16)                                     */
36011  #define R_ETHSW_VLAN_VERIFY_VLANDISC_Msk                                 (0xf0000UL)    /*!< VLANDISC (Bitfield-Mask: 0x0f)                        */
36012 /* ==================================================  BCAST_DEFAULT_MASK0  ================================================== */
36013  #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Pos                          (0UL)          /*!< BCASTDM (Bit 0)                                       */
36014  #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Msk                          (0xfUL)        /*!< BCASTDM (Bitfield-Mask: 0x0f)                         */
36015 /* ==================================================  MCAST_DEFAULT_MASK0  ================================================== */
36016  #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Pos                          (0UL)          /*!< MCASTDM (Bit 0)                                       */
36017  #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Msk                          (0xfUL)        /*!< MCASTDM (Bitfield-Mask: 0x0f)                         */
36018 /* ===================================================  INPUT_LEARN_BLOCK  =================================================== */
36019  #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Pos                            (0UL)          /*!< BLOCKEN (Bit 0)                                       */
36020  #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Msk                            (0xfUL)        /*!< BLOCKEN (Bitfield-Mask: 0x0f)                         */
36021  #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Pos                           (16UL)         /*!< LEARNDIS (Bit 16)                                     */
36022  #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Msk                           (0xf0000UL)    /*!< LEARNDIS (Bitfield-Mask: 0x0f)                        */
36023 /* ======================================================  MGMT_CONFIG  ====================================================== */
36024  #define R_ETHSW_MGMT_CONFIG_PORT_Pos                                     (0UL)          /*!< PORT (Bit 0)                                          */
36025  #define R_ETHSW_MGMT_CONFIG_PORT_Msk                                     (0xfUL)        /*!< PORT (Bitfield-Mask: 0x0f)                            */
36026  #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Pos                                (5UL)          /*!< MSG_TRANS (Bit 5)                                     */
36027  #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Msk                                (0x20UL)       /*!< MSG_TRANS (Bitfield-Mask: 0x01)                       */
36028  #define R_ETHSW_MGMT_CONFIG_ENABLE_Pos                                   (6UL)          /*!< ENABLE (Bit 6)                                        */
36029  #define R_ETHSW_MGMT_CONFIG_ENABLE_Msk                                   (0x40UL)       /*!< ENABLE (Bitfield-Mask: 0x01)                          */
36030  #define R_ETHSW_MGMT_CONFIG_DISCARD_Pos                                  (7UL)          /*!< DISCARD (Bit 7)                                       */
36031  #define R_ETHSW_MGMT_CONFIG_DISCARD_Msk                                  (0x80UL)       /*!< DISCARD (Bitfield-Mask: 0x01)                         */
36032  #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Pos                                  (8UL)          /*!< MGMT_EN (Bit 8)                                       */
36033  #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Msk                                  (0x100UL)      /*!< MGMT_EN (Bitfield-Mask: 0x01)                         */
36034  #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Pos                                (9UL)          /*!< MGMT_DISC (Bit 9)                                     */
36035  #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Msk                                (0x200UL)      /*!< MGMT_DISC (Bitfield-Mask: 0x01)                       */
36036  #define R_ETHSW_MGMT_CONFIG_PRIORITY_Pos                                 (13UL)         /*!< PRIORITY (Bit 13)                                     */
36037  #define R_ETHSW_MGMT_CONFIG_PRIORITY_Msk                                 (0xe000UL)     /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
36038  #define R_ETHSW_MGMT_CONFIG_PORTMASK_Pos                                 (16UL)         /*!< PORTMASK (Bit 16)                                     */
36039  #define R_ETHSW_MGMT_CONFIG_PORTMASK_Msk                                 (0xf0000UL)    /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
36040 /* ======================================================  MODE_CONFIG  ====================================================== */
36041  #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Pos                              (8UL)          /*!< CUT_THRU_EN (Bit 8)                                   */
36042  #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Msk                              (0xf00UL)      /*!< CUT_THRU_EN (Bitfield-Mask: 0x0f)                     */
36043  #define R_ETHSW_MODE_CONFIG_STATSRESET_Pos                               (31UL)         /*!< STATSRESET (Bit 31)                                   */
36044  #define R_ETHSW_MODE_CONFIG_STATSRESET_Msk                               (0x80000000UL) /*!< STATSRESET (Bitfield-Mask: 0x01)                      */
36045 /* =====================================================  VLAN_IN_MODE  ====================================================== */
36046  #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Pos                              (0UL)          /*!< P0VLANINMD (Bit 0)                                    */
36047  #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Msk                              (0x3UL)        /*!< P0VLANINMD (Bitfield-Mask: 0x03)                      */
36048  #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Pos                              (2UL)          /*!< P1VLANINMD (Bit 2)                                    */
36049  #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Msk                              (0xcUL)        /*!< P1VLANINMD (Bitfield-Mask: 0x03)                      */
36050  #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Pos                              (4UL)          /*!< P2VLANINMD (Bit 4)                                    */
36051  #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Msk                              (0x30UL)       /*!< P2VLANINMD (Bitfield-Mask: 0x03)                      */
36052  #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Pos                              (6UL)          /*!< P3VLANINMD (Bit 6)                                    */
36053  #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Msk                              (0xc0UL)       /*!< P3VLANINMD (Bitfield-Mask: 0x03)                      */
36054 /* =====================================================  VLAN_OUT_MODE  ===================================================== */
36055  #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Pos                            (0UL)          /*!< P0VLANOUTMD (Bit 0)                                   */
36056  #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Msk                            (0x3UL)        /*!< P0VLANOUTMD (Bitfield-Mask: 0x03)                     */
36057  #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Pos                            (2UL)          /*!< P1VLANOUTMD (Bit 2)                                   */
36058  #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Msk                            (0xcUL)        /*!< P1VLANOUTMD (Bitfield-Mask: 0x03)                     */
36059  #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Pos                            (4UL)          /*!< P2VLANOUTMD (Bit 4)                                   */
36060  #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Msk                            (0x30UL)       /*!< P2VLANOUTMD (Bitfield-Mask: 0x03)                     */
36061  #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Pos                            (6UL)          /*!< P3VLANOUTMD (Bit 6)                                   */
36062  #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Msk                            (0xc0UL)       /*!< P3VLANOUTMD (Bitfield-Mask: 0x03)                     */
36063 /* ===================================================  VLAN_IN_MODE_ENA  ==================================================== */
36064  #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Pos                          (0UL)          /*!< VLANINMDEN (Bit 0)                                    */
36065  #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Msk                          (0xfUL)        /*!< VLANINMDEN (Bitfield-Mask: 0x0f)                      */
36066 /* ======================================================  VLAN_TAG_ID  ====================================================== */
36067  #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Pos                                (0UL)          /*!< VLANTAGID (Bit 0)                                     */
36068  #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Msk                                (0xffffUL)     /*!< VLANTAGID (Bitfield-Mask: 0xffff)                     */
36069 /* ===================================================  BCAST_STORM_LIMIT  =================================================== */
36070  #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Pos                              (0UL)          /*!< TMOUT (Bit 0)                                         */
36071  #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Msk                              (0xffffUL)     /*!< TMOUT (Bitfield-Mask: 0xffff)                         */
36072  #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Pos                         (16UL)         /*!< BCASTLIMIT (Bit 16)                                   */
36073  #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Msk                         (0xffff0000UL) /*!< BCASTLIMIT (Bitfield-Mask: 0xffff)                    */
36074 /* ===================================================  MCAST_STORM_LIMIT  =================================================== */
36075  #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Pos                         (16UL)         /*!< MCASTLIMIT (Bit 16)                                   */
36076  #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Msk                         (0xffff0000UL) /*!< MCASTLIMIT (Bitfield-Mask: 0xffff)                    */
36077 /* ====================================================  MIRROR_CONTROL  ===================================================== */
36078  #define R_ETHSW_MIRROR_CONTROL_PORT_Pos                                  (0UL)          /*!< PORT (Bit 0)                                          */
36079  #define R_ETHSW_MIRROR_CONTROL_PORT_Msk                                  (0x3UL)        /*!< PORT (Bitfield-Mask: 0x03)                            */
36080  #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Pos                             (4UL)          /*!< MIRROR_EN (Bit 4)                                     */
36081  #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Msk                             (0x10UL)       /*!< MIRROR_EN (Bitfield-Mask: 0x01)                       */
36082  #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Pos                            (5UL)          /*!< ING_MAP_EN (Bit 5)                                    */
36083  #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Msk                            (0x20UL)       /*!< ING_MAP_EN (Bitfield-Mask: 0x01)                      */
36084  #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Pos                             (6UL)          /*!< EG_MAP_EN (Bit 6)                                     */
36085  #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Msk                             (0x40UL)       /*!< EG_MAP_EN (Bitfield-Mask: 0x01)                       */
36086  #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Pos                          (7UL)          /*!< ING_SA_MATCH (Bit 7)                                  */
36087  #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Msk                          (0x80UL)       /*!< ING_SA_MATCH (Bitfield-Mask: 0x01)                    */
36088  #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Pos                          (8UL)          /*!< ING_DA_MATCH (Bit 8)                                  */
36089  #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Msk                          (0x100UL)      /*!< ING_DA_MATCH (Bitfield-Mask: 0x01)                    */
36090  #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Pos                           (9UL)          /*!< EG_SA_MATCH (Bit 9)                                   */
36091  #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Msk                           (0x200UL)      /*!< EG_SA_MATCH (Bitfield-Mask: 0x01)                     */
36092  #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Pos                           (10UL)         /*!< EG_DA_MATCH (Bit 10)                                  */
36093  #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Msk                           (0x400UL)      /*!< EG_DA_MATCH (Bitfield-Mask: 0x01)                     */
36094 /* =====================================================  MIRROR_EG_MAP  ===================================================== */
36095  #define R_ETHSW_MIRROR_EG_MAP_EMAP_Pos                                   (0UL)          /*!< EMAP (Bit 0)                                          */
36096  #define R_ETHSW_MIRROR_EG_MAP_EMAP_Msk                                   (0xfUL)        /*!< EMAP (Bitfield-Mask: 0x0f)                            */
36097 /* ====================================================  MIRROR_ING_MAP  ===================================================== */
36098  #define R_ETHSW_MIRROR_ING_MAP_IMAP_Pos                                  (0UL)          /*!< IMAP (Bit 0)                                          */
36099  #define R_ETHSW_MIRROR_ING_MAP_IMAP_Msk                                  (0xfUL)        /*!< IMAP (Bitfield-Mask: 0x0f)                            */
36100 /* =====================================================  MIRROR_ISRC_0  ===================================================== */
36101  #define R_ETHSW_MIRROR_ISRC_0_ISRC_Pos                                   (0UL)          /*!< ISRC (Bit 0)                                          */
36102  #define R_ETHSW_MIRROR_ISRC_0_ISRC_Msk                                   (0xffffffffUL) /*!< ISRC (Bitfield-Mask: 0xffffffff)                      */
36103 /* =====================================================  MIRROR_ISRC_1  ===================================================== */
36104  #define R_ETHSW_MIRROR_ISRC_1_ISRC_Pos                                   (0UL)          /*!< ISRC (Bit 0)                                          */
36105  #define R_ETHSW_MIRROR_ISRC_1_ISRC_Msk                                   (0xffffUL)     /*!< ISRC (Bitfield-Mask: 0xffff)                          */
36106 /* =====================================================  MIRROR_IDST_0  ===================================================== */
36107  #define R_ETHSW_MIRROR_IDST_0_IDST_Pos                                   (0UL)          /*!< IDST (Bit 0)                                          */
36108  #define R_ETHSW_MIRROR_IDST_0_IDST_Msk                                   (0xffffffffUL) /*!< IDST (Bitfield-Mask: 0xffffffff)                      */
36109 /* =====================================================  MIRROR_IDST_1  ===================================================== */
36110  #define R_ETHSW_MIRROR_IDST_1_IDST_Pos                                   (0UL)          /*!< IDST (Bit 0)                                          */
36111  #define R_ETHSW_MIRROR_IDST_1_IDST_Msk                                   (0xffffUL)     /*!< IDST (Bitfield-Mask: 0xffff)                          */
36112 /* =====================================================  MIRROR_ESRC_0  ===================================================== */
36113  #define R_ETHSW_MIRROR_ESRC_0_ESRC_Pos                                   (0UL)          /*!< ESRC (Bit 0)                                          */
36114  #define R_ETHSW_MIRROR_ESRC_0_ESRC_Msk                                   (0xffffffffUL) /*!< ESRC (Bitfield-Mask: 0xffffffff)                      */
36115 /* =====================================================  MIRROR_ESRC_1  ===================================================== */
36116  #define R_ETHSW_MIRROR_ESRC_1_ESRC_Pos                                   (0UL)          /*!< ESRC (Bit 0)                                          */
36117  #define R_ETHSW_MIRROR_ESRC_1_ESRC_Msk                                   (0xffffUL)     /*!< ESRC (Bitfield-Mask: 0xffff)                          */
36118 /* =====================================================  MIRROR_EDST_0  ===================================================== */
36119  #define R_ETHSW_MIRROR_EDST_0_EDST_Pos                                   (0UL)          /*!< EDST (Bit 0)                                          */
36120  #define R_ETHSW_MIRROR_EDST_0_EDST_Msk                                   (0xffffffffUL) /*!< EDST (Bitfield-Mask: 0xffffffff)                      */
36121 /* =====================================================  MIRROR_EDST_1  ===================================================== */
36122  #define R_ETHSW_MIRROR_EDST_1_EDST_Pos                                   (0UL)          /*!< EDST (Bit 0)                                          */
36123  #define R_ETHSW_MIRROR_EDST_1_EDST_Msk                                   (0xffffUL)     /*!< EDST (Bitfield-Mask: 0xffff)                          */
36124 /* ======================================================  MIRROR_CNT  ======================================================= */
36125  #define R_ETHSW_MIRROR_CNT_CNT_Pos                                       (0UL)          /*!< CNT (Bit 0)                                           */
36126  #define R_ETHSW_MIRROR_CNT_CNT_Msk                                       (0xffUL)       /*!< CNT (Bitfield-Mask: 0xff)                             */
36127 /* ==================================================  UCAST_DEFAULT_MASK1  ================================================== */
36128  #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Pos                         (0UL)          /*!< UCASTDM1 (Bit 0)                                      */
36129  #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Msk                         (0xfUL)        /*!< UCASTDM1 (Bitfield-Mask: 0x0f)                        */
36130 /* ==================================================  BCAST_DEFAULT_MASK1  ================================================== */
36131  #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Pos                         (0UL)          /*!< BCASTDM1 (Bit 0)                                      */
36132  #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Msk                         (0xfUL)        /*!< BCASTDM1 (Bitfield-Mask: 0x0f)                        */
36133 /* ==================================================  MCAST_DEFAULT_MASK1  ================================================== */
36134  #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Pos                         (0UL)          /*!< MCASTDM1 (Bit 0)                                      */
36135  #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Msk                         (0xfUL)        /*!< MCASTDM1 (Bitfield-Mask: 0x0f)                        */
36136 /* ==================================================  PORT_XCAST_MASK_SEL  ================================================== */
36137  #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Pos                             (0UL)          /*!< MSEL (Bit 0)                                          */
36138  #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Msk                             (0xfUL)        /*!< MSEL (Bitfield-Mask: 0x0f)                            */
36139 /* ===================================================  QMGR_ST_MINCELLS  ==================================================== */
36140  #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Pos                          (0UL)          /*!< STMINCELLS (Bit 0)                                    */
36141  #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Msk                          (0x7ffUL)      /*!< STMINCELLS (Bitfield-Mask: 0x7ff)                     */
36142 /* =====================================================  QMGR_RED_MIN4  ===================================================== */
36143  #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Pos                          (0UL)          /*!< CFGRED_MINTH4 (Bit 0)                                 */
36144  #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Msk                          (0xffffffffUL) /*!< CFGRED_MINTH4 (Bitfield-Mask: 0xffffffff)             */
36145 /* =====================================================  QMGR_RED_MAX4  ===================================================== */
36146  #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Pos                          (0UL)          /*!< CFGRED_MAXTH4 (Bit 0)                                 */
36147  #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Msk                          (0xffffffffUL) /*!< CFGRED_MAXTH4 (Bitfield-Mask: 0xffffffff)             */
36148 /* ====================================================  QMGR_RED_CONFIG  ==================================================== */
36149  #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Pos                         (0UL)          /*!< QUEUE_RED_EN (Bit 0)                                  */
36150  #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Msk                         (0xfUL)        /*!< QUEUE_RED_EN (Bitfield-Mask: 0x0f)                    */
36151  #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Pos                         (8UL)          /*!< GACTIVITY_EN (Bit 8)                                  */
36152  #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Msk                         (0x100UL)      /*!< GACTIVITY_EN (Bitfield-Mask: 0x01)                    */
36153 /* ======================================================  IMC_STATUS  ======================================================= */
36154  #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Pos                           (0UL)          /*!< CELLS_AVAILABLE (Bit 0)                               */
36155  #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Msk                           (0xffffffUL)   /*!< CELLS_AVAILABLE (Bitfield-Mask: 0xffffff)             */
36156  #define R_ETHSW_IMC_STATUS_CF_ERR_Pos                                    (24UL)         /*!< CF_ERR (Bit 24)                                       */
36157  #define R_ETHSW_IMC_STATUS_CF_ERR_Msk                                    (0x1000000UL)  /*!< CF_ERR (Bitfield-Mask: 0x01)                          */
36158  #define R_ETHSW_IMC_STATUS_DE_ERR_Pos                                    (25UL)         /*!< DE_ERR (Bit 25)                                       */
36159  #define R_ETHSW_IMC_STATUS_DE_ERR_Msk                                    (0x2000000UL)  /*!< DE_ERR (Bitfield-Mask: 0x01)                          */
36160  #define R_ETHSW_IMC_STATUS_DE_INIT_Pos                                   (26UL)         /*!< DE_INIT (Bit 26)                                      */
36161  #define R_ETHSW_IMC_STATUS_DE_INIT_Msk                                   (0x4000000UL)  /*!< DE_INIT (Bitfield-Mask: 0x01)                         */
36162  #define R_ETHSW_IMC_STATUS_MEM_FULL_Pos                                  (27UL)         /*!< MEM_FULL (Bit 27)                                     */
36163  #define R_ETHSW_IMC_STATUS_MEM_FULL_Msk                                  (0x8000000UL)  /*!< MEM_FULL (Bitfield-Mask: 0x01)                        */
36164 /* =====================================================  IMC_ERR_FULL  ====================================================== */
36165  #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Pos                            (0UL)          /*!< IPC_ERR_FULL (Bit 0)                                  */
36166  #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Msk                            (0xfUL)        /*!< IPC_ERR_FULL (Bitfield-Mask: 0x0f)                    */
36167  #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Pos                           (16UL)         /*!< IPC_ERR_TRUNC (Bit 16)                                */
36168  #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Msk                           (0xf0000UL)    /*!< IPC_ERR_TRUNC (Bitfield-Mask: 0x0f)                   */
36169 /* =====================================================  IMC_ERR_IFACE  ===================================================== */
36170  #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Pos                          (0UL)          /*!< IPC_ERR_IFACE (Bit 0)                                 */
36171  #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Msk                          (0xfUL)        /*!< IPC_ERR_IFACE (Bitfield-Mask: 0x0f)                   */
36172  #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Pos                               (16UL)         /*!< WBUF_OVF (Bit 16)                                     */
36173  #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Msk                               (0xf0000UL)    /*!< WBUF_OVF (Bitfield-Mask: 0x0f)                        */
36174 /* ====================================================  IMC_ERR_QOFLOW  ===================================================== */
36175  #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Pos                                (0UL)          /*!< OP_ERR (Bit 0)                                        */
36176  #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Msk                                (0xfUL)        /*!< OP_ERR (Bitfield-Mask: 0x0f)                          */
36177 /* ======================================================  IMC_CONFIG  ======================================================= */
36178  #define R_ETHSW_IMC_CONFIG_WFQ_EN_Pos                                    (0UL)          /*!< WFQ_EN (Bit 0)                                        */
36179  #define R_ETHSW_IMC_CONFIG_WFQ_EN_Msk                                    (0x1UL)        /*!< WFQ_EN (Bitfield-Mask: 0x01)                          */
36180  #define R_ETHSW_IMC_CONFIG_RSV_ENA_Pos                                   (1UL)          /*!< RSV_ENA (Bit 1)                                       */
36181  #define R_ETHSW_IMC_CONFIG_RSV_ENA_Msk                                   (0x2UL)        /*!< RSV_ENA (Bitfield-Mask: 0x01)                         */
36182  #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Pos                           (2UL)          /*!< SPEED_HIPRI_THR (Bit 2)                               */
36183  #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Msk                           (0x1cUL)       /*!< SPEED_HIPRI_THR (Bitfield-Mask: 0x07)                 */
36184  #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Pos                             (5UL)          /*!< CTFL_EMPTY_MD (Bit 5)                                 */
36185  #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Msk                             (0x20UL)       /*!< CTFL_EMPTY_MD (Bitfield-Mask: 0x01)                   */
36186 /* =====================================================  IMC_ERR_ALLOC  ===================================================== */
36187  #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Pos                              (0UL)          /*!< DISC_FULL (Bit 0)                                     */
36188  #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Msk                              (0xfUL)        /*!< DISC_FULL (Bitfield-Mask: 0x0f)                       */
36189  #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Pos                              (16UL)         /*!< DISC_LATE (Bit 16)                                    */
36190  #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Msk                              (0xf0000UL)    /*!< DISC_LATE (Bitfield-Mask: 0x0f)                       */
36191 /* =======================================================  GPARSER0  ======================================================== */
36192  #define R_ETHSW_GPARSER0_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36193  #define R_ETHSW_GPARSER0_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36194  #define R_ETHSW_GPARSER0_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36195  #define R_ETHSW_GPARSER0_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36196  #define R_ETHSW_GPARSER0_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36197  #define R_ETHSW_GPARSER0_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36198  #define R_ETHSW_GPARSER0_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36199  #define R_ETHSW_GPARSER0_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36200  #define R_ETHSW_GPARSER0_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36201  #define R_ETHSW_GPARSER0_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36202  #define R_ETHSW_GPARSER0_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36203  #define R_ETHSW_GPARSER0_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36204  #define R_ETHSW_GPARSER0_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36205  #define R_ETHSW_GPARSER0_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36206  #define R_ETHSW_GPARSER0_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36207  #define R_ETHSW_GPARSER0_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36208  #define R_ETHSW_GPARSER0_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36209  #define R_ETHSW_GPARSER0_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36210  #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36211  #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36212  #define R_ETHSW_GPARSER0_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36213  #define R_ETHSW_GPARSER0_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36214 /* =======================================================  GPARSER1  ======================================================== */
36215  #define R_ETHSW_GPARSER1_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36216  #define R_ETHSW_GPARSER1_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36217  #define R_ETHSW_GPARSER1_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36218  #define R_ETHSW_GPARSER1_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36219  #define R_ETHSW_GPARSER1_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36220  #define R_ETHSW_GPARSER1_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36221  #define R_ETHSW_GPARSER1_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36222  #define R_ETHSW_GPARSER1_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36223  #define R_ETHSW_GPARSER1_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36224  #define R_ETHSW_GPARSER1_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36225  #define R_ETHSW_GPARSER1_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36226  #define R_ETHSW_GPARSER1_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36227  #define R_ETHSW_GPARSER1_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36228  #define R_ETHSW_GPARSER1_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36229  #define R_ETHSW_GPARSER1_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36230  #define R_ETHSW_GPARSER1_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36231  #define R_ETHSW_GPARSER1_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36232  #define R_ETHSW_GPARSER1_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36233  #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36234  #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36235  #define R_ETHSW_GPARSER1_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36236  #define R_ETHSW_GPARSER1_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36237 /* =======================================================  GPARSER2  ======================================================== */
36238  #define R_ETHSW_GPARSER2_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36239  #define R_ETHSW_GPARSER2_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36240  #define R_ETHSW_GPARSER2_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36241  #define R_ETHSW_GPARSER2_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36242  #define R_ETHSW_GPARSER2_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36243  #define R_ETHSW_GPARSER2_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36244  #define R_ETHSW_GPARSER2_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36245  #define R_ETHSW_GPARSER2_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36246  #define R_ETHSW_GPARSER2_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36247  #define R_ETHSW_GPARSER2_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36248  #define R_ETHSW_GPARSER2_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36249  #define R_ETHSW_GPARSER2_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36250  #define R_ETHSW_GPARSER2_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36251  #define R_ETHSW_GPARSER2_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36252  #define R_ETHSW_GPARSER2_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36253  #define R_ETHSW_GPARSER2_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36254  #define R_ETHSW_GPARSER2_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36255  #define R_ETHSW_GPARSER2_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36256  #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36257  #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36258  #define R_ETHSW_GPARSER2_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36259  #define R_ETHSW_GPARSER2_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36260 /* =======================================================  GPARSER3  ======================================================== */
36261  #define R_ETHSW_GPARSER3_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36262  #define R_ETHSW_GPARSER3_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36263  #define R_ETHSW_GPARSER3_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36264  #define R_ETHSW_GPARSER3_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36265  #define R_ETHSW_GPARSER3_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36266  #define R_ETHSW_GPARSER3_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36267  #define R_ETHSW_GPARSER3_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36268  #define R_ETHSW_GPARSER3_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36269  #define R_ETHSW_GPARSER3_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36270  #define R_ETHSW_GPARSER3_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36271  #define R_ETHSW_GPARSER3_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36272  #define R_ETHSW_GPARSER3_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36273  #define R_ETHSW_GPARSER3_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36274  #define R_ETHSW_GPARSER3_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36275  #define R_ETHSW_GPARSER3_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36276  #define R_ETHSW_GPARSER3_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36277  #define R_ETHSW_GPARSER3_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36278  #define R_ETHSW_GPARSER3_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36279  #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36280  #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36281  #define R_ETHSW_GPARSER3_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36282  #define R_ETHSW_GPARSER3_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36283 /* ========================================================  GARITH0  ======================================================== */
36284  #define R_ETHSW_GARITH0_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36285  #define R_ETHSW_GARITH0_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36286  #define R_ETHSW_GARITH0_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36287  #define R_ETHSW_GARITH0_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36288  #define R_ETHSW_GARITH0_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36289  #define R_ETHSW_GARITH0_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36290  #define R_ETHSW_GARITH0_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36291  #define R_ETHSW_GARITH0_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36292  #define R_ETHSW_GARITH0_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36293  #define R_ETHSW_GARITH0_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36294  #define R_ETHSW_GARITH0_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36295  #define R_ETHSW_GARITH0_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36296  #define R_ETHSW_GARITH0_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36297  #define R_ETHSW_GARITH0_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36298  #define R_ETHSW_GARITH0_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36299  #define R_ETHSW_GARITH0_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36300 /* ========================================================  GARITH1  ======================================================== */
36301  #define R_ETHSW_GARITH1_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36302  #define R_ETHSW_GARITH1_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36303  #define R_ETHSW_GARITH1_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36304  #define R_ETHSW_GARITH1_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36305  #define R_ETHSW_GARITH1_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36306  #define R_ETHSW_GARITH1_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36307  #define R_ETHSW_GARITH1_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36308  #define R_ETHSW_GARITH1_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36309  #define R_ETHSW_GARITH1_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36310  #define R_ETHSW_GARITH1_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36311  #define R_ETHSW_GARITH1_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36312  #define R_ETHSW_GARITH1_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36313  #define R_ETHSW_GARITH1_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36314  #define R_ETHSW_GARITH1_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36315  #define R_ETHSW_GARITH1_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36316  #define R_ETHSW_GARITH1_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36317 /* ========================================================  GARITH2  ======================================================== */
36318  #define R_ETHSW_GARITH2_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36319  #define R_ETHSW_GARITH2_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36320  #define R_ETHSW_GARITH2_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36321  #define R_ETHSW_GARITH2_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36322  #define R_ETHSW_GARITH2_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36323  #define R_ETHSW_GARITH2_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36324  #define R_ETHSW_GARITH2_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36325  #define R_ETHSW_GARITH2_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36326  #define R_ETHSW_GARITH2_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36327  #define R_ETHSW_GARITH2_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36328  #define R_ETHSW_GARITH2_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36329  #define R_ETHSW_GARITH2_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36330  #define R_ETHSW_GARITH2_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36331  #define R_ETHSW_GARITH2_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36332  #define R_ETHSW_GARITH2_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36333  #define R_ETHSW_GARITH2_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36334 /* ========================================================  GARITH3  ======================================================== */
36335  #define R_ETHSW_GARITH3_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36336  #define R_ETHSW_GARITH3_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36337  #define R_ETHSW_GARITH3_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36338  #define R_ETHSW_GARITH3_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36339  #define R_ETHSW_GARITH3_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36340  #define R_ETHSW_GARITH3_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36341  #define R_ETHSW_GARITH3_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36342  #define R_ETHSW_GARITH3_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36343  #define R_ETHSW_GARITH3_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36344  #define R_ETHSW_GARITH3_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36345  #define R_ETHSW_GARITH3_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36346  #define R_ETHSW_GARITH3_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36347  #define R_ETHSW_GARITH3_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36348  #define R_ETHSW_GARITH3_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36349  #define R_ETHSW_GARITH3_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36350  #define R_ETHSW_GARITH3_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36351 /* =======================================================  GPARSER4  ======================================================== */
36352  #define R_ETHSW_GPARSER4_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36353  #define R_ETHSW_GPARSER4_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36354  #define R_ETHSW_GPARSER4_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36355  #define R_ETHSW_GPARSER4_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36356  #define R_ETHSW_GPARSER4_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36357  #define R_ETHSW_GPARSER4_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36358  #define R_ETHSW_GPARSER4_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36359  #define R_ETHSW_GPARSER4_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36360  #define R_ETHSW_GPARSER4_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36361  #define R_ETHSW_GPARSER4_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36362  #define R_ETHSW_GPARSER4_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36363  #define R_ETHSW_GPARSER4_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36364  #define R_ETHSW_GPARSER4_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36365  #define R_ETHSW_GPARSER4_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36366  #define R_ETHSW_GPARSER4_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36367  #define R_ETHSW_GPARSER4_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36368  #define R_ETHSW_GPARSER4_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36369  #define R_ETHSW_GPARSER4_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36370  #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36371  #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36372  #define R_ETHSW_GPARSER4_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36373  #define R_ETHSW_GPARSER4_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36374 /* =======================================================  GPARSER5  ======================================================== */
36375  #define R_ETHSW_GPARSER5_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36376  #define R_ETHSW_GPARSER5_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36377  #define R_ETHSW_GPARSER5_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36378  #define R_ETHSW_GPARSER5_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36379  #define R_ETHSW_GPARSER5_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36380  #define R_ETHSW_GPARSER5_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36381  #define R_ETHSW_GPARSER5_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36382  #define R_ETHSW_GPARSER5_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36383  #define R_ETHSW_GPARSER5_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36384  #define R_ETHSW_GPARSER5_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36385  #define R_ETHSW_GPARSER5_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36386  #define R_ETHSW_GPARSER5_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36387  #define R_ETHSW_GPARSER5_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36388  #define R_ETHSW_GPARSER5_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36389  #define R_ETHSW_GPARSER5_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36390  #define R_ETHSW_GPARSER5_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36391  #define R_ETHSW_GPARSER5_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36392  #define R_ETHSW_GPARSER5_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36393  #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36394  #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36395  #define R_ETHSW_GPARSER5_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36396  #define R_ETHSW_GPARSER5_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36397 /* =======================================================  GPARSER6  ======================================================== */
36398  #define R_ETHSW_GPARSER6_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36399  #define R_ETHSW_GPARSER6_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36400  #define R_ETHSW_GPARSER6_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36401  #define R_ETHSW_GPARSER6_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36402  #define R_ETHSW_GPARSER6_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36403  #define R_ETHSW_GPARSER6_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36404  #define R_ETHSW_GPARSER6_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36405  #define R_ETHSW_GPARSER6_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36406  #define R_ETHSW_GPARSER6_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36407  #define R_ETHSW_GPARSER6_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36408  #define R_ETHSW_GPARSER6_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36409  #define R_ETHSW_GPARSER6_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36410  #define R_ETHSW_GPARSER6_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36411  #define R_ETHSW_GPARSER6_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36412  #define R_ETHSW_GPARSER6_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36413  #define R_ETHSW_GPARSER6_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36414  #define R_ETHSW_GPARSER6_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36415  #define R_ETHSW_GPARSER6_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36416  #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36417  #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36418  #define R_ETHSW_GPARSER6_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36419  #define R_ETHSW_GPARSER6_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36420 /* =======================================================  GPARSER7  ======================================================== */
36421  #define R_ETHSW_GPARSER7_MASK_VAL2_Pos                                   (0UL)          /*!< MASK_VAL2 (Bit 0)                                     */
36422  #define R_ETHSW_GPARSER7_MASK_VAL2_Msk                                   (0xffUL)       /*!< MASK_VAL2 (Bitfield-Mask: 0xff)                       */
36423  #define R_ETHSW_GPARSER7_COMPARE_VAL_Pos                                 (8UL)          /*!< COMPARE_VAL (Bit 8)                                   */
36424  #define R_ETHSW_GPARSER7_COMPARE_VAL_Msk                                 (0xff00UL)     /*!< COMPARE_VAL (Bitfield-Mask: 0xff)                     */
36425  #define R_ETHSW_GPARSER7_OFFSET_Pos                                      (16UL)         /*!< OFFSET (Bit 16)                                       */
36426  #define R_ETHSW_GPARSER7_OFFSET_Msk                                      (0x3f0000UL)   /*!< OFFSET (Bitfield-Mask: 0x3f)                          */
36427  #define R_ETHSW_GPARSER7_OFFSET_DA_Pos                                   (23UL)         /*!< OFFSET_DA (Bit 23)                                    */
36428  #define R_ETHSW_GPARSER7_OFFSET_DA_Msk                                   (0x800000UL)   /*!< OFFSET_DA (Bitfield-Mask: 0x01)                       */
36429  #define R_ETHSW_GPARSER7_VALID_Pos                                       (24UL)         /*!< VALID (Bit 24)                                        */
36430  #define R_ETHSW_GPARSER7_VALID_Msk                                       (0x1000000UL)  /*!< VALID (Bitfield-Mask: 0x01)                           */
36431  #define R_ETHSW_GPARSER7_SKIPVLAN_Pos                                    (25UL)         /*!< SKIPVLAN (Bit 25)                                     */
36432  #define R_ETHSW_GPARSER7_SKIPVLAN_Msk                                    (0x2000000UL)  /*!< SKIPVLAN (Bitfield-Mask: 0x01)                        */
36433  #define R_ETHSW_GPARSER7_IPDATA_Pos                                      (26UL)         /*!< IPDATA (Bit 26)                                       */
36434  #define R_ETHSW_GPARSER7_IPDATA_Msk                                      (0x4000000UL)  /*!< IPDATA (Bitfield-Mask: 0x01)                          */
36435  #define R_ETHSW_GPARSER7_IPPROTOCOL_Pos                                  (27UL)         /*!< IPPROTOCOL (Bit 27)                                   */
36436  #define R_ETHSW_GPARSER7_IPPROTOCOL_Msk                                  (0x8000000UL)  /*!< IPPROTOCOL (Bitfield-Mask: 0x01)                      */
36437  #define R_ETHSW_GPARSER7_CMP16_Pos                                       (28UL)         /*!< CMP16 (Bit 28)                                        */
36438  #define R_ETHSW_GPARSER7_CMP16_Msk                                       (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01)                           */
36439  #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Pos                                (29UL)         /*!< OFFSET_PLUS2 (Bit 29)                                 */
36440  #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Msk                                (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01)                    */
36441  #define R_ETHSW_GPARSER7_CMP_MASK_OR_Pos                                 (30UL)         /*!< CMP_MASK_OR (Bit 30)                                  */
36442  #define R_ETHSW_GPARSER7_CMP_MASK_OR_Msk                                 (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01)                     */
36443 /* ========================================================  GARITH4  ======================================================== */
36444  #define R_ETHSW_GARITH4_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36445  #define R_ETHSW_GARITH4_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36446  #define R_ETHSW_GARITH4_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36447  #define R_ETHSW_GARITH4_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36448  #define R_ETHSW_GARITH4_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36449  #define R_ETHSW_GARITH4_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36450  #define R_ETHSW_GARITH4_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36451  #define R_ETHSW_GARITH4_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36452  #define R_ETHSW_GARITH4_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36453  #define R_ETHSW_GARITH4_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36454  #define R_ETHSW_GARITH4_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36455  #define R_ETHSW_GARITH4_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36456  #define R_ETHSW_GARITH4_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36457  #define R_ETHSW_GARITH4_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36458  #define R_ETHSW_GARITH4_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36459  #define R_ETHSW_GARITH4_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36460 /* ========================================================  GARITH5  ======================================================== */
36461  #define R_ETHSW_GARITH5_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36462  #define R_ETHSW_GARITH5_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36463  #define R_ETHSW_GARITH5_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36464  #define R_ETHSW_GARITH5_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36465  #define R_ETHSW_GARITH5_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36466  #define R_ETHSW_GARITH5_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36467  #define R_ETHSW_GARITH5_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36468  #define R_ETHSW_GARITH5_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36469  #define R_ETHSW_GARITH5_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36470  #define R_ETHSW_GARITH5_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36471  #define R_ETHSW_GARITH5_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36472  #define R_ETHSW_GARITH5_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36473  #define R_ETHSW_GARITH5_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36474  #define R_ETHSW_GARITH5_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36475  #define R_ETHSW_GARITH5_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36476  #define R_ETHSW_GARITH5_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36477 /* ========================================================  GARITH6  ======================================================== */
36478  #define R_ETHSW_GARITH6_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36479  #define R_ETHSW_GARITH6_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36480  #define R_ETHSW_GARITH6_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36481  #define R_ETHSW_GARITH6_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36482  #define R_ETHSW_GARITH6_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36483  #define R_ETHSW_GARITH6_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36484  #define R_ETHSW_GARITH6_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36485  #define R_ETHSW_GARITH6_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36486  #define R_ETHSW_GARITH6_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36487  #define R_ETHSW_GARITH6_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36488  #define R_ETHSW_GARITH6_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36489  #define R_ETHSW_GARITH6_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36490  #define R_ETHSW_GARITH6_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36491  #define R_ETHSW_GARITH6_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36492  #define R_ETHSW_GARITH6_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36493  #define R_ETHSW_GARITH6_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36494 /* ========================================================  GARITH7  ======================================================== */
36495  #define R_ETHSW_GARITH7_NOT_INP_Pos                                      (0UL)          /*!< NOT_INP (Bit 0)                                       */
36496  #define R_ETHSW_GARITH7_NOT_INP_Msk                                      (0xfUL)        /*!< NOT_INP (Bitfield-Mask: 0x0f)                         */
36497  #define R_ETHSW_GARITH7_SEL_MATCH_Pos                                    (8UL)          /*!< SEL_MATCH (Bit 8)                                     */
36498  #define R_ETHSW_GARITH7_SEL_MATCH_Msk                                    (0xf00UL)      /*!< SEL_MATCH (Bitfield-Mask: 0x0f)                       */
36499  #define R_ETHSW_GARITH7_SEL_ARITH0_Pos                                   (12UL)         /*!< SEL_ARITH0 (Bit 12)                                   */
36500  #define R_ETHSW_GARITH7_SEL_ARITH0_Msk                                   (0x1000UL)     /*!< SEL_ARITH0 (Bitfield-Mask: 0x01)                      */
36501  #define R_ETHSW_GARITH7_SEL_ARITH1_Pos                                   (13UL)         /*!< SEL_ARITH1 (Bit 13)                                   */
36502  #define R_ETHSW_GARITH7_SEL_ARITH1_Msk                                   (0x2000UL)     /*!< SEL_ARITH1 (Bitfield-Mask: 0x01)                      */
36503  #define R_ETHSW_GARITH7_SEL_ARITH2_Pos                                   (14UL)         /*!< SEL_ARITH2 (Bit 14)                                   */
36504  #define R_ETHSW_GARITH7_SEL_ARITH2_Msk                                   (0x4000UL)     /*!< SEL_ARITH2 (Bitfield-Mask: 0x01)                      */
36505  #define R_ETHSW_GARITH7_OP_Pos                                           (16UL)         /*!< OP (Bit 16)                                           */
36506  #define R_ETHSW_GARITH7_OP_Msk                                           (0x10000UL)    /*!< OP (Bitfield-Mask: 0x01)                              */
36507  #define R_ETHSW_GARITH7_RESULT_INV_Pos                                   (17UL)         /*!< RESULT_INV (Bit 17)                                   */
36508  #define R_ETHSW_GARITH7_RESULT_INV_Msk                                   (0x20000UL)    /*!< RESULT_INV (Bitfield-Mask: 0x01)                      */
36509  #define R_ETHSW_GARITH7_SNP_MD_Pos                                       (20UL)         /*!< SNP_MD (Bit 20)                                       */
36510  #define R_ETHSW_GARITH7_SNP_MD_Msk                                       (0x300000UL)   /*!< SNP_MD (Bitfield-Mask: 0x03)                          */
36511 /* =====================================================  VLAN_PRIORITY  ===================================================== */
36512  #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Pos                              (0UL)          /*!< PRIORITY0 (Bit 0)                                     */
36513  #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Msk                              (0x7UL)        /*!< PRIORITY0 (Bitfield-Mask: 0x07)                       */
36514  #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Pos                              (3UL)          /*!< PRIORITY1 (Bit 3)                                     */
36515  #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Msk                              (0x38UL)       /*!< PRIORITY1 (Bitfield-Mask: 0x07)                       */
36516  #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Pos                              (6UL)          /*!< PRIORITY2 (Bit 6)                                     */
36517  #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Msk                              (0x1c0UL)      /*!< PRIORITY2 (Bitfield-Mask: 0x07)                       */
36518  #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Pos                              (9UL)          /*!< PRIORITY3 (Bit 9)                                     */
36519  #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Msk                              (0xe00UL)      /*!< PRIORITY3 (Bitfield-Mask: 0x07)                       */
36520  #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Pos                              (12UL)         /*!< PRIORITY4 (Bit 12)                                    */
36521  #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Msk                              (0x7000UL)     /*!< PRIORITY4 (Bitfield-Mask: 0x07)                       */
36522  #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Pos                              (15UL)         /*!< PRIORITY5 (Bit 15)                                    */
36523  #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Msk                              (0x38000UL)    /*!< PRIORITY5 (Bitfield-Mask: 0x07)                       */
36524  #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Pos                              (18UL)         /*!< PRIORITY6 (Bit 18)                                    */
36525  #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Msk                              (0x1c0000UL)   /*!< PRIORITY6 (Bitfield-Mask: 0x07)                       */
36526  #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Pos                              (21UL)         /*!< PRIORITY7 (Bit 21)                                    */
36527  #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Msk                              (0xe00000UL)   /*!< PRIORITY7 (Bitfield-Mask: 0x07)                       */
36528 /* ======================================================  IP_PRIORITY  ====================================================== */
36529  #define R_ETHSW_IP_PRIORITY_ADDRESS_Pos                                  (0UL)          /*!< ADDRESS (Bit 0)                                       */
36530  #define R_ETHSW_IP_PRIORITY_ADDRESS_Msk                                  (0xffUL)       /*!< ADDRESS (Bitfield-Mask: 0xff)                         */
36531  #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Pos                               (8UL)          /*!< IPV6SELECT (Bit 8)                                    */
36532  #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Msk                               (0x100UL)      /*!< IPV6SELECT (Bitfield-Mask: 0x01)                      */
36533  #define R_ETHSW_IP_PRIORITY_PRIORITY_Pos                                 (9UL)          /*!< PRIORITY (Bit 9)                                      */
36534  #define R_ETHSW_IP_PRIORITY_PRIORITY_Msk                                 (0xe00UL)      /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
36535  #define R_ETHSW_IP_PRIORITY_READ_Pos                                     (31UL)         /*!< READ (Bit 31)                                         */
36536  #define R_ETHSW_IP_PRIORITY_READ_Msk                                     (0x80000000UL) /*!< READ (Bitfield-Mask: 0x01)                            */
36537 /* =====================================================  PRIORITY_CFG  ====================================================== */
36538  #define R_ETHSW_PRIORITY_CFG_VLANEN_Pos                                  (0UL)          /*!< VLANEN (Bit 0)                                        */
36539  #define R_ETHSW_PRIORITY_CFG_VLANEN_Msk                                  (0x1UL)        /*!< VLANEN (Bitfield-Mask: 0x01)                          */
36540  #define R_ETHSW_PRIORITY_CFG_IPEN_Pos                                    (1UL)          /*!< IPEN (Bit 1)                                          */
36541  #define R_ETHSW_PRIORITY_CFG_IPEN_Msk                                    (0x2UL)        /*!< IPEN (Bitfield-Mask: 0x01)                            */
36542  #define R_ETHSW_PRIORITY_CFG_MACEN_Pos                                   (2UL)          /*!< MACEN (Bit 2)                                         */
36543  #define R_ETHSW_PRIORITY_CFG_MACEN_Msk                                   (0x4UL)        /*!< MACEN (Bitfield-Mask: 0x01)                           */
36544  #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Pos                                 (3UL)          /*!< TYPE_EN (Bit 3)                                       */
36545  #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Msk                                 (0x8UL)        /*!< TYPE_EN (Bitfield-Mask: 0x01)                         */
36546  #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Pos                              (4UL)          /*!< DEFAULTPRI (Bit 4)                                    */
36547  #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Msk                              (0x70UL)       /*!< DEFAULTPRI (Bitfield-Mask: 0x07)                      */
36548  #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Pos                           (7UL)          /*!< PCP_REMAP_DIS (Bit 7)                                 */
36549  #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Msk                           (0x80UL)       /*!< PCP_REMAP_DIS (Bitfield-Mask: 0x01)                   */
36550  #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Pos                               (8UL)          /*!< PCP_REMAP (Bit 8)                                     */
36551  #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Msk                               (0xffffff00UL) /*!< PCP_REMAP (Bitfield-Mask: 0xffffff)                   */
36552 /* ====================================================  PRIORITY_TYPE1  ===================================================== */
36553  #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Pos                               (0UL)          /*!< TYPEVAL (Bit 0)                                       */
36554  #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Msk                               (0xffffUL)     /*!< TYPEVAL (Bitfield-Mask: 0xffff)                       */
36555  #define R_ETHSW_PRIORITY_TYPE1_VALID_Pos                                 (16UL)         /*!< VALID (Bit 16)                                        */
36556  #define R_ETHSW_PRIORITY_TYPE1_VALID_Msk                                 (0x10000UL)    /*!< VALID (Bitfield-Mask: 0x01)                           */
36557  #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Pos                              (17UL)         /*!< PRIORITY (Bit 17)                                     */
36558  #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Msk                              (0xe0000UL)    /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
36559 /* ====================================================  PRIORITY_TYPE2  ===================================================== */
36560  #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Pos                               (0UL)          /*!< TYPEVAL (Bit 0)                                       */
36561  #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Msk                               (0xffffUL)     /*!< TYPEVAL (Bitfield-Mask: 0xffff)                       */
36562  #define R_ETHSW_PRIORITY_TYPE2_VALID_Pos                                 (16UL)         /*!< VALID (Bit 16)                                        */
36563  #define R_ETHSW_PRIORITY_TYPE2_VALID_Msk                                 (0x10000UL)    /*!< VALID (Bitfield-Mask: 0x01)                           */
36564  #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Pos                              (17UL)         /*!< PRIORITY (Bit 17)                                     */
36565  #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Msk                              (0xe0000UL)    /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
36566 /* ======================================================  SRCFLT_ENA  ======================================================= */
36567  #define R_ETHSW_SRCFLT_ENA_SRCENA_Pos                                    (0UL)          /*!< SRCENA (Bit 0)                                        */
36568  #define R_ETHSW_SRCFLT_ENA_SRCENA_Msk                                    (0x7UL)        /*!< SRCENA (Bitfield-Mask: 0x07)                          */
36569  #define R_ETHSW_SRCFLT_ENA_DSTENA_Pos                                    (16UL)         /*!< DSTENA (Bit 16)                                       */
36570  #define R_ETHSW_SRCFLT_ENA_DSTENA_Msk                                    (0xf0000UL)    /*!< DSTENA (Bitfield-Mask: 0x0f)                          */
36571 /* ====================================================  SRCFLT_CONTROL  ===================================================== */
36572  #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Pos                              (0UL)          /*!< MGMT_FWD (Bit 0)                                      */
36573  #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Msk                              (0x1UL)        /*!< MGMT_FWD (Bitfield-Mask: 0x01)                        */
36574  #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Pos                          (1UL)          /*!< WATCHDOG_ENA (Bit 1)                                  */
36575  #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Msk                          (0x2UL)        /*!< WATCHDOG_ENA (Bitfield-Mask: 0x01)                    */
36576  #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Pos                         (16UL)         /*!< WATCHDOG_TIME (Bit 16)                                */
36577  #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Msk                         (0xffff0000UL) /*!< WATCHDOG_TIME (Bitfield-Mask: 0xffff)                 */
36578 /* ===================================================  SRCFLT_MACADDR_LO  =================================================== */
36579  #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Pos                     (0UL)          /*!< SRCFLT_MACADDR (Bit 0)                                */
36580  #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Msk                     (0xffffffffUL) /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffffffff)            */
36581 /* ===================================================  SRCFLT_MACADDR_HI  =================================================== */
36582  #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Pos                     (0UL)          /*!< SRCFLT_MACADDR (Bit 0)                                */
36583  #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Msk                     (0xffffUL)     /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffff)                */
36584  #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Pos                               (16UL)         /*!< MASK (Bit 16)                                         */
36585  #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Msk                               (0xffff0000UL) /*!< MASK (Bitfield-Mask: 0xffff)                          */
36586 /* ====================================================  PHY_FILTER_CFG  ===================================================== */
36587  #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Pos                       (0UL)          /*!< FILTER_DURATION (Bit 0)                               */
36588  #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Msk                       (0x1ffUL)      /*!< FILTER_DURATION (Bitfield-Mask: 0x1ff)                */
36589  #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Pos                                (16UL)         /*!< FLT_EN (Bit 16)                                       */
36590  #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Msk                                (0x70000UL)    /*!< FLT_EN (Bitfield-Mask: 0x07)                          */
36591 /* ====================================================  SYSTEM_TAGINFO  ===================================================== */
36592  #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Pos                           (0UL)          /*!< SYSVLANINFO (Bit 0)                                   */
36593  #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Msk                           (0xffffUL)     /*!< SYSVLANINFO (Bitfield-Mask: 0xffff)                   */
36594 /* =======================================================  AUTH_PORT  ======================================================= */
36595  #define R_ETHSW_AUTH_PORT_AUTH_Pos                                       (0UL)          /*!< AUTH (Bit 0)                                          */
36596  #define R_ETHSW_AUTH_PORT_AUTH_Msk                                       (0x1UL)        /*!< AUTH (Bitfield-Mask: 0x01)                            */
36597  #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Pos                                  (1UL)          /*!< CTRL_BOTH (Bit 1)                                     */
36598  #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Msk                                  (0x2UL)        /*!< CTRL_BOTH (Bitfield-Mask: 0x01)                       */
36599  #define R_ETHSW_AUTH_PORT_EAPOL_EN_Pos                                   (2UL)          /*!< EAPOL_EN (Bit 2)                                      */
36600  #define R_ETHSW_AUTH_PORT_EAPOL_EN_Msk                                   (0x4UL)        /*!< EAPOL_EN (Bitfield-Mask: 0x01)                        */
36601  #define R_ETHSW_AUTH_PORT_GUEST_EN_Pos                                   (3UL)          /*!< GUEST_EN (Bit 3)                                      */
36602  #define R_ETHSW_AUTH_PORT_GUEST_EN_Msk                                   (0x8UL)        /*!< GUEST_EN (Bitfield-Mask: 0x01)                        */
36603  #define R_ETHSW_AUTH_PORT_BPDU_EN_Pos                                    (4UL)          /*!< BPDU_EN (Bit 4)                                       */
36604  #define R_ETHSW_AUTH_PORT_BPDU_EN_Msk                                    (0x10UL)       /*!< BPDU_EN (Bitfield-Mask: 0x01)                         */
36605  #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Pos                                (5UL)          /*!< EAPOL_UC_EN (Bit 5)                                   */
36606  #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Msk                                (0x20UL)       /*!< EAPOL_UC_EN (Bitfield-Mask: 0x01)                     */
36607  #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Pos                                (11UL)         /*!< ACHG_UNAUTH (Bit 11)                                  */
36608  #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Msk                                (0x800UL)      /*!< ACHG_UNAUTH (Bitfield-Mask: 0x01)                     */
36609  #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Pos                                 (12UL)         /*!< EAPOL_PNUM (Bit 12)                                   */
36610  #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Msk                                 (0xf000UL)     /*!< EAPOL_PNUM (Bitfield-Mask: 0x0f)                      */
36611  #define R_ETHSW_AUTH_PORT_GUEST_MASK_Pos                                 (16UL)         /*!< GUEST_MASK (Bit 16)                                   */
36612  #define R_ETHSW_AUTH_PORT_GUEST_MASK_Msk                                 (0xf0000UL)    /*!< GUEST_MASK (Bitfield-Mask: 0x0f)                      */
36613 /* ====================================================  VLAN_RES_TABLE  ===================================================== */
36614  #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos                              (0UL)          /*!< PORTMASK (Bit 0)                                      */
36615  #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk                              (0xfUL)        /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
36616  #define R_ETHSW_VLAN_RES_TABLE_VLANID_Pos                                (4UL)          /*!< VLANID (Bit 4)                                        */
36617  #define R_ETHSW_VLAN_RES_TABLE_VLANID_Msk                                (0xfff0UL)     /*!< VLANID (Bitfield-Mask: 0xfff)                         */
36618  #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Pos                             (28UL)         /*!< RD_TAGMSK (Bit 28)                                    */
36619  #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Msk                             (0x10000000UL) /*!< RD_TAGMSK (Bitfield-Mask: 0x01)                       */
36620  #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Pos                             (29UL)         /*!< WT_TAGMSK (Bit 29)                                    */
36621  #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Msk                             (0x20000000UL) /*!< WT_TAGMSK (Bitfield-Mask: 0x01)                       */
36622  #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Pos                             (30UL)         /*!< WT_PRTMSK (Bit 30)                                    */
36623  #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Msk                             (0x40000000UL) /*!< WT_PRTMSK (Bitfield-Mask: 0x01)                       */
36624 /* ======================================================  TOTAL_DISC  ======================================================= */
36625  #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Pos                                (0UL)          /*!< TOTAL_DISC (Bit 0)                                    */
36626  #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Msk                                (0xffffffffUL) /*!< TOTAL_DISC (Bitfield-Mask: 0xffffffff)                */
36627 /* ====================================================  TOTAL_BYT_DISC  ===================================================== */
36628  #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Pos                        (0UL)          /*!< TOTAL_BYT_DISC (Bit 0)                                */
36629  #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Msk                        (0xffffffffUL) /*!< TOTAL_BYT_DISC (Bitfield-Mask: 0xffffffff)            */
36630 /* =======================================================  TOTAL_FRM  ======================================================= */
36631  #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Pos                                  (0UL)          /*!< TOTAL_FRM (Bit 0)                                     */
36632  #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Msk                                  (0xffffffffUL) /*!< TOTAL_FRM (Bitfield-Mask: 0xffffffff)                 */
36633 /* =====================================================  TOTAL_BYT_FRM  ===================================================== */
36634  #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Pos                          (0UL)          /*!< TOTAL_BYT_FRM (Bit 0)                                 */
36635  #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Msk                          (0xffffffffUL) /*!< TOTAL_BYT_FRM (Bitfield-Mask: 0xffffffff)             */
36636 /* =====================================================  IALK_CONTROL  ====================================================== */
36637  #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Pos                             (0UL)          /*!< IA_LKUP_ENA (Bit 0)                                   */
36638  #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Msk                             (0xfUL)        /*!< IA_LKUP_ENA (Bitfield-Mask: 0x0f)                     */
36639  #define R_ETHSW_IALK_CONTROL_CT_ENA_Pos                                  (16UL)         /*!< CT_ENA (Bit 16)                                       */
36640  #define R_ETHSW_IALK_CONTROL_CT_ENA_Msk                                  (0xf0000UL)    /*!< CT_ENA (Bitfield-Mask: 0x0f)                          */
36641 /* =======================================================  IALK_OUI  ======================================================== */
36642  #define R_ETHSW_IALK_OUI_IALK_OUI_Pos                                    (0UL)          /*!< IALK_OUI (Bit 0)                                      */
36643  #define R_ETHSW_IALK_OUI_IALK_OUI_Msk                                    (0xffffffUL)   /*!< IALK_OUI (Bitfield-Mask: 0xffffff)                    */
36644 /* ======================================================  IALK_ID_MIN  ====================================================== */
36645  #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Pos                              (0UL)          /*!< IALK_ID_MIN (Bit 0)                                   */
36646  #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Msk                              (0xffffffUL)   /*!< IALK_ID_MIN (Bitfield-Mask: 0xffffff)                 */
36647 /* ======================================================  IALK_ID_MAX  ====================================================== */
36648  #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Pos                              (0UL)          /*!< IALK_ID_MAX (Bit 0)                                   */
36649  #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Msk                              (0xffffffUL)   /*!< IALK_ID_MAX (Bitfield-Mask: 0xffffff)                 */
36650 /* ======================================================  IALK_ID_SUB  ====================================================== */
36651  #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Pos                              (0UL)          /*!< IALK_ID_SUB (Bit 0)                                   */
36652  #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Msk                              (0xffffffUL)   /*!< IALK_ID_SUB (Bitfield-Mask: 0xffffff)                 */
36653 /* ====================================================  IALK_ID_CONFIG  ===================================================== */
36654  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Pos                        (0UL)          /*!< INVLD_ID_FLOOD (Bit 0)                                */
36655  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Msk                        (0x1UL)        /*!< INVLD_ID_FLOOD (Bitfield-Mask: 0x01)                  */
36656  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Pos                      (1UL)          /*!< INVLD_ID_LRN_ENA (Bit 1)                              */
36657  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Msk                      (0x2UL)        /*!< INVLD_ID_LRN_ENA (Bitfield-Mask: 0x01)                */
36658  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Pos                         (4UL)          /*!< INVLD_ID_PRIO (Bit 4)                                 */
36659  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Msk                         (0x70UL)       /*!< INVLD_ID_PRIO (Bitfield-Mask: 0x07)                   */
36660  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Pos                     (7UL)          /*!< INVLD_ID_PRIO_VLD (Bit 7)                             */
36661  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Msk                     (0x80UL)       /*!< INVLD_ID_PRIO_VLD (Bitfield-Mask: 0x01)               */
36662  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Pos                   (16UL)         /*!< INVLD_ID_FLOOD_MASK (Bit 16)                          */
36663  #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Msk                   (0xf0000UL)    /*!< INVLD_ID_FLOOD_MASK (Bitfield-Mask: 0x0f)             */
36664 /* ===================================================  IALK_VLAN_CONFIG  ==================================================== */
36665  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Pos                    (0UL)          /*!< UNKWN_VLAN_FLOOD (Bit 0)                              */
36666  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Msk                    (0x1UL)        /*!< UNKWN_VLAN_FLOOD (Bitfield-Mask: 0x01)                */
36667  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Pos                  (1UL)          /*!< UNKWN_VLAN_LRN_ENA (Bit 1)                            */
36668  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Msk                  (0x2UL)        /*!< UNKWN_VLAN_LRN_ENA (Bitfield-Mask: 0x01)              */
36669  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Pos                     (4UL)          /*!< UNKWN_VLAN_PRIO (Bit 4)                               */
36670  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Msk                     (0x70UL)       /*!< UNKWN_VLAN_PRIO (Bitfield-Mask: 0x07)                 */
36671  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Pos                 (7UL)          /*!< UNKWN_VLAN_PRIO_VLD (Bit 7)                           */
36672  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Msk                 (0x80UL)       /*!< UNKWN_VLAN_PRIO_VLD (Bitfield-Mask: 0x01)             */
36673  #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Pos                       (8UL)          /*!< VLANS_ENABLED (Bit 8)                                 */
36674  #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Msk                       (0x700UL)      /*!< VLANS_ENABLED (Bitfield-Mask: 0x07)                   */
36675  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Pos               (16UL)         /*!< UNKWN_VLAN_FLOOD_MASK (Bit 16)                        */
36676  #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Msk               (0xf0000UL)    /*!< UNKWN_VLAN_FLOOD_MASK (Bitfield-Mask: 0x0f)        */
36677 /* =====================================================  IALK_TBL_ADDR  ===================================================== */
36678  #define R_ETHSW_IALK_TBL_ADDR_ADDR_Pos                                   (0UL)          /*!< ADDR (Bit 0)                                          */
36679  #define R_ETHSW_IALK_TBL_ADDR_ADDR_Msk                                   (0x1fffUL)     /*!< ADDR (Bitfield-Mask: 0x1fff)                          */
36680  #define R_ETHSW_IALK_TBL_ADDR_AINC_Pos                                   (28UL)         /*!< AINC (Bit 28)                                         */
36681  #define R_ETHSW_IALK_TBL_ADDR_AINC_Msk                                   (0xf0000000UL) /*!< AINC (Bitfield-Mask: 0x0f)                            */
36682 /* =====================================================  IALK_TBL_DATA  ===================================================== */
36683  #define R_ETHSW_IALK_TBL_DATA_VALID_Pos                                  (0UL)          /*!< VALID (Bit 0)                                         */
36684  #define R_ETHSW_IALK_TBL_DATA_VALID_Msk                                  (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
36685  #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Pos                               (1UL)          /*!< FWD_MASK (Bit 1)                                      */
36686  #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Msk                               (0x1eUL)       /*!< FWD_MASK (Bitfield-Mask: 0x0f)                        */
36687 /* ======================================================  IALK_VLANID  ====================================================== */
36688  #define R_ETHSW_IALK_VLANID_VLANID_Pos                                   (0UL)          /*!< VLANID (Bit 0)                                        */
36689  #define R_ETHSW_IALK_VLANID_VLANID_Msk                                   (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
36690  #define R_ETHSW_IALK_VLANID_VLANID_ENA_Pos                               (12UL)         /*!< VLANID_ENA (Bit 12)                                   */
36691  #define R_ETHSW_IALK_VLANID_VLANID_ENA_Msk                               (0x1000UL)     /*!< VLANID_ENA (Bitfield-Mask: 0x01)                      */
36692  #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Pos                           (13UL)         /*!< VLANID_LRN_ENA (Bit 13)                               */
36693  #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Msk                           (0x2000UL)     /*!< VLANID_LRN_ENA (Bitfield-Mask: 0x01)                  */
36694  #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Pos                        (16UL)         /*!< VLANID_FLOOD_MASK (Bit 16)                            */
36695  #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Msk                        (0xf0000UL)    /*!< VLANID_FLOOD_MASK (Bitfield-Mask: 0x0f)               */
36696  #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Pos                              (28UL)         /*!< VLANID_PRIO (Bit 28)                                  */
36697  #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Msk                              (0x70000000UL) /*!< VLANID_PRIO (Bitfield-Mask: 0x07)                     */
36698  #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Pos                          (31UL)         /*!< VLANID_PRIO_VLD (Bit 31)                              */
36699  #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Msk                          (0x80000000UL) /*!< VLANID_PRIO_VLD (Bitfield-Mask: 0x01)                 */
36700 /* =====================================================  IMC_QLEVEL_P  ====================================================== */
36701  #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Pos                                  (0UL)          /*!< QUEUE0 (Bit 0)                                        */
36702  #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Msk                                  (0xfUL)        /*!< QUEUE0 (Bitfield-Mask: 0x0f)                          */
36703  #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Pos                                  (4UL)          /*!< QUEUE1 (Bit 4)                                        */
36704  #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Msk                                  (0xf0UL)       /*!< QUEUE1 (Bitfield-Mask: 0x0f)                          */
36705  #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Pos                                  (8UL)          /*!< QUEUE2 (Bit 8)                                        */
36706  #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Msk                                  (0xf00UL)      /*!< QUEUE2 (Bitfield-Mask: 0x0f)                          */
36707  #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Pos                                  (12UL)         /*!< QUEUE3 (Bit 12)                                       */
36708  #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Msk                                  (0xf000UL)     /*!< QUEUE3 (Bitfield-Mask: 0x0f)                          */
36709  #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Pos                                  (16UL)         /*!< QUEUE4 (Bit 16)                                       */
36710  #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Msk                                  (0xf0000UL)    /*!< QUEUE4 (Bitfield-Mask: 0x0f)                          */
36711  #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Pos                                  (20UL)         /*!< QUEUE5 (Bit 20)                                       */
36712  #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Msk                                  (0xf00000UL)   /*!< QUEUE5 (Bitfield-Mask: 0x0f)                          */
36713  #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Pos                                  (24UL)         /*!< QUEUE6 (Bit 24)                                       */
36714  #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Msk                                  (0xf000000UL)  /*!< QUEUE6 (Bitfield-Mask: 0x0f)                          */
36715  #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Pos                                  (28UL)         /*!< QUEUE7 (Bit 28)                                       */
36716  #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Msk                                  (0xf0000000UL) /*!< QUEUE7 (Bitfield-Mask: 0x0f)                          */
36717 /* ========================================================  LK_CTRL  ======================================================== */
36718  #define R_ETHSW_LK_CTRL_LKUP_EN_Pos                                      (0UL)          /*!< LKUP_EN (Bit 0)                                       */
36719  #define R_ETHSW_LK_CTRL_LKUP_EN_Msk                                      (0x1UL)        /*!< LKUP_EN (Bitfield-Mask: 0x01)                         */
36720  #define R_ETHSW_LK_CTRL_LEARN_EN_Pos                                     (1UL)          /*!< LEARN_EN (Bit 1)                                      */
36721  #define R_ETHSW_LK_CTRL_LEARN_EN_Msk                                     (0x2UL)        /*!< LEARN_EN (Bitfield-Mask: 0x01)                        */
36722  #define R_ETHSW_LK_CTRL_AGING_EN_Pos                                     (2UL)          /*!< AGING_EN (Bit 2)                                      */
36723  #define R_ETHSW_LK_CTRL_AGING_EN_Msk                                     (0x4UL)        /*!< AGING_EN (Bitfield-Mask: 0x01)                        */
36724  #define R_ETHSW_LK_CTRL_ALW_MGRT_Pos                                     (3UL)          /*!< ALW_MGRT (Bit 3)                                      */
36725  #define R_ETHSW_LK_CTRL_ALW_MGRT_Msk                                     (0x8UL)        /*!< ALW_MGRT (Bitfield-Mask: 0x01)                        */
36726  #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Pos                                (4UL)          /*!< DISC_UNK_DEST (Bit 4)                                 */
36727  #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Msk                                (0x10UL)       /*!< DISC_UNK_DEST (Bitfield-Mask: 0x01)                   */
36728  #define R_ETHSW_LK_CTRL_CLRTBL_Pos                                       (6UL)          /*!< CLRTBL (Bit 6)                                        */
36729  #define R_ETHSW_LK_CTRL_CLRTBL_Msk                                       (0x40UL)       /*!< CLRTBL (Bitfield-Mask: 0x01)                          */
36730  #define R_ETHSW_LK_CTRL_IND_VLAN_Pos                                     (7UL)          /*!< IND_VLAN (Bit 7)                                      */
36731  #define R_ETHSW_LK_CTRL_IND_VLAN_Msk                                     (0x80UL)       /*!< IND_VLAN (Bitfield-Mask: 0x01)                        */
36732  #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Pos                                 (16UL)         /*!< DISC_UNK_SRC (Bit 16)                                 */
36733  #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Msk                                 (0xf0000UL)    /*!< DISC_UNK_SRC (Bitfield-Mask: 0x0f)                    */
36734 /* =======================================================  LK_STATUS  ======================================================= */
36735  #define R_ETHSW_LK_STATUS_AGEADDR_Pos                                    (0UL)          /*!< AGEADDR (Bit 0)                                       */
36736  #define R_ETHSW_LK_STATUS_AGEADDR_Msk                                    (0xffffUL)     /*!< AGEADDR (Bitfield-Mask: 0xffff)                       */
36737  #define R_ETHSW_LK_STATUS_OVRF_Pos                                       (16UL)         /*!< OVRF (Bit 16)                                         */
36738  #define R_ETHSW_LK_STATUS_OVRF_Msk                                       (0x3fff0000UL) /*!< OVRF (Bitfield-Mask: 0x3fff)                          */
36739  #define R_ETHSW_LK_STATUS_LRNEVNT_Pos                                    (31UL)         /*!< LRNEVNT (Bit 31)                                      */
36740  #define R_ETHSW_LK_STATUS_LRNEVNT_Msk                                    (0x80000000UL) /*!< LRNEVNT (Bitfield-Mask: 0x01)                         */
36741 /* =====================================================  LK_ADDR_CTRL  ====================================================== */
36742  #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Pos                                (0UL)          /*!< ADDR_MSK (Bit 0)                                      */
36743  #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Msk                                (0xfffUL)      /*!< ADDR_MSK (Bitfield-Mask: 0xfff)                       */
36744  #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Pos                             (22UL)         /*!< CLR_DYNAMIC (Bit 22)                                  */
36745  #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Msk                             (0x400000UL)   /*!< CLR_DYNAMIC (Bitfield-Mask: 0x01)                     */
36746  #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Pos                              (23UL)         /*!< CLR_STATIC (Bit 23)                                   */
36747  #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Msk                              (0x800000UL)   /*!< CLR_STATIC (Bitfield-Mask: 0x01)                      */
36748  #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Pos                              (24UL)         /*!< GETLASTNEW (Bit 24)                                   */
36749  #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Msk                              (0x1000000UL)  /*!< GETLASTNEW (Bitfield-Mask: 0x01)                      */
36750  #define R_ETHSW_LK_ADDR_CTRL_WRITE_Pos                                   (25UL)         /*!< WRITE (Bit 25)                                        */
36751  #define R_ETHSW_LK_ADDR_CTRL_WRITE_Msk                                   (0x2000000UL)  /*!< WRITE (Bitfield-Mask: 0x01)                           */
36752  #define R_ETHSW_LK_ADDR_CTRL_READ_Pos                                    (26UL)         /*!< READ (Bit 26)                                         */
36753  #define R_ETHSW_LK_ADDR_CTRL_READ_Msk                                    (0x4000000UL)  /*!< READ (Bitfield-Mask: 0x01)                            */
36754  #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Pos                               (27UL)         /*!< WAIT_COMP (Bit 27)                                    */
36755  #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Msk                               (0x8000000UL)  /*!< WAIT_COMP (Bitfield-Mask: 0x01)                       */
36756  #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Pos                                  (28UL)         /*!< LOOKUP (Bit 28)                                       */
36757  #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Msk                                  (0x10000000UL) /*!< LOOKUP (Bitfield-Mask: 0x01)                          */
36758  #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Pos                                   (29UL)         /*!< CLEAR (Bit 29)                                        */
36759  #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Msk                                   (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01)                           */
36760  #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Pos                                (30UL)         /*!< DEL_PORT (Bit 30)                                     */
36761  #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Msk                                (0x40000000UL) /*!< DEL_PORT (Bitfield-Mask: 0x01)                        */
36762  #define R_ETHSW_LK_ADDR_CTRL_BUSY_Pos                                    (31UL)         /*!< BUSY (Bit 31)                                         */
36763  #define R_ETHSW_LK_ADDR_CTRL_BUSY_Msk                                    (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01)                            */
36764 /* ======================================================  LK_DATA_LO  ======================================================= */
36765  #define R_ETHSW_LK_DATA_LO_MEMDATA_Pos                                   (0UL)          /*!< MEMDATA (Bit 0)                                       */
36766  #define R_ETHSW_LK_DATA_LO_MEMDATA_Msk                                   (0xffffffffUL) /*!< MEMDATA (Bitfield-Mask: 0xffffffff)                   */
36767 /* ======================================================  LK_DATA_HI  ======================================================= */
36768  #define R_ETHSW_LK_DATA_HI_MEMDATA_Pos                                   (0UL)          /*!< MEMDATA (Bit 0)                                       */
36769  #define R_ETHSW_LK_DATA_HI_MEMDATA_Msk                                   (0x1ffffffUL)  /*!< MEMDATA (Bitfield-Mask: 0x1ffffff)                    */
36770 /* ======================================================  LK_DATA_HI2  ====================================================== */
36771  #define R_ETHSW_LK_DATA_HI2_MEMDATA_Pos                                  (8UL)          /*!< MEMDATA (Bit 8)                                       */
36772  #define R_ETHSW_LK_DATA_HI2_MEMDATA_Msk                                  (0xfff00UL)    /*!< MEMDATA (Bitfield-Mask: 0xfff)                        */
36773 /* =====================================================  LK_LEARNCOUNT  ===================================================== */
36774  #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Pos                             (0UL)          /*!< LEARNCOUNT (Bit 0)                                    */
36775  #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Msk                             (0x1fffUL)     /*!< LEARNCOUNT (Bitfield-Mask: 0x1fff)                    */
36776  #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Pos                               (30UL)         /*!< WRITE_MD (Bit 30)                                     */
36777  #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Msk                               (0xc0000000UL) /*!< WRITE_MD (Bitfield-Mask: 0x03)                        */
36778 /* ======================================================  LK_AGETIME  ======================================================= */
36779  #define R_ETHSW_LK_AGETIME_AGETIME_Pos                                   (0UL)          /*!< AGETIME (Bit 0)                                       */
36780  #define R_ETHSW_LK_AGETIME_AGETIME_Msk                                   (0xffffffUL)   /*!< AGETIME (Bitfield-Mask: 0xffffff)                     */
36781 /* ====================================================  MGMT_TAG_CONFIG  ==================================================== */
36782  #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Pos                               (0UL)          /*!< ENABLE (Bit 0)                                        */
36783  #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Msk                               (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
36784  #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Pos                            (1UL)          /*!< AL_FRAMES (Bit 1)                                     */
36785  #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Msk                            (0x2UL)        /*!< AL_FRAMES (Bitfield-Mask: 0x01)                       */
36786  #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Pos                             (4UL)          /*!< TYPE1_EN (Bit 4)                                      */
36787  #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Msk                             (0x10UL)       /*!< TYPE1_EN (Bitfield-Mask: 0x01)                        */
36788  #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Pos                             (5UL)          /*!< TYPE2_EN (Bit 5)                                      */
36789  #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Msk                             (0x20UL)       /*!< TYPE2_EN (Bitfield-Mask: 0x01)                        */
36790  #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Pos                             (16UL)         /*!< TAGFIELD (Bit 16)                                     */
36791  #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Msk                             (0xffff0000UL) /*!< TAGFIELD (Bitfield-Mask: 0xffff)                      */
36792 /* ======================================================  TSM_CONFIG  ======================================================= */
36793  #define R_ETHSW_TSM_CONFIG_IRQ_EN_Pos                                    (0UL)          /*!< IRQ_EN (Bit 0)                                        */
36794  #define R_ETHSW_TSM_CONFIG_IRQ_EN_Msk                                    (0x1UL)        /*!< IRQ_EN (Bitfield-Mask: 0x01)                          */
36795  #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Pos                                  (1UL)          /*!< IRQ_TEST (Bit 1)                                      */
36796  #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Msk                                  (0x2UL)        /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
36797  #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Pos                            (2UL)          /*!< IRQ_TSFIFO_OVR (Bit 2)                                */
36798  #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Msk                            (0x4UL)        /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01)                  */
36799  #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Pos                            (4UL)          /*!< IRQ_EVT_OFFSET (Bit 4)                                */
36800  #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Msk                            (0x30UL)       /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03)                  */
36801  #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Pos                            (8UL)          /*!< IRQ_EVT_PERIOD (Bit 8)                                */
36802  #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Msk                            (0x300UL)      /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03)                  */
36803  #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Pos                            (12UL)         /*!< IRQ_ATIME_OVER (Bit 12)                               */
36804  #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Msk                            (0x3000UL)     /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03)                  */
36805  #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Pos                                 (16UL)         /*!< IRQ_TX_EN (Bit 16)                                    */
36806  #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk                                 (0xf0000UL)    /*!< IRQ_TX_EN (Bitfield-Mask: 0x0f)                       */
36807 /* ===================================================  TSM_IRQ_STAT_ACK  ==================================================== */
36808  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Pos                            (0UL)          /*!< IRQ_STAT (Bit 0)                                      */
36809  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Msk                            (0x1UL)        /*!< IRQ_STAT (Bitfield-Mask: 0x01)                        */
36810  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Pos                            (1UL)          /*!< IRQ_TEST (Bit 1)                                      */
36811  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Msk                            (0x2UL)        /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
36812  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Pos                      (2UL)          /*!< IRQ_TSFIFO_OVR (Bit 2)                                */
36813  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Msk                      (0x4UL)        /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01)                  */
36814  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Pos                      (4UL)          /*!< IRQ_EVT_OFFSET (Bit 4)                                */
36815  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Msk                      (0x30UL)       /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03)                  */
36816  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Pos                      (8UL)          /*!< IRQ_EVT_PERIOD (Bit 8)                                */
36817  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Msk                      (0x300UL)      /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03)                  */
36818  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Pos                      (12UL)         /*!< IRQ_ATIME_OVER (Bit 12)                               */
36819  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Msk                      (0x3000UL)     /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03)                  */
36820  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Pos                              (16UL)         /*!< IRQ_TX (Bit 16)                                       */
36821  #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Msk                              (0xf0000UL)    /*!< IRQ_TX (Bitfield-Mask: 0x0f)                          */
36822 /* ======================================================  PTP_DOMAIN  ======================================================= */
36823  #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Pos                                   (0UL)          /*!< DOMAIN0 (Bit 0)                                       */
36824  #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Msk                                   (0xffUL)       /*!< DOMAIN0 (Bitfield-Mask: 0xff)                         */
36825  #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Pos                                   (8UL)          /*!< DOMAIN1 (Bit 8)                                       */
36826  #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Msk                                   (0xff00UL)     /*!< DOMAIN1 (Bitfield-Mask: 0xff)                         */
36827 /* ====================================================  PEERDELAY_P0_T0  ==================================================== */
36828  #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36829  #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36830 /* ====================================================  PEERDELAY_P1_T0  ==================================================== */
36831  #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36832  #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36833 /* ====================================================  PEERDELAY_P2_T0  ==================================================== */
36834  #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36835  #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36836 /* ====================================================  PEERDELAY_P3_T0  ==================================================== */
36837  #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36838  #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36839 /* ====================================================  PEERDELAY_P0_T1  ==================================================== */
36840  #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36841  #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36842 /* ====================================================  PEERDELAY_P1_T1  ==================================================== */
36843  #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36844  #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36845 /* ====================================================  PEERDELAY_P2_T1  ==================================================== */
36846  #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36847  #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36848 /* ====================================================  PEERDELAY_P3_T1  ==================================================== */
36849  #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Pos                            (0UL)          /*!< PEERDELAY (Bit 0)                                     */
36850  #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Msk                            (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff)                 */
36851 /* ====================================================  TS_FIFO_STATUS  ===================================================== */
36852  #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Pos                              (0UL)          /*!< FF_VALID (Bit 0)                                      */
36853  #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Msk                              (0xfUL)        /*!< FF_VALID (Bitfield-Mask: 0x0f)                        */
36854  #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Pos                                (16UL)         /*!< FF_OVR (Bit 16)                                       */
36855  #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Msk                                (0xf0000UL)    /*!< FF_OVR (Bitfield-Mask: 0x0f)                          */
36856 /* ===================================================  TS_FIFO_READ_CTRL  =================================================== */
36857  #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Pos                           (0UL)          /*!< PORT_NUM (Bit 0)                                      */
36858  #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Msk                           (0x3UL)        /*!< PORT_NUM (Bitfield-Mask: 0x03)                        */
36859  #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Pos                           (4UL)          /*!< TS_VALID (Bit 4)                                      */
36860  #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Msk                           (0x10UL)       /*!< TS_VALID (Bitfield-Mask: 0x01)                        */
36861  #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Pos                             (6UL)          /*!< TS_SEL (Bit 6)                                        */
36862  #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Msk                             (0x40UL)       /*!< TS_SEL (Bitfield-Mask: 0x01)                          */
36863  #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Pos                              (8UL)          /*!< TS_ID (Bit 8)                                         */
36864  #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Msk                              (0x7f00UL)     /*!< TS_ID (Bitfield-Mask: 0x7f)                           */
36865 /* ================================================  TS_FIFO_READ_TIMESTAMP  ================================================= */
36866  #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Pos                     (0UL)          /*!< TIMESTAMP (Bit 0)                                     */
36867  #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Msk                     (0xffffffffUL) /*!< TIMESTAMP (Bitfield-Mask: 0xffffffff)                 */
36868 /* ======================================================  INT_CONFIG  ======================================================= */
36869  #define R_ETHSW_INT_CONFIG_IRQ_EN_Pos                                    (0UL)          /*!< IRQ_EN (Bit 0)                                        */
36870  #define R_ETHSW_INT_CONFIG_IRQ_EN_Msk                                    (0x1UL)        /*!< IRQ_EN (Bitfield-Mask: 0x01)                          */
36871  #define R_ETHSW_INT_CONFIG_MDIO1_Pos                                     (1UL)          /*!< MDIO1 (Bit 1)                                         */
36872  #define R_ETHSW_INT_CONFIG_MDIO1_Msk                                     (0x2UL)        /*!< MDIO1 (Bitfield-Mask: 0x01)                           */
36873  #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Pos                                (3UL)          /*!< LK_NEW_SRC (Bit 3)                                    */
36874  #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Msk                                (0x8UL)        /*!< LK_NEW_SRC (Bitfield-Mask: 0x01)                      */
36875  #define R_ETHSW_INT_CONFIG_IRQ_TEST_Pos                                  (4UL)          /*!< IRQ_TEST (Bit 4)                                      */
36876  #define R_ETHSW_INT_CONFIG_IRQ_TEST_Msk                                  (0x10UL)       /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
36877  #define R_ETHSW_INT_CONFIG_DLR_INT_Pos                                   (5UL)          /*!< DLR_INT (Bit 5)                                       */
36878  #define R_ETHSW_INT_CONFIG_DLR_INT_Msk                                   (0x20UL)       /*!< DLR_INT (Bitfield-Mask: 0x01)                         */
36879  #define R_ETHSW_INT_CONFIG_PRP_INT_Pos                                   (6UL)          /*!< PRP_INT (Bit 6)                                       */
36880  #define R_ETHSW_INT_CONFIG_PRP_INT_Msk                                   (0x40UL)       /*!< PRP_INT (Bitfield-Mask: 0x01)                         */
36881  #define R_ETHSW_INT_CONFIG_HUB_INT_Pos                                   (7UL)          /*!< HUB_INT (Bit 7)                                       */
36882  #define R_ETHSW_INT_CONFIG_HUB_INT_Msk                                   (0x80UL)       /*!< HUB_INT (Bitfield-Mask: 0x01)                         */
36883  #define R_ETHSW_INT_CONFIG_IRQ_LINK_Pos                                  (8UL)          /*!< IRQ_LINK (Bit 8)                                      */
36884  #define R_ETHSW_INT_CONFIG_IRQ_LINK_Msk                                  (0x700UL)      /*!< IRQ_LINK (Bitfield-Mask: 0x07)                        */
36885  #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Pos                               (16UL)         /*!< IRQ_MAC_EEE (Bit 16)                                  */
36886  #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Msk                               (0x70000UL)    /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07)                     */
36887  #define R_ETHSW_INT_CONFIG_EFP_INT_Pos                                   (27UL)         /*!< EFP_INT (Bit 27)                                      */
36888  #define R_ETHSW_INT_CONFIG_EFP_INT_Msk                                   (0x8000000UL)  /*!< EFP_INT (Bitfield-Mask: 0x01)                         */
36889  #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Pos                             (28UL)         /*!< SRCFLT_WD_INT (Bit 28)                                */
36890  #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Msk                             (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01)                   */
36891  #define R_ETHSW_INT_CONFIG_TSM_INT_Pos                                   (29UL)         /*!< TSM_INT (Bit 29)                                      */
36892  #define R_ETHSW_INT_CONFIG_TSM_INT_Msk                                   (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01)                         */
36893  #define R_ETHSW_INT_CONFIG_TDMA_INT_Pos                                  (30UL)         /*!< TDMA_INT (Bit 30)                                     */
36894  #define R_ETHSW_INT_CONFIG_TDMA_INT_Msk                                  (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01)                        */
36895  #define R_ETHSW_INT_CONFIG_PATTERN_INT_Pos                               (31UL)         /*!< PATTERN_INT (Bit 31)                                  */
36896  #define R_ETHSW_INT_CONFIG_PATTERN_INT_Msk                               (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01)                     */
36897 /* =====================================================  INT_STAT_ACK  ====================================================== */
36898  #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Pos                                (0UL)          /*!< IRQ_PEND (Bit 0)                                      */
36899  #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Msk                                (0x1UL)        /*!< IRQ_PEND (Bitfield-Mask: 0x01)                        */
36900  #define R_ETHSW_INT_STAT_ACK_MDIO1_Pos                                   (1UL)          /*!< MDIO1 (Bit 1)                                         */
36901  #define R_ETHSW_INT_STAT_ACK_MDIO1_Msk                                   (0x2UL)        /*!< MDIO1 (Bitfield-Mask: 0x01)                           */
36902  #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Pos                              (3UL)          /*!< LK_NEW_SRC (Bit 3)                                    */
36903  #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Msk                              (0x8UL)        /*!< LK_NEW_SRC (Bitfield-Mask: 0x01)                      */
36904  #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Pos                                (4UL)          /*!< IRQ_TEST (Bit 4)                                      */
36905  #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Msk                                (0x10UL)       /*!< IRQ_TEST (Bitfield-Mask: 0x01)                        */
36906  #define R_ETHSW_INT_STAT_ACK_DLR_INT_Pos                                 (5UL)          /*!< DLR_INT (Bit 5)                                       */
36907  #define R_ETHSW_INT_STAT_ACK_DLR_INT_Msk                                 (0x20UL)       /*!< DLR_INT (Bitfield-Mask: 0x01)                         */
36908  #define R_ETHSW_INT_STAT_ACK_PRP_INT_Pos                                 (6UL)          /*!< PRP_INT (Bit 6)                                       */
36909  #define R_ETHSW_INT_STAT_ACK_PRP_INT_Msk                                 (0x40UL)       /*!< PRP_INT (Bitfield-Mask: 0x01)                         */
36910  #define R_ETHSW_INT_STAT_ACK_HUB_INT_Pos                                 (7UL)          /*!< HUB_INT (Bit 7)                                       */
36911  #define R_ETHSW_INT_STAT_ACK_HUB_INT_Msk                                 (0x80UL)       /*!< HUB_INT (Bitfield-Mask: 0x01)                         */
36912  #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Pos                                (8UL)          /*!< IRQ_LINK (Bit 8)                                      */
36913  #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Msk                                (0x700UL)      /*!< IRQ_LINK (Bitfield-Mask: 0x07)                        */
36914  #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Pos                             (16UL)         /*!< IRQ_MAC_EEE (Bit 16)                                  */
36915  #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Msk                             (0x70000UL)    /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07)                     */
36916  #define R_ETHSW_INT_STAT_ACK_EFP_INT_Pos                                 (27UL)         /*!< EFP_INT (Bit 27)                                      */
36917  #define R_ETHSW_INT_STAT_ACK_EFP_INT_Msk                                 (0x8000000UL)  /*!< EFP_INT (Bitfield-Mask: 0x01)                         */
36918  #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Pos                           (28UL)         /*!< SRCFLT_WD_INT (Bit 28)                                */
36919  #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Msk                           (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01)                   */
36920  #define R_ETHSW_INT_STAT_ACK_TSM_INT_Pos                                 (29UL)         /*!< TSM_INT (Bit 29)                                      */
36921  #define R_ETHSW_INT_STAT_ACK_TSM_INT_Msk                                 (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01)                         */
36922  #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Pos                                (30UL)         /*!< TDMA_INT (Bit 30)                                     */
36923  #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Msk                                (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01)                        */
36924  #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Pos                             (31UL)         /*!< PATTERN_INT (Bit 31)                                  */
36925  #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Msk                             (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01)                     */
36926 /* ======================================================  ATIME_CTRL0  ====================================================== */
36927  #define R_ETHSW_ATIME_CTRL0_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
36928  #define R_ETHSW_ATIME_CTRL0_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
36929  #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Pos                                 (1UL)          /*!< ONE_SHOT (Bit 1)                                      */
36930  #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Msk                                 (0x2UL)        /*!< ONE_SHOT (Bitfield-Mask: 0x01)                        */
36931  #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Pos                           (2UL)          /*!< EVT_OFFSET_ENA (Bit 2)                                */
36932  #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Msk                           (0x4UL)        /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01)                  */
36933  #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Pos                           (4UL)          /*!< EVT_PERIOD_ENA (Bit 4)                                */
36934  #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Msk                           (0x10UL)       /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01)                  */
36935  #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Pos                           (5UL)          /*!< EVT_PERIOD_RST (Bit 5)                                */
36936  #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Msk                           (0x20UL)       /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01)                  */
36937  #define R_ETHSW_ATIME_CTRL0_RESTART_Pos                                  (9UL)          /*!< RESTART (Bit 9)                                       */
36938  #define R_ETHSW_ATIME_CTRL0_RESTART_Msk                                  (0x200UL)      /*!< RESTART (Bitfield-Mask: 0x01)                         */
36939  #define R_ETHSW_ATIME_CTRL0_CAPTURE_Pos                                  (11UL)         /*!< CAPTURE (Bit 11)                                      */
36940  #define R_ETHSW_ATIME_CTRL0_CAPTURE_Msk                                  (0x800UL)      /*!< CAPTURE (Bitfield-Mask: 0x01)                         */
36941  #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Pos                              (12UL)         /*!< CAPTURE_ALL (Bit 12)                                  */
36942  #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Msk                              (0x1000UL)     /*!< CAPTURE_ALL (Bitfield-Mask: 0x01)                     */
36943 /* ======================================================  ATIME_CTRL1  ====================================================== */
36944  #define R_ETHSW_ATIME_CTRL1_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
36945  #define R_ETHSW_ATIME_CTRL1_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
36946  #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Pos                                 (1UL)          /*!< ONE_SHOT (Bit 1)                                      */
36947  #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Msk                                 (0x2UL)        /*!< ONE_SHOT (Bitfield-Mask: 0x01)                        */
36948  #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Pos                           (2UL)          /*!< EVT_OFFSET_ENA (Bit 2)                                */
36949  #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Msk                           (0x4UL)        /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01)                  */
36950  #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Pos                           (4UL)          /*!< EVT_PERIOD_ENA (Bit 4)                                */
36951  #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Msk                           (0x10UL)       /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01)                  */
36952  #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Pos                           (5UL)          /*!< EVT_PERIOD_RST (Bit 5)                                */
36953  #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Msk                           (0x20UL)       /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01)                  */
36954  #define R_ETHSW_ATIME_CTRL1_RESTART_Pos                                  (9UL)          /*!< RESTART (Bit 9)                                       */
36955  #define R_ETHSW_ATIME_CTRL1_RESTART_Msk                                  (0x200UL)      /*!< RESTART (Bitfield-Mask: 0x01)                         */
36956  #define R_ETHSW_ATIME_CTRL1_CAPTURE_Pos                                  (11UL)         /*!< CAPTURE (Bit 11)                                      */
36957  #define R_ETHSW_ATIME_CTRL1_CAPTURE_Msk                                  (0x800UL)      /*!< CAPTURE (Bitfield-Mask: 0x01)                         */
36958  #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Pos                              (12UL)         /*!< CAPTURE_ALL (Bit 12)                                  */
36959  #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Msk                              (0x1000UL)     /*!< CAPTURE_ALL (Bitfield-Mask: 0x01)                     */
36960 /* ========================================================  ATIME0  ========================================================= */
36961  #define R_ETHSW_ATIME0_TIMER_VAL_Pos                                     (0UL)          /*!< TIMER_VAL (Bit 0)                                     */
36962  #define R_ETHSW_ATIME0_TIMER_VAL_Msk                                     (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff)                 */
36963 /* ========================================================  ATIME1  ========================================================= */
36964  #define R_ETHSW_ATIME1_TIMER_VAL_Pos                                     (0UL)          /*!< TIMER_VAL (Bit 0)                                     */
36965  #define R_ETHSW_ATIME1_TIMER_VAL_Msk                                     (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff)                 */
36966 /* =====================================================  ATIME_OFFSET0  ===================================================== */
36967  #define R_ETHSW_ATIME_OFFSET0_OFFSET_Pos                                 (0UL)          /*!< OFFSET (Bit 0)                                        */
36968  #define R_ETHSW_ATIME_OFFSET0_OFFSET_Msk                                 (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff)                    */
36969 /* =====================================================  ATIME_OFFSET1  ===================================================== */
36970  #define R_ETHSW_ATIME_OFFSET1_OFFSET_Pos                                 (0UL)          /*!< OFFSET (Bit 0)                                        */
36971  #define R_ETHSW_ATIME_OFFSET1_OFFSET_Msk                                 (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff)                    */
36972 /* ===================================================  ATIME_EVT_PERIOD0  =================================================== */
36973  #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Pos                             (0UL)          /*!< PERIOD (Bit 0)                                        */
36974  #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Msk                             (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff)                    */
36975 /* ===================================================  ATIME_EVT_PERIOD1  =================================================== */
36976  #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Pos                             (0UL)          /*!< PERIOD (Bit 0)                                        */
36977  #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Msk                             (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff)                    */
36978 /* ======================================================  ATIME_CORR0  ====================================================== */
36979  #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Pos                              (0UL)          /*!< CORR_PERIOD (Bit 0)                                   */
36980  #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Msk                              (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff)               */
36981 /* ======================================================  ATIME_CORR1  ====================================================== */
36982  #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Pos                              (0UL)          /*!< CORR_PERIOD (Bit 0)                                   */
36983  #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Msk                              (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff)               */
36984 /* ======================================================  ATIME_INC0  ======================================================= */
36985  #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Pos                                (0UL)          /*!< CLK_PERIOD (Bit 0)                                    */
36986  #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Msk                                (0x7fUL)       /*!< CLK_PERIOD (Bitfield-Mask: 0x7f)                      */
36987  #define R_ETHSW_ATIME_INC0_CORR_INC_Pos                                  (8UL)          /*!< CORR_INC (Bit 8)                                      */
36988  #define R_ETHSW_ATIME_INC0_CORR_INC_Msk                                  (0x7f00UL)     /*!< CORR_INC (Bitfield-Mask: 0x7f)                        */
36989  #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Pos                             (16UL)         /*!< OFFS_CORR_INC (Bit 16)                                */
36990  #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Msk                             (0x7f0000UL)   /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f)                   */
36991 /* ======================================================  ATIME_INC1  ======================================================= */
36992  #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Pos                                (0UL)          /*!< CLK_PERIOD (Bit 0)                                    */
36993  #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Msk                                (0x7fUL)       /*!< CLK_PERIOD (Bitfield-Mask: 0x7f)                      */
36994  #define R_ETHSW_ATIME_INC1_CORR_INC_Pos                                  (8UL)          /*!< CORR_INC (Bit 8)                                      */
36995  #define R_ETHSW_ATIME_INC1_CORR_INC_Msk                                  (0x7f00UL)     /*!< CORR_INC (Bitfield-Mask: 0x7f)                        */
36996  #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Pos                             (16UL)         /*!< OFFS_CORR_INC (Bit 16)                                */
36997  #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Msk                             (0x7f0000UL)   /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f)                   */
36998 /* ======================================================  ATIME_SEC0  ======================================================= */
36999  #define R_ETHSW_ATIME_SEC0_SEC_TIME_Pos                                  (0UL)          /*!< SEC_TIME (Bit 0)                                      */
37000  #define R_ETHSW_ATIME_SEC0_SEC_TIME_Msk                                  (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff)                  */
37001 /* ======================================================  ATIME_SEC1  ======================================================= */
37002  #define R_ETHSW_ATIME_SEC1_SEC_TIME_Pos                                  (0UL)          /*!< SEC_TIME (Bit 0)                                      */
37003  #define R_ETHSW_ATIME_SEC1_SEC_TIME_Msk                                  (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff)                  */
37004 /* ===================================================  ATIME_OFFS_CORR0  ==================================================== */
37005  #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Pos                       (0UL)          /*!< OFFS_CORR_CNT (Bit 0)                                 */
37006  #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Msk                       (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff)             */
37007 /* ===================================================  ATIME_OFFS_CORR1  ==================================================== */
37008  #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Pos                       (0UL)          /*!< OFFS_CORR_CNT (Bit 0)                                 */
37009  #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Msk                       (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff)             */
37010 /* ====================================================  MDIO_CFG_STATUS  ==================================================== */
37011  #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Pos                                 (0UL)          /*!< BUSY (Bit 0)                                          */
37012  #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Msk                                 (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
37013  #define R_ETHSW_MDIO_CFG_STATUS_READERR_Pos                              (1UL)          /*!< READERR (Bit 1)                                       */
37014  #define R_ETHSW_MDIO_CFG_STATUS_READERR_Msk                              (0x2UL)        /*!< READERR (Bitfield-Mask: 0x01)                         */
37015  #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Pos                                 (2UL)          /*!< HOLD (Bit 2)                                          */
37016  #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Msk                                 (0x1cUL)       /*!< HOLD (Bitfield-Mask: 0x07)                            */
37017  #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Pos                             (5UL)          /*!< DISPREAM (Bit 5)                                      */
37018  #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Msk                             (0x20UL)       /*!< DISPREAM (Bitfield-Mask: 0x01)                        */
37019  #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Pos                               (7UL)          /*!< CLKDIV (Bit 7)                                        */
37020  #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Msk                               (0xff80UL)     /*!< CLKDIV (Bitfield-Mask: 0x1ff)                         */
37021 /* =====================================================  MDIO_COMMAND  ====================================================== */
37022  #define R_ETHSW_MDIO_COMMAND_REGADDR_Pos                                 (0UL)          /*!< REGADDR (Bit 0)                                       */
37023  #define R_ETHSW_MDIO_COMMAND_REGADDR_Msk                                 (0x1fUL)       /*!< REGADDR (Bitfield-Mask: 0x1f)                         */
37024  #define R_ETHSW_MDIO_COMMAND_PHYADDR_Pos                                 (5UL)          /*!< PHYADDR (Bit 5)                                       */
37025  #define R_ETHSW_MDIO_COMMAND_PHYADDR_Msk                                 (0x3e0UL)      /*!< PHYADDR (Bitfield-Mask: 0x1f)                         */
37026  #define R_ETHSW_MDIO_COMMAND_TRANINIT_Pos                                (15UL)         /*!< TRANINIT (Bit 15)                                     */
37027  #define R_ETHSW_MDIO_COMMAND_TRANINIT_Msk                                (0x8000UL)     /*!< TRANINIT (Bitfield-Mask: 0x01)                        */
37028 /* =======================================================  MDIO_DATA  ======================================================= */
37029  #define R_ETHSW_MDIO_DATA_MDIO_DATA_Pos                                  (0UL)          /*!< MDIO_DATA (Bit 0)                                     */
37030  #define R_ETHSW_MDIO_DATA_MDIO_DATA_Msk                                  (0xffffUL)     /*!< MDIO_DATA (Bitfield-Mask: 0xffff)                     */
37031 /* ========================================================  REV_P0  ========================================================= */
37032  #define R_ETHSW_REV_P0_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
37033  #define R_ETHSW_REV_P0_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
37034 /* ========================================================  REV_P1  ========================================================= */
37035  #define R_ETHSW_REV_P1_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
37036  #define R_ETHSW_REV_P1_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
37037 /* ========================================================  REV_P2  ========================================================= */
37038  #define R_ETHSW_REV_P2_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
37039  #define R_ETHSW_REV_P2_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
37040 /* ========================================================  REV_P3  ========================================================= */
37041  #define R_ETHSW_REV_P3_REV_Pos                                           (0UL)          /*!< REV (Bit 0)                                           */
37042  #define R_ETHSW_REV_P3_REV_Msk                                           (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff)                       */
37043 /* ===================================================  COMMAND_CONFIG_P0  =================================================== */
37044  #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
37045  #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
37046  #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
37047  #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
37048  #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
37049  #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
37050  #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
37051  #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
37052  #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
37053  #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
37054  #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
37055  #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
37056  #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
37057  #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
37058  #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
37059  #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
37060  #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
37061  #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
37062  #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
37063  #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
37064  #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
37065  #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
37066  #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
37067  #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
37068  #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
37069  #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
37070  #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
37071  #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
37072  #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
37073  #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
37074  #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
37075  #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
37076  #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
37077  #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
37078  #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
37079  #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
37080 /* ===================================================  COMMAND_CONFIG_P1  =================================================== */
37081  #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
37082  #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
37083  #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
37084  #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
37085  #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
37086  #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
37087  #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
37088  #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
37089  #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
37090  #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
37091  #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
37092  #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
37093  #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
37094  #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
37095  #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
37096  #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
37097  #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
37098  #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
37099  #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
37100  #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
37101  #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
37102  #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
37103  #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
37104  #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
37105  #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
37106  #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
37107  #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
37108  #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
37109  #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
37110  #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
37111  #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
37112  #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
37113  #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
37114  #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
37115  #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
37116  #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
37117 /* ===================================================  COMMAND_CONFIG_P2  =================================================== */
37118  #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
37119  #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
37120  #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
37121  #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
37122  #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
37123  #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
37124  #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
37125  #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
37126  #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
37127  #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
37128  #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
37129  #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
37130  #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
37131  #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
37132  #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
37133  #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
37134  #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
37135  #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
37136  #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
37137  #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
37138  #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
37139  #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
37140  #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
37141  #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
37142  #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
37143  #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
37144  #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
37145  #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
37146  #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
37147  #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
37148  #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
37149  #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
37150  #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
37151  #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
37152  #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
37153  #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
37154 /* ===================================================  COMMAND_CONFIG_P3  =================================================== */
37155  #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Pos                             (0UL)          /*!< TX_ENA (Bit 0)                                        */
37156  #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Msk                             (0x1UL)        /*!< TX_ENA (Bitfield-Mask: 0x01)                          */
37157  #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Pos                             (1UL)          /*!< RX_ENA (Bit 1)                                        */
37158  #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Msk                             (0x2UL)        /*!< RX_ENA (Bitfield-Mask: 0x01)                          */
37159  #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Pos                    (2UL)          /*!< TDMA_PREBUF_DIS (Bit 2)                               */
37160  #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Msk                    (0x4UL)        /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01)                 */
37161  #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Pos                          (3UL)          /*!< ETH_SPEED (Bit 3)                                     */
37162  #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Msk                          (0x8UL)        /*!< ETH_SPEED (Bitfield-Mask: 0x01)                       */
37163  #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Pos                          (4UL)          /*!< PROMIS_EN (Bit 4)                                     */
37164  #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Msk                          (0x10UL)       /*!< PROMIS_EN (Bitfield-Mask: 0x01)                       */
37165  #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Pos                             (5UL)          /*!< PAD_EN (Bit 5)                                        */
37166  #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Msk                             (0x20UL)       /*!< PAD_EN (Bitfield-Mask: 0x01)                          */
37167  #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Pos                          (7UL)          /*!< PAUSE_FWD (Bit 7)                                     */
37168  #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Msk                          (0x80UL)       /*!< PAUSE_FWD (Bitfield-Mask: 0x01)                       */
37169  #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Pos                       (8UL)          /*!< PAUSE_IGNORE (Bit 8)                                  */
37170  #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Msk                       (0x100UL)      /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01)                    */
37171  #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Pos                        (9UL)          /*!< TX_ADDR_INS (Bit 9)                                   */
37172  #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Msk                        (0x200UL)      /*!< TX_ADDR_INS (Bitfield-Mask: 0x01)                     */
37173  #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Pos                             (10UL)         /*!< HD_ENA (Bit 10)                                       */
37174  #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Msk                             (0x400UL)      /*!< HD_ENA (Bitfield-Mask: 0x01)                          */
37175  #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Pos                      (11UL)         /*!< TX_CRC_APPEND (Bit 11)                                */
37176  #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Msk                      (0x800UL)      /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01)                   */
37177  #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Pos                           (13UL)         /*!< SW_RESET (Bit 13)                                     */
37178  #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Msk                           (0x2000UL)     /*!< SW_RESET (Bitfield-Mask: 0x01)                        */
37179  #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Pos                       (23UL)         /*!< CNTL_FRM_ENA (Bit 23)                                 */
37180  #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Msk                       (0x800000UL)   /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01)                    */
37181  #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Pos                        (24UL)         /*!< NO_LGTH_CHK (Bit 24)                                  */
37182  #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Msk                        (0x1000000UL)  /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01)                     */
37183  #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Pos                             (25UL)         /*!< ENA_10 (Bit 25)                                       */
37184  #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Msk                             (0x2000000UL)  /*!< ENA_10 (Bitfield-Mask: 0x01)                          */
37185  #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Pos                        (26UL)         /*!< EFPI_SELECT (Bit 26)                                  */
37186  #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Msk                        (0x4000000UL)  /*!< EFPI_SELECT (Bitfield-Mask: 0x01)                     */
37187  #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Pos                        (27UL)         /*!< TX_TRUNCATE (Bit 27)                                  */
37188  #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Msk                        (0x8000000UL)  /*!< TX_TRUNCATE (Bitfield-Mask: 0x01)                     */
37189  #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Pos                          (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
37190  #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Msk                          (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
37191 /* =====================================================  MAC_ADDR_0_P0  ===================================================== */
37192  #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
37193  #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
37194 /* =====================================================  MAC_ADDR_0_P1  ===================================================== */
37195  #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
37196  #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
37197 /* =====================================================  MAC_ADDR_0_P2  ===================================================== */
37198  #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
37199  #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Msk                               (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff)                  */
37200 /* =====================================================  MAC_ADDR_1_P0  ===================================================== */
37201  #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
37202  #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
37203 /* =====================================================  MAC_ADDR_1_P1  ===================================================== */
37204  #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
37205  #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
37206 /* =====================================================  MAC_ADDR_1_P2  ===================================================== */
37207  #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Pos                               (0UL)          /*!< MAC_ADDR (Bit 0)                                      */
37208  #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Msk                               (0xffffUL)     /*!< MAC_ADDR (Bitfield-Mask: 0xffff)                      */
37209 /* =====================================================  FRM_LENGTH_P0  ===================================================== */
37210  #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
37211  #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
37212 /* =====================================================  FRM_LENGTH_P1  ===================================================== */
37213  #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
37214  #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
37215 /* =====================================================  FRM_LENGTH_P2  ===================================================== */
37216  #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
37217  #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
37218 /* =====================================================  FRM_LENGTH_P3  ===================================================== */
37219  #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Pos                             (0UL)          /*!< FRM_LENGTH (Bit 0)                                    */
37220  #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Msk                             (0x3fffUL)     /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff)                    */
37221 /* ====================================================  PAUSE_QUANT_P0  ===================================================== */
37222  #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
37223  #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
37224 /* ====================================================  PAUSE_QUANT_P1  ===================================================== */
37225  #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
37226  #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
37227 /* ====================================================  PAUSE_QUANT_P2  ===================================================== */
37228  #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
37229  #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
37230 /* ====================================================  PAUSE_QUANT_P3  ===================================================== */
37231  #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Pos                           (0UL)          /*!< PAUSE_QUANT (Bit 0)                                   */
37232  #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Msk                           (0xffffUL)     /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff)                   */
37233 /* ===================================================  MAC_LINK_QTRIG_P0  =================================================== */
37234  #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
37235  #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
37236  #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
37237  #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
37238  #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
37239  #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
37240  #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
37241  #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
37242  #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
37243  #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
37244  #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
37245  #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
37246 /* ===================================================  MAC_LINK_QTRIG_P1  =================================================== */
37247  #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
37248  #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
37249  #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
37250  #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
37251  #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
37252  #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
37253  #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
37254  #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
37255  #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
37256  #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
37257  #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
37258  #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
37259 /* ===================================================  MAC_LINK_QTRIG_P2  =================================================== */
37260  #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Pos                          (0UL)          /*!< PORT_MASK (Bit 0)                                     */
37261  #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Msk                          (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
37262  #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Pos                         (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
37263  #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Msk                         (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
37264  #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Pos                          (28UL)         /*!< TRIGGERED (Bit 28)                                    */
37265  #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Msk                          (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01)                       */
37266  #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Pos                           (29UL)         /*!< DLR_MODE (Bit 29)                                     */
37267  #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Msk                           (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01)                        */
37268  #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Pos                               (30UL)         /*!< MODE (Bit 30)                                         */
37269  #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Msk                               (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01)                            */
37270  #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Pos                             (31UL)         /*!< ENABLE (Bit 31)                                       */
37271  #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Msk                             (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01)                          */
37272 /* =================================================  PTPCLOCKIDENTITY1_P0  ================================================== */
37273  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
37274  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
37275  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
37276  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
37277  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
37278  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
37279  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
37280  #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
37281 /* =================================================  PTPCLOCKIDENTITY1_P1  ================================================== */
37282  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
37283  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
37284  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
37285  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
37286  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
37287  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
37288  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
37289  #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
37290 /* =================================================  PTPCLOCKIDENTITY1_P2  ================================================== */
37291  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Pos                   (0UL)          /*!< CLK_IDENTITY0 (Bit 0)                                 */
37292  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Msk                   (0xffUL)       /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff)                   */
37293  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Pos                   (8UL)          /*!< CLK_IDENTITY1 (Bit 8)                                 */
37294  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Msk                   (0xff00UL)     /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff)                   */
37295  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Pos                   (16UL)         /*!< CLK_IDENTITY2 (Bit 16)                                */
37296  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff)                   */
37297  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Pos                   (24UL)         /*!< CLK_IDENTITY3 (Bit 24)                                */
37298  #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Msk                   (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff)                 */
37299 /* =================================================  PTPCLOCKIDENTITY2_P0  ================================================== */
37300  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
37301  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
37302  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
37303  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
37304  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
37305  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
37306  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
37307  #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
37308 /* =================================================  PTPCLOCKIDENTITY2_P1  ================================================== */
37309  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
37310  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
37311  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
37312  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
37313  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
37314  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
37315  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
37316  #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
37317 /* =================================================  PTPCLOCKIDENTITY2_P2  ================================================== */
37318  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Pos                   (0UL)          /*!< CLK_IDENTITY4 (Bit 0)                                 */
37319  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Msk                   (0xffUL)       /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff)                   */
37320  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Pos                   (8UL)          /*!< CLK_IDENTITY5 (Bit 8)                                 */
37321  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Msk                   (0xff00UL)     /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff)                   */
37322  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Pos                   (16UL)         /*!< CLK_IDENTITY6 (Bit 16)                                */
37323  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Msk                   (0xff0000UL)   /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff)                   */
37324  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Pos                   (24UL)         /*!< CLK_IDENTITY7 (Bit 24)                                */
37325  #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Msk                   (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff)                 */
37326 /* ==================================================  PTPAUTORESPONSE_P0  =================================================== */
37327  #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
37328  #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
37329  #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
37330  #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
37331  #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
37332  #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
37333  #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
37334  #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
37335 /* ==================================================  PTPAUTORESPONSE_P1  =================================================== */
37336  #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
37337  #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
37338  #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
37339  #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
37340  #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
37341  #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
37342  #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
37343  #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
37344 /* ==================================================  PTPAUTORESPONSE_P2  =================================================== */
37345  #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Pos                           (0UL)          /*!< ARSP_EN (Bit 0)                                       */
37346  #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Msk                           (0x1UL)        /*!< ARSP_EN (Bitfield-Mask: 0x01)                         */
37347  #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Pos                           (1UL)          /*!< D_TIMER (Bit 1)                                       */
37348  #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Msk                           (0x2UL)        /*!< D_TIMER (Bitfield-Mask: 0x01)                         */
37349  #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Pos                          (16UL)         /*!< PORTNUM1 (Bit 16)                                     */
37350  #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Msk                          (0xff0000UL)   /*!< PORTNUM1 (Bitfield-Mask: 0xff)                        */
37351  #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Pos                          (24UL)         /*!< PORTNUM0 (Bit 24)                                     */
37352  #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Msk                          (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff)                        */
37353 /* =======================================================  STATUS_P0  ======================================================= */
37354  #define R_ETHSW_STATUS_P0_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
37355  #define R_ETHSW_STATUS_P0_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
37356  #define R_ETHSW_STATUS_P0_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
37357  #define R_ETHSW_STATUS_P0_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
37358  #define R_ETHSW_STATUS_P0_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
37359  #define R_ETHSW_STATUS_P0_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
37360  #define R_ETHSW_STATUS_P0_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
37361  #define R_ETHSW_STATUS_P0_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
37362  #define R_ETHSW_STATUS_P0_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
37363  #define R_ETHSW_STATUS_P0_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
37364  #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
37365  #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
37366 /* =======================================================  STATUS_P1  ======================================================= */
37367  #define R_ETHSW_STATUS_P1_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
37368  #define R_ETHSW_STATUS_P1_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
37369  #define R_ETHSW_STATUS_P1_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
37370  #define R_ETHSW_STATUS_P1_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
37371  #define R_ETHSW_STATUS_P1_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
37372  #define R_ETHSW_STATUS_P1_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
37373  #define R_ETHSW_STATUS_P1_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
37374  #define R_ETHSW_STATUS_P1_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
37375  #define R_ETHSW_STATUS_P1_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
37376  #define R_ETHSW_STATUS_P1_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
37377  #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
37378  #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
37379 /* =======================================================  STATUS_P2  ======================================================= */
37380  #define R_ETHSW_STATUS_P2_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
37381  #define R_ETHSW_STATUS_P2_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
37382  #define R_ETHSW_STATUS_P2_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
37383  #define R_ETHSW_STATUS_P2_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
37384  #define R_ETHSW_STATUS_P2_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
37385  #define R_ETHSW_STATUS_P2_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
37386  #define R_ETHSW_STATUS_P2_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
37387  #define R_ETHSW_STATUS_P2_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
37388  #define R_ETHSW_STATUS_P2_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
37389  #define R_ETHSW_STATUS_P2_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
37390  #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
37391  #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
37392 /* =======================================================  STATUS_P3  ======================================================= */
37393  #define R_ETHSW_STATUS_P3_PHYSPEED_Pos                                   (0UL)          /*!< PHYSPEED (Bit 0)                                      */
37394  #define R_ETHSW_STATUS_P3_PHYSPEED_Msk                                   (0x3UL)        /*!< PHYSPEED (Bitfield-Mask: 0x03)                        */
37395  #define R_ETHSW_STATUS_P3_PHYLINK_Pos                                    (2UL)          /*!< PHYLINK (Bit 2)                                       */
37396  #define R_ETHSW_STATUS_P3_PHYLINK_Msk                                    (0x4UL)        /*!< PHYLINK (Bitfield-Mask: 0x01)                         */
37397  #define R_ETHSW_STATUS_P3_PHYDUPLEX_Pos                                  (3UL)          /*!< PHYDUPLEX (Bit 3)                                     */
37398  #define R_ETHSW_STATUS_P3_PHYDUPLEX_Msk                                  (0x8UL)        /*!< PHYDUPLEX (Bitfield-Mask: 0x01)                       */
37399  #define R_ETHSW_STATUS_P3_TX_UNDFLW_Pos                                  (4UL)          /*!< TX_UNDFLW (Bit 4)                                     */
37400  #define R_ETHSW_STATUS_P3_TX_UNDFLW_Msk                                  (0x10UL)       /*!< TX_UNDFLW (Bitfield-Mask: 0x01)                       */
37401  #define R_ETHSW_STATUS_P3_LK_DST_ERR_Pos                                 (5UL)          /*!< LK_DST_ERR (Bit 5)                                    */
37402  #define R_ETHSW_STATUS_P3_LK_DST_ERR_Msk                                 (0x20UL)       /*!< LK_DST_ERR (Bitfield-Mask: 0x01)                      */
37403  #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Pos                                (6UL)          /*!< BR_VERIF_ST (Bit 6)                                   */
37404  #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Msk                                (0x1c0UL)      /*!< BR_VERIF_ST (Bitfield-Mask: 0x07)                     */
37405 /* ===================================================  TX_IPG_LENGTH_P0  ==================================================== */
37406  #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
37407  #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
37408  #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
37409  #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
37410 /* ===================================================  TX_IPG_LENGTH_P1  ==================================================== */
37411  #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
37412  #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
37413  #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
37414  #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
37415 /* ===================================================  TX_IPG_LENGTH_P2  ==================================================== */
37416  #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
37417  #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
37418  #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
37419  #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
37420 /* ===================================================  TX_IPG_LENGTH_P3  ==================================================== */
37421  #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Pos                       (0UL)          /*!< TX_IPG_LENGTH (Bit 0)                                 */
37422  #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Msk                       (0x1fUL)       /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f)                   */
37423  #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Pos                          (16UL)         /*!< MINRTC3GAP (Bit 16)                                   */
37424  #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Msk                          (0x1f0000UL)   /*!< MINRTC3GAP (Bitfield-Mask: 0x1f)                      */
37425 /* ====================================================  EEE_CTL_STAT_P0  ==================================================== */
37426  #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
37427  #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
37428  #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
37429  #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
37430  #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
37431  #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
37432  #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
37433  #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
37434  #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
37435  #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
37436  #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
37437  #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
37438  #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
37439  #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
37440  #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
37441  #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
37442  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
37443  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
37444  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
37445  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
37446  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
37447  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
37448  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
37449  #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
37450 /* ====================================================  EEE_CTL_STAT_P1  ==================================================== */
37451  #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
37452  #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
37453  #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
37454  #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
37455  #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
37456  #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
37457  #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
37458  #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
37459  #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
37460  #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
37461  #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
37462  #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
37463  #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
37464  #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
37465  #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
37466  #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
37467  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
37468  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
37469  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
37470  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
37471  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
37472  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
37473  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
37474  #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
37475 /* ====================================================  EEE_CTL_STAT_P2  ==================================================== */
37476  #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Pos                             (0UL)          /*!< EEE_AUTO (Bit 0)                                      */
37477  #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Msk                             (0x1UL)        /*!< EEE_AUTO (Bitfield-Mask: 0x01)                        */
37478  #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Pos                              (1UL)          /*!< LPI_REQ (Bit 1)                                       */
37479  #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Msk                              (0x2UL)        /*!< LPI_REQ (Bitfield-Mask: 0x01)                         */
37480  #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Pos                           (2UL)          /*!< LPI_TXHOLD (Bit 2)                                    */
37481  #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Msk                           (0x4UL)        /*!< LPI_TXHOLD (Bitfield-Mask: 0x01)                      */
37482  #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Pos                           (8UL)          /*!< ST_LPI_REQ (Bit 8)                                    */
37483  #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Msk                           (0x100UL)      /*!< ST_LPI_REQ (Bitfield-Mask: 0x01)                      */
37484  #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Pos                        (9UL)          /*!< ST_LPI_TXHOLD (Bit 9)                                 */
37485  #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Msk                        (0x200UL)      /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01)                   */
37486  #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Pos                            (10UL)         /*!< ST_TXBUSY (Bit 10)                                    */
37487  #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Msk                            (0x400UL)      /*!< ST_TXBUSY (Bitfield-Mask: 0x01)                       */
37488  #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Pos                           (11UL)         /*!< ST_TXAVAIL (Bit 11)                                   */
37489  #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Msk                           (0x800UL)      /*!< ST_TXAVAIL (Bitfield-Mask: 0x01)                      */
37490  #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Pos                           (12UL)         /*!< ST_LPI_IND (Bit 12)                                   */
37491  #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Msk                           (0x1000UL)     /*!< ST_LPI_IND (Bitfield-Mask: 0x01)                      */
37492  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Pos                         (16UL)         /*!< STLH_LPI_REQ (Bit 16)                                 */
37493  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Msk                         (0x10000UL)    /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01)                    */
37494  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Pos                      (17UL)         /*!< STLH_LPI_TXHOLD (Bit 17)                              */
37495  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Msk                      (0x20000UL)    /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01)                 */
37496  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Pos                          (18UL)         /*!< STLH_TXBUSY (Bit 18)                                  */
37497  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Msk                          (0x40000UL)    /*!< STLH_TXBUSY (Bitfield-Mask: 0x01)                     */
37498  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Pos                         (20UL)         /*!< STLH_LPI_IND (Bit 20)                                 */
37499  #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Msk                         (0x100000UL)   /*!< STLH_LPI_IND (Bitfield-Mask: 0x01)                    */
37500 /* ===================================================  EEE_IDLE_TIME_P0  ==================================================== */
37501  #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
37502  #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
37503 /* ===================================================  EEE_IDLE_TIME_P1  ==================================================== */
37504  #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
37505  #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
37506 /* ===================================================  EEE_IDLE_TIME_P2  ==================================================== */
37507  #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Pos                       (0UL)          /*!< EEE_IDLE_TIME (Bit 0)                                 */
37508  #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Msk                       (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff)             */
37509 /* ===================================================  EEE_TWSYS_TIME_P0  =================================================== */
37510  #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
37511  #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
37512 /* ===================================================  EEE_TWSYS_TIME_P1  =================================================== */
37513  #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
37514  #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
37515 /* ===================================================  EEE_TWSYS_TIME_P2  =================================================== */
37516  #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Pos                      (0UL)          /*!< EEE_WKUP_TIME (Bit 0)                                 */
37517  #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Msk                      (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff)             */
37518 /* =====================================================  IDLE_SLOPE_P0  ===================================================== */
37519  #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
37520  #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
37521 /* =====================================================  IDLE_SLOPE_P1  ===================================================== */
37522  #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
37523  #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
37524 /* =====================================================  IDLE_SLOPE_P2  ===================================================== */
37525  #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
37526  #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
37527 /* =====================================================  IDLE_SLOPE_P3  ===================================================== */
37528  #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Pos                             (0UL)          /*!< IDLE_SLOPE (Bit 0)                                    */
37529  #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Msk                             (0x7ffUL)      /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff)                     */
37530 /* ======================================================  CT_DELAY_P0  ====================================================== */
37531  #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
37532  #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
37533 /* ======================================================  CT_DELAY_P1  ====================================================== */
37534  #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
37535  #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
37536 /* ======================================================  CT_DELAY_P2  ====================================================== */
37537  #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Pos                                 (0UL)          /*!< CT_DELAY (Bit 0)                                      */
37538  #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Msk                                 (0x1ffUL)      /*!< CT_DELAY (Bitfield-Mask: 0x1ff)                       */
37539 /* =====================================================  BR_CONTROL_P0  ===================================================== */
37540  #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
37541  #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
37542  #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
37543  #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
37544  #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
37545  #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
37546  #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
37547  #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
37548  #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
37549  #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
37550  #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
37551  #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
37552  #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
37553  #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
37554  #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
37555  #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
37556  #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
37557  #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
37558  #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
37559  #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
37560 /* =====================================================  BR_CONTROL_P1  ===================================================== */
37561  #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
37562  #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
37563  #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
37564  #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
37565  #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
37566  #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
37567  #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
37568  #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
37569  #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
37570  #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
37571  #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
37572  #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
37573  #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
37574  #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
37575  #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
37576  #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
37577  #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
37578  #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
37579  #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
37580  #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
37581 /* =====================================================  BR_CONTROL_P2  ===================================================== */
37582  #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Pos                            (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
37583  #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Msk                            (0x1UL)        /*!< PREEMPT_ENA (Bitfield-Mask: 0x01)                     */
37584  #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Pos                             (1UL)          /*!< VERIFY_DIS (Bit 1)                                    */
37585  #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Msk                             (0x2UL)        /*!< VERIFY_DIS (Bitfield-Mask: 0x01)                      */
37586  #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Pos                           (2UL)          /*!< RESPONSE_DIS (Bit 2)                                  */
37587  #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Msk                           (0x4UL)        /*!< RESPONSE_DIS (Bitfield-Mask: 0x01)                    */
37588  #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Pos                            (4UL)          /*!< ADDFRAGSIZE (Bit 4)                                   */
37589  #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Msk                            (0x30UL)       /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03)                     */
37590  #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Pos                         (8UL)          /*!< TX_VERIFY_TIME (Bit 8)                                */
37591  #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Msk                         (0x7f00UL)     /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f)                  */
37592  #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Pos                          (16UL)         /*!< RX_STRICT_PRE (Bit 16)                                */
37593  #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Msk                          (0x10000UL)    /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01)                   */
37594  #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Pos                          (17UL)         /*!< RX_BR_SMD_DIS (Bit 17)                                */
37595  #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Msk                          (0x20000UL)    /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01)                   */
37596  #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Pos                       (18UL)         /*!< RX_STRICT_BR_CTL (Bit 18)                             */
37597  #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Msk                       (0x40000UL)    /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01)                */
37598  #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Pos                            (19UL)         /*!< TX_MCRC_INV (Bit 19)                                  */
37599  #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Msk                            (0x80000UL)    /*!< TX_MCRC_INV (Bitfield-Mask: 0x01)                     */
37600  #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Pos                            (20UL)         /*!< RX_MCRC_INV (Bit 20)                                  */
37601  #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Msk                            (0x100000UL)   /*!< RX_MCRC_INV (Bitfield-Mask: 0x01)                     */
37602 /* ================================================  AFRAMESTRANSMITTEDOK_P0  ================================================ */
37603  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
37604  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
37605 /* ================================================  AFRAMESTRANSMITTEDOK_P1  ================================================ */
37606  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
37607  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
37608 /* ================================================  AFRAMESTRANSMITTEDOK_P2  ================================================ */
37609  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
37610  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
37611 /* ================================================  AFRAMESTRANSMITTEDOK_P3  ================================================ */
37612  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Pos                 (0UL)          /*!< TXVALIDCOUNT (Bit 0)                                  */
37613  #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Msk                 (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff)          */
37614 /* =================================================  AFRAMESRECEIVEDOK_P0  ================================================== */
37615  #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
37616  #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
37617 /* =================================================  AFRAMESRECEIVEDOK_P1  ================================================== */
37618  #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
37619  #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
37620 /* =================================================  AFRAMESRECEIVEDOK_P2  ================================================== */
37621  #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
37622  #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
37623 /* =================================================  AFRAMESRECEIVEDOK_P3  ================================================== */
37624  #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Pos                    (0UL)          /*!< RXVALIDCOUNT (Bit 0)                                  */
37625  #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Msk                    (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff)             */
37626 /* =============================================  AFRAMECHECKSEQUENCEERRORS_P0  ============================================== */
37627  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
37628  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
37629 /* =============================================  AFRAMECHECKSEQUENCEERRORS_P1  ============================================== */
37630  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
37631  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
37632 /* =============================================  AFRAMECHECKSEQUENCEERRORS_P2  ============================================== */
37633  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
37634  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
37635 /* =============================================  AFRAMECHECKSEQUENCEERRORS_P3  ============================================== */
37636  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Pos             (0UL)          /*!< FCSERRCOUNT (Bit 0)                                   */
37637  #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Msk             (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff)       */
37638 /* ==================================================  AALIGNMENTERRORS_P0  ================================================== */
37639  #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
37640  #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
37641 /* ==================================================  AALIGNMENTERRORS_P1  ================================================== */
37642  #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
37643  #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
37644 /* ==================================================  AALIGNMENTERRORS_P2  ================================================== */
37645  #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
37646  #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
37647 /* ==================================================  AALIGNMENTERRORS_P3  ================================================== */
37648  #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Pos                     (0UL)          /*!< ALGNERRCOUNT (Bit 0)                                  */
37649  #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Msk                     (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff)              */
37650 /* ================================================  AOCTETSTRANSMITTEDOK_P0  ================================================ */
37651  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
37652  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
37653 /* ================================================  AOCTETSTRANSMITTEDOK_P1  ================================================ */
37654  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
37655  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
37656 /* ================================================  AOCTETSTRANSMITTEDOK_P2  ================================================ */
37657  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
37658  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
37659 /* ================================================  AOCTETSTRANSMITTEDOK_P3  ================================================ */
37660  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Pos                (0UL)          /*!< TXVALIDOCTETS (Bit 0)                                 */
37661  #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Msk                (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff)        */
37662 /* =================================================  AOCTETSRECEIVEDOK_P0  ================================================== */
37663  #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
37664  #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
37665 /* =================================================  AOCTETSRECEIVEDOK_P1  ================================================== */
37666  #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
37667  #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
37668 /* =================================================  AOCTETSRECEIVEDOK_P2  ================================================== */
37669  #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
37670  #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
37671 /* =================================================  AOCTETSRECEIVEDOK_P3  ================================================== */
37672  #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Pos                   (0UL)          /*!< RXVALIDOCTETS (Bit 0)                                 */
37673  #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Msk                   (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff)           */
37674 /* ===============================================  ATXPAUSEMACCTRLFRAMES_P0  ================================================ */
37675  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
37676  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37677 /* ===============================================  ATXPAUSEMACCTRLFRAMES_P1  ================================================ */
37678  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
37679  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37680 /* ===============================================  ATXPAUSEMACCTRLFRAMES_P2  ================================================ */
37681  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
37682  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37683 /* ===============================================  ATXPAUSEMACCTRLFRAMES_P3  ================================================ */
37684  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Pos                (0UL)          /*!< TXPAUSECOUNT (Bit 0)                                  */
37685  #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Msk                (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37686 /* ===============================================  ARXPAUSEMACCTRLFRAMES_P0  ================================================ */
37687  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
37688  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37689 /* ===============================================  ARXPAUSEMACCTRLFRAMES_P1  ================================================ */
37690  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
37691  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37692 /* ===============================================  ARXPAUSEMACCTRLFRAMES_P2  ================================================ */
37693  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
37694  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37695 /* ===============================================  ARXPAUSEMACCTRLFRAMES_P3  ================================================ */
37696  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Pos                (0UL)          /*!< RXPAUSECOUNT (Bit 0)                                  */
37697  #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Msk                (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff)         */
37698 /* =====================================================  IFINERRORS_P0  ===================================================== */
37699  #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
37700  #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
37701 /* =====================================================  IFINERRORS_P1  ===================================================== */
37702  #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
37703  #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
37704 /* =====================================================  IFINERRORS_P2  ===================================================== */
37705  #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
37706  #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
37707 /* =====================================================  IFINERRORS_P3  ===================================================== */
37708  #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Pos                             (0UL)          /*!< INERRCOUNT (Bit 0)                                    */
37709  #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Msk                             (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff)                */
37710 /* ====================================================  IFOUTERRORS_P0  ===================================================== */
37711  #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
37712  #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
37713 /* ====================================================  IFOUTERRORS_P1  ===================================================== */
37714  #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
37715  #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
37716 /* ====================================================  IFOUTERRORS_P2  ===================================================== */
37717  #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
37718  #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
37719 /* ====================================================  IFOUTERRORS_P3  ===================================================== */
37720  #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Pos                           (0UL)          /*!< OUTERRCOUNT (Bit 0)                                   */
37721  #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Msk                           (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff)               */
37722 /* ===================================================  IFINUCASTPKTS_P0  ==================================================== */
37723  #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
37724  #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37725 /* ===================================================  IFINUCASTPKTS_P1  ==================================================== */
37726  #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
37727  #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37728 /* ===================================================  IFINUCASTPKTS_P2  ==================================================== */
37729  #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
37730  #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37731 /* ===================================================  IFINUCASTPKTS_P3  ==================================================== */
37732  #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Pos                        (0UL)          /*!< RXUCASTCOUNT (Bit 0)                                  */
37733  #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Msk                        (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37734 /* =================================================  IFINMULTICASTPKTS_P0  ================================================== */
37735  #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
37736  #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37737 /* =================================================  IFINMULTICASTPKTS_P1  ================================================== */
37738  #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
37739  #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37740 /* =================================================  IFINMULTICASTPKTS_P2  ================================================== */
37741  #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
37742  #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37743 /* =================================================  IFINMULTICASTPKTS_P3  ================================================== */
37744  #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Pos                    (0UL)          /*!< RXMCASTCOUNT (Bit 0)                                  */
37745  #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37746 /* =================================================  IFINBROADCASTPKTS_P0  ================================================== */
37747  #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
37748  #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37749 /* =================================================  IFINBROADCASTPKTS_P1  ================================================== */
37750  #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
37751  #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37752 /* =================================================  IFINBROADCASTPKTS_P2  ================================================== */
37753  #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
37754  #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37755 /* =================================================  IFINBROADCASTPKTS_P3  ================================================== */
37756  #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Pos                    (0UL)          /*!< RXBCASTCOUNT (Bit 0)                                  */
37757  #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Msk                    (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff)             */
37758 /* ===================================================  IFOUTDISCARDS_P0  ==================================================== */
37759  #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
37760  #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
37761 /* ===================================================  IFOUTDISCARDS_P1  ==================================================== */
37762  #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
37763  #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
37764 /* ===================================================  IFOUTDISCARDS_P2  ==================================================== */
37765  #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
37766  #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
37767 /* ===================================================  IFOUTDISCARDS_P3  ==================================================== */
37768  #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Pos                         (0UL)          /*!< DISCOBCOUNT (Bit 0)                                   */
37769  #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Msk                         (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff)               */
37770 /* ===================================================  IFOUTUCASTPKTS_P0  =================================================== */
37771  #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
37772  #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37773 /* ===================================================  IFOUTUCASTPKTS_P1  =================================================== */
37774  #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
37775  #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37776 /* ===================================================  IFOUTUCASTPKTS_P2  =================================================== */
37777  #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
37778  #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37779 /* ===================================================  IFOUTUCASTPKTS_P3  =================================================== */
37780  #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Pos                       (0UL)          /*!< TXUCASTCOUNT (Bit 0)                                  */
37781  #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Msk                       (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff)              */
37782 /* =================================================  IFOUTMULTICASTPKTS_P0  ================================================= */
37783  #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
37784  #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37785 /* =================================================  IFOUTMULTICASTPKTS_P1  ================================================= */
37786  #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
37787  #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37788 /* =================================================  IFOUTMULTICASTPKTS_P2  ================================================= */
37789  #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
37790  #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37791 /* =================================================  IFOUTMULTICASTPKTS_P3  ================================================= */
37792  #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Pos                   (0UL)          /*!< TXMCASTCOUNT (Bit 0)                                  */
37793  #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37794 /* =================================================  IFOUTBROADCASTPKTS_P0  ================================================= */
37795  #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
37796  #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37797 /* =================================================  IFOUTBROADCASTPKTS_P1  ================================================= */
37798  #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
37799  #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37800 /* =================================================  IFOUTBROADCASTPKTS_P2  ================================================= */
37801  #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
37802  #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37803 /* =================================================  IFOUTBROADCASTPKTS_P3  ================================================= */
37804  #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Pos                   (0UL)          /*!< TXBCASTCOUNT (Bit 0)                                  */
37805  #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Msk                   (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff)            */
37806 /* ================================================  ETHERSTATSDROPEVENTS_P0  ================================================ */
37807  #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
37808  #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
37809 /* ================================================  ETHERSTATSDROPEVENTS_P1  ================================================ */
37810  #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
37811  #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
37812 /* ================================================  ETHERSTATSDROPEVENTS_P2  ================================================ */
37813  #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
37814  #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
37815 /* ================================================  ETHERSTATSDROPEVENTS_P3  ================================================ */
37816  #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Pos                    (0UL)          /*!< DROPCOUNT (Bit 0)                                     */
37817  #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Msk                    (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff)                */
37818 /* ==================================================  ETHERSTATSOCTETS_P0  ================================================== */
37819  #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
37820  #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
37821 /* ==================================================  ETHERSTATSOCTETS_P1  ================================================== */
37822  #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
37823  #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
37824 /* ==================================================  ETHERSTATSOCTETS_P2  ================================================== */
37825  #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
37826  #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
37827 /* ==================================================  ETHERSTATSOCTETS_P3  ================================================== */
37828  #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Pos                        (0UL)          /*!< ALLOCTETS (Bit 0)                                     */
37829  #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Msk                        (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff)                 */
37830 /* ===================================================  ETHERSTATSPKTS_P0  =================================================== */
37831  #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
37832  #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
37833 /* ===================================================  ETHERSTATSPKTS_P1  =================================================== */
37834  #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
37835  #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
37836 /* ===================================================  ETHERSTATSPKTS_P2  =================================================== */
37837  #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
37838  #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
37839 /* ===================================================  ETHERSTATSPKTS_P3  =================================================== */
37840  #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Pos                           (0UL)          /*!< ALLCOUNT (Bit 0)                                      */
37841  #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Msk                           (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff)                  */
37842 /* ==============================================  ETHERSTATSUNDERSIZEPKTS_P0  =============================================== */
37843  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
37844  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
37845 /* ==============================================  ETHERSTATSUNDERSIZEPKTS_P1  =============================================== */
37846  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
37847  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
37848 /* ==============================================  ETHERSTATSUNDERSIZEPKTS_P2  =============================================== */
37849  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
37850  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
37851 /* ==============================================  ETHERSTATSUNDERSIZEPKTS_P3  =============================================== */
37852  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Pos              (0UL)          /*!< TOOSHRTCOUNT (Bit 0)                                  */
37853  #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Msk              (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff)       */
37854 /* ===============================================  ETHERSTATSOVERSIZEPKTS_P0  =============================================== */
37855  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
37856  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
37857 /* ===============================================  ETHERSTATSOVERSIZEPKTS_P1  =============================================== */
37858  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
37859  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
37860 /* ===============================================  ETHERSTATSOVERSIZEPKTS_P2  =============================================== */
37861  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
37862  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
37863 /* ===============================================  ETHERSTATSOVERSIZEPKTS_P3  =============================================== */
37864  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Pos               (0UL)          /*!< TOOLONGCOUNT (Bit 0)                                  */
37865  #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Msk               (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff)        */
37866 /* ===============================================  ETHERSTATSPKTS64OCTETS_P0  =============================================== */
37867  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
37868  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
37869 /* ===============================================  ETHERSTATSPKTS64OCTETS_P1  =============================================== */
37870  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
37871  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
37872 /* ===============================================  ETHERSTATSPKTS64OCTETS_P2  =============================================== */
37873  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
37874  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
37875 /* ===============================================  ETHERSTATSPKTS64OCTETS_P3  =============================================== */
37876  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Pos                   (0UL)          /*!< OCTCNT64 (Bit 0)                                      */
37877  #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Msk                   (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff)                */
37878 /* ============================================  ETHERSTATSPKTS65TO127OCTETS_P0  ============================================= */
37879  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
37880  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
37881 /* ============================================  ETHERSTATSPKTS65TO127OCTETS_P1  ============================================= */
37882  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
37883  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
37884 /* ============================================  ETHERSTATSPKTS65TO127OCTETS_P2  ============================================= */
37885  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
37886  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
37887 /* ============================================  ETHERSTATSPKTS65TO127OCTETS_P3  ============================================= */
37888  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Pos          (0UL)          /*!< OCTCNT65T127 (Bit 0)                                */
37889  #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Msk          (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff)   */
37890 /* ============================================  ETHERSTATSPKTS128TO255OCTETS_P0  ============================================ */
37891  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
37892  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
37893 /* ============================================  ETHERSTATSPKTS128TO255OCTETS_P1  ============================================ */
37894  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
37895  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
37896 /* ============================================  ETHERSTATSPKTS128TO255OCTETS_P2  ============================================ */
37897  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
37898  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
37899 /* ============================================  ETHERSTATSPKTS128TO255OCTETS_P3  ============================================ */
37900  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Pos        (0UL)          /*!< OCTCNT128T255 (Bit 0)                             */
37901  #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Msk        (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */
37902 /* ============================================  ETHERSTATSPKTS256TO511OCTETS_P0  ============================================ */
37903  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
37904  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
37905 /* ============================================  ETHERSTATSPKTS256TO511OCTETS_P1  ============================================ */
37906  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
37907  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
37908 /* ============================================  ETHERSTATSPKTS256TO511OCTETS_P2  ============================================ */
37909  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
37910  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
37911 /* ============================================  ETHERSTATSPKTS256TO511OCTETS_P3  ============================================ */
37912  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Pos        (0UL)          /*!< OCTCNT256T511 (Bit 0)                             */
37913  #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Msk        (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */
37914 /* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P0  ============================================ */
37915  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
37916  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
37917 /* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P1  ============================================ */
37918  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
37919  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
37920 /* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P2  ============================================ */
37921  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
37922  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
37923 /* ===========================================  ETHERSTATSPKTS512TO1023OCTETS_P3  ============================================ */
37924  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Pos      (0UL)          /*!< OCTCNT512T1023 (Bit 0)                          */
37925  #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Msk      (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */
37926 /* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P0  =========================================== */
37927  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
37928  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
37929 /* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P1  =========================================== */
37930  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
37931  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
37932 /* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P2  =========================================== */
37933  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
37934  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
37935 /* ===========================================  ETHERSTATSPKTS1024TO1518OCTETS_P3  =========================================== */
37936  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Pos    (0UL)          /*!< OCTCNT1024T1518 (Bit 0)                       */
37937  #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Msk    (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */
37938 /* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P0  ============================================= */
37939  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
37940  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
37941 /* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P1  ============================================= */
37942  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
37943  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
37944 /* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P2  ============================================= */
37945  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
37946  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
37947 /* ============================================  ETHERSTATSPKTS1519TOXOCTETS_P3  ============================================= */
37948  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Pos          (0UL)          /*!< OCTCNT1519TX (Bit 0)                                */
37949  #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Msk          (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff)   */
37950 /* =================================================  ETHERSTATSJABBERS_P0  ================================================== */
37951  #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
37952  #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
37953 /* =================================================  ETHERSTATSJABBERS_P1  ================================================== */
37954  #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
37955  #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
37956 /* =================================================  ETHERSTATSJABBERS_P2  ================================================== */
37957  #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
37958  #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
37959 /* =================================================  ETHERSTATSJABBERS_P3  ================================================== */
37960  #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Pos                     (0UL)          /*!< JABBERCOUNT (Bit 0)                                   */
37961  #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Msk                     (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff)               */
37962 /* ================================================  ETHERSTATSFRAGMENTS_P0  ================================================= */
37963  #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
37964  #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
37965 /* ================================================  ETHERSTATSFRAGMENTS_P1  ================================================= */
37966  #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
37967  #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
37968 /* ================================================  ETHERSTATSFRAGMENTS_P2  ================================================= */
37969  #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
37970  #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
37971 /* ================================================  ETHERSTATSFRAGMENTS_P3  ================================================= */
37972  #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Pos                     (0UL)          /*!< FRAGCOUNT (Bit 0)                                     */
37973  #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Msk                     (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff)                 */
37974 /* ===================================================  VLANRECEIVEDOK_P0  =================================================== */
37975  #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
37976  #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
37977 /* ===================================================  VLANRECEIVEDOK_P1  =================================================== */
37978  #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
37979  #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
37980 /* ===================================================  VLANRECEIVEDOK_P2  =================================================== */
37981  #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
37982  #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
37983 /* ===================================================  VLANRECEIVEDOK_P3  =================================================== */
37984  #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Pos                       (0UL)          /*!< RXVLANTAGCNT (Bit 0)                                  */
37985  #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Msk                       (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff)              */
37986 /* =================================================  VLANTRANSMITTEDOK_P0  ================================================== */
37987  #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
37988  #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
37989 /* =================================================  VLANTRANSMITTEDOK_P1  ================================================== */
37990  #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
37991  #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
37992 /* =================================================  VLANTRANSMITTEDOK_P2  ================================================== */
37993  #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
37994  #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
37995 /* =================================================  VLANTRANSMITTEDOK_P3  ================================================== */
37996  #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Pos                    (0UL)          /*!< TXVLANTAGCNT (Bit 0)                                  */
37997  #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Msk                    (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff)             */
37998 /* ================================================  FRAMESRETRANSMITTED_P0  ================================================= */
37999  #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
38000  #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
38001 /* ================================================  FRAMESRETRANSMITTED_P1  ================================================= */
38002  #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
38003  #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
38004 /* ================================================  FRAMESRETRANSMITTED_P2  ================================================= */
38005  #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
38006  #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
38007 /* ================================================  FRAMESRETRANSMITTED_P3  ================================================= */
38008  #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Pos                     (0UL)          /*!< RETXCOUNT (Bit 0)                                     */
38009  #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Msk                     (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff)                 */
38010 /* ====================================================  STATS_HIWORD_P0  ==================================================== */
38011  #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
38012  #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
38013 /* ====================================================  STATS_HIWORD_P1  ==================================================== */
38014  #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
38015  #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
38016 /* ====================================================  STATS_HIWORD_P2  ==================================================== */
38017  #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
38018  #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
38019 /* ====================================================  STATS_HIWORD_P3  ==================================================== */
38020  #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Pos                         (0UL)          /*!< STATS_HIWORD (Bit 0)                                  */
38021  #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Msk                         (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff)              */
38022 /* =====================================================  STATS_CTRL_P0  ===================================================== */
38023  #define R_ETHSW_STATS_CTRL_P0_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
38024  #define R_ETHSW_STATS_CTRL_P0_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
38025  #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
38026  #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
38027 /* =====================================================  STATS_CTRL_P1  ===================================================== */
38028  #define R_ETHSW_STATS_CTRL_P1_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
38029  #define R_ETHSW_STATS_CTRL_P1_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
38030  #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
38031  #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
38032 /* =====================================================  STATS_CTRL_P2  ===================================================== */
38033  #define R_ETHSW_STATS_CTRL_P2_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
38034  #define R_ETHSW_STATS_CTRL_P2_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
38035  #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
38036  #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
38037 /* =====================================================  STATS_CTRL_P3  ===================================================== */
38038  #define R_ETHSW_STATS_CTRL_P3_CLRALL_Pos                                 (0UL)          /*!< CLRALL (Bit 0)                                        */
38039  #define R_ETHSW_STATS_CTRL_P3_CLRALL_Msk                                 (0x1UL)        /*!< CLRALL (Bitfield-Mask: 0x01)                          */
38040  #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Pos                                (1UL)          /*!< CLRBUSY (Bit 1)                                       */
38041  #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Msk                                (0x2UL)        /*!< CLRBUSY (Bitfield-Mask: 0x01)                         */
38042 /* ================================================  STATS_CLEAR_VALUELO_P0  ================================================= */
38043  #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
38044  #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
38045 /* ================================================  STATS_CLEAR_VALUELO_P1  ================================================= */
38046  #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
38047  #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
38048 /* ================================================  STATS_CLEAR_VALUELO_P2  ================================================= */
38049  #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
38050  #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
38051 /* ================================================  STATS_CLEAR_VALUELO_P3  ================================================= */
38052  #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Pos           (0UL)          /*!< STATS_CLEAR_VALUELO (Bit 0)                          */
38053  #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */
38054 /* ================================================  STATS_CLEAR_VALUEHI_P0  ================================================= */
38055  #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
38056  #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
38057 /* ================================================  STATS_CLEAR_VALUEHI_P1  ================================================= */
38058  #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
38059  #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
38060 /* ================================================  STATS_CLEAR_VALUEHI_P2  ================================================= */
38061  #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
38062  #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
38063 /* ================================================  STATS_CLEAR_VALUEHI_P3  ================================================= */
38064  #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Pos           (0UL)          /*!< STATS_CLEAR_VALUEHI (Bit 0)                          */
38065  #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Msk           (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */
38066 /* =====================================================  ADEFERRED_P0  ====================================================== */
38067  #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
38068  #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
38069 /* =====================================================  ADEFERRED_P1  ====================================================== */
38070  #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
38071  #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
38072 /* =====================================================  ADEFERRED_P2  ====================================================== */
38073  #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
38074  #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
38075 /* =====================================================  ADEFERRED_P3  ====================================================== */
38076  #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Pos                              (0UL)          /*!< DEFERCOUNT (Bit 0)                                    */
38077  #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Msk                              (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff)                */
38078 /* ================================================  AMULTIPLECOLLISIONS_P0  ================================================= */
38079  #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
38080  #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
38081 /* ================================================  AMULTIPLECOLLISIONS_P1  ================================================= */
38082  #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
38083  #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
38084 /* ================================================  AMULTIPLECOLLISIONS_P2  ================================================= */
38085  #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
38086  #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
38087 /* ================================================  AMULTIPLECOLLISIONS_P3  ================================================= */
38088  #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Pos               (0UL)          /*!< COUNTAFTMLTCOLL (Bit 0)                               */
38089  #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Msk               (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff)     */
38090 /* =================================================  ASINGLECOLLISIONS_P0  ================================================== */
38091  #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
38092  #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
38093 /* =================================================  ASINGLECOLLISIONS_P1  ================================================== */
38094  #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
38095  #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
38096 /* =================================================  ASINGLECOLLISIONS_P2  ================================================== */
38097  #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
38098  #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
38099 /* =================================================  ASINGLECOLLISIONS_P3  ================================================== */
38100  #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Pos                (0UL)          /*!< COUNTAFTSNGLCOLL (Bit 0)                              */
38101  #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Msk                (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff)     */
38102 /* ==================================================  ALATECOLLISIONS_P0  =================================================== */
38103  #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
38104  #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
38105 /* ==================================================  ALATECOLLISIONS_P1  =================================================== */
38106  #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
38107  #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
38108 /* ==================================================  ALATECOLLISIONS_P2  =================================================== */
38109  #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
38110  #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
38111 /* ==================================================  ALATECOLLISIONS_P3  =================================================== */
38112  #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Pos                     (0UL)          /*!< LATECOLLCOUNT (Bit 0)                                 */
38113  #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Msk                     (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff)             */
38114 /* ================================================  AEXCESSIVECOLLISIONS_P0  ================================================ */
38115  #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
38116  #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
38117 /* ================================================  AEXCESSIVECOLLISIONS_P1  ================================================ */
38118  #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
38119  #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
38120 /* ================================================  AEXCESSIVECOLLISIONS_P2  ================================================ */
38121  #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
38122  #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
38123 /* ================================================  AEXCESSIVECOLLISIONS_P3  ================================================ */
38124  #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Pos                 (0UL)          /*!< EXCCOLLCOUNT (Bit 0)                                  */
38125  #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Msk                 (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff)          */
38126 /* ================================================  ACARRIERSENSEERRORS_P0  ================================================= */
38127  #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
38128  #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
38129 /* ================================================  ACARRIERSENSEERRORS_P1  ================================================= */
38130  #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
38131  #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
38132 /* ================================================  ACARRIERSENSEERRORS_P2  ================================================= */
38133  #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
38134  #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
38135 /* ================================================  ACARRIERSENSEERRORS_P3  ================================================= */
38136  #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Pos                    (0UL)          /*!< CSERRCOUNT (Bit 0)                                    */
38137  #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Msk                    (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff)               */
38138 /* ======================================================  P0_QSTMACU0  ====================================================== */
38139  #define R_ETHSW_P0_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38140  #define R_ETHSW_P0_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38141  #define R_ETHSW_P0_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38142  #define R_ETHSW_P0_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38143 /* ======================================================  P0_QSTMACU1  ====================================================== */
38144  #define R_ETHSW_P0_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38145  #define R_ETHSW_P0_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38146  #define R_ETHSW_P0_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38147  #define R_ETHSW_P0_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38148 /* ======================================================  P0_QSTMACU2  ====================================================== */
38149  #define R_ETHSW_P0_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38150  #define R_ETHSW_P0_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38151  #define R_ETHSW_P0_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38152  #define R_ETHSW_P0_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38153 /* ======================================================  P0_QSTMACU3  ====================================================== */
38154  #define R_ETHSW_P0_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38155  #define R_ETHSW_P0_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38156  #define R_ETHSW_P0_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38157  #define R_ETHSW_P0_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38158 /* ======================================================  P0_QSTMACU4  ====================================================== */
38159  #define R_ETHSW_P0_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38160  #define R_ETHSW_P0_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38161  #define R_ETHSW_P0_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38162  #define R_ETHSW_P0_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38163 /* ======================================================  P0_QSTMACU5  ====================================================== */
38164  #define R_ETHSW_P0_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38165  #define R_ETHSW_P0_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38166  #define R_ETHSW_P0_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38167  #define R_ETHSW_P0_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38168 /* ======================================================  P0_QSTMACU6  ====================================================== */
38169  #define R_ETHSW_P0_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38170  #define R_ETHSW_P0_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38171  #define R_ETHSW_P0_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38172  #define R_ETHSW_P0_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38173 /* ======================================================  P0_QSTMACU7  ====================================================== */
38174  #define R_ETHSW_P0_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38175  #define R_ETHSW_P0_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
38176  #define R_ETHSW_P0_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
38177  #define R_ETHSW_P0_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
38178 /* ======================================================  P0_QSTMACD0  ====================================================== */
38179  #define R_ETHSW_P0_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38180  #define R_ETHSW_P0_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38181 /* ======================================================  P0_QSTMACD1  ====================================================== */
38182  #define R_ETHSW_P0_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38183  #define R_ETHSW_P0_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38184 /* ======================================================  P0_QSTMACD2  ====================================================== */
38185  #define R_ETHSW_P0_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38186  #define R_ETHSW_P0_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38187 /* ======================================================  P0_QSTMACD3  ====================================================== */
38188  #define R_ETHSW_P0_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38189  #define R_ETHSW_P0_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38190 /* ======================================================  P0_QSTMACD4  ====================================================== */
38191  #define R_ETHSW_P0_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38192  #define R_ETHSW_P0_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38193 /* ======================================================  P0_QSTMACD5  ====================================================== */
38194  #define R_ETHSW_P0_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38195  #define R_ETHSW_P0_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38196 /* ======================================================  P0_QSTMACD6  ====================================================== */
38197  #define R_ETHSW_P0_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38198  #define R_ETHSW_P0_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38199 /* ======================================================  P0_QSTMACD7  ====================================================== */
38200  #define R_ETHSW_P0_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
38201  #define R_ETHSW_P0_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
38202 /* ======================================================  P0_QSTMAMU0  ====================================================== */
38203  #define R_ETHSW_P0_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38204  #define R_ETHSW_P0_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38205 /* ======================================================  P0_QSTMAMU1  ====================================================== */
38206  #define R_ETHSW_P0_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38207  #define R_ETHSW_P0_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38208 /* ======================================================  P0_QSTMAMU2  ====================================================== */
38209  #define R_ETHSW_P0_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38210  #define R_ETHSW_P0_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38211 /* ======================================================  P0_QSTMAMU3  ====================================================== */
38212  #define R_ETHSW_P0_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38213  #define R_ETHSW_P0_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38214 /* ======================================================  P0_QSTMAMU4  ====================================================== */
38215  #define R_ETHSW_P0_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38216  #define R_ETHSW_P0_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38217 /* ======================================================  P0_QSTMAMU5  ====================================================== */
38218  #define R_ETHSW_P0_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38219  #define R_ETHSW_P0_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38220 /* ======================================================  P0_QSTMAMU6  ====================================================== */
38221  #define R_ETHSW_P0_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38222  #define R_ETHSW_P0_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38223 /* ======================================================  P0_QSTMAMU7  ====================================================== */
38224  #define R_ETHSW_P0_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38225  #define R_ETHSW_P0_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
38226 /* ======================================================  P0_QSTMAMD0  ====================================================== */
38227  #define R_ETHSW_P0_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38228  #define R_ETHSW_P0_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38229 /* ======================================================  P0_QSTMAMD1  ====================================================== */
38230  #define R_ETHSW_P0_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38231  #define R_ETHSW_P0_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38232 /* ======================================================  P0_QSTMAMD2  ====================================================== */
38233  #define R_ETHSW_P0_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38234  #define R_ETHSW_P0_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38235 /* ======================================================  P0_QSTMAMD3  ====================================================== */
38236  #define R_ETHSW_P0_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38237  #define R_ETHSW_P0_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38238 /* ======================================================  P0_QSTMAMD4  ====================================================== */
38239  #define R_ETHSW_P0_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38240  #define R_ETHSW_P0_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38241 /* ======================================================  P0_QSTMAMD5  ====================================================== */
38242  #define R_ETHSW_P0_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38243  #define R_ETHSW_P0_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38244 /* ======================================================  P0_QSTMAMD6  ====================================================== */
38245  #define R_ETHSW_P0_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38246  #define R_ETHSW_P0_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38247 /* ======================================================  P0_QSTMAMD7  ====================================================== */
38248  #define R_ETHSW_P0_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
38249  #define R_ETHSW_P0_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
38250 /* ======================================================  P0_QSFTVL0  ======================================================= */
38251  #define R_ETHSW_P0_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38252  #define R_ETHSW_P0_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38253  #define R_ETHSW_P0_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38254  #define R_ETHSW_P0_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38255  #define R_ETHSW_P0_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38256  #define R_ETHSW_P0_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38257  #define R_ETHSW_P0_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38258  #define R_ETHSW_P0_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38259 /* ======================================================  P0_QSFTVL1  ======================================================= */
38260  #define R_ETHSW_P0_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38261  #define R_ETHSW_P0_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38262  #define R_ETHSW_P0_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38263  #define R_ETHSW_P0_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38264  #define R_ETHSW_P0_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38265  #define R_ETHSW_P0_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38266  #define R_ETHSW_P0_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38267  #define R_ETHSW_P0_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38268 /* ======================================================  P0_QSFTVL2  ======================================================= */
38269  #define R_ETHSW_P0_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38270  #define R_ETHSW_P0_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38271  #define R_ETHSW_P0_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38272  #define R_ETHSW_P0_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38273  #define R_ETHSW_P0_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38274  #define R_ETHSW_P0_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38275  #define R_ETHSW_P0_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38276  #define R_ETHSW_P0_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38277 /* ======================================================  P0_QSFTVL3  ======================================================= */
38278  #define R_ETHSW_P0_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38279  #define R_ETHSW_P0_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38280  #define R_ETHSW_P0_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38281  #define R_ETHSW_P0_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38282  #define R_ETHSW_P0_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38283  #define R_ETHSW_P0_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38284  #define R_ETHSW_P0_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38285  #define R_ETHSW_P0_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38286 /* ======================================================  P0_QSFTVL4  ======================================================= */
38287  #define R_ETHSW_P0_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38288  #define R_ETHSW_P0_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38289  #define R_ETHSW_P0_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38290  #define R_ETHSW_P0_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38291  #define R_ETHSW_P0_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38292  #define R_ETHSW_P0_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38293  #define R_ETHSW_P0_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38294  #define R_ETHSW_P0_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38295 /* ======================================================  P0_QSFTVL5  ======================================================= */
38296  #define R_ETHSW_P0_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38297  #define R_ETHSW_P0_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38298  #define R_ETHSW_P0_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38299  #define R_ETHSW_P0_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38300  #define R_ETHSW_P0_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38301  #define R_ETHSW_P0_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38302  #define R_ETHSW_P0_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38303  #define R_ETHSW_P0_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38304 /* ======================================================  P0_QSFTVL6  ======================================================= */
38305  #define R_ETHSW_P0_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38306  #define R_ETHSW_P0_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38307  #define R_ETHSW_P0_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38308  #define R_ETHSW_P0_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38309  #define R_ETHSW_P0_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38310  #define R_ETHSW_P0_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38311  #define R_ETHSW_P0_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38312  #define R_ETHSW_P0_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38313 /* ======================================================  P0_QSFTVL7  ======================================================= */
38314  #define R_ETHSW_P0_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
38315  #define R_ETHSW_P0_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
38316  #define R_ETHSW_P0_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
38317  #define R_ETHSW_P0_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38318  #define R_ETHSW_P0_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
38319  #define R_ETHSW_P0_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38320  #define R_ETHSW_P0_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
38321  #define R_ETHSW_P0_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
38322 /* ======================================================  P0_QSFTVLM0  ====================================================== */
38323  #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38324  #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38325  #define R_ETHSW_P0_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38326  #define R_ETHSW_P0_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38327  #define R_ETHSW_P0_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38328  #define R_ETHSW_P0_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38329 /* ======================================================  P0_QSFTVLM1  ====================================================== */
38330  #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38331  #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38332  #define R_ETHSW_P0_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38333  #define R_ETHSW_P0_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38334  #define R_ETHSW_P0_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38335  #define R_ETHSW_P0_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38336 /* ======================================================  P0_QSFTVLM2  ====================================================== */
38337  #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38338  #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38339  #define R_ETHSW_P0_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38340  #define R_ETHSW_P0_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38341  #define R_ETHSW_P0_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38342  #define R_ETHSW_P0_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38343 /* ======================================================  P0_QSFTVLM3  ====================================================== */
38344  #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38345  #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38346  #define R_ETHSW_P0_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38347  #define R_ETHSW_P0_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38348  #define R_ETHSW_P0_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38349  #define R_ETHSW_P0_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38350 /* ======================================================  P0_QSFTVLM4  ====================================================== */
38351  #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38352  #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38353  #define R_ETHSW_P0_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38354  #define R_ETHSW_P0_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38355  #define R_ETHSW_P0_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38356  #define R_ETHSW_P0_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38357 /* ======================================================  P0_QSFTVLM5  ====================================================== */
38358  #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38359  #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38360  #define R_ETHSW_P0_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38361  #define R_ETHSW_P0_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38362  #define R_ETHSW_P0_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38363  #define R_ETHSW_P0_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38364 /* ======================================================  P0_QSFTVLM6  ====================================================== */
38365  #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38366  #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38367  #define R_ETHSW_P0_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38368  #define R_ETHSW_P0_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38369  #define R_ETHSW_P0_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38370  #define R_ETHSW_P0_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38371 /* ======================================================  P0_QSFTVLM7  ====================================================== */
38372  #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
38373  #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
38374  #define R_ETHSW_P0_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
38375  #define R_ETHSW_P0_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
38376  #define R_ETHSW_P0_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
38377  #define R_ETHSW_P0_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
38378 /* ======================================================  P0_QSFTBL0  ======================================================= */
38379  #define R_ETHSW_P0_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38380  #define R_ETHSW_P0_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38381  #define R_ETHSW_P0_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38382  #define R_ETHSW_P0_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38383  #define R_ETHSW_P0_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38384  #define R_ETHSW_P0_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38385  #define R_ETHSW_P0_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38386  #define R_ETHSW_P0_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38387  #define R_ETHSW_P0_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38388  #define R_ETHSW_P0_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38389  #define R_ETHSW_P0_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38390  #define R_ETHSW_P0_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38391  #define R_ETHSW_P0_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38392  #define R_ETHSW_P0_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38393  #define R_ETHSW_P0_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38394  #define R_ETHSW_P0_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38395 /* ======================================================  P0_QSFTBL1  ======================================================= */
38396  #define R_ETHSW_P0_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38397  #define R_ETHSW_P0_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38398  #define R_ETHSW_P0_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38399  #define R_ETHSW_P0_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38400  #define R_ETHSW_P0_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38401  #define R_ETHSW_P0_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38402  #define R_ETHSW_P0_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38403  #define R_ETHSW_P0_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38404  #define R_ETHSW_P0_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38405  #define R_ETHSW_P0_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38406  #define R_ETHSW_P0_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38407  #define R_ETHSW_P0_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38408  #define R_ETHSW_P0_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38409  #define R_ETHSW_P0_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38410  #define R_ETHSW_P0_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38411  #define R_ETHSW_P0_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38412 /* ======================================================  P0_QSFTBL2  ======================================================= */
38413  #define R_ETHSW_P0_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38414  #define R_ETHSW_P0_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38415  #define R_ETHSW_P0_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38416  #define R_ETHSW_P0_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38417  #define R_ETHSW_P0_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38418  #define R_ETHSW_P0_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38419  #define R_ETHSW_P0_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38420  #define R_ETHSW_P0_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38421  #define R_ETHSW_P0_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38422  #define R_ETHSW_P0_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38423  #define R_ETHSW_P0_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38424  #define R_ETHSW_P0_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38425  #define R_ETHSW_P0_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38426  #define R_ETHSW_P0_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38427  #define R_ETHSW_P0_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38428  #define R_ETHSW_P0_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38429 /* ======================================================  P0_QSFTBL3  ======================================================= */
38430  #define R_ETHSW_P0_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38431  #define R_ETHSW_P0_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38432  #define R_ETHSW_P0_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38433  #define R_ETHSW_P0_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38434  #define R_ETHSW_P0_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38435  #define R_ETHSW_P0_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38436  #define R_ETHSW_P0_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38437  #define R_ETHSW_P0_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38438  #define R_ETHSW_P0_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38439  #define R_ETHSW_P0_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38440  #define R_ETHSW_P0_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38441  #define R_ETHSW_P0_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38442  #define R_ETHSW_P0_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38443  #define R_ETHSW_P0_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38444  #define R_ETHSW_P0_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38445  #define R_ETHSW_P0_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38446 /* ======================================================  P0_QSFTBL4  ======================================================= */
38447  #define R_ETHSW_P0_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38448  #define R_ETHSW_P0_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38449  #define R_ETHSW_P0_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38450  #define R_ETHSW_P0_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38451  #define R_ETHSW_P0_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38452  #define R_ETHSW_P0_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38453  #define R_ETHSW_P0_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38454  #define R_ETHSW_P0_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38455  #define R_ETHSW_P0_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38456  #define R_ETHSW_P0_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38457  #define R_ETHSW_P0_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38458  #define R_ETHSW_P0_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38459  #define R_ETHSW_P0_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38460  #define R_ETHSW_P0_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38461  #define R_ETHSW_P0_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38462  #define R_ETHSW_P0_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38463 /* ======================================================  P0_QSFTBL5  ======================================================= */
38464  #define R_ETHSW_P0_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38465  #define R_ETHSW_P0_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38466  #define R_ETHSW_P0_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38467  #define R_ETHSW_P0_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38468  #define R_ETHSW_P0_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38469  #define R_ETHSW_P0_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38470  #define R_ETHSW_P0_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38471  #define R_ETHSW_P0_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38472  #define R_ETHSW_P0_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38473  #define R_ETHSW_P0_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38474  #define R_ETHSW_P0_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38475  #define R_ETHSW_P0_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38476  #define R_ETHSW_P0_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38477  #define R_ETHSW_P0_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38478  #define R_ETHSW_P0_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38479  #define R_ETHSW_P0_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38480 /* ======================================================  P0_QSFTBL6  ======================================================= */
38481  #define R_ETHSW_P0_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38482  #define R_ETHSW_P0_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38483  #define R_ETHSW_P0_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38484  #define R_ETHSW_P0_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38485  #define R_ETHSW_P0_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38486  #define R_ETHSW_P0_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38487  #define R_ETHSW_P0_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38488  #define R_ETHSW_P0_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38489  #define R_ETHSW_P0_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38490  #define R_ETHSW_P0_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38491  #define R_ETHSW_P0_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38492  #define R_ETHSW_P0_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38493  #define R_ETHSW_P0_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38494  #define R_ETHSW_P0_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38495  #define R_ETHSW_P0_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38496  #define R_ETHSW_P0_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38497 /* ======================================================  P0_QSFTBL7  ======================================================= */
38498  #define R_ETHSW_P0_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
38499  #define R_ETHSW_P0_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
38500  #define R_ETHSW_P0_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
38501  #define R_ETHSW_P0_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
38502  #define R_ETHSW_P0_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
38503  #define R_ETHSW_P0_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
38504  #define R_ETHSW_P0_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
38505  #define R_ETHSW_P0_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
38506  #define R_ETHSW_P0_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
38507  #define R_ETHSW_P0_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
38508  #define R_ETHSW_P0_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
38509  #define R_ETHSW_P0_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
38510  #define R_ETHSW_P0_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
38511  #define R_ETHSW_P0_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
38512  #define R_ETHSW_P0_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
38513  #define R_ETHSW_P0_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
38514 /* =======================================================  P0_QSMFC0  ======================================================= */
38515  #define R_ETHSW_P0_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38516  #define R_ETHSW_P0_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38517 /* =======================================================  P0_QSMFC1  ======================================================= */
38518  #define R_ETHSW_P0_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38519  #define R_ETHSW_P0_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38520 /* =======================================================  P0_QSMFC2  ======================================================= */
38521  #define R_ETHSW_P0_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38522  #define R_ETHSW_P0_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38523 /* =======================================================  P0_QSMFC3  ======================================================= */
38524  #define R_ETHSW_P0_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38525  #define R_ETHSW_P0_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38526 /* =======================================================  P0_QSMFC4  ======================================================= */
38527  #define R_ETHSW_P0_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38528  #define R_ETHSW_P0_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38529 /* =======================================================  P0_QSMFC5  ======================================================= */
38530  #define R_ETHSW_P0_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38531  #define R_ETHSW_P0_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38532 /* =======================================================  P0_QSMFC6  ======================================================= */
38533  #define R_ETHSW_P0_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38534  #define R_ETHSW_P0_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38535 /* =======================================================  P0_QSMFC7  ======================================================= */
38536  #define R_ETHSW_P0_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
38537  #define R_ETHSW_P0_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
38538 /* ======================================================  P0_QMSPPC0  ======================================================= */
38539  #define R_ETHSW_P0_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38540  #define R_ETHSW_P0_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38541 /* ======================================================  P0_QMSPPC1  ======================================================= */
38542  #define R_ETHSW_P0_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38543  #define R_ETHSW_P0_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38544 /* ======================================================  P0_QMSPPC2  ======================================================= */
38545  #define R_ETHSW_P0_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38546  #define R_ETHSW_P0_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38547 /* ======================================================  P0_QMSPPC3  ======================================================= */
38548  #define R_ETHSW_P0_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38549  #define R_ETHSW_P0_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38550 /* ======================================================  P0_QMSPPC4  ======================================================= */
38551  #define R_ETHSW_P0_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38552  #define R_ETHSW_P0_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38553 /* ======================================================  P0_QMSPPC5  ======================================================= */
38554  #define R_ETHSW_P0_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38555  #define R_ETHSW_P0_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38556 /* ======================================================  P0_QMSPPC6  ======================================================= */
38557  #define R_ETHSW_P0_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38558  #define R_ETHSW_P0_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38559 /* ======================================================  P0_QMSPPC7  ======================================================= */
38560  #define R_ETHSW_P0_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
38561  #define R_ETHSW_P0_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
38562 /* ======================================================  P0_QMSRPC0  ======================================================= */
38563  #define R_ETHSW_P0_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38564  #define R_ETHSW_P0_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38565 /* ======================================================  P0_QMSRPC1  ======================================================= */
38566  #define R_ETHSW_P0_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38567  #define R_ETHSW_P0_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38568 /* ======================================================  P0_QMSRPC2  ======================================================= */
38569  #define R_ETHSW_P0_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38570  #define R_ETHSW_P0_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38571 /* ======================================================  P0_QMSRPC3  ======================================================= */
38572  #define R_ETHSW_P0_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38573  #define R_ETHSW_P0_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38574 /* ======================================================  P0_QMSRPC4  ======================================================= */
38575  #define R_ETHSW_P0_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38576  #define R_ETHSW_P0_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38577 /* ======================================================  P0_QMSRPC5  ======================================================= */
38578  #define R_ETHSW_P0_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38579  #define R_ETHSW_P0_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38580 /* ======================================================  P0_QMSRPC6  ======================================================= */
38581  #define R_ETHSW_P0_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38582  #define R_ETHSW_P0_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38583 /* ======================================================  P0_QMSRPC7  ======================================================= */
38584  #define R_ETHSW_P0_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
38585  #define R_ETHSW_P0_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
38586 /* =======================================================  P0_QSEIS  ======================================================== */
38587  #define R_ETHSW_P0_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
38588  #define R_ETHSW_P0_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
38589 /* =======================================================  P1_QSEIS  ======================================================== */
38590  #define R_ETHSW_P1_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
38591  #define R_ETHSW_P1_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
38592 /* =======================================================  P2_QSEIS  ======================================================== */
38593  #define R_ETHSW_P2_QSEIS_QSMOIS_Pos                                      (0UL)          /*!< QSMOIS (Bit 0)                                        */
38594  #define R_ETHSW_P2_QSEIS_QSMOIS_Msk                                      (0xffUL)       /*!< QSMOIS (Bitfield-Mask: 0xff)                          */
38595 /* =======================================================  P0_QSEIE  ======================================================== */
38596  #define R_ETHSW_P0_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
38597  #define R_ETHSW_P0_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
38598 /* =======================================================  P1_QSEIE  ======================================================== */
38599  #define R_ETHSW_P1_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
38600  #define R_ETHSW_P1_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
38601 /* =======================================================  P2_QSEIE  ======================================================== */
38602  #define R_ETHSW_P2_QSEIE_QSMOIE_Pos                                      (0UL)          /*!< QSMOIE (Bit 0)                                        */
38603  #define R_ETHSW_P2_QSEIE_QSMOIE_Msk                                      (0xffUL)       /*!< QSMOIE (Bitfield-Mask: 0xff)                          */
38604 /* =======================================================  P0_QSEID  ======================================================== */
38605  #define R_ETHSW_P0_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
38606  #define R_ETHSW_P0_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
38607 /* =======================================================  P1_QSEID  ======================================================== */
38608  #define R_ETHSW_P1_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
38609  #define R_ETHSW_P1_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
38610 /* =======================================================  P2_QSEID  ======================================================== */
38611  #define R_ETHSW_P2_QSEID_QSMOID_Pos                                      (0UL)          /*!< QSMOID (Bit 0)                                        */
38612  #define R_ETHSW_P2_QSEID_QSMOID_Msk                                      (0xffUL)       /*!< QSMOID (Bitfield-Mask: 0xff)                          */
38613 /* =======================================================  P0_QGMOD  ======================================================== */
38614  #define R_ETHSW_P0_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
38615  #define R_ETHSW_P0_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
38616 /* =======================================================  P1_QGMOD  ======================================================== */
38617  #define R_ETHSW_P1_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
38618  #define R_ETHSW_P1_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
38619 /* =======================================================  P2_QGMOD  ======================================================== */
38620  #define R_ETHSW_P2_QGMOD_QGMOD_Pos                                       (0UL)          /*!< QGMOD (Bit 0)                                         */
38621  #define R_ETHSW_P2_QGMOD_QGMOD_Msk                                       (0xffUL)       /*!< QGMOD (Bitfield-Mask: 0xff)                           */
38622 /* =======================================================  P0_QGPPC  ======================================================== */
38623  #define R_ETHSW_P0_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
38624  #define R_ETHSW_P0_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
38625 /* =======================================================  P1_QGPPC  ======================================================== */
38626  #define R_ETHSW_P1_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
38627  #define R_ETHSW_P1_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
38628 /* =======================================================  P2_QGPPC  ======================================================== */
38629  #define R_ETHSW_P2_QGPPC_QGPPC_Pos                                       (0UL)          /*!< QGPPC (Bit 0)                                         */
38630  #define R_ETHSW_P2_QGPPC_QGPPC_Msk                                       (0xffffUL)     /*!< QGPPC (Bitfield-Mask: 0xffff)                         */
38631 /* =======================================================  P0_QGDPC0  ======================================================= */
38632  #define R_ETHSW_P0_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38633  #define R_ETHSW_P0_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38634 /* =======================================================  P0_QGDPC1  ======================================================= */
38635  #define R_ETHSW_P0_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38636  #define R_ETHSW_P0_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38637 /* =======================================================  P0_QGDPC2  ======================================================= */
38638  #define R_ETHSW_P0_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38639  #define R_ETHSW_P0_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38640 /* =======================================================  P0_QGDPC3  ======================================================= */
38641  #define R_ETHSW_P0_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38642  #define R_ETHSW_P0_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38643 /* =======================================================  P0_QGDPC4  ======================================================= */
38644  #define R_ETHSW_P0_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38645  #define R_ETHSW_P0_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38646 /* =======================================================  P0_QGDPC5  ======================================================= */
38647  #define R_ETHSW_P0_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38648  #define R_ETHSW_P0_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38649 /* =======================================================  P0_QGDPC6  ======================================================= */
38650  #define R_ETHSW_P0_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38651  #define R_ETHSW_P0_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38652 /* =======================================================  P0_QGDPC7  ======================================================= */
38653  #define R_ETHSW_P0_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
38654  #define R_ETHSW_P0_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
38655 /* =======================================================  P0_QGEIS  ======================================================== */
38656  #define R_ETHSW_P0_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
38657  #define R_ETHSW_P0_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
38658 /* =======================================================  P1_QGEIS  ======================================================== */
38659  #define R_ETHSW_P1_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
38660  #define R_ETHSW_P1_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
38661 /* =======================================================  P2_QGEIS  ======================================================== */
38662  #define R_ETHSW_P2_QGEIS_QGMOIS_Pos                                      (0UL)          /*!< QGMOIS (Bit 0)                                        */
38663  #define R_ETHSW_P2_QGEIS_QGMOIS_Msk                                      (0xffUL)       /*!< QGMOIS (Bitfield-Mask: 0xff)                          */
38664 /* =======================================================  P0_QGEIE  ======================================================== */
38665  #define R_ETHSW_P0_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
38666  #define R_ETHSW_P0_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
38667 /* =======================================================  P1_QGEIE  ======================================================== */
38668  #define R_ETHSW_P1_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
38669  #define R_ETHSW_P1_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
38670 /* =======================================================  P2_QGEIE  ======================================================== */
38671  #define R_ETHSW_P2_QGEIE_QGMOIE_Pos                                      (0UL)          /*!< QGMOIE (Bit 0)                                        */
38672  #define R_ETHSW_P2_QGEIE_QGMOIE_Msk                                      (0xffUL)       /*!< QGMOIE (Bitfield-Mask: 0xff)                          */
38673 /* =======================================================  P0_QGEID  ======================================================== */
38674  #define R_ETHSW_P0_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
38675  #define R_ETHSW_P0_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
38676 /* =======================================================  P1_QGEID  ======================================================== */
38677  #define R_ETHSW_P1_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
38678  #define R_ETHSW_P1_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
38679 /* =======================================================  P2_QGEID  ======================================================== */
38680  #define R_ETHSW_P2_QGEID_QGMOID_Pos                                      (0UL)          /*!< QGMOID (Bit 0)                                        */
38681  #define R_ETHSW_P2_QGEID_QGMOID_Msk                                      (0xffUL)       /*!< QGMOID (Bitfield-Mask: 0xff)                          */
38682 /* ======================================================  P0_QMDESC0  ======================================================= */
38683  #define R_ETHSW_P0_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38684  #define R_ETHSW_P0_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38685  #define R_ETHSW_P0_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38686  #define R_ETHSW_P0_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38687  #define R_ETHSW_P0_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38688  #define R_ETHSW_P0_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38689 /* ======================================================  P0_QMDESC1  ======================================================= */
38690  #define R_ETHSW_P0_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38691  #define R_ETHSW_P0_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38692  #define R_ETHSW_P0_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38693  #define R_ETHSW_P0_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38694  #define R_ETHSW_P0_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38695  #define R_ETHSW_P0_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38696 /* ======================================================  P0_QMDESC2  ======================================================= */
38697  #define R_ETHSW_P0_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38698  #define R_ETHSW_P0_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38699  #define R_ETHSW_P0_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38700  #define R_ETHSW_P0_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38701  #define R_ETHSW_P0_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38702  #define R_ETHSW_P0_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38703 /* ======================================================  P0_QMDESC3  ======================================================= */
38704  #define R_ETHSW_P0_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38705  #define R_ETHSW_P0_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38706  #define R_ETHSW_P0_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38707  #define R_ETHSW_P0_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38708  #define R_ETHSW_P0_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38709  #define R_ETHSW_P0_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38710 /* ======================================================  P0_QMDESC4  ======================================================= */
38711  #define R_ETHSW_P0_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38712  #define R_ETHSW_P0_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38713  #define R_ETHSW_P0_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38714  #define R_ETHSW_P0_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38715  #define R_ETHSW_P0_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38716  #define R_ETHSW_P0_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38717 /* ======================================================  P0_QMDESC5  ======================================================= */
38718  #define R_ETHSW_P0_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38719  #define R_ETHSW_P0_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38720  #define R_ETHSW_P0_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38721  #define R_ETHSW_P0_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38722  #define R_ETHSW_P0_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38723  #define R_ETHSW_P0_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38724 /* ======================================================  P0_QMDESC6  ======================================================= */
38725  #define R_ETHSW_P0_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38726  #define R_ETHSW_P0_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38727  #define R_ETHSW_P0_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38728  #define R_ETHSW_P0_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38729  #define R_ETHSW_P0_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38730  #define R_ETHSW_P0_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38731 /* ======================================================  P0_QMDESC7  ======================================================= */
38732  #define R_ETHSW_P0_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
38733  #define R_ETHSW_P0_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
38734  #define R_ETHSW_P0_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
38735  #define R_ETHSW_P0_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
38736  #define R_ETHSW_P0_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
38737  #define R_ETHSW_P0_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
38738 /* ======================================================  P0_QMCBSC0  ======================================================= */
38739  #define R_ETHSW_P0_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38740  #define R_ETHSW_P0_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38741 /* ======================================================  P0_QMCBSC1  ======================================================= */
38742  #define R_ETHSW_P0_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38743  #define R_ETHSW_P0_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38744 /* ======================================================  P0_QMCBSC2  ======================================================= */
38745  #define R_ETHSW_P0_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38746  #define R_ETHSW_P0_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38747 /* ======================================================  P0_QMCBSC3  ======================================================= */
38748  #define R_ETHSW_P0_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38749  #define R_ETHSW_P0_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38750 /* ======================================================  P0_QMCBSC4  ======================================================= */
38751  #define R_ETHSW_P0_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38752  #define R_ETHSW_P0_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38753 /* ======================================================  P0_QMCBSC5  ======================================================= */
38754  #define R_ETHSW_P0_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38755  #define R_ETHSW_P0_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38756 /* ======================================================  P0_QMCBSC6  ======================================================= */
38757  #define R_ETHSW_P0_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38758  #define R_ETHSW_P0_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38759 /* ======================================================  P0_QMCBSC7  ======================================================= */
38760  #define R_ETHSW_P0_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
38761  #define R_ETHSW_P0_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
38762 /* ======================================================  P0_QMCIRC0  ======================================================= */
38763  #define R_ETHSW_P0_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38764  #define R_ETHSW_P0_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38765 /* ======================================================  P0_QMCIRC1  ======================================================= */
38766  #define R_ETHSW_P0_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38767  #define R_ETHSW_P0_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38768 /* ======================================================  P0_QMCIRC2  ======================================================= */
38769  #define R_ETHSW_P0_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38770  #define R_ETHSW_P0_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38771 /* ======================================================  P0_QMCIRC3  ======================================================= */
38772  #define R_ETHSW_P0_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38773  #define R_ETHSW_P0_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38774 /* ======================================================  P0_QMCIRC4  ======================================================= */
38775  #define R_ETHSW_P0_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38776  #define R_ETHSW_P0_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38777 /* ======================================================  P0_QMCIRC5  ======================================================= */
38778  #define R_ETHSW_P0_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38779  #define R_ETHSW_P0_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38780 /* ======================================================  P0_QMCIRC6  ======================================================= */
38781  #define R_ETHSW_P0_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38782  #define R_ETHSW_P0_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38783 /* ======================================================  P0_QMCIRC7  ======================================================= */
38784  #define R_ETHSW_P0_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
38785  #define R_ETHSW_P0_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
38786 /* =======================================================  P0_QMGPC0  ======================================================= */
38787  #define R_ETHSW_P0_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38788  #define R_ETHSW_P0_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38789 /* =======================================================  P0_QMGPC1  ======================================================= */
38790  #define R_ETHSW_P0_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38791  #define R_ETHSW_P0_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38792 /* =======================================================  P0_QMGPC2  ======================================================= */
38793  #define R_ETHSW_P0_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38794  #define R_ETHSW_P0_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38795 /* =======================================================  P0_QMGPC3  ======================================================= */
38796  #define R_ETHSW_P0_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38797  #define R_ETHSW_P0_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38798 /* =======================================================  P0_QMGPC4  ======================================================= */
38799  #define R_ETHSW_P0_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38800  #define R_ETHSW_P0_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38801 /* =======================================================  P0_QMGPC5  ======================================================= */
38802  #define R_ETHSW_P0_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38803  #define R_ETHSW_P0_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38804 /* =======================================================  P0_QMGPC6  ======================================================= */
38805  #define R_ETHSW_P0_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38806  #define R_ETHSW_P0_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38807 /* =======================================================  P0_QMGPC7  ======================================================= */
38808  #define R_ETHSW_P0_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
38809  #define R_ETHSW_P0_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
38810 /* =======================================================  P0_QMRPC0  ======================================================= */
38811  #define R_ETHSW_P0_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38812  #define R_ETHSW_P0_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38813 /* =======================================================  P0_QMRPC1  ======================================================= */
38814  #define R_ETHSW_P0_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38815  #define R_ETHSW_P0_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38816 /* =======================================================  P0_QMRPC2  ======================================================= */
38817  #define R_ETHSW_P0_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38818  #define R_ETHSW_P0_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38819 /* =======================================================  P0_QMRPC3  ======================================================= */
38820  #define R_ETHSW_P0_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38821  #define R_ETHSW_P0_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38822 /* =======================================================  P0_QMRPC4  ======================================================= */
38823  #define R_ETHSW_P0_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38824  #define R_ETHSW_P0_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38825 /* =======================================================  P0_QMRPC5  ======================================================= */
38826  #define R_ETHSW_P0_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38827  #define R_ETHSW_P0_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38828 /* =======================================================  P0_QMRPC6  ======================================================= */
38829  #define R_ETHSW_P0_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38830  #define R_ETHSW_P0_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38831 /* =======================================================  P0_QMRPC7  ======================================================= */
38832  #define R_ETHSW_P0_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
38833  #define R_ETHSW_P0_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
38834 /* ========================================================  P0_QMEC  ======================================================== */
38835  #define R_ETHSW_P0_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
38836  #define R_ETHSW_P0_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
38837 /* ========================================================  P1_QMEC  ======================================================== */
38838  #define R_ETHSW_P1_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
38839  #define R_ETHSW_P1_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
38840 /* ========================================================  P2_QMEC  ======================================================== */
38841  #define R_ETHSW_P2_QMEC_ME_Pos                                           (0UL)          /*!< ME (Bit 0)                                            */
38842  #define R_ETHSW_P2_QMEC_ME_Msk                                           (0xffUL)       /*!< ME (Bitfield-Mask: 0xff)                              */
38843 /* =======================================================  P0_QMEIS  ======================================================== */
38844  #define R_ETHSW_P0_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
38845  #define R_ETHSW_P0_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
38846 /* =======================================================  P1_QMEIS  ======================================================== */
38847  #define R_ETHSW_P1_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
38848  #define R_ETHSW_P1_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
38849 /* =======================================================  P2_QMEIS  ======================================================== */
38850  #define R_ETHSW_P2_QMEIS_QRFIS_Pos                                       (0UL)          /*!< QRFIS (Bit 0)                                         */
38851  #define R_ETHSW_P2_QMEIS_QRFIS_Msk                                       (0xffUL)       /*!< QRFIS (Bitfield-Mask: 0xff)                           */
38852 /* =======================================================  P0_QMEIE  ======================================================== */
38853  #define R_ETHSW_P0_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
38854  #define R_ETHSW_P0_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
38855 /* =======================================================  P1_QMEIE  ======================================================== */
38856  #define R_ETHSW_P1_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
38857  #define R_ETHSW_P1_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
38858 /* =======================================================  P2_QMEIE  ======================================================== */
38859  #define R_ETHSW_P2_QMEIE_QRFIE_Pos                                       (0UL)          /*!< QRFIE (Bit 0)                                         */
38860  #define R_ETHSW_P2_QMEIE_QRFIE_Msk                                       (0xffUL)       /*!< QRFIE (Bitfield-Mask: 0xff)                           */
38861 /* =======================================================  P0_QMEID  ======================================================== */
38862  #define R_ETHSW_P0_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
38863  #define R_ETHSW_P0_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
38864 /* =======================================================  P1_QMEID  ======================================================== */
38865  #define R_ETHSW_P1_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
38866  #define R_ETHSW_P1_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
38867 /* =======================================================  P2_QMEID  ======================================================== */
38868  #define R_ETHSW_P2_QMEID_QRFID_Pos                                       (0UL)          /*!< QRFID (Bit 0)                                         */
38869  #define R_ETHSW_P2_QMEID_QRFID_Msk                                       (0xffUL)       /*!< QRFID (Bitfield-Mask: 0xff)                           */
38870 /* =====================================================  P0_PCP_REMAP  ====================================================== */
38871  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
38872  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
38873  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
38874  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
38875  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
38876  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
38877  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
38878  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
38879  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
38880  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
38881  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
38882  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
38883  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
38884  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
38885  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
38886  #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
38887 /* =====================================================  P1_PCP_REMAP  ====================================================== */
38888  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
38889  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
38890  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
38891  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
38892  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
38893  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
38894  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
38895  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
38896  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
38897  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
38898  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
38899  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
38900  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
38901  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
38902  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
38903  #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
38904 /* =====================================================  P2_PCP_REMAP  ====================================================== */
38905  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Pos                              (0UL)          /*!< PCP_REMAP0 (Bit 0)                                    */
38906  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Msk                              (0x7UL)        /*!< PCP_REMAP0 (Bitfield-Mask: 0x07)                      */
38907  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Pos                              (3UL)          /*!< PCP_REMAP1 (Bit 3)                                    */
38908  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Msk                              (0x38UL)       /*!< PCP_REMAP1 (Bitfield-Mask: 0x07)                      */
38909  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Pos                              (6UL)          /*!< PCP_REMAP2 (Bit 6)                                    */
38910  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Msk                              (0x1c0UL)      /*!< PCP_REMAP2 (Bitfield-Mask: 0x07)                      */
38911  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Pos                              (9UL)          /*!< PCP_REMAP3 (Bit 9)                                    */
38912  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Msk                              (0xe00UL)      /*!< PCP_REMAP3 (Bitfield-Mask: 0x07)                      */
38913  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Pos                              (12UL)         /*!< PCP_REMAP4 (Bit 12)                                   */
38914  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Msk                              (0x7000UL)     /*!< PCP_REMAP4 (Bitfield-Mask: 0x07)                      */
38915  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Pos                              (15UL)         /*!< PCP_REMAP5 (Bit 15)                                   */
38916  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Msk                              (0x38000UL)    /*!< PCP_REMAP5 (Bitfield-Mask: 0x07)                      */
38917  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Pos                              (18UL)         /*!< PCP_REMAP6 (Bit 18)                                   */
38918  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Msk                              (0x1c0000UL)   /*!< PCP_REMAP6 (Bitfield-Mask: 0x07)                      */
38919  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Pos                              (21UL)         /*!< PCP_REMAP7 (Bit 21)                                   */
38920  #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Msk                              (0xe00000UL)   /*!< PCP_REMAP7 (Bitfield-Mask: 0x07)                      */
38921 /* ======================================================  P0_VLAN_TAG  ====================================================== */
38922  #define R_ETHSW_P0_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
38923  #define R_ETHSW_P0_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
38924  #define R_ETHSW_P0_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
38925  #define R_ETHSW_P0_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38926  #define R_ETHSW_P0_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
38927  #define R_ETHSW_P0_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38928  #define R_ETHSW_P0_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
38929  #define R_ETHSW_P0_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
38930 /* ======================================================  P1_VLAN_TAG  ====================================================== */
38931  #define R_ETHSW_P1_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
38932  #define R_ETHSW_P1_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
38933  #define R_ETHSW_P1_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
38934  #define R_ETHSW_P1_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38935  #define R_ETHSW_P1_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
38936  #define R_ETHSW_P1_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38937  #define R_ETHSW_P1_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
38938  #define R_ETHSW_P1_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
38939 /* ======================================================  P2_VLAN_TAG  ====================================================== */
38940  #define R_ETHSW_P2_VLAN_TAG_VID_Pos                                      (0UL)          /*!< VID (Bit 0)                                           */
38941  #define R_ETHSW_P2_VLAN_TAG_VID_Msk                                      (0xfffUL)      /*!< VID (Bitfield-Mask: 0xfff)                            */
38942  #define R_ETHSW_P2_VLAN_TAG_DEI_Pos                                      (12UL)         /*!< DEI (Bit 12)                                          */
38943  #define R_ETHSW_P2_VLAN_TAG_DEI_Msk                                      (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
38944  #define R_ETHSW_P2_VLAN_TAG_PCP_Pos                                      (13UL)         /*!< PCP (Bit 13)                                          */
38945  #define R_ETHSW_P2_VLAN_TAG_PCP_Msk                                      (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
38946  #define R_ETHSW_P2_VLAN_TAG_TPID_Pos                                     (16UL)         /*!< TPID (Bit 16)                                         */
38947  #define R_ETHSW_P2_VLAN_TAG_TPID_Msk                                     (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff)                          */
38948 /* =====================================================  P0_VLAN_MODE  ====================================================== */
38949  #define R_ETHSW_P0_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
38950  #define R_ETHSW_P0_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
38951  #define R_ETHSW_P0_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
38952  #define R_ETHSW_P0_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
38953 /* =====================================================  P1_VLAN_MODE  ====================================================== */
38954  #define R_ETHSW_P1_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
38955  #define R_ETHSW_P1_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
38956  #define R_ETHSW_P1_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
38957  #define R_ETHSW_P1_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
38958 /* =====================================================  P2_VLAN_MODE  ====================================================== */
38959  #define R_ETHSW_P2_VLAN_MODE_VITM_Pos                                    (0UL)          /*!< VITM (Bit 0)                                          */
38960  #define R_ETHSW_P2_VLAN_MODE_VITM_Msk                                    (0x3UL)        /*!< VITM (Bitfield-Mask: 0x03)                            */
38961  #define R_ETHSW_P2_VLAN_MODE_VICM_Pos                                    (2UL)          /*!< VICM (Bit 2)                                          */
38962  #define R_ETHSW_P2_VLAN_MODE_VICM_Msk                                    (0xcUL)        /*!< VICM (Bitfield-Mask: 0x03)                            */
38963 /* ====================================================  P0_VIC_DROP_CNT  ==================================================== */
38964  #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
38965  #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
38966 /* ====================================================  P1_VIC_DROP_CNT  ==================================================== */
38967  #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
38968  #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
38969 /* ====================================================  P2_VIC_DROP_CNT  ==================================================== */
38970  #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Pos                         (0UL)          /*!< VIC_DROP_CNT (Bit 0)                                  */
38971  #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Msk                         (0xffffUL)     /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff)                  */
38972 /* ===================================================  P0_LOOKUP_HIT_CNT  =================================================== */
38973  #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
38974  #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
38975 /* ===================================================  P1_LOOKUP_HIT_CNT  =================================================== */
38976  #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
38977  #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
38978 /* ===================================================  P2_LOOKUP_HIT_CNT  =================================================== */
38979  #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos                     (0UL)          /*!< LOOKUP_HIT_CNT (Bit 0)                                */
38980  #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk                     (0xffffffUL)   /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff)              */
38981 /* ====================================================  P0_ERROR_STATUS  ==================================================== */
38982  #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
38983  #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
38984  #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
38985  #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
38986  #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
38987  #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
38988  #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
38989  #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
38990  #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
38991  #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
38992 /* ====================================================  P1_ERROR_STATUS  ==================================================== */
38993  #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
38994  #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
38995  #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
38996  #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
38997  #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
38998  #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
38999  #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
39000  #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
39001  #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
39002  #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
39003 /* ====================================================  P2_ERROR_STATUS  ==================================================== */
39004  #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Pos                               (0UL)          /*!< SOPERR (Bit 0)                                        */
39005  #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Msk                               (0x1UL)        /*!< SOPERR (Bitfield-Mask: 0x01)                          */
39006  #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Pos                               (1UL)          /*!< PUNDSZ (Bit 1)                                        */
39007  #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Msk                               (0x2UL)        /*!< PUNDSZ (Bitfield-Mask: 0x01)                          */
39008  #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Pos                               (2UL)          /*!< POVRSZ (Bit 2)                                        */
39009  #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Msk                               (0x4UL)        /*!< POVRSZ (Bitfield-Mask: 0x01)                          */
39010  #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Pos                               (3UL)          /*!< EUNDSZ (Bit 3)                                        */
39011  #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Msk                               (0x8UL)        /*!< EUNDSZ (Bitfield-Mask: 0x01)                          */
39012  #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Pos                               (4UL)          /*!< EOVRSZ (Bit 4)                                        */
39013  #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Msk                               (0x10UL)       /*!< EOVRSZ (Bitfield-Mask: 0x01)                          */
39014 /* =====================================================  P0_ERROR_MASK  ===================================================== */
39015  #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
39016  #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
39017  #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
39018  #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
39019  #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
39020  #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
39021  #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
39022  #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
39023  #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
39024  #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
39025 /* =====================================================  P1_ERROR_MASK  ===================================================== */
39026  #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
39027  #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
39028  #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
39029  #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
39030  #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
39031  #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
39032  #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
39033  #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
39034  #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
39035  #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
39036 /* =====================================================  P2_ERROR_MASK  ===================================================== */
39037  #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Pos                                (0UL)          /*!< MSOPERR (Bit 0)                                       */
39038  #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Msk                                (0x1UL)        /*!< MSOPERR (Bitfield-Mask: 0x01)                         */
39039  #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Pos                                (1UL)          /*!< MPUNDSZ (Bit 1)                                       */
39040  #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Msk                                (0x2UL)        /*!< MPUNDSZ (Bitfield-Mask: 0x01)                         */
39041  #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Pos                                (2UL)          /*!< MPOVRSZ (Bit 2)                                       */
39042  #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Msk                                (0x4UL)        /*!< MPOVRSZ (Bitfield-Mask: 0x01)                         */
39043  #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Pos                                (3UL)          /*!< MEUNDSZ (Bit 3)                                       */
39044  #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Msk                                (0x8UL)        /*!< MEUNDSZ (Bitfield-Mask: 0x01)                         */
39045  #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Pos                                (4UL)          /*!< MEOVRSZ (Bit 4)                                       */
39046  #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Msk                                (0x10UL)       /*!< MEOVRSZ (Bitfield-Mask: 0x01)                         */
39047 /* =====================================================  CHANNEL_STATE  ===================================================== */
39048  #define R_ETHSW_CHANNEL_STATE_CH0ACT_Pos                                 (0UL)          /*!< CH0ACT (Bit 0)                                        */
39049  #define R_ETHSW_CHANNEL_STATE_CH0ACT_Msk                                 (0x1UL)        /*!< CH0ACT (Bitfield-Mask: 0x01)                          */
39050  #define R_ETHSW_CHANNEL_STATE_CH1ACT_Pos                                 (1UL)          /*!< CH1ACT (Bit 1)                                        */
39051  #define R_ETHSW_CHANNEL_STATE_CH1ACT_Msk                                 (0x2UL)        /*!< CH1ACT (Bitfield-Mask: 0x01)                          */
39052  #define R_ETHSW_CHANNEL_STATE_CH2ACT_Pos                                 (2UL)          /*!< CH2ACT (Bit 2)                                        */
39053  #define R_ETHSW_CHANNEL_STATE_CH2ACT_Msk                                 (0x4UL)        /*!< CH2ACT (Bitfield-Mask: 0x01)                          */
39054 /* ====================================================  CHANNEL_ENABLE  ===================================================== */
39055  #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Pos                                (0UL)          /*!< CH0ENA (Bit 0)                                        */
39056  #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Msk                                (0x1UL)        /*!< CH0ENA (Bitfield-Mask: 0x01)                          */
39057  #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Pos                                (1UL)          /*!< CH1ENA (Bit 1)                                        */
39058  #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Msk                                (0x2UL)        /*!< CH1ENA (Bitfield-Mask: 0x01)                          */
39059  #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Pos                                (2UL)          /*!< CH2ENA (Bit 2)                                        */
39060  #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Msk                                (0x4UL)        /*!< CH2ENA (Bitfield-Mask: 0x01)                          */
39061 /* ====================================================  CHANNEL_DISABLE  ==================================================== */
39062  #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Pos                               (0UL)          /*!< CH0DIS (Bit 0)                                        */
39063  #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Msk                               (0x1UL)        /*!< CH0DIS (Bitfield-Mask: 0x01)                          */
39064  #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Pos                               (1UL)          /*!< CH1DIS (Bit 1)                                        */
39065  #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Msk                               (0x2UL)        /*!< CH1DIS (Bitfield-Mask: 0x01)                          */
39066  #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Pos                               (2UL)          /*!< CH2DIS (Bit 2)                                        */
39067  #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Msk                               (0x4UL)        /*!< CH2DIS (Bitfield-Mask: 0x01)                          */
39068 /* =====================================================  ASI_MEM_WDATA  ===================================================== */
39069  #define R_ETHSW_ASI_MEM_WDATA_WDATA_Pos                                  (0UL)          /*!< WDATA (Bit 0)                                         */
39070  #define R_ETHSW_ASI_MEM_WDATA_WDATA_Msk                                  (0xffffffffUL) /*!< WDATA (Bitfield-Mask: 0xffffffff)                     */
39071 /* =====================================================  ASI_MEM_ADDR  ====================================================== */
39072  #define R_ETHSW_ASI_MEM_ADDR_ADDR_Pos                                    (0UL)          /*!< ADDR (Bit 0)                                          */
39073  #define R_ETHSW_ASI_MEM_ADDR_ADDR_Msk                                    (0x7fUL)       /*!< ADDR (Bitfield-Mask: 0x7f)                            */
39074  #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Pos                                 (7UL)          /*!< MEM_WEN (Bit 7)                                       */
39075  #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Msk                                 (0x80UL)       /*!< MEM_WEN (Bitfield-Mask: 0x01)                         */
39076  #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos                                 (8UL)          /*!< MEM_REQ (Bit 8)                                       */
39077  #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk                                 (0x700UL)      /*!< MEM_REQ (Bitfield-Mask: 0x07)                         */
39078 /* =====================================================  ASI_MEM_RDATA  ===================================================== */
39079  #define R_ETHSW_ASI_MEM_RDATA_RDATA_Pos                                  (0UL)          /*!< RDATA (Bit 0)                                         */
39080  #define R_ETHSW_ASI_MEM_RDATA_RDATA_Msk                                  (0xffffffffUL) /*!< RDATA (Bitfield-Mask: 0xffffffff)                     */
39081 /* ======================================================  P1_QSTMACU0  ====================================================== */
39082  #define R_ETHSW_P1_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39083  #define R_ETHSW_P1_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39084  #define R_ETHSW_P1_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39085  #define R_ETHSW_P1_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39086 /* ======================================================  P1_QSTMACU1  ====================================================== */
39087  #define R_ETHSW_P1_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39088  #define R_ETHSW_P1_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39089  #define R_ETHSW_P1_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39090  #define R_ETHSW_P1_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39091 /* ======================================================  P1_QSTMACU2  ====================================================== */
39092  #define R_ETHSW_P1_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39093  #define R_ETHSW_P1_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39094  #define R_ETHSW_P1_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39095  #define R_ETHSW_P1_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39096 /* ======================================================  P1_QSTMACU3  ====================================================== */
39097  #define R_ETHSW_P1_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39098  #define R_ETHSW_P1_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39099  #define R_ETHSW_P1_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39100  #define R_ETHSW_P1_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39101 /* ======================================================  P1_QSTMACU4  ====================================================== */
39102  #define R_ETHSW_P1_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39103  #define R_ETHSW_P1_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39104  #define R_ETHSW_P1_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39105  #define R_ETHSW_P1_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39106 /* ======================================================  P1_QSTMACU5  ====================================================== */
39107  #define R_ETHSW_P1_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39108  #define R_ETHSW_P1_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39109  #define R_ETHSW_P1_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39110  #define R_ETHSW_P1_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39111 /* ======================================================  P1_QSTMACU6  ====================================================== */
39112  #define R_ETHSW_P1_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39113  #define R_ETHSW_P1_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39114  #define R_ETHSW_P1_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39115  #define R_ETHSW_P1_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39116 /* ======================================================  P1_QSTMACU7  ====================================================== */
39117  #define R_ETHSW_P1_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39118  #define R_ETHSW_P1_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39119  #define R_ETHSW_P1_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39120  #define R_ETHSW_P1_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39121 /* ======================================================  P1_QSTMACD0  ====================================================== */
39122  #define R_ETHSW_P1_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39123  #define R_ETHSW_P1_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39124 /* ======================================================  P1_QSTMACD1  ====================================================== */
39125  #define R_ETHSW_P1_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39126  #define R_ETHSW_P1_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39127 /* ======================================================  P1_QSTMACD2  ====================================================== */
39128  #define R_ETHSW_P1_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39129  #define R_ETHSW_P1_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39130 /* ======================================================  P1_QSTMACD3  ====================================================== */
39131  #define R_ETHSW_P1_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39132  #define R_ETHSW_P1_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39133 /* ======================================================  P1_QSTMACD4  ====================================================== */
39134  #define R_ETHSW_P1_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39135  #define R_ETHSW_P1_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39136 /* ======================================================  P1_QSTMACD5  ====================================================== */
39137  #define R_ETHSW_P1_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39138  #define R_ETHSW_P1_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39139 /* ======================================================  P1_QSTMACD6  ====================================================== */
39140  #define R_ETHSW_P1_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39141  #define R_ETHSW_P1_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39142 /* ======================================================  P1_QSTMACD7  ====================================================== */
39143  #define R_ETHSW_P1_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39144  #define R_ETHSW_P1_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39145 /* ======================================================  P1_QSTMAMU0  ====================================================== */
39146  #define R_ETHSW_P1_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39147  #define R_ETHSW_P1_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39148 /* ======================================================  P1_QSTMAMU1  ====================================================== */
39149  #define R_ETHSW_P1_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39150  #define R_ETHSW_P1_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39151 /* ======================================================  P1_QSTMAMU2  ====================================================== */
39152  #define R_ETHSW_P1_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39153  #define R_ETHSW_P1_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39154 /* ======================================================  P1_QSTMAMU3  ====================================================== */
39155  #define R_ETHSW_P1_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39156  #define R_ETHSW_P1_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39157 /* ======================================================  P1_QSTMAMU4  ====================================================== */
39158  #define R_ETHSW_P1_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39159  #define R_ETHSW_P1_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39160 /* ======================================================  P1_QSTMAMU5  ====================================================== */
39161  #define R_ETHSW_P1_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39162  #define R_ETHSW_P1_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39163 /* ======================================================  P1_QSTMAMU6  ====================================================== */
39164  #define R_ETHSW_P1_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39165  #define R_ETHSW_P1_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39166 /* ======================================================  P1_QSTMAMU7  ====================================================== */
39167  #define R_ETHSW_P1_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39168  #define R_ETHSW_P1_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39169 /* ======================================================  P1_QSTMAMD0  ====================================================== */
39170  #define R_ETHSW_P1_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39171  #define R_ETHSW_P1_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39172 /* ======================================================  P1_QSTMAMD1  ====================================================== */
39173  #define R_ETHSW_P1_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39174  #define R_ETHSW_P1_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39175 /* ======================================================  P1_QSTMAMD2  ====================================================== */
39176  #define R_ETHSW_P1_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39177  #define R_ETHSW_P1_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39178 /* ======================================================  P1_QSTMAMD3  ====================================================== */
39179  #define R_ETHSW_P1_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39180  #define R_ETHSW_P1_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39181 /* ======================================================  P1_QSTMAMD4  ====================================================== */
39182  #define R_ETHSW_P1_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39183  #define R_ETHSW_P1_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39184 /* ======================================================  P1_QSTMAMD5  ====================================================== */
39185  #define R_ETHSW_P1_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39186  #define R_ETHSW_P1_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39187 /* ======================================================  P1_QSTMAMD6  ====================================================== */
39188  #define R_ETHSW_P1_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39189  #define R_ETHSW_P1_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39190 /* ======================================================  P1_QSTMAMD7  ====================================================== */
39191  #define R_ETHSW_P1_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39192  #define R_ETHSW_P1_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39193 /* ======================================================  P1_QSFTVL0  ======================================================= */
39194  #define R_ETHSW_P1_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39195  #define R_ETHSW_P1_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39196  #define R_ETHSW_P1_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39197  #define R_ETHSW_P1_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39198  #define R_ETHSW_P1_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39199  #define R_ETHSW_P1_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39200  #define R_ETHSW_P1_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39201  #define R_ETHSW_P1_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39202 /* ======================================================  P1_QSFTVL1  ======================================================= */
39203  #define R_ETHSW_P1_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39204  #define R_ETHSW_P1_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39205  #define R_ETHSW_P1_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39206  #define R_ETHSW_P1_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39207  #define R_ETHSW_P1_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39208  #define R_ETHSW_P1_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39209  #define R_ETHSW_P1_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39210  #define R_ETHSW_P1_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39211 /* ======================================================  P1_QSFTVL2  ======================================================= */
39212  #define R_ETHSW_P1_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39213  #define R_ETHSW_P1_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39214  #define R_ETHSW_P1_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39215  #define R_ETHSW_P1_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39216  #define R_ETHSW_P1_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39217  #define R_ETHSW_P1_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39218  #define R_ETHSW_P1_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39219  #define R_ETHSW_P1_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39220 /* ======================================================  P1_QSFTVL3  ======================================================= */
39221  #define R_ETHSW_P1_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39222  #define R_ETHSW_P1_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39223  #define R_ETHSW_P1_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39224  #define R_ETHSW_P1_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39225  #define R_ETHSW_P1_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39226  #define R_ETHSW_P1_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39227  #define R_ETHSW_P1_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39228  #define R_ETHSW_P1_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39229 /* ======================================================  P1_QSFTVL4  ======================================================= */
39230  #define R_ETHSW_P1_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39231  #define R_ETHSW_P1_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39232  #define R_ETHSW_P1_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39233  #define R_ETHSW_P1_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39234  #define R_ETHSW_P1_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39235  #define R_ETHSW_P1_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39236  #define R_ETHSW_P1_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39237  #define R_ETHSW_P1_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39238 /* ======================================================  P1_QSFTVL5  ======================================================= */
39239  #define R_ETHSW_P1_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39240  #define R_ETHSW_P1_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39241  #define R_ETHSW_P1_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39242  #define R_ETHSW_P1_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39243  #define R_ETHSW_P1_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39244  #define R_ETHSW_P1_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39245  #define R_ETHSW_P1_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39246  #define R_ETHSW_P1_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39247 /* ======================================================  P1_QSFTVL6  ======================================================= */
39248  #define R_ETHSW_P1_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39249  #define R_ETHSW_P1_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39250  #define R_ETHSW_P1_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39251  #define R_ETHSW_P1_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39252  #define R_ETHSW_P1_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39253  #define R_ETHSW_P1_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39254  #define R_ETHSW_P1_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39255  #define R_ETHSW_P1_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39256 /* ======================================================  P1_QSFTVL7  ======================================================= */
39257  #define R_ETHSW_P1_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39258  #define R_ETHSW_P1_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39259  #define R_ETHSW_P1_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39260  #define R_ETHSW_P1_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39261  #define R_ETHSW_P1_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39262  #define R_ETHSW_P1_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39263  #define R_ETHSW_P1_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39264  #define R_ETHSW_P1_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39265 /* ======================================================  P1_QSFTVLM0  ====================================================== */
39266  #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39267  #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39268  #define R_ETHSW_P1_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39269  #define R_ETHSW_P1_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39270  #define R_ETHSW_P1_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39271  #define R_ETHSW_P1_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39272 /* ======================================================  P1_QSFTVLM1  ====================================================== */
39273  #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39274  #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39275  #define R_ETHSW_P1_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39276  #define R_ETHSW_P1_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39277  #define R_ETHSW_P1_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39278  #define R_ETHSW_P1_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39279 /* ======================================================  P1_QSFTVLM2  ====================================================== */
39280  #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39281  #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39282  #define R_ETHSW_P1_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39283  #define R_ETHSW_P1_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39284  #define R_ETHSW_P1_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39285  #define R_ETHSW_P1_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39286 /* ======================================================  P1_QSFTVLM3  ====================================================== */
39287  #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39288  #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39289  #define R_ETHSW_P1_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39290  #define R_ETHSW_P1_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39291  #define R_ETHSW_P1_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39292  #define R_ETHSW_P1_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39293 /* ======================================================  P1_QSFTVLM4  ====================================================== */
39294  #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39295  #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39296  #define R_ETHSW_P1_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39297  #define R_ETHSW_P1_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39298  #define R_ETHSW_P1_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39299  #define R_ETHSW_P1_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39300 /* ======================================================  P1_QSFTVLM5  ====================================================== */
39301  #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39302  #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39303  #define R_ETHSW_P1_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39304  #define R_ETHSW_P1_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39305  #define R_ETHSW_P1_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39306  #define R_ETHSW_P1_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39307 /* ======================================================  P1_QSFTVLM6  ====================================================== */
39308  #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39309  #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39310  #define R_ETHSW_P1_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39311  #define R_ETHSW_P1_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39312  #define R_ETHSW_P1_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39313  #define R_ETHSW_P1_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39314 /* ======================================================  P1_QSFTVLM7  ====================================================== */
39315  #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39316  #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39317  #define R_ETHSW_P1_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39318  #define R_ETHSW_P1_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39319  #define R_ETHSW_P1_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39320  #define R_ETHSW_P1_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39321 /* ======================================================  P1_QSFTBL0  ======================================================= */
39322  #define R_ETHSW_P1_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39323  #define R_ETHSW_P1_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39324  #define R_ETHSW_P1_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39325  #define R_ETHSW_P1_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39326  #define R_ETHSW_P1_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39327  #define R_ETHSW_P1_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39328  #define R_ETHSW_P1_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39329  #define R_ETHSW_P1_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39330  #define R_ETHSW_P1_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39331  #define R_ETHSW_P1_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39332  #define R_ETHSW_P1_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39333  #define R_ETHSW_P1_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39334  #define R_ETHSW_P1_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39335  #define R_ETHSW_P1_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39336  #define R_ETHSW_P1_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39337  #define R_ETHSW_P1_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39338 /* ======================================================  P1_QSFTBL1  ======================================================= */
39339  #define R_ETHSW_P1_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39340  #define R_ETHSW_P1_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39341  #define R_ETHSW_P1_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39342  #define R_ETHSW_P1_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39343  #define R_ETHSW_P1_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39344  #define R_ETHSW_P1_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39345  #define R_ETHSW_P1_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39346  #define R_ETHSW_P1_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39347  #define R_ETHSW_P1_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39348  #define R_ETHSW_P1_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39349  #define R_ETHSW_P1_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39350  #define R_ETHSW_P1_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39351  #define R_ETHSW_P1_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39352  #define R_ETHSW_P1_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39353  #define R_ETHSW_P1_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39354  #define R_ETHSW_P1_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39355 /* ======================================================  P1_QSFTBL2  ======================================================= */
39356  #define R_ETHSW_P1_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39357  #define R_ETHSW_P1_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39358  #define R_ETHSW_P1_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39359  #define R_ETHSW_P1_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39360  #define R_ETHSW_P1_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39361  #define R_ETHSW_P1_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39362  #define R_ETHSW_P1_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39363  #define R_ETHSW_P1_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39364  #define R_ETHSW_P1_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39365  #define R_ETHSW_P1_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39366  #define R_ETHSW_P1_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39367  #define R_ETHSW_P1_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39368  #define R_ETHSW_P1_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39369  #define R_ETHSW_P1_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39370  #define R_ETHSW_P1_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39371  #define R_ETHSW_P1_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39372 /* ======================================================  P1_QSFTBL3  ======================================================= */
39373  #define R_ETHSW_P1_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39374  #define R_ETHSW_P1_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39375  #define R_ETHSW_P1_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39376  #define R_ETHSW_P1_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39377  #define R_ETHSW_P1_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39378  #define R_ETHSW_P1_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39379  #define R_ETHSW_P1_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39380  #define R_ETHSW_P1_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39381  #define R_ETHSW_P1_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39382  #define R_ETHSW_P1_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39383  #define R_ETHSW_P1_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39384  #define R_ETHSW_P1_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39385  #define R_ETHSW_P1_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39386  #define R_ETHSW_P1_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39387  #define R_ETHSW_P1_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39388  #define R_ETHSW_P1_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39389 /* ======================================================  P1_QSFTBL4  ======================================================= */
39390  #define R_ETHSW_P1_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39391  #define R_ETHSW_P1_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39392  #define R_ETHSW_P1_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39393  #define R_ETHSW_P1_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39394  #define R_ETHSW_P1_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39395  #define R_ETHSW_P1_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39396  #define R_ETHSW_P1_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39397  #define R_ETHSW_P1_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39398  #define R_ETHSW_P1_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39399  #define R_ETHSW_P1_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39400  #define R_ETHSW_P1_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39401  #define R_ETHSW_P1_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39402  #define R_ETHSW_P1_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39403  #define R_ETHSW_P1_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39404  #define R_ETHSW_P1_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39405  #define R_ETHSW_P1_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39406 /* ======================================================  P1_QSFTBL5  ======================================================= */
39407  #define R_ETHSW_P1_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39408  #define R_ETHSW_P1_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39409  #define R_ETHSW_P1_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39410  #define R_ETHSW_P1_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39411  #define R_ETHSW_P1_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39412  #define R_ETHSW_P1_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39413  #define R_ETHSW_P1_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39414  #define R_ETHSW_P1_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39415  #define R_ETHSW_P1_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39416  #define R_ETHSW_P1_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39417  #define R_ETHSW_P1_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39418  #define R_ETHSW_P1_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39419  #define R_ETHSW_P1_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39420  #define R_ETHSW_P1_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39421  #define R_ETHSW_P1_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39422  #define R_ETHSW_P1_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39423 /* ======================================================  P1_QSFTBL6  ======================================================= */
39424  #define R_ETHSW_P1_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39425  #define R_ETHSW_P1_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39426  #define R_ETHSW_P1_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39427  #define R_ETHSW_P1_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39428  #define R_ETHSW_P1_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39429  #define R_ETHSW_P1_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39430  #define R_ETHSW_P1_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39431  #define R_ETHSW_P1_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39432  #define R_ETHSW_P1_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39433  #define R_ETHSW_P1_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39434  #define R_ETHSW_P1_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39435  #define R_ETHSW_P1_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39436  #define R_ETHSW_P1_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39437  #define R_ETHSW_P1_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39438  #define R_ETHSW_P1_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39439  #define R_ETHSW_P1_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39440 /* ======================================================  P1_QSFTBL7  ======================================================= */
39441  #define R_ETHSW_P1_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39442  #define R_ETHSW_P1_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39443  #define R_ETHSW_P1_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39444  #define R_ETHSW_P1_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39445  #define R_ETHSW_P1_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39446  #define R_ETHSW_P1_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39447  #define R_ETHSW_P1_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39448  #define R_ETHSW_P1_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39449  #define R_ETHSW_P1_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39450  #define R_ETHSW_P1_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39451  #define R_ETHSW_P1_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39452  #define R_ETHSW_P1_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39453  #define R_ETHSW_P1_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39454  #define R_ETHSW_P1_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39455  #define R_ETHSW_P1_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39456  #define R_ETHSW_P1_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39457 /* =======================================================  P1_QSMFC0  ======================================================= */
39458  #define R_ETHSW_P1_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39459  #define R_ETHSW_P1_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39460 /* =======================================================  P1_QSMFC1  ======================================================= */
39461  #define R_ETHSW_P1_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39462  #define R_ETHSW_P1_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39463 /* =======================================================  P1_QSMFC2  ======================================================= */
39464  #define R_ETHSW_P1_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39465  #define R_ETHSW_P1_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39466 /* =======================================================  P1_QSMFC3  ======================================================= */
39467  #define R_ETHSW_P1_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39468  #define R_ETHSW_P1_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39469 /* =======================================================  P1_QSMFC4  ======================================================= */
39470  #define R_ETHSW_P1_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39471  #define R_ETHSW_P1_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39472 /* =======================================================  P1_QSMFC5  ======================================================= */
39473  #define R_ETHSW_P1_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39474  #define R_ETHSW_P1_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39475 /* =======================================================  P1_QSMFC6  ======================================================= */
39476  #define R_ETHSW_P1_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39477  #define R_ETHSW_P1_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39478 /* =======================================================  P1_QSMFC7  ======================================================= */
39479  #define R_ETHSW_P1_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
39480  #define R_ETHSW_P1_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
39481 /* ======================================================  P1_QMSPPC0  ======================================================= */
39482  #define R_ETHSW_P1_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39483  #define R_ETHSW_P1_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39484 /* ======================================================  P1_QMSPPC1  ======================================================= */
39485  #define R_ETHSW_P1_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39486  #define R_ETHSW_P1_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39487 /* ======================================================  P1_QMSPPC2  ======================================================= */
39488  #define R_ETHSW_P1_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39489  #define R_ETHSW_P1_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39490 /* ======================================================  P1_QMSPPC3  ======================================================= */
39491  #define R_ETHSW_P1_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39492  #define R_ETHSW_P1_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39493 /* ======================================================  P1_QMSPPC4  ======================================================= */
39494  #define R_ETHSW_P1_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39495  #define R_ETHSW_P1_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39496 /* ======================================================  P1_QMSPPC5  ======================================================= */
39497  #define R_ETHSW_P1_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39498  #define R_ETHSW_P1_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39499 /* ======================================================  P1_QMSPPC6  ======================================================= */
39500  #define R_ETHSW_P1_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39501  #define R_ETHSW_P1_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39502 /* ======================================================  P1_QMSPPC7  ======================================================= */
39503  #define R_ETHSW_P1_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
39504  #define R_ETHSW_P1_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
39505 /* ======================================================  P1_QMSRPC0  ======================================================= */
39506  #define R_ETHSW_P1_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39507  #define R_ETHSW_P1_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39508 /* ======================================================  P1_QMSRPC1  ======================================================= */
39509  #define R_ETHSW_P1_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39510  #define R_ETHSW_P1_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39511 /* ======================================================  P1_QMSRPC2  ======================================================= */
39512  #define R_ETHSW_P1_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39513  #define R_ETHSW_P1_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39514 /* ======================================================  P1_QMSRPC3  ======================================================= */
39515  #define R_ETHSW_P1_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39516  #define R_ETHSW_P1_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39517 /* ======================================================  P1_QMSRPC4  ======================================================= */
39518  #define R_ETHSW_P1_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39519  #define R_ETHSW_P1_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39520 /* ======================================================  P1_QMSRPC5  ======================================================= */
39521  #define R_ETHSW_P1_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39522  #define R_ETHSW_P1_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39523 /* ======================================================  P1_QMSRPC6  ======================================================= */
39524  #define R_ETHSW_P1_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39525  #define R_ETHSW_P1_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39526 /* ======================================================  P1_QMSRPC7  ======================================================= */
39527  #define R_ETHSW_P1_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
39528  #define R_ETHSW_P1_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
39529 /* =======================================================  P1_QGDPC0  ======================================================= */
39530  #define R_ETHSW_P1_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39531  #define R_ETHSW_P1_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39532 /* =======================================================  P1_QGDPC1  ======================================================= */
39533  #define R_ETHSW_P1_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39534  #define R_ETHSW_P1_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39535 /* =======================================================  P1_QGDPC2  ======================================================= */
39536  #define R_ETHSW_P1_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39537  #define R_ETHSW_P1_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39538 /* =======================================================  P1_QGDPC3  ======================================================= */
39539  #define R_ETHSW_P1_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39540  #define R_ETHSW_P1_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39541 /* =======================================================  P1_QGDPC4  ======================================================= */
39542  #define R_ETHSW_P1_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39543  #define R_ETHSW_P1_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39544 /* =======================================================  P1_QGDPC5  ======================================================= */
39545  #define R_ETHSW_P1_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39546  #define R_ETHSW_P1_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39547 /* =======================================================  P1_QGDPC6  ======================================================= */
39548  #define R_ETHSW_P1_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39549  #define R_ETHSW_P1_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39550 /* =======================================================  P1_QGDPC7  ======================================================= */
39551  #define R_ETHSW_P1_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
39552  #define R_ETHSW_P1_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
39553 /* ======================================================  P1_QMDESC0  ======================================================= */
39554  #define R_ETHSW_P1_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39555  #define R_ETHSW_P1_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39556  #define R_ETHSW_P1_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39557  #define R_ETHSW_P1_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39558  #define R_ETHSW_P1_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39559  #define R_ETHSW_P1_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39560 /* ======================================================  P1_QMDESC1  ======================================================= */
39561  #define R_ETHSW_P1_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39562  #define R_ETHSW_P1_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39563  #define R_ETHSW_P1_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39564  #define R_ETHSW_P1_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39565  #define R_ETHSW_P1_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39566  #define R_ETHSW_P1_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39567 /* ======================================================  P1_QMDESC2  ======================================================= */
39568  #define R_ETHSW_P1_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39569  #define R_ETHSW_P1_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39570  #define R_ETHSW_P1_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39571  #define R_ETHSW_P1_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39572  #define R_ETHSW_P1_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39573  #define R_ETHSW_P1_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39574 /* ======================================================  P1_QMDESC3  ======================================================= */
39575  #define R_ETHSW_P1_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39576  #define R_ETHSW_P1_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39577  #define R_ETHSW_P1_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39578  #define R_ETHSW_P1_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39579  #define R_ETHSW_P1_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39580  #define R_ETHSW_P1_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39581 /* ======================================================  P1_QMDESC4  ======================================================= */
39582  #define R_ETHSW_P1_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39583  #define R_ETHSW_P1_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39584  #define R_ETHSW_P1_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39585  #define R_ETHSW_P1_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39586  #define R_ETHSW_P1_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39587  #define R_ETHSW_P1_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39588 /* ======================================================  P1_QMDESC5  ======================================================= */
39589  #define R_ETHSW_P1_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39590  #define R_ETHSW_P1_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39591  #define R_ETHSW_P1_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39592  #define R_ETHSW_P1_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39593  #define R_ETHSW_P1_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39594  #define R_ETHSW_P1_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39595 /* ======================================================  P1_QMDESC6  ======================================================= */
39596  #define R_ETHSW_P1_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39597  #define R_ETHSW_P1_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39598  #define R_ETHSW_P1_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39599  #define R_ETHSW_P1_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39600  #define R_ETHSW_P1_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39601  #define R_ETHSW_P1_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39602 /* ======================================================  P1_QMDESC7  ======================================================= */
39603  #define R_ETHSW_P1_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
39604  #define R_ETHSW_P1_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
39605  #define R_ETHSW_P1_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
39606  #define R_ETHSW_P1_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
39607  #define R_ETHSW_P1_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
39608  #define R_ETHSW_P1_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
39609 /* ======================================================  P1_QMCBSC0  ======================================================= */
39610  #define R_ETHSW_P1_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39611  #define R_ETHSW_P1_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39612 /* ======================================================  P1_QMCBSC1  ======================================================= */
39613  #define R_ETHSW_P1_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39614  #define R_ETHSW_P1_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39615 /* ======================================================  P1_QMCBSC2  ======================================================= */
39616  #define R_ETHSW_P1_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39617  #define R_ETHSW_P1_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39618 /* ======================================================  P1_QMCBSC3  ======================================================= */
39619  #define R_ETHSW_P1_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39620  #define R_ETHSW_P1_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39621 /* ======================================================  P1_QMCBSC4  ======================================================= */
39622  #define R_ETHSW_P1_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39623  #define R_ETHSW_P1_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39624 /* ======================================================  P1_QMCBSC5  ======================================================= */
39625  #define R_ETHSW_P1_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39626  #define R_ETHSW_P1_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39627 /* ======================================================  P1_QMCBSC6  ======================================================= */
39628  #define R_ETHSW_P1_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39629  #define R_ETHSW_P1_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39630 /* ======================================================  P1_QMCBSC7  ======================================================= */
39631  #define R_ETHSW_P1_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
39632  #define R_ETHSW_P1_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
39633 /* ======================================================  P1_QMCIRC0  ======================================================= */
39634  #define R_ETHSW_P1_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39635  #define R_ETHSW_P1_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39636 /* ======================================================  P1_QMCIRC1  ======================================================= */
39637  #define R_ETHSW_P1_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39638  #define R_ETHSW_P1_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39639 /* ======================================================  P1_QMCIRC2  ======================================================= */
39640  #define R_ETHSW_P1_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39641  #define R_ETHSW_P1_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39642 /* ======================================================  P1_QMCIRC3  ======================================================= */
39643  #define R_ETHSW_P1_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39644  #define R_ETHSW_P1_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39645 /* ======================================================  P1_QMCIRC4  ======================================================= */
39646  #define R_ETHSW_P1_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39647  #define R_ETHSW_P1_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39648 /* ======================================================  P1_QMCIRC5  ======================================================= */
39649  #define R_ETHSW_P1_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39650  #define R_ETHSW_P1_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39651 /* ======================================================  P1_QMCIRC6  ======================================================= */
39652  #define R_ETHSW_P1_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39653  #define R_ETHSW_P1_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39654 /* ======================================================  P1_QMCIRC7  ======================================================= */
39655  #define R_ETHSW_P1_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
39656  #define R_ETHSW_P1_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
39657 /* =======================================================  P1_QMGPC0  ======================================================= */
39658  #define R_ETHSW_P1_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39659  #define R_ETHSW_P1_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39660 /* =======================================================  P1_QMGPC1  ======================================================= */
39661  #define R_ETHSW_P1_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39662  #define R_ETHSW_P1_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39663 /* =======================================================  P1_QMGPC2  ======================================================= */
39664  #define R_ETHSW_P1_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39665  #define R_ETHSW_P1_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39666 /* =======================================================  P1_QMGPC3  ======================================================= */
39667  #define R_ETHSW_P1_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39668  #define R_ETHSW_P1_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39669 /* =======================================================  P1_QMGPC4  ======================================================= */
39670  #define R_ETHSW_P1_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39671  #define R_ETHSW_P1_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39672 /* =======================================================  P1_QMGPC5  ======================================================= */
39673  #define R_ETHSW_P1_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39674  #define R_ETHSW_P1_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39675 /* =======================================================  P1_QMGPC6  ======================================================= */
39676  #define R_ETHSW_P1_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39677  #define R_ETHSW_P1_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39678 /* =======================================================  P1_QMGPC7  ======================================================= */
39679  #define R_ETHSW_P1_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
39680  #define R_ETHSW_P1_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
39681 /* =======================================================  P1_QMRPC0  ======================================================= */
39682  #define R_ETHSW_P1_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39683  #define R_ETHSW_P1_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39684 /* =======================================================  P1_QMRPC1  ======================================================= */
39685  #define R_ETHSW_P1_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39686  #define R_ETHSW_P1_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39687 /* =======================================================  P1_QMRPC2  ======================================================= */
39688  #define R_ETHSW_P1_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39689  #define R_ETHSW_P1_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39690 /* =======================================================  P1_QMRPC3  ======================================================= */
39691  #define R_ETHSW_P1_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39692  #define R_ETHSW_P1_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39693 /* =======================================================  P1_QMRPC4  ======================================================= */
39694  #define R_ETHSW_P1_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39695  #define R_ETHSW_P1_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39696 /* =======================================================  P1_QMRPC5  ======================================================= */
39697  #define R_ETHSW_P1_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39698  #define R_ETHSW_P1_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39699 /* =======================================================  P1_QMRPC6  ======================================================= */
39700  #define R_ETHSW_P1_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39701  #define R_ETHSW_P1_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39702 /* =======================================================  P1_QMRPC7  ======================================================= */
39703  #define R_ETHSW_P1_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
39704  #define R_ETHSW_P1_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
39705 /* ======================================================  P2_QSTMACU0  ====================================================== */
39706  #define R_ETHSW_P2_QSTMACU0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39707  #define R_ETHSW_P2_QSTMACU0_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39708  #define R_ETHSW_P2_QSTMACU0_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39709  #define R_ETHSW_P2_QSTMACU0_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39710 /* ======================================================  P2_QSTMACU1  ====================================================== */
39711  #define R_ETHSW_P2_QSTMACU1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39712  #define R_ETHSW_P2_QSTMACU1_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39713  #define R_ETHSW_P2_QSTMACU1_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39714  #define R_ETHSW_P2_QSTMACU1_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39715 /* ======================================================  P2_QSTMACU2  ====================================================== */
39716  #define R_ETHSW_P2_QSTMACU2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39717  #define R_ETHSW_P2_QSTMACU2_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39718  #define R_ETHSW_P2_QSTMACU2_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39719  #define R_ETHSW_P2_QSTMACU2_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39720 /* ======================================================  P2_QSTMACU3  ====================================================== */
39721  #define R_ETHSW_P2_QSTMACU3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39722  #define R_ETHSW_P2_QSTMACU3_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39723  #define R_ETHSW_P2_QSTMACU3_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39724  #define R_ETHSW_P2_QSTMACU3_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39725 /* ======================================================  P2_QSTMACU4  ====================================================== */
39726  #define R_ETHSW_P2_QSTMACU4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39727  #define R_ETHSW_P2_QSTMACU4_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39728  #define R_ETHSW_P2_QSTMACU4_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39729  #define R_ETHSW_P2_QSTMACU4_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39730 /* ======================================================  P2_QSTMACU5  ====================================================== */
39731  #define R_ETHSW_P2_QSTMACU5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39732  #define R_ETHSW_P2_QSTMACU5_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39733  #define R_ETHSW_P2_QSTMACU5_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39734  #define R_ETHSW_P2_QSTMACU5_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39735 /* ======================================================  P2_QSTMACU6  ====================================================== */
39736  #define R_ETHSW_P2_QSTMACU6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39737  #define R_ETHSW_P2_QSTMACU6_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39738  #define R_ETHSW_P2_QSTMACU6_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39739  #define R_ETHSW_P2_QSTMACU6_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39740 /* ======================================================  P2_QSTMACU7  ====================================================== */
39741  #define R_ETHSW_P2_QSTMACU7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39742  #define R_ETHSW_P2_QSTMACU7_MACA_Msk                                     (0xffffUL)     /*!< MACA (Bitfield-Mask: 0xffff)                          */
39743  #define R_ETHSW_P2_QSTMACU7_DASA_Pos                                     (16UL)         /*!< DASA (Bit 16)                                         */
39744  #define R_ETHSW_P2_QSTMACU7_DASA_Msk                                     (0x10000UL)    /*!< DASA (Bitfield-Mask: 0x01)                            */
39745 /* ======================================================  P2_QSTMACD0  ====================================================== */
39746  #define R_ETHSW_P2_QSTMACD0_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39747  #define R_ETHSW_P2_QSTMACD0_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39748 /* ======================================================  P2_QSTMACD1  ====================================================== */
39749  #define R_ETHSW_P2_QSTMACD1_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39750  #define R_ETHSW_P2_QSTMACD1_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39751 /* ======================================================  P2_QSTMACD2  ====================================================== */
39752  #define R_ETHSW_P2_QSTMACD2_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39753  #define R_ETHSW_P2_QSTMACD2_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39754 /* ======================================================  P2_QSTMACD3  ====================================================== */
39755  #define R_ETHSW_P2_QSTMACD3_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39756  #define R_ETHSW_P2_QSTMACD3_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39757 /* ======================================================  P2_QSTMACD4  ====================================================== */
39758  #define R_ETHSW_P2_QSTMACD4_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39759  #define R_ETHSW_P2_QSTMACD4_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39760 /* ======================================================  P2_QSTMACD5  ====================================================== */
39761  #define R_ETHSW_P2_QSTMACD5_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39762  #define R_ETHSW_P2_QSTMACD5_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39763 /* ======================================================  P2_QSTMACD6  ====================================================== */
39764  #define R_ETHSW_P2_QSTMACD6_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39765  #define R_ETHSW_P2_QSTMACD6_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39766 /* ======================================================  P2_QSTMACD7  ====================================================== */
39767  #define R_ETHSW_P2_QSTMACD7_MACA_Pos                                     (0UL)          /*!< MACA (Bit 0)                                          */
39768  #define R_ETHSW_P2_QSTMACD7_MACA_Msk                                     (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff)                      */
39769 /* ======================================================  P2_QSTMAMU0  ====================================================== */
39770  #define R_ETHSW_P2_QSTMAMU0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39771  #define R_ETHSW_P2_QSTMAMU0_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39772 /* ======================================================  P2_QSTMAMU1  ====================================================== */
39773  #define R_ETHSW_P2_QSTMAMU1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39774  #define R_ETHSW_P2_QSTMAMU1_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39775 /* ======================================================  P2_QSTMAMU2  ====================================================== */
39776  #define R_ETHSW_P2_QSTMAMU2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39777  #define R_ETHSW_P2_QSTMAMU2_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39778 /* ======================================================  P2_QSTMAMU3  ====================================================== */
39779  #define R_ETHSW_P2_QSTMAMU3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39780  #define R_ETHSW_P2_QSTMAMU3_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39781 /* ======================================================  P2_QSTMAMU4  ====================================================== */
39782  #define R_ETHSW_P2_QSTMAMU4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39783  #define R_ETHSW_P2_QSTMAMU4_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39784 /* ======================================================  P2_QSTMAMU5  ====================================================== */
39785  #define R_ETHSW_P2_QSTMAMU5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39786  #define R_ETHSW_P2_QSTMAMU5_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39787 /* ======================================================  P2_QSTMAMU6  ====================================================== */
39788  #define R_ETHSW_P2_QSTMAMU6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39789  #define R_ETHSW_P2_QSTMAMU6_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39790 /* ======================================================  P2_QSTMAMU7  ====================================================== */
39791  #define R_ETHSW_P2_QSTMAMU7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39792  #define R_ETHSW_P2_QSTMAMU7_MACAM_Msk                                    (0xffffUL)     /*!< MACAM (Bitfield-Mask: 0xffff)                         */
39793 /* ======================================================  P2_QSTMAMD0  ====================================================== */
39794  #define R_ETHSW_P2_QSTMAMD0_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39795  #define R_ETHSW_P2_QSTMAMD0_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39796 /* ======================================================  P2_QSTMAMD1  ====================================================== */
39797  #define R_ETHSW_P2_QSTMAMD1_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39798  #define R_ETHSW_P2_QSTMAMD1_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39799 /* ======================================================  P2_QSTMAMD2  ====================================================== */
39800  #define R_ETHSW_P2_QSTMAMD2_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39801  #define R_ETHSW_P2_QSTMAMD2_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39802 /* ======================================================  P2_QSTMAMD3  ====================================================== */
39803  #define R_ETHSW_P2_QSTMAMD3_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39804  #define R_ETHSW_P2_QSTMAMD3_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39805 /* ======================================================  P2_QSTMAMD4  ====================================================== */
39806  #define R_ETHSW_P2_QSTMAMD4_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39807  #define R_ETHSW_P2_QSTMAMD4_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39808 /* ======================================================  P2_QSTMAMD5  ====================================================== */
39809  #define R_ETHSW_P2_QSTMAMD5_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39810  #define R_ETHSW_P2_QSTMAMD5_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39811 /* ======================================================  P2_QSTMAMD6  ====================================================== */
39812  #define R_ETHSW_P2_QSTMAMD6_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39813  #define R_ETHSW_P2_QSTMAMD6_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39814 /* ======================================================  P2_QSTMAMD7  ====================================================== */
39815  #define R_ETHSW_P2_QSTMAMD7_MACAM_Pos                                    (0UL)          /*!< MACAM (Bit 0)                                         */
39816  #define R_ETHSW_P2_QSTMAMD7_MACAM_Msk                                    (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff)                     */
39817 /* ======================================================  P2_QSFTVL0  ======================================================= */
39818  #define R_ETHSW_P2_QSFTVL0_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39819  #define R_ETHSW_P2_QSFTVL0_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39820  #define R_ETHSW_P2_QSFTVL0_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39821  #define R_ETHSW_P2_QSFTVL0_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39822  #define R_ETHSW_P2_QSFTVL0_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39823  #define R_ETHSW_P2_QSFTVL0_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39824  #define R_ETHSW_P2_QSFTVL0_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39825  #define R_ETHSW_P2_QSFTVL0_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39826 /* ======================================================  P2_QSFTVL1  ======================================================= */
39827  #define R_ETHSW_P2_QSFTVL1_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39828  #define R_ETHSW_P2_QSFTVL1_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39829  #define R_ETHSW_P2_QSFTVL1_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39830  #define R_ETHSW_P2_QSFTVL1_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39831  #define R_ETHSW_P2_QSFTVL1_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39832  #define R_ETHSW_P2_QSFTVL1_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39833  #define R_ETHSW_P2_QSFTVL1_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39834  #define R_ETHSW_P2_QSFTVL1_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39835 /* ======================================================  P2_QSFTVL2  ======================================================= */
39836  #define R_ETHSW_P2_QSFTVL2_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39837  #define R_ETHSW_P2_QSFTVL2_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39838  #define R_ETHSW_P2_QSFTVL2_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39839  #define R_ETHSW_P2_QSFTVL2_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39840  #define R_ETHSW_P2_QSFTVL2_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39841  #define R_ETHSW_P2_QSFTVL2_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39842  #define R_ETHSW_P2_QSFTVL2_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39843  #define R_ETHSW_P2_QSFTVL2_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39844 /* ======================================================  P2_QSFTVL3  ======================================================= */
39845  #define R_ETHSW_P2_QSFTVL3_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39846  #define R_ETHSW_P2_QSFTVL3_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39847  #define R_ETHSW_P2_QSFTVL3_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39848  #define R_ETHSW_P2_QSFTVL3_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39849  #define R_ETHSW_P2_QSFTVL3_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39850  #define R_ETHSW_P2_QSFTVL3_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39851  #define R_ETHSW_P2_QSFTVL3_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39852  #define R_ETHSW_P2_QSFTVL3_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39853 /* ======================================================  P2_QSFTVL4  ======================================================= */
39854  #define R_ETHSW_P2_QSFTVL4_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39855  #define R_ETHSW_P2_QSFTVL4_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39856  #define R_ETHSW_P2_QSFTVL4_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39857  #define R_ETHSW_P2_QSFTVL4_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39858  #define R_ETHSW_P2_QSFTVL4_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39859  #define R_ETHSW_P2_QSFTVL4_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39860  #define R_ETHSW_P2_QSFTVL4_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39861  #define R_ETHSW_P2_QSFTVL4_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39862 /* ======================================================  P2_QSFTVL5  ======================================================= */
39863  #define R_ETHSW_P2_QSFTVL5_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39864  #define R_ETHSW_P2_QSFTVL5_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39865  #define R_ETHSW_P2_QSFTVL5_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39866  #define R_ETHSW_P2_QSFTVL5_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39867  #define R_ETHSW_P2_QSFTVL5_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39868  #define R_ETHSW_P2_QSFTVL5_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39869  #define R_ETHSW_P2_QSFTVL5_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39870  #define R_ETHSW_P2_QSFTVL5_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39871 /* ======================================================  P2_QSFTVL6  ======================================================= */
39872  #define R_ETHSW_P2_QSFTVL6_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39873  #define R_ETHSW_P2_QSFTVL6_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39874  #define R_ETHSW_P2_QSFTVL6_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39875  #define R_ETHSW_P2_QSFTVL6_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39876  #define R_ETHSW_P2_QSFTVL6_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39877  #define R_ETHSW_P2_QSFTVL6_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39878  #define R_ETHSW_P2_QSFTVL6_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39879  #define R_ETHSW_P2_QSFTVL6_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39880 /* ======================================================  P2_QSFTVL7  ======================================================= */
39881  #define R_ETHSW_P2_QSFTVL7_VLANID_Pos                                    (0UL)          /*!< VLANID (Bit 0)                                        */
39882  #define R_ETHSW_P2_QSFTVL7_VLANID_Msk                                    (0xfffUL)      /*!< VLANID (Bitfield-Mask: 0xfff)                         */
39883  #define R_ETHSW_P2_QSFTVL7_DEI_Pos                                       (12UL)         /*!< DEI (Bit 12)                                          */
39884  #define R_ETHSW_P2_QSFTVL7_DEI_Msk                                       (0x1000UL)     /*!< DEI (Bitfield-Mask: 0x01)                             */
39885  #define R_ETHSW_P2_QSFTVL7_PCP_Pos                                       (13UL)         /*!< PCP (Bit 13)                                          */
39886  #define R_ETHSW_P2_QSFTVL7_PCP_Msk                                       (0xe000UL)     /*!< PCP (Bitfield-Mask: 0x07)                             */
39887  #define R_ETHSW_P2_QSFTVL7_TAGMD_Pos                                     (16UL)         /*!< TAGMD (Bit 16)                                        */
39888  #define R_ETHSW_P2_QSFTVL7_TAGMD_Msk                                     (0x30000UL)    /*!< TAGMD (Bitfield-Mask: 0x03)                           */
39889 /* ======================================================  P2_QSFTVLM0  ====================================================== */
39890  #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39891  #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39892  #define R_ETHSW_P2_QSFTVLM0_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39893  #define R_ETHSW_P2_QSFTVLM0_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39894  #define R_ETHSW_P2_QSFTVLM0_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39895  #define R_ETHSW_P2_QSFTVLM0_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39896 /* ======================================================  P2_QSFTVLM1  ====================================================== */
39897  #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39898  #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39899  #define R_ETHSW_P2_QSFTVLM1_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39900  #define R_ETHSW_P2_QSFTVLM1_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39901  #define R_ETHSW_P2_QSFTVLM1_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39902  #define R_ETHSW_P2_QSFTVLM1_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39903 /* ======================================================  P2_QSFTVLM2  ====================================================== */
39904  #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39905  #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39906  #define R_ETHSW_P2_QSFTVLM2_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39907  #define R_ETHSW_P2_QSFTVLM2_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39908  #define R_ETHSW_P2_QSFTVLM2_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39909  #define R_ETHSW_P2_QSFTVLM2_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39910 /* ======================================================  P2_QSFTVLM3  ====================================================== */
39911  #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39912  #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39913  #define R_ETHSW_P2_QSFTVLM3_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39914  #define R_ETHSW_P2_QSFTVLM3_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39915  #define R_ETHSW_P2_QSFTVLM3_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39916  #define R_ETHSW_P2_QSFTVLM3_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39917 /* ======================================================  P2_QSFTVLM4  ====================================================== */
39918  #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39919  #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39920  #define R_ETHSW_P2_QSFTVLM4_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39921  #define R_ETHSW_P2_QSFTVLM4_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39922  #define R_ETHSW_P2_QSFTVLM4_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39923  #define R_ETHSW_P2_QSFTVLM4_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39924 /* ======================================================  P2_QSFTVLM5  ====================================================== */
39925  #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39926  #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39927  #define R_ETHSW_P2_QSFTVLM5_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39928  #define R_ETHSW_P2_QSFTVLM5_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39929  #define R_ETHSW_P2_QSFTVLM5_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39930  #define R_ETHSW_P2_QSFTVLM5_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39931 /* ======================================================  P2_QSFTVLM6  ====================================================== */
39932  #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39933  #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39934  #define R_ETHSW_P2_QSFTVLM6_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39935  #define R_ETHSW_P2_QSFTVLM6_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39936  #define R_ETHSW_P2_QSFTVLM6_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39937  #define R_ETHSW_P2_QSFTVLM6_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39938 /* ======================================================  P2_QSFTVLM7  ====================================================== */
39939  #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Pos                                  (0UL)          /*!< VLANIDM (Bit 0)                                       */
39940  #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Msk                                  (0xfffUL)      /*!< VLANIDM (Bitfield-Mask: 0xfff)                        */
39941  #define R_ETHSW_P2_QSFTVLM7_DEIM_Pos                                     (12UL)         /*!< DEIM (Bit 12)                                         */
39942  #define R_ETHSW_P2_QSFTVLM7_DEIM_Msk                                     (0x1000UL)     /*!< DEIM (Bitfield-Mask: 0x01)                            */
39943  #define R_ETHSW_P2_QSFTVLM7_PCPM_Pos                                     (13UL)         /*!< PCPM (Bit 13)                                         */
39944  #define R_ETHSW_P2_QSFTVLM7_PCPM_Msk                                     (0xe000UL)     /*!< PCPM (Bitfield-Mask: 0x07)                            */
39945 /* ======================================================  P2_QSFTBL0  ======================================================= */
39946  #define R_ETHSW_P2_QSFTBL0_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39947  #define R_ETHSW_P2_QSFTBL0_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39948  #define R_ETHSW_P2_QSFTBL0_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39949  #define R_ETHSW_P2_QSFTBL0_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39950  #define R_ETHSW_P2_QSFTBL0_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39951  #define R_ETHSW_P2_QSFTBL0_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39952  #define R_ETHSW_P2_QSFTBL0_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39953  #define R_ETHSW_P2_QSFTBL0_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39954  #define R_ETHSW_P2_QSFTBL0_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39955  #define R_ETHSW_P2_QSFTBL0_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39956  #define R_ETHSW_P2_QSFTBL0_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39957  #define R_ETHSW_P2_QSFTBL0_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39958  #define R_ETHSW_P2_QSFTBL0_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39959  #define R_ETHSW_P2_QSFTBL0_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39960  #define R_ETHSW_P2_QSFTBL0_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39961  #define R_ETHSW_P2_QSFTBL0_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39962 /* ======================================================  P2_QSFTBL1  ======================================================= */
39963  #define R_ETHSW_P2_QSFTBL1_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39964  #define R_ETHSW_P2_QSFTBL1_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39965  #define R_ETHSW_P2_QSFTBL1_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39966  #define R_ETHSW_P2_QSFTBL1_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39967  #define R_ETHSW_P2_QSFTBL1_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39968  #define R_ETHSW_P2_QSFTBL1_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39969  #define R_ETHSW_P2_QSFTBL1_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39970  #define R_ETHSW_P2_QSFTBL1_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39971  #define R_ETHSW_P2_QSFTBL1_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39972  #define R_ETHSW_P2_QSFTBL1_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39973  #define R_ETHSW_P2_QSFTBL1_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39974  #define R_ETHSW_P2_QSFTBL1_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39975  #define R_ETHSW_P2_QSFTBL1_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39976  #define R_ETHSW_P2_QSFTBL1_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39977  #define R_ETHSW_P2_QSFTBL1_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39978  #define R_ETHSW_P2_QSFTBL1_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39979 /* ======================================================  P2_QSFTBL2  ======================================================= */
39980  #define R_ETHSW_P2_QSFTBL2_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39981  #define R_ETHSW_P2_QSFTBL2_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39982  #define R_ETHSW_P2_QSFTBL2_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
39983  #define R_ETHSW_P2_QSFTBL2_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
39984  #define R_ETHSW_P2_QSFTBL2_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
39985  #define R_ETHSW_P2_QSFTBL2_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
39986  #define R_ETHSW_P2_QSFTBL2_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
39987  #define R_ETHSW_P2_QSFTBL2_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
39988  #define R_ETHSW_P2_QSFTBL2_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
39989  #define R_ETHSW_P2_QSFTBL2_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
39990  #define R_ETHSW_P2_QSFTBL2_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
39991  #define R_ETHSW_P2_QSFTBL2_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
39992  #define R_ETHSW_P2_QSFTBL2_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
39993  #define R_ETHSW_P2_QSFTBL2_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
39994  #define R_ETHSW_P2_QSFTBL2_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
39995  #define R_ETHSW_P2_QSFTBL2_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
39996 /* ======================================================  P2_QSFTBL3  ======================================================= */
39997  #define R_ETHSW_P2_QSFTBL3_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
39998  #define R_ETHSW_P2_QSFTBL3_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
39999  #define R_ETHSW_P2_QSFTBL3_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
40000  #define R_ETHSW_P2_QSFTBL3_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
40001  #define R_ETHSW_P2_QSFTBL3_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
40002  #define R_ETHSW_P2_QSFTBL3_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
40003  #define R_ETHSW_P2_QSFTBL3_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
40004  #define R_ETHSW_P2_QSFTBL3_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
40005  #define R_ETHSW_P2_QSFTBL3_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
40006  #define R_ETHSW_P2_QSFTBL3_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
40007  #define R_ETHSW_P2_QSFTBL3_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
40008  #define R_ETHSW_P2_QSFTBL3_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
40009  #define R_ETHSW_P2_QSFTBL3_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
40010  #define R_ETHSW_P2_QSFTBL3_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
40011  #define R_ETHSW_P2_QSFTBL3_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
40012  #define R_ETHSW_P2_QSFTBL3_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
40013 /* ======================================================  P2_QSFTBL4  ======================================================= */
40014  #define R_ETHSW_P2_QSFTBL4_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
40015  #define R_ETHSW_P2_QSFTBL4_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
40016  #define R_ETHSW_P2_QSFTBL4_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
40017  #define R_ETHSW_P2_QSFTBL4_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
40018  #define R_ETHSW_P2_QSFTBL4_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
40019  #define R_ETHSW_P2_QSFTBL4_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
40020  #define R_ETHSW_P2_QSFTBL4_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
40021  #define R_ETHSW_P2_QSFTBL4_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
40022  #define R_ETHSW_P2_QSFTBL4_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
40023  #define R_ETHSW_P2_QSFTBL4_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
40024  #define R_ETHSW_P2_QSFTBL4_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
40025  #define R_ETHSW_P2_QSFTBL4_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
40026  #define R_ETHSW_P2_QSFTBL4_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
40027  #define R_ETHSW_P2_QSFTBL4_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
40028  #define R_ETHSW_P2_QSFTBL4_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
40029  #define R_ETHSW_P2_QSFTBL4_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
40030 /* ======================================================  P2_QSFTBL5  ======================================================= */
40031  #define R_ETHSW_P2_QSFTBL5_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
40032  #define R_ETHSW_P2_QSFTBL5_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
40033  #define R_ETHSW_P2_QSFTBL5_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
40034  #define R_ETHSW_P2_QSFTBL5_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
40035  #define R_ETHSW_P2_QSFTBL5_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
40036  #define R_ETHSW_P2_QSFTBL5_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
40037  #define R_ETHSW_P2_QSFTBL5_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
40038  #define R_ETHSW_P2_QSFTBL5_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
40039  #define R_ETHSW_P2_QSFTBL5_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
40040  #define R_ETHSW_P2_QSFTBL5_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
40041  #define R_ETHSW_P2_QSFTBL5_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
40042  #define R_ETHSW_P2_QSFTBL5_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
40043  #define R_ETHSW_P2_QSFTBL5_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
40044  #define R_ETHSW_P2_QSFTBL5_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
40045  #define R_ETHSW_P2_QSFTBL5_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
40046  #define R_ETHSW_P2_QSFTBL5_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
40047 /* ======================================================  P2_QSFTBL6  ======================================================= */
40048  #define R_ETHSW_P2_QSFTBL6_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
40049  #define R_ETHSW_P2_QSFTBL6_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
40050  #define R_ETHSW_P2_QSFTBL6_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
40051  #define R_ETHSW_P2_QSFTBL6_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
40052  #define R_ETHSW_P2_QSFTBL6_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
40053  #define R_ETHSW_P2_QSFTBL6_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
40054  #define R_ETHSW_P2_QSFTBL6_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
40055  #define R_ETHSW_P2_QSFTBL6_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
40056  #define R_ETHSW_P2_QSFTBL6_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
40057  #define R_ETHSW_P2_QSFTBL6_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
40058  #define R_ETHSW_P2_QSFTBL6_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
40059  #define R_ETHSW_P2_QSFTBL6_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
40060  #define R_ETHSW_P2_QSFTBL6_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
40061  #define R_ETHSW_P2_QSFTBL6_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
40062  #define R_ETHSW_P2_QSFTBL6_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
40063  #define R_ETHSW_P2_QSFTBL6_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
40064 /* ======================================================  P2_QSFTBL7  ======================================================= */
40065  #define R_ETHSW_P2_QSFTBL7_QSTE_Pos                                      (0UL)          /*!< QSTE (Bit 0)                                          */
40066  #define R_ETHSW_P2_QSFTBL7_QSTE_Msk                                      (0x1UL)        /*!< QSTE (Bitfield-Mask: 0x01)                            */
40067  #define R_ETHSW_P2_QSFTBL7_GAID_Pos                                      (4UL)          /*!< GAID (Bit 4)                                          */
40068  #define R_ETHSW_P2_QSFTBL7_GAID_Msk                                      (0x70UL)       /*!< GAID (Bitfield-Mask: 0x07)                            */
40069  #define R_ETHSW_P2_QSFTBL7_GAIDV_Pos                                     (7UL)          /*!< GAIDV (Bit 7)                                         */
40070  #define R_ETHSW_P2_QSFTBL7_GAIDV_Msk                                     (0x80UL)       /*!< GAIDV (Bitfield-Mask: 0x01)                           */
40071  #define R_ETHSW_P2_QSFTBL7_MEID_Pos                                      (8UL)          /*!< MEID (Bit 8)                                          */
40072  #define R_ETHSW_P2_QSFTBL7_MEID_Msk                                      (0x700UL)      /*!< MEID (Bitfield-Mask: 0x07)                            */
40073  #define R_ETHSW_P2_QSFTBL7_MEIDV_Pos                                     (12UL)         /*!< MEIDV (Bit 12)                                        */
40074  #define R_ETHSW_P2_QSFTBL7_MEIDV_Msk                                     (0x1000UL)     /*!< MEIDV (Bitfield-Mask: 0x01)                           */
40075  #define R_ETHSW_P2_QSFTBL7_MSDU_Pos                                      (16UL)         /*!< MSDU (Bit 16)                                         */
40076  #define R_ETHSW_P2_QSFTBL7_MSDU_Msk                                      (0x7ff0000UL)  /*!< MSDU (Bitfield-Mask: 0x7ff)                           */
40077  #define R_ETHSW_P2_QSFTBL7_MSDUE_Pos                                     (27UL)         /*!< MSDUE (Bit 27)                                        */
40078  #define R_ETHSW_P2_QSFTBL7_MSDUE_Msk                                     (0x8000000UL)  /*!< MSDUE (Bitfield-Mask: 0x01)                           */
40079  #define R_ETHSW_P2_QSFTBL7_QSMSM_Pos                                     (28UL)         /*!< QSMSM (Bit 28)                                        */
40080  #define R_ETHSW_P2_QSFTBL7_QSMSM_Msk                                     (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01)                           */
40081 /* =======================================================  P2_QSMFC0  ======================================================= */
40082  #define R_ETHSW_P2_QSMFC0_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40083  #define R_ETHSW_P2_QSMFC0_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40084 /* =======================================================  P2_QSMFC1  ======================================================= */
40085  #define R_ETHSW_P2_QSMFC1_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40086  #define R_ETHSW_P2_QSMFC1_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40087 /* =======================================================  P2_QSMFC2  ======================================================= */
40088  #define R_ETHSW_P2_QSMFC2_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40089  #define R_ETHSW_P2_QSMFC2_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40090 /* =======================================================  P2_QSMFC3  ======================================================= */
40091  #define R_ETHSW_P2_QSMFC3_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40092  #define R_ETHSW_P2_QSMFC3_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40093 /* =======================================================  P2_QSMFC4  ======================================================= */
40094  #define R_ETHSW_P2_QSMFC4_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40095  #define R_ETHSW_P2_QSMFC4_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40096 /* =======================================================  P2_QSMFC5  ======================================================= */
40097  #define R_ETHSW_P2_QSMFC5_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40098  #define R_ETHSW_P2_QSMFC5_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40099 /* =======================================================  P2_QSMFC6  ======================================================= */
40100  #define R_ETHSW_P2_QSMFC6_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40101  #define R_ETHSW_P2_QSMFC6_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40102 /* =======================================================  P2_QSMFC7  ======================================================= */
40103  #define R_ETHSW_P2_QSMFC7_QSMFC_Pos                                      (0UL)          /*!< QSMFC (Bit 0)                                         */
40104  #define R_ETHSW_P2_QSMFC7_QSMFC_Msk                                      (0xffffUL)     /*!< QSMFC (Bitfield-Mask: 0xffff)                         */
40105 /* ======================================================  P2_QMSPPC0  ======================================================= */
40106  #define R_ETHSW_P2_QMSPPC0_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40107  #define R_ETHSW_P2_QMSPPC0_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40108 /* ======================================================  P2_QMSPPC1  ======================================================= */
40109  #define R_ETHSW_P2_QMSPPC1_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40110  #define R_ETHSW_P2_QMSPPC1_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40111 /* ======================================================  P2_QMSPPC2  ======================================================= */
40112  #define R_ETHSW_P2_QMSPPC2_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40113  #define R_ETHSW_P2_QMSPPC2_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40114 /* ======================================================  P2_QMSPPC3  ======================================================= */
40115  #define R_ETHSW_P2_QMSPPC3_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40116  #define R_ETHSW_P2_QMSPPC3_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40117 /* ======================================================  P2_QMSPPC4  ======================================================= */
40118  #define R_ETHSW_P2_QMSPPC4_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40119  #define R_ETHSW_P2_QMSPPC4_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40120 /* ======================================================  P2_QMSPPC5  ======================================================= */
40121  #define R_ETHSW_P2_QMSPPC5_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40122  #define R_ETHSW_P2_QMSPPC5_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40123 /* ======================================================  P2_QMSPPC6  ======================================================= */
40124  #define R_ETHSW_P2_QMSPPC6_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40125  #define R_ETHSW_P2_QMSPPC6_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40126 /* ======================================================  P2_QMSPPC7  ======================================================= */
40127  #define R_ETHSW_P2_QMSPPC7_QMSPPC_Pos                                    (0UL)          /*!< QMSPPC (Bit 0)                                        */
40128  #define R_ETHSW_P2_QMSPPC7_QMSPPC_Msk                                    (0xffffUL)     /*!< QMSPPC (Bitfield-Mask: 0xffff)                        */
40129 /* ======================================================  P2_QMSRPC0  ======================================================= */
40130  #define R_ETHSW_P2_QMSRPC0_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40131  #define R_ETHSW_P2_QMSRPC0_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40132 /* ======================================================  P2_QMSRPC1  ======================================================= */
40133  #define R_ETHSW_P2_QMSRPC1_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40134  #define R_ETHSW_P2_QMSRPC1_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40135 /* ======================================================  P2_QMSRPC2  ======================================================= */
40136  #define R_ETHSW_P2_QMSRPC2_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40137  #define R_ETHSW_P2_QMSRPC2_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40138 /* ======================================================  P2_QMSRPC3  ======================================================= */
40139  #define R_ETHSW_P2_QMSRPC3_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40140  #define R_ETHSW_P2_QMSRPC3_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40141 /* ======================================================  P2_QMSRPC4  ======================================================= */
40142  #define R_ETHSW_P2_QMSRPC4_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40143  #define R_ETHSW_P2_QMSRPC4_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40144 /* ======================================================  P2_QMSRPC5  ======================================================= */
40145  #define R_ETHSW_P2_QMSRPC5_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40146  #define R_ETHSW_P2_QMSRPC5_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40147 /* ======================================================  P2_QMSRPC6  ======================================================= */
40148  #define R_ETHSW_P2_QMSRPC6_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40149  #define R_ETHSW_P2_QMSRPC6_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40150 /* ======================================================  P2_QMSRPC7  ======================================================= */
40151  #define R_ETHSW_P2_QMSRPC7_QMSRPC_Pos                                    (0UL)          /*!< QMSRPC (Bit 0)                                        */
40152  #define R_ETHSW_P2_QMSRPC7_QMSRPC_Msk                                    (0xffffUL)     /*!< QMSRPC (Bitfield-Mask: 0xffff)                        */
40153 /* =======================================================  P2_QGDPC0  ======================================================= */
40154  #define R_ETHSW_P2_QGDPC0_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40155  #define R_ETHSW_P2_QGDPC0_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40156 /* =======================================================  P2_QGDPC1  ======================================================= */
40157  #define R_ETHSW_P2_QGDPC1_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40158  #define R_ETHSW_P2_QGDPC1_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40159 /* =======================================================  P2_QGDPC2  ======================================================= */
40160  #define R_ETHSW_P2_QGDPC2_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40161  #define R_ETHSW_P2_QGDPC2_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40162 /* =======================================================  P2_QGDPC3  ======================================================= */
40163  #define R_ETHSW_P2_QGDPC3_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40164  #define R_ETHSW_P2_QGDPC3_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40165 /* =======================================================  P2_QGDPC4  ======================================================= */
40166  #define R_ETHSW_P2_QGDPC4_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40167  #define R_ETHSW_P2_QGDPC4_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40168 /* =======================================================  P2_QGDPC5  ======================================================= */
40169  #define R_ETHSW_P2_QGDPC5_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40170  #define R_ETHSW_P2_QGDPC5_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40171 /* =======================================================  P2_QGDPC6  ======================================================= */
40172  #define R_ETHSW_P2_QGDPC6_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40173  #define R_ETHSW_P2_QGDPC6_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40174 /* =======================================================  P2_QGDPC7  ======================================================= */
40175  #define R_ETHSW_P2_QGDPC7_QGDPC_Pos                                      (0UL)          /*!< QGDPC (Bit 0)                                         */
40176  #define R_ETHSW_P2_QGDPC7_QGDPC_Msk                                      (0xffffUL)     /*!< QGDPC (Bitfield-Mask: 0xffff)                         */
40177 /* ======================================================  P2_QMDESC0  ======================================================= */
40178  #define R_ETHSW_P2_QMDESC0_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40179  #define R_ETHSW_P2_QMDESC0_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40180  #define R_ETHSW_P2_QMDESC0_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40181  #define R_ETHSW_P2_QMDESC0_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40182  #define R_ETHSW_P2_QMDESC0_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40183  #define R_ETHSW_P2_QMDESC0_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40184 /* ======================================================  P2_QMDESC1  ======================================================= */
40185  #define R_ETHSW_P2_QMDESC1_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40186  #define R_ETHSW_P2_QMDESC1_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40187  #define R_ETHSW_P2_QMDESC1_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40188  #define R_ETHSW_P2_QMDESC1_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40189  #define R_ETHSW_P2_QMDESC1_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40190  #define R_ETHSW_P2_QMDESC1_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40191 /* ======================================================  P2_QMDESC2  ======================================================= */
40192  #define R_ETHSW_P2_QMDESC2_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40193  #define R_ETHSW_P2_QMDESC2_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40194  #define R_ETHSW_P2_QMDESC2_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40195  #define R_ETHSW_P2_QMDESC2_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40196  #define R_ETHSW_P2_QMDESC2_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40197  #define R_ETHSW_P2_QMDESC2_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40198 /* ======================================================  P2_QMDESC3  ======================================================= */
40199  #define R_ETHSW_P2_QMDESC3_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40200  #define R_ETHSW_P2_QMDESC3_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40201  #define R_ETHSW_P2_QMDESC3_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40202  #define R_ETHSW_P2_QMDESC3_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40203  #define R_ETHSW_P2_QMDESC3_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40204  #define R_ETHSW_P2_QMDESC3_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40205 /* ======================================================  P2_QMDESC4  ======================================================= */
40206  #define R_ETHSW_P2_QMDESC4_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40207  #define R_ETHSW_P2_QMDESC4_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40208  #define R_ETHSW_P2_QMDESC4_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40209  #define R_ETHSW_P2_QMDESC4_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40210  #define R_ETHSW_P2_QMDESC4_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40211  #define R_ETHSW_P2_QMDESC4_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40212 /* ======================================================  P2_QMDESC5  ======================================================= */
40213  #define R_ETHSW_P2_QMDESC5_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40214  #define R_ETHSW_P2_QMDESC5_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40215  #define R_ETHSW_P2_QMDESC5_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40216  #define R_ETHSW_P2_QMDESC5_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40217  #define R_ETHSW_P2_QMDESC5_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40218  #define R_ETHSW_P2_QMDESC5_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40219 /* ======================================================  P2_QMDESC6  ======================================================= */
40220  #define R_ETHSW_P2_QMDESC6_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40221  #define R_ETHSW_P2_QMDESC6_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40222  #define R_ETHSW_P2_QMDESC6_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40223  #define R_ETHSW_P2_QMDESC6_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40224  #define R_ETHSW_P2_QMDESC6_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40225  #define R_ETHSW_P2_QMDESC6_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40226 /* ======================================================  P2_QMDESC7  ======================================================= */
40227  #define R_ETHSW_P2_QMDESC7_RFD_Pos                                       (0UL)          /*!< RFD (Bit 0)                                           */
40228  #define R_ETHSW_P2_QMDESC7_RFD_Msk                                       (0x1UL)        /*!< RFD (Bitfield-Mask: 0x01)                             */
40229  #define R_ETHSW_P2_QMDESC7_MM_Pos                                        (1UL)          /*!< MM (Bit 1)                                            */
40230  #define R_ETHSW_P2_QMDESC7_MM_Msk                                        (0x2UL)        /*!< MM (Bitfield-Mask: 0x01)                              */
40231  #define R_ETHSW_P2_QMDESC7_CF_Pos                                        (2UL)          /*!< CF (Bit 2)                                            */
40232  #define R_ETHSW_P2_QMDESC7_CF_Msk                                        (0x4UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
40233 /* ======================================================  P2_QMCBSC0  ======================================================= */
40234  #define R_ETHSW_P2_QMCBSC0_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40235  #define R_ETHSW_P2_QMCBSC0_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40236 /* ======================================================  P2_QMCBSC1  ======================================================= */
40237  #define R_ETHSW_P2_QMCBSC1_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40238  #define R_ETHSW_P2_QMCBSC1_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40239 /* ======================================================  P2_QMCBSC2  ======================================================= */
40240  #define R_ETHSW_P2_QMCBSC2_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40241  #define R_ETHSW_P2_QMCBSC2_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40242 /* ======================================================  P2_QMCBSC3  ======================================================= */
40243  #define R_ETHSW_P2_QMCBSC3_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40244  #define R_ETHSW_P2_QMCBSC3_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40245 /* ======================================================  P2_QMCBSC4  ======================================================= */
40246  #define R_ETHSW_P2_QMCBSC4_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40247  #define R_ETHSW_P2_QMCBSC4_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40248 /* ======================================================  P2_QMCBSC5  ======================================================= */
40249  #define R_ETHSW_P2_QMCBSC5_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40250  #define R_ETHSW_P2_QMCBSC5_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40251 /* ======================================================  P2_QMCBSC6  ======================================================= */
40252  #define R_ETHSW_P2_QMCBSC6_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40253  #define R_ETHSW_P2_QMCBSC6_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40254 /* ======================================================  P2_QMCBSC7  ======================================================= */
40255  #define R_ETHSW_P2_QMCBSC7_CBS_Pos                                       (0UL)          /*!< CBS (Bit 0)                                           */
40256  #define R_ETHSW_P2_QMCBSC7_CBS_Msk                                       (0x3ffffUL)    /*!< CBS (Bitfield-Mask: 0x3ffff)                          */
40257 /* ======================================================  P2_QMCIRC0  ======================================================= */
40258  #define R_ETHSW_P2_QMCIRC0_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40259  #define R_ETHSW_P2_QMCIRC0_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40260 /* ======================================================  P2_QMCIRC1  ======================================================= */
40261  #define R_ETHSW_P2_QMCIRC1_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40262  #define R_ETHSW_P2_QMCIRC1_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40263 /* ======================================================  P2_QMCIRC2  ======================================================= */
40264  #define R_ETHSW_P2_QMCIRC2_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40265  #define R_ETHSW_P2_QMCIRC2_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40266 /* ======================================================  P2_QMCIRC3  ======================================================= */
40267  #define R_ETHSW_P2_QMCIRC3_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40268  #define R_ETHSW_P2_QMCIRC3_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40269 /* ======================================================  P2_QMCIRC4  ======================================================= */
40270  #define R_ETHSW_P2_QMCIRC4_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40271  #define R_ETHSW_P2_QMCIRC4_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40272 /* ======================================================  P2_QMCIRC5  ======================================================= */
40273  #define R_ETHSW_P2_QMCIRC5_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40274  #define R_ETHSW_P2_QMCIRC5_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40275 /* ======================================================  P2_QMCIRC6  ======================================================= */
40276  #define R_ETHSW_P2_QMCIRC6_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40277  #define R_ETHSW_P2_QMCIRC6_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40278 /* ======================================================  P2_QMCIRC7  ======================================================= */
40279  #define R_ETHSW_P2_QMCIRC7_CIR_Pos                                       (0UL)          /*!< CIR (Bit 0)                                           */
40280  #define R_ETHSW_P2_QMCIRC7_CIR_Msk                                       (0x1ffffUL)    /*!< CIR (Bitfield-Mask: 0x1ffff)                          */
40281 /* =======================================================  P2_QMGPC0  ======================================================= */
40282  #define R_ETHSW_P2_QMGPC0_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40283  #define R_ETHSW_P2_QMGPC0_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40284 /* =======================================================  P2_QMGPC1  ======================================================= */
40285  #define R_ETHSW_P2_QMGPC1_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40286  #define R_ETHSW_P2_QMGPC1_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40287 /* =======================================================  P2_QMGPC2  ======================================================= */
40288  #define R_ETHSW_P2_QMGPC2_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40289  #define R_ETHSW_P2_QMGPC2_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40290 /* =======================================================  P2_QMGPC3  ======================================================= */
40291  #define R_ETHSW_P2_QMGPC3_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40292  #define R_ETHSW_P2_QMGPC3_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40293 /* =======================================================  P2_QMGPC4  ======================================================= */
40294  #define R_ETHSW_P2_QMGPC4_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40295  #define R_ETHSW_P2_QMGPC4_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40296 /* =======================================================  P2_QMGPC5  ======================================================= */
40297  #define R_ETHSW_P2_QMGPC5_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40298  #define R_ETHSW_P2_QMGPC5_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40299 /* =======================================================  P2_QMGPC6  ======================================================= */
40300  #define R_ETHSW_P2_QMGPC6_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40301  #define R_ETHSW_P2_QMGPC6_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40302 /* =======================================================  P2_QMGPC7  ======================================================= */
40303  #define R_ETHSW_P2_QMGPC7_QMGPC_Pos                                      (0UL)          /*!< QMGPC (Bit 0)                                         */
40304  #define R_ETHSW_P2_QMGPC7_QMGPC_Msk                                      (0xffffUL)     /*!< QMGPC (Bitfield-Mask: 0xffff)                         */
40305 /* =======================================================  P2_QMRPC0  ======================================================= */
40306  #define R_ETHSW_P2_QMRPC0_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40307  #define R_ETHSW_P2_QMRPC0_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40308 /* =======================================================  P2_QMRPC1  ======================================================= */
40309  #define R_ETHSW_P2_QMRPC1_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40310  #define R_ETHSW_P2_QMRPC1_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40311 /* =======================================================  P2_QMRPC2  ======================================================= */
40312  #define R_ETHSW_P2_QMRPC2_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40313  #define R_ETHSW_P2_QMRPC2_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40314 /* =======================================================  P2_QMRPC3  ======================================================= */
40315  #define R_ETHSW_P2_QMRPC3_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40316  #define R_ETHSW_P2_QMRPC3_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40317 /* =======================================================  P2_QMRPC4  ======================================================= */
40318  #define R_ETHSW_P2_QMRPC4_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40319  #define R_ETHSW_P2_QMRPC4_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40320 /* =======================================================  P2_QMRPC5  ======================================================= */
40321  #define R_ETHSW_P2_QMRPC5_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40322  #define R_ETHSW_P2_QMRPC5_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40323 /* =======================================================  P2_QMRPC6  ======================================================= */
40324  #define R_ETHSW_P2_QMRPC6_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40325  #define R_ETHSW_P2_QMRPC6_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40326 /* =======================================================  P2_QMRPC7  ======================================================= */
40327  #define R_ETHSW_P2_QMRPC7_QMRPC_Pos                                      (0UL)          /*!< QMRPC (Bit 0)                                         */
40328  #define R_ETHSW_P2_QMRPC7_QMRPC_Msk                                      (0xffffUL)     /*!< QMRPC (Bitfield-Mask: 0xffff)                         */
40329 /* =====================================================  STATN_STATUS  ====================================================== */
40330  #define R_ETHSW_STATN_STATUS_BUSY_Pos                                    (0UL)          /*!< BUSY (Bit 0)                                          */
40331  #define R_ETHSW_STATN_STATUS_BUSY_Msk                                    (0x1UL)        /*!< BUSY (Bitfield-Mask: 0x01)                            */
40332 /* =====================================================  STATN_CONFIG  ====================================================== */
40333  #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Pos                           (1UL)          /*!< CLEAR_ON_READ (Bit 1)                                 */
40334  #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Msk                           (0x2UL)        /*!< CLEAR_ON_READ (Bitfield-Mask: 0x01)                   */
40335  #define R_ETHSW_STATN_CONFIG_RESET_Pos                                   (31UL)         /*!< RESET (Bit 31)                                        */
40336  #define R_ETHSW_STATN_CONFIG_RESET_Msk                                   (0x80000000UL) /*!< RESET (Bitfield-Mask: 0x01)                           */
40337 /* =====================================================  STATN_CONTROL  ===================================================== */
40338  #define R_ETHSW_STATN_CONTROL_CHANMASK_Pos                               (0UL)          /*!< CHANMASK (Bit 0)                                      */
40339  #define R_ETHSW_STATN_CONTROL_CHANMASK_Msk                               (0xfUL)        /*!< CHANMASK (Bitfield-Mask: 0x0f)                        */
40340  #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Pos                              (29UL)         /*!< CLEAR_PRE (Bit 29)                                    */
40341  #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Msk                              (0x20000000UL) /*!< CLEAR_PRE (Bitfield-Mask: 0x01)                       */
40342  #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Pos                              (31UL)         /*!< CMD_CLEAR (Bit 31)                                    */
40343  #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Msk                              (0x80000000UL) /*!< CMD_CLEAR (Bitfield-Mask: 0x01)                       */
40344 /* ==================================================  STATN_CLEARVALUE_LO  ================================================== */
40345  #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Pos              (0UL)          /*!< STATN_CLEARVALUE_LO (Bit 0)                           */
40346  #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Msk              (0xffffffffUL) /*!< STATN_CLEARVALUE_LO (Bitfield-Mask: 0xffffffff) */
40347 /* ========================================================  ODISC0  ========================================================= */
40348  #define R_ETHSW_ODISC0_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
40349  #define R_ETHSW_ODISC0_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
40350 /* ========================================================  ODISC1  ========================================================= */
40351  #define R_ETHSW_ODISC1_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
40352  #define R_ETHSW_ODISC1_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
40353 /* ========================================================  ODISC2  ========================================================= */
40354  #define R_ETHSW_ODISC2_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
40355  #define R_ETHSW_ODISC2_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
40356 /* ========================================================  ODISC3  ========================================================= */
40357  #define R_ETHSW_ODISC3_ODISC_Pos                                         (0UL)          /*!< ODISC (Bit 0)                                         */
40358  #define R_ETHSW_ODISC3_ODISC_Msk                                         (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff)                     */
40359 /* ======================================================  IDISC_VLAN0  ====================================================== */
40360  #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
40361  #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
40362 /* ======================================================  IDISC_VLAN1  ====================================================== */
40363  #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
40364  #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
40365 /* ======================================================  IDISC_VLAN2  ====================================================== */
40366  #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
40367  #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
40368 /* ======================================================  IDISC_VLAN3  ====================================================== */
40369  #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Pos                               (0UL)          /*!< IDISC_VLAN (Bit 0)                                    */
40370  #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Msk                               (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff)                */
40371 /* ====================================================  IDISC_UNTAGGED0  ==================================================== */
40372  #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
40373  #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
40374 /* ====================================================  IDISC_UNTAGGED1  ==================================================== */
40375  #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
40376  #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
40377 /* ====================================================  IDISC_UNTAGGED2  ==================================================== */
40378  #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
40379  #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
40380 /* ====================================================  IDISC_UNTAGGED3  ==================================================== */
40381  #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Pos                       (0UL)          /*!< IDISC_UNTAGGED (Bit 0)                                */
40382  #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Msk                       (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff)            */
40383 /* ====================================================  IDISC_BLOCKED0  ===================================================== */
40384  #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
40385  #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
40386 /* ====================================================  IDISC_BLOCKED1  ===================================================== */
40387  #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
40388  #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
40389 /* ====================================================  IDISC_BLOCKED2  ===================================================== */
40390  #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
40391  #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
40392 /* ====================================================  IDISC_BLOCKED3  ===================================================== */
40393  #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Pos                         (0UL)          /*!< IDISC_BLOCKED (Bit 0)                                 */
40394  #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Msk                         (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff)             */
40395 /* ======================================================  IDISC_ANY0  ======================================================= */
40396  #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
40397  #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
40398 /* ======================================================  IDISC_ANY1  ======================================================= */
40399  #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
40400  #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
40401 /* ======================================================  IDISC_ANY2  ======================================================= */
40402  #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
40403  #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
40404 /* ======================================================  IDISC_ANY3  ======================================================= */
40405  #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Pos                                 (0UL)          /*!< IDISC_ANY (Bit 0)                                     */
40406  #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Msk                                 (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff)                 */
40407 /* =====================================================  IDISC_SRCFLT0  ===================================================== */
40408  #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
40409  #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
40410 /* =====================================================  IDISC_SRCFLT1  ===================================================== */
40411  #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
40412  #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
40413 /* =====================================================  IDISC_SRCFLT2  ===================================================== */
40414  #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Pos                           (0UL)          /*!< IDISC_SRCFLT (Bit 0)                                  */
40415  #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Msk                           (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff)              */
40416 /* ===================================================  TX_HOLD_REQ_CNT0  ==================================================== */
40417  #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
40418  #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
40419 /* ===================================================  TX_HOLD_REQ_CNT1  ==================================================== */
40420  #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
40421  #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
40422 /* ===================================================  TX_HOLD_REQ_CNT2  ==================================================== */
40423  #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Pos                     (0UL)          /*!< TX_HOLD_REQ_CNT (Bit 0)                               */
40424  #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Msk                     (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff)           */
40425 /* =====================================================  TX_FRAG_CNT0  ====================================================== */
40426  #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
40427  #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
40428 /* =====================================================  TX_FRAG_CNT1  ====================================================== */
40429  #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
40430  #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
40431 /* =====================================================  TX_FRAG_CNT2  ====================================================== */
40432  #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Pos                             (0UL)          /*!< TX_FRAG_CNT (Bit 0)                                   */
40433  #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
40434 /* =====================================================  RX_FRAG_CNT0  ====================================================== */
40435  #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
40436  #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
40437 /* =====================================================  RX_FRAG_CNT1  ====================================================== */
40438  #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
40439  #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
40440 /* =====================================================  RX_FRAG_CNT2  ====================================================== */
40441  #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Pos                             (0UL)          /*!< RX_FRAG_CNT (Bit 0)                                   */
40442  #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Msk                             (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff)               */
40443 /* ====================================================  RX_ASSY_OK_CNT0  ==================================================== */
40444  #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
40445  #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
40446 /* ====================================================  RX_ASSY_OK_CNT1  ==================================================== */
40447  #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
40448  #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
40449 /* ====================================================  RX_ASSY_OK_CNT2  ==================================================== */
40450  #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Pos                       (0UL)          /*!< RX_ASSY_OK_CNT (Bit 0)                                */
40451  #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Msk                       (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff)            */
40452 /* ===================================================  RX_ASSY_ERR_CNT0  ==================================================== */
40453  #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
40454  #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
40455 /* ===================================================  RX_ASSY_ERR_CNT1  ==================================================== */
40456  #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
40457  #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
40458 /* ===================================================  RX_ASSY_ERR_CNT2  ==================================================== */
40459  #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Pos                     (0UL)          /*!< RX_ASSY_ERR_CNT (Bit 0)                               */
40460  #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Msk                     (0xffffUL)     /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff)               */
40461 /* ====================================================  RX_SMD_ERR_CNT0  ==================================================== */
40462  #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
40463  #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
40464 /* ====================================================  RX_SMD_ERR_CNT1  ==================================================== */
40465  #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
40466  #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
40467 /* ====================================================  RX_SMD_ERR_CNT2  ==================================================== */
40468  #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Pos                       (0UL)          /*!< RX_SMD_ERR_CNT (Bit 0)                                */
40469  #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Msk                       (0xffffUL)     /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff)                */
40470 /* ===================================================  TX_VERIFY_OK_CNT0  =================================================== */
40471  #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
40472  #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
40473 /* ===================================================  TX_VERIFY_OK_CNT1  =================================================== */
40474  #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
40475  #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
40476 /* ===================================================  TX_VERIFY_OK_CNT2  =================================================== */
40477  #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< TX_VERIFY_OK_CNT (Bit 0)                              */
40478  #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
40479 /* ==================================================  TX_RESPONSE_OK_CNT0  ================================================== */
40480  #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
40481  #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
40482 /* ==================================================  TX_RESPONSE_OK_CNT1  ================================================== */
40483  #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
40484  #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
40485 /* ==================================================  TX_RESPONSE_OK_CNT2  ================================================== */
40486  #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< TX_RESPONSE_OK_CNT (Bit 0)                            */
40487  #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
40488 /* ===================================================  RX_VERIFY_OK_CNT0  =================================================== */
40489  #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
40490  #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
40491 /* ===================================================  RX_VERIFY_OK_CNT1  =================================================== */
40492  #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
40493  #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
40494 /* ===================================================  RX_VERIFY_OK_CNT2  =================================================== */
40495  #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Pos                   (0UL)          /*!< RX_VERIFY_OK_CNT (Bit 0)                              */
40496  #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Msk                   (0xffUL)       /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff)                */
40497 /* ==================================================  RX_RESPONSE_OK_CNT0  ================================================== */
40498  #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
40499  #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
40500 /* ==================================================  RX_RESPONSE_OK_CNT1  ================================================== */
40501  #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
40502  #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
40503 /* ==================================================  RX_RESPONSE_OK_CNT2  ================================================== */
40504  #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Pos               (0UL)          /*!< RX_RESPONSE_OK_CNT (Bit 0)                            */
40505  #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Msk               (0xffUL)       /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff)              */
40506 /* ==================================================  RX_VERIFY_BAD_CNT0  =================================================== */
40507  #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
40508  #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
40509 /* ==================================================  RX_VERIFY_BAD_CNT1  =================================================== */
40510  #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
40511  #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
40512 /* ==================================================  RX_VERIFY_BAD_CNT2  =================================================== */
40513  #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Pos                 (0UL)          /*!< RX_VERIFY_BAD_CNT (Bit 0)                             */
40514  #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Msk                 (0xffUL)       /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff)               */
40515 /* =================================================  RX_RESPONSE_BAD_CNT0  ================================================== */
40516  #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
40517  #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
40518 /* =================================================  RX_RESPONSE_BAD_CNT1  ================================================== */
40519  #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
40520  #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
40521 /* =================================================  RX_RESPONSE_BAD_CNT2  ================================================== */
40522  #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Pos             (0UL)          /*!< RX_RESPONSE_BAD_CNT (Bit 0)                           */
40523  #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Msk             (0xffUL)       /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff)           */
40524 /* =====================================================  MMCTL_OUT_CT  ====================================================== */
40525  #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Pos                              (0UL)          /*!< CT_OVR_ENA (Bit 0)                                    */
40526  #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Msk                              (0x7UL)        /*!< CT_OVR_ENA (Bitfield-Mask: 0x07)                      */
40527  #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Pos                                  (16UL)         /*!< CT_OVR (Bit 16)                                       */
40528  #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Msk                                  (0x70000UL)    /*!< CT_OVR (Bitfield-Mask: 0x07)                          */
40529 /* ==================================================  MMCTL_CTFL_P0_3_ENA  ================================================== */
40530  #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Pos                      (0UL)          /*!< CTFL_P0_ENA (Bit 0)                                   */
40531  #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Msk                      (0xffUL)       /*!< CTFL_P0_ENA (Bitfield-Mask: 0xff)                     */
40532  #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Pos                      (8UL)          /*!< CTFL_P1_ENA (Bit 8)                                   */
40533  #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Msk                      (0xff00UL)     /*!< CTFL_P1_ENA (Bitfield-Mask: 0xff)                     */
40534  #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Pos                      (16UL)         /*!< CTFL_P2_ENA (Bit 16)                                  */
40535  #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Msk                      (0xff0000UL)   /*!< CTFL_P2_ENA (Bitfield-Mask: 0xff)                     */
40536 /* ==============================================  MMCTL_YELLOW_BYTE_LENGTH_P  =============================================== */
40537  #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Pos                (2UL)          /*!< YELLOW_LEN (Bit 2)                                    */
40538  #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Msk                (0xfffcUL)     /*!< YELLOW_LEN (Bitfield-Mask: 0x3fff)                   */
40539  #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Pos                   (16UL)         /*!< YLEN_EN (Bit 16)                                      */
40540  #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Msk                   (0x10000UL)    /*!< YLEN_EN (Bitfield-Mask: 0x01)                         */
40541 /* ====================================================  MMCTL_POOL0_CTR  ==================================================== */
40542  #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Pos                                (0UL)          /*!< CELLS (Bit 0)                                         */
40543  #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Msk                                (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
40544  #define R_ETHSW_MMCTL_POOL0_CTR_USED_Pos                                 (16UL)         /*!< USED (Bit 16)                                         */
40545  #define R_ETHSW_MMCTL_POOL0_CTR_USED_Msk                                 (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
40546 /* ====================================================  MMCTL_POOL1_CTR  ==================================================== */
40547  #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Pos                                (0UL)          /*!< CELLS (Bit 0)                                         */
40548  #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Msk                                (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
40549  #define R_ETHSW_MMCTL_POOL1_CTR_USED_Pos                                 (16UL)         /*!< USED (Bit 16)                                         */
40550  #define R_ETHSW_MMCTL_POOL1_CTR_USED_Msk                                 (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
40551 /* ===================================================  MMCTL_POOL_GLOBAL  =================================================== */
40552  #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Pos                              (0UL)          /*!< CELLS (Bit 0)                                         */
40553  #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Msk                              (0x3ffUL)      /*!< CELLS (Bitfield-Mask: 0x3ff)                          */
40554  #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Pos                               (16UL)         /*!< USED (Bit 16)                                         */
40555  #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Msk                               (0x3ff0000UL)  /*!< USED (Bitfield-Mask: 0x3ff)                           */
40556 /* ===================================================  MMCTL_POOL_STATUS  =================================================== */
40557  #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Pos                         (0UL)          /*!< QUEUE_FULL (Bit 0)                                    */
40558  #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Msk                         (0xffUL)       /*!< QUEUE_FULL (Bitfield-Mask: 0xff)                      */
40559 /* ====================================================  MMCTL_POOL_QMAP  ==================================================== */
40560  #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Pos                               (0UL)          /*!< Q0_MAP (Bit 0)                                        */
40561  #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Msk                               (0x1UL)        /*!< Q0_MAP (Bitfield-Mask: 0x01)                          */
40562  #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Pos                               (3UL)          /*!< Q0_ENA (Bit 3)                                        */
40563  #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Msk                               (0x8UL)        /*!< Q0_ENA (Bitfield-Mask: 0x01)                          */
40564  #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Pos                               (4UL)          /*!< Q1_MAP (Bit 4)                                        */
40565  #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Msk                               (0x10UL)       /*!< Q1_MAP (Bitfield-Mask: 0x01)                          */
40566  #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Pos                               (7UL)          /*!< Q1_ENA (Bit 7)                                        */
40567  #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Msk                               (0x80UL)       /*!< Q1_ENA (Bitfield-Mask: 0x01)                          */
40568  #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Pos                               (8UL)          /*!< Q2_MAP (Bit 8)                                        */
40569  #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Msk                               (0x100UL)      /*!< Q2_MAP (Bitfield-Mask: 0x01)                          */
40570  #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Pos                               (11UL)         /*!< Q2_ENA (Bit 11)                                       */
40571  #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Msk                               (0x800UL)      /*!< Q2_ENA (Bitfield-Mask: 0x01)                          */
40572  #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Pos                               (12UL)         /*!< Q3_MAP (Bit 12)                                       */
40573  #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Msk                               (0x1000UL)     /*!< Q3_MAP (Bitfield-Mask: 0x01)                          */
40574  #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Pos                               (15UL)         /*!< Q3_ENA (Bit 15)                                       */
40575  #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Msk                               (0x8000UL)     /*!< Q3_ENA (Bitfield-Mask: 0x01)                          */
40576  #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Pos                               (16UL)         /*!< Q4_MAP (Bit 16)                                       */
40577  #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Msk                               (0x10000UL)    /*!< Q4_MAP (Bitfield-Mask: 0x01)                          */
40578  #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Pos                               (19UL)         /*!< Q4_ENA (Bit 19)                                       */
40579  #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Msk                               (0x80000UL)    /*!< Q4_ENA (Bitfield-Mask: 0x01)                          */
40580  #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Pos                               (20UL)         /*!< Q5_MAP (Bit 20)                                       */
40581  #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Msk                               (0x100000UL)   /*!< Q5_MAP (Bitfield-Mask: 0x01)                          */
40582  #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Pos                               (23UL)         /*!< Q5_ENA (Bit 23)                                       */
40583  #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Msk                               (0x800000UL)   /*!< Q5_ENA (Bitfield-Mask: 0x01)                          */
40584  #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Pos                               (24UL)         /*!< Q6_MAP (Bit 24)                                       */
40585  #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Msk                               (0x1000000UL)  /*!< Q6_MAP (Bitfield-Mask: 0x01)                          */
40586  #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Pos                               (27UL)         /*!< Q6_ENA (Bit 27)                                       */
40587  #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Msk                               (0x8000000UL)  /*!< Q6_ENA (Bitfield-Mask: 0x01)                          */
40588  #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Pos                               (28UL)         /*!< Q7_MAP (Bit 28)                                       */
40589  #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Msk                               (0x10000000UL) /*!< Q7_MAP (Bitfield-Mask: 0x01)                          */
40590  #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Pos                               (31UL)         /*!< Q7_ENA (Bit 31)                                       */
40591  #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Msk                               (0x80000000UL) /*!< Q7_ENA (Bitfield-Mask: 0x01)                          */
40592 /* ======================================================  MMCTL_QGATE  ====================================================== */
40593  #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Pos                                (0UL)          /*!< PORT_MASK (Bit 0)                                     */
40594  #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Msk                                (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
40595  #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Pos                               (16UL)         /*!< QUEUE_GATE (Bit 16)                                   */
40596  #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Msk                               (0xffff0000UL) /*!< QUEUE_GATE (Bitfield-Mask: 0xffff)                    */
40597 /* ======================================================  MMCTL_QTRIG  ====================================================== */
40598  #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Pos                                (0UL)          /*!< PORT_MASK (Bit 0)                                     */
40599  #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Msk                                (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
40600  #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Pos                               (16UL)         /*!< QUEUE_TRIG (Bit 16)                                   */
40601  #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Msk                               (0xff0000UL)   /*!< QUEUE_TRIG (Bitfield-Mask: 0xff)                      */
40602 /* =====================================================  MMCTL_QFLUSH  ====================================================== */
40603  #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Pos                               (0UL)          /*!< PORT_MASK (Bit 0)                                     */
40604  #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Msk                               (0xfUL)        /*!< PORT_MASK (Bitfield-Mask: 0x0f)                       */
40605  #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Pos                              (16UL)         /*!< QUEUE_MASK (Bit 16)                                   */
40606  #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Msk                              (0xff0000UL)   /*!< QUEUE_MASK (Bitfield-Mask: 0xff)                      */
40607  #define R_ETHSW_MMCTL_QFLUSH_ACTION_Pos                                  (24UL)         /*!< ACTION (Bit 24)                                       */
40608  #define R_ETHSW_MMCTL_QFLUSH_ACTION_Msk                                  (0x3000000UL)  /*!< ACTION (Bitfield-Mask: 0x03)                          */
40609 /* ===============================================  MMCTL_QCLOSED_STATUS_P0_3  =============================================== */
40610  #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Pos                  (0UL)          /*!< P0_STATUS (Bit 0)                                     */
40611  #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Msk                  (0xffUL)       /*!< P0_STATUS (Bitfield-Mask: 0xff)                       */
40612  #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Pos                  (8UL)          /*!< P1_STATUS (Bit 8)                                     */
40613  #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Msk                  (0xff00UL)     /*!< P1_STATUS (Bitfield-Mask: 0xff)                       */
40614  #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Pos                  (16UL)         /*!< P2_STATUS (Bit 16)                                    */
40615  #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Msk                  (0xff0000UL)   /*!< P2_STATUS (Bitfield-Mask: 0xff)                      */
40616 /* ==================================================  MMCTL_1FRAME_MODE_P  ================================================== */
40617  #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Pos                     (0UL)          /*!< Q_1FRAME_ENA (Bit 0)                                  */
40618  #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Msk                     (0xffUL)       /*!< Q_1FRAME_ENA (Bitfield-Mask: 0xff)                    */
40619  #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Pos                        (16UL)         /*!< Q_BUF_ENA (Bit 16)                                    */
40620  #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Msk                        (0xff0000UL)   /*!< Q_BUF_ENA (Bitfield-Mask: 0xff)                       */
40621 /* ================================================  MMCTL_P0_3_QUEUE_STATUS  ================================================ */
40622  #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Pos                  (0UL)          /*!< P0_Q_STATUS (Bit 0)                                   */
40623  #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Msk                  (0xffUL)       /*!< P0_Q_STATUS (Bitfield-Mask: 0xff)                     */
40624  #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Pos                  (8UL)          /*!< P1_Q_STATUS (Bit 8)                                   */
40625  #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Msk                  (0xff00UL)     /*!< P1_Q_STATUS (Bitfield-Mask: 0xff)                     */
40626  #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Pos                  (16UL)         /*!< P2_Q_STATUS (Bit 16)                                  */
40627  #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Msk                  (0xff0000UL)   /*!< P2_Q_STATUS (Bitfield-Mask: 0xff)                    */
40628 /* ================================================  MMCTL_P0_3_FLUSH_STATUS  ================================================ */
40629  #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Pos                  (0UL)          /*!< P0_F_STATUS (Bit 0)                                   */
40630  #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Msk                  (0xffUL)       /*!< P0_F_STATUS (Bitfield-Mask: 0xff)                     */
40631  #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Pos                  (8UL)          /*!< P1_F_STATUS (Bit 8)                                   */
40632  #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Msk                  (0xff00UL)     /*!< P1_F_STATUS (Bitfield-Mask: 0xff)                     */
40633  #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Pos                  (16UL)         /*!< P2_F_STATUS (Bit 16)                                  */
40634  #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Msk                  (0xff0000UL)   /*!< P2_F_STATUS (Bitfield-Mask: 0xff)                    */
40635 /* ================================================  MMCTL_DLY_QTRIGGER_CTRL  ================================================ */
40636  #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Pos                   (0UL)          /*!< DELAY_TIME (Bit 0)                                    */
40637  #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Msk                   (0x3fffffffUL) /*!< DELAY_TIME (Bitfield-Mask: 0x3fffffff)              */
40638  #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Pos                    (30UL)         /*!< TIMER_SEL (Bit 30)                                    */
40639  #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Msk                    (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01)                      */
40640 /* =================================================  MMCTL_PREEMPT_QUEUES  ================================================== */
40641  #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Pos                     (0UL)          /*!< PREEMPT_ENA (Bit 0)                                   */
40642  #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Msk                     (0xffUL)       /*!< PREEMPT_ENA (Bitfield-Mask: 0xff)                     */
40643  #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Pos               (8UL)          /*!< PREEMPT_ON_QCLOSE (Bit 8)                             */
40644  #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Msk               (0xff00UL)     /*!< PREEMPT_ON_QCLOSE (Bitfield-Mask: 0xff)             */
40645 /* ==================================================  MMCTL_HOLD_CONTROL  =================================================== */
40646  #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Pos                  (0UL)          /*!< Q_HOLD_REQ_FORCE (Bit 0)                              */
40647  #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Msk                  (0x7UL)        /*!< Q_HOLD_REQ_FORCE (Bitfield-Mask: 0x07)                */
40648  #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Pos                (16UL)         /*!< Q_HOLD_REQ_RELEASE (Bit 16)                           */
40649  #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Msk                (0x70000UL)    /*!< Q_HOLD_REQ_RELEASE (Bitfield-Mask: 0x07)            */
40650 /* =================================================  MMCTL_PREEMPT_STATUS  ================================================== */
40651  #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Pos                   (0UL)          /*!< PREEMPT_STATE (Bit 0)                                 */
40652  #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Msk                   (0x7UL)        /*!< PREEMPT_STATE (Bitfield-Mask: 0x07)                   */
40653  #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Pos                  (16UL)         /*!< HOLD_REQ_STATE (Bit 16)                               */
40654  #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Msk                  (0x70000UL)    /*!< HOLD_REQ_STATE (Bitfield-Mask: 0x07)                  */
40655 /* ===================================================  MMCTL_CQF_CTRL_P  ==================================================== */
40656  #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Pos                        (0UL)          /*!< PRIO_ENABLE0 (Bit 0)                                  */
40657  #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Msk                        (0xffUL)       /*!< PRIO_ENABLE0 (Bitfield-Mask: 0xff)                    */
40658  #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Pos                          (8UL)          /*!< QUEUE_SEL0 (Bit 8)                                    */
40659  #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Msk                          (0x700UL)      /*!< QUEUE_SEL0 (Bitfield-Mask: 0x07)                      */
40660  #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Pos                           (11UL)         /*!< GATE_SEL0 (Bit 11)                                    */
40661  #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Msk                           (0x3800UL)     /*!< GATE_SEL0 (Bitfield-Mask: 0x07)                       */
40662  #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Pos                            (14UL)         /*!< USE_SOP0 (Bit 14)                                     */
40663  #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Msk                            (0x4000UL)     /*!< USE_SOP0 (Bitfield-Mask: 0x01)                        */
40664  #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Pos                            (15UL)         /*!< REF_SEL0 (Bit 15)                                     */
40665  #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Msk                            (0x8000UL)     /*!< REF_SEL0 (Bitfield-Mask: 0x01)                        */
40666 /* ==============================================  MMCTL_P0_3_QCLOSED_NONEMPTY  ============================================== */
40667  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Pos              (0UL)          /*!< P0_Q_STATUS (Bit 0)                                   */
40668  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Msk              (0xffUL)       /*!< P0_Q_STATUS (Bitfield-Mask: 0xff)                    */
40669  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Pos              (8UL)          /*!< P1_Q_STATUS (Bit 8)                                   */
40670  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Msk              (0xff00UL)     /*!< P1_Q_STATUS (Bitfield-Mask: 0xff)                  */
40671  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Pos              (16UL)         /*!< P2_Q_STATUS (Bit 16)                                  */
40672  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Msk              (0xff0000UL)   /*!< P2_Q_STATUS (Bitfield-Mask: 0xff)                */
40673  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Pos              (24UL)         /*!< P3_Q_STATUS (Bit 24)                                  */
40674  #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Msk              (0xff000000UL) /*!< P3_Q_STATUS (Bitfield-Mask: 0xff)              */
40675 /* ==================================================  MMCTL_PREEMPT_EXTRA  ================================================== */
40676  #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Pos                     (0UL)          /*!< MIN_PFRM_ADJ (Bit 0)                                  */
40677  #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Msk                     (0xfUL)        /*!< MIN_PFRM_ADJ (Bitfield-Mask: 0x0f)                    */
40678  #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Pos                    (4UL)          /*!< LAST_PFRM_ADJ (Bit 4)                                 */
40679  #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Msk                    (0xf0UL)       /*!< LAST_PFRM_ADJ (Bitfield-Mask: 0x0f)                   */
40680 /* ======================================================  DLR_CONTROL  ====================================================== */
40681  #define R_ETHSW_DLR_CONTROL_ENABLE_Pos                                   (0UL)          /*!< ENABLE (Bit 0)                                        */
40682  #define R_ETHSW_DLR_CONTROL_ENABLE_Msk                                   (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
40683  #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Pos                                (1UL)          /*!< AUTOFLUSH (Bit 1)                                     */
40684  #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Msk                                (0x2UL)        /*!< AUTOFLUSH (Bitfield-Mask: 0x01)                       */
40685  #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Pos                          (2UL)          /*!< LOOP_FILTER_ENA (Bit 2)                               */
40686  #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Msk                          (0x4UL)        /*!< LOOP_FILTER_ENA (Bitfield-Mask: 0x01)                 */
40687  #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Pos                             (4UL)          /*!< IGNORE_INVTM (Bit 4)                                  */
40688  #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Msk                             (0x10UL)       /*!< IGNORE_INVTM (Bitfield-Mask: 0x01)                    */
40689  #define R_ETHSW_DLR_CONTROL_US_TIME_Pos                                  (8UL)          /*!< US_TIME (Bit 8)                                       */
40690  #define R_ETHSW_DLR_CONTROL_US_TIME_Msk                                  (0xfff00UL)    /*!< US_TIME (Bitfield-Mask: 0xfff)                        */
40691 /* ======================================================  DLR_STATUS  ======================================================= */
40692  #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Pos                            (0UL)          /*!< LastBcnRcvPort (Bit 0)                                */
40693  #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Msk                            (0x3UL)        /*!< LastBcnRcvPort (Bitfield-Mask: 0x03)                  */
40694  #define R_ETHSW_DLR_STATUS_NODE_STATE_Pos                                (8UL)          /*!< NODE_STATE (Bit 8)                                    */
40695  #define R_ETHSW_DLR_STATUS_NODE_STATE_Msk                                (0xff00UL)     /*!< NODE_STATE (Bitfield-Mask: 0xff)                      */
40696  #define R_ETHSW_DLR_STATUS_LINK_STATUS_Pos                               (16UL)         /*!< LINK_STATUS (Bit 16)                                  */
40697  #define R_ETHSW_DLR_STATUS_LINK_STATUS_Msk                               (0x30000UL)    /*!< LINK_STATUS (Bitfield-Mask: 0x03)                     */
40698  #define R_ETHSW_DLR_STATUS_TOPOLOGY_Pos                                  (24UL)         /*!< TOPOLOGY (Bit 24)                                     */
40699  #define R_ETHSW_DLR_STATUS_TOPOLOGY_Msk                                  (0xff000000UL) /*!< TOPOLOGY (Bitfield-Mask: 0xff)                        */
40700 /* ======================================================  DLR_ETH_TYP  ====================================================== */
40701  #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Pos                              (0UL)          /*!< DLR_ETH_TYP (Bit 0)                                   */
40702  #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Msk                              (0xffffUL)     /*!< DLR_ETH_TYP (Bitfield-Mask: 0xffff)                   */
40703 /* ====================================================  DLR_IRQ_CONTROL  ==================================================== */
40704  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Pos                   (0UL)          /*!< IRQ_state_chng_ena (Bit 0)                            */
40705  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Msk                   (0x1UL)        /*!< IRQ_state_chng_ena (Bitfield-Mask: 0x01)              */
40706  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Pos                (1UL)          /*!< IRQ_flush_macaddr_ena (Bit 1)                         */
40707  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Msk                (0x2UL)        /*!< IRQ_flush_macaddr_ena (Bitfield-Mask: 0x01)           */
40708  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Pos                  (2UL)          /*!< IRQ_stop_nbchk0_ena (Bit 2)                           */
40709  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Msk                  (0x4UL)        /*!< IRQ_stop_nbchk0_ena (Bitfield-Mask: 0x01)             */
40710  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Pos                  (3UL)          /*!< IRQ_stop_nbchk1_ena (Bit 3)                           */
40711  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Msk                  (0x8UL)        /*!< IRQ_stop_nbchk1_ena (Bitfield-Mask: 0x01)             */
40712  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Pos                 (4UL)          /*!< IRQ_bec_tmr0_exp_ena (Bit 4)                          */
40713  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Msk                 (0x10UL)       /*!< IRQ_bec_tmr0_exp_ena (Bitfield-Mask: 0x01)            */
40714  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Pos                 (5UL)          /*!< IRQ_bec_tmr1_exp_ena (Bit 5)                          */
40715  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Msk                 (0x20UL)       /*!< IRQ_bec_tmr1_exp_ena (Bitfield-Mask: 0x01)            */
40716  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Pos                    (6UL)          /*!< IRQ_supr_chng_ena (Bit 6)                             */
40717  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Msk                    (0x40UL)       /*!< IRQ_supr_chng_ena (Bitfield-Mask: 0x01)               */
40718  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Pos                   (7UL)          /*!< IRQ_link_chng0_ena (Bit 7)                            */
40719  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Msk                   (0x80UL)       /*!< IRQ_link_chng0_ena (Bitfield-Mask: 0x01)              */
40720  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Pos                   (8UL)          /*!< IRQ_link_chng1_ena (Bit 8)                            */
40721  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Msk                   (0x100UL)      /*!< IRQ_link_chng1_ena (Bitfield-Mask: 0x01)              */
40722  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Pos                   (9UL)          /*!< IRQ_sup_ignord_ena (Bit 9)                            */
40723  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Msk                   (0x200UL)      /*!< IRQ_sup_ignord_ena (Bitfield-Mask: 0x01)              */
40724  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Pos                 (10UL)         /*!< IRQ_ip_addr_chng_ena (Bit 10)                         */
40725  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Msk                 (0x400UL)      /*!< IRQ_ip_addr_chng_ena (Bitfield-Mask: 0x01)            */
40726  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Pos                  (11UL)         /*!< IRQ_invalid_tmr_ena (Bit 11)                          */
40727  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Msk                  (0x800UL)      /*!< IRQ_invalid_tmr_ena (Bitfield-Mask: 0x01)             */
40728  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Pos                     (12UL)         /*!< IRQ_bec_rcv0_ena (Bit 12)                             */
40729  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Msk                     (0x1000UL)     /*!< IRQ_bec_rcv0_ena (Bitfield-Mask: 0x01)                */
40730  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Pos                     (13UL)         /*!< IRQ_bec_rcv1_ena (Bit 13)                             */
40731  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Msk                     (0x2000UL)     /*!< IRQ_bec_rcv1_ena (Bitfield-Mask: 0x01)                */
40732  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Pos                       (14UL)         /*!< IRQ_frm_dscrd0 (Bit 14)                               */
40733  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Msk                       (0x4000UL)     /*!< IRQ_frm_dscrd0 (Bitfield-Mask: 0x01)                  */
40734  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Pos                       (15UL)         /*!< IRQ_frm_dscrd1 (Bit 15)                               */
40735  #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Msk                       (0x8000UL)     /*!< IRQ_frm_dscrd1 (Bitfield-Mask: 0x01)                  */
40736  #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Pos                           (29UL)         /*!< low_int_en (Bit 29)                                   */
40737  #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Msk                           (0x20000000UL) /*!< low_int_en (Bitfield-Mask: 0x01)                      */
40738  #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Pos                            (30UL)         /*!< atomic_OR (Bit 30)                                    */
40739  #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Msk                            (0x40000000UL) /*!< atomic_OR (Bitfield-Mask: 0x01)                       */
40740  #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Pos                           (31UL)         /*!< atomic_AND (Bit 31)                                   */
40741  #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Msk                           (0x80000000UL) /*!< atomic_AND (Bitfield-Mask: 0x01)                      */
40742 /* ===================================================  DLR_IRQ_STAT_ACK  ==================================================== */
40743  #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Pos              (0UL)          /*!< state_chng_IRQ_pending (Bit 0)                        */
40744  #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Msk              (0x1UL)        /*!< state_chng_IRQ_pending (Bitfield-Mask: 0x01)          */
40745  #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Pos                   (1UL)          /*!< flush_IRQ_pending (Bit 1)                             */
40746  #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Msk                   (0x2UL)        /*!< flush_IRQ_pending (Bitfield-Mask: 0x01)               */
40747  #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Pos                  (2UL)          /*!< nbchk0_IRQ_pending (Bit 2)                            */
40748  #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Msk                  (0x4UL)        /*!< nbchk0_IRQ_pending (Bitfield-Mask: 0x01)              */
40749  #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Pos                  (3UL)          /*!< nbchk1_IRQ_pending (Bit 3)                            */
40750  #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Msk                  (0x8UL)        /*!< nbchk1_IRQ_pending (Bitfield-Mask: 0x01)              */
40751  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Pos                (4UL)          /*!< bec_tmr0_IRQ_pending (Bit 4)                          */
40752  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Msk                (0x10UL)       /*!< bec_tmr0_IRQ_pending (Bitfield-Mask: 0x01)            */
40753  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Pos                (5UL)          /*!< bec_tmr1_IRQ_pending (Bit 5)                          */
40754  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Msk                (0x20UL)       /*!< bec_tmr1_IRQ_pending (Bitfield-Mask: 0x01)            */
40755  #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Pos               (6UL)          /*!< supr_chng_IRQ_pending (Bit 6)                         */
40756  #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Msk               (0x40UL)       /*!< supr_chng_IRQ_pending (Bitfield-Mask: 0x01)           */
40757  #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Pos                   (7UL)          /*!< Link0_IRQ_pending (Bit 7)                             */
40758  #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Msk                   (0x80UL)       /*!< Link0_IRQ_pending (Bitfield-Mask: 0x01)               */
40759  #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Pos                   (8UL)          /*!< Link1_IRQ_pending (Bit 8)                             */
40760  #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Msk                   (0x100UL)      /*!< Link1_IRQ_pending (Bitfield-Mask: 0x01)               */
40761  #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Pos              (9UL)          /*!< sup_ignord_IRQ_pending (Bit 9)                        */
40762  #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Msk              (0x200UL)      /*!< sup_ignord_IRQ_pending (Bitfield-Mask: 0x01)        */
40763  #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Pos                 (10UL)         /*!< ip_chng_IRQ_pending (Bit 10)                          */
40764  #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Msk                 (0x400UL)      /*!< ip_chng_IRQ_pending (Bitfield-Mask: 0x01)             */
40765  #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Pos             (11UL)         /*!< invalid_tmr_IRQ_pending (Bit 11)                      */
40766  #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Msk             (0x800UL)      /*!< invalid_tmr_IRQ_pending (Bitfield-Mask: 0x01)      */
40767  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Pos                (12UL)         /*!< bec_rcv0_IRQ_pending (Bit 12)                         */
40768  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Msk                (0x1000UL)     /*!< bec_rcv0_IRQ_pending (Bitfield-Mask: 0x01)           */
40769  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Pos                (13UL)         /*!< bec_rcv1_IRQ_pending (Bit 13)                         */
40770  #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Msk                (0x2000UL)     /*!< bec_rcv1_IRQ_pending (Bitfield-Mask: 0x01)           */
40771  #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Pos              (14UL)         /*!< frm_dscrd0_IRQ_pending (Bit 14)                       */
40772  #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Msk              (0x4000UL)     /*!< frm_dscrd0_IRQ_pending (Bitfield-Mask: 0x01)       */
40773  #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Pos              (15UL)         /*!< frm_dscrd1_IRQ_pending (Bit 15)                       */
40774  #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Msk              (0x8000UL)     /*!< frm_dscrd1_IRQ_pending (Bitfield-Mask: 0x01)       */
40775 /* =====================================================  DLR_LOC_MAClo  ===================================================== */
40776  #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Pos                                (0UL)          /*!< LOC_MAC (Bit 0)                                       */
40777  #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Msk                                (0xffffffffUL) /*!< LOC_MAC (Bitfield-Mask: 0xffffffff)                   */
40778 /* =====================================================  DLR_LOC_MAChi  ===================================================== */
40779  #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Pos                                (0UL)          /*!< LOC_MAC (Bit 0)                                       */
40780  #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Msk                                (0xffffUL)     /*!< LOC_MAC (Bitfield-Mask: 0xffff)                       */
40781 /* ====================================================  DLR_SUPR_MAClo  ===================================================== */
40782  #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Pos                              (0UL)          /*!< SUPR_MAC (Bit 0)                                      */
40783  #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Msk                              (0xffffffffUL) /*!< SUPR_MAC (Bitfield-Mask: 0xffffffff)                  */
40784 /* ====================================================  DLR_SUPR_MAChi  ===================================================== */
40785  #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Pos                              (0UL)          /*!< SUPR_MAC (Bit 0)                                      */
40786  #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Msk                              (0xffffUL)     /*!< SUPR_MAC (Bitfield-Mask: 0xffff)                      */
40787  #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Pos                                 (16UL)         /*!< PRECE (Bit 16)                                        */
40788  #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Msk                                 (0xff0000UL)   /*!< PRECE (Bitfield-Mask: 0xff)                           */
40789 /* ====================================================  DLR_STATE_VLAN  ===================================================== */
40790  #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Pos                              (0UL)          /*!< RINGSTAT (Bit 0)                                      */
40791  #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Msk                              (0xffUL)       /*!< RINGSTAT (Bitfield-Mask: 0xff)                        */
40792  #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Pos                             (8UL)          /*!< VLANVALID (Bit 8)                                     */
40793  #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Msk                             (0x100UL)      /*!< VLANVALID (Bitfield-Mask: 0x01)                       */
40794  #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Pos                              (16UL)         /*!< VLANINFO (Bit 16)                                     */
40795  #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Msk                              (0xffff0000UL) /*!< VLANINFO (Bitfield-Mask: 0xffff)                      */
40796 /* =====================================================  DLR_BEC_TMOUT  ===================================================== */
40797  #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Pos                              (0UL)          /*!< BEC_TMOUT (Bit 0)                                     */
40798  #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Msk                              (0xffffffffUL) /*!< BEC_TMOUT (Bitfield-Mask: 0xffffffff)                 */
40799 /* ====================================================  DLR_BEC_INTRVL  ===================================================== */
40800  #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Pos                            (0UL)          /*!< BEC_INTRVL (Bit 0)                                    */
40801  #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Msk                            (0xffffffffUL) /*!< BEC_INTRVL (Bitfield-Mask: 0xffffffff)                */
40802 /* ====================================================  DLR_SUPR_IPADR  ===================================================== */
40803  #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Pos                            (0UL)          /*!< SUPR_IPADR (Bit 0)                                    */
40804  #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Msk                            (0xffffffffUL) /*!< SUPR_IPADR (Bitfield-Mask: 0xffffffff)                */
40805 /* ===================================================  DLR_ETH_STYP_VER  ==================================================== */
40806  #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Pos                             (0UL)          /*!< SUBTYPE (Bit 0)                                       */
40807  #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Msk                             (0xffUL)       /*!< SUBTYPE (Bitfield-Mask: 0xff)                         */
40808  #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Pos                             (8UL)          /*!< PROTVER (Bit 8)                                       */
40809  #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Msk                             (0xff00UL)     /*!< PROTVER (Bitfield-Mask: 0xff)                         */
40810  #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Pos                               (16UL)         /*!< SPORT (Bit 16)                                        */
40811  #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Msk                               (0xff0000UL)   /*!< SPORT (Bitfield-Mask: 0xff)                           */
40812 /* =====================================================  DLR_INV_TMOUT  ===================================================== */
40813  #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Pos                              (0UL)          /*!< INV_TMOUT (Bit 0)                                     */
40814  #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Msk                              (0xffffffffUL) /*!< INV_TMOUT (Bitfield-Mask: 0xffffffff)                 */
40815 /* ======================================================  DLR_SEQ_ID  ======================================================= */
40816  #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Pos                                    (0UL)          /*!< SEQ_ID (Bit 0)                                        */
40817  #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Msk                                    (0xffffffffUL) /*!< SEQ_ID (Bitfield-Mask: 0xffffffff)                    */
40818 /* =======================================================  DLR_DSTlo  ======================================================= */
40819  #define R_ETHSW_DLR_DSTlo_DLR_DST_Pos                                    (0UL)          /*!< DLR_DST (Bit 0)                                       */
40820  #define R_ETHSW_DLR_DSTlo_DLR_DST_Msk                                    (0xffffffffUL) /*!< DLR_DST (Bitfield-Mask: 0xffffffff)                   */
40821 /* =======================================================  DLR_DSThi  ======================================================= */
40822  #define R_ETHSW_DLR_DSThi_DLR_DST_Pos                                    (0UL)          /*!< DLR_DST (Bit 0)                                       */
40823  #define R_ETHSW_DLR_DSThi_DLR_DST_Msk                                    (0xffffUL)     /*!< DLR_DST (Bitfield-Mask: 0xffff)                       */
40824 /* =====================================================  DLR_RX_STAT0  ====================================================== */
40825  #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Pos                                (0UL)          /*!< RX_STAT0 (Bit 0)                                      */
40826  #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Msk                                (0xffffffffUL) /*!< RX_STAT0 (Bitfield-Mask: 0xffffffff)                  */
40827 /* ===================================================  DLR_RX_ERR_STAT0  ==================================================== */
40828  #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Pos                        (0UL)          /*!< RX_ERR_STAT0 (Bit 0)                                  */
40829  #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Msk                        (0xffffffffUL) /*!< RX_ERR_STAT0 (Bitfield-Mask: 0xffffffff)              */
40830 /* ====================================================  DLR_RX_LF_STAT0  ==================================================== */
40831  #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Pos                          (0UL)          /*!< RX_LF_STAT0 (Bit 0)                                   */
40832  #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Msk                          (0xffUL)       /*!< RX_LF_STAT0 (Bitfield-Mask: 0xff)                     */
40833 /* =====================================================  DLR_RX_STAT1  ====================================================== */
40834  #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Pos                                (0UL)          /*!< RX_STAT1 (Bit 0)                                      */
40835  #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Msk                                (0xffffffffUL) /*!< RX_STAT1 (Bitfield-Mask: 0xffffffff)                  */
40836 /* ===================================================  DLR_RX_ERR_STAT1  ==================================================== */
40837  #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Pos                        (0UL)          /*!< RX_ERR_STAT1 (Bit 0)                                  */
40838  #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Msk                        (0xffffffffUL) /*!< RX_ERR_STAT1 (Bitfield-Mask: 0xffffffff)              */
40839 /* ====================================================  DLR_RX_LF_STAT1  ==================================================== */
40840  #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Pos                          (0UL)          /*!< RX_LF_STAT1 (Bit 0)                                   */
40841  #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Msk                          (0xffUL)       /*!< RX_LF_STAT1 (Bitfield-Mask: 0xff)                     */
40842 /* ======================================================  PRP_CONFIG  ======================================================= */
40843  #define R_ETHSW_PRP_CONFIG_PRP_ENA_Pos                                   (0UL)          /*!< PRP_ENA (Bit 0)                                       */
40844  #define R_ETHSW_PRP_CONFIG_PRP_ENA_Msk                                   (0x1UL)        /*!< PRP_ENA (Bitfield-Mask: 0x01)                         */
40845  #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Pos                             (1UL)          /*!< RX_DUP_ACCEPT (Bit 1)                                 */
40846  #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Msk                             (0x2UL)        /*!< RX_DUP_ACCEPT (Bitfield-Mask: 0x01)                   */
40847  #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Pos                             (2UL)          /*!< RX_REMOVE_RCT (Bit 2)                                 */
40848  #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Msk                             (0x4UL)        /*!< RX_REMOVE_RCT (Bitfield-Mask: 0x01)                   */
40849  #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Pos                               (3UL)          /*!< TX_RCT_MODE (Bit 3)                                   */
40850  #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Msk                               (0x18UL)       /*!< TX_RCT_MODE (Bitfield-Mask: 0x03)                     */
40851  #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Pos                          (5UL)          /*!< TX_RCT_BROADCAST (Bit 5)                              */
40852  #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Msk                          (0x20UL)       /*!< TX_RCT_BROADCAST (Bitfield-Mask: 0x01)                */
40853  #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Pos                          (6UL)          /*!< TX_RCT_MULTICAST (Bit 6)                              */
40854  #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Msk                          (0x40UL)       /*!< TX_RCT_MULTICAST (Bitfield-Mask: 0x01)                */
40855  #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Pos                            (7UL)          /*!< TX_RCT_UNKNOWN (Bit 7)                                */
40856  #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Msk                            (0x80UL)       /*!< TX_RCT_UNKNOWN (Bitfield-Mask: 0x01)                  */
40857  #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Pos                               (8UL)          /*!< TX_RCT_1588 (Bit 8)                                   */
40858  #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Msk                               (0x100UL)      /*!< TX_RCT_1588 (Bitfield-Mask: 0x01)                     */
40859  #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Pos                           (9UL)          /*!< RCT_LEN_CHK_DIS (Bit 9)                               */
40860  #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Msk                           (0x200UL)      /*!< RCT_LEN_CHK_DIS (Bitfield-Mask: 0x01)                 */
40861  #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Pos                               (16UL)         /*!< PRP_AGE_ENA (Bit 16)                                  */
40862  #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Msk                               (0x10000UL)    /*!< PRP_AGE_ENA (Bitfield-Mask: 0x01)                     */
40863 /* =======================================================  PRP_GROUP  ======================================================= */
40864  #define R_ETHSW_PRP_GROUP_PRP_GROUP_Pos                                  (0UL)          /*!< PRP_GROUP (Bit 0)                                     */
40865  #define R_ETHSW_PRP_GROUP_PRP_GROUP_Msk                                  (0x7UL)        /*!< PRP_GROUP (Bitfield-Mask: 0x07)                       */
40866  #define R_ETHSW_PRP_GROUP_LANB_MASK_Pos                                  (16UL)         /*!< LANB_MASK (Bit 16)                                    */
40867  #define R_ETHSW_PRP_GROUP_LANB_MASK_Msk                                  (0x70000UL)    /*!< LANB_MASK (Bitfield-Mask: 0x07)                       */
40868 /* ======================================================  PRP_SUFFIX  ======================================================= */
40869  #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Pos                                (0UL)          /*!< PRP_SUFFIX (Bit 0)                                    */
40870  #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Msk                                (0xffffUL)     /*!< PRP_SUFFIX (Bitfield-Mask: 0xffff)                    */
40871 /* =======================================================  PRP_LANID  ======================================================= */
40872  #define R_ETHSW_PRP_LANID_LANAID_Pos                                     (0UL)          /*!< LANAID (Bit 0)                                        */
40873  #define R_ETHSW_PRP_LANID_LANAID_Msk                                     (0xfUL)        /*!< LANAID (Bitfield-Mask: 0x0f)                          */
40874  #define R_ETHSW_PRP_LANID_LANBID_Pos                                     (4UL)          /*!< LANBID (Bit 4)                                        */
40875  #define R_ETHSW_PRP_LANID_LANBID_Msk                                     (0xf0UL)       /*!< LANBID (Bitfield-Mask: 0x0f)                          */
40876 /* =========================================================  DUP_W  ========================================================= */
40877  #define R_ETHSW_DUP_W_DUP_W_Pos                                          (0UL)          /*!< DUP_W (Bit 0)                                         */
40878  #define R_ETHSW_DUP_W_DUP_W_Msk                                          (0xffUL)       /*!< DUP_W (Bitfield-Mask: 0xff)                           */
40879 /* ======================================================  PRP_AGETIME  ====================================================== */
40880  #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Pos                              (0UL)          /*!< PRP_AGETIME (Bit 0)                                   */
40881  #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Msk                              (0xffffffUL)   /*!< PRP_AGETIME (Bitfield-Mask: 0xffffff)                 */
40882 /* ====================================================  PRP_IRQ_CONTROL  ==================================================== */
40883  #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Pos                           (0UL)          /*!< MEMTOOLATE (Bit 0)                                    */
40884  #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Msk                           (0x1UL)        /*!< MEMTOOLATE (Bitfield-Mask: 0x01)                      */
40885  #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Pos                             (1UL)          /*!< WRONGLAN (Bit 1)                                      */
40886  #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Msk                             (0x2UL)        /*!< WRONGLAN (Bitfield-Mask: 0x01)                        */
40887  #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Pos                             (2UL)          /*!< OUTOFSEQ (Bit 2)                                      */
40888  #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Msk                             (0x4UL)        /*!< OUTOFSEQ (Bitfield-Mask: 0x01)                        */
40889  #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Pos                           (3UL)          /*!< SEQMISSING (Bit 3)                                    */
40890  #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Msk                           (0x8UL)        /*!< SEQMISSING (Bitfield-Mask: 0x01)                      */
40891 /* ===================================================  PRP_IRQ_STAT_ACK  ==================================================== */
40892  #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Pos                          (0UL)          /*!< MEMTOOLATE (Bit 0)                                    */
40893  #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Msk                          (0x1UL)        /*!< MEMTOOLATE (Bitfield-Mask: 0x01)                      */
40894  #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Pos                            (1UL)          /*!< WRONGLAN (Bit 1)                                      */
40895  #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Msk                            (0x2UL)        /*!< WRONGLAN (Bitfield-Mask: 0x01)                        */
40896  #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Pos                            (2UL)          /*!< OUTOFSEQ (Bit 2)                                      */
40897  #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Msk                            (0x4UL)        /*!< OUTOFSEQ (Bitfield-Mask: 0x01)                        */
40898  #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Pos                          (3UL)          /*!< SEQMISSING (Bit 3)                                    */
40899  #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Msk                          (0x8UL)        /*!< SEQMISSING (Bitfield-Mask: 0x01)                      */
40900 /* =====================================================  RM_ADDR_CTRL  ====================================================== */
40901  #define R_ETHSW_RM_ADDR_CTRL_address_Pos                                 (0UL)          /*!< address (Bit 0)                                       */
40902  #define R_ETHSW_RM_ADDR_CTRL_address_Msk                                 (0xfffUL)      /*!< address (Bitfield-Mask: 0xfff)                        */
40903  #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Pos                           (22UL)         /*!< CLEAR_DYNAMIC (Bit 22)                                */
40904  #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Msk                           (0x400000UL)   /*!< CLEAR_DYNAMIC (Bitfield-Mask: 0x01)                   */
40905  #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Pos                            (23UL)         /*!< CLEAR_MEMORY (Bit 23)                                 */
40906  #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Msk                            (0x800000UL)   /*!< CLEAR_MEMORY (Bitfield-Mask: 0x01)                    */
40907  #define R_ETHSW_RM_ADDR_CTRL_WRITE_Pos                                   (25UL)         /*!< WRITE (Bit 25)                                        */
40908  #define R_ETHSW_RM_ADDR_CTRL_WRITE_Msk                                   (0x2000000UL)  /*!< WRITE (Bitfield-Mask: 0x01)                           */
40909  #define R_ETHSW_RM_ADDR_CTRL_READ_Pos                                    (26UL)         /*!< READ (Bit 26)                                         */
40910  #define R_ETHSW_RM_ADDR_CTRL_READ_Msk                                    (0x4000000UL)  /*!< READ (Bitfield-Mask: 0x01)                            */
40911  #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Pos                                   (29UL)         /*!< CLEAR (Bit 29)                                        */
40912  #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Msk                                   (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01)                           */
40913  #define R_ETHSW_RM_ADDR_CTRL_BUSY_Pos                                    (31UL)         /*!< BUSY (Bit 31)                                         */
40914  #define R_ETHSW_RM_ADDR_CTRL_BUSY_Msk                                    (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01)                            */
40915 /* ========================================================  RM_DATA  ======================================================== */
40916  #define R_ETHSW_RM_DATA_RM_DATA_Pos                                      (0UL)          /*!< RM_DATA (Bit 0)                                       */
40917  #define R_ETHSW_RM_DATA_RM_DATA_Msk                                      (0xffffffffUL) /*!< RM_DATA (Bitfield-Mask: 0xffffffff)                   */
40918 /* ======================================================  RM_DATA_HI  ======================================================= */
40919  #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Pos                                (0UL)          /*!< RM_DATA_HI (Bit 0)                                    */
40920  #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Msk                                (0xffffffffUL) /*!< RM_DATA_HI (Bitfield-Mask: 0xffffffff)                */
40921 /* =======================================================  RM_STATUS  ======================================================= */
40922  #define R_ETHSW_RM_STATUS_ageaddress_Pos                                 (0UL)          /*!< ageaddress (Bit 0)                                    */
40923  #define R_ETHSW_RM_STATUS_ageaddress_Msk                                 (0xfffUL)      /*!< ageaddress (Bitfield-Mask: 0xfff)                     */
40924 /* =====================================================  TxSeqTooLate  ====================================================== */
40925  #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Pos                            (0UL)          /*!< TxSeqTooLate (Bit 0)                                  */
40926  #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Msk                            (0xfUL)        /*!< TxSeqTooLate (Bitfield-Mask: 0x0f)                    */
40927 /* ====================================================  CntErrWrongLanA  ==================================================== */
40928  #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Pos                      (0UL)          /*!< CntErrWrongLanA (Bit 0)                               */
40929  #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Msk                      (0xffffffffUL) /*!< CntErrWrongLanA (Bitfield-Mask: 0xffffffff)           */
40930 /* ====================================================  CntErrWrongLanB  ==================================================== */
40931  #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Pos                      (0UL)          /*!< CntErrWrongLanB (Bit 0)                               */
40932  #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Msk                      (0xffffffffUL) /*!< CntErrWrongLanB (Bitfield-Mask: 0xffffffff)           */
40933 /* ======================================================  CntDupLanA  ======================================================= */
40934  #define R_ETHSW_CntDupLanA_CntDupLanA_Pos                                (0UL)          /*!< CntDupLanA (Bit 0)                                    */
40935  #define R_ETHSW_CntDupLanA_CntDupLanA_Msk                                (0xffffffffUL) /*!< CntDupLanA (Bitfield-Mask: 0xffffffff)                */
40936 /* ======================================================  CntDupLanB  ======================================================= */
40937  #define R_ETHSW_CntDupLanB_CntDupLanB_Pos                                (0UL)          /*!< CntDupLanB (Bit 0)                                    */
40938  #define R_ETHSW_CntDupLanB_CntDupLanB_Msk                                (0xffffffffUL) /*!< CntDupLanB (Bitfield-Mask: 0xffffffff)                */
40939 /* ====================================================  CntOutOfSeqLowA  ==================================================== */
40940  #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Pos                      (0UL)          /*!< CntOutOfSeqLowA (Bit 0)                               */
40941  #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Msk                      (0xffffffffUL) /*!< CntOutOfSeqLowA (Bitfield-Mask: 0xffffffff)           */
40942 /* ====================================================  CntOutOfSeqLowB  ==================================================== */
40943  #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Pos                      (0UL)          /*!< CntOutOfSeqLowB (Bit 0)                               */
40944  #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Msk                      (0xffffffffUL) /*!< CntOutOfSeqLowB (Bitfield-Mask: 0xffffffff)           */
40945 /* =====================================================  CntOutOfSeqA  ====================================================== */
40946  #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Pos                            (0UL)          /*!< CntOutOfSeqA (Bit 0)                                  */
40947  #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Msk                            (0xffffffffUL) /*!< CntOutOfSeqA (Bitfield-Mask: 0xffffffff)              */
40948 /* =====================================================  CntOutOfSeqB  ====================================================== */
40949  #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Pos                            (0UL)          /*!< CntOutOfSeqB (Bit 0)                                  */
40950  #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Msk                            (0xffffffffUL) /*!< CntOutOfSeqB (Bitfield-Mask: 0xffffffff)              */
40951 /* ======================================================  CntAcceptA  ======================================================= */
40952  #define R_ETHSW_CntAcceptA_CntAcceptA_Pos                                (0UL)          /*!< CntAcceptA (Bit 0)                                    */
40953  #define R_ETHSW_CntAcceptA_CntAcceptA_Msk                                (0xffffffffUL) /*!< CntAcceptA (Bitfield-Mask: 0xffffffff)                */
40954 /* ======================================================  CntAcceptB  ======================================================= */
40955  #define R_ETHSW_CntAcceptB_CntAcceptB_Pos                                (0UL)          /*!< CntAcceptB (Bit 0)                                    */
40956  #define R_ETHSW_CntAcceptB_CntAcceptB_Msk                                (0xffffffffUL) /*!< CntAcceptB (Bitfield-Mask: 0xffffffff)                */
40957 /* ======================================================  CntMissing  ======================================================= */
40958  #define R_ETHSW_CntMissing_CntMissing_Pos                                (0UL)          /*!< CntMissing (Bit 0)                                    */
40959  #define R_ETHSW_CntMissing_CntMissing_Msk                                (0xffffffffUL) /*!< CntMissing (Bitfield-Mask: 0xffffffff)                */
40960 /* ======================================================  HUB_CONFIG  ======================================================= */
40961  #define R_ETHSW_HUB_CONFIG_HUB_ENA_Pos                                   (0UL)          /*!< HUB_ENA (Bit 0)                                       */
40962  #define R_ETHSW_HUB_CONFIG_HUB_ENA_Msk                                   (0x1UL)        /*!< HUB_ENA (Bitfield-Mask: 0x01)                         */
40963  #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Pos                            (1UL)          /*!< RETRANSMIT_ENA (Bit 1)                                */
40964  #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Msk                            (0x2UL)        /*!< RETRANSMIT_ENA (Bitfield-Mask: 0x01)                  */
40965  #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Pos                              (2UL)          /*!< TRIGGER_MODE (Bit 2)                                  */
40966  #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Msk                              (0x4UL)        /*!< TRIGGER_MODE (Bitfield-Mask: 0x01)                    */
40967  #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Pos                               (3UL)          /*!< HUB_ISOLATE (Bit 3)                                   */
40968  #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Msk                               (0x8UL)        /*!< HUB_ISOLATE (Bitfield-Mask: 0x01)                     */
40969  #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Pos                                 (4UL)          /*!< TIMER_SEL (Bit 4)                                     */
40970  #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Msk                                 (0x10UL)       /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
40971  #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Pos                                  (6UL)          /*!< IPG_WAIT (Bit 6)                                      */
40972  #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Msk                                  (0x1c0UL)      /*!< IPG_WAIT (Bitfield-Mask: 0x07)                        */
40973  #define R_ETHSW_HUB_CONFIG_CRS_GEN_Pos                                   (9UL)          /*!< CRS_GEN (Bit 9)                                       */
40974  #define R_ETHSW_HUB_CONFIG_CRS_GEN_Msk                                   (0x200UL)      /*!< CRS_GEN (Bitfield-Mask: 0x01)                         */
40975  #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Pos                              (10UL)         /*!< PRMB_GEN_DIS (Bit 10)                                 */
40976  #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Msk                              (0x400UL)      /*!< PRMB_GEN_DIS (Bitfield-Mask: 0x01)                    */
40977  #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Pos                             (11UL)         /*!< JAM_WAIT_IDLE (Bit 11)                                */
40978  #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Msk                             (0x800UL)      /*!< JAM_WAIT_IDLE (Bitfield-Mask: 0x01)                   */
40979 /* =======================================================  HUB_GROUP  ======================================================= */
40980  #define R_ETHSW_HUB_GROUP_HUB_GROUP_Pos                                  (0UL)          /*!< HUB_GROUP (Bit 0)                                     */
40981  #define R_ETHSW_HUB_GROUP_HUB_GROUP_Msk                                  (0x7UL)        /*!< HUB_GROUP (Bitfield-Mask: 0x07)                       */
40982 /* ======================================================  HUB_DEFPORT  ====================================================== */
40983  #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Pos                              (0UL)          /*!< HUB_DEFPORT (Bit 0)                                   */
40984  #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Msk                              (0x7UL)        /*!< HUB_DEFPORT (Bitfield-Mask: 0x07)                     */
40985 /* =================================================  HUB_TRIGGER_IMMEDIATE  ================================================= */
40986  #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Pos          (0UL)          /*!< HUB_TRIGGER_IMMEDIATE (Bit 0)                       */
40987  #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Msk          (0x7UL)        /*!< HUB_TRIGGER_IMMEDIATE (Bitfield-Mask: 0x07)       */
40988 /* ====================================================  HUB_TRIGGER_AT  ===================================================== */
40989  #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Pos                        (0UL)          /*!< HUB_TRIGGER_AT (Bit 0)                                */
40990  #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Msk                        (0x7UL)        /*!< HUB_TRIGGER_AT (Bitfield-Mask: 0x07)                  */
40991 /* =======================================================  HUB_TTIME  ======================================================= */
40992  #define R_ETHSW_HUB_TTIME_HUB_TTIME_Pos                                  (0UL)          /*!< HUB_TTIME (Bit 0)                                     */
40993  #define R_ETHSW_HUB_TTIME_HUB_TTIME_Msk                                  (0xffffffffUL) /*!< HUB_TTIME (Bitfield-Mask: 0xffffffff)                 */
40994 /* ====================================================  HUB_IRQ_CONTROL  ==================================================== */
40995  #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Pos                           (0UL)          /*!< RX_TRIGGER (Bit 0)                                    */
40996  #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Msk                           (0x7UL)        /*!< RX_TRIGGER (Bitfield-Mask: 0x07)                      */
40997  #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Pos                           (3UL)          /*!< CHANGE_DET (Bit 3)                                    */
40998  #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Msk                           (0x8UL)        /*!< CHANGE_DET (Bitfield-Mask: 0x01)                      */
40999  #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Pos                    (4UL)          /*!< TRIGGER_IMMEDIATE (Bit 4)                             */
41000  #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Msk                    (0x10UL)       /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01)               */
41001  #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Pos                        (5UL)          /*!< TRIGGER_TIMER (Bit 5)                                 */
41002  #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Msk                        (0x20UL)       /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01)                   */
41003 /* ===================================================  HUB_IRQ_STAT_ACK  ==================================================== */
41004  #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Pos                          (0UL)          /*!< RX_TRIGGER (Bit 0)                                    */
41005  #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Msk                          (0x7UL)        /*!< RX_TRIGGER (Bitfield-Mask: 0x07)                      */
41006  #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Pos                          (3UL)          /*!< CHANGE_DET (Bit 3)                                    */
41007  #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Msk                          (0x8UL)        /*!< CHANGE_DET (Bitfield-Mask: 0x01)                      */
41008  #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Pos                   (4UL)          /*!< TRIGGER_IMMEDIATE (Bit 4)                             */
41009  #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Msk                   (0x10UL)       /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01)               */
41010  #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Pos                       (5UL)          /*!< TRIGGER_TIMER (Bit 5)                                 */
41011  #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Msk                       (0x20UL)       /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01)                   */
41012 /* ======================================================  HUB_STATUS  ======================================================= */
41013  #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Pos                              (0UL)          /*!< PORTS_ACTIVE (Bit 0)                                  */
41014  #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Msk                              (0x7UL)        /*!< PORTS_ACTIVE (Bitfield-Mask: 0x07)                    */
41015  #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Pos                                 (9UL)          /*!< TX_ACTIVE (Bit 9)                                     */
41016  #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Msk                                 (0x200UL)      /*!< TX_ACTIVE (Bitfield-Mask: 0x01)                       */
41017  #define R_ETHSW_HUB_STATUS_TX_BUSY_Pos                                   (10UL)         /*!< TX_BUSY (Bit 10)                                      */
41018  #define R_ETHSW_HUB_STATUS_TX_BUSY_Msk                                   (0x400UL)      /*!< TX_BUSY (Bitfield-Mask: 0x01)                         */
41019  #define R_ETHSW_HUB_STATUS_Speed_OK_Pos                                  (11UL)         /*!< Speed_OK (Bit 11)                                     */
41020  #define R_ETHSW_HUB_STATUS_Speed_OK_Msk                                  (0x800UL)      /*!< Speed_OK (Bitfield-Mask: 0x01)                        */
41021  #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Pos                         (12UL)         /*!< TX_Change_Pending (Bit 12)                            */
41022  #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Msk                         (0x1000UL)     /*!< TX_Change_Pending (Bitfield-Mask: 0x01)               */
41023 /* ===================================================  HUB_OPORT_STATUS  ==================================================== */
41024  #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Pos                    (0UL)          /*!< HUB_OPORT_STATUS (Bit 0)                              */
41025  #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Msk                    (0x7UL)        /*!< HUB_OPORT_STATUS (Bitfield-Mask: 0x07)                */
41026 /* ======================================================  TDMA_CONFIG  ====================================================== */
41027  #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Pos                                 (0UL)          /*!< TDMA_ENA (Bit 0)                                      */
41028  #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Msk                                 (0x1UL)        /*!< TDMA_ENA (Bitfield-Mask: 0x01)                        */
41029  #define R_ETHSW_TDMA_CONFIG_WAIT_START_Pos                               (1UL)          /*!< WAIT_START (Bit 1)                                    */
41030  #define R_ETHSW_TDMA_CONFIG_WAIT_START_Msk                               (0x2UL)        /*!< WAIT_START (Bitfield-Mask: 0x01)                      */
41031  #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Pos                                (2UL)          /*!< TIMER_SEL (Bit 2)                                     */
41032  #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Msk                                (0x4UL)        /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
41033  #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Pos                               (4UL)          /*!< RED_PERIOD (Bit 4)                                    */
41034  #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Msk                               (0x10UL)       /*!< RED_PERIOD (Bitfield-Mask: 0x01)                      */
41035  #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Pos                             (5UL)          /*!< RED_OVRD_ENA (Bit 5)                                  */
41036  #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Msk                             (0x20UL)       /*!< RED_OVRD_ENA (Bitfield-Mask: 0x01)                    */
41037  #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Pos                                 (6UL)          /*!< RED_OVRD (Bit 6)                                      */
41038  #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Msk                                 (0x40UL)       /*!< RED_OVRD (Bitfield-Mask: 0x01)                        */
41039  #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Pos                               (7UL)          /*!< IN_CT_WREN (Bit 7)                                    */
41040  #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Msk                               (0x80UL)       /*!< IN_CT_WREN (Bitfield-Mask: 0x01)                      */
41041  #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Pos                              (8UL)          /*!< OUT_CT_WREN (Bit 8)                                   */
41042  #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Msk                              (0x100UL)      /*!< OUT_CT_WREN (Bitfield-Mask: 0x01)                     */
41043  #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Pos                             (9UL)          /*!< HOLD_REQ_CLR (Bit 9)                                  */
41044  #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Msk                             (0x200UL)      /*!< HOLD_REQ_CLR (Bitfield-Mask: 0x01)                    */
41045  #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Pos                         (12UL)         /*!< TIMER_SEL_ACTIVE (Bit 12)                             */
41046  #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Msk                         (0x1000UL)     /*!< TIMER_SEL_ACTIVE (Bitfield-Mask: 0x01)                */
41047  #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Pos                                (16UL)         /*!< IN_CT_ENA (Bit 16)                                    */
41048  #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Msk                                (0xf0000UL)    /*!< IN_CT_ENA (Bitfield-Mask: 0x0f)                       */
41049  #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Pos                               (24UL)         /*!< OUT_CT_ENA (Bit 24)                                   */
41050  #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Msk                               (0xf000000UL)  /*!< OUT_CT_ENA (Bitfield-Mask: 0x0f)                      */
41051 /* =====================================================  TDMA_ENA_CTRL  ===================================================== */
41052  #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Pos                               (0UL)          /*!< PORT_ENA (Bit 0)                                      */
41053  #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Msk                               (0xfUL)        /*!< PORT_ENA (Bitfield-Mask: 0x0f)                        */
41054  #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Pos                              (16UL)         /*!< QGATE_DIS (Bit 16)                                    */
41055  #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Msk                              (0xff0000UL)   /*!< QGATE_DIS (Bitfield-Mask: 0xff)                       */
41056  #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Pos                              (24UL)         /*!< QTRIG_DIS (Bit 24)                                    */
41057  #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Msk                              (0xff000000UL) /*!< QTRIG_DIS (Bitfield-Mask: 0xff)                       */
41058 /* ======================================================  TDMA_START  ======================================================= */
41059  #define R_ETHSW_TDMA_START_TDMA_START_Pos                                (0UL)          /*!< TDMA_START (Bit 0)                                    */
41060  #define R_ETHSW_TDMA_START_TDMA_START_Msk                                (0xffffffffUL) /*!< TDMA_START (Bitfield-Mask: 0xffffffff)                */
41061 /* ======================================================  TDMA_MODULO  ====================================================== */
41062  #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Pos                              (0UL)          /*!< TDMA_MODULO (Bit 0)                                   */
41063  #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Msk                              (0xffffffffUL) /*!< TDMA_MODULO (Bitfield-Mask: 0xffffffff)               */
41064 /* ======================================================  TDMA_CYCLE  ======================================================= */
41065  #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Pos                                (0UL)          /*!< TDMA_CYCLE (Bit 0)                                    */
41066  #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Msk                                (0xffffffffUL) /*!< TDMA_CYCLE (Bitfield-Mask: 0xffffffff)                */
41067 /* =====================================================  TCV_SEQ_ADDR  ====================================================== */
41068  #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Pos                              (0UL)          /*!< TCV_S_ADDR (Bit 0)                                    */
41069  #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Msk                              (0xfffUL)      /*!< TCV_S_ADDR (Bitfield-Mask: 0xfff)                     */
41070  #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Pos                               (31UL)         /*!< ADDR_AINC (Bit 31)                                    */
41071  #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Msk                               (0x80000000UL) /*!< ADDR_AINC (Bitfield-Mask: 0x01)                       */
41072 /* =====================================================  TCV_SEQ_CTRL  ====================================================== */
41073  #define R_ETHSW_TCV_SEQ_CTRL_START_Pos                                   (0UL)          /*!< START (Bit 0)                                         */
41074  #define R_ETHSW_TCV_SEQ_CTRL_START_Msk                                   (0x1UL)        /*!< START (Bitfield-Mask: 0x01)                           */
41075  #define R_ETHSW_TCV_SEQ_CTRL_INT_Pos                                     (1UL)          /*!< INT (Bit 1)                                           */
41076  #define R_ETHSW_TCV_SEQ_CTRL_INT_Msk                                     (0x2UL)        /*!< INT (Bitfield-Mask: 0x01)                             */
41077  #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Pos                               (2UL)          /*!< TCV_D_IDX (Bit 2)                                     */
41078  #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Msk                               (0x7fcUL)      /*!< TCV_D_IDX (Bitfield-Mask: 0x1ff)                      */
41079  #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Pos                                    (22UL)         /*!< GPIO (Bit 22)                                         */
41080  #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Msk                                    (0x3fc00000UL) /*!< GPIO (Bitfield-Mask: 0xff)                            */
41081  #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Pos                               (31UL)         /*!< READ_MODE (Bit 31)                                    */
41082  #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Msk                               (0x80000000UL) /*!< READ_MODE (Bitfield-Mask: 0x01)                       */
41083 /* =====================================================  TCV_SEQ_LAST  ====================================================== */
41084  #define R_ETHSW_TCV_SEQ_LAST_LAST_Pos                                    (0UL)          /*!< LAST (Bit 0)                                          */
41085  #define R_ETHSW_TCV_SEQ_LAST_LAST_Msk                                    (0xfffUL)      /*!< LAST (Bitfield-Mask: 0xfff)                           */
41086  #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Pos                                  (16UL)         /*!< ACTIVE (Bit 16)                                       */
41087  #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Msk                                  (0xfff0000UL)  /*!< ACTIVE (Bitfield-Mask: 0xfff)                         */
41088 /* ======================================================  TCV_D_ADDR  ======================================================= */
41089  #define R_ETHSW_TCV_D_ADDR_ADDR_Pos                                      (0UL)          /*!< ADDR (Bit 0)                                          */
41090  #define R_ETHSW_TCV_D_ADDR_ADDR_Msk                                      (0x1ffUL)      /*!< ADDR (Bitfield-Mask: 0x1ff)                           */
41091  #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Pos                               (31UL)         /*!< AINC_WR_ENA (Bit 31)                                  */
41092  #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Msk                               (0x80000000UL) /*!< AINC_WR_ENA (Bitfield-Mask: 0x01)                     */
41093 /* =====================================================  TCV_D_OFFSET  ====================================================== */
41094  #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Pos                            (0UL)          /*!< TCV_D_OFFSET (Bit 0)                                  */
41095  #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Msk                            (0xffffffffUL) /*!< TCV_D_OFFSET (Bitfield-Mask: 0xffffffff)              */
41096 /* ======================================================  TCV_D_CTRL  ======================================================= */
41097  #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Pos                                  (0UL)          /*!< INC_CTR0 (Bit 0)                                      */
41098  #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Msk                                  (0x1UL)        /*!< INC_CTR0 (Bitfield-Mask: 0x01)                        */
41099  #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Pos                                  (1UL)          /*!< INC_CTR1 (Bit 1)                                      */
41100  #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Msk                                  (0x2UL)        /*!< INC_CTR1 (Bitfield-Mask: 0x01)                        */
41101  #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Pos                                (2UL)          /*!< RED_PERIOD (Bit 2)                                    */
41102  #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Msk                                (0x4UL)        /*!< RED_PERIOD (Bitfield-Mask: 0x01)                      */
41103  #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Pos                                (3UL)          /*!< OUT_CT_ENA (Bit 3)                                    */
41104  #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Msk                                (0x8UL)        /*!< OUT_CT_ENA (Bitfield-Mask: 0x01)                      */
41105  #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Pos                                 (4UL)          /*!< IN_CT_ENA (Bit 4)                                     */
41106  #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Msk                                 (0x10UL)       /*!< IN_CT_ENA (Bitfield-Mask: 0x01)                       */
41107  #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Pos                              (5UL)          /*!< TRIGGER_MODE (Bit 5)                                  */
41108  #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Msk                              (0x20UL)       /*!< TRIGGER_MODE (Bitfield-Mask: 0x01)                    */
41109  #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Pos                                 (6UL)          /*!< GATE_MODE (Bit 6)                                     */
41110  #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Msk                                 (0x40UL)       /*!< GATE_MODE (Bitfield-Mask: 0x01)                       */
41111  #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Pos                                  (7UL)          /*!< HOLD_REQ (Bit 7)                                      */
41112  #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Msk                                  (0x80UL)       /*!< HOLD_REQ (Bitfield-Mask: 0x01)                        */
41113  #define R_ETHSW_TCV_D_CTRL_QGATE_Pos                                     (8UL)          /*!< QGATE (Bit 8)                                         */
41114  #define R_ETHSW_TCV_D_CTRL_QGATE_Msk                                     (0xff00UL)     /*!< QGATE (Bitfield-Mask: 0xff)                           */
41115  #define R_ETHSW_TCV_D_CTRL_PMASK_Pos                                     (16UL)         /*!< PMASK (Bit 16)                                        */
41116  #define R_ETHSW_TCV_D_CTRL_PMASK_Msk                                     (0xf0000UL)    /*!< PMASK (Bitfield-Mask: 0x0f)                           */
41117 /* =======================================================  TDMA_CTR0  ======================================================= */
41118  #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Pos                                  (0UL)          /*!< TDMA_CTR0 (Bit 0)                                     */
41119  #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Msk                                  (0xffffffffUL) /*!< TDMA_CTR0 (Bitfield-Mask: 0xffffffff)                 */
41120 /* =======================================================  TDMA_CTR1  ======================================================= */
41121  #define R_ETHSW_TDMA_CTR1_VALUE_Pos                                      (0UL)          /*!< VALUE (Bit 0)                                         */
41122  #define R_ETHSW_TDMA_CTR1_VALUE_Msk                                      (0xffUL)       /*!< VALUE (Bitfield-Mask: 0xff)                           */
41123  #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Pos                                  (8UL)          /*!< WRITE_ENA (Bit 8)                                     */
41124  #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Msk                                  (0x100UL)      /*!< WRITE_ENA (Bitfield-Mask: 0x01)                       */
41125  #define R_ETHSW_TDMA_CTR1_MAX_Pos                                        (16UL)         /*!< MAX (Bit 16)                                          */
41126  #define R_ETHSW_TDMA_CTR1_MAX_Msk                                        (0xff0000UL)   /*!< MAX (Bitfield-Mask: 0xff)                             */
41127  #define R_ETHSW_TDMA_CTR1_INT_VALUE_Pos                                  (24UL)         /*!< INT_VALUE (Bit 24)                                    */
41128  #define R_ETHSW_TDMA_CTR1_INT_VALUE_Msk                                  (0xff000000UL) /*!< INT_VALUE (Bitfield-Mask: 0xff)                       */
41129 /* ====================================================  TDMA_TCV_START  ===================================================== */
41130  #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Pos                        (0UL)          /*!< TDMA_TCV_START (Bit 0)                                */
41131  #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Msk                        (0xfffUL)      /*!< TDMA_TCV_START (Bitfield-Mask: 0xfff)                 */
41132 /* ====================================================  TIME_LOAD_NEXT  ===================================================== */
41133  #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Pos                        (0UL)          /*!< TIME_LOAD_NEXT (Bit 0)                                */
41134  #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Msk                        (0xffffffffUL) /*!< TIME_LOAD_NEXT (Bitfield-Mask: 0xffffffff)            */
41135 /* ===================================================  TDMA_IRQ_CONTROL  ==================================================== */
41136  #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Pos                          (0UL)          /*!< TCV_INT_EN (Bit 0)                                    */
41137  #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Msk                          (0x1UL)        /*!< TCV_INT_EN (Bitfield-Mask: 0x01)                      */
41138  #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Pos                         (13UL)         /*!< CTR1_INT_EN (Bit 13)                                  */
41139  #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Msk                         (0x2000UL)     /*!< CTR1_INT_EN (Bitfield-Mask: 0x01)                     */
41140 /* ===================================================  TDMA_IRQ_STAT_ACK  =================================================== */
41141  #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Pos                            (0UL)          /*!< TCV_ACK (Bit 0)                                       */
41142  #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Msk                            (0x1UL)        /*!< TCV_ACK (Bitfield-Mask: 0x01)                         */
41143  #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Pos                           (13UL)         /*!< CTR1_ACK (Bit 13)                                     */
41144  #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Msk                           (0x2000UL)     /*!< CTR1_ACK (Bitfield-Mask: 0x01)                        */
41145 /* =======================================================  TDMA_GPIO  ======================================================= */
41146  #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Pos                                (0UL)          /*!< GPIO_STATUS (Bit 0)                                   */
41147  #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Msk                                (0xffUL)       /*!< GPIO_STATUS (Bitfield-Mask: 0xff)                     */
41148  #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Pos                                  (16UL)         /*!< GPIO_MODE (Bit 16)                                    */
41149  #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Msk                                  (0xffff0000UL) /*!< GPIO_MODE (Bitfield-Mask: 0xffff)                     */
41150 /* ====================================================  RXMATCH_CONFIG  ===================================================== */
41151  #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Pos                            (0UL)          /*!< PATTERN_EN (Bit 0)                                    */
41152  #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk                            (0xfffUL)      /*!< PATTERN_EN (Bitfield-Mask: 0xfff)                     */
41153 /* =====================================================  PATTERN_CTRL  ====================================================== */
41154  #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Pos                               (0UL)          /*!< MATCH_NOT (Bit 0)                                     */
41155  #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Msk                               (0x1UL)        /*!< MATCH_NOT (Bitfield-Mask: 0x01)                       */
41156  #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Pos                                 (1UL)          /*!< MGMTFWD (Bit 1)                                       */
41157  #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Msk                                 (0x2UL)        /*!< MGMTFWD (Bitfield-Mask: 0x01)                         */
41158  #define R_ETHSW_PATTERN_CTRL_DISCARD_Pos                                 (2UL)          /*!< DISCARD (Bit 2)                                       */
41159  #define R_ETHSW_PATTERN_CTRL_DISCARD_Msk                                 (0x4UL)        /*!< DISCARD (Bitfield-Mask: 0x01)                         */
41160  #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Pos                                (3UL)          /*!< SET_PRIO (Bit 3)                                      */
41161  #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Msk                                (0x8UL)        /*!< SET_PRIO (Bitfield-Mask: 0x01)                        */
41162  #define R_ETHSW_PATTERN_CTRL_MODE_Pos                                    (4UL)          /*!< MODE (Bit 4)                                          */
41163  #define R_ETHSW_PATTERN_CTRL_MODE_Msk                                    (0x30UL)       /*!< MODE (Bitfield-Mask: 0x03)                            */
41164  #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Pos                           (6UL)          /*!< TIMER_SEL_OVR (Bit 6)                                 */
41165  #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Msk                           (0x40UL)       /*!< TIMER_SEL_OVR (Bitfield-Mask: 0x01)                   */
41166  #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Pos                           (7UL)          /*!< FORCE_FORWARD (Bit 7)                                 */
41167  #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Msk                           (0x80UL)       /*!< FORCE_FORWARD (Bitfield-Mask: 0x01)                   */
41168  #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Pos                              (8UL)          /*!< HUBTRIGGER (Bit 8)                                    */
41169  #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Msk                              (0x100UL)      /*!< HUBTRIGGER (Bitfield-Mask: 0x01)                      */
41170  #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Pos                               (9UL)          /*!< MATCH_RED (Bit 9)                                     */
41171  #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Msk                               (0x200UL)      /*!< MATCH_RED (Bitfield-Mask: 0x01)                       */
41172  #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Pos                           (10UL)         /*!< MATCH_NOT_RED (Bit 10)                                */
41173  #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Msk                           (0x400UL)      /*!< MATCH_NOT_RED (Bitfield-Mask: 0x01)                   */
41174  #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Pos                               (11UL)         /*!< VLAN_SKIP (Bit 11)                                    */
41175  #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Msk                               (0x800UL)      /*!< VLAN_SKIP (Bitfield-Mask: 0x01)                       */
41176  #define R_ETHSW_PATTERN_CTRL_PRIORITY_Pos                                (12UL)         /*!< PRIORITY (Bit 12)                                     */
41177  #define R_ETHSW_PATTERN_CTRL_PRIORITY_Msk                                (0x7000UL)     /*!< PRIORITY (Bitfield-Mask: 0x07)                        */
41178  #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Pos                            (15UL)         /*!< LEARNING_DIS (Bit 15)                                 */
41179  #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Msk                            (0x8000UL)     /*!< LEARNING_DIS (Bitfield-Mask: 0x01)                    */
41180  #define R_ETHSW_PATTERN_CTRL_PORTMASK_Pos                                (16UL)         /*!< PORTMASK (Bit 16)                                     */
41181  #define R_ETHSW_PATTERN_CTRL_PORTMASK_Msk                                (0xf0000UL)    /*!< PORTMASK (Bitfield-Mask: 0x0f)                        */
41182  #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Pos                             (22UL)         /*!< IMC_TRIGGER (Bit 22)                                  */
41183  #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Msk                             (0x400000UL)   /*!< IMC_TRIGGER (Bitfield-Mask: 0x01)                     */
41184  #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Pos                         (23UL)         /*!< IMC_TRIGGER_DLY (Bit 23)                              */
41185  #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Msk                         (0x800000UL)   /*!< IMC_TRIGGER_DLY (Bitfield-Mask: 0x01)                 */
41186  #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Pos                              (24UL)         /*!< SWAP_BYTES (Bit 24)                                   */
41187  #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Msk                              (0x1000000UL)  /*!< SWAP_BYTES (Bitfield-Mask: 0x01)                      */
41188  #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Pos                                (25UL)         /*!< MATCH_LT (Bit 25)                                     */
41189  #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Msk                                (0x2000000UL)  /*!< MATCH_LT (Bitfield-Mask: 0x01)                        */
41190  #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Pos                               (26UL)         /*!< TIMER_SEL (Bit 26)                                    */
41191  #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Msk                               (0x4000000UL)  /*!< TIMER_SEL (Bitfield-Mask: 0x01)                       */
41192  #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Pos                                (28UL)         /*!< QUEUESEL (Bit 28)                                     */
41193  #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Msk                                (0xf0000000UL) /*!< QUEUESEL (Bitfield-Mask: 0x0f)                        */
41194 /* ==================================================  PATTERN_IRQ_CONTROL  ================================================== */
41195  #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Pos                         (0UL)          /*!< MATCHINT (Bit 0)                                      */
41196  #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk                         (0xfffUL)      /*!< MATCHINT (Bitfield-Mask: 0xfff)                       */
41197  #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Pos                        (16UL)         /*!< ERROR_INT (Bit 16)                                    */
41198  #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Msk                        (0xf0000UL)    /*!< ERROR_INT (Bitfield-Mask: 0x0f)                       */
41199 /* =================================================  PATTERN_IRQ_STAT_ACK  ================================================== */
41200  #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Pos                        (0UL)          /*!< MATCHINT (Bit 0)                                      */
41201  #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Msk                        (0xfffUL)      /*!< MATCHINT (Bitfield-Mask: 0xfff)                       */
41202  #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Pos                       (16UL)         /*!< ERROR_INT (Bit 16)                                    */
41203  #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Msk                       (0xf0000UL)    /*!< ERROR_INT (Bitfield-Mask: 0x0f)                       */
41204 /* ======================================================  PTRN_VLANID  ====================================================== */
41205  #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Pos                              (0UL)          /*!< PTRN_VLANID (Bit 0)                                   */
41206  #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Msk                              (0xffffUL)     /*!< PTRN_VLANID (Bitfield-Mask: 0xffff)                   */
41207 /* ======================================================  PATTERN_SEL  ====================================================== */
41208  #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Pos                              (0UL)          /*!< PATTERN_SEL (Bit 0)                                   */
41209  #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Msk                              (0xfUL)        /*!< PATTERN_SEL (Bitfield-Mask: 0x0f)                     */
41210 /* ======================================================  PTRN_CMP_30  ====================================================== */
41211  #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Pos                              (0UL)          /*!< PTRN_CMP_30 (Bit 0)                                   */
41212  #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Msk                              (0xffffffffUL) /*!< PTRN_CMP_30 (Bitfield-Mask: 0xffffffff)               */
41213 /* ======================================================  PTRN_CMP_74  ====================================================== */
41214  #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Pos                              (0UL)          /*!< PTRN_CMP_74 (Bit 0)                                   */
41215  #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Msk                              (0xffffffffUL) /*!< PTRN_CMP_74 (Bitfield-Mask: 0xffffffff)               */
41216 /* =====================================================  PTRN_CMP_118  ====================================================== */
41217  #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Pos                            (0UL)          /*!< PTRN_CMP_118 (Bit 0)                                  */
41218  #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Msk                            (0xffffffffUL) /*!< PTRN_CMP_118 (Bitfield-Mask: 0xffffffff)              */
41219 /* ======================================================  PTRN_MSK_30  ====================================================== */
41220  #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Pos                              (0UL)          /*!< PTRN_MSK_30 (Bit 0)                                   */
41221  #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Msk                              (0xffffffffUL) /*!< PTRN_MSK_30 (Bitfield-Mask: 0xffffffff)               */
41222 /* ======================================================  PTRN_MSK_74  ====================================================== */
41223  #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Pos                              (0UL)          /*!< PTRN_MSK_74 (Bit 0)                                   */
41224  #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Msk                              (0xffffffffUL) /*!< PTRN_MSK_74 (Bitfield-Mask: 0xffffffff)               */
41225 /* =====================================================  PTRN_MSK_118  ====================================================== */
41226  #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Pos                            (0UL)          /*!< PTRN_MSK_118 (Bit 0)                                  */
41227  #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Msk                            (0xffffffffUL) /*!< PTRN_MSK_118 (Bitfield-Mask: 0xffffffff)              */
41228 
41229 /* =========================================================================================================================== */
41230 /* ================                                           R_ESC                                           ================ */
41231 /* =========================================================================================================================== */
41232 
41233 /* =========================================================  TYPE  ========================================================== */
41234  #define R_ESC_TYPE_TYPE_Pos                        (0UL)          /*!< TYPE (Bit 0)                                          */
41235  #define R_ESC_TYPE_TYPE_Msk                        (0xffUL)       /*!< TYPE (Bitfield-Mask: 0xff)                            */
41236 /* =======================================================  REVISION  ======================================================== */
41237  #define R_ESC_REVISION_REV_Pos                     (0UL)          /*!< REV (Bit 0)                                           */
41238  #define R_ESC_REVISION_REV_Msk                     (0xffUL)       /*!< REV (Bitfield-Mask: 0xff)                             */
41239 /* =========================================================  BUILD  ========================================================= */
41240  #define R_ESC_BUILD_BUILD_Pos                      (0UL)          /*!< BUILD (Bit 0)                                         */
41241  #define R_ESC_BUILD_BUILD_Msk                      (0xffUL)       /*!< BUILD (Bitfield-Mask: 0xff)                           */
41242 /* =======================================================  FMMU_NUM  ======================================================== */
41243  #define R_ESC_FMMU_NUM_NUMFMMU_Pos                 (0UL)          /*!< NUMFMMU (Bit 0)                                       */
41244  #define R_ESC_FMMU_NUM_NUMFMMU_Msk                 (0xffUL)       /*!< NUMFMMU (Bitfield-Mask: 0xff)                         */
41245 /* =====================================================  SYNC_MANAGER  ====================================================== */
41246  #define R_ESC_SYNC_MANAGER_NUMSYNC_Pos             (0UL)          /*!< NUMSYNC (Bit 0)                                       */
41247  #define R_ESC_SYNC_MANAGER_NUMSYNC_Msk             (0xffUL)       /*!< NUMSYNC (Bitfield-Mask: 0xff)                         */
41248 /* =======================================================  RAM_SIZE  ======================================================== */
41249  #define R_ESC_RAM_SIZE_RAMSIZE_Pos                 (0UL)          /*!< RAMSIZE (Bit 0)                                       */
41250  #define R_ESC_RAM_SIZE_RAMSIZE_Msk                 (0xffUL)       /*!< RAMSIZE (Bitfield-Mask: 0xff)                         */
41251 /* =======================================================  PORT_DESC  ======================================================= */
41252  #define R_ESC_PORT_DESC_P0_Pos                     (0UL)          /*!< P0 (Bit 0)                                            */
41253  #define R_ESC_PORT_DESC_P0_Msk                     (0x3UL)        /*!< P0 (Bitfield-Mask: 0x03)                              */
41254  #define R_ESC_PORT_DESC_P1_Pos                     (2UL)          /*!< P1 (Bit 2)                                            */
41255  #define R_ESC_PORT_DESC_P1_Msk                     (0xcUL)        /*!< P1 (Bitfield-Mask: 0x03)                              */
41256  #define R_ESC_PORT_DESC_P2_Pos                     (4UL)          /*!< P2 (Bit 4)                                            */
41257  #define R_ESC_PORT_DESC_P2_Msk                     (0x30UL)       /*!< P2 (Bitfield-Mask: 0x03)                              */
41258  #define R_ESC_PORT_DESC_P3_Pos                     (6UL)          /*!< P3 (Bit 6)                                            */
41259  #define R_ESC_PORT_DESC_P3_Msk                     (0xc0UL)       /*!< P3 (Bitfield-Mask: 0x03)                              */
41260 /* ========================================================  FEATURE  ======================================================== */
41261  #define R_ESC_FEATURE_FMMU_Pos                     (0UL)          /*!< FMMU (Bit 0)                                          */
41262  #define R_ESC_FEATURE_FMMU_Msk                     (0x1UL)        /*!< FMMU (Bitfield-Mask: 0x01)                            */
41263  #define R_ESC_FEATURE_DC_Pos                       (2UL)          /*!< DC (Bit 2)                                            */
41264  #define R_ESC_FEATURE_DC_Msk                       (0x4UL)        /*!< DC (Bitfield-Mask: 0x01)                              */
41265  #define R_ESC_FEATURE_DCWID_Pos                    (3UL)          /*!< DCWID (Bit 3)                                         */
41266  #define R_ESC_FEATURE_DCWID_Msk                    (0x8UL)        /*!< DCWID (Bitfield-Mask: 0x01)                           */
41267  #define R_ESC_FEATURE_LINKDECMII_Pos               (6UL)          /*!< LINKDECMII (Bit 6)                                    */
41268  #define R_ESC_FEATURE_LINKDECMII_Msk               (0x40UL)       /*!< LINKDECMII (Bitfield-Mask: 0x01)                      */
41269  #define R_ESC_FEATURE_FCS_Pos                      (7UL)          /*!< FCS (Bit 7)                                           */
41270  #define R_ESC_FEATURE_FCS_Msk                      (0x80UL)       /*!< FCS (Bitfield-Mask: 0x01)                             */
41271  #define R_ESC_FEATURE_DCSYNC_Pos                   (8UL)          /*!< DCSYNC (Bit 8)                                        */
41272  #define R_ESC_FEATURE_DCSYNC_Msk                   (0x100UL)      /*!< DCSYNC (Bitfield-Mask: 0x01)                          */
41273  #define R_ESC_FEATURE_LRW_Pos                      (9UL)          /*!< LRW (Bit 9)                                           */
41274  #define R_ESC_FEATURE_LRW_Msk                      (0x200UL)      /*!< LRW (Bitfield-Mask: 0x01)                             */
41275  #define R_ESC_FEATURE_RWSUPP_Pos                   (10UL)         /*!< RWSUPP (Bit 10)                                       */
41276  #define R_ESC_FEATURE_RWSUPP_Msk                   (0x400UL)      /*!< RWSUPP (Bitfield-Mask: 0x01)                          */
41277  #define R_ESC_FEATURE_FSCONFIG_Pos                 (11UL)         /*!< FSCONFIG (Bit 11)                                     */
41278  #define R_ESC_FEATURE_FSCONFIG_Msk                 (0x800UL)      /*!< FSCONFIG (Bitfield-Mask: 0x01)                        */
41279 /* ======================================================  STATION_ADR  ====================================================== */
41280  #define R_ESC_STATION_ADR_NODADDR_Pos              (0UL)          /*!< NODADDR (Bit 0)                                       */
41281  #define R_ESC_STATION_ADR_NODADDR_Msk              (0xffffUL)     /*!< NODADDR (Bitfield-Mask: 0xffff)                       */
41282 /* =====================================================  STATION_ALIAS  ===================================================== */
41283  #define R_ESC_STATION_ALIAS_NODALIADDR_Pos         (0UL)          /*!< NODALIADDR (Bit 0)                                    */
41284  #define R_ESC_STATION_ALIAS_NODALIADDR_Msk         (0xffffUL)     /*!< NODALIADDR (Bitfield-Mask: 0xffff)                    */
41285 /* =====================================================  WR_REG_ENABLE  ===================================================== */
41286  #define R_ESC_WR_REG_ENABLE_ENABLE_Pos             (0UL)          /*!< ENABLE (Bit 0)                                        */
41287  #define R_ESC_WR_REG_ENABLE_ENABLE_Msk             (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
41288 /* ====================================================  WR_REG_PROTECT  ===================================================== */
41289  #define R_ESC_WR_REG_PROTECT_PROTECT_Pos           (0UL)          /*!< PROTECT (Bit 0)                                       */
41290  #define R_ESC_WR_REG_PROTECT_PROTECT_Msk           (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
41291 /* =====================================================  ESC_WR_ENABLE  ===================================================== */
41292  #define R_ESC_ESC_WR_ENABLE_ENABLE_Pos             (0UL)          /*!< ENABLE (Bit 0)                                        */
41293  #define R_ESC_ESC_WR_ENABLE_ENABLE_Msk             (0x1UL)        /*!< ENABLE (Bitfield-Mask: 0x01)                          */
41294 /* ====================================================  ESC_WR_PROTECT  ===================================================== */
41295  #define R_ESC_ESC_WR_PROTECT_PROTECT_Pos           (0UL)          /*!< PROTECT (Bit 0)                                       */
41296  #define R_ESC_ESC_WR_PROTECT_PROTECT_Msk           (0x1UL)        /*!< PROTECT (Bitfield-Mask: 0x01)                         */
41297 /* ===================================================  ESC_RESET_ECAT_R  ==================================================== */
41298  #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Pos      (0UL)          /*!< RESET_ECAT (Bit 0)                                    */
41299  #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Msk      (0x3UL)        /*!< RESET_ECAT (Bitfield-Mask: 0x03)                      */
41300 /* ===================================================  ESC_RESET_ECAT_W  ==================================================== */
41301  #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Pos      (0UL)          /*!< RESET_ECAT (Bit 0)                                    */
41302  #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Msk      (0xffUL)       /*!< RESET_ECAT (Bitfield-Mask: 0xff)                      */
41303 /* ====================================================  ESC_RESET_PDI_R  ==================================================== */
41304  #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Pos        (0UL)          /*!< RESET_PDI (Bit 0)                                     */
41305  #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Msk        (0x3UL)        /*!< RESET_PDI (Bitfield-Mask: 0x03)                       */
41306 /* ====================================================  ESC_RESET_PDI_W  ==================================================== */
41307  #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Pos        (0UL)          /*!< RESET_PDI (Bit 0)                                     */
41308  #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Msk        (0xffUL)       /*!< RESET_PDI (Bitfield-Mask: 0xff)                       */
41309 /* ====================================================  ESC_DL_CONTROL  ===================================================== */
41310  #define R_ESC_ESC_DL_CONTROL_FWDRULE_Pos           (0UL)          /*!< FWDRULE (Bit 0)                                       */
41311  #define R_ESC_ESC_DL_CONTROL_FWDRULE_Msk           (0x1UL)        /*!< FWDRULE (Bitfield-Mask: 0x01)                         */
41312  #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Pos           (1UL)          /*!< TEMPUSE (Bit 1)                                       */
41313  #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Msk           (0x2UL)        /*!< TEMPUSE (Bitfield-Mask: 0x01)                         */
41314  #define R_ESC_ESC_DL_CONTROL_LP0_Pos               (8UL)          /*!< LP0 (Bit 8)                                           */
41315  #define R_ESC_ESC_DL_CONTROL_LP0_Msk               (0x300UL)      /*!< LP0 (Bitfield-Mask: 0x03)                             */
41316  #define R_ESC_ESC_DL_CONTROL_LP1_Pos               (10UL)         /*!< LP1 (Bit 10)                                          */
41317  #define R_ESC_ESC_DL_CONTROL_LP1_Msk               (0xc00UL)      /*!< LP1 (Bitfield-Mask: 0x03)                             */
41318  #define R_ESC_ESC_DL_CONTROL_LP2_Pos               (12UL)         /*!< LP2 (Bit 12)                                          */
41319  #define R_ESC_ESC_DL_CONTROL_LP2_Msk               (0x3000UL)     /*!< LP2 (Bitfield-Mask: 0x03)                             */
41320  #define R_ESC_ESC_DL_CONTROL_LP3_Pos               (14UL)         /*!< LP3 (Bit 14)                                          */
41321  #define R_ESC_ESC_DL_CONTROL_LP3_Msk               (0xc000UL)     /*!< LP3 (Bitfield-Mask: 0x03)                             */
41322  #define R_ESC_ESC_DL_CONTROL_RXFIFO_Pos            (16UL)         /*!< RXFIFO (Bit 16)                                       */
41323  #define R_ESC_ESC_DL_CONTROL_RXFIFO_Msk            (0x70000UL)    /*!< RXFIFO (Bitfield-Mask: 0x07)                          */
41324  #define R_ESC_ESC_DL_CONTROL_STAALIAS_Pos          (24UL)         /*!< STAALIAS (Bit 24)                                     */
41325  #define R_ESC_ESC_DL_CONTROL_STAALIAS_Msk          (0x1000000UL)  /*!< STAALIAS (Bitfield-Mask: 0x01)                        */
41326 /* ==================================================  PHYSICAL_RW_OFFSET  =================================================== */
41327  #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Pos      (0UL)          /*!< RWOFFSET (Bit 0)                                      */
41328  #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Msk      (0xffffUL)     /*!< RWOFFSET (Bitfield-Mask: 0xffff)                      */
41329 /* =====================================================  ESC_DL_STATUS  ===================================================== */
41330  #define R_ESC_ESC_DL_STATUS_PDIOPE_Pos             (0UL)          /*!< PDIOPE (Bit 0)                                        */
41331  #define R_ESC_ESC_DL_STATUS_PDIOPE_Msk             (0x1UL)        /*!< PDIOPE (Bitfield-Mask: 0x01)                          */
41332  #define R_ESC_ESC_DL_STATUS_PDIWDST_Pos            (1UL)          /*!< PDIWDST (Bit 1)                                       */
41333  #define R_ESC_ESC_DL_STATUS_PDIWDST_Msk            (0x2UL)        /*!< PDIWDST (Bitfield-Mask: 0x01)                         */
41334  #define R_ESC_ESC_DL_STATUS_ENHLINKD_Pos           (2UL)          /*!< ENHLINKD (Bit 2)                                      */
41335  #define R_ESC_ESC_DL_STATUS_ENHLINKD_Msk           (0x4UL)        /*!< ENHLINKD (Bitfield-Mask: 0x01)                        */
41336  #define R_ESC_ESC_DL_STATUS_PHYP0_Pos              (4UL)          /*!< PHYP0 (Bit 4)                                         */
41337  #define R_ESC_ESC_DL_STATUS_PHYP0_Msk              (0x10UL)       /*!< PHYP0 (Bitfield-Mask: 0x01)                           */
41338  #define R_ESC_ESC_DL_STATUS_PHYP1_Pos              (5UL)          /*!< PHYP1 (Bit 5)                                         */
41339  #define R_ESC_ESC_DL_STATUS_PHYP1_Msk              (0x20UL)       /*!< PHYP1 (Bitfield-Mask: 0x01)                           */
41340  #define R_ESC_ESC_DL_STATUS_PHYP2_Pos              (6UL)          /*!< PHYP2 (Bit 6)                                         */
41341  #define R_ESC_ESC_DL_STATUS_PHYP2_Msk              (0x40UL)       /*!< PHYP2 (Bitfield-Mask: 0x01)                           */
41342  #define R_ESC_ESC_DL_STATUS_PHYP3_Pos              (7UL)          /*!< PHYP3 (Bit 7)                                         */
41343  #define R_ESC_ESC_DL_STATUS_PHYP3_Msk              (0x80UL)       /*!< PHYP3 (Bitfield-Mask: 0x01)                           */
41344  #define R_ESC_ESC_DL_STATUS_LP0_Pos                (8UL)          /*!< LP0 (Bit 8)                                           */
41345  #define R_ESC_ESC_DL_STATUS_LP0_Msk                (0x100UL)      /*!< LP0 (Bitfield-Mask: 0x01)                             */
41346  #define R_ESC_ESC_DL_STATUS_COMP0_Pos              (9UL)          /*!< COMP0 (Bit 9)                                         */
41347  #define R_ESC_ESC_DL_STATUS_COMP0_Msk              (0x200UL)      /*!< COMP0 (Bitfield-Mask: 0x01)                           */
41348  #define R_ESC_ESC_DL_STATUS_LP1_Pos                (10UL)         /*!< LP1 (Bit 10)                                          */
41349  #define R_ESC_ESC_DL_STATUS_LP1_Msk                (0x400UL)      /*!< LP1 (Bitfield-Mask: 0x01)                             */
41350  #define R_ESC_ESC_DL_STATUS_COMP1_Pos              (11UL)         /*!< COMP1 (Bit 11)                                        */
41351  #define R_ESC_ESC_DL_STATUS_COMP1_Msk              (0x800UL)      /*!< COMP1 (Bitfield-Mask: 0x01)                           */
41352  #define R_ESC_ESC_DL_STATUS_LP2_Pos                (12UL)         /*!< LP2 (Bit 12)                                          */
41353  #define R_ESC_ESC_DL_STATUS_LP2_Msk                (0x1000UL)     /*!< LP2 (Bitfield-Mask: 0x01)                             */
41354  #define R_ESC_ESC_DL_STATUS_COMP2_Pos              (13UL)         /*!< COMP2 (Bit 13)                                        */
41355  #define R_ESC_ESC_DL_STATUS_COMP2_Msk              (0x2000UL)     /*!< COMP2 (Bitfield-Mask: 0x01)                           */
41356  #define R_ESC_ESC_DL_STATUS_LP3_Pos                (14UL)         /*!< LP3 (Bit 14)                                          */
41357  #define R_ESC_ESC_DL_STATUS_LP3_Msk                (0x4000UL)     /*!< LP3 (Bitfield-Mask: 0x01)                             */
41358  #define R_ESC_ESC_DL_STATUS_COMP3_Pos              (15UL)         /*!< COMP3 (Bit 15)                                        */
41359  #define R_ESC_ESC_DL_STATUS_COMP3_Msk              (0x8000UL)     /*!< COMP3 (Bitfield-Mask: 0x01)                           */
41360 /* ======================================================  AL_CONTROL  ======================================================= */
41361  #define R_ESC_AL_CONTROL_INISTATE_Pos              (0UL)          /*!< INISTATE (Bit 0)                                      */
41362  #define R_ESC_AL_CONTROL_INISTATE_Msk              (0xfUL)        /*!< INISTATE (Bitfield-Mask: 0x0f)                        */
41363  #define R_ESC_AL_CONTROL_ERRINDACK_Pos             (4UL)          /*!< ERRINDACK (Bit 4)                                     */
41364  #define R_ESC_AL_CONTROL_ERRINDACK_Msk             (0x10UL)       /*!< ERRINDACK (Bitfield-Mask: 0x01)                       */
41365  #define R_ESC_AL_CONTROL_DEVICEID_Pos              (5UL)          /*!< DEVICEID (Bit 5)                                      */
41366  #define R_ESC_AL_CONTROL_DEVICEID_Msk              (0x20UL)       /*!< DEVICEID (Bitfield-Mask: 0x01)                        */
41367 /* =======================================================  AL_STATUS  ======================================================= */
41368  #define R_ESC_AL_STATUS_ACTSTATE_Pos               (0UL)          /*!< ACTSTATE (Bit 0)                                      */
41369  #define R_ESC_AL_STATUS_ACTSTATE_Msk               (0xfUL)        /*!< ACTSTATE (Bitfield-Mask: 0x0f)                        */
41370  #define R_ESC_AL_STATUS_ERR_Pos                    (4UL)          /*!< ERR (Bit 4)                                           */
41371  #define R_ESC_AL_STATUS_ERR_Msk                    (0x10UL)       /*!< ERR (Bitfield-Mask: 0x01)                             */
41372  #define R_ESC_AL_STATUS_DEVICEID_Pos               (5UL)          /*!< DEVICEID (Bit 5)                                      */
41373  #define R_ESC_AL_STATUS_DEVICEID_Msk               (0x20UL)       /*!< DEVICEID (Bitfield-Mask: 0x01)                        */
41374 /* ====================================================  AL_STATUS_CODE  ===================================================== */
41375  #define R_ESC_AL_STATUS_CODE_STATUSCODE_Pos        (0UL)          /*!< STATUSCODE (Bit 0)                                    */
41376  #define R_ESC_AL_STATUS_CODE_STATUSCODE_Msk        (0xffffUL)     /*!< STATUSCODE (Bitfield-Mask: 0xffff)                    */
41377 /* ===================================================  RUN_LED_OVERRIDE  ==================================================== */
41378  #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Pos         (0UL)          /*!< LEDCODE (Bit 0)                                       */
41379  #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Msk         (0xfUL)        /*!< LEDCODE (Bitfield-Mask: 0x0f)                         */
41380  #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Pos      (4UL)          /*!< OVERRIDEEN (Bit 4)                                    */
41381  #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Msk      (0x10UL)       /*!< OVERRIDEEN (Bitfield-Mask: 0x01)                      */
41382 /* ===================================================  ERR_LED_OVERRIDE  ==================================================== */
41383  #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Pos         (0UL)          /*!< LEDCODE (Bit 0)                                       */
41384  #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Msk         (0xfUL)        /*!< LEDCODE (Bitfield-Mask: 0x0f)                         */
41385  #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Pos      (4UL)          /*!< OVERRIDEEN (Bit 4)                                    */
41386  #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Msk      (0x10UL)       /*!< OVERRIDEEN (Bitfield-Mask: 0x01)                      */
41387 /* ======================================================  PDI_CONTROL  ====================================================== */
41388  #define R_ESC_PDI_CONTROL_PDI_Pos                  (0UL)          /*!< PDI (Bit 0)                                           */
41389  #define R_ESC_PDI_CONTROL_PDI_Msk                  (0xffUL)       /*!< PDI (Bitfield-Mask: 0xff)                             */
41390 /* ======================================================  ESC_CONFIG  ======================================================= */
41391  #define R_ESC_ESC_CONFIG_DEVEMU_Pos                (0UL)          /*!< DEVEMU (Bit 0)                                        */
41392  #define R_ESC_ESC_CONFIG_DEVEMU_Msk                (0x1UL)        /*!< DEVEMU (Bitfield-Mask: 0x01)                          */
41393  #define R_ESC_ESC_CONFIG_ENLALLP_Pos               (1UL)          /*!< ENLALLP (Bit 1)                                       */
41394  #define R_ESC_ESC_CONFIG_ENLALLP_Msk               (0x2UL)        /*!< ENLALLP (Bitfield-Mask: 0x01)                         */
41395  #define R_ESC_ESC_CONFIG_DCSYNC_Pos                (2UL)          /*!< DCSYNC (Bit 2)                                        */
41396  #define R_ESC_ESC_CONFIG_DCSYNC_Msk                (0x4UL)        /*!< DCSYNC (Bitfield-Mask: 0x01)                          */
41397  #define R_ESC_ESC_CONFIG_DCLATCH_Pos               (3UL)          /*!< DCLATCH (Bit 3)                                       */
41398  #define R_ESC_ESC_CONFIG_DCLATCH_Msk               (0x8UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
41399  #define R_ESC_ESC_CONFIG_ENLP0_Pos                 (4UL)          /*!< ENLP0 (Bit 4)                                         */
41400  #define R_ESC_ESC_CONFIG_ENLP0_Msk                 (0x10UL)       /*!< ENLP0 (Bitfield-Mask: 0x01)                           */
41401  #define R_ESC_ESC_CONFIG_ENLP1_Pos                 (5UL)          /*!< ENLP1 (Bit 5)                                         */
41402  #define R_ESC_ESC_CONFIG_ENLP1_Msk                 (0x20UL)       /*!< ENLP1 (Bitfield-Mask: 0x01)                           */
41403  #define R_ESC_ESC_CONFIG_ENLP2_Pos                 (6UL)          /*!< ENLP2 (Bit 6)                                         */
41404  #define R_ESC_ESC_CONFIG_ENLP2_Msk                 (0x40UL)       /*!< ENLP2 (Bitfield-Mask: 0x01)                           */
41405  #define R_ESC_ESC_CONFIG_ENLP3_Pos                 (7UL)          /*!< ENLP3 (Bit 7)                                         */
41406  #define R_ESC_ESC_CONFIG_ENLP3_Msk                 (0x80UL)       /*!< ENLP3 (Bitfield-Mask: 0x01)                           */
41407 /* ======================================================  PDI_CONFIG  ======================================================= */
41408  #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Pos          (0UL)          /*!< ONCHIPBUSCLK (Bit 0)                                  */
41409  #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Msk          (0x1fUL)       /*!< ONCHIPBUSCLK (Bitfield-Mask: 0x1f)                    */
41410  #define R_ESC_PDI_CONFIG_ONCHIPBUS_Pos             (5UL)          /*!< ONCHIPBUS (Bit 5)                                     */
41411  #define R_ESC_PDI_CONFIG_ONCHIPBUS_Msk             (0xe0UL)       /*!< ONCHIPBUS (Bitfield-Mask: 0x07)                       */
41412 /* ===================================================  SYNC_LATCH_CONFIG  =================================================== */
41413  #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Pos       (0UL)          /*!< SYNC0OUT (Bit 0)                                      */
41414  #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Msk       (0x3UL)        /*!< SYNC0OUT (Bitfield-Mask: 0x03)                        */
41415  #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Pos       (2UL)          /*!< SYNCLAT0 (Bit 2)                                      */
41416  #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Msk       (0x4UL)        /*!< SYNCLAT0 (Bitfield-Mask: 0x01)                        */
41417  #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Pos       (3UL)          /*!< SYNC0MAP (Bit 3)                                      */
41418  #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Msk       (0x8UL)        /*!< SYNC0MAP (Bitfield-Mask: 0x01)                        */
41419  #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Pos       (4UL)          /*!< SYNC1OUT (Bit 4)                                      */
41420  #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Msk       (0x30UL)       /*!< SYNC1OUT (Bitfield-Mask: 0x03)                        */
41421  #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Pos       (6UL)          /*!< SYNCLAT1 (Bit 6)                                      */
41422  #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Msk       (0x40UL)       /*!< SYNCLAT1 (Bitfield-Mask: 0x01)                        */
41423  #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Pos       (7UL)          /*!< SYNC1MAP (Bit 7)                                      */
41424  #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Msk       (0x80UL)       /*!< SYNC1MAP (Bitfield-Mask: 0x01)                        */
41425 /* ====================================================  EXT_PDI_CONFIG  ===================================================== */
41426  #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Pos        (0UL)          /*!< DATABUSWID (Bit 0)                                    */
41427  #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Msk        (0x3UL)        /*!< DATABUSWID (Bitfield-Mask: 0x03)                      */
41428 /* ====================================================  ECAT_EVENT_MASK  ==================================================== */
41429  #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Pos       (0UL)          /*!< ECATEVMASK (Bit 0)                                    */
41430  #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Msk       (0xffffUL)     /*!< ECATEVMASK (Bitfield-Mask: 0xffff)                    */
41431 /* =====================================================  AL_EVENT_MASK  ===================================================== */
41432  #define R_ESC_AL_EVENT_MASK_ALEVMASK_Pos           (0UL)          /*!< ALEVMASK (Bit 0)                                      */
41433  #define R_ESC_AL_EVENT_MASK_ALEVMASK_Msk           (0xffffffffUL) /*!< ALEVMASK (Bitfield-Mask: 0xffffffff)                  */
41434 /* ====================================================  ECAT_EVENT_REQ  ===================================================== */
41435  #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Pos           (0UL)          /*!< DCLATCH (Bit 0)                                       */
41436  #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Msk           (0x1UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
41437  #define R_ESC_ECAT_EVENT_REQ_DLSTA_Pos             (2UL)          /*!< DLSTA (Bit 2)                                         */
41438  #define R_ESC_ECAT_EVENT_REQ_DLSTA_Msk             (0x4UL)        /*!< DLSTA (Bitfield-Mask: 0x01)                           */
41439  #define R_ESC_ECAT_EVENT_REQ_ALSTA_Pos             (3UL)          /*!< ALSTA (Bit 3)                                         */
41440  #define R_ESC_ECAT_EVENT_REQ_ALSTA_Msk             (0x8UL)        /*!< ALSTA (Bitfield-Mask: 0x01)                           */
41441  #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Pos            (4UL)          /*!< SMSTA0 (Bit 4)                                        */
41442  #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Msk            (0x10UL)       /*!< SMSTA0 (Bitfield-Mask: 0x01)                          */
41443  #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Pos            (5UL)          /*!< SMSTA1 (Bit 5)                                        */
41444  #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Msk            (0x20UL)       /*!< SMSTA1 (Bitfield-Mask: 0x01)                          */
41445  #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Pos            (6UL)          /*!< SMSTA2 (Bit 6)                                        */
41446  #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Msk            (0x40UL)       /*!< SMSTA2 (Bitfield-Mask: 0x01)                          */
41447  #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Pos            (7UL)          /*!< SMSTA3 (Bit 7)                                        */
41448  #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Msk            (0x80UL)       /*!< SMSTA3 (Bitfield-Mask: 0x01)                          */
41449  #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Pos            (8UL)          /*!< SMSTA4 (Bit 8)                                        */
41450  #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Msk            (0x100UL)      /*!< SMSTA4 (Bitfield-Mask: 0x01)                          */
41451  #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Pos            (9UL)          /*!< SMSTA5 (Bit 9)                                        */
41452  #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Msk            (0x200UL)      /*!< SMSTA5 (Bitfield-Mask: 0x01)                          */
41453  #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Pos            (10UL)         /*!< SMSTA6 (Bit 10)                                       */
41454  #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Msk            (0x400UL)      /*!< SMSTA6 (Bitfield-Mask: 0x01)                          */
41455  #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Pos            (11UL)         /*!< SMSTA7 (Bit 11)                                       */
41456  #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Msk            (0x800UL)      /*!< SMSTA7 (Bitfield-Mask: 0x01)                          */
41457 /* =====================================================  AL_EVENT_REQ  ====================================================== */
41458  #define R_ESC_AL_EVENT_REQ_ALCTRL_Pos              (0UL)          /*!< ALCTRL (Bit 0)                                        */
41459  #define R_ESC_AL_EVENT_REQ_ALCTRL_Msk              (0x1UL)        /*!< ALCTRL (Bitfield-Mask: 0x01)                          */
41460  #define R_ESC_AL_EVENT_REQ_DCLATCH_Pos             (1UL)          /*!< DCLATCH (Bit 1)                                       */
41461  #define R_ESC_AL_EVENT_REQ_DCLATCH_Msk             (0x2UL)        /*!< DCLATCH (Bitfield-Mask: 0x01)                         */
41462  #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Pos          (2UL)          /*!< DCSYNC0STA (Bit 2)                                    */
41463  #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Msk          (0x4UL)        /*!< DCSYNC0STA (Bitfield-Mask: 0x01)                      */
41464  #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Pos          (3UL)          /*!< DCSYNC1STA (Bit 3)                                    */
41465  #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Msk          (0x8UL)        /*!< DCSYNC1STA (Bitfield-Mask: 0x01)                      */
41466  #define R_ESC_AL_EVENT_REQ_SYNCACT_Pos             (4UL)          /*!< SYNCACT (Bit 4)                                       */
41467  #define R_ESC_AL_EVENT_REQ_SYNCACT_Msk             (0x10UL)       /*!< SYNCACT (Bitfield-Mask: 0x01)                         */
41468  #define R_ESC_AL_EVENT_REQ_WDPD_Pos                (6UL)          /*!< WDPD (Bit 6)                                          */
41469  #define R_ESC_AL_EVENT_REQ_WDPD_Msk                (0x40UL)       /*!< WDPD (Bitfield-Mask: 0x01)                            */
41470  #define R_ESC_AL_EVENT_REQ_SMINT0_Pos              (8UL)          /*!< SMINT0 (Bit 8)                                        */
41471  #define R_ESC_AL_EVENT_REQ_SMINT0_Msk              (0x100UL)      /*!< SMINT0 (Bitfield-Mask: 0x01)                          */
41472  #define R_ESC_AL_EVENT_REQ_SMINT1_Pos              (9UL)          /*!< SMINT1 (Bit 9)                                        */
41473  #define R_ESC_AL_EVENT_REQ_SMINT1_Msk              (0x200UL)      /*!< SMINT1 (Bitfield-Mask: 0x01)                          */
41474  #define R_ESC_AL_EVENT_REQ_SMINT2_Pos              (10UL)         /*!< SMINT2 (Bit 10)                                       */
41475  #define R_ESC_AL_EVENT_REQ_SMINT2_Msk              (0x400UL)      /*!< SMINT2 (Bitfield-Mask: 0x01)                          */
41476  #define R_ESC_AL_EVENT_REQ_SMINT3_Pos              (11UL)         /*!< SMINT3 (Bit 11)                                       */
41477  #define R_ESC_AL_EVENT_REQ_SMINT3_Msk              (0x800UL)      /*!< SMINT3 (Bitfield-Mask: 0x01)                          */
41478  #define R_ESC_AL_EVENT_REQ_SMINT4_Pos              (12UL)         /*!< SMINT4 (Bit 12)                                       */
41479  #define R_ESC_AL_EVENT_REQ_SMINT4_Msk              (0x1000UL)     /*!< SMINT4 (Bitfield-Mask: 0x01)                          */
41480  #define R_ESC_AL_EVENT_REQ_SMINT5_Pos              (13UL)         /*!< SMINT5 (Bit 13)                                       */
41481  #define R_ESC_AL_EVENT_REQ_SMINT5_Msk              (0x2000UL)     /*!< SMINT5 (Bitfield-Mask: 0x01)                          */
41482  #define R_ESC_AL_EVENT_REQ_SMINT6_Pos              (14UL)         /*!< SMINT6 (Bit 14)                                       */
41483  #define R_ESC_AL_EVENT_REQ_SMINT6_Msk              (0x4000UL)     /*!< SMINT6 (Bitfield-Mask: 0x01)                          */
41484  #define R_ESC_AL_EVENT_REQ_SMINT7_Pos              (15UL)         /*!< SMINT7 (Bit 15)                                       */
41485  #define R_ESC_AL_EVENT_REQ_SMINT7_Msk              (0x8000UL)     /*!< SMINT7 (Bitfield-Mask: 0x01)                          */
41486 /* =====================================================  RX_ERR_COUNT  ====================================================== */
41487  #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Pos           (0UL)          /*!< INVFRMCNT (Bit 0)                                     */
41488  #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Msk           (0xffUL)       /*!< INVFRMCNT (Bitfield-Mask: 0xff)                       */
41489  #define R_ESC_RX_ERR_COUNT_RXERRCNT_Pos            (8UL)          /*!< RXERRCNT (Bit 8)                                      */
41490  #define R_ESC_RX_ERR_COUNT_RXERRCNT_Msk            (0xff00UL)     /*!< RXERRCNT (Bitfield-Mask: 0xff)                        */
41491 /* ===================================================  FWD_RX_ERR_COUNT  ==================================================== */
41492  #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Pos       (0UL)          /*!< FWDERRCNT (Bit 0)                                     */
41493  #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Msk       (0xffUL)       /*!< FWDERRCNT (Bitfield-Mask: 0xff)                       */
41494 /* ==================================================  ECAT_PROC_ERR_COUNT  ================================================== */
41495  #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Pos    (0UL)          /*!< EPUERRCNT (Bit 0)                                     */
41496  #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Msk    (0xffUL)       /*!< EPUERRCNT (Bitfield-Mask: 0xff)                       */
41497 /* =====================================================  PDI_ERR_COUNT  ===================================================== */
41498  #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Pos          (0UL)          /*!< PDIERRCNT (Bit 0)                                     */
41499  #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Msk          (0xffUL)       /*!< PDIERRCNT (Bitfield-Mask: 0xff)                       */
41500 /* ====================================================  LOST_LINK_COUNT  ==================================================== */
41501  #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Pos      (0UL)          /*!< LOSTLINKCNT (Bit 0)                                   */
41502  #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Msk      (0xffUL)       /*!< LOSTLINKCNT (Bitfield-Mask: 0xff)                     */
41503 /* =======================================================  WD_DIVIDE  ======================================================= */
41504  #define R_ESC_WD_DIVIDE_WDDIV_Pos                  (0UL)          /*!< WDDIV (Bit 0)                                         */
41505  #define R_ESC_WD_DIVIDE_WDDIV_Msk                  (0xffffUL)     /*!< WDDIV (Bitfield-Mask: 0xffff)                         */
41506 /* ========================================================  WDT_PDI  ======================================================== */
41507  #define R_ESC_WDT_PDI_WDTIMPDI_Pos                 (0UL)          /*!< WDTIMPDI (Bit 0)                                      */
41508  #define R_ESC_WDT_PDI_WDTIMPDI_Msk                 (0xffffUL)     /*!< WDTIMPDI (Bitfield-Mask: 0xffff)                      */
41509 /* =======================================================  WDT_DATA  ======================================================== */
41510  #define R_ESC_WDT_DATA_WDTIMPD_Pos                 (0UL)          /*!< WDTIMPD (Bit 0)                                       */
41511  #define R_ESC_WDT_DATA_WDTIMPD_Msk                 (0xffffUL)     /*!< WDTIMPD (Bitfield-Mask: 0xffff)                       */
41512 /* =======================================================  WDS_DATA  ======================================================== */
41513  #define R_ESC_WDS_DATA_WDSTAPD_Pos                 (0UL)          /*!< WDSTAPD (Bit 0)                                       */
41514  #define R_ESC_WDS_DATA_WDSTAPD_Msk                 (0x1UL)        /*!< WDSTAPD (Bitfield-Mask: 0x01)                         */
41515 /* =======================================================  WDC_DATA  ======================================================== */
41516  #define R_ESC_WDC_DATA_WDCNTPD_Pos                 (0UL)          /*!< WDCNTPD (Bit 0)                                       */
41517  #define R_ESC_WDC_DATA_WDCNTPD_Msk                 (0xffUL)       /*!< WDCNTPD (Bitfield-Mask: 0xff)                         */
41518 /* ========================================================  WDC_PDI  ======================================================== */
41519  #define R_ESC_WDC_PDI_WDCNTPDI_Pos                 (0UL)          /*!< WDCNTPDI (Bit 0)                                      */
41520  #define R_ESC_WDC_PDI_WDCNTPDI_Msk                 (0xffUL)       /*!< WDCNTPDI (Bitfield-Mask: 0xff)                        */
41521 /* =======================================================  EEP_CONF  ======================================================== */
41522  #define R_ESC_EEP_CONF_CTRLPDI_Pos                 (0UL)          /*!< CTRLPDI (Bit 0)                                       */
41523  #define R_ESC_EEP_CONF_CTRLPDI_Msk                 (0x1UL)        /*!< CTRLPDI (Bitfield-Mask: 0x01)                         */
41524  #define R_ESC_EEP_CONF_FORCEECAT_Pos               (1UL)          /*!< FORCEECAT (Bit 1)                                     */
41525  #define R_ESC_EEP_CONF_FORCEECAT_Msk               (0x2UL)        /*!< FORCEECAT (Bitfield-Mask: 0x01)                       */
41526 /* =======================================================  EEP_STATE  ======================================================= */
41527  #define R_ESC_EEP_STATE_PDIACCESS_Pos              (0UL)          /*!< PDIACCESS (Bit 0)                                     */
41528  #define R_ESC_EEP_STATE_PDIACCESS_Msk              (0x1UL)        /*!< PDIACCESS (Bitfield-Mask: 0x01)                       */
41529 /* =====================================================  EEP_CONT_STAT  ===================================================== */
41530  #define R_ESC_EEP_CONT_STAT_ECATWREN_Pos           (0UL)          /*!< ECATWREN (Bit 0)                                      */
41531  #define R_ESC_EEP_CONT_STAT_ECATWREN_Msk           (0x1UL)        /*!< ECATWREN (Bitfield-Mask: 0x01)                        */
41532  #define R_ESC_EEP_CONT_STAT_READBYTE_Pos           (6UL)          /*!< READBYTE (Bit 6)                                      */
41533  #define R_ESC_EEP_CONT_STAT_READBYTE_Msk           (0x40UL)       /*!< READBYTE (Bitfield-Mask: 0x01)                        */
41534  #define R_ESC_EEP_CONT_STAT_PROMSIZE_Pos           (7UL)          /*!< PROMSIZE (Bit 7)                                      */
41535  #define R_ESC_EEP_CONT_STAT_PROMSIZE_Msk           (0x80UL)       /*!< PROMSIZE (Bitfield-Mask: 0x01)                        */
41536  #define R_ESC_EEP_CONT_STAT_COMMAND_Pos            (8UL)          /*!< COMMAND (Bit 8)                                       */
41537  #define R_ESC_EEP_CONT_STAT_COMMAND_Msk            (0x700UL)      /*!< COMMAND (Bitfield-Mask: 0x07)                         */
41538  #define R_ESC_EEP_CONT_STAT_CKSUMERR_Pos           (11UL)         /*!< CKSUMERR (Bit 11)                                     */
41539  #define R_ESC_EEP_CONT_STAT_CKSUMERR_Msk           (0x800UL)      /*!< CKSUMERR (Bitfield-Mask: 0x01)                        */
41540  #define R_ESC_EEP_CONT_STAT_LOADSTA_Pos            (12UL)         /*!< LOADSTA (Bit 12)                                      */
41541  #define R_ESC_EEP_CONT_STAT_LOADSTA_Msk            (0x1000UL)     /*!< LOADSTA (Bitfield-Mask: 0x01)                         */
41542  #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Pos          (13UL)         /*!< ACKCMDERR (Bit 13)                                    */
41543  #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Msk          (0x2000UL)     /*!< ACKCMDERR (Bitfield-Mask: 0x01)                       */
41544  #define R_ESC_EEP_CONT_STAT_WRENERR_Pos            (14UL)         /*!< WRENERR (Bit 14)                                      */
41545  #define R_ESC_EEP_CONT_STAT_WRENERR_Msk            (0x4000UL)     /*!< WRENERR (Bitfield-Mask: 0x01)                         */
41546  #define R_ESC_EEP_CONT_STAT_BUSY_Pos               (15UL)         /*!< BUSY (Bit 15)                                         */
41547  #define R_ESC_EEP_CONT_STAT_BUSY_Msk               (0x8000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
41548 /* ========================================================  EEP_ADR  ======================================================== */
41549  #define R_ESC_EEP_ADR_ADDRESS_Pos                  (0UL)          /*!< ADDRESS (Bit 0)                                       */
41550  #define R_ESC_EEP_ADR_ADDRESS_Msk                  (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff)                   */
41551 /* =======================================================  EEP_DATA  ======================================================== */
41552  #define R_ESC_EEP_DATA_LODATA_Pos                  (0UL)          /*!< LODATA (Bit 0)                                        */
41553  #define R_ESC_EEP_DATA_LODATA_Msk                  (0xffffUL)     /*!< LODATA (Bitfield-Mask: 0xffff)                        */
41554  #define R_ESC_EEP_DATA_HIDATA_Pos                  (16UL)         /*!< HIDATA (Bit 16)                                       */
41555  #define R_ESC_EEP_DATA_HIDATA_Msk                  (0xffff0000UL) /*!< HIDATA (Bitfield-Mask: 0xffff)                        */
41556 /* =====================================================  MII_CONT_STAT  ===================================================== */
41557  #define R_ESC_MII_CONT_STAT_WREN_Pos               (0UL)          /*!< WREN (Bit 0)                                          */
41558  #define R_ESC_MII_CONT_STAT_WREN_Msk               (0x1UL)        /*!< WREN (Bitfield-Mask: 0x01)                            */
41559  #define R_ESC_MII_CONT_STAT_PDICTRL_Pos            (1UL)          /*!< PDICTRL (Bit 1)                                       */
41560  #define R_ESC_MII_CONT_STAT_PDICTRL_Msk            (0x2UL)        /*!< PDICTRL (Bitfield-Mask: 0x01)                         */
41561  #define R_ESC_MII_CONT_STAT_MILINK_Pos             (2UL)          /*!< MILINK (Bit 2)                                        */
41562  #define R_ESC_MII_CONT_STAT_MILINK_Msk             (0x4UL)        /*!< MILINK (Bitfield-Mask: 0x01)                          */
41563  #define R_ESC_MII_CONT_STAT_PHYOFFSET_Pos          (3UL)          /*!< PHYOFFSET (Bit 3)                                     */
41564  #define R_ESC_MII_CONT_STAT_PHYOFFSET_Msk          (0xf8UL)       /*!< PHYOFFSET (Bitfield-Mask: 0x1f)                       */
41565  #define R_ESC_MII_CONT_STAT_COMMAND_Pos            (8UL)          /*!< COMMAND (Bit 8)                                       */
41566  #define R_ESC_MII_CONT_STAT_COMMAND_Msk            (0x300UL)      /*!< COMMAND (Bitfield-Mask: 0x03)                         */
41567  #define R_ESC_MII_CONT_STAT_READERR_Pos            (13UL)         /*!< READERR (Bit 13)                                      */
41568  #define R_ESC_MII_CONT_STAT_READERR_Msk            (0x2000UL)     /*!< READERR (Bitfield-Mask: 0x01)                         */
41569  #define R_ESC_MII_CONT_STAT_CMDERR_Pos             (14UL)         /*!< CMDERR (Bit 14)                                       */
41570  #define R_ESC_MII_CONT_STAT_CMDERR_Msk             (0x4000UL)     /*!< CMDERR (Bitfield-Mask: 0x01)                          */
41571  #define R_ESC_MII_CONT_STAT_BUSY_Pos               (15UL)         /*!< BUSY (Bit 15)                                         */
41572  #define R_ESC_MII_CONT_STAT_BUSY_Msk               (0x8000UL)     /*!< BUSY (Bitfield-Mask: 0x01)                            */
41573 /* ========================================================  PHY_ADR  ======================================================== */
41574  #define R_ESC_PHY_ADR_PHYADDR_Pos                  (0UL)          /*!< PHYADDR (Bit 0)                                       */
41575  #define R_ESC_PHY_ADR_PHYADDR_Msk                  (0x1fUL)       /*!< PHYADDR (Bitfield-Mask: 0x1f)                         */
41576 /* ======================================================  PHY_REG_ADR  ====================================================== */
41577  #define R_ESC_PHY_REG_ADR_PHYREGADDR_Pos           (0UL)          /*!< PHYREGADDR (Bit 0)                                    */
41578  #define R_ESC_PHY_REG_ADR_PHYREGADDR_Msk           (0x1fUL)       /*!< PHYREGADDR (Bitfield-Mask: 0x1f)                      */
41579 /* =======================================================  PHY_DATA  ======================================================== */
41580  #define R_ESC_PHY_DATA_PHYREGDATA_Pos              (0UL)          /*!< PHYREGDATA (Bit 0)                                    */
41581  #define R_ESC_PHY_DATA_PHYREGDATA_Msk              (0xffffUL)     /*!< PHYREGDATA (Bitfield-Mask: 0xffff)                    */
41582 /* ===================================================  MII_ECAT_ACS_STAT  =================================================== */
41583  #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Pos         (0UL)          /*!< ACSMII (Bit 0)                                        */
41584  #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Msk         (0x1UL)        /*!< ACSMII (Bitfield-Mask: 0x01)                          */
41585 /* ===================================================  MII_PDI_ACS_STAT  ==================================================== */
41586  #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Pos          (0UL)          /*!< ACSMII (Bit 0)                                        */
41587  #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Msk          (0x1UL)        /*!< ACSMII (Bitfield-Mask: 0x01)                          */
41588  #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Pos          (1UL)          /*!< FORPDI (Bit 1)                                        */
41589  #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Msk          (0x2UL)        /*!< FORPDI (Bitfield-Mask: 0x01)                          */
41590 /* ===================================================  DC_RCV_TIME_PORT  ==================================================== */
41591  #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Pos        (0UL)          /*!< RCVTIME0 (Bit 0)                                      */
41592  #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Msk        (0xffffffffUL) /*!< RCVTIME0 (Bitfield-Mask: 0xffffffff)                  */
41593 /* =====================================================  DC_SYS_TIME_L  ===================================================== */
41594 /* =====================================================  DC_SYS_TIME_H  ===================================================== */
41595 /* ==================================================  DC_RCV_TIME_UNIT_L  =================================================== */
41596 /* ==================================================  DC_RCV_TIME_UNIT_H  =================================================== */
41597 /* =================================================  DC_SYS_TIME_OFFSET_L  ================================================== */
41598 /* =================================================  DC_SYS_TIME_OFFSET_H  ================================================== */
41599 /* ===================================================  DC_SYS_TIME_DELAY  =================================================== */
41600  #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Pos             (0UL)          /*!< SYSTIMDLY (Bit 0)                                     */
41601  #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Msk             (0xffffffffUL) /*!< SYSTIMDLY (Bitfield-Mask: 0xffffffff)                 */
41602 /* ===================================================  DC_SYS_TIME_DIFF  ==================================================== */
41603  #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Pos                   (0UL)          /*!< DIFF (Bit 0)                                          */
41604  #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Msk                   (0x7fffffffUL) /*!< DIFF (Bitfield-Mask: 0x7fffffff)                      */
41605  #define R_ESC_DC_SYS_TIME_DIFF_LCP_Pos                    (31UL)         /*!< LCP (Bit 31)                                          */
41606  #define R_ESC_DC_SYS_TIME_DIFF_LCP_Msk                    (0x80000000UL) /*!< LCP (Bitfield-Mask: 0x01)                             */
41607 /* =================================================  DC_SPEED_COUNT_START  ================================================== */
41608  #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Pos         (0UL)          /*!< SPDCNTSTRT (Bit 0)                                    */
41609  #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Msk         (0x7fffUL)     /*!< SPDCNTSTRT (Bitfield-Mask: 0x7fff)                    */
41610 /* ==================================================  DC_SPEED_COUNT_DIFF  ================================================== */
41611  #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Pos          (0UL)          /*!< SPDCNTDIFF (Bit 0)                                    */
41612  #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Msk          (0xffffUL)     /*!< SPDCNTDIFF (Bitfield-Mask: 0xffff)                    */
41613 /* ==============================================  DC_SYS_TIME_DIFF_FIL_DEPTH  =============================================== */
41614  #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Pos    (0UL)          /*!< SYSTIMDEP (Bit 0)                                     */
41615  #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Msk    (0xfUL)        /*!< SYSTIMDEP (Bitfield-Mask: 0x0f)                       */
41616 /* ===============================================  DC_SPEED_COUNT_FIL_DEPTH  ================================================ */
41617  #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Pos      (0UL)          /*!< CLKPERDEP (Bit 0)                                     */
41618  #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Msk      (0xfUL)        /*!< CLKPERDEP (Bitfield-Mask: 0x0f)                       */
41619 /* ======================================================  DC_CYC_CONT  ====================================================== */
41620  #define R_ESC_DC_CYC_CONT_SYNCOUT_Pos                     (0UL)          /*!< SYNCOUT (Bit 0)                                       */
41621  #define R_ESC_DC_CYC_CONT_SYNCOUT_Msk                     (0x1UL)        /*!< SYNCOUT (Bitfield-Mask: 0x01)                         */
41622  #define R_ESC_DC_CYC_CONT_LATCH0_Pos                      (4UL)          /*!< LATCH0 (Bit 4)                                        */
41623  #define R_ESC_DC_CYC_CONT_LATCH0_Msk                      (0x10UL)       /*!< LATCH0 (Bitfield-Mask: 0x01)                          */
41624  #define R_ESC_DC_CYC_CONT_LATCH1_Pos                      (5UL)          /*!< LATCH1 (Bit 5)                                        */
41625  #define R_ESC_DC_CYC_CONT_LATCH1_Msk                      (0x20UL)       /*!< LATCH1 (Bitfield-Mask: 0x01)                          */
41626 /* ========================================================  DC_ACT  ========================================================= */
41627  #define R_ESC_DC_ACT_SYNCACT_Pos                          (0UL)          /*!< SYNCACT (Bit 0)                                       */
41628  #define R_ESC_DC_ACT_SYNCACT_Msk                          (0x1UL)        /*!< SYNCACT (Bitfield-Mask: 0x01)                         */
41629  #define R_ESC_DC_ACT_SYNC0_Pos                            (1UL)          /*!< SYNC0 (Bit 1)                                         */
41630  #define R_ESC_DC_ACT_SYNC0_Msk                            (0x2UL)        /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
41631  #define R_ESC_DC_ACT_SYNC1_Pos                            (2UL)          /*!< SYNC1 (Bit 2)                                         */
41632  #define R_ESC_DC_ACT_SYNC1_Msk                            (0x4UL)        /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
41633  #define R_ESC_DC_ACT_AUTOACT_Pos                          (3UL)          /*!< AUTOACT (Bit 3)                                       */
41634  #define R_ESC_DC_ACT_AUTOACT_Msk                          (0x8UL)        /*!< AUTOACT (Bitfield-Mask: 0x01)                         */
41635  #define R_ESC_DC_ACT_EXTSTARTTIME_Pos                     (4UL)          /*!< EXTSTARTTIME (Bit 4)                                  */
41636  #define R_ESC_DC_ACT_EXTSTARTTIME_Msk                     (0x10UL)       /*!< EXTSTARTTIME (Bitfield-Mask: 0x01)                    */
41637  #define R_ESC_DC_ACT_STARTTIME_Pos                        (5UL)          /*!< STARTTIME (Bit 5)                                     */
41638  #define R_ESC_DC_ACT_STARTTIME_Msk                        (0x20UL)       /*!< STARTTIME (Bitfield-Mask: 0x01)                       */
41639  #define R_ESC_DC_ACT_NEARFUTURE_Pos                       (6UL)          /*!< NEARFUTURE (Bit 6)                                    */
41640  #define R_ESC_DC_ACT_NEARFUTURE_Msk                       (0x40UL)       /*!< NEARFUTURE (Bitfield-Mask: 0x01)                      */
41641  #define R_ESC_DC_ACT_DBGPULSE_Pos                         (7UL)          /*!< DBGPULSE (Bit 7)                                      */
41642  #define R_ESC_DC_ACT_DBGPULSE_Msk                         (0x80UL)       /*!< DBGPULSE (Bitfield-Mask: 0x01)                        */
41643 /* =====================================================  DC_PULSE_LEN  ====================================================== */
41644  #define R_ESC_DC_PULSE_LEN_PULSELEN_Pos                   (0UL)          /*!< PULSELEN (Bit 0)                                      */
41645  #define R_ESC_DC_PULSE_LEN_PULSELEN_Msk                   (0xffffUL)     /*!< PULSELEN (Bitfield-Mask: 0xffff)                      */
41646 /* ======================================================  DC_ACT_STAT  ====================================================== */
41647  #define R_ESC_DC_ACT_STAT_SYNC0ACT_Pos                    (0UL)          /*!< SYNC0ACT (Bit 0)                                      */
41648  #define R_ESC_DC_ACT_STAT_SYNC0ACT_Msk                    (0x1UL)        /*!< SYNC0ACT (Bitfield-Mask: 0x01)                        */
41649  #define R_ESC_DC_ACT_STAT_SYNC1ACT_Pos                    (1UL)          /*!< SYNC1ACT (Bit 1)                                      */
41650  #define R_ESC_DC_ACT_STAT_SYNC1ACT_Msk                    (0x2UL)        /*!< SYNC1ACT (Bitfield-Mask: 0x01)                        */
41651  #define R_ESC_DC_ACT_STAT_STARTTIME_Pos                   (2UL)          /*!< STARTTIME (Bit 2)                                     */
41652  #define R_ESC_DC_ACT_STAT_STARTTIME_Msk                   (0x4UL)        /*!< STARTTIME (Bitfield-Mask: 0x01)                       */
41653 /* =====================================================  DC_SYNC0_STAT  ===================================================== */
41654  #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Pos                  (0UL)          /*!< SYNC0STA (Bit 0)                                      */
41655  #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Msk                  (0x1UL)        /*!< SYNC0STA (Bitfield-Mask: 0x01)                        */
41656 /* =====================================================  DC_SYNC1_STAT  ===================================================== */
41657  #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Pos                  (0UL)          /*!< SYNC1STA (Bit 0)                                      */
41658  #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Msk                  (0x1UL)        /*!< SYNC1STA (Bitfield-Mask: 0x01)                        */
41659 /* ==================================================  DC_CYC_START_TIME_L  ================================================== */
41660 /* ==================================================  DC_CYC_START_TIME_H  ================================================== */
41661 /* =================================================  DC_NEXT_SYNC1_PULSE_L  ================================================= */
41662 /* =================================================  DC_NEXT_SYNC1_PULSE_H  ================================================= */
41663 /* ===================================================  DC_SYNC0_CYC_TIME  =================================================== */
41664  #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Pos    (0UL)          /*!< SYNC0CYC (Bit 0)                                      */
41665  #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Msk    (0xffffffffUL) /*!< SYNC0CYC (Bitfield-Mask: 0xffffffff)                  */
41666 /* ===================================================  DC_SYNC1_CYC_TIME  =================================================== */
41667  #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Pos    (0UL)          /*!< SYNC1CYC (Bit 0)                                      */
41668  #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Msk    (0xffffffffUL) /*!< SYNC1CYC (Bitfield-Mask: 0xffffffff)                  */
41669 /* ====================================================  DC_LATCH0_CONT  ===================================================== */
41670  #define R_ESC_DC_LATCH0_CONT_POSEDGE_Pos        (0UL)          /*!< POSEDGE (Bit 0)                                       */
41671  #define R_ESC_DC_LATCH0_CONT_POSEDGE_Msk        (0x1UL)        /*!< POSEDGE (Bitfield-Mask: 0x01)                         */
41672  #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Pos        (1UL)          /*!< NEGEDGE (Bit 1)                                       */
41673  #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Msk        (0x2UL)        /*!< NEGEDGE (Bitfield-Mask: 0x01)                         */
41674 /* ====================================================  DC_LATCH1_CONT  ===================================================== */
41675  #define R_ESC_DC_LATCH1_CONT_POSEDGE_Pos        (0UL)          /*!< POSEDGE (Bit 0)                                       */
41676  #define R_ESC_DC_LATCH1_CONT_POSEDGE_Msk        (0x1UL)        /*!< POSEDGE (Bitfield-Mask: 0x01)                         */
41677  #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Pos        (1UL)          /*!< NEGEDGE (Bit 1)                                       */
41678  #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Msk        (0x2UL)        /*!< NEGEDGE (Bitfield-Mask: 0x01)                         */
41679 /* ====================================================  DC_LATCH0_STAT  ===================================================== */
41680  #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Pos       (0UL)          /*!< EVENTPOS (Bit 0)                                      */
41681  #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Msk       (0x1UL)        /*!< EVENTPOS (Bitfield-Mask: 0x01)                        */
41682  #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Pos       (1UL)          /*!< EVENTNEG (Bit 1)                                      */
41683  #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Msk       (0x2UL)        /*!< EVENTNEG (Bitfield-Mask: 0x01)                        */
41684  #define R_ESC_DC_LATCH0_STAT_PINSTATE_Pos       (2UL)          /*!< PINSTATE (Bit 2)                                      */
41685  #define R_ESC_DC_LATCH0_STAT_PINSTATE_Msk       (0x4UL)        /*!< PINSTATE (Bitfield-Mask: 0x01)                        */
41686 /* ====================================================  DC_LATCH1_STAT  ===================================================== */
41687  #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Pos       (0UL)          /*!< EVENTPOS (Bit 0)                                      */
41688  #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Msk       (0x1UL)        /*!< EVENTPOS (Bitfield-Mask: 0x01)                        */
41689  #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Pos       (1UL)          /*!< EVENTNEG (Bit 1)                                      */
41690  #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Msk       (0x2UL)        /*!< EVENTNEG (Bitfield-Mask: 0x01)                        */
41691  #define R_ESC_DC_LATCH1_STAT_PINSTATE_Pos       (2UL)          /*!< PINSTATE (Bit 2)                                      */
41692  #define R_ESC_DC_LATCH1_STAT_PINSTATE_Msk       (0x4UL)        /*!< PINSTATE (Bitfield-Mask: 0x01)                        */
41693 /* =================================================  DC_LATCH0_TIME_POS_L  ================================================== */
41694 /* =================================================  DC_LATCH0_TIME_POS_H  ================================================== */
41695 /* =================================================  DC_LATCH0_TIME_NEG_L  ================================================== */
41696 /* =================================================  DC_LATCH0_TIME_NEG_H  ================================================== */
41697 /* =================================================  DC_LATCH1_TIME_POS_L  ================================================== */
41698 /* =================================================  DC_LATCH1_TIME_POS_H  ================================================== */
41699 /* =================================================  DC_LATCH1_TIME_NEG_L  ================================================== */
41700 /* =================================================  DC_LATCH1_TIME_NEG_H  ================================================== */
41701 /* ==================================================  DC_ECAT_CNG_EV_TIME  ================================================== */
41702  #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Pos    (0UL)          /*!< ECATCHANGE (Bit 0)                                    */
41703  #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Msk    (0xffffffffUL) /*!< ECATCHANGE (Bitfield-Mask: 0xffffffff)                */
41704 /* =================================================  DC_PDI_START_EV_TIME  ================================================== */
41705  #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Pos     (0UL)          /*!< PDISTART (Bit 0)                                      */
41706  #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Msk     (0xffffffffUL) /*!< PDISTART (Bitfield-Mask: 0xffffffff)                  */
41707 /* ==================================================  DC_PDI_CNG_EV_TIME  =================================================== */
41708  #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Pos      (0UL)          /*!< PDICHANGE (Bit 0)                                     */
41709  #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Msk      (0xffffffffUL) /*!< PDICHANGE (Bitfield-Mask: 0xffffffff)                 */
41710 /* =====================================================  PRODUCT_ID_L  ====================================================== */
41711 /* =====================================================  PRODUCT_ID_H  ====================================================== */
41712 /* ======================================================  VENDOR_ID_L  ====================================================== */
41713  #define R_ESC_VENDOR_ID_L_VENDORID_Pos              (0UL)          /*!< VENDORID (Bit 0)                                      */
41714  #define R_ESC_VENDOR_ID_L_VENDORID_Msk              (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
41715 
41716 /* =========================================================================================================================== */
41717 /* ================                                          R_USBHC                                          ================ */
41718 /* =========================================================================================================================== */
41719 
41720 /* ======================================================  HCREVISION  ======================================================= */
41721  #define R_USBHC_HCREVISION_REV_Pos              (0UL)          /*!< REV (Bit 0)                                           */
41722  #define R_USBHC_HCREVISION_REV_Msk              (0xffUL)       /*!< REV (Bitfield-Mask: 0xff)                             */
41723 /* =======================================================  HCCONTROL  ======================================================= */
41724  #define R_USBHC_HCCONTROL_CBSR_Pos              (0UL)          /*!< CBSR (Bit 0)                                          */
41725  #define R_USBHC_HCCONTROL_CBSR_Msk              (0x3UL)        /*!< CBSR (Bitfield-Mask: 0x03)                            */
41726  #define R_USBHC_HCCONTROL_PLE_Pos               (2UL)          /*!< PLE (Bit 2)                                           */
41727  #define R_USBHC_HCCONTROL_PLE_Msk               (0x4UL)        /*!< PLE (Bitfield-Mask: 0x01)                             */
41728  #define R_USBHC_HCCONTROL_IE_Pos                (3UL)          /*!< IE (Bit 3)                                            */
41729  #define R_USBHC_HCCONTROL_IE_Msk                (0x8UL)        /*!< IE (Bitfield-Mask: 0x01)                              */
41730  #define R_USBHC_HCCONTROL_CLE_Pos               (4UL)          /*!< CLE (Bit 4)                                           */
41731  #define R_USBHC_HCCONTROL_CLE_Msk               (0x10UL)       /*!< CLE (Bitfield-Mask: 0x01)                             */
41732  #define R_USBHC_HCCONTROL_BLE_Pos               (5UL)          /*!< BLE (Bit 5)                                           */
41733  #define R_USBHC_HCCONTROL_BLE_Msk               (0x20UL)       /*!< BLE (Bitfield-Mask: 0x01)                             */
41734  #define R_USBHC_HCCONTROL_HCFS_Pos              (6UL)          /*!< HCFS (Bit 6)                                          */
41735  #define R_USBHC_HCCONTROL_HCFS_Msk              (0xc0UL)       /*!< HCFS (Bitfield-Mask: 0x03)                            */
41736  #define R_USBHC_HCCONTROL_IR_Pos                (8UL)          /*!< IR (Bit 8)                                            */
41737  #define R_USBHC_HCCONTROL_IR_Msk                (0x100UL)      /*!< IR (Bitfield-Mask: 0x01)                              */
41738  #define R_USBHC_HCCONTROL_RWC_Pos               (9UL)          /*!< RWC (Bit 9)                                           */
41739  #define R_USBHC_HCCONTROL_RWC_Msk               (0x200UL)      /*!< RWC (Bitfield-Mask: 0x01)                             */
41740  #define R_USBHC_HCCONTROL_RWE_Pos               (10UL)         /*!< RWE (Bit 10)                                          */
41741  #define R_USBHC_HCCONTROL_RWE_Msk               (0x400UL)      /*!< RWE (Bitfield-Mask: 0x01)                             */
41742 /* ====================================================  HCCOMMANDSTATUS  ==================================================== */
41743  #define R_USBHC_HCCOMMANDSTATUS_HCR_Pos         (0UL)          /*!< HCR (Bit 0)                                           */
41744  #define R_USBHC_HCCOMMANDSTATUS_HCR_Msk         (0x1UL)        /*!< HCR (Bitfield-Mask: 0x01)                             */
41745  #define R_USBHC_HCCOMMANDSTATUS_CLF_Pos         (1UL)          /*!< CLF (Bit 1)                                           */
41746  #define R_USBHC_HCCOMMANDSTATUS_CLF_Msk         (0x2UL)        /*!< CLF (Bitfield-Mask: 0x01)                             */
41747  #define R_USBHC_HCCOMMANDSTATUS_BLF_Pos         (2UL)          /*!< BLF (Bit 2)                                           */
41748  #define R_USBHC_HCCOMMANDSTATUS_BLF_Msk         (0x4UL)        /*!< BLF (Bitfield-Mask: 0x01)                             */
41749  #define R_USBHC_HCCOMMANDSTATUS_OCR_Pos         (3UL)          /*!< OCR (Bit 3)                                           */
41750  #define R_USBHC_HCCOMMANDSTATUS_OCR_Msk         (0x8UL)        /*!< OCR (Bitfield-Mask: 0x01)                             */
41751  #define R_USBHC_HCCOMMANDSTATUS_SOC_Pos         (16UL)         /*!< SOC (Bit 16)                                          */
41752  #define R_USBHC_HCCOMMANDSTATUS_SOC_Msk         (0x30000UL)    /*!< SOC (Bitfield-Mask: 0x03)                             */
41753 /* ===================================================  HCINTERRUPTSTATUS  =================================================== */
41754  #define R_USBHC_HCINTERRUPTSTATUS_SO_Pos        (0UL)          /*!< SO (Bit 0)                                            */
41755  #define R_USBHC_HCINTERRUPTSTATUS_SO_Msk        (0x1UL)        /*!< SO (Bitfield-Mask: 0x01)                              */
41756  #define R_USBHC_HCINTERRUPTSTATUS_WDH_Pos       (1UL)          /*!< WDH (Bit 1)                                           */
41757  #define R_USBHC_HCINTERRUPTSTATUS_WDH_Msk       (0x2UL)        /*!< WDH (Bitfield-Mask: 0x01)                             */
41758  #define R_USBHC_HCINTERRUPTSTATUS_SF_Pos        (2UL)          /*!< SF (Bit 2)                                            */
41759  #define R_USBHC_HCINTERRUPTSTATUS_SF_Msk        (0x4UL)        /*!< SF (Bitfield-Mask: 0x01)                              */
41760  #define R_USBHC_HCINTERRUPTSTATUS_RD_Pos        (3UL)          /*!< RD (Bit 3)                                            */
41761  #define R_USBHC_HCINTERRUPTSTATUS_RD_Msk        (0x8UL)        /*!< RD (Bitfield-Mask: 0x01)                              */
41762  #define R_USBHC_HCINTERRUPTSTATUS_UE_Pos        (4UL)          /*!< UE (Bit 4)                                            */
41763  #define R_USBHC_HCINTERRUPTSTATUS_UE_Msk        (0x10UL)       /*!< UE (Bitfield-Mask: 0x01)                              */
41764  #define R_USBHC_HCINTERRUPTSTATUS_FNO_Pos       (5UL)          /*!< FNO (Bit 5)                                           */
41765  #define R_USBHC_HCINTERRUPTSTATUS_FNO_Msk       (0x20UL)       /*!< FNO (Bitfield-Mask: 0x01)                             */
41766  #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Pos      (6UL)          /*!< RHSC (Bit 6)                                          */
41767  #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Msk      (0x40UL)       /*!< RHSC (Bitfield-Mask: 0x01)                            */
41768  #define R_USBHC_HCINTERRUPTSTATUS_OC_Pos        (30UL)         /*!< OC (Bit 30)                                           */
41769  #define R_USBHC_HCINTERRUPTSTATUS_OC_Msk        (0x40000000UL) /*!< OC (Bitfield-Mask: 0x01)                              */
41770 /* ===================================================  HCINTERRUPTENABLE  =================================================== */
41771  #define R_USBHC_HCINTERRUPTENABLE_SOE_Pos       (0UL)          /*!< SOE (Bit 0)                                           */
41772  #define R_USBHC_HCINTERRUPTENABLE_SOE_Msk       (0x1UL)        /*!< SOE (Bitfield-Mask: 0x01)                             */
41773  #define R_USBHC_HCINTERRUPTENABLE_WDHE_Pos      (1UL)          /*!< WDHE (Bit 1)                                          */
41774  #define R_USBHC_HCINTERRUPTENABLE_WDHE_Msk      (0x2UL)        /*!< WDHE (Bitfield-Mask: 0x01)                            */
41775  #define R_USBHC_HCINTERRUPTENABLE_SFE_Pos       (2UL)          /*!< SFE (Bit 2)                                           */
41776  #define R_USBHC_HCINTERRUPTENABLE_SFE_Msk       (0x4UL)        /*!< SFE (Bitfield-Mask: 0x01)                             */
41777  #define R_USBHC_HCINTERRUPTENABLE_RDE_Pos       (3UL)          /*!< RDE (Bit 3)                                           */
41778  #define R_USBHC_HCINTERRUPTENABLE_RDE_Msk       (0x8UL)        /*!< RDE (Bitfield-Mask: 0x01)                             */
41779  #define R_USBHC_HCINTERRUPTENABLE_UEE_Pos       (4UL)          /*!< UEE (Bit 4)                                           */
41780  #define R_USBHC_HCINTERRUPTENABLE_UEE_Msk       (0x10UL)       /*!< UEE (Bitfield-Mask: 0x01)                             */
41781  #define R_USBHC_HCINTERRUPTENABLE_FNOE_Pos      (5UL)          /*!< FNOE (Bit 5)                                          */
41782  #define R_USBHC_HCINTERRUPTENABLE_FNOE_Msk      (0x20UL)       /*!< FNOE (Bitfield-Mask: 0x01)                            */
41783  #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Pos     (6UL)          /*!< RHSCE (Bit 6)                                         */
41784  #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Msk     (0x40UL)       /*!< RHSCE (Bitfield-Mask: 0x01)                           */
41785  #define R_USBHC_HCINTERRUPTENABLE_OCE_Pos       (30UL)         /*!< OCE (Bit 30)                                          */
41786  #define R_USBHC_HCINTERRUPTENABLE_OCE_Msk       (0x40000000UL) /*!< OCE (Bitfield-Mask: 0x01)                             */
41787  #define R_USBHC_HCINTERRUPTENABLE_MIE_Pos       (31UL)         /*!< MIE (Bit 31)                                          */
41788  #define R_USBHC_HCINTERRUPTENABLE_MIE_Msk       (0x80000000UL) /*!< MIE (Bitfield-Mask: 0x01)                             */
41789 /* ==================================================  HCINTERRUPTDISABLE  =================================================== */
41790  #define R_USBHC_HCINTERRUPTDISABLE_SOD_Pos      (0UL)          /*!< SOD (Bit 0)                                           */
41791  #define R_USBHC_HCINTERRUPTDISABLE_SOD_Msk      (0x1UL)        /*!< SOD (Bitfield-Mask: 0x01)                             */
41792  #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Pos     (1UL)          /*!< WDHD (Bit 1)                                          */
41793  #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Msk     (0x2UL)        /*!< WDHD (Bitfield-Mask: 0x01)                            */
41794  #define R_USBHC_HCINTERRUPTDISABLE_SFD_Pos      (2UL)          /*!< SFD (Bit 2)                                           */
41795  #define R_USBHC_HCINTERRUPTDISABLE_SFD_Msk      (0x4UL)        /*!< SFD (Bitfield-Mask: 0x01)                             */
41796  #define R_USBHC_HCINTERRUPTDISABLE_RDD_Pos      (3UL)          /*!< RDD (Bit 3)                                           */
41797  #define R_USBHC_HCINTERRUPTDISABLE_RDD_Msk      (0x8UL)        /*!< RDD (Bitfield-Mask: 0x01)                             */
41798  #define R_USBHC_HCINTERRUPTDISABLE_UED_Pos      (4UL)          /*!< UED (Bit 4)                                           */
41799  #define R_USBHC_HCINTERRUPTDISABLE_UED_Msk      (0x10UL)       /*!< UED (Bitfield-Mask: 0x01)                             */
41800  #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Pos     (5UL)          /*!< FNOD (Bit 5)                                          */
41801  #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Msk     (0x20UL)       /*!< FNOD (Bitfield-Mask: 0x01)                            */
41802  #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Pos    (6UL)          /*!< RHSCD (Bit 6)                                         */
41803  #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Msk    (0x40UL)       /*!< RHSCD (Bitfield-Mask: 0x01)                           */
41804  #define R_USBHC_HCINTERRUPTDISABLE_OCD_Pos      (30UL)         /*!< OCD (Bit 30)                                          */
41805  #define R_USBHC_HCINTERRUPTDISABLE_OCD_Msk      (0x40000000UL) /*!< OCD (Bitfield-Mask: 0x01)                             */
41806  #define R_USBHC_HCINTERRUPTDISABLE_MID_Pos      (31UL)         /*!< MID (Bit 31)                                          */
41807  #define R_USBHC_HCINTERRUPTDISABLE_MID_Msk      (0x80000000UL) /*!< MID (Bitfield-Mask: 0x01)                             */
41808 /* ========================================================  HCHCCA  ========================================================= */
41809  #define R_USBHC_HCHCCA_RAMBA_Pos                (8UL)          /*!< RAMBA (Bit 8)                                         */
41810  #define R_USBHC_HCHCCA_RAMBA_Msk                (0xffffff00UL) /*!< RAMBA (Bitfield-Mask: 0xffffff)                       */
41811 /* ==================================================  HCPERIODCCURRENTIED  ================================================== */
41812  #define R_USBHC_HCPERIODCCURRENTIED_PCED_Pos    (4UL)          /*!< PCED (Bit 4)                                          */
41813  #define R_USBHC_HCPERIODCCURRENTIED_PCED_Msk    (0xfffffff0UL) /*!< PCED (Bitfield-Mask: 0xfffffff)                       */
41814 /* ====================================================  HCCONTROLHEADED  ==================================================== */
41815  #define R_USBHC_HCCONTROLHEADED_CHED_Pos        (4UL)          /*!< CHED (Bit 4)                                          */
41816  #define R_USBHC_HCCONTROLHEADED_CHED_Msk        (0xfffffff0UL) /*!< CHED (Bitfield-Mask: 0xfffffff)                       */
41817 /* ==================================================  HCCONTROLCURRENTED  =================================================== */
41818  #define R_USBHC_HCCONTROLCURRENTED_CCED_Pos     (4UL)          /*!< CCED (Bit 4)                                          */
41819  #define R_USBHC_HCCONTROLCURRENTED_CCED_Msk     (0xfffffff0UL) /*!< CCED (Bitfield-Mask: 0xfffffff)                       */
41820 /* =====================================================  HCBULKHEADED  ====================================================== */
41821  #define R_USBHC_HCBULKHEADED_BHED_Pos           (4UL)          /*!< BHED (Bit 4)                                          */
41822  #define R_USBHC_HCBULKHEADED_BHED_Msk           (0xfffffff0UL) /*!< BHED (Bitfield-Mask: 0xfffffff)                       */
41823 /* ====================================================  HCBULKCURRENTED  ==================================================== */
41824  #define R_USBHC_HCBULKCURRENTED_BCED_Pos        (4UL)          /*!< BCED (Bit 4)                                          */
41825  #define R_USBHC_HCBULKCURRENTED_BCED_Msk        (0xfffffff0UL) /*!< BCED (Bitfield-Mask: 0xfffffff)                       */
41826 /* ======================================================  HCDONEHEAD  ======================================================= */
41827  #define R_USBHC_HCDONEHEAD_DH_Pos               (4UL)          /*!< DH (Bit 4)                                            */
41828  #define R_USBHC_HCDONEHEAD_DH_Msk               (0xfffffff0UL) /*!< DH (Bitfield-Mask: 0xfffffff)                         */
41829 /* =====================================================  HCFMINTERVAL  ====================================================== */
41830  #define R_USBHC_HCFMINTERVAL_FI_Pos             (0UL)          /*!< FI (Bit 0)                                            */
41831  #define R_USBHC_HCFMINTERVAL_FI_Msk             (0x3fffUL)     /*!< FI (Bitfield-Mask: 0x3fff)                            */
41832  #define R_USBHC_HCFMINTERVAL_FSMPS_Pos          (16UL)         /*!< FSMPS (Bit 16)                                        */
41833  #define R_USBHC_HCFMINTERVAL_FSMPS_Msk          (0x7fff0000UL) /*!< FSMPS (Bitfield-Mask: 0x7fff)                         */
41834  #define R_USBHC_HCFMINTERVAL_FIT_Pos            (31UL)         /*!< FIT (Bit 31)                                          */
41835  #define R_USBHC_HCFMINTERVAL_FIT_Msk            (0x80000000UL) /*!< FIT (Bitfield-Mask: 0x01)                             */
41836 /* =====================================================  HCFNREMAINING  ===================================================== */
41837  #define R_USBHC_HCFNREMAINING_FR_Pos            (0UL)          /*!< FR (Bit 0)                                            */
41838  #define R_USBHC_HCFNREMAINING_FR_Msk            (0x3fffUL)     /*!< FR (Bitfield-Mask: 0x3fff)                            */
41839  #define R_USBHC_HCFNREMAINING_FRT_Pos           (31UL)         /*!< FRT (Bit 31)                                          */
41840  #define R_USBHC_HCFNREMAINING_FRT_Msk           (0x80000000UL) /*!< FRT (Bitfield-Mask: 0x01)                             */
41841 /* ======================================================  HCFMNUMBER  ======================================================= */
41842  #define R_USBHC_HCFMNUMBER_FN_Pos               (0UL)          /*!< FN (Bit 0)                                            */
41843  #define R_USBHC_HCFMNUMBER_FN_Msk               (0xffffUL)     /*!< FN (Bitfield-Mask: 0xffff)                            */
41844 /* =====================================================  HCPERIODSTART  ===================================================== */
41845  #define R_USBHC_HCPERIODSTART_PS_Pos            (0UL)          /*!< PS (Bit 0)                                            */
41846  #define R_USBHC_HCPERIODSTART_PS_Msk            (0x3fffUL)     /*!< PS (Bitfield-Mask: 0x3fff)                            */
41847 /* =====================================================  HCLSTHRESHOLD  ===================================================== */
41848  #define R_USBHC_HCLSTHRESHOLD_LS_Pos            (0UL)          /*!< LS (Bit 0)                                            */
41849  #define R_USBHC_HCLSTHRESHOLD_LS_Msk            (0xfffUL)      /*!< LS (Bitfield-Mask: 0xfff)                             */
41850 /* ====================================================  HCRHDESCRIPTORA  ==================================================== */
41851  #define R_USBHC_HCRHDESCRIPTORA_NDP_Pos         (0UL)          /*!< NDP (Bit 0)                                           */
41852  #define R_USBHC_HCRHDESCRIPTORA_NDP_Msk         (0xffUL)       /*!< NDP (Bitfield-Mask: 0xff)                             */
41853  #define R_USBHC_HCRHDESCRIPTORA_PSM_Pos         (8UL)          /*!< PSM (Bit 8)                                           */
41854  #define R_USBHC_HCRHDESCRIPTORA_PSM_Msk         (0x100UL)      /*!< PSM (Bitfield-Mask: 0x01)                             */
41855  #define R_USBHC_HCRHDESCRIPTORA_NPS_Pos         (9UL)          /*!< NPS (Bit 9)                                           */
41856  #define R_USBHC_HCRHDESCRIPTORA_NPS_Msk         (0x200UL)      /*!< NPS (Bitfield-Mask: 0x01)                             */
41857  #define R_USBHC_HCRHDESCRIPTORA_DT_Pos          (10UL)         /*!< DT (Bit 10)                                           */
41858  #define R_USBHC_HCRHDESCRIPTORA_DT_Msk          (0x400UL)      /*!< DT (Bitfield-Mask: 0x01)                              */
41859  #define R_USBHC_HCRHDESCRIPTORA_OCPM_Pos        (11UL)         /*!< OCPM (Bit 11)                                         */
41860  #define R_USBHC_HCRHDESCRIPTORA_OCPM_Msk        (0x800UL)      /*!< OCPM (Bitfield-Mask: 0x01)                            */
41861  #define R_USBHC_HCRHDESCRIPTORA_NOCP_Pos        (12UL)         /*!< NOCP (Bit 12)                                         */
41862  #define R_USBHC_HCRHDESCRIPTORA_NOCP_Msk        (0x1000UL)     /*!< NOCP (Bitfield-Mask: 0x01)                            */
41863  #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Pos      (24UL)         /*!< POTPGT (Bit 24)                                       */
41864  #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Msk      (0xff000000UL) /*!< POTPGT (Bitfield-Mask: 0xff)                          */
41865 /* ====================================================  HCRHDESCRIPTORB  ==================================================== */
41866  #define R_USBHC_HCRHDESCRIPTORB_DR_Pos          (0UL)          /*!< DR (Bit 0)                                            */
41867  #define R_USBHC_HCRHDESCRIPTORB_DR_Msk          (0xffffUL)     /*!< DR (Bitfield-Mask: 0xffff)                            */
41868  #define R_USBHC_HCRHDESCRIPTORB_PPCM_Pos        (16UL)         /*!< PPCM (Bit 16)                                         */
41869  #define R_USBHC_HCRHDESCRIPTORB_PPCM_Msk        (0xffff0000UL) /*!< PPCM (Bitfield-Mask: 0xffff)                          */
41870 /* ======================================================  HCRHSTATUS  ======================================================= */
41871  #define R_USBHC_HCRHSTATUS_LPS_Pos              (0UL)          /*!< LPS (Bit 0)                                           */
41872  #define R_USBHC_HCRHSTATUS_LPS_Msk              (0x1UL)        /*!< LPS (Bitfield-Mask: 0x01)                             */
41873  #define R_USBHC_HCRHSTATUS_OCI_Pos              (1UL)          /*!< OCI (Bit 1)                                           */
41874  #define R_USBHC_HCRHSTATUS_OCI_Msk              (0x2UL)        /*!< OCI (Bitfield-Mask: 0x01)                             */
41875  #define R_USBHC_HCRHSTATUS_DRWE_Pos             (15UL)         /*!< DRWE (Bit 15)                                         */
41876  #define R_USBHC_HCRHSTATUS_DRWE_Msk             (0x8000UL)     /*!< DRWE (Bitfield-Mask: 0x01)                            */
41877  #define R_USBHC_HCRHSTATUS_LPSC_Pos             (16UL)         /*!< LPSC (Bit 16)                                         */
41878  #define R_USBHC_HCRHSTATUS_LPSC_Msk             (0x10000UL)    /*!< LPSC (Bitfield-Mask: 0x01)                            */
41879  #define R_USBHC_HCRHSTATUS_OCIC_Pos             (17UL)         /*!< OCIC (Bit 17)                                         */
41880  #define R_USBHC_HCRHSTATUS_OCIC_Msk             (0x20000UL)    /*!< OCIC (Bitfield-Mask: 0x01)                            */
41881  #define R_USBHC_HCRHSTATUS_CRWE_Pos             (31UL)         /*!< CRWE (Bit 31)                                         */
41882  #define R_USBHC_HCRHSTATUS_CRWE_Msk             (0x80000000UL) /*!< CRWE (Bitfield-Mask: 0x01)                            */
41883 /* ====================================================  HCRHPORTSTATUS1  ==================================================== */
41884  #define R_USBHC_HCRHPORTSTATUS1_CCS_Pos         (0UL)          /*!< CCS (Bit 0)                                           */
41885  #define R_USBHC_HCRHPORTSTATUS1_CCS_Msk         (0x1UL)        /*!< CCS (Bitfield-Mask: 0x01)                             */
41886  #define R_USBHC_HCRHPORTSTATUS1_PES_Pos         (1UL)          /*!< PES (Bit 1)                                           */
41887  #define R_USBHC_HCRHPORTSTATUS1_PES_Msk         (0x2UL)        /*!< PES (Bitfield-Mask: 0x01)                             */
41888  #define R_USBHC_HCRHPORTSTATUS1_PSS_Pos         (2UL)          /*!< PSS (Bit 2)                                           */
41889  #define R_USBHC_HCRHPORTSTATUS1_PSS_Msk         (0x4UL)        /*!< PSS (Bitfield-Mask: 0x01)                             */
41890  #define R_USBHC_HCRHPORTSTATUS1_POCI_Pos        (3UL)          /*!< POCI (Bit 3)                                          */
41891  #define R_USBHC_HCRHPORTSTATUS1_POCI_Msk        (0x8UL)        /*!< POCI (Bitfield-Mask: 0x01)                            */
41892  #define R_USBHC_HCRHPORTSTATUS1_PRS_Pos         (4UL)          /*!< PRS (Bit 4)                                           */
41893  #define R_USBHC_HCRHPORTSTATUS1_PRS_Msk         (0x10UL)       /*!< PRS (Bitfield-Mask: 0x01)                             */
41894  #define R_USBHC_HCRHPORTSTATUS1_PPS_Pos         (8UL)          /*!< PPS (Bit 8)                                           */
41895  #define R_USBHC_HCRHPORTSTATUS1_PPS_Msk         (0x100UL)      /*!< PPS (Bitfield-Mask: 0x01)                             */
41896  #define R_USBHC_HCRHPORTSTATUS1_LSDA_Pos        (9UL)          /*!< LSDA (Bit 9)                                          */
41897  #define R_USBHC_HCRHPORTSTATUS1_LSDA_Msk        (0x200UL)      /*!< LSDA (Bitfield-Mask: 0x01)                            */
41898  #define R_USBHC_HCRHPORTSTATUS1_CSC_Pos         (16UL)         /*!< CSC (Bit 16)                                          */
41899  #define R_USBHC_HCRHPORTSTATUS1_CSC_Msk         (0x10000UL)    /*!< CSC (Bitfield-Mask: 0x01)                             */
41900  #define R_USBHC_HCRHPORTSTATUS1_PESC_Pos        (17UL)         /*!< PESC (Bit 17)                                         */
41901  #define R_USBHC_HCRHPORTSTATUS1_PESC_Msk        (0x20000UL)    /*!< PESC (Bitfield-Mask: 0x01)                            */
41902  #define R_USBHC_HCRHPORTSTATUS1_PSSC_Pos        (18UL)         /*!< PSSC (Bit 18)                                         */
41903  #define R_USBHC_HCRHPORTSTATUS1_PSSC_Msk        (0x40000UL)    /*!< PSSC (Bitfield-Mask: 0x01)                            */
41904  #define R_USBHC_HCRHPORTSTATUS1_OCIC_Pos        (19UL)         /*!< OCIC (Bit 19)                                         */
41905  #define R_USBHC_HCRHPORTSTATUS1_OCIC_Msk        (0x80000UL)    /*!< OCIC (Bitfield-Mask: 0x01)                            */
41906  #define R_USBHC_HCRHPORTSTATUS1_PRSC_Pos        (20UL)         /*!< PRSC (Bit 20)                                         */
41907  #define R_USBHC_HCRHPORTSTATUS1_PRSC_Msk        (0x100000UL)   /*!< PRSC (Bitfield-Mask: 0x01)                            */
41908 /* =====================================================  CAPL_VERSION  ====================================================== */
41909  #define R_USBHC_CAPL_VERSION_CRL_Pos            (0UL)          /*!< CRL (Bit 0)                                           */
41910  #define R_USBHC_CAPL_VERSION_CRL_Msk            (0xffUL)       /*!< CRL (Bitfield-Mask: 0xff)                             */
41911  #define R_USBHC_CAPL_VERSION_HCIVN_Pos          (16UL)         /*!< HCIVN (Bit 16)                                        */
41912  #define R_USBHC_CAPL_VERSION_HCIVN_Msk          (0xffff0000UL) /*!< HCIVN (Bitfield-Mask: 0xffff)                         */
41913 /* =======================================================  HCSPARAMS  ======================================================= */
41914  #define R_USBHC_HCSPARAMS_N_PORTS_Pos           (0UL)          /*!< N_PORTS (Bit 0)                                       */
41915  #define R_USBHC_HCSPARAMS_N_PORTS_Msk           (0xfUL)        /*!< N_PORTS (Bitfield-Mask: 0x0f)                         */
41916  #define R_USBHC_HCSPARAMS_PPC_Pos               (4UL)          /*!< PPC (Bit 4)                                           */
41917  #define R_USBHC_HCSPARAMS_PPC_Msk               (0x10UL)       /*!< PPC (Bitfield-Mask: 0x01)                             */
41918  #define R_USBHC_HCSPARAMS_PTRR_Pos              (7UL)          /*!< PTRR (Bit 7)                                          */
41919  #define R_USBHC_HCSPARAMS_PTRR_Msk              (0x80UL)       /*!< PTRR (Bitfield-Mask: 0x01)                            */
41920  #define R_USBHC_HCSPARAMS_N_PCC_Pos             (8UL)          /*!< N_PCC (Bit 8)                                         */
41921  #define R_USBHC_HCSPARAMS_N_PCC_Msk             (0xf00UL)      /*!< N_PCC (Bitfield-Mask: 0x0f)                           */
41922  #define R_USBHC_HCSPARAMS_N_CC_Pos              (12UL)         /*!< N_CC (Bit 12)                                         */
41923  #define R_USBHC_HCSPARAMS_N_CC_Msk              (0xf000UL)     /*!< N_CC (Bitfield-Mask: 0x0f)                            */
41924  #define R_USBHC_HCSPARAMS_P_INDICATOR_Pos       (16UL)         /*!< P_INDICATOR (Bit 16)                                  */
41925  #define R_USBHC_HCSPARAMS_P_INDICATOR_Msk       (0x10000UL)    /*!< P_INDICATOR (Bitfield-Mask: 0x01)                     */
41926  #define R_USBHC_HCSPARAMS_DBGPTNUM_Pos          (20UL)         /*!< DBGPTNUM (Bit 20)                                     */
41927  #define R_USBHC_HCSPARAMS_DBGPTNUM_Msk          (0xf00000UL)   /*!< DBGPTNUM (Bitfield-Mask: 0x0f)                        */
41928 /* =======================================================  HCCPARAMS  ======================================================= */
41929  #define R_USBHC_HCCPARAMS_AC64_Pos              (0UL)          /*!< AC64 (Bit 0)                                          */
41930  #define R_USBHC_HCCPARAMS_AC64_Msk              (0x1UL)        /*!< AC64 (Bitfield-Mask: 0x01)                            */
41931  #define R_USBHC_HCCPARAMS_PFLF_Pos              (1UL)          /*!< PFLF (Bit 1)                                          */
41932  #define R_USBHC_HCCPARAMS_PFLF_Msk              (0x2UL)        /*!< PFLF (Bitfield-Mask: 0x01)                            */
41933  #define R_USBHC_HCCPARAMS_ASPC_Pos              (2UL)          /*!< ASPC (Bit 2)                                          */
41934  #define R_USBHC_HCCPARAMS_ASPC_Msk              (0x4UL)        /*!< ASPC (Bitfield-Mask: 0x01)                            */
41935  #define R_USBHC_HCCPARAMS_IST_Pos               (4UL)          /*!< IST (Bit 4)                                           */
41936  #define R_USBHC_HCCPARAMS_IST_Msk               (0xf0UL)       /*!< IST (Bitfield-Mask: 0x0f)                             */
41937  #define R_USBHC_HCCPARAMS_EECP_Pos              (8UL)          /*!< EECP (Bit 8)                                          */
41938  #define R_USBHC_HCCPARAMS_EECP_Msk              (0xff00UL)     /*!< EECP (Bitfield-Mask: 0xff)                            */
41939  #define R_USBHC_HCCPARAMS_HP_Pos                (16UL)         /*!< HP (Bit 16)                                           */
41940  #define R_USBHC_HCCPARAMS_HP_Msk                (0x10000UL)    /*!< HP (Bitfield-Mask: 0x01)                              */
41941  #define R_USBHC_HCCPARAMS_LPMC_Pos              (17UL)         /*!< LPMC (Bit 17)                                         */
41942  #define R_USBHC_HCCPARAMS_LPMC_Msk              (0x20000UL)    /*!< LPMC (Bitfield-Mask: 0x01)                            */
41943  #define R_USBHC_HCCPARAMS_PCEC_Pos              (18UL)         /*!< PCEC (Bit 18)                                         */
41944  #define R_USBHC_HCCPARAMS_PCEC_Msk              (0x40000UL)    /*!< PCEC (Bitfield-Mask: 0x01)                            */
41945  #define R_USBHC_HCCPARAMS_PL32_Pos              (19UL)         /*!< PL32 (Bit 19)                                         */
41946  #define R_USBHC_HCCPARAMS_PL32_Msk              (0x80000UL)    /*!< PL32 (Bitfield-Mask: 0x01)                            */
41947 /* ====================================================  HCSP_PORTROUTE  ===================================================== */
41948 /* ========================================================  USBCMD  ========================================================= */
41949  #define R_USBHC_USBCMD_RS_Pos                   (0UL)          /*!< RS (Bit 0)                                            */
41950  #define R_USBHC_USBCMD_RS_Msk                   (0x1UL)        /*!< RS (Bitfield-Mask: 0x01)                              */
41951  #define R_USBHC_USBCMD_HCRESET_Pos              (1UL)          /*!< HCRESET (Bit 1)                                       */
41952  #define R_USBHC_USBCMD_HCRESET_Msk              (0x2UL)        /*!< HCRESET (Bitfield-Mask: 0x01)                         */
41953  #define R_USBHC_USBCMD_FLS_Pos                  (2UL)          /*!< FLS (Bit 2)                                           */
41954  #define R_USBHC_USBCMD_FLS_Msk                  (0xcUL)        /*!< FLS (Bitfield-Mask: 0x03)                             */
41955  #define R_USBHC_USBCMD_PSE_Pos                  (4UL)          /*!< PSE (Bit 4)                                           */
41956  #define R_USBHC_USBCMD_PSE_Msk                  (0x10UL)       /*!< PSE (Bitfield-Mask: 0x01)                             */
41957  #define R_USBHC_USBCMD_ASYNSE_Pos               (5UL)          /*!< ASYNSE (Bit 5)                                        */
41958  #define R_USBHC_USBCMD_ASYNSE_Msk               (0x20UL)       /*!< ASYNSE (Bitfield-Mask: 0x01)                          */
41959  #define R_USBHC_USBCMD_IAAD_Pos                 (6UL)          /*!< IAAD (Bit 6)                                          */
41960  #define R_USBHC_USBCMD_IAAD_Msk                 (0x40UL)       /*!< IAAD (Bitfield-Mask: 0x01)                            */
41961  #define R_USBHC_USBCMD_LHCR_Pos                 (7UL)          /*!< LHCR (Bit 7)                                          */
41962  #define R_USBHC_USBCMD_LHCR_Msk                 (0x80UL)       /*!< LHCR (Bitfield-Mask: 0x01)                            */
41963  #define R_USBHC_USBCMD_ASPMC_Pos                (8UL)          /*!< ASPMC (Bit 8)                                         */
41964  #define R_USBHC_USBCMD_ASPMC_Msk                (0x300UL)      /*!< ASPMC (Bitfield-Mask: 0x03)                           */
41965  #define R_USBHC_USBCMD_ASPME_Pos                (11UL)         /*!< ASPME (Bit 11)                                        */
41966  #define R_USBHC_USBCMD_ASPME_Msk                (0x800UL)      /*!< ASPME (Bitfield-Mask: 0x01)                           */
41967  #define R_USBHC_USBCMD_PPCEE_Pos                (15UL)         /*!< PPCEE (Bit 15)                                        */
41968  #define R_USBHC_USBCMD_PPCEE_Msk                (0x8000UL)     /*!< PPCEE (Bitfield-Mask: 0x01)                           */
41969  #define R_USBHC_USBCMD_ITC_Pos                  (16UL)         /*!< ITC (Bit 16)                                          */
41970  #define R_USBHC_USBCMD_ITC_Msk                  (0xff0000UL)   /*!< ITC (Bitfield-Mask: 0xff)                             */
41971  #define R_USBHC_USBCMD_HIRD_Pos                 (24UL)         /*!< HIRD (Bit 24)                                         */
41972  #define R_USBHC_USBCMD_HIRD_Msk                 (0xf000000UL)  /*!< HIRD (Bitfield-Mask: 0x0f)                            */
41973 /* ========================================================  USBSTS  ========================================================= */
41974  #define R_USBHC_USBSTS_USBINT_Pos               (0UL)          /*!< USBINT (Bit 0)                                        */
41975  #define R_USBHC_USBSTS_USBINT_Msk               (0x1UL)        /*!< USBINT (Bitfield-Mask: 0x01)                          */
41976  #define R_USBHC_USBSTS_USBERRINT_Pos            (1UL)          /*!< USBERRINT (Bit 1)                                     */
41977  #define R_USBHC_USBSTS_USBERRINT_Msk            (0x2UL)        /*!< USBERRINT (Bitfield-Mask: 0x01)                       */
41978  #define R_USBHC_USBSTS_PTCGDET_Pos              (2UL)          /*!< PTCGDET (Bit 2)                                       */
41979  #define R_USBHC_USBSTS_PTCGDET_Msk              (0x4UL)        /*!< PTCGDET (Bitfield-Mask: 0x01)                         */
41980  #define R_USBHC_USBSTS_FLROV_Pos                (3UL)          /*!< FLROV (Bit 3)                                         */
41981  #define R_USBHC_USBSTS_FLROV_Msk                (0x8UL)        /*!< FLROV (Bitfield-Mask: 0x01)                           */
41982  #define R_USBHC_USBSTS_HSYSE_Pos                (4UL)          /*!< HSYSE (Bit 4)                                         */
41983  #define R_USBHC_USBSTS_HSYSE_Msk                (0x10UL)       /*!< HSYSE (Bitfield-Mask: 0x01)                           */
41984  #define R_USBHC_USBSTS_IAAIS_Pos                (5UL)          /*!< IAAIS (Bit 5)                                         */
41985  #define R_USBHC_USBSTS_IAAIS_Msk                (0x20UL)       /*!< IAAIS (Bitfield-Mask: 0x01)                           */
41986  #define R_USBHC_USBSTS_EHCSTS_Pos               (12UL)         /*!< EHCSTS (Bit 12)                                       */
41987  #define R_USBHC_USBSTS_EHCSTS_Msk               (0x1000UL)     /*!< EHCSTS (Bitfield-Mask: 0x01)                          */
41988  #define R_USBHC_USBSTS_RECLAM_Pos               (13UL)         /*!< RECLAM (Bit 13)                                       */
41989  #define R_USBHC_USBSTS_RECLAM_Msk               (0x2000UL)     /*!< RECLAM (Bitfield-Mask: 0x01)                          */
41990  #define R_USBHC_USBSTS_PSCHSTS_Pos              (14UL)         /*!< PSCHSTS (Bit 14)                                      */
41991  #define R_USBHC_USBSTS_PSCHSTS_Msk              (0x4000UL)     /*!< PSCHSTS (Bitfield-Mask: 0x01)                         */
41992  #define R_USBHC_USBSTS_ASS_Pos                  (15UL)         /*!< ASS (Bit 15)                                          */
41993  #define R_USBHC_USBSTS_ASS_Msk                  (0x8000UL)     /*!< ASS (Bitfield-Mask: 0x01)                             */
41994  #define R_USBHC_USBSTS_PTCGDETC_Pos             (16UL)         /*!< PTCGDETC (Bit 16)                                     */
41995  #define R_USBHC_USBSTS_PTCGDETC_Msk             (0xffff0000UL) /*!< PTCGDETC (Bitfield-Mask: 0xffff)                      */
41996 /* ========================================================  USBINTR  ======================================================== */
41997  #define R_USBHC_USBINTR_USBIE_Pos               (0UL)          /*!< USBIE (Bit 0)                                         */
41998  #define R_USBHC_USBINTR_USBIE_Msk               (0x1UL)        /*!< USBIE (Bitfield-Mask: 0x01)                           */
41999  #define R_USBHC_USBINTR_USBEIE_Pos              (1UL)          /*!< USBEIE (Bit 1)                                        */
42000  #define R_USBHC_USBINTR_USBEIE_Msk              (0x2UL)        /*!< USBEIE (Bitfield-Mask: 0x01)                          */
42001  #define R_USBHC_USBINTR_PTCGIE_Pos              (2UL)          /*!< PTCGIE (Bit 2)                                        */
42002  #define R_USBHC_USBINTR_PTCGIE_Msk              (0x4UL)        /*!< PTCGIE (Bitfield-Mask: 0x01)                          */
42003  #define R_USBHC_USBINTR_FMLSTROE_Pos            (3UL)          /*!< FMLSTROE (Bit 3)                                      */
42004  #define R_USBHC_USBINTR_FMLSTROE_Msk            (0x8UL)        /*!< FMLSTROE (Bitfield-Mask: 0x01)                        */
42005  #define R_USBHC_USBINTR_HSEE_Pos                (4UL)          /*!< HSEE (Bit 4)                                          */
42006  #define R_USBHC_USBINTR_HSEE_Msk                (0x10UL)       /*!< HSEE (Bitfield-Mask: 0x01)                            */
42007  #define R_USBHC_USBINTR_INTAADVE_Pos            (5UL)          /*!< INTAADVE (Bit 5)                                      */
42008  #define R_USBHC_USBINTR_INTAADVE_Msk            (0x20UL)       /*!< INTAADVE (Bitfield-Mask: 0x01)                        */
42009  #define R_USBHC_USBINTR_PCGIE_Pos               (16UL)         /*!< PCGIE (Bit 16)                                        */
42010  #define R_USBHC_USBINTR_PCGIE_Msk               (0xffff0000UL) /*!< PCGIE (Bitfield-Mask: 0xffff)                         */
42011 /* ========================================================  FRINDEX  ======================================================== */
42012  #define R_USBHC_FRINDEX_FRAMEINDEX_Pos          (0UL)          /*!< FRAMEINDEX (Bit 0)                                    */
42013  #define R_USBHC_FRINDEX_FRAMEINDEX_Msk          (0x3fffUL)     /*!< FRAMEINDEX (Bitfield-Mask: 0x3fff)                    */
42014 /* =====================================================  CTRLDSSEGMENT  ===================================================== */
42015 /* ===================================================  PERIODICLISTBASE  ==================================================== */
42016  #define R_USBHC_PERIODICLISTBASE_PFLSA_Pos      (12UL)         /*!< PFLSA (Bit 12)                                        */
42017  #define R_USBHC_PERIODICLISTBASE_PFLSA_Msk      (0xfffff000UL) /*!< PFLSA (Bitfield-Mask: 0xfffff)                        */
42018 /* =====================================================  ASYNCLISTADDR  ===================================================== */
42019  #define R_USBHC_ASYNCLISTADDR_LPL_Pos           (5UL)          /*!< LPL (Bit 5)                                           */
42020  #define R_USBHC_ASYNCLISTADDR_LPL_Msk           (0xffffffe0UL) /*!< LPL (Bitfield-Mask: 0x7ffffff)                        */
42021 /* ======================================================  CONFIGFLAG  ======================================================= */
42022  #define R_USBHC_CONFIGFLAG_CF_Pos               (0UL)          /*!< CF (Bit 0)                                            */
42023  #define R_USBHC_CONFIGFLAG_CF_Msk               (0x1UL)        /*!< CF (Bitfield-Mask: 0x01)                              */
42024 /* ========================================================  PORTSC1  ======================================================== */
42025  #define R_USBHC_PORTSC1_CCSTS_Pos               (0UL)          /*!< CCSTS (Bit 0)                                         */
42026  #define R_USBHC_PORTSC1_CCSTS_Msk               (0x1UL)        /*!< CCSTS (Bitfield-Mask: 0x01)                           */
42027  #define R_USBHC_PORTSC1_CSC_Pos                 (1UL)          /*!< CSC (Bit 1)                                           */
42028  #define R_USBHC_PORTSC1_CSC_Msk                 (0x2UL)        /*!< CSC (Bitfield-Mask: 0x01)                             */
42029  #define R_USBHC_PORTSC1_PTE_Pos                 (2UL)          /*!< PTE (Bit 2)                                           */
42030  #define R_USBHC_PORTSC1_PTE_Msk                 (0x4UL)        /*!< PTE (Bitfield-Mask: 0x01)                             */
42031  #define R_USBHC_PORTSC1_PTESC_Pos               (3UL)          /*!< PTESC (Bit 3)                                         */
42032  #define R_USBHC_PORTSC1_PTESC_Msk               (0x8UL)        /*!< PTESC (Bitfield-Mask: 0x01)                           */
42033  #define R_USBHC_PORTSC1_OVCACT_Pos              (4UL)          /*!< OVCACT (Bit 4)                                        */
42034  #define R_USBHC_PORTSC1_OVCACT_Msk              (0x10UL)       /*!< OVCACT (Bitfield-Mask: 0x01)                          */
42035  #define R_USBHC_PORTSC1_OVCC_Pos                (5UL)          /*!< OVCC (Bit 5)                                          */
42036  #define R_USBHC_PORTSC1_OVCC_Msk                (0x20UL)       /*!< OVCC (Bitfield-Mask: 0x01)                            */
42037  #define R_USBHC_PORTSC1_FRCPTRSM_Pos            (6UL)          /*!< FRCPTRSM (Bit 6)                                      */
42038  #define R_USBHC_PORTSC1_FRCPTRSM_Msk            (0x40UL)       /*!< FRCPTRSM (Bitfield-Mask: 0x01)                        */
42039  #define R_USBHC_PORTSC1_SUSPEND_Pos             (7UL)          /*!< SUSPEND (Bit 7)                                       */
42040  #define R_USBHC_PORTSC1_SUSPEND_Msk             (0x80UL)       /*!< SUSPEND (Bitfield-Mask: 0x01)                         */
42041  #define R_USBHC_PORTSC1_PTRST_Pos               (8UL)          /*!< PTRST (Bit 8)                                         */
42042  #define R_USBHC_PORTSC1_PTRST_Msk               (0x100UL)      /*!< PTRST (Bitfield-Mask: 0x01)                           */
42043  #define R_USBHC_PORTSC1_LPMCTL_Pos              (9UL)          /*!< LPMCTL (Bit 9)                                        */
42044  #define R_USBHC_PORTSC1_LPMCTL_Msk              (0x200UL)      /*!< LPMCTL (Bitfield-Mask: 0x01)                          */
42045  #define R_USBHC_PORTSC1_LINESTS_Pos             (10UL)         /*!< LINESTS (Bit 10)                                      */
42046  #define R_USBHC_PORTSC1_LINESTS_Msk             (0xc00UL)      /*!< LINESTS (Bitfield-Mask: 0x03)                         */
42047  #define R_USBHC_PORTSC1_PP_Pos                  (12UL)         /*!< PP (Bit 12)                                           */
42048  #define R_USBHC_PORTSC1_PP_Msk                  (0x1000UL)     /*!< PP (Bitfield-Mask: 0x01)                              */
42049  #define R_USBHC_PORTSC1_PTOWNR_Pos              (13UL)         /*!< PTOWNR (Bit 13)                                       */
42050  #define R_USBHC_PORTSC1_PTOWNR_Msk              (0x2000UL)     /*!< PTOWNR (Bitfield-Mask: 0x01)                          */
42051  #define R_USBHC_PORTSC1_PTINDCTL_Pos            (14UL)         /*!< PTINDCTL (Bit 14)                                     */
42052  #define R_USBHC_PORTSC1_PTINDCTL_Msk            (0xc000UL)     /*!< PTINDCTL (Bitfield-Mask: 0x03)                        */
42053  #define R_USBHC_PORTSC1_PTTST_Pos               (16UL)         /*!< PTTST (Bit 16)                                        */
42054  #define R_USBHC_PORTSC1_PTTST_Msk               (0xf0000UL)    /*!< PTTST (Bitfield-Mask: 0x0f)                           */
42055  #define R_USBHC_PORTSC1_WKCNNT_E_Pos            (20UL)         /*!< WKCNNT_E (Bit 20)                                     */
42056  #define R_USBHC_PORTSC1_WKCNNT_E_Msk            (0x100000UL)   /*!< WKCNNT_E (Bitfield-Mask: 0x01)                        */
42057  #define R_USBHC_PORTSC1_WKDSCNNT_E_Pos          (21UL)         /*!< WKDSCNNT_E (Bit 21)                                   */
42058  #define R_USBHC_PORTSC1_WKDSCNNT_E_Msk          (0x200000UL)   /*!< WKDSCNNT_E (Bitfield-Mask: 0x01)                      */
42059  #define R_USBHC_PORTSC1_WKOC_E_Pos              (22UL)         /*!< WKOC_E (Bit 22)                                       */
42060  #define R_USBHC_PORTSC1_WKOC_E_Msk              (0x400000UL)   /*!< WKOC_E (Bitfield-Mask: 0x01)                          */
42061  #define R_USBHC_PORTSC1_SUSPSTS_Pos             (23UL)         /*!< SUSPSTS (Bit 23)                                      */
42062  #define R_USBHC_PORTSC1_SUSPSTS_Msk             (0x1800000UL)  /*!< SUSPSTS (Bitfield-Mask: 0x03)                         */
42063  #define R_USBHC_PORTSC1_DVADDR_Pos              (25UL)         /*!< DVADDR (Bit 25)                                       */
42064  #define R_USBHC_PORTSC1_DVADDR_Msk              (0xfe000000UL) /*!< DVADDR (Bitfield-Mask: 0x7f)                          */
42065 /* =======================================================  INTENABLE  ======================================================= */
42066  #define R_USBHC_INTENABLE_AHB_INTEN_Pos         (0UL)          /*!< AHB_INTEN (Bit 0)                                     */
42067  #define R_USBHC_INTENABLE_AHB_INTEN_Msk         (0x1UL)        /*!< AHB_INTEN (Bitfield-Mask: 0x01)                       */
42068  #define R_USBHC_INTENABLE_USBH_INTAEN_Pos       (1UL)          /*!< USBH_INTAEN (Bit 1)                                   */
42069  #define R_USBHC_INTENABLE_USBH_INTAEN_Msk       (0x2UL)        /*!< USBH_INTAEN (Bitfield-Mask: 0x01)                     */
42070  #define R_USBHC_INTENABLE_USBH_INTBEN_Pos       (2UL)          /*!< USBH_INTBEN (Bit 2)                                   */
42071  #define R_USBHC_INTENABLE_USBH_INTBEN_Msk       (0x4UL)        /*!< USBH_INTBEN (Bitfield-Mask: 0x01)                     */
42072  #define R_USBHC_INTENABLE_UCOM_INTEN_Pos        (3UL)          /*!< UCOM_INTEN (Bit 3)                                    */
42073  #define R_USBHC_INTENABLE_UCOM_INTEN_Msk        (0x8UL)        /*!< UCOM_INTEN (Bitfield-Mask: 0x01)                      */
42074  #define R_USBHC_INTENABLE_WAKEON_INTEN_Pos      (4UL)          /*!< WAKEON_INTEN (Bit 4)                                  */
42075  #define R_USBHC_INTENABLE_WAKEON_INTEN_Msk      (0x10UL)       /*!< WAKEON_INTEN (Bitfield-Mask: 0x01)                    */
42076 /* =======================================================  INTSTATUS  ======================================================= */
42077  #define R_USBHC_INTSTATUS_AHB_INT_Pos           (0UL)          /*!< AHB_INT (Bit 0)                                       */
42078  #define R_USBHC_INTSTATUS_AHB_INT_Msk           (0x1UL)        /*!< AHB_INT (Bitfield-Mask: 0x01)                         */
42079  #define R_USBHC_INTSTATUS_USBH_INTA_Pos         (1UL)          /*!< USBH_INTA (Bit 1)                                     */
42080  #define R_USBHC_INTSTATUS_USBH_INTA_Msk         (0x2UL)        /*!< USBH_INTA (Bitfield-Mask: 0x01)                       */
42081  #define R_USBHC_INTSTATUS_USBH_INTB_Pos         (2UL)          /*!< USBH_INTB (Bit 2)                                     */
42082  #define R_USBHC_INTSTATUS_USBH_INTB_Msk         (0x4UL)        /*!< USBH_INTB (Bitfield-Mask: 0x01)                       */
42083  #define R_USBHC_INTSTATUS_UCOM_INT_Pos          (3UL)          /*!< UCOM_INT (Bit 3)                                      */
42084  #define R_USBHC_INTSTATUS_UCOM_INT_Msk          (0x8UL)        /*!< UCOM_INT (Bitfield-Mask: 0x01)                        */
42085  #define R_USBHC_INTSTATUS_WAKEON_INT_Pos        (4UL)          /*!< WAKEON_INT (Bit 4)                                    */
42086  #define R_USBHC_INTSTATUS_WAKEON_INT_Msk        (0x10UL)       /*!< WAKEON_INT (Bitfield-Mask: 0x01)                      */
42087 /* =======================================================  AHBBUSCTR  ======================================================= */
42088  #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Pos     (0UL)          /*!< MAX_BURST_LEN (Bit 0)                                 */
42089  #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Msk     (0x3UL)        /*!< MAX_BURST_LEN (Bitfield-Mask: 0x03)                   */
42090  #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Pos     (4UL)          /*!< ALIGN_ADDRESS (Bit 4)                                 */
42091  #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Msk     (0x30UL)       /*!< ALIGN_ADDRESS (Bitfield-Mask: 0x03)                   */
42092  #define R_USBHC_AHBBUSCTR_PROT_MODE_Pos         (8UL)          /*!< PROT_MODE (Bit 8)                                     */
42093  #define R_USBHC_AHBBUSCTR_PROT_MODE_Msk         (0x100UL)      /*!< PROT_MODE (Bitfield-Mask: 0x01)                       */
42094  #define R_USBHC_AHBBUSCTR_PROT_TYPE_Pos         (12UL)         /*!< PROT_TYPE (Bit 12)                                    */
42095  #define R_USBHC_AHBBUSCTR_PROT_TYPE_Msk         (0xf000UL)     /*!< PROT_TYPE (Bitfield-Mask: 0x0f)                       */
42096 /* ========================================================  USBCTR  ========================================================= */
42097  #define R_USBHC_USBCTR_USBH_RST_Pos             (0UL)          /*!< USBH_RST (Bit 0)                                      */
42098  #define R_USBHC_USBCTR_USBH_RST_Msk             (0x1UL)        /*!< USBH_RST (Bitfield-Mask: 0x01)                        */
42099  #define R_USBHC_USBCTR_PLL_RST_Pos              (1UL)          /*!< PLL_RST (Bit 1)                                       */
42100  #define R_USBHC_USBCTR_PLL_RST_Msk              (0x2UL)        /*!< PLL_RST (Bitfield-Mask: 0x01)                         */
42101  #define R_USBHC_USBCTR_DIRPD_Pos                (2UL)          /*!< DIRPD (Bit 2)                                         */
42102  #define R_USBHC_USBCTR_DIRPD_Msk                (0x4UL)        /*!< DIRPD (Bitfield-Mask: 0x01)                           */
42103 /* =========================================================  REVID  ========================================================= */
42104  #define R_USBHC_REVID_MINV_Pos                  (0UL)          /*!< MINV (Bit 0)                                          */
42105  #define R_USBHC_REVID_MINV_Msk                  (0xffUL)       /*!< MINV (Bitfield-Mask: 0xff)                            */
42106  #define R_USBHC_REVID_MAJV_Pos                  (8UL)          /*!< MAJV (Bit 8)                                          */
42107  #define R_USBHC_REVID_MAJV_Msk                  (0xff00UL)     /*!< MAJV (Bitfield-Mask: 0xff)                            */
42108  #define R_USBHC_REVID_COREID_Pos                (24UL)         /*!< COREID (Bit 24)                                       */
42109  #define R_USBHC_REVID_COREID_Msk                (0xff000000UL) /*!< COREID (Bitfield-Mask: 0xff)                          */
42110 /* ======================================================  OCSLPTIMSET  ====================================================== */
42111  #define R_USBHC_OCSLPTIMSET_TIMER_OC_Pos        (0UL)          /*!< TIMER_OC (Bit 0)                                      */
42112  #define R_USBHC_OCSLPTIMSET_TIMER_OC_Msk        (0xfffffUL)    /*!< TIMER_OC (Bitfield-Mask: 0xfffff)                     */
42113  #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Pos     (20UL)         /*!< TIMER_SLEEP (Bit 20)                                  */
42114  #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Msk     (0x1ff00000UL) /*!< TIMER_SLEEP (Bitfield-Mask: 0x1ff)                    */
42115 /* =======================================================  COMMCTRL  ======================================================== */
42116  #define R_USBHC_COMMCTRL_PERI_Pos               (31UL)         /*!< PERI (Bit 31)                                         */
42117  #define R_USBHC_COMMCTRL_PERI_Msk               (0x80000000UL) /*!< PERI (Bitfield-Mask: 0x01)                            */
42118 /* =======================================================  OBINTSTA  ======================================================== */
42119  #define R_USBHC_OBINTSTA_IDCHG_STA_Pos          (0UL)          /*!< IDCHG_STA (Bit 0)                                     */
42120  #define R_USBHC_OBINTSTA_IDCHG_STA_Msk          (0x1UL)        /*!< IDCHG_STA (Bitfield-Mask: 0x01)                       */
42121  #define R_USBHC_OBINTSTA_OCINT_STA_Pos          (1UL)          /*!< OCINT_STA (Bit 1)                                     */
42122  #define R_USBHC_OBINTSTA_OCINT_STA_Msk          (0x2UL)        /*!< OCINT_STA (Bitfield-Mask: 0x01)                       */
42123  #define R_USBHC_OBINTSTA_VBSTACHG_STA_Pos       (2UL)          /*!< VBSTACHG_STA (Bit 2)                                  */
42124  #define R_USBHC_OBINTSTA_VBSTACHG_STA_Msk       (0x4UL)        /*!< VBSTACHG_STA (Bitfield-Mask: 0x01)                    */
42125  #define R_USBHC_OBINTSTA_VBSTAINT_STA_Pos       (3UL)          /*!< VBSTAINT_STA (Bit 3)                                  */
42126  #define R_USBHC_OBINTSTA_VBSTAINT_STA_Msk       (0x8UL)        /*!< VBSTAINT_STA (Bitfield-Mask: 0x01)                    */
42127  #define R_USBHC_OBINTSTA_DMMONCHG_STA_Pos       (16UL)         /*!< DMMONCHG_STA (Bit 16)                                 */
42128  #define R_USBHC_OBINTSTA_DMMONCHG_STA_Msk       (0x10000UL)    /*!< DMMONCHG_STA (Bitfield-Mask: 0x01)                    */
42129  #define R_USBHC_OBINTSTA_DPMONCHG_STA_Pos       (17UL)         /*!< DPMONCHG_STA (Bit 17)                                 */
42130  #define R_USBHC_OBINTSTA_DPMONCHG_STA_Msk       (0x20000UL)    /*!< DPMONCHG_STA (Bitfield-Mask: 0x01)                    */
42131 /* ========================================================  OBINTEN  ======================================================== */
42132  #define R_USBHC_OBINTEN_IDCHG_EN_Pos            (0UL)          /*!< IDCHG_EN (Bit 0)                                      */
42133  #define R_USBHC_OBINTEN_IDCHG_EN_Msk            (0x1UL)        /*!< IDCHG_EN (Bitfield-Mask: 0x01)                        */
42134  #define R_USBHC_OBINTEN_OCINT_EN_Pos            (1UL)          /*!< OCINT_EN (Bit 1)                                      */
42135  #define R_USBHC_OBINTEN_OCINT_EN_Msk            (0x2UL)        /*!< OCINT_EN (Bitfield-Mask: 0x01)                        */
42136  #define R_USBHC_OBINTEN_VBSTACHG_EN_Pos         (2UL)          /*!< VBSTACHG_EN (Bit 2)                                   */
42137  #define R_USBHC_OBINTEN_VBSTACHG_EN_Msk         (0x4UL)        /*!< VBSTACHG_EN (Bitfield-Mask: 0x01)                     */
42138  #define R_USBHC_OBINTEN_VBSTAINT_EN_Pos         (3UL)          /*!< VBSTAINT_EN (Bit 3)                                   */
42139  #define R_USBHC_OBINTEN_VBSTAINT_EN_Msk         (0x8UL)        /*!< VBSTAINT_EN (Bitfield-Mask: 0x01)                     */
42140  #define R_USBHC_OBINTEN_DMMONCHG_EN_Pos         (16UL)         /*!< DMMONCHG_EN (Bit 16)                                  */
42141  #define R_USBHC_OBINTEN_DMMONCHG_EN_Msk         (0x10000UL)    /*!< DMMONCHG_EN (Bitfield-Mask: 0x01)                     */
42142  #define R_USBHC_OBINTEN_DPMONCHG_EN_Pos         (17UL)         /*!< DPMONCHG_EN (Bit 17)                                  */
42143  #define R_USBHC_OBINTEN_DPMONCHG_EN_Msk         (0x20000UL)    /*!< DPMONCHG_EN (Bitfield-Mask: 0x01)                     */
42144 /* ========================================================  VBCTRL  ========================================================= */
42145  #define R_USBHC_VBCTRL_VBOUT_Pos                (0UL)          /*!< VBOUT (Bit 0)                                         */
42146  #define R_USBHC_VBCTRL_VBOUT_Msk                (0x1UL)        /*!< VBOUT (Bitfield-Mask: 0x01)                           */
42147  #define R_USBHC_VBCTRL_VBUSENSEL_Pos            (1UL)          /*!< VBUSENSEL (Bit 1)                                     */
42148  #define R_USBHC_VBCTRL_VBUSENSEL_Msk            (0x2UL)        /*!< VBUSENSEL (Bitfield-Mask: 0x01)                       */
42149  #define R_USBHC_VBCTRL_VGPUO_Pos                (4UL)          /*!< VGPUO (Bit 4)                                         */
42150  #define R_USBHC_VBCTRL_VGPUO_Msk                (0x10UL)       /*!< VGPUO (Bitfield-Mask: 0x01)                           */
42151  #define R_USBHC_VBCTRL_OCCLRIEN_Pos             (16UL)         /*!< OCCLRIEN (Bit 16)                                     */
42152  #define R_USBHC_VBCTRL_OCCLRIEN_Msk             (0x10000UL)    /*!< OCCLRIEN (Bitfield-Mask: 0x01)                        */
42153  #define R_USBHC_VBCTRL_OCISEL_Pos               (17UL)         /*!< OCISEL (Bit 17)                                       */
42154  #define R_USBHC_VBCTRL_OCISEL_Msk               (0x20000UL)    /*!< OCISEL (Bitfield-Mask: 0x01)                          */
42155  #define R_USBHC_VBCTRL_VBLVL_Pos                (20UL)         /*!< VBLVL (Bit 20)                                        */
42156  #define R_USBHC_VBCTRL_VBLVL_Msk                (0xf00000UL)   /*!< VBLVL (Bitfield-Mask: 0x0f)                           */
42157  #define R_USBHC_VBCTRL_VBSTA_Pos                (28UL)         /*!< VBSTA (Bit 28)                                        */
42158  #define R_USBHC_VBCTRL_VBSTA_Msk                (0xf0000000UL) /*!< VBSTA (Bitfield-Mask: 0x0f)                           */
42159 /* =======================================================  LINECTRL1  ======================================================= */
42160  #define R_USBHC_LINECTRL1_IDMON_Pos             (0UL)          /*!< IDMON (Bit 0)                                         */
42161  #define R_USBHC_LINECTRL1_IDMON_Msk             (0x1UL)        /*!< IDMON (Bitfield-Mask: 0x01)                           */
42162  #define R_USBHC_LINECTRL1_DMMON_Pos             (2UL)          /*!< DMMON (Bit 2)                                         */
42163  #define R_USBHC_LINECTRL1_DMMON_Msk             (0x4UL)        /*!< DMMON (Bitfield-Mask: 0x01)                           */
42164  #define R_USBHC_LINECTRL1_DPMON_Pos             (3UL)          /*!< DPMON (Bit 3)                                         */
42165  #define R_USBHC_LINECTRL1_DPMON_Msk             (0x8UL)        /*!< DPMON (Bitfield-Mask: 0x01)                           */
42166  #define R_USBHC_LINECTRL1_DM_RPD_Pos            (16UL)         /*!< DM_RPD (Bit 16)                                       */
42167  #define R_USBHC_LINECTRL1_DM_RPD_Msk            (0x10000UL)    /*!< DM_RPD (Bitfield-Mask: 0x01)                          */
42168  #define R_USBHC_LINECTRL1_DMRPD_EN_Pos          (17UL)         /*!< DMRPD_EN (Bit 17)                                     */
42169  #define R_USBHC_LINECTRL1_DMRPD_EN_Msk          (0x20000UL)    /*!< DMRPD_EN (Bitfield-Mask: 0x01)                        */
42170  #define R_USBHC_LINECTRL1_DP_RPD_Pos            (18UL)         /*!< DP_RPD (Bit 18)                                       */
42171  #define R_USBHC_LINECTRL1_DP_RPD_Msk            (0x40000UL)    /*!< DP_RPD (Bitfield-Mask: 0x01)                          */
42172  #define R_USBHC_LINECTRL1_DPRPD_EN_Pos          (19UL)         /*!< DPRPD_EN (Bit 19)                                     */
42173  #define R_USBHC_LINECTRL1_DPRPD_EN_Msk          (0x80000UL)    /*!< DPRPD_EN (Bitfield-Mask: 0x01)                        */
42174 
42175 /* =========================================================================================================================== */
42176 /* ================                                          R_USBF                                           ================ */
42177 /* =========================================================================================================================== */
42178 
42179 /* ========================================================  SYSCFG0  ======================================================== */
42180  #define R_USBF_SYSCFG0_USBE_Pos            (0UL)          /*!< USBE (Bit 0)                                          */
42181  #define R_USBF_SYSCFG0_USBE_Msk            (0x1UL)        /*!< USBE (Bitfield-Mask: 0x01)                            */
42182  #define R_USBF_SYSCFG0_DPRPU_Pos           (4UL)          /*!< DPRPU (Bit 4)                                         */
42183  #define R_USBF_SYSCFG0_DPRPU_Msk           (0x10UL)       /*!< DPRPU (Bitfield-Mask: 0x01)                           */
42184  #define R_USBF_SYSCFG0_DRPD_Pos            (5UL)          /*!< DRPD (Bit 5)                                          */
42185  #define R_USBF_SYSCFG0_DRPD_Msk            (0x20UL)       /*!< DRPD (Bitfield-Mask: 0x01)                            */
42186  #define R_USBF_SYSCFG0_HSE_Pos             (7UL)          /*!< HSE (Bit 7)                                           */
42187  #define R_USBF_SYSCFG0_HSE_Msk             (0x80UL)       /*!< HSE (Bitfield-Mask: 0x01)                             */
42188  #define R_USBF_SYSCFG0_CNEN_Pos            (8UL)          /*!< CNEN (Bit 8)                                          */
42189  #define R_USBF_SYSCFG0_CNEN_Msk            (0x100UL)      /*!< CNEN (Bitfield-Mask: 0x01)                            */
42190 /* ========================================================  SYSCFG1  ======================================================== */
42191  #define R_USBF_SYSCFG1_BWAIT_Pos           (0UL)          /*!< BWAIT (Bit 0)                                         */
42192  #define R_USBF_SYSCFG1_BWAIT_Msk           (0x3fUL)       /*!< BWAIT (Bitfield-Mask: 0x3f)                           */
42193  #define R_USBF_SYSCFG1_AWAIT_Pos           (8UL)          /*!< AWAIT (Bit 8)                                         */
42194  #define R_USBF_SYSCFG1_AWAIT_Msk           (0x3f00UL)     /*!< AWAIT (Bitfield-Mask: 0x3f)                           */
42195 /* ========================================================  SYSSTS0  ======================================================== */
42196  #define R_USBF_SYSSTS0_LNST_Pos            (0UL)          /*!< LNST (Bit 0)                                          */
42197  #define R_USBF_SYSSTS0_LNST_Msk            (0x3UL)        /*!< LNST (Bitfield-Mask: 0x03)                            */
42198 /* =======================================================  DVSTCTR0  ======================================================== */
42199  #define R_USBF_DVSTCTR0_RHST_Pos           (0UL)          /*!< RHST (Bit 0)                                          */
42200  #define R_USBF_DVSTCTR0_RHST_Msk           (0x7UL)        /*!< RHST (Bitfield-Mask: 0x07)                            */
42201  #define R_USBF_DVSTCTR0_WKUP_Pos           (8UL)          /*!< WKUP (Bit 8)                                          */
42202  #define R_USBF_DVSTCTR0_WKUP_Msk           (0x100UL)      /*!< WKUP (Bitfield-Mask: 0x01)                            */
42203 /* =======================================================  TESTMODE  ======================================================== */
42204  #define R_USBF_TESTMODE_UTST_Pos           (0UL)          /*!< UTST (Bit 0)                                          */
42205  #define R_USBF_TESTMODE_UTST_Msk           (0xfUL)        /*!< UTST (Bitfield-Mask: 0x0f)                            */
42206 /* =========================================================  CFIFO  ========================================================= */
42207  #define R_USBF_CFIFO_FIFOPORT_Pos          (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42208  #define R_USBF_CFIFO_FIFOPORT_Msk          (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
42209 /* ========================================================  CFIFOL  ========================================================= */
42210 /* ========================================================  CFIFOLL  ======================================================== */
42211 /* ========================================================  CFIFOH  ========================================================= */
42212  #define R_USBF_CFIFOH_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42213  #define R_USBF_CFIFOH_FIFOPORT_Msk         (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
42214 /* ========================================================  CFIFOHH  ======================================================== */
42215  #define R_USBF_CFIFOHH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42216  #define R_USBF_CFIFOHH_FIFOPORT_Msk        (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
42217 /* ========================================================  D0FIFO  ========================================================= */
42218  #define R_USBF_D0FIFO_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42219  #define R_USBF_D0FIFO_FIFOPORT_Msk         (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
42220 /* ========================================================  D0FIFOL  ======================================================== */
42221 /* =======================================================  D0FIFOLL  ======================================================== */
42222 /* ========================================================  D0FIFOH  ======================================================== */
42223  #define R_USBF_D0FIFOH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42224  #define R_USBF_D0FIFOH_FIFOPORT_Msk        (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
42225 /* =======================================================  D0FIFOHH  ======================================================== */
42226  #define R_USBF_D0FIFOHH_FIFOPORT_Pos       (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42227  #define R_USBF_D0FIFOHH_FIFOPORT_Msk       (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
42228 /* ========================================================  D1FIFO  ========================================================= */
42229  #define R_USBF_D1FIFO_FIFOPORT_Pos         (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42230  #define R_USBF_D1FIFO_FIFOPORT_Msk         (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff)                  */
42231 /* ========================================================  D1FIFOL  ======================================================== */
42232 /* =======================================================  D1FIFOLL  ======================================================== */
42233 /* ========================================================  D1FIFOH  ======================================================== */
42234  #define R_USBF_D1FIFOH_FIFOPORT_Pos        (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42235  #define R_USBF_D1FIFOH_FIFOPORT_Msk        (0xffffUL)     /*!< FIFOPORT (Bitfield-Mask: 0xffff)                      */
42236 /* =======================================================  D1FIFOHH  ======================================================== */
42237  #define R_USBF_D1FIFOHH_FIFOPORT_Pos       (0UL)          /*!< FIFOPORT (Bit 0)                                      */
42238  #define R_USBF_D1FIFOHH_FIFOPORT_Msk       (0xffUL)       /*!< FIFOPORT (Bitfield-Mask: 0xff)                        */
42239 /* =======================================================  CFIFOSEL  ======================================================== */
42240  #define R_USBF_CFIFOSEL_CURPIPE_Pos        (0UL)          /*!< CURPIPE (Bit 0)                                       */
42241  #define R_USBF_CFIFOSEL_CURPIPE_Msk        (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
42242  #define R_USBF_CFIFOSEL_ISEL_Pos           (5UL)          /*!< ISEL (Bit 5)                                          */
42243  #define R_USBF_CFIFOSEL_ISEL_Msk           (0x20UL)       /*!< ISEL (Bitfield-Mask: 0x01)                            */
42244  #define R_USBF_CFIFOSEL_BIGEND_Pos         (8UL)          /*!< BIGEND (Bit 8)                                        */
42245  #define R_USBF_CFIFOSEL_BIGEND_Msk         (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
42246  #define R_USBF_CFIFOSEL_MBW_Pos            (10UL)         /*!< MBW (Bit 10)                                          */
42247  #define R_USBF_CFIFOSEL_MBW_Msk            (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
42248  #define R_USBF_CFIFOSEL_REW_Pos            (14UL)         /*!< REW (Bit 14)                                          */
42249  #define R_USBF_CFIFOSEL_REW_Msk            (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
42250  #define R_USBF_CFIFOSEL_RCNT_Pos           (15UL)         /*!< RCNT (Bit 15)                                         */
42251  #define R_USBF_CFIFOSEL_RCNT_Msk           (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
42252 /* =======================================================  CFIFOCTR  ======================================================== */
42253  #define R_USBF_CFIFOCTR_DTLN_Pos           (0UL)          /*!< DTLN (Bit 0)                                          */
42254  #define R_USBF_CFIFOCTR_DTLN_Msk           (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
42255  #define R_USBF_CFIFOCTR_FRDY_Pos           (13UL)         /*!< FRDY (Bit 13)                                         */
42256  #define R_USBF_CFIFOCTR_FRDY_Msk           (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
42257  #define R_USBF_CFIFOCTR_BCLR_Pos           (14UL)         /*!< BCLR (Bit 14)                                         */
42258  #define R_USBF_CFIFOCTR_BCLR_Msk           (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
42259  #define R_USBF_CFIFOCTR_BVAL_Pos           (15UL)         /*!< BVAL (Bit 15)                                         */
42260  #define R_USBF_CFIFOCTR_BVAL_Msk           (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
42261 /* =======================================================  D0FIFOSEL  ======================================================= */
42262  #define R_USBF_D0FIFOSEL_CURPIPE_Pos       (0UL)          /*!< CURPIPE (Bit 0)                                       */
42263  #define R_USBF_D0FIFOSEL_CURPIPE_Msk       (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
42264  #define R_USBF_D0FIFOSEL_BIGEND_Pos        (8UL)          /*!< BIGEND (Bit 8)                                        */
42265  #define R_USBF_D0FIFOSEL_BIGEND_Msk        (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
42266  #define R_USBF_D0FIFOSEL_MBW_Pos           (10UL)         /*!< MBW (Bit 10)                                          */
42267  #define R_USBF_D0FIFOSEL_MBW_Msk           (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
42268  #define R_USBF_D0FIFOSEL_DREQE_Pos         (12UL)         /*!< DREQE (Bit 12)                                        */
42269  #define R_USBF_D0FIFOSEL_DREQE_Msk         (0x1000UL)     /*!< DREQE (Bitfield-Mask: 0x01)                           */
42270  #define R_USBF_D0FIFOSEL_DCLRM_Pos         (13UL)         /*!< DCLRM (Bit 13)                                        */
42271  #define R_USBF_D0FIFOSEL_DCLRM_Msk         (0x2000UL)     /*!< DCLRM (Bitfield-Mask: 0x01)                           */
42272  #define R_USBF_D0FIFOSEL_REW_Pos           (14UL)         /*!< REW (Bit 14)                                          */
42273  #define R_USBF_D0FIFOSEL_REW_Msk           (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
42274  #define R_USBF_D0FIFOSEL_RCNT_Pos          (15UL)         /*!< RCNT (Bit 15)                                         */
42275  #define R_USBF_D0FIFOSEL_RCNT_Msk          (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
42276 /* =======================================================  D1FIFOSEL  ======================================================= */
42277  #define R_USBF_D1FIFOSEL_CURPIPE_Pos       (0UL)          /*!< CURPIPE (Bit 0)                                       */
42278  #define R_USBF_D1FIFOSEL_CURPIPE_Msk       (0xfUL)        /*!< CURPIPE (Bitfield-Mask: 0x0f)                         */
42279  #define R_USBF_D1FIFOSEL_BIGEND_Pos        (8UL)          /*!< BIGEND (Bit 8)                                        */
42280  #define R_USBF_D1FIFOSEL_BIGEND_Msk        (0x100UL)      /*!< BIGEND (Bitfield-Mask: 0x01)                          */
42281  #define R_USBF_D1FIFOSEL_MBW_Pos           (10UL)         /*!< MBW (Bit 10)                                          */
42282  #define R_USBF_D1FIFOSEL_MBW_Msk           (0xc00UL)      /*!< MBW (Bitfield-Mask: 0x03)                             */
42283  #define R_USBF_D1FIFOSEL_DREQE_Pos         (12UL)         /*!< DREQE (Bit 12)                                        */
42284  #define R_USBF_D1FIFOSEL_DREQE_Msk         (0x1000UL)     /*!< DREQE (Bitfield-Mask: 0x01)                           */
42285  #define R_USBF_D1FIFOSEL_DCLRM_Pos         (13UL)         /*!< DCLRM (Bit 13)                                        */
42286  #define R_USBF_D1FIFOSEL_DCLRM_Msk         (0x2000UL)     /*!< DCLRM (Bitfield-Mask: 0x01)                           */
42287  #define R_USBF_D1FIFOSEL_REW_Pos           (14UL)         /*!< REW (Bit 14)                                          */
42288  #define R_USBF_D1FIFOSEL_REW_Msk           (0x4000UL)     /*!< REW (Bitfield-Mask: 0x01)                             */
42289  #define R_USBF_D1FIFOSEL_RCNT_Pos          (15UL)         /*!< RCNT (Bit 15)                                         */
42290  #define R_USBF_D1FIFOSEL_RCNT_Msk          (0x8000UL)     /*!< RCNT (Bitfield-Mask: 0x01)                            */
42291 /* =======================================================  D0FIFOCTR  ======================================================= */
42292  #define R_USBF_D0FIFOCTR_DTLN_Pos          (0UL)          /*!< DTLN (Bit 0)                                          */
42293  #define R_USBF_D0FIFOCTR_DTLN_Msk          (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
42294  #define R_USBF_D0FIFOCTR_FRDY_Pos          (13UL)         /*!< FRDY (Bit 13)                                         */
42295  #define R_USBF_D0FIFOCTR_FRDY_Msk          (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
42296  #define R_USBF_D0FIFOCTR_BCLR_Pos          (14UL)         /*!< BCLR (Bit 14)                                         */
42297  #define R_USBF_D0FIFOCTR_BCLR_Msk          (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
42298  #define R_USBF_D0FIFOCTR_BVAL_Pos          (15UL)         /*!< BVAL (Bit 15)                                         */
42299  #define R_USBF_D0FIFOCTR_BVAL_Msk          (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
42300 /* =======================================================  D1FIFOCTR  ======================================================= */
42301  #define R_USBF_D1FIFOCTR_DTLN_Pos          (0UL)          /*!< DTLN (Bit 0)                                          */
42302  #define R_USBF_D1FIFOCTR_DTLN_Msk          (0xfffUL)      /*!< DTLN (Bitfield-Mask: 0xfff)                           */
42303  #define R_USBF_D1FIFOCTR_FRDY_Pos          (13UL)         /*!< FRDY (Bit 13)                                         */
42304  #define R_USBF_D1FIFOCTR_FRDY_Msk          (0x2000UL)     /*!< FRDY (Bitfield-Mask: 0x01)                            */
42305  #define R_USBF_D1FIFOCTR_BCLR_Pos          (14UL)         /*!< BCLR (Bit 14)                                         */
42306  #define R_USBF_D1FIFOCTR_BCLR_Msk          (0x4000UL)     /*!< BCLR (Bitfield-Mask: 0x01)                            */
42307  #define R_USBF_D1FIFOCTR_BVAL_Pos          (15UL)         /*!< BVAL (Bit 15)                                         */
42308  #define R_USBF_D1FIFOCTR_BVAL_Msk          (0x8000UL)     /*!< BVAL (Bitfield-Mask: 0x01)                            */
42309 /* ========================================================  INTENB0  ======================================================== */
42310  #define R_USBF_INTENB0_BRDYE_Pos           (8UL)          /*!< BRDYE (Bit 8)                                         */
42311  #define R_USBF_INTENB0_BRDYE_Msk           (0x100UL)      /*!< BRDYE (Bitfield-Mask: 0x01)                           */
42312  #define R_USBF_INTENB0_NRDYE_Pos           (9UL)          /*!< NRDYE (Bit 9)                                         */
42313  #define R_USBF_INTENB0_NRDYE_Msk           (0x200UL)      /*!< NRDYE (Bitfield-Mask: 0x01)                           */
42314  #define R_USBF_INTENB0_BEMPE_Pos           (10UL)         /*!< BEMPE (Bit 10)                                        */
42315  #define R_USBF_INTENB0_BEMPE_Msk           (0x400UL)      /*!< BEMPE (Bitfield-Mask: 0x01)                           */
42316  #define R_USBF_INTENB0_CTRE_Pos            (11UL)         /*!< CTRE (Bit 11)                                         */
42317  #define R_USBF_INTENB0_CTRE_Msk            (0x800UL)      /*!< CTRE (Bitfield-Mask: 0x01)                            */
42318  #define R_USBF_INTENB0_DVSE_Pos            (12UL)         /*!< DVSE (Bit 12)                                         */
42319  #define R_USBF_INTENB0_DVSE_Msk            (0x1000UL)     /*!< DVSE (Bitfield-Mask: 0x01)                            */
42320  #define R_USBF_INTENB0_SOFE_Pos            (13UL)         /*!< SOFE (Bit 13)                                         */
42321  #define R_USBF_INTENB0_SOFE_Msk            (0x2000UL)     /*!< SOFE (Bitfield-Mask: 0x01)                            */
42322  #define R_USBF_INTENB0_RSME_Pos            (14UL)         /*!< RSME (Bit 14)                                         */
42323  #define R_USBF_INTENB0_RSME_Msk            (0x4000UL)     /*!< RSME (Bitfield-Mask: 0x01)                            */
42324  #define R_USBF_INTENB0_VBSE_Pos            (15UL)         /*!< VBSE (Bit 15)                                         */
42325  #define R_USBF_INTENB0_VBSE_Msk            (0x8000UL)     /*!< VBSE (Bitfield-Mask: 0x01)                            */
42326 /* ========================================================  INTENB1  ======================================================== */
42327  #define R_USBF_INTENB1_PDDETINTE_Pos       (0UL)          /*!< PDDETINTE (Bit 0)                                     */
42328  #define R_USBF_INTENB1_PDDETINTE_Msk       (0x1UL)        /*!< PDDETINTE (Bitfield-Mask: 0x01)                       */
42329 /* ========================================================  BRDYENB  ======================================================== */
42330  #define R_USBF_BRDYENB_PIPEBRDYE_Pos       (0UL)          /*!< PIPEBRDYE (Bit 0)                                     */
42331  #define R_USBF_BRDYENB_PIPEBRDYE_Msk       (0x3ffUL)      /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff)                      */
42332 /* ========================================================  NRDYENB  ======================================================== */
42333  #define R_USBF_NRDYENB_PIPENRDYE_Pos       (0UL)          /*!< PIPENRDYE (Bit 0)                                     */
42334  #define R_USBF_NRDYENB_PIPENRDYE_Msk       (0x3ffUL)      /*!< PIPENRDYE (Bitfield-Mask: 0x3ff)                      */
42335 /* ========================================================  BEMPENB  ======================================================== */
42336  #define R_USBF_BEMPENB_PIPEBEMPE_Pos       (0UL)          /*!< PIPEBEMPE (Bit 0)                                     */
42337  #define R_USBF_BEMPENB_PIPEBEMPE_Msk       (0x3ffUL)      /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff)                      */
42338 /* ========================================================  SOFCFG  ========================================================= */
42339  #define R_USBF_SOFCFG_EDGESTS_Pos          (4UL)          /*!< EDGESTS (Bit 4)                                       */
42340  #define R_USBF_SOFCFG_EDGESTS_Msk          (0x10UL)       /*!< EDGESTS (Bitfield-Mask: 0x01)                         */
42341  #define R_USBF_SOFCFG_INTL_Pos             (5UL)          /*!< INTL (Bit 5)                                          */
42342  #define R_USBF_SOFCFG_INTL_Msk             (0x20UL)       /*!< INTL (Bitfield-Mask: 0x01)                            */
42343  #define R_USBF_SOFCFG_BRDYM_Pos            (6UL)          /*!< BRDYM (Bit 6)                                         */
42344  #define R_USBF_SOFCFG_BRDYM_Msk            (0x40UL)       /*!< BRDYM (Bitfield-Mask: 0x01)                           */
42345 /* ========================================================  INTSTS0  ======================================================== */
42346  #define R_USBF_INTSTS0_CTSQ_Pos            (0UL)          /*!< CTSQ (Bit 0)                                          */
42347  #define R_USBF_INTSTS0_CTSQ_Msk            (0x7UL)        /*!< CTSQ (Bitfield-Mask: 0x07)                            */
42348  #define R_USBF_INTSTS0_VALID_Pos           (3UL)          /*!< VALID (Bit 3)                                         */
42349  #define R_USBF_INTSTS0_VALID_Msk           (0x8UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
42350  #define R_USBF_INTSTS0_DVSQ_Pos            (4UL)          /*!< DVSQ (Bit 4)                                          */
42351  #define R_USBF_INTSTS0_DVSQ_Msk            (0x70UL)       /*!< DVSQ (Bitfield-Mask: 0x07)                            */
42352  #define R_USBF_INTSTS0_VBSTS_Pos           (7UL)          /*!< VBSTS (Bit 7)                                         */
42353  #define R_USBF_INTSTS0_VBSTS_Msk           (0x80UL)       /*!< VBSTS (Bitfield-Mask: 0x01)                           */
42354  #define R_USBF_INTSTS0_BRDY_Pos            (8UL)          /*!< BRDY (Bit 8)                                          */
42355  #define R_USBF_INTSTS0_BRDY_Msk            (0x100UL)      /*!< BRDY (Bitfield-Mask: 0x01)                            */
42356  #define R_USBF_INTSTS0_NRDY_Pos            (9UL)          /*!< NRDY (Bit 9)                                          */
42357  #define R_USBF_INTSTS0_NRDY_Msk            (0x200UL)      /*!< NRDY (Bitfield-Mask: 0x01)                            */
42358  #define R_USBF_INTSTS0_BEMP_Pos            (10UL)         /*!< BEMP (Bit 10)                                         */
42359  #define R_USBF_INTSTS0_BEMP_Msk            (0x400UL)      /*!< BEMP (Bitfield-Mask: 0x01)                            */
42360  #define R_USBF_INTSTS0_CTRT_Pos            (11UL)         /*!< CTRT (Bit 11)                                         */
42361  #define R_USBF_INTSTS0_CTRT_Msk            (0x800UL)      /*!< CTRT (Bitfield-Mask: 0x01)                            */
42362  #define R_USBF_INTSTS0_DVST_Pos            (12UL)         /*!< DVST (Bit 12)                                         */
42363  #define R_USBF_INTSTS0_DVST_Msk            (0x1000UL)     /*!< DVST (Bitfield-Mask: 0x01)                            */
42364  #define R_USBF_INTSTS0_SOFR_Pos            (13UL)         /*!< SOFR (Bit 13)                                         */
42365  #define R_USBF_INTSTS0_SOFR_Msk            (0x2000UL)     /*!< SOFR (Bitfield-Mask: 0x01)                            */
42366  #define R_USBF_INTSTS0_RESM_Pos            (14UL)         /*!< RESM (Bit 14)                                         */
42367  #define R_USBF_INTSTS0_RESM_Msk            (0x4000UL)     /*!< RESM (Bitfield-Mask: 0x01)                            */
42368  #define R_USBF_INTSTS0_VBINT_Pos           (15UL)         /*!< VBINT (Bit 15)                                        */
42369  #define R_USBF_INTSTS0_VBINT_Msk           (0x8000UL)     /*!< VBINT (Bitfield-Mask: 0x01)                           */
42370 /* ========================================================  INTSTS1  ======================================================== */
42371  #define R_USBF_INTSTS1_PDDETINT_Pos        (0UL)          /*!< PDDETINT (Bit 0)                                      */
42372  #define R_USBF_INTSTS1_PDDETINT_Msk        (0x1UL)        /*!< PDDETINT (Bitfield-Mask: 0x01)                        */
42373 /* ========================================================  BRDYSTS  ======================================================== */
42374  #define R_USBF_BRDYSTS_PIPEBRDY_Pos        (0UL)          /*!< PIPEBRDY (Bit 0)                                      */
42375  #define R_USBF_BRDYSTS_PIPEBRDY_Msk        (0x3ffUL)      /*!< PIPEBRDY (Bitfield-Mask: 0x3ff)                       */
42376 /* ========================================================  NRDYSTS  ======================================================== */
42377  #define R_USBF_NRDYSTS_PIPENRDY_Pos        (0UL)          /*!< PIPENRDY (Bit 0)                                      */
42378  #define R_USBF_NRDYSTS_PIPENRDY_Msk        (0x3ffUL)      /*!< PIPENRDY (Bitfield-Mask: 0x3ff)                       */
42379 /* ========================================================  BEMPSTS  ======================================================== */
42380  #define R_USBF_BEMPSTS_PIPEBEMP_Pos        (0UL)          /*!< PIPEBEMP (Bit 0)                                      */
42381  #define R_USBF_BEMPSTS_PIPEBEMP_Msk        (0x3ffUL)      /*!< PIPEBEMP (Bitfield-Mask: 0x3ff)                       */
42382 /* ========================================================  FRMNUM  ========================================================= */
42383  #define R_USBF_FRMNUM_FRNM_Pos             (0UL)          /*!< FRNM (Bit 0)                                          */
42384  #define R_USBF_FRMNUM_FRNM_Msk             (0x7ffUL)      /*!< FRNM (Bitfield-Mask: 0x7ff)                           */
42385  #define R_USBF_FRMNUM_CRCE_Pos             (14UL)         /*!< CRCE (Bit 14)                                         */
42386  #define R_USBF_FRMNUM_CRCE_Msk             (0x4000UL)     /*!< CRCE (Bitfield-Mask: 0x01)                            */
42387  #define R_USBF_FRMNUM_OVRN_Pos             (15UL)         /*!< OVRN (Bit 15)                                         */
42388  #define R_USBF_FRMNUM_OVRN_Msk             (0x8000UL)     /*!< OVRN (Bitfield-Mask: 0x01)                            */
42389 /* ========================================================  UFRMNUM  ======================================================== */
42390  #define R_USBF_UFRMNUM_UFRNM_Pos           (0UL)          /*!< UFRNM (Bit 0)                                         */
42391  #define R_USBF_UFRMNUM_UFRNM_Msk           (0x7UL)        /*!< UFRNM (Bitfield-Mask: 0x07)                           */
42392 /* ========================================================  USBADDR  ======================================================== */
42393  #define R_USBF_USBADDR_USBADDR_Pos         (0UL)          /*!< USBADDR (Bit 0)                                       */
42394  #define R_USBF_USBADDR_USBADDR_Msk         (0x7fUL)       /*!< USBADDR (Bitfield-Mask: 0x7f)                         */
42395 /* ========================================================  USBREQ  ========================================================= */
42396  #define R_USBF_USBREQ_BMREQUESTTYPE_Pos    (0UL)          /*!< BMREQUESTTYPE (Bit 0)                                 */
42397  #define R_USBF_USBREQ_BMREQUESTTYPE_Msk    (0xffUL)       /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff)                   */
42398  #define R_USBF_USBREQ_BREQUEST_Pos         (8UL)          /*!< BREQUEST (Bit 8)                                      */
42399  #define R_USBF_USBREQ_BREQUEST_Msk         (0xff00UL)     /*!< BREQUEST (Bitfield-Mask: 0xff)                        */
42400 /* ========================================================  USBVAL  ========================================================= */
42401  #define R_USBF_USBVAL_WVALUE_Pos           (0UL)          /*!< WVALUE (Bit 0)                                        */
42402  #define R_USBF_USBVAL_WVALUE_Msk           (0xffffUL)     /*!< WVALUE (Bitfield-Mask: 0xffff)                        */
42403 /* ========================================================  USBINDX  ======================================================== */
42404  #define R_USBF_USBINDX_WINDEX_Pos          (0UL)          /*!< WINDEX (Bit 0)                                        */
42405  #define R_USBF_USBINDX_WINDEX_Msk          (0xffffUL)     /*!< WINDEX (Bitfield-Mask: 0xffff)                        */
42406 /* ========================================================  USBLENG  ======================================================== */
42407  #define R_USBF_USBLENG_WLENGTH_Pos         (0UL)          /*!< WLENGTH (Bit 0)                                       */
42408  #define R_USBF_USBLENG_WLENGTH_Msk         (0xffffUL)     /*!< WLENGTH (Bitfield-Mask: 0xffff)                       */
42409 /* ========================================================  DCPCFG  ========================================================= */
42410  #define R_USBF_DCPCFG_SHTNAK_Pos           (7UL)          /*!< SHTNAK (Bit 7)                                        */
42411  #define R_USBF_DCPCFG_SHTNAK_Msk           (0x80UL)       /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
42412  #define R_USBF_DCPCFG_CNTMD_Pos            (8UL)          /*!< CNTMD (Bit 8)                                         */
42413  #define R_USBF_DCPCFG_CNTMD_Msk            (0x100UL)      /*!< CNTMD (Bitfield-Mask: 0x01)                           */
42414 /* ========================================================  DCPMAXP  ======================================================== */
42415  #define R_USBF_DCPMAXP_MXPS_Pos            (0UL)          /*!< MXPS (Bit 0)                                          */
42416  #define R_USBF_DCPMAXP_MXPS_Msk            (0x7fUL)       /*!< MXPS (Bitfield-Mask: 0x7f)                            */
42417 /* ========================================================  DCPCTR  ========================================================= */
42418  #define R_USBF_DCPCTR_PID_Pos              (0UL)          /*!< PID (Bit 0)                                           */
42419  #define R_USBF_DCPCTR_PID_Msk              (0x3UL)        /*!< PID (Bitfield-Mask: 0x03)                             */
42420  #define R_USBF_DCPCTR_CCPL_Pos             (2UL)          /*!< CCPL (Bit 2)                                          */
42421  #define R_USBF_DCPCTR_CCPL_Msk             (0x4UL)        /*!< CCPL (Bitfield-Mask: 0x01)                            */
42422  #define R_USBF_DCPCTR_PBUSY_Pos            (5UL)          /*!< PBUSY (Bit 5)                                         */
42423  #define R_USBF_DCPCTR_PBUSY_Msk            (0x20UL)       /*!< PBUSY (Bitfield-Mask: 0x01)                           */
42424  #define R_USBF_DCPCTR_SQMON_Pos            (6UL)          /*!< SQMON (Bit 6)                                         */
42425  #define R_USBF_DCPCTR_SQMON_Msk            (0x40UL)       /*!< SQMON (Bitfield-Mask: 0x01)                           */
42426  #define R_USBF_DCPCTR_SQSET_Pos            (7UL)          /*!< SQSET (Bit 7)                                         */
42427  #define R_USBF_DCPCTR_SQSET_Msk            (0x80UL)       /*!< SQSET (Bitfield-Mask: 0x01)                           */
42428  #define R_USBF_DCPCTR_SQCLR_Pos            (8UL)          /*!< SQCLR (Bit 8)                                         */
42429  #define R_USBF_DCPCTR_SQCLR_Msk            (0x100UL)      /*!< SQCLR (Bitfield-Mask: 0x01)                           */
42430  #define R_USBF_DCPCTR_BSTS_Pos             (15UL)         /*!< BSTS (Bit 15)                                         */
42431  #define R_USBF_DCPCTR_BSTS_Msk             (0x8000UL)     /*!< BSTS (Bitfield-Mask: 0x01)                            */
42432 /* ========================================================  PIPESEL  ======================================================== */
42433  #define R_USBF_PIPESEL_PIPESEL_Pos         (0UL)          /*!< PIPESEL (Bit 0)                                       */
42434  #define R_USBF_PIPESEL_PIPESEL_Msk         (0xfUL)        /*!< PIPESEL (Bitfield-Mask: 0x0f)                         */
42435 /* ========================================================  PIPECFG  ======================================================== */
42436  #define R_USBF_PIPECFG_EPNUM_Pos           (0UL)          /*!< EPNUM (Bit 0)                                         */
42437  #define R_USBF_PIPECFG_EPNUM_Msk           (0xfUL)        /*!< EPNUM (Bitfield-Mask: 0x0f)                           */
42438  #define R_USBF_PIPECFG_DIR_Pos             (4UL)          /*!< DIR (Bit 4)                                           */
42439  #define R_USBF_PIPECFG_DIR_Msk             (0x10UL)       /*!< DIR (Bitfield-Mask: 0x01)                             */
42440  #define R_USBF_PIPECFG_SHTNAK_Pos          (7UL)          /*!< SHTNAK (Bit 7)                                        */
42441  #define R_USBF_PIPECFG_SHTNAK_Msk          (0x80UL)       /*!< SHTNAK (Bitfield-Mask: 0x01)                          */
42442  #define R_USBF_PIPECFG_CNTMD_Pos           (8UL)          /*!< CNTMD (Bit 8)                                         */
42443  #define R_USBF_PIPECFG_CNTMD_Msk           (0x100UL)      /*!< CNTMD (Bitfield-Mask: 0x01)                           */
42444  #define R_USBF_PIPECFG_DBLB_Pos            (9UL)          /*!< DBLB (Bit 9)                                          */
42445  #define R_USBF_PIPECFG_DBLB_Msk            (0x200UL)      /*!< DBLB (Bitfield-Mask: 0x01)                            */
42446  #define R_USBF_PIPECFG_BFRE_Pos            (10UL)         /*!< BFRE (Bit 10)                                         */
42447  #define R_USBF_PIPECFG_BFRE_Msk            (0x400UL)      /*!< BFRE (Bitfield-Mask: 0x01)                            */
42448  #define R_USBF_PIPECFG_TYPE_Pos            (14UL)         /*!< TYPE (Bit 14)                                         */
42449  #define R_USBF_PIPECFG_TYPE_Msk            (0xc000UL)     /*!< TYPE (Bitfield-Mask: 0x03)                            */
42450 /* ========================================================  PIPEBUF  ======================================================== */
42451  #define R_USBF_PIPEBUF_BUFNMB_Pos          (0UL)          /*!< BUFNMB (Bit 0)                                        */
42452  #define R_USBF_PIPEBUF_BUFNMB_Msk          (0xffUL)       /*!< BUFNMB (Bitfield-Mask: 0xff)                          */
42453  #define R_USBF_PIPEBUF_BUFSIZE_Pos         (10UL)         /*!< BUFSIZE (Bit 10)                                      */
42454  #define R_USBF_PIPEBUF_BUFSIZE_Msk         (0x7c00UL)     /*!< BUFSIZE (Bitfield-Mask: 0x1f)                         */
42455 /* =======================================================  PIPEMAXP  ======================================================== */
42456  #define R_USBF_PIPEMAXP_MXPS_Pos           (0UL)          /*!< MXPS (Bit 0)                                          */
42457  #define R_USBF_PIPEMAXP_MXPS_Msk           (0x7ffUL)      /*!< MXPS (Bitfield-Mask: 0x7ff)                           */
42458 /* =======================================================  PIPEPERI  ======================================================== */
42459  #define R_USBF_PIPEPERI_IITV_Pos           (0UL)          /*!< IITV (Bit 0)                                          */
42460  #define R_USBF_PIPEPERI_IITV_Msk           (0x7UL)        /*!< IITV (Bitfield-Mask: 0x07)                            */
42461  #define R_USBF_PIPEPERI_IFIS_Pos           (12UL)         /*!< IFIS (Bit 12)                                         */
42462  #define R_USBF_PIPEPERI_IFIS_Msk           (0x1000UL)     /*!< IFIS (Bitfield-Mask: 0x01)                            */
42463 /* =======================================================  PIPE_CTR  ======================================================== */
42464  #define R_USBF_PIPE_CTR_PID_Pos            (0UL)          /*!< PID (Bit 0)                                           */
42465  #define R_USBF_PIPE_CTR_PID_Msk            (0x3UL)        /*!< PID (Bitfield-Mask: 0x03)                             */
42466  #define R_USBF_PIPE_CTR_PBUSY_Pos          (5UL)          /*!< PBUSY (Bit 5)                                         */
42467  #define R_USBF_PIPE_CTR_PBUSY_Msk          (0x20UL)       /*!< PBUSY (Bitfield-Mask: 0x01)                           */
42468  #define R_USBF_PIPE_CTR_SQMON_Pos          (6UL)          /*!< SQMON (Bit 6)                                         */
42469  #define R_USBF_PIPE_CTR_SQMON_Msk          (0x40UL)       /*!< SQMON (Bitfield-Mask: 0x01)                           */
42470  #define R_USBF_PIPE_CTR_SQSET_Pos          (7UL)          /*!< SQSET (Bit 7)                                         */
42471  #define R_USBF_PIPE_CTR_SQSET_Msk          (0x80UL)       /*!< SQSET (Bitfield-Mask: 0x01)                           */
42472  #define R_USBF_PIPE_CTR_SQCLR_Pos          (8UL)          /*!< SQCLR (Bit 8)                                         */
42473  #define R_USBF_PIPE_CTR_SQCLR_Msk          (0x100UL)      /*!< SQCLR (Bitfield-Mask: 0x01)                           */
42474  #define R_USBF_PIPE_CTR_ACLRM_Pos          (9UL)          /*!< ACLRM (Bit 9)                                         */
42475  #define R_USBF_PIPE_CTR_ACLRM_Msk          (0x200UL)      /*!< ACLRM (Bitfield-Mask: 0x01)                           */
42476  #define R_USBF_PIPE_CTR_ATREPM_Pos         (10UL)         /*!< ATREPM (Bit 10)                                       */
42477  #define R_USBF_PIPE_CTR_ATREPM_Msk         (0x400UL)      /*!< ATREPM (Bitfield-Mask: 0x01)                          */
42478  #define R_USBF_PIPE_CTR_INBUFM_Pos         (14UL)         /*!< INBUFM (Bit 14)                                       */
42479  #define R_USBF_PIPE_CTR_INBUFM_Msk         (0x4000UL)     /*!< INBUFM (Bitfield-Mask: 0x01)                          */
42480  #define R_USBF_PIPE_CTR_BSTS_Pos           (15UL)         /*!< BSTS (Bit 15)                                         */
42481  #define R_USBF_PIPE_CTR_BSTS_Msk           (0x8000UL)     /*!< BSTS (Bitfield-Mask: 0x01)                            */
42482 /* =========================================================  LPSTS  ========================================================= */
42483  #define R_USBF_LPSTS_SUSPM_Pos             (14UL)         /*!< SUSPM (Bit 14)                                        */
42484  #define R_USBF_LPSTS_SUSPM_Msk             (0x4000UL)     /*!< SUSPM (Bitfield-Mask: 0x01)                           */
42485 /* =========================================================  DCTRL  ========================================================= */
42486  #define R_USBF_DCTRL_PR_Pos                (0UL)          /*!< PR (Bit 0)                                            */
42487  #define R_USBF_DCTRL_PR_Msk                (0x1UL)        /*!< PR (Bitfield-Mask: 0x01)                              */
42488  #define R_USBF_DCTRL_LDPR_Pos              (16UL)         /*!< LDPR (Bit 16)                                         */
42489  #define R_USBF_DCTRL_LDPR_Msk              (0xf0000UL)    /*!< LDPR (Bitfield-Mask: 0x0f)                            */
42490  #define R_USBF_DCTRL_LWPR_Pos              (24UL)         /*!< LWPR (Bit 24)                                         */
42491  #define R_USBF_DCTRL_LWPR_Msk              (0xf000000UL)  /*!< LWPR (Bitfield-Mask: 0x0f)                            */
42492 /* ========================================================  DSCITVL  ======================================================== */
42493  #define R_USBF_DSCITVL_DITVL_Pos           (8UL)          /*!< DITVL (Bit 8)                                         */
42494  #define R_USBF_DSCITVL_DITVL_Msk           (0xff00UL)     /*!< DITVL (Bitfield-Mask: 0xff)                           */
42495 /* =======================================================  DSTAT_EN  ======================================================== */
42496  #define R_USBF_DSTAT_EN_EN0_Pos            (0UL)          /*!< EN0 (Bit 0)                                           */
42497  #define R_USBF_DSTAT_EN_EN0_Msk            (0x1UL)        /*!< EN0 (Bitfield-Mask: 0x01)                             */
42498  #define R_USBF_DSTAT_EN_EN1_Pos            (1UL)          /*!< EN1 (Bit 1)                                           */
42499  #define R_USBF_DSTAT_EN_EN1_Msk            (0x2UL)        /*!< EN1 (Bitfield-Mask: 0x01)                             */
42500 /* =======================================================  DSTAT_ER  ======================================================== */
42501  #define R_USBF_DSTAT_ER_ER0_Pos            (0UL)          /*!< ER0 (Bit 0)                                           */
42502  #define R_USBF_DSTAT_ER_ER0_Msk            (0x1UL)        /*!< ER0 (Bitfield-Mask: 0x01)                             */
42503  #define R_USBF_DSTAT_ER_ER1_Pos            (1UL)          /*!< ER1 (Bit 1)                                           */
42504  #define R_USBF_DSTAT_ER_ER1_Msk            (0x2UL)        /*!< ER1 (Bitfield-Mask: 0x01)                             */
42505 /* =======================================================  DSTAT_END  ======================================================= */
42506  #define R_USBF_DSTAT_END_END0_Pos          (0UL)          /*!< END0 (Bit 0)                                          */
42507  #define R_USBF_DSTAT_END_END0_Msk          (0x1UL)        /*!< END0 (Bitfield-Mask: 0x01)                            */
42508  #define R_USBF_DSTAT_END_END1_Pos          (1UL)          /*!< END1 (Bit 1)                                          */
42509  #define R_USBF_DSTAT_END_END1_Msk          (0x2UL)        /*!< END1 (Bitfield-Mask: 0x01)                            */
42510 /* =======================================================  DSTAT_TC  ======================================================== */
42511  #define R_USBF_DSTAT_TC_TC0_Pos            (0UL)          /*!< TC0 (Bit 0)                                           */
42512  #define R_USBF_DSTAT_TC_TC0_Msk            (0x1UL)        /*!< TC0 (Bitfield-Mask: 0x01)                             */
42513  #define R_USBF_DSTAT_TC_TC1_Pos            (1UL)          /*!< TC1 (Bit 1)                                           */
42514  #define R_USBF_DSTAT_TC_TC1_Msk            (0x2UL)        /*!< TC1 (Bitfield-Mask: 0x01)                             */
42515 /* =======================================================  DSTAT_SUS  ======================================================= */
42516  #define R_USBF_DSTAT_SUS_SUS0_Pos          (0UL)          /*!< SUS0 (Bit 0)                                          */
42517  #define R_USBF_DSTAT_SUS_SUS0_Msk          (0x1UL)        /*!< SUS0 (Bitfield-Mask: 0x01)                            */
42518  #define R_USBF_DSTAT_SUS_SUS1_Pos          (1UL)          /*!< SUS1 (Bit 1)                                          */
42519  #define R_USBF_DSTAT_SUS_SUS1_Msk          (0x2UL)        /*!< SUS1 (Bitfield-Mask: 0x01)                            */
42520 
42521 /* =========================================================================================================================== */
42522 /* ================                                           R_BSC                                           ================ */
42523 /* =========================================================================================================================== */
42524 
42525 /* =========================================================  CMNCR  ========================================================= */
42526  #define R_BSC_CMNCR_DPRTY_Pos        (9UL)          /*!< DPRTY (Bit 9)                                         */
42527  #define R_BSC_CMNCR_DPRTY_Msk        (0x600UL)      /*!< DPRTY (Bitfield-Mask: 0x03)                           */
42528  #define R_BSC_CMNCR_AL_Pos           (24UL)         /*!< AL (Bit 24)                                           */
42529  #define R_BSC_CMNCR_AL_Msk           (0x1000000UL)  /*!< AL (Bitfield-Mask: 0x01)                              */
42530  #define R_BSC_CMNCR_TL_Pos           (28UL)         /*!< TL (Bit 28)                                           */
42531  #define R_BSC_CMNCR_TL_Msk           (0x10000000UL) /*!< TL (Bitfield-Mask: 0x01)                              */
42532 /* ========================================================  CSnBCR  ========================================================= */
42533  #define R_BSC_CSnBCR_BSZ_Pos         (9UL)          /*!< BSZ (Bit 9)                                           */
42534  #define R_BSC_CSnBCR_BSZ_Msk         (0x600UL)      /*!< BSZ (Bitfield-Mask: 0x03)                             */
42535  #define R_BSC_CSnBCR_TYPE_Pos        (12UL)         /*!< TYPE (Bit 12)                                         */
42536  #define R_BSC_CSnBCR_TYPE_Msk        (0x7000UL)     /*!< TYPE (Bitfield-Mask: 0x07)                            */
42537  #define R_BSC_CSnBCR_IWRRS_Pos       (16UL)         /*!< IWRRS (Bit 16)                                        */
42538  #define R_BSC_CSnBCR_IWRRS_Msk       (0x70000UL)    /*!< IWRRS (Bitfield-Mask: 0x07)                           */
42539  #define R_BSC_CSnBCR_IWRRD_Pos       (19UL)         /*!< IWRRD (Bit 19)                                        */
42540  #define R_BSC_CSnBCR_IWRRD_Msk       (0x380000UL)   /*!< IWRRD (Bitfield-Mask: 0x07)                           */
42541  #define R_BSC_CSnBCR_IWRWS_Pos       (22UL)         /*!< IWRWS (Bit 22)                                        */
42542  #define R_BSC_CSnBCR_IWRWS_Msk       (0x1c00000UL)  /*!< IWRWS (Bitfield-Mask: 0x07)                           */
42543  #define R_BSC_CSnBCR_IWRWD_Pos       (25UL)         /*!< IWRWD (Bit 25)                                        */
42544  #define R_BSC_CSnBCR_IWRWD_Msk       (0xe000000UL)  /*!< IWRWD (Bitfield-Mask: 0x07)                           */
42545  #define R_BSC_CSnBCR_IWW_Pos         (28UL)         /*!< IWW (Bit 28)                                          */
42546  #define R_BSC_CSnBCR_IWW_Msk         (0x70000000UL) /*!< IWW (Bitfield-Mask: 0x07)                             */
42547 /* =======================================================  CS0WCR_0  ======================================================== */
42548  #define R_BSC_CS0WCR_0_HW_Pos        (0UL)          /*!< HW (Bit 0)                                            */
42549  #define R_BSC_CS0WCR_0_HW_Msk        (0x3UL)        /*!< HW (Bitfield-Mask: 0x03)                              */
42550  #define R_BSC_CS0WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
42551  #define R_BSC_CS0WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
42552  #define R_BSC_CS0WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
42553  #define R_BSC_CS0WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
42554  #define R_BSC_CS0WCR_0_SW_Pos        (11UL)         /*!< SW (Bit 11)                                           */
42555  #define R_BSC_CS0WCR_0_SW_Msk        (0x1800UL)     /*!< SW (Bitfield-Mask: 0x03)                              */
42556  #define R_BSC_CS0WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
42557  #define R_BSC_CS0WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
42558 /* =======================================================  CS0WCR_1  ======================================================== */
42559  #define R_BSC_CS0WCR_1_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
42560  #define R_BSC_CS0WCR_1_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
42561  #define R_BSC_CS0WCR_1_W_Pos         (7UL)          /*!< W (Bit 7)                                             */
42562  #define R_BSC_CS0WCR_1_W_Msk         (0x780UL)      /*!< W (Bitfield-Mask: 0x0f)                               */
42563  #define R_BSC_CS0WCR_1_BW_Pos        (16UL)         /*!< BW (Bit 16)                                           */
42564  #define R_BSC_CS0WCR_1_BW_Msk        (0x30000UL)    /*!< BW (Bitfield-Mask: 0x03)                              */
42565  #define R_BSC_CS0WCR_1_BST_Pos       (20UL)         /*!< BST (Bit 20)                                          */
42566  #define R_BSC_CS0WCR_1_BST_Msk       (0x300000UL)   /*!< BST (Bitfield-Mask: 0x03)                             */
42567 /* =======================================================  CS0WCR_2  ======================================================== */
42568  #define R_BSC_CS0WCR_2_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
42569  #define R_BSC_CS0WCR_2_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
42570  #define R_BSC_CS0WCR_2_W_Pos         (7UL)          /*!< W (Bit 7)                                             */
42571  #define R_BSC_CS0WCR_2_W_Msk         (0x780UL)      /*!< W (Bitfield-Mask: 0x0f)                               */
42572  #define R_BSC_CS0WCR_2_BW_Pos        (16UL)         /*!< BW (Bit 16)                                           */
42573  #define R_BSC_CS0WCR_2_BW_Msk        (0x30000UL)    /*!< BW (Bitfield-Mask: 0x03)                              */
42574 /* =======================================================  CS2WCR_0  ======================================================== */
42575  #define R_BSC_CS2WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
42576  #define R_BSC_CS2WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
42577  #define R_BSC_CS2WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
42578  #define R_BSC_CS2WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
42579  #define R_BSC_CS2WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
42580  #define R_BSC_CS2WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
42581 /* =======================================================  CS2WCR_1  ======================================================== */
42582  #define R_BSC_CS2WCR_1_A2CL_Pos      (7UL)          /*!< A2CL (Bit 7)                                          */
42583  #define R_BSC_CS2WCR_1_A2CL_Msk      (0x180UL)      /*!< A2CL (Bitfield-Mask: 0x03)                            */
42584 /* =======================================================  CS3WCR_0  ======================================================== */
42585  #define R_BSC_CS3WCR_0_WM_Pos        (6UL)          /*!< WM (Bit 6)                                            */
42586  #define R_BSC_CS3WCR_0_WM_Msk        (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
42587  #define R_BSC_CS3WCR_0_WR_Pos        (7UL)          /*!< WR (Bit 7)                                            */
42588  #define R_BSC_CS3WCR_0_WR_Msk        (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
42589  #define R_BSC_CS3WCR_0_BAS_Pos       (20UL)         /*!< BAS (Bit 20)                                          */
42590  #define R_BSC_CS3WCR_0_BAS_Msk       (0x100000UL)   /*!< BAS (Bitfield-Mask: 0x01)                             */
42591 /* =======================================================  CS3WCR_1  ======================================================== */
42592  #define R_BSC_CS3WCR_1_WTRC_Pos      (0UL)          /*!< WTRC (Bit 0)                                          */
42593  #define R_BSC_CS3WCR_1_WTRC_Msk      (0x3UL)        /*!< WTRC (Bitfield-Mask: 0x03)                            */
42594  #define R_BSC_CS3WCR_1_TRWL_Pos      (3UL)          /*!< TRWL (Bit 3)                                          */
42595  #define R_BSC_CS3WCR_1_TRWL_Msk      (0x18UL)       /*!< TRWL (Bitfield-Mask: 0x03)                            */
42596  #define R_BSC_CS3WCR_1_A3CL_Pos      (7UL)          /*!< A3CL (Bit 7)                                          */
42597  #define R_BSC_CS3WCR_1_A3CL_Msk      (0x180UL)      /*!< A3CL (Bitfield-Mask: 0x03)                            */
42598  #define R_BSC_CS3WCR_1_WTRCD_Pos     (10UL)         /*!< WTRCD (Bit 10)                                        */
42599  #define R_BSC_CS3WCR_1_WTRCD_Msk     (0xc00UL)      /*!< WTRCD (Bitfield-Mask: 0x03)                           */
42600  #define R_BSC_CS3WCR_1_WTRP_Pos      (13UL)         /*!< WTRP (Bit 13)                                         */
42601  #define R_BSC_CS3WCR_1_WTRP_Msk      (0x6000UL)     /*!< WTRP (Bitfield-Mask: 0x03)                            */
42602 /* ========================================================  CS5WCR  ========================================================= */
42603  #define R_BSC_CS5WCR_HW_Pos          (0UL)          /*!< HW (Bit 0)                                            */
42604  #define R_BSC_CS5WCR_HW_Msk          (0x3UL)        /*!< HW (Bitfield-Mask: 0x03)                              */
42605  #define R_BSC_CS5WCR_WM_Pos          (6UL)          /*!< WM (Bit 6)                                            */
42606  #define R_BSC_CS5WCR_WM_Msk          (0x40UL)       /*!< WM (Bitfield-Mask: 0x01)                              */
42607  #define R_BSC_CS5WCR_WR_Pos          (7UL)          /*!< WR (Bit 7)                                            */
42608  #define R_BSC_CS5WCR_WR_Msk          (0x780UL)      /*!< WR (Bitfield-Mask: 0x0f)                              */
42609  #define R_BSC_CS5WCR_SW_Pos          (11UL)         /*!< SW (Bit 11)                                           */
42610  #define R_BSC_CS5WCR_SW_Msk          (0x1800UL)     /*!< SW (Bitfield-Mask: 0x03)                              */
42611  #define R_BSC_CS5WCR_WW_Pos          (16UL)         /*!< WW (Bit 16)                                           */
42612  #define R_BSC_CS5WCR_WW_Msk          (0x70000UL)    /*!< WW (Bitfield-Mask: 0x07)                              */
42613  #define R_BSC_CS5WCR_MPXWSBAS_Pos    (20UL)         /*!< MPXWSBAS (Bit 20)                                     */
42614  #define R_BSC_CS5WCR_MPXWSBAS_Msk    (0x100000UL)   /*!< MPXWSBAS (Bitfield-Mask: 0x01)                        */
42615  #define R_BSC_CS5WCR_SZSEL_Pos       (21UL)         /*!< SZSEL (Bit 21)                                        */
42616  #define R_BSC_CS5WCR_SZSEL_Msk       (0x200000UL)   /*!< SZSEL (Bitfield-Mask: 0x01)                           */
42617 /* =========================================================  SDCR  ========================================================== */
42618  #define R_BSC_SDCR_A3COL_Pos         (0UL)          /*!< A3COL (Bit 0)                                         */
42619  #define R_BSC_SDCR_A3COL_Msk         (0x3UL)        /*!< A3COL (Bitfield-Mask: 0x03)                           */
42620  #define R_BSC_SDCR_A3ROW_Pos         (3UL)          /*!< A3ROW (Bit 3)                                         */
42621  #define R_BSC_SDCR_A3ROW_Msk         (0x18UL)       /*!< A3ROW (Bitfield-Mask: 0x03)                           */
42622  #define R_BSC_SDCR_BACTV_Pos         (8UL)          /*!< BACTV (Bit 8)                                         */
42623  #define R_BSC_SDCR_BACTV_Msk         (0x100UL)      /*!< BACTV (Bitfield-Mask: 0x01)                           */
42624  #define R_BSC_SDCR_PDOWN_Pos         (9UL)          /*!< PDOWN (Bit 9)                                         */
42625  #define R_BSC_SDCR_PDOWN_Msk         (0x200UL)      /*!< PDOWN (Bitfield-Mask: 0x01)                           */
42626  #define R_BSC_SDCR_RMODE_Pos         (10UL)         /*!< RMODE (Bit 10)                                        */
42627  #define R_BSC_SDCR_RMODE_Msk         (0x400UL)      /*!< RMODE (Bitfield-Mask: 0x01)                           */
42628  #define R_BSC_SDCR_RFSH_Pos          (11UL)         /*!< RFSH (Bit 11)                                         */
42629  #define R_BSC_SDCR_RFSH_Msk          (0x800UL)      /*!< RFSH (Bitfield-Mask: 0x01)                            */
42630  #define R_BSC_SDCR_DEEP_Pos          (13UL)         /*!< DEEP (Bit 13)                                         */
42631  #define R_BSC_SDCR_DEEP_Msk          (0x2000UL)     /*!< DEEP (Bitfield-Mask: 0x01)                            */
42632  #define R_BSC_SDCR_A2COL_Pos         (16UL)         /*!< A2COL (Bit 16)                                        */
42633  #define R_BSC_SDCR_A2COL_Msk         (0x30000UL)    /*!< A2COL (Bitfield-Mask: 0x03)                           */
42634  #define R_BSC_SDCR_A2ROW_Pos         (19UL)         /*!< A2ROW (Bit 19)                                        */
42635  #define R_BSC_SDCR_A2ROW_Msk         (0x180000UL)   /*!< A2ROW (Bitfield-Mask: 0x03)                           */
42636 /* =========================================================  RTCSR  ========================================================= */
42637 /* =========================================================  RTCNT  ========================================================= */
42638 /* =========================================================  RTCOR  ========================================================= */
42639 /* ========================================================  TOSCOR  ========================================================= */
42640  #define R_BSC_TOSCOR_TOCNUM_Pos      (0UL)      /*!< TOCNUM (Bit 0)                                        */
42641  #define R_BSC_TOSCOR_TOCNUM_Msk      (0xffffUL) /*!< TOCNUM (Bitfield-Mask: 0xffff)                        */
42642 /* =========================================================  TOSTR  ========================================================= */
42643  #define R_BSC_TOSTR_CS0TOSTF_Pos     (0UL)      /*!< CS0TOSTF (Bit 0)                                      */
42644  #define R_BSC_TOSTR_CS0TOSTF_Msk     (0x1UL)    /*!< CS0TOSTF (Bitfield-Mask: 0x01)                        */
42645  #define R_BSC_TOSTR_CS2TOSTF_Pos     (2UL)      /*!< CS2TOSTF (Bit 2)                                      */
42646  #define R_BSC_TOSTR_CS2TOSTF_Msk     (0x4UL)    /*!< CS2TOSTF (Bitfield-Mask: 0x01)                        */
42647  #define R_BSC_TOSTR_CS3TOSTF_Pos     (3UL)      /*!< CS3TOSTF (Bit 3)                                      */
42648  #define R_BSC_TOSTR_CS3TOSTF_Msk     (0x8UL)    /*!< CS3TOSTF (Bitfield-Mask: 0x01)                        */
42649  #define R_BSC_TOSTR_CS5TOSTF_Pos     (5UL)      /*!< CS5TOSTF (Bit 5)                                      */
42650  #define R_BSC_TOSTR_CS5TOSTF_Msk     (0x20UL)   /*!< CS5TOSTF (Bitfield-Mask: 0x01)                        */
42651 /* =========================================================  TOENR  ========================================================= */
42652  #define R_BSC_TOENR_CS0TOEN_Pos      (0UL)      /*!< CS0TOEN (Bit 0)                                       */
42653  #define R_BSC_TOENR_CS0TOEN_Msk      (0x1UL)    /*!< CS0TOEN (Bitfield-Mask: 0x01)                         */
42654  #define R_BSC_TOENR_CS2TOEN_Pos      (2UL)      /*!< CS2TOEN (Bit 2)                                       */
42655  #define R_BSC_TOENR_CS2TOEN_Msk      (0x4UL)    /*!< CS2TOEN (Bitfield-Mask: 0x01)                         */
42656  #define R_BSC_TOENR_CS3TOEN_Pos      (3UL)      /*!< CS3TOEN (Bit 3)                                       */
42657  #define R_BSC_TOENR_CS3TOEN_Msk      (0x8UL)    /*!< CS3TOEN (Bitfield-Mask: 0x01)                         */
42658  #define R_BSC_TOENR_CS5TOEN_Pos      (5UL)      /*!< CS5TOEN (Bit 5)                                       */
42659  #define R_BSC_TOENR_CS5TOEN_Msk      (0x20UL)   /*!< CS5TOEN (Bitfield-Mask: 0x01)                         */
42660 
42661 /* =========================================================================================================================== */
42662 /* ================                                          R_XSPI0                                          ================ */
42663 /* =========================================================================================================================== */
42664 
42665 /* ========================================================  WRAPCFG  ======================================================== */
42666  #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos      (8UL)          /*!< DSSFTCS0 (Bit 8)                                      */
42667  #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk      (0x1f00UL)     /*!< DSSFTCS0 (Bitfield-Mask: 0x1f)                        */
42668  #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos      (24UL)         /*!< DSSFTCS1 (Bit 24)                                     */
42669  #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk      (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f)                        */
42670 /* ========================================================  COMCFG  ========================================================= */
42671  #define R_XSPI0_COMCFG_OEASTEX_Pos        (16UL)         /*!< OEASTEX (Bit 16)                                      */
42672  #define R_XSPI0_COMCFG_OEASTEX_Msk        (0x10000UL)    /*!< OEASTEX (Bitfield-Mask: 0x01)                         */
42673  #define R_XSPI0_COMCFG_OENEGEX_Pos        (17UL)         /*!< OENEGEX (Bit 17)                                      */
42674  #define R_XSPI0_COMCFG_OENEGEX_Msk        (0x20000UL)    /*!< OENEGEX (Bitfield-Mask: 0x01)                         */
42675 /* =========================================================  BMCFG  ========================================================= */
42676  #define R_XSPI0_BMCFG_WRMD_Pos            (0UL)          /*!< WRMD (Bit 0)                                          */
42677  #define R_XSPI0_BMCFG_WRMD_Msk            (0x1UL)        /*!< WRMD (Bitfield-Mask: 0x01)                            */
42678  #define R_XSPI0_BMCFG_MWRCOMB_Pos         (7UL)          /*!< MWRCOMB (Bit 7)                                       */
42679  #define R_XSPI0_BMCFG_MWRCOMB_Msk         (0x80UL)       /*!< MWRCOMB (Bitfield-Mask: 0x01)                         */
42680  #define R_XSPI0_BMCFG_MWRSIZE_Pos         (8UL)          /*!< MWRSIZE (Bit 8)                                       */
42681  #define R_XSPI0_BMCFG_MWRSIZE_Msk         (0xff00UL)     /*!< MWRSIZE (Bitfield-Mask: 0xff)                         */
42682  #define R_XSPI0_BMCFG_PREEN_Pos           (16UL)         /*!< PREEN (Bit 16)                                        */
42683  #define R_XSPI0_BMCFG_PREEN_Msk           (0x10000UL)    /*!< PREEN (Bitfield-Mask: 0x01)                           */
42684 /* =======================================================  LIOCFGCS  ======================================================== */
42685  #define R_XSPI0_LIOCFGCS_PRTMD_Pos        (0UL)          /*!< PRTMD (Bit 0)                                         */
42686  #define R_XSPI0_LIOCFGCS_PRTMD_Msk        (0x3ffUL)      /*!< PRTMD (Bitfield-Mask: 0x3ff)                          */
42687  #define R_XSPI0_LIOCFGCS_LATEMD_Pos       (10UL)         /*!< LATEMD (Bit 10)                                       */
42688  #define R_XSPI0_LIOCFGCS_LATEMD_Msk       (0x400UL)      /*!< LATEMD (Bitfield-Mask: 0x01)                          */
42689  #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos      (11UL)         /*!< WRMSKMD (Bit 11)                                      */
42690  #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk      (0x800UL)      /*!< WRMSKMD (Bitfield-Mask: 0x01)                         */
42691  #define R_XSPI0_LIOCFGCS_CSMIN_Pos        (16UL)         /*!< CSMIN (Bit 16)                                        */
42692  #define R_XSPI0_LIOCFGCS_CSMIN_Msk        (0xf0000UL)    /*!< CSMIN (Bitfield-Mask: 0x0f)                           */
42693  #define R_XSPI0_LIOCFGCS_CSASTEX_Pos      (20UL)         /*!< CSASTEX (Bit 20)                                      */
42694  #define R_XSPI0_LIOCFGCS_CSASTEX_Msk      (0x100000UL)   /*!< CSASTEX (Bitfield-Mask: 0x01)                         */
42695  #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos      (21UL)         /*!< CSNEGEX (Bit 21)                                      */
42696  #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk      (0x200000UL)   /*!< CSNEGEX (Bitfield-Mask: 0x01)                         */
42697  #define R_XSPI0_LIOCFGCS_SDRDRV_Pos       (22UL)         /*!< SDRDRV (Bit 22)                                       */
42698  #define R_XSPI0_LIOCFGCS_SDRDRV_Msk       (0x400000UL)   /*!< SDRDRV (Bitfield-Mask: 0x01)                          */
42699  #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos     (23UL)         /*!< SDRSMPMD (Bit 23)                                     */
42700  #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk     (0x800000UL)   /*!< SDRSMPMD (Bitfield-Mask: 0x01)                        */
42701  #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos    (24UL)         /*!< SDRSMPSFT (Bit 24)                                    */
42702  #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk    (0xf000000UL)  /*!< SDRSMPSFT (Bitfield-Mask: 0x0f)                       */
42703  #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos     (28UL)         /*!< DDRSMPEX (Bit 28)                                     */
42704  #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk     (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f)                        */
42705 /* ========================================================  BMCTL0  ========================================================= */
42706  #define R_XSPI0_BMCTL0_CS0ACC_Pos         (0UL)          /*!< CS0ACC (Bit 0)                                        */
42707  #define R_XSPI0_BMCTL0_CS0ACC_Msk         (0x3UL)        /*!< CS0ACC (Bitfield-Mask: 0x03)                          */
42708  #define R_XSPI0_BMCTL0_CS1ACC_Pos         (2UL)          /*!< CS1ACC (Bit 2)                                        */
42709  #define R_XSPI0_BMCTL0_CS1ACC_Msk         (0xcUL)        /*!< CS1ACC (Bitfield-Mask: 0x03)                          */
42710 /* ========================================================  BMCTL1  ========================================================= */
42711  #define R_XSPI0_BMCTL1_MWRPUSH_Pos        (8UL)          /*!< MWRPUSH (Bit 8)                                       */
42712  #define R_XSPI0_BMCTL1_MWRPUSH_Msk        (0x100UL)      /*!< MWRPUSH (Bitfield-Mask: 0x01)                         */
42713  #define R_XSPI0_BMCTL1_PBUFCLR_Pos        (10UL)         /*!< PBUFCLR (Bit 10)                                      */
42714  #define R_XSPI0_BMCTL1_PBUFCLR_Msk        (0x400UL)      /*!< PBUFCLR (Bitfield-Mask: 0x01)                         */
42715 /* =========================================================  CMCTL  ========================================================= */
42716  #define R_XSPI0_CMCTL_XIPENCODE_Pos       (0UL)          /*!< XIPENCODE (Bit 0)                                     */
42717  #define R_XSPI0_CMCTL_XIPENCODE_Msk       (0xffUL)       /*!< XIPENCODE (Bitfield-Mask: 0xff)                       */
42718  #define R_XSPI0_CMCTL_XIPEXCODE_Pos       (8UL)          /*!< XIPEXCODE (Bit 8)                                     */
42719  #define R_XSPI0_CMCTL_XIPEXCODE_Msk       (0xff00UL)     /*!< XIPEXCODE (Bitfield-Mask: 0xff)                       */
42720  #define R_XSPI0_CMCTL_XIPEN_Pos           (16UL)         /*!< XIPEN (Bit 16)                                        */
42721  #define R_XSPI0_CMCTL_XIPEN_Msk           (0x10000UL)    /*!< XIPEN (Bitfield-Mask: 0x01)                           */
42722 /* ========================================================  CSSCTL  ========================================================= */
42723  #define R_XSPI0_CSSCTL_CS0SIZE_Pos        (0UL)          /*!< CS0SIZE (Bit 0)                                       */
42724  #define R_XSPI0_CSSCTL_CS0SIZE_Msk        (0x3fUL)       /*!< CS0SIZE (Bitfield-Mask: 0x3f)                         */
42725  #define R_XSPI0_CSSCTL_CS1SIZE_Pos        (8UL)          /*!< CS1SIZE (Bit 8)                                       */
42726  #define R_XSPI0_CSSCTL_CS1SIZE_Msk        (0x3f00UL)     /*!< CS1SIZE (Bitfield-Mask: 0x3f)                         */
42727 /* ========================================================  CDCTL0  ========================================================= */
42728  #define R_XSPI0_CDCTL0_TRREQ_Pos          (0UL)          /*!< TRREQ (Bit 0)                                         */
42729  #define R_XSPI0_CDCTL0_TRREQ_Msk          (0x1UL)        /*!< TRREQ (Bitfield-Mask: 0x01)                           */
42730  #define R_XSPI0_CDCTL0_PERMD_Pos          (1UL)          /*!< PERMD (Bit 1)                                         */
42731  #define R_XSPI0_CDCTL0_PERMD_Msk          (0x2UL)        /*!< PERMD (Bitfield-Mask: 0x01)                           */
42732  #define R_XSPI0_CDCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
42733  #define R_XSPI0_CDCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
42734  #define R_XSPI0_CDCTL0_TRNUM_Pos          (4UL)          /*!< TRNUM (Bit 4)                                         */
42735  #define R_XSPI0_CDCTL0_TRNUM_Msk          (0x30UL)       /*!< TRNUM (Bitfield-Mask: 0x03)                           */
42736  #define R_XSPI0_CDCTL0_PERITV_Pos         (16UL)         /*!< PERITV (Bit 16)                                       */
42737  #define R_XSPI0_CDCTL0_PERITV_Msk         (0x1f0000UL)   /*!< PERITV (Bitfield-Mask: 0x1f)                          */
42738  #define R_XSPI0_CDCTL0_PERREP_Pos         (24UL)         /*!< PERREP (Bit 24)                                       */
42739  #define R_XSPI0_CDCTL0_PERREP_Msk         (0xf000000UL)  /*!< PERREP (Bitfield-Mask: 0x0f)                          */
42740 /* ========================================================  CDCTL1  ========================================================= */
42741  #define R_XSPI0_CDCTL1_PEREXP_Pos         (0UL)          /*!< PEREXP (Bit 0)                                        */
42742  #define R_XSPI0_CDCTL1_PEREXP_Msk         (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff)                    */
42743 /* ========================================================  CDCTL2  ========================================================= */
42744  #define R_XSPI0_CDCTL2_PERMSK_Pos         (0UL)          /*!< PERMSK (Bit 0)                                        */
42745  #define R_XSPI0_CDCTL2_PERMSK_Msk         (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff)                    */
42746 /* ========================================================  LPCTL0  ========================================================= */
42747  #define R_XSPI0_LPCTL0_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
42748  #define R_XSPI0_LPCTL0_PATREQ_Msk         (0x1UL)        /*!< PATREQ (Bitfield-Mask: 0x01)                          */
42749  #define R_XSPI0_LPCTL0_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
42750  #define R_XSPI0_LPCTL0_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
42751  #define R_XSPI0_LPCTL0_XDPIN_Pos          (4UL)          /*!< XDPIN (Bit 4)                                         */
42752  #define R_XSPI0_LPCTL0_XDPIN_Msk          (0x30UL)       /*!< XDPIN (Bitfield-Mask: 0x03)                           */
42753  #define R_XSPI0_LPCTL0_XD1LEN_Pos         (16UL)         /*!< XD1LEN (Bit 16)                                       */
42754  #define R_XSPI0_LPCTL0_XD1LEN_Msk         (0x1f0000UL)   /*!< XD1LEN (Bitfield-Mask: 0x1f)                          */
42755  #define R_XSPI0_LPCTL0_XD1VAL_Pos         (23UL)         /*!< XD1VAL (Bit 23)                                       */
42756  #define R_XSPI0_LPCTL0_XD1VAL_Msk         (0x800000UL)   /*!< XD1VAL (Bitfield-Mask: 0x01)                          */
42757  #define R_XSPI0_LPCTL0_XD2LEN_Pos         (24UL)         /*!< XD2LEN (Bit 24)                                       */
42758  #define R_XSPI0_LPCTL0_XD2LEN_Msk         (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f)                          */
42759  #define R_XSPI0_LPCTL0_XD2VAL_Pos         (31UL)         /*!< XD2VAL (Bit 31)                                       */
42760  #define R_XSPI0_LPCTL0_XD2VAL_Msk         (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01)                          */
42761 /* ========================================================  LPCTL1  ========================================================= */
42762  #define R_XSPI0_LPCTL1_PATREQ_Pos         (0UL)          /*!< PATREQ (Bit 0)                                        */
42763  #define R_XSPI0_LPCTL1_PATREQ_Msk         (0x3UL)        /*!< PATREQ (Bitfield-Mask: 0x03)                          */
42764  #define R_XSPI0_LPCTL1_CSSEL_Pos          (3UL)          /*!< CSSEL (Bit 3)                                         */
42765  #define R_XSPI0_LPCTL1_CSSEL_Msk          (0x8UL)        /*!< CSSEL (Bitfield-Mask: 0x01)                           */
42766  #define R_XSPI0_LPCTL1_RSTREP_Pos         (4UL)          /*!< RSTREP (Bit 4)                                        */
42767  #define R_XSPI0_LPCTL1_RSTREP_Msk         (0x30UL)       /*!< RSTREP (Bitfield-Mask: 0x03)                          */
42768  #define R_XSPI0_LPCTL1_RSTWID_Pos         (8UL)          /*!< RSTWID (Bit 8)                                        */
42769  #define R_XSPI0_LPCTL1_RSTWID_Msk         (0x700UL)      /*!< RSTWID (Bitfield-Mask: 0x07)                          */
42770  #define R_XSPI0_LPCTL1_RSTSU_Pos          (12UL)         /*!< RSTSU (Bit 12)                                        */
42771  #define R_XSPI0_LPCTL1_RSTSU_Msk          (0x7000UL)     /*!< RSTSU (Bitfield-Mask: 0x07)                           */
42772 /* ========================================================  LIOCTL  ========================================================= */
42773  #define R_XSPI0_LIOCTL_WPCS0_Pos          (0UL)          /*!< WPCS0 (Bit 0)                                         */
42774  #define R_XSPI0_LIOCTL_WPCS0_Msk          (0x1UL)        /*!< WPCS0 (Bitfield-Mask: 0x01)                           */
42775  #define R_XSPI0_LIOCTL_WPCS1_Pos          (1UL)          /*!< WPCS1 (Bit 1)                                         */
42776  #define R_XSPI0_LIOCTL_WPCS1_Msk          (0x2UL)        /*!< WPCS1 (Bitfield-Mask: 0x01)                           */
42777  #define R_XSPI0_LIOCTL_RSTCS0_Pos         (16UL)         /*!< RSTCS0 (Bit 16)                                       */
42778  #define R_XSPI0_LIOCTL_RSTCS0_Msk         (0x10000UL)    /*!< RSTCS0 (Bitfield-Mask: 0x01)                          */
42779  #define R_XSPI0_LIOCTL_RSTCS1_Pos         (17UL)         /*!< RSTCS1 (Bit 17)                                       */
42780  #define R_XSPI0_LIOCTL_RSTCS1_Msk         (0x20000UL)    /*!< RSTCS1 (Bitfield-Mask: 0x01)                          */
42781 /* ========================================================  VERSTT  ========================================================= */
42782  #define R_XSPI0_VERSTT_VER_Pos            (0UL)          /*!< VER (Bit 0)                                           */
42783  #define R_XSPI0_VERSTT_VER_Msk            (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff)                       */
42784 /* ========================================================  COMSTT  ========================================================= */
42785  #define R_XSPI0_COMSTT_MEMACC_Pos         (0UL)          /*!< MEMACC (Bit 0)                                        */
42786  #define R_XSPI0_COMSTT_MEMACC_Msk         (0x1UL)        /*!< MEMACC (Bitfield-Mask: 0x01)                          */
42787  #define R_XSPI0_COMSTT_PBUFNE_Pos         (4UL)          /*!< PBUFNE (Bit 4)                                        */
42788  #define R_XSPI0_COMSTT_PBUFNE_Msk         (0x10UL)       /*!< PBUFNE (Bitfield-Mask: 0x01)                          */
42789  #define R_XSPI0_COMSTT_WRBUFNE_Pos        (6UL)          /*!< WRBUFNE (Bit 6)                                       */
42790  #define R_XSPI0_COMSTT_WRBUFNE_Msk        (0x40UL)       /*!< WRBUFNE (Bitfield-Mask: 0x01)                         */
42791  #define R_XSPI0_COMSTT_ECSCS0_Pos         (16UL)         /*!< ECSCS0 (Bit 16)                                       */
42792  #define R_XSPI0_COMSTT_ECSCS0_Msk         (0x10000UL)    /*!< ECSCS0 (Bitfield-Mask: 0x01)                          */
42793  #define R_XSPI0_COMSTT_INTCS0_Pos         (17UL)         /*!< INTCS0 (Bit 17)                                       */
42794  #define R_XSPI0_COMSTT_INTCS0_Msk         (0x20000UL)    /*!< INTCS0 (Bitfield-Mask: 0x01)                          */
42795  #define R_XSPI0_COMSTT_RSTOCS0_Pos        (18UL)         /*!< RSTOCS0 (Bit 18)                                      */
42796  #define R_XSPI0_COMSTT_RSTOCS0_Msk        (0x40000UL)    /*!< RSTOCS0 (Bitfield-Mask: 0x01)                         */
42797  #define R_XSPI0_COMSTT_ECSCS1_Pos         (20UL)         /*!< ECSCS1 (Bit 20)                                       */
42798  #define R_XSPI0_COMSTT_ECSCS1_Msk         (0x100000UL)   /*!< ECSCS1 (Bitfield-Mask: 0x01)                          */
42799  #define R_XSPI0_COMSTT_INTCS1_Pos         (21UL)         /*!< INTCS1 (Bit 21)                                       */
42800  #define R_XSPI0_COMSTT_INTCS1_Msk         (0x200000UL)   /*!< INTCS1 (Bitfield-Mask: 0x01)                          */
42801  #define R_XSPI0_COMSTT_RSTOCS1_Pos        (22UL)         /*!< RSTOCS1 (Bit 22)                                      */
42802  #define R_XSPI0_COMSTT_RSTOCS1_Msk        (0x400000UL)   /*!< RSTOCS1 (Bitfield-Mask: 0x01)                         */
42803 /* ========================================================  CASTTCS  ======================================================== */
42804  #define R_XSPI0_CASTTCS_CASUC_Pos         (0UL)          /*!< CASUC (Bit 0)                                         */
42805  #define R_XSPI0_CASTTCS_CASUC_Msk         (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff)                     */
42806 /* =========================================================  INTS  ========================================================== */
42807  #define R_XSPI0_INTS_CMDCMP_Pos           (0UL)          /*!< CMDCMP (Bit 0)                                        */
42808  #define R_XSPI0_INTS_CMDCMP_Msk           (0x1UL)        /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
42809  #define R_XSPI0_INTS_PATCMP_Pos           (1UL)          /*!< PATCMP (Bit 1)                                        */
42810  #define R_XSPI0_INTS_PATCMP_Msk           (0x2UL)        /*!< PATCMP (Bitfield-Mask: 0x01)                          */
42811  #define R_XSPI0_INTS_INICMP_Pos           (2UL)          /*!< INICMP (Bit 2)                                        */
42812  #define R_XSPI0_INTS_INICMP_Msk           (0x4UL)        /*!< INICMP (Bitfield-Mask: 0x01)                          */
42813  #define R_XSPI0_INTS_PERTO_Pos            (3UL)          /*!< PERTO (Bit 3)                                         */
42814  #define R_XSPI0_INTS_PERTO_Msk            (0x8UL)        /*!< PERTO (Bitfield-Mask: 0x01)                           */
42815  #define R_XSPI0_INTS_DSTOCS0_Pos          (4UL)          /*!< DSTOCS0 (Bit 4)                                       */
42816  #define R_XSPI0_INTS_DSTOCS0_Msk          (0x10UL)       /*!< DSTOCS0 (Bitfield-Mask: 0x01)                         */
42817  #define R_XSPI0_INTS_DSTOCS1_Pos          (5UL)          /*!< DSTOCS1 (Bit 5)                                       */
42818  #define R_XSPI0_INTS_DSTOCS1_Msk          (0x20UL)       /*!< DSTOCS1 (Bitfield-Mask: 0x01)                         */
42819  #define R_XSPI0_INTS_ECSCS0_Pos           (8UL)          /*!< ECSCS0 (Bit 8)                                        */
42820  #define R_XSPI0_INTS_ECSCS0_Msk           (0x100UL)      /*!< ECSCS0 (Bitfield-Mask: 0x01)                          */
42821  #define R_XSPI0_INTS_ECSCS1_Pos           (9UL)          /*!< ECSCS1 (Bit 9)                                        */
42822  #define R_XSPI0_INTS_ECSCS1_Msk           (0x200UL)      /*!< ECSCS1 (Bitfield-Mask: 0x01)                          */
42823  #define R_XSPI0_INTS_INTCS0_Pos           (12UL)         /*!< INTCS0 (Bit 12)                                       */
42824  #define R_XSPI0_INTS_INTCS0_Msk           (0x1000UL)     /*!< INTCS0 (Bitfield-Mask: 0x01)                          */
42825  #define R_XSPI0_INTS_INTCS1_Pos           (13UL)         /*!< INTCS1 (Bit 13)                                       */
42826  #define R_XSPI0_INTS_INTCS1_Msk           (0x2000UL)     /*!< INTCS1 (Bitfield-Mask: 0x01)                          */
42827  #define R_XSPI0_INTS_BRGOF_Pos            (16UL)         /*!< BRGOF (Bit 16)                                        */
42828  #define R_XSPI0_INTS_BRGOF_Msk            (0x10000UL)    /*!< BRGOF (Bitfield-Mask: 0x01)                           */
42829  #define R_XSPI0_INTS_BRGUF_Pos            (18UL)         /*!< BRGUF (Bit 18)                                        */
42830  #define R_XSPI0_INTS_BRGUF_Msk            (0x40000UL)    /*!< BRGUF (Bitfield-Mask: 0x01)                           */
42831  #define R_XSPI0_INTS_BUSERR_Pos           (20UL)         /*!< BUSERR (Bit 20)                                       */
42832  #define R_XSPI0_INTS_BUSERR_Msk           (0x100000UL)   /*!< BUSERR (Bitfield-Mask: 0x01)                          */
42833  #define R_XSPI0_INTS_CAFAILCS0_Pos        (28UL)         /*!< CAFAILCS0 (Bit 28)                                    */
42834  #define R_XSPI0_INTS_CAFAILCS0_Msk        (0x10000000UL) /*!< CAFAILCS0 (Bitfield-Mask: 0x01)                       */
42835  #define R_XSPI0_INTS_CAFAILCS1_Pos        (29UL)         /*!< CAFAILCS1 (Bit 29)                                    */
42836  #define R_XSPI0_INTS_CAFAILCS1_Msk        (0x20000000UL) /*!< CAFAILCS1 (Bitfield-Mask: 0x01)                       */
42837  #define R_XSPI0_INTS_CASUCCS0_Pos         (30UL)         /*!< CASUCCS0 (Bit 30)                                     */
42838  #define R_XSPI0_INTS_CASUCCS0_Msk         (0x40000000UL) /*!< CASUCCS0 (Bitfield-Mask: 0x01)                        */
42839  #define R_XSPI0_INTS_CASUCCS1_Pos         (31UL)         /*!< CASUCCS1 (Bit 31)                                     */
42840  #define R_XSPI0_INTS_CASUCCS1_Msk         (0x80000000UL) /*!< CASUCCS1 (Bitfield-Mask: 0x01)                        */
42841 /* =========================================================  INTC  ========================================================== */
42842  #define R_XSPI0_INTC_CMDCMPC_Pos          (0UL)          /*!< CMDCMPC (Bit 0)                                       */
42843  #define R_XSPI0_INTC_CMDCMPC_Msk          (0x1UL)        /*!< CMDCMPC (Bitfield-Mask: 0x01)                         */
42844  #define R_XSPI0_INTC_PATCMPC_Pos          (1UL)          /*!< PATCMPC (Bit 1)                                       */
42845  #define R_XSPI0_INTC_PATCMPC_Msk          (0x2UL)        /*!< PATCMPC (Bitfield-Mask: 0x01)                         */
42846  #define R_XSPI0_INTC_INICMPC_Pos          (2UL)          /*!< INICMPC (Bit 2)                                       */
42847  #define R_XSPI0_INTC_INICMPC_Msk          (0x4UL)        /*!< INICMPC (Bitfield-Mask: 0x01)                         */
42848  #define R_XSPI0_INTC_PERTOC_Pos           (3UL)          /*!< PERTOC (Bit 3)                                        */
42849  #define R_XSPI0_INTC_PERTOC_Msk           (0x8UL)        /*!< PERTOC (Bitfield-Mask: 0x01)                          */
42850  #define R_XSPI0_INTC_DSTOCS0C_Pos         (4UL)          /*!< DSTOCS0C (Bit 4)                                      */
42851  #define R_XSPI0_INTC_DSTOCS0C_Msk         (0x10UL)       /*!< DSTOCS0C (Bitfield-Mask: 0x01)                        */
42852  #define R_XSPI0_INTC_DSTOCS1C_Pos         (5UL)          /*!< DSTOCS1C (Bit 5)                                      */
42853  #define R_XSPI0_INTC_DSTOCS1C_Msk         (0x20UL)       /*!< DSTOCS1C (Bitfield-Mask: 0x01)                        */
42854  #define R_XSPI0_INTC_ECSCS0C_Pos          (8UL)          /*!< ECSCS0C (Bit 8)                                       */
42855  #define R_XSPI0_INTC_ECSCS0C_Msk          (0x100UL)      /*!< ECSCS0C (Bitfield-Mask: 0x01)                         */
42856  #define R_XSPI0_INTC_ECSCS1C_Pos          (9UL)          /*!< ECSCS1C (Bit 9)                                       */
42857  #define R_XSPI0_INTC_ECSCS1C_Msk          (0x200UL)      /*!< ECSCS1C (Bitfield-Mask: 0x01)                         */
42858  #define R_XSPI0_INTC_INTCS0C_Pos          (12UL)         /*!< INTCS0C (Bit 12)                                      */
42859  #define R_XSPI0_INTC_INTCS0C_Msk          (0x1000UL)     /*!< INTCS0C (Bitfield-Mask: 0x01)                         */
42860  #define R_XSPI0_INTC_INTCS1C_Pos          (13UL)         /*!< INTCS1C (Bit 13)                                      */
42861  #define R_XSPI0_INTC_INTCS1C_Msk          (0x2000UL)     /*!< INTCS1C (Bitfield-Mask: 0x01)                         */
42862  #define R_XSPI0_INTC_BRGOFC_Pos           (16UL)         /*!< BRGOFC (Bit 16)                                       */
42863  #define R_XSPI0_INTC_BRGOFC_Msk           (0x10000UL)    /*!< BRGOFC (Bitfield-Mask: 0x01)                          */
42864  #define R_XSPI0_INTC_BRGUFC_Pos           (18UL)         /*!< BRGUFC (Bit 18)                                       */
42865  #define R_XSPI0_INTC_BRGUFC_Msk           (0x40000UL)    /*!< BRGUFC (Bitfield-Mask: 0x01)                          */
42866  #define R_XSPI0_INTC_BUSERRC_Pos          (20UL)         /*!< BUSERRC (Bit 20)                                      */
42867  #define R_XSPI0_INTC_BUSERRC_Msk          (0x100000UL)   /*!< BUSERRC (Bitfield-Mask: 0x01)                         */
42868  #define R_XSPI0_INTC_CAFAILCS0C_Pos       (28UL)         /*!< CAFAILCS0C (Bit 28)                                   */
42869  #define R_XSPI0_INTC_CAFAILCS0C_Msk       (0x10000000UL) /*!< CAFAILCS0C (Bitfield-Mask: 0x01)                      */
42870  #define R_XSPI0_INTC_CAFAILCS1C_Pos       (29UL)         /*!< CAFAILCS1C (Bit 29)                                   */
42871  #define R_XSPI0_INTC_CAFAILCS1C_Msk       (0x20000000UL) /*!< CAFAILCS1C (Bitfield-Mask: 0x01)                      */
42872  #define R_XSPI0_INTC_CASUCCS0C_Pos        (30UL)         /*!< CASUCCS0C (Bit 30)                                    */
42873  #define R_XSPI0_INTC_CASUCCS0C_Msk        (0x40000000UL) /*!< CASUCCS0C (Bitfield-Mask: 0x01)                       */
42874  #define R_XSPI0_INTC_CASUCCS1C_Pos        (31UL)         /*!< CASUCCS1C (Bit 31)                                    */
42875  #define R_XSPI0_INTC_CASUCCS1C_Msk        (0x80000000UL) /*!< CASUCCS1C (Bitfield-Mask: 0x01)                       */
42876 /* =========================================================  INTE  ========================================================== */
42877  #define R_XSPI0_INTE_CMDCMPE_Pos          (0UL)          /*!< CMDCMPE (Bit 0)                                       */
42878  #define R_XSPI0_INTE_CMDCMPE_Msk          (0x1UL)        /*!< CMDCMPE (Bitfield-Mask: 0x01)                         */
42879  #define R_XSPI0_INTE_PATCMPE_Pos          (1UL)          /*!< PATCMPE (Bit 1)                                       */
42880  #define R_XSPI0_INTE_PATCMPE_Msk          (0x2UL)        /*!< PATCMPE (Bitfield-Mask: 0x01)                         */
42881  #define R_XSPI0_INTE_INICMPE_Pos          (2UL)          /*!< INICMPE (Bit 2)                                       */
42882  #define R_XSPI0_INTE_INICMPE_Msk          (0x4UL)        /*!< INICMPE (Bitfield-Mask: 0x01)                         */
42883  #define R_XSPI0_INTE_PERTOE_Pos           (3UL)          /*!< PERTOE (Bit 3)                                        */
42884  #define R_XSPI0_INTE_PERTOE_Msk           (0x8UL)        /*!< PERTOE (Bitfield-Mask: 0x01)                          */
42885  #define R_XSPI0_INTE_DSTOCS0E_Pos         (4UL)          /*!< DSTOCS0E (Bit 4)                                      */
42886  #define R_XSPI0_INTE_DSTOCS0E_Msk         (0x10UL)       /*!< DSTOCS0E (Bitfield-Mask: 0x01)                        */
42887  #define R_XSPI0_INTE_DSTOCS1E_Pos         (5UL)          /*!< DSTOCS1E (Bit 5)                                      */
42888  #define R_XSPI0_INTE_DSTOCS1E_Msk         (0x20UL)       /*!< DSTOCS1E (Bitfield-Mask: 0x01)                        */
42889  #define R_XSPI0_INTE_ECSCS0E_Pos          (8UL)          /*!< ECSCS0E (Bit 8)                                       */
42890  #define R_XSPI0_INTE_ECSCS0E_Msk          (0x100UL)      /*!< ECSCS0E (Bitfield-Mask: 0x01)                         */
42891  #define R_XSPI0_INTE_ECSCS1E_Pos          (9UL)          /*!< ECSCS1E (Bit 9)                                       */
42892  #define R_XSPI0_INTE_ECSCS1E_Msk          (0x200UL)      /*!< ECSCS1E (Bitfield-Mask: 0x01)                         */
42893  #define R_XSPI0_INTE_INTCS0E_Pos          (12UL)         /*!< INTCS0E (Bit 12)                                      */
42894  #define R_XSPI0_INTE_INTCS0E_Msk          (0x1000UL)     /*!< INTCS0E (Bitfield-Mask: 0x01)                         */
42895  #define R_XSPI0_INTE_INTCS1E_Pos          (13UL)         /*!< INTCS1E (Bit 13)                                      */
42896  #define R_XSPI0_INTE_INTCS1E_Msk          (0x2000UL)     /*!< INTCS1E (Bitfield-Mask: 0x01)                         */
42897  #define R_XSPI0_INTE_BRGOFE_Pos           (16UL)         /*!< BRGOFE (Bit 16)                                       */
42898  #define R_XSPI0_INTE_BRGOFE_Msk           (0x10000UL)    /*!< BRGOFE (Bitfield-Mask: 0x01)                          */
42899  #define R_XSPI0_INTE_BRGUFE_Pos           (18UL)         /*!< BRGUFE (Bit 18)                                       */
42900  #define R_XSPI0_INTE_BRGUFE_Msk           (0x40000UL)    /*!< BRGUFE (Bitfield-Mask: 0x01)                          */
42901  #define R_XSPI0_INTE_BUSERRE_Pos          (20UL)         /*!< BUSERRE (Bit 20)                                      */
42902  #define R_XSPI0_INTE_BUSERRE_Msk          (0x100000UL)   /*!< BUSERRE (Bitfield-Mask: 0x01)                         */
42903  #define R_XSPI0_INTE_CAFAILCS0E_Pos       (28UL)         /*!< CAFAILCS0E (Bit 28)                                   */
42904  #define R_XSPI0_INTE_CAFAILCS0E_Msk       (0x10000000UL) /*!< CAFAILCS0E (Bitfield-Mask: 0x01)                      */
42905  #define R_XSPI0_INTE_CAFAILCS1E_Pos       (29UL)         /*!< CAFAILCS1E (Bit 29)                                   */
42906  #define R_XSPI0_INTE_CAFAILCS1E_Msk       (0x20000000UL) /*!< CAFAILCS1E (Bitfield-Mask: 0x01)                      */
42907  #define R_XSPI0_INTE_CASUCCS0E_Pos        (30UL)         /*!< CASUCCS0E (Bit 30)                                    */
42908  #define R_XSPI0_INTE_CASUCCS0E_Msk        (0x40000000UL) /*!< CASUCCS0E (Bitfield-Mask: 0x01)                       */
42909  #define R_XSPI0_INTE_CASUCCS1E_Pos        (31UL)         /*!< CASUCCS1E (Bit 31)                                    */
42910  #define R_XSPI0_INTE_CASUCCS1E_Msk        (0x80000000UL) /*!< CASUCCS1E (Bitfield-Mask: 0x01)                       */
42911 
42912 /* =========================================================================================================================== */
42913 /* ================                                         R_MBXSEM                                          ================ */
42914 /* =========================================================================================================================== */
42915 
42916 /* ==========================================================  SEM  ========================================================== */
42917  #define R_MBXSEM_SEM_SEM_Pos                  (0UL)          /*!< SEM (Bit 0)                                           */
42918  #define R_MBXSEM_SEM_SEM_Msk                  (0x1UL)        /*!< SEM (Bitfield-Mask: 0x01)                             */
42919 /* ========================================================  SEMRCEN  ======================================================== */
42920  #define R_MBXSEM_SEMRCEN_SEMRCEN0_Pos         (0UL)          /*!< SEMRCEN0 (Bit 0)                                      */
42921  #define R_MBXSEM_SEMRCEN_SEMRCEN0_Msk         (0x1UL)        /*!< SEMRCEN0 (Bitfield-Mask: 0x01)                        */
42922  #define R_MBXSEM_SEMRCEN_SEMRCEN1_Pos         (1UL)          /*!< SEMRCEN1 (Bit 1)                                      */
42923  #define R_MBXSEM_SEMRCEN_SEMRCEN1_Msk         (0x2UL)        /*!< SEMRCEN1 (Bitfield-Mask: 0x01)                        */
42924  #define R_MBXSEM_SEMRCEN_SEMRCEN2_Pos         (2UL)          /*!< SEMRCEN2 (Bit 2)                                      */
42925  #define R_MBXSEM_SEMRCEN_SEMRCEN2_Msk         (0x4UL)        /*!< SEMRCEN2 (Bitfield-Mask: 0x01)                        */
42926  #define R_MBXSEM_SEMRCEN_SEMRCEN3_Pos         (3UL)          /*!< SEMRCEN3 (Bit 3)                                      */
42927  #define R_MBXSEM_SEMRCEN_SEMRCEN3_Msk         (0x8UL)        /*!< SEMRCEN3 (Bitfield-Mask: 0x01)                        */
42928  #define R_MBXSEM_SEMRCEN_SEMRCEN4_Pos         (4UL)          /*!< SEMRCEN4 (Bit 4)                                      */
42929  #define R_MBXSEM_SEMRCEN_SEMRCEN4_Msk         (0x10UL)       /*!< SEMRCEN4 (Bitfield-Mask: 0x01)                        */
42930  #define R_MBXSEM_SEMRCEN_SEMRCEN5_Pos         (5UL)          /*!< SEMRCEN5 (Bit 5)                                      */
42931  #define R_MBXSEM_SEMRCEN_SEMRCEN5_Msk         (0x20UL)       /*!< SEMRCEN5 (Bitfield-Mask: 0x01)                        */
42932  #define R_MBXSEM_SEMRCEN_SEMRCEN6_Pos         (6UL)          /*!< SEMRCEN6 (Bit 6)                                      */
42933  #define R_MBXSEM_SEMRCEN_SEMRCEN6_Msk         (0x40UL)       /*!< SEMRCEN6 (Bitfield-Mask: 0x01)                        */
42934  #define R_MBXSEM_SEMRCEN_SEMRCEN7_Pos         (7UL)          /*!< SEMRCEN7 (Bit 7)                                      */
42935  #define R_MBXSEM_SEMRCEN_SEMRCEN7_Msk         (0x80UL)       /*!< SEMRCEN7 (Bitfield-Mask: 0x01)                        */
42936 /* ========================================================  MBXH2C  ========================================================= */
42937  #define R_MBXSEM_MBXH2C_MBX_Pos               (0UL)          /*!< MBX (Bit 0)                                           */
42938  #define R_MBXSEM_MBXH2C_MBX_Msk               (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
42939 /* ======================================================  MBXISETH2C  ======================================================= */
42940  #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Pos     (0UL)          /*!< MBX_INT0S (Bit 0)                                     */
42941  #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Msk     (0x1UL)        /*!< MBX_INT0S (Bitfield-Mask: 0x01)                       */
42942  #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Pos     (1UL)          /*!< MBX_INT1S (Bit 1)                                     */
42943  #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Msk     (0x2UL)        /*!< MBX_INT1S (Bitfield-Mask: 0x01)                       */
42944  #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Pos     (2UL)          /*!< MBX_INT2S (Bit 2)                                     */
42945  #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Msk     (0x4UL)        /*!< MBX_INT2S (Bitfield-Mask: 0x01)                       */
42946  #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Pos     (3UL)          /*!< MBX_INT3S (Bit 3)                                     */
42947  #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Msk     (0x8UL)        /*!< MBX_INT3S (Bitfield-Mask: 0x01)                       */
42948 /* ======================================================  MBXICLRH2C  ======================================================= */
42949  #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Pos     (0UL)          /*!< MBX_INT0C (Bit 0)                                     */
42950  #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Msk     (0x1UL)        /*!< MBX_INT0C (Bitfield-Mask: 0x01)                       */
42951  #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Pos     (1UL)          /*!< MBX_INT1C (Bit 1)                                     */
42952  #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Msk     (0x2UL)        /*!< MBX_INT1C (Bitfield-Mask: 0x01)                       */
42953  #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Pos     (2UL)          /*!< MBX_INT2C (Bit 2)                                     */
42954  #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Msk     (0x4UL)        /*!< MBX_INT2C (Bitfield-Mask: 0x01)                       */
42955  #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Pos     (3UL)          /*!< MBX_INT3C (Bit 3)                                     */
42956  #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Msk     (0x8UL)        /*!< MBX_INT3C (Bitfield-Mask: 0x01)                       */
42957 /* ========================================================  MBXC2H  ========================================================= */
42958  #define R_MBXSEM_MBXC2H_MBX_Pos               (0UL)          /*!< MBX (Bit 0)                                           */
42959  #define R_MBXSEM_MBXC2H_MBX_Msk               (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff)                       */
42960 /* ======================================================  MBXISETC2H  ======================================================= */
42961  #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Pos    (0UL)          /*!< MBX_HINT0S (Bit 0)                                    */
42962  #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Msk    (0x1UL)        /*!< MBX_HINT0S (Bitfield-Mask: 0x01)                      */
42963  #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Pos    (1UL)          /*!< MBX_HINT1S (Bit 1)                                    */
42964  #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Msk    (0x2UL)        /*!< MBX_HINT1S (Bitfield-Mask: 0x01)                      */
42965  #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Pos    (2UL)          /*!< MBX_HINT2S (Bit 2)                                    */
42966  #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Msk    (0x4UL)        /*!< MBX_HINT2S (Bitfield-Mask: 0x01)                      */
42967  #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Pos    (3UL)          /*!< MBX_HINT3S (Bit 3)                                    */
42968  #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Msk    (0x8UL)        /*!< MBX_HINT3S (Bitfield-Mask: 0x01)                      */
42969 /* ======================================================  MBXICLRC2H  ======================================================= */
42970  #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Pos    (0UL)          /*!< MBX_HINT0C (Bit 0)                                    */
42971  #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Msk    (0x1UL)        /*!< MBX_HINT0C (Bitfield-Mask: 0x01)                      */
42972  #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Pos    (1UL)          /*!< MBX_HINT1C (Bit 1)                                    */
42973  #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Msk    (0x2UL)        /*!< MBX_HINT1C (Bitfield-Mask: 0x01)                      */
42974  #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Pos    (2UL)          /*!< MBX_HINT2C (Bit 2)                                    */
42975  #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Msk    (0x4UL)        /*!< MBX_HINT2C (Bitfield-Mask: 0x01)                      */
42976  #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Pos    (3UL)          /*!< MBX_HINT3C (Bit 3)                                    */
42977  #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Msk    (0x8UL)        /*!< MBX_HINT3C (Bitfield-Mask: 0x01)                      */
42978 
42979 /* =========================================================================================================================== */
42980 /* ================                                         R_SHOSTIF                                         ================ */
42981 /* =========================================================================================================================== */
42982 
42983 /* ========================================================  CTRLR0  ========================================================= */
42984  #define R_SHOSTIF_CTRLR0_SCPH_Pos        (8UL)     /*!< SCPH (Bit 8)                                          */
42985  #define R_SHOSTIF_CTRLR0_SCPH_Msk        (0x100UL) /*!< SCPH (Bitfield-Mask: 0x01)                            */
42986  #define R_SHOSTIF_CTRLR0_SCPOL_Pos       (9UL)     /*!< SCPOL (Bit 9)                                         */
42987  #define R_SHOSTIF_CTRLR0_SCPOL_Msk       (0x200UL) /*!< SCPOL (Bitfield-Mask: 0x01)                           */
42988 /* ==========================================================  ENR  ========================================================== */
42989  #define R_SHOSTIF_ENR_ENABLE_Pos         (0UL)     /*!< ENABLE (Bit 0)                                        */
42990  #define R_SHOSTIF_ENR_ENABLE_Msk         (0x1UL)   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
42991 /* ========================================================  RXFBTR  ========================================================= */
42992  #define R_SHOSTIF_RXFBTR_RXFBTL_Pos      (0UL)     /*!< RXFBTL (Bit 0)                                        */
42993  #define R_SHOSTIF_RXFBTR_RXFBTL_Msk      (0x3fUL)  /*!< RXFBTL (Bitfield-Mask: 0x3f)                          */
42994 /* ========================================================  TXFTLR  ========================================================= */
42995  #define R_SHOSTIF_TXFTLR_TFT_Pos         (0UL)     /*!< TFT (Bit 0)                                           */
42996  #define R_SHOSTIF_TXFTLR_TFT_Msk         (0x3fUL)  /*!< TFT (Bitfield-Mask: 0x3f)                             */
42997 /* ========================================================  RXFTLR  ========================================================= */
42998  #define R_SHOSTIF_RXFTLR_RFT_Pos         (0UL)     /*!< RFT (Bit 0)                                           */
42999  #define R_SHOSTIF_RXFTLR_RFT_Msk         (0x3fUL)  /*!< RFT (Bitfield-Mask: 0x3f)                             */
43000 /* ==========================================================  SR  =========================================================== */
43001  #define R_SHOSTIF_SR_BUSY_Pos            (0UL)     /*!< BUSY (Bit 0)                                          */
43002  #define R_SHOSTIF_SR_BUSY_Msk            (0x1UL)   /*!< BUSY (Bitfield-Mask: 0x01)                            */
43003 /* ==========================================================  IMR  ========================================================== */
43004  #define R_SHOSTIF_IMR_TXEIM_Pos          (0UL)     /*!< TXEIM (Bit 0)                                         */
43005  #define R_SHOSTIF_IMR_TXEIM_Msk          (0x1UL)   /*!< TXEIM (Bitfield-Mask: 0x01)                           */
43006  #define R_SHOSTIF_IMR_RXOIM_Pos          (3UL)     /*!< RXOIM (Bit 3)                                         */
43007  #define R_SHOSTIF_IMR_RXOIM_Msk          (0x8UL)   /*!< RXOIM (Bitfield-Mask: 0x01)                           */
43008  #define R_SHOSTIF_IMR_RXFIM_Pos          (4UL)     /*!< RXFIM (Bit 4)                                         */
43009  #define R_SHOSTIF_IMR_RXFIM_Msk          (0x10UL)  /*!< RXFIM (Bitfield-Mask: 0x01)                           */
43010  #define R_SHOSTIF_IMR_TXUIM_Pos          (7UL)     /*!< TXUIM (Bit 7)                                         */
43011  #define R_SHOSTIF_IMR_TXUIM_Msk          (0x80UL)  /*!< TXUIM (Bitfield-Mask: 0x01)                           */
43012  #define R_SHOSTIF_IMR_AHBEM_Pos          (8UL)     /*!< AHBEM (Bit 8)                                         */
43013  #define R_SHOSTIF_IMR_AHBEM_Msk          (0x100UL) /*!< AHBEM (Bitfield-Mask: 0x01)                           */
43014  #define R_SHOSTIF_IMR_SPIMEM_Pos         (9UL)     /*!< SPIMEM (Bit 9)                                        */
43015  #define R_SHOSTIF_IMR_SPIMEM_Msk         (0x200UL) /*!< SPIMEM (Bitfield-Mask: 0x01)                          */
43016 /* ==========================================================  ISR  ========================================================== */
43017  #define R_SHOSTIF_ISR_TXEIS_Pos          (0UL)     /*!< TXEIS (Bit 0)                                         */
43018  #define R_SHOSTIF_ISR_TXEIS_Msk          (0x1UL)   /*!< TXEIS (Bitfield-Mask: 0x01)                           */
43019  #define R_SHOSTIF_ISR_RXOIS_Pos          (3UL)     /*!< RXOIS (Bit 3)                                         */
43020  #define R_SHOSTIF_ISR_RXOIS_Msk          (0x8UL)   /*!< RXOIS (Bitfield-Mask: 0x01)                           */
43021  #define R_SHOSTIF_ISR_RXFIS_Pos          (4UL)     /*!< RXFIS (Bit 4)                                         */
43022  #define R_SHOSTIF_ISR_RXFIS_Msk          (0x10UL)  /*!< RXFIS (Bitfield-Mask: 0x01)                           */
43023  #define R_SHOSTIF_ISR_TXUIS_Pos          (7UL)     /*!< TXUIS (Bit 7)                                         */
43024  #define R_SHOSTIF_ISR_TXUIS_Msk          (0x80UL)  /*!< TXUIS (Bitfield-Mask: 0x01)                           */
43025  #define R_SHOSTIF_ISR_AHBES_Pos          (8UL)     /*!< AHBES (Bit 8)                                         */
43026  #define R_SHOSTIF_ISR_AHBES_Msk          (0x100UL) /*!< AHBES (Bitfield-Mask: 0x01)                           */
43027  #define R_SHOSTIF_ISR_SPIMES_Pos         (9UL)     /*!< SPIMES (Bit 9)                                        */
43028  #define R_SHOSTIF_ISR_SPIMES_Msk         (0x200UL) /*!< SPIMES (Bitfield-Mask: 0x01)                          */
43029 /* =========================================================  RISR  ========================================================== */
43030  #define R_SHOSTIF_RISR_TXEIR_Pos         (0UL)     /*!< TXEIR (Bit 0)                                         */
43031  #define R_SHOSTIF_RISR_TXEIR_Msk         (0x1UL)   /*!< TXEIR (Bitfield-Mask: 0x01)                           */
43032  #define R_SHOSTIF_RISR_RXOIR_Pos         (3UL)     /*!< RXOIR (Bit 3)                                         */
43033  #define R_SHOSTIF_RISR_RXOIR_Msk         (0x8UL)   /*!< RXOIR (Bitfield-Mask: 0x01)                           */
43034  #define R_SHOSTIF_RISR_RXFIR_Pos         (4UL)     /*!< RXFIR (Bit 4)                                         */
43035  #define R_SHOSTIF_RISR_RXFIR_Msk         (0x10UL)  /*!< RXFIR (Bitfield-Mask: 0x01)                           */
43036  #define R_SHOSTIF_RISR_TXUIR_Pos         (7UL)     /*!< TXUIR (Bit 7)                                         */
43037  #define R_SHOSTIF_RISR_TXUIR_Msk         (0x80UL)  /*!< TXUIR (Bitfield-Mask: 0x01)                           */
43038  #define R_SHOSTIF_RISR_AHBER_Pos         (8UL)     /*!< AHBER (Bit 8)                                         */
43039  #define R_SHOSTIF_RISR_AHBER_Msk         (0x100UL) /*!< AHBER (Bitfield-Mask: 0x01)                           */
43040  #define R_SHOSTIF_RISR_SPIMER_Pos        (9UL)     /*!< SPIMER (Bit 9)                                        */
43041  #define R_SHOSTIF_RISR_SPIMER_Msk        (0x200UL) /*!< SPIMER (Bitfield-Mask: 0x01)                          */
43042 /* ========================================================  TXUICR  ========================================================= */
43043  #define R_SHOSTIF_TXUICR_TXUICR_Pos      (0UL)     /*!< TXUICR (Bit 0)                                        */
43044  #define R_SHOSTIF_TXUICR_TXUICR_Msk      (0x1UL)   /*!< TXUICR (Bitfield-Mask: 0x01)                          */
43045 /* ========================================================  RXOICR  ========================================================= */
43046  #define R_SHOSTIF_RXOICR_RXOICR_Pos      (0UL)     /*!< RXOICR (Bit 0)                                        */
43047  #define R_SHOSTIF_RXOICR_RXOICR_Msk      (0x1UL)   /*!< RXOICR (Bitfield-Mask: 0x01)                          */
43048 /* ========================================================  SPIMECR  ======================================================== */
43049  #define R_SHOSTIF_SPIMECR_SPIMECR_Pos    (0UL)     /*!< SPIMECR (Bit 0)                                       */
43050  #define R_SHOSTIF_SPIMECR_SPIMECR_Msk    (0x1UL)   /*!< SPIMECR (Bitfield-Mask: 0x01)                         */
43051 /* ========================================================  AHBECR  ========================================================= */
43052  #define R_SHOSTIF_AHBECR_AHBECR_Pos      (0UL)     /*!< AHBECR (Bit 0)                                        */
43053  #define R_SHOSTIF_AHBECR_AHBECR_Msk      (0x1UL)   /*!< AHBECR (Bitfield-Mask: 0x01)                          */
43054 /* ==========================================================  ICR  ========================================================== */
43055  #define R_SHOSTIF_ICR_ICR_Pos            (0UL)     /*!< ICR (Bit 0)                                           */
43056  #define R_SHOSTIF_ICR_ICR_Msk            (0x1UL)   /*!< ICR (Bitfield-Mask: 0x01)                             */
43057 
43058 /* =========================================================================================================================== */
43059 /* ================                                         R_PHOSTIF                                         ================ */
43060 /* =========================================================================================================================== */
43061 
43062 /* ========================================================  HIFBCC  ========================================================= */
43063  #define R_PHOSTIF_HIFBCC_RBUFON0_Pos     (0UL)          /*!< RBUFON0 (Bit 0)                                       */
43064  #define R_PHOSTIF_HIFBCC_RBUFON0_Msk     (0x1UL)        /*!< RBUFON0 (Bitfield-Mask: 0x01)                         */
43065  #define R_PHOSTIF_HIFBCC_RBUFON1_Pos     (1UL)          /*!< RBUFON1 (Bit 1)                                       */
43066  #define R_PHOSTIF_HIFBCC_RBUFON1_Msk     (0x2UL)        /*!< RBUFON1 (Bitfield-Mask: 0x01)                         */
43067  #define R_PHOSTIF_HIFBCC_RBUFON2_Pos     (2UL)          /*!< RBUFON2 (Bit 2)                                       */
43068  #define R_PHOSTIF_HIFBCC_RBUFON2_Msk     (0x4UL)        /*!< RBUFON2 (Bitfield-Mask: 0x01)                         */
43069  #define R_PHOSTIF_HIFBCC_RBUFON3_Pos     (3UL)          /*!< RBUFON3 (Bit 3)                                       */
43070  #define R_PHOSTIF_HIFBCC_RBUFON3_Msk     (0x8UL)        /*!< RBUFON3 (Bitfield-Mask: 0x01)                         */
43071  #define R_PHOSTIF_HIFBCC_RBUFON4_Pos     (4UL)          /*!< RBUFON4 (Bit 4)                                       */
43072  #define R_PHOSTIF_HIFBCC_RBUFON4_Msk     (0x10UL)       /*!< RBUFON4 (Bitfield-Mask: 0x01)                         */
43073  #define R_PHOSTIF_HIFBCC_RBUFON5_Pos     (5UL)          /*!< RBUFON5 (Bit 5)                                       */
43074  #define R_PHOSTIF_HIFBCC_RBUFON5_Msk     (0x20UL)       /*!< RBUFON5 (Bitfield-Mask: 0x01)                         */
43075  #define R_PHOSTIF_HIFBCC_RBUFONX_Pos     (8UL)          /*!< RBUFONX (Bit 8)                                       */
43076  #define R_PHOSTIF_HIFBCC_RBUFONX_Msk     (0x100UL)      /*!< RBUFONX (Bitfield-Mask: 0x01)                         */
43077  #define R_PHOSTIF_HIFBCC_BSTON_Pos       (12UL)         /*!< BSTON (Bit 12)                                        */
43078  #define R_PHOSTIF_HIFBCC_BSTON_Msk       (0x1000UL)     /*!< BSTON (Bitfield-Mask: 0x01)                           */
43079  #define R_PHOSTIF_HIFBCC_WRPON_Pos       (13UL)         /*!< WRPON (Bit 13)                                        */
43080  #define R_PHOSTIF_HIFBCC_WRPON_Msk       (0x2000UL)     /*!< WRPON (Bitfield-Mask: 0x01)                           */
43081 /* ========================================================  HIFBTC  ========================================================= */
43082  #define R_PHOSTIF_HIFBTC_WRSTD_Pos       (0UL)          /*!< WRSTD (Bit 0)                                         */
43083  #define R_PHOSTIF_HIFBTC_WRSTD_Msk       (0x7UL)        /*!< WRSTD (Bitfield-Mask: 0x07)                           */
43084  #define R_PHOSTIF_HIFBTC_RDSTD_Pos       (4UL)          /*!< RDSTD (Bit 4)                                         */
43085  #define R_PHOSTIF_HIFBTC_RDSTD_Msk       (0x30UL)       /*!< RDSTD (Bitfield-Mask: 0x03)                           */
43086  #define R_PHOSTIF_HIFBTC_PASTD_Pos       (8UL)          /*!< PASTD (Bit 8)                                         */
43087  #define R_PHOSTIF_HIFBTC_PASTD_Msk       (0x700UL)      /*!< PASTD (Bitfield-Mask: 0x07)                           */
43088  #define R_PHOSTIF_HIFBTC_RDDTS_Pos       (12UL)         /*!< RDDTS (Bit 12)                                        */
43089  #define R_PHOSTIF_HIFBTC_RDDTS_Msk       (0x3000UL)     /*!< RDDTS (Bitfield-Mask: 0x03)                           */
43090 /* ========================================================  HIFPRC  ========================================================= */
43091  #define R_PHOSTIF_HIFPRC_PAGEON0_Pos     (0UL)          /*!< PAGEON0 (Bit 0)                                       */
43092  #define R_PHOSTIF_HIFPRC_PAGEON0_Msk     (0x1UL)        /*!< PAGEON0 (Bitfield-Mask: 0x01)                         */
43093  #define R_PHOSTIF_HIFPRC_PAGEON1_Pos     (1UL)          /*!< PAGEON1 (Bit 1)                                       */
43094  #define R_PHOSTIF_HIFPRC_PAGEON1_Msk     (0x2UL)        /*!< PAGEON1 (Bitfield-Mask: 0x01)                         */
43095  #define R_PHOSTIF_HIFPRC_PAGEON2_Pos     (2UL)          /*!< PAGEON2 (Bit 2)                                       */
43096  #define R_PHOSTIF_HIFPRC_PAGEON2_Msk     (0x4UL)        /*!< PAGEON2 (Bitfield-Mask: 0x01)                         */
43097  #define R_PHOSTIF_HIFPRC_PAGEON3_Pos     (3UL)          /*!< PAGEON3 (Bit 3)                                       */
43098  #define R_PHOSTIF_HIFPRC_PAGEON3_Msk     (0x8UL)        /*!< PAGEON3 (Bitfield-Mask: 0x01)                         */
43099  #define R_PHOSTIF_HIFPRC_PAGEON4_Pos     (4UL)          /*!< PAGEON4 (Bit 4)                                       */
43100  #define R_PHOSTIF_HIFPRC_PAGEON4_Msk     (0x10UL)       /*!< PAGEON4 (Bitfield-Mask: 0x01)                         */
43101  #define R_PHOSTIF_HIFPRC_PAGEON5_Pos     (5UL)          /*!< PAGEON5 (Bit 5)                                       */
43102  #define R_PHOSTIF_HIFPRC_PAGEON5_Msk     (0x20UL)       /*!< PAGEON5 (Bitfield-Mask: 0x01)                         */
43103  #define R_PHOSTIF_HIFPRC_PAGEONX_Pos     (8UL)          /*!< PAGEONX (Bit 8)                                       */
43104  #define R_PHOSTIF_HIFPRC_PAGEONX_Msk     (0x100UL)      /*!< PAGEONX (Bitfield-Mask: 0x01)                         */
43105  #define R_PHOSTIF_HIFPRC_PAGESZ_Pos      (12UL)         /*!< PAGESZ (Bit 12)                                       */
43106  #define R_PHOSTIF_HIFPRC_PAGESZ_Msk      (0x1000UL)     /*!< PAGESZ (Bitfield-Mask: 0x01)                          */
43107 /* ========================================================  HIFIRC  ========================================================= */
43108  #define R_PHOSTIF_HIFIRC_ERRRSP_Pos      (0UL)          /*!< ERRRSP (Bit 0)                                        */
43109  #define R_PHOSTIF_HIFIRC_ERRRSP_Msk      (0x1UL)        /*!< ERRRSP (Bitfield-Mask: 0x01)                          */
43110 /* ========================================================  HIFECR0  ======================================================== */
43111  #define R_PHOSTIF_HIFECR0_ERRADDR_Pos    (0UL)          /*!< ERRADDR (Bit 0)                                       */
43112  #define R_PHOSTIF_HIFECR0_ERRADDR_Msk    (0xffffffffUL) /*!< ERRADDR (Bitfield-Mask: 0xffffffff)                   */
43113 /* ========================================================  HIFECR1  ======================================================== */
43114  #define R_PHOSTIF_HIFECR1_ERRSZ_Pos      (0UL)          /*!< ERRSZ (Bit 0)                                         */
43115  #define R_PHOSTIF_HIFECR1_ERRSZ_Msk      (0x7UL)        /*!< ERRSZ (Bitfield-Mask: 0x07)                           */
43116  #define R_PHOSTIF_HIFECR1_ERRWR_Pos      (3UL)          /*!< ERRWR (Bit 3)                                         */
43117  #define R_PHOSTIF_HIFECR1_ERRWR_Msk      (0x8UL)        /*!< ERRWR (Bitfield-Mask: 0x01)                           */
43118 /* ========================================================  HIFMON1  ======================================================== */
43119  #define R_PHOSTIF_HIFMON1_HIFRDY_Pos     (0UL)          /*!< HIFRDY (Bit 0)                                        */
43120  #define R_PHOSTIF_HIFMON1_HIFRDY_Msk     (0x1UL)        /*!< HIFRDY (Bitfield-Mask: 0x01)                          */
43121  #define R_PHOSTIF_HIFMON1_BUSSEL_Pos     (1UL)          /*!< BUSSEL (Bit 1)                                        */
43122  #define R_PHOSTIF_HIFMON1_BUSSEL_Msk     (0x2UL)        /*!< BUSSEL (Bitfield-Mask: 0x01)                          */
43123  #define R_PHOSTIF_HIFMON1_HIFSYNC_Pos    (3UL)          /*!< HIFSYNC (Bit 3)                                       */
43124  #define R_PHOSTIF_HIFMON1_HIFSYNC_Msk    (0x8UL)        /*!< HIFSYNC (Bitfield-Mask: 0x01)                         */
43125 /* ========================================================  HIFMON2  ======================================================== */
43126  #define R_PHOSTIF_HIFMON2_HIFBCC_Pos     (0UL)          /*!< HIFBCC (Bit 0)                                        */
43127  #define R_PHOSTIF_HIFMON2_HIFBCC_Msk     (0x1UL)        /*!< HIFBCC (Bitfield-Mask: 0x01)                          */
43128  #define R_PHOSTIF_HIFMON2_HIFBTC_Pos     (1UL)          /*!< HIFBTC (Bit 1)                                        */
43129  #define R_PHOSTIF_HIFMON2_HIFBTC_Msk     (0x2UL)        /*!< HIFBTC (Bitfield-Mask: 0x01)                          */
43130  #define R_PHOSTIF_HIFMON2_HIFPRC_Pos     (2UL)          /*!< HIFPRC (Bit 2)                                        */
43131  #define R_PHOSTIF_HIFMON2_HIFPRC_Msk     (0x4UL)        /*!< HIFPRC (Bitfield-Mask: 0x01)                          */
43132  #define R_PHOSTIF_HIFMON2_HIFIRC_Pos     (3UL)          /*!< HIFIRC (Bit 3)                                        */
43133  #define R_PHOSTIF_HIFMON2_HIFIRC_Msk     (0x8UL)        /*!< HIFIRC (Bitfield-Mask: 0x01)                          */
43134  #define R_PHOSTIF_HIFMON2_HIFXAL_Pos     (4UL)          /*!< HIFXAL (Bit 4)                                        */
43135  #define R_PHOSTIF_HIFMON2_HIFXAL_Msk     (0x10UL)       /*!< HIFXAL (Bitfield-Mask: 0x01)                          */
43136  #define R_PHOSTIF_HIFMON2_HIFXAH_Pos     (5UL)          /*!< HIFXAH (Bit 5)                                        */
43137  #define R_PHOSTIF_HIFMON2_HIFXAH_Msk     (0x20UL)       /*!< HIFXAH (Bitfield-Mask: 0x01)                          */
43138 /* ========================================================  HIFMON3  ======================================================== */
43139  #define R_PHOSTIF_HIFMON3_HIFEXT0_Pos    (0UL)          /*!< HIFEXT0 (Bit 0)                                       */
43140  #define R_PHOSTIF_HIFMON3_HIFEXT0_Msk    (0x1UL)        /*!< HIFEXT0 (Bitfield-Mask: 0x01)                         */
43141  #define R_PHOSTIF_HIFMON3_HIFEXT1_Pos    (1UL)          /*!< HIFEXT1 (Bit 1)                                       */
43142  #define R_PHOSTIF_HIFMON3_HIFEXT1_Msk    (0x2UL)        /*!< HIFEXT1 (Bitfield-Mask: 0x01)                         */
43143 /* ========================================================  HIFXAL  ========================================================= */
43144  #define R_PHOSTIF_HIFXAL_XADDRL_Pos      (0UL)          /*!< XADDRL (Bit 0)                                        */
43145  #define R_PHOSTIF_HIFXAL_XADDRL_Msk      (0x1ffUL)      /*!< XADDRL (Bitfield-Mask: 0x1ff)                         */
43146 /* ========================================================  HIFXAH  ========================================================= */
43147  #define R_PHOSTIF_HIFXAH_XADDRH_Pos      (0UL)          /*!< XADDRH (Bit 0)                                        */
43148  #define R_PHOSTIF_HIFXAH_XADDRH_Msk      (0x1ffUL)      /*!< XADDRH (Bitfield-Mask: 0x1ff)                         */
43149 /* ========================================================  HIFEXT0  ======================================================== */
43150  #define R_PHOSTIF_HIFEXT0_KESSBI_Pos     (0UL)          /*!< KESSBI (Bit 0)                                        */
43151  #define R_PHOSTIF_HIFEXT0_KESSBI_Msk     (0x1UL)        /*!< KESSBI (Bitfield-Mask: 0x01)                          */
43152  #define R_PHOSTIF_HIFEXT0_KESDTI_Pos     (2UL)          /*!< KESDTI (Bit 2)                                        */
43153  #define R_PHOSTIF_HIFEXT0_KESDTI_Msk     (0x4UL)        /*!< KESDTI (Bitfield-Mask: 0x01)                          */
43154  #define R_PHOSTIF_HIFEXT0_KESAVI_Pos     (3UL)          /*!< KESAVI (Bit 3)                                        */
43155  #define R_PHOSTIF_HIFEXT0_KESAVI_Msk     (0x8UL)        /*!< KESAVI (Bitfield-Mask: 0x01)                          */
43156  #define R_PHOSTIF_HIFEXT0_KESDTO_Pos     (4UL)          /*!< KESDTO (Bit 4)                                        */
43157  #define R_PHOSTIF_HIFEXT0_KESDTO_Msk     (0x10UL)       /*!< KESDTO (Bitfield-Mask: 0x01)                          */
43158  #define R_PHOSTIF_HIFEXT0_KESWTO_Pos     (5UL)          /*!< KESWTO (Bit 5)                                        */
43159  #define R_PHOSTIF_HIFEXT0_KESWTO_Msk     (0x20UL)       /*!< KESWTO (Bitfield-Mask: 0x01)                          */
43160  #define R_PHOSTIF_HIFEXT0_CNDWEO_Pos     (9UL)          /*!< CNDWEO (Bit 9)                                        */
43161  #define R_PHOSTIF_HIFEXT0_CNDWEO_Msk     (0x200UL)      /*!< CNDWEO (Bitfield-Mask: 0x01)                          */
43162  #define R_PHOSTIF_HIFEXT0_MODTRN_Pos     (15UL)         /*!< MODTRN (Bit 15)                                       */
43163  #define R_PHOSTIF_HIFEXT0_MODTRN_Msk     (0x8000UL)     /*!< MODTRN (Bitfield-Mask: 0x01)                          */
43164 /* ========================================================  HIFEXT1  ======================================================== */
43165  #define R_PHOSTIF_HIFEXT1_DLYWA_Pos      (0UL)          /*!< DLYWA (Bit 0)                                         */
43166  #define R_PHOSTIF_HIFEXT1_DLYWA_Msk      (0xfUL)        /*!< DLYWA (Bitfield-Mask: 0x0f)                           */
43167  #define R_PHOSTIF_HIFEXT1_DLYRA_Pos      (8UL)          /*!< DLYRA (Bit 8)                                         */
43168  #define R_PHOSTIF_HIFEXT1_DLYRA_Msk      (0xf00UL)      /*!< DLYRA (Bitfield-Mask: 0x0f)                           */
43169 
43170 /* =========================================================================================================================== */
43171 /* ================                                         R_SYSC_NS                                         ================ */
43172 /* =========================================================================================================================== */
43173 
43174 /* =========================================================  SCKCR  ========================================================= */
43175  #define R_SYSC_NS_SCKCR_FSELXSPI0_Pos       (0UL)          /*!< FSELXSPI0 (Bit 0)                                     */
43176  #define R_SYSC_NS_SCKCR_FSELXSPI0_Msk       (0x7UL)        /*!< FSELXSPI0 (Bitfield-Mask: 0x07)                       */
43177  #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Pos     (6UL)          /*!< DIVSELXSPI0 (Bit 6)                                   */
43178  #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Msk     (0x40UL)       /*!< DIVSELXSPI0 (Bitfield-Mask: 0x01)                     */
43179  #define R_SYSC_NS_SCKCR_FSELXSPI1_Pos       (8UL)          /*!< FSELXSPI1 (Bit 8)                                     */
43180  #define R_SYSC_NS_SCKCR_FSELXSPI1_Msk       (0x700UL)      /*!< FSELXSPI1 (Bitfield-Mask: 0x07)                       */
43181  #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Pos     (14UL)         /*!< DIVSELXSPI1 (Bit 14)                                  */
43182  #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Msk     (0x4000UL)     /*!< DIVSELXSPI1 (Bitfield-Mask: 0x01)                     */
43183  #define R_SYSC_NS_SCKCR_CKIO_Pos            (16UL)         /*!< CKIO (Bit 16)                                         */
43184  #define R_SYSC_NS_SCKCR_CKIO_Msk            (0x70000UL)    /*!< CKIO (Bitfield-Mask: 0x07)                            */
43185  #define R_SYSC_NS_SCKCR_FSELCANFD_Pos       (20UL)         /*!< FSELCANFD (Bit 20)                                    */
43186  #define R_SYSC_NS_SCKCR_FSELCANFD_Msk       (0x100000UL)   /*!< FSELCANFD (Bitfield-Mask: 0x01)                       */
43187  #define R_SYSC_NS_SCKCR_PHYSEL_Pos          (21UL)         /*!< PHYSEL (Bit 21)                                       */
43188  #define R_SYSC_NS_SCKCR_PHYSEL_Msk          (0x200000UL)   /*!< PHYSEL (Bitfield-Mask: 0x01)                          */
43189  #define R_SYSC_NS_SCKCR_CLMASEL_Pos         (22UL)         /*!< CLMASEL (Bit 22)                                      */
43190  #define R_SYSC_NS_SCKCR_CLMASEL_Msk         (0x400000UL)   /*!< CLMASEL (Bitfield-Mask: 0x01)                         */
43191  #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Pos    (24UL)         /*!< SPI0ASYNCSEL (Bit 24)                                 */
43192  #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Msk    (0x1000000UL)  /*!< SPI0ASYNCSEL (Bitfield-Mask: 0x01)                    */
43193  #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Pos    (25UL)         /*!< SPI1ASYNCSEL (Bit 25)                                 */
43194  #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Msk    (0x2000000UL)  /*!< SPI1ASYNCSEL (Bitfield-Mask: 0x01)                    */
43195  #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Pos    (26UL)         /*!< SPI2ASYNCSEL (Bit 26)                                 */
43196  #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Msk    (0x4000000UL)  /*!< SPI2ASYNCSEL (Bitfield-Mask: 0x01)                    */
43197  #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Pos    (27UL)         /*!< SCI0ASYNCSEL (Bit 27)                                 */
43198  #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Msk    (0x8000000UL)  /*!< SCI0ASYNCSEL (Bitfield-Mask: 0x01)                    */
43199  #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Pos    (28UL)         /*!< SCI1ASYNCSEL (Bit 28)                                 */
43200  #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Msk    (0x10000000UL) /*!< SCI1ASYNCSEL (Bitfield-Mask: 0x01)                    */
43201  #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Pos    (29UL)         /*!< SCI2ASYNCSEL (Bit 29)                                 */
43202  #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Msk    (0x20000000UL) /*!< SCI2ASYNCSEL (Bitfield-Mask: 0x01)                    */
43203  #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Pos    (30UL)         /*!< SCI3ASYNCSEL (Bit 30)                                 */
43204  #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Msk    (0x40000000UL) /*!< SCI3ASYNCSEL (Bitfield-Mask: 0x01)                    */
43205  #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Pos    (31UL)         /*!< SCI4ASYNCSEL (Bit 31)                                 */
43206  #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Msk    (0x80000000UL) /*!< SCI4ASYNCSEL (Bitfield-Mask: 0x01)                    */
43207 /* ========================================================  RSTSR0  ========================================================= */
43208  #define R_SYSC_NS_RSTSR0_TRF_Pos            (1UL)          /*!< TRF (Bit 1)                                           */
43209  #define R_SYSC_NS_RSTSR0_TRF_Msk            (0x2UL)        /*!< TRF (Bitfield-Mask: 0x01)                             */
43210  #define R_SYSC_NS_RSTSR0_ERRF_Pos           (2UL)          /*!< ERRF (Bit 2)                                          */
43211  #define R_SYSC_NS_RSTSR0_ERRF_Msk           (0x4UL)        /*!< ERRF (Bitfield-Mask: 0x01)                            */
43212  #define R_SYSC_NS_RSTSR0_SWRSF_Pos          (3UL)          /*!< SWRSF (Bit 3)                                         */
43213  #define R_SYSC_NS_RSTSR0_SWRSF_Msk          (0x8UL)        /*!< SWRSF (Bitfield-Mask: 0x01)                           */
43214  #define R_SYSC_NS_RSTSR0_SWR0F_Pos          (4UL)          /*!< SWR0F (Bit 4)                                         */
43215  #define R_SYSC_NS_RSTSR0_SWR0F_Msk          (0x10UL)       /*!< SWR0F (Bitfield-Mask: 0x01)                           */
43216 /* ========================================================  MRCTLA  ========================================================= */
43217  #define R_SYSC_NS_MRCTLA_MRCTLA04_Pos       (4UL)          /*!< MRCTLA04 (Bit 4)                                      */
43218  #define R_SYSC_NS_MRCTLA_MRCTLA04_Msk       (0x10UL)       /*!< MRCTLA04 (Bitfield-Mask: 0x01)                        */
43219  #define R_SYSC_NS_MRCTLA_MRCTLA05_Pos       (5UL)          /*!< MRCTLA05 (Bit 5)                                      */
43220  #define R_SYSC_NS_MRCTLA_MRCTLA05_Msk       (0x20UL)       /*!< MRCTLA05 (Bitfield-Mask: 0x01)                        */
43221 /* ========================================================  MRCTLE  ========================================================= */
43222  #define R_SYSC_NS_MRCTLE_MRCTLE00_Pos       (0UL)          /*!< MRCTLE00 (Bit 0)                                      */
43223  #define R_SYSC_NS_MRCTLE_MRCTLE00_Msk       (0x1UL)        /*!< MRCTLE00 (Bitfield-Mask: 0x01)                        */
43224  #define R_SYSC_NS_MRCTLE_MRCTLE01_Pos       (1UL)          /*!< MRCTLE01 (Bit 1)                                      */
43225  #define R_SYSC_NS_MRCTLE_MRCTLE01_Msk       (0x2UL)        /*!< MRCTLE01 (Bitfield-Mask: 0x01)                        */
43226  #define R_SYSC_NS_MRCTLE_MRCTLE02_Pos       (2UL)          /*!< MRCTLE02 (Bit 2)                                      */
43227  #define R_SYSC_NS_MRCTLE_MRCTLE02_Msk       (0x4UL)        /*!< MRCTLE02 (Bitfield-Mask: 0x01)                        */
43228  #define R_SYSC_NS_MRCTLE_MRCTLE03_Pos       (3UL)          /*!< MRCTLE03 (Bit 3)                                      */
43229  #define R_SYSC_NS_MRCTLE_MRCTLE03_Msk       (0x8UL)        /*!< MRCTLE03 (Bitfield-Mask: 0x01)                        */
43230  #define R_SYSC_NS_MRCTLE_MRCTLE04_Pos       (4UL)          /*!< MRCTLE04 (Bit 4)                                      */
43231  #define R_SYSC_NS_MRCTLE_MRCTLE04_Msk       (0x10UL)       /*!< MRCTLE04 (Bitfield-Mask: 0x01)                        */
43232  #define R_SYSC_NS_MRCTLE_MRCTLE05_Pos       (5UL)          /*!< MRCTLE05 (Bit 5)                                      */
43233  #define R_SYSC_NS_MRCTLE_MRCTLE05_Msk       (0x20UL)       /*!< MRCTLE05 (Bitfield-Mask: 0x01)                        */
43234  #define R_SYSC_NS_MRCTLE_MRCTLE06_Pos       (6UL)          /*!< MRCTLE06 (Bit 6)                                      */
43235  #define R_SYSC_NS_MRCTLE_MRCTLE06_Msk       (0x40UL)       /*!< MRCTLE06 (Bitfield-Mask: 0x01)                        */
43236 /* ========================================================  MSTPCRA  ======================================================== */
43237  #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Pos     (0UL)          /*!< MSTPCRA00 (Bit 0)                                     */
43238  #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Msk     (0x1UL)        /*!< MSTPCRA00 (Bitfield-Mask: 0x01)                       */
43239  #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Pos     (4UL)          /*!< MSTPCRA04 (Bit 4)                                     */
43240  #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Msk     (0x10UL)       /*!< MSTPCRA04 (Bitfield-Mask: 0x01)                       */
43241  #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Pos     (5UL)          /*!< MSTPCRA05 (Bit 5)                                     */
43242  #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Msk     (0x20UL)       /*!< MSTPCRA05 (Bitfield-Mask: 0x01)                       */
43243  #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Pos     (8UL)          /*!< MSTPCRA08 (Bit 8)                                     */
43244  #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Msk     (0x100UL)      /*!< MSTPCRA08 (Bitfield-Mask: 0x01)                       */
43245  #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Pos     (9UL)          /*!< MSTPCRA09 (Bit 9)                                     */
43246  #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Msk     (0x200UL)      /*!< MSTPCRA09 (Bitfield-Mask: 0x01)                       */
43247  #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Pos     (10UL)         /*!< MSTPCRA10 (Bit 10)                                    */
43248  #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Msk     (0x400UL)      /*!< MSTPCRA10 (Bitfield-Mask: 0x01)                       */
43249  #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Pos     (11UL)         /*!< MSTPCRA11 (Bit 11)                                    */
43250  #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Msk     (0x800UL)      /*!< MSTPCRA11 (Bitfield-Mask: 0x01)                       */
43251  #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Pos     (12UL)         /*!< MSTPCRA12 (Bit 12)                                    */
43252  #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Msk     (0x1000UL)     /*!< MSTPCRA12 (Bitfield-Mask: 0x01)                       */
43253 /* ========================================================  MSTPCRB  ======================================================== */
43254  #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Pos     (0UL)          /*!< MSTPCRB00 (Bit 0)                                     */
43255  #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Msk     (0x1UL)        /*!< MSTPCRB00 (Bitfield-Mask: 0x01)                       */
43256  #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Pos     (1UL)          /*!< MSTPCRB01 (Bit 1)                                     */
43257  #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Msk     (0x2UL)        /*!< MSTPCRB01 (Bitfield-Mask: 0x01)                       */
43258  #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Pos     (4UL)          /*!< MSTPCRB04 (Bit 4)                                     */
43259  #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Msk     (0x10UL)       /*!< MSTPCRB04 (Bitfield-Mask: 0x01)                       */
43260  #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Pos     (5UL)          /*!< MSTPCRB05 (Bit 5)                                     */
43261  #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Msk     (0x20UL)       /*!< MSTPCRB05 (Bitfield-Mask: 0x01)                       */
43262  #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Pos     (6UL)          /*!< MSTPCRB06 (Bit 6)                                     */
43263  #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Msk     (0x40UL)       /*!< MSTPCRB06 (Bitfield-Mask: 0x01)                       */
43264 /* ========================================================  MSTPCRC  ======================================================== */
43265  #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Pos     (0UL)          /*!< MSTPCRC00 (Bit 0)                                     */
43266  #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Msk     (0x1UL)        /*!< MSTPCRC00 (Bitfield-Mask: 0x01)                       */
43267  #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Pos     (1UL)          /*!< MSTPCRC01 (Bit 1)                                     */
43268  #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Msk     (0x2UL)        /*!< MSTPCRC01 (Bitfield-Mask: 0x01)                       */
43269  #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Pos     (2UL)          /*!< MSTPCRC02 (Bit 2)                                     */
43270  #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Msk     (0x4UL)        /*!< MSTPCRC02 (Bitfield-Mask: 0x01)                       */
43271  #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Pos     (5UL)          /*!< MSTPCRC05 (Bit 5)                                     */
43272  #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Msk     (0x20UL)       /*!< MSTPCRC05 (Bitfield-Mask: 0x01)                       */
43273  #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Pos     (6UL)          /*!< MSTPCRC06 (Bit 6)                                     */
43274  #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Msk     (0x40UL)       /*!< MSTPCRC06 (Bitfield-Mask: 0x01)                       */
43275  #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Pos     (7UL)          /*!< MSTPCRC07 (Bit 7)                                     */
43276  #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Msk     (0x80UL)       /*!< MSTPCRC07 (Bitfield-Mask: 0x01)                       */
43277 /* ========================================================  MSTPCRD  ======================================================== */
43278  #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Pos     (0UL)          /*!< MSTPCRD00 (Bit 0)                                     */
43279  #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Msk     (0x1UL)        /*!< MSTPCRD00 (Bitfield-Mask: 0x01)                       */
43280  #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Pos     (1UL)          /*!< MSTPCRD01 (Bit 1)                                     */
43281  #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Msk     (0x2UL)        /*!< MSTPCRD01 (Bitfield-Mask: 0x01)                       */
43282  #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Pos     (2UL)          /*!< MSTPCRD02 (Bit 2)                                     */
43283  #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Msk     (0x4UL)        /*!< MSTPCRD02 (Bitfield-Mask: 0x01)                       */
43284  #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Pos     (3UL)          /*!< MSTPCRD03 (Bit 3)                                     */
43285  #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Msk     (0x8UL)        /*!< MSTPCRD03 (Bitfield-Mask: 0x01)                       */
43286  #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Pos     (4UL)          /*!< MSTPCRD04 (Bit 4)                                     */
43287  #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Msk     (0x10UL)       /*!< MSTPCRD04 (Bitfield-Mask: 0x01)                       */
43288  #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Pos     (5UL)          /*!< MSTPCRD05 (Bit 5)                                     */
43289  #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Msk     (0x20UL)       /*!< MSTPCRD05 (Bitfield-Mask: 0x01)                       */
43290  #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Pos     (6UL)          /*!< MSTPCRD06 (Bit 6)                                     */
43291  #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Msk     (0x40UL)       /*!< MSTPCRD06 (Bitfield-Mask: 0x01)                       */
43292  #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Pos     (7UL)          /*!< MSTPCRD07 (Bit 7)                                     */
43293  #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Msk     (0x80UL)       /*!< MSTPCRD07 (Bitfield-Mask: 0x01)                       */
43294  #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Pos     (8UL)          /*!< MSTPCRD08 (Bit 8)                                     */
43295  #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Msk     (0x100UL)      /*!< MSTPCRD08 (Bitfield-Mask: 0x01)                       */
43296  #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Pos     (9UL)          /*!< MSTPCRD09 (Bit 9)                                     */
43297  #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Msk     (0x200UL)      /*!< MSTPCRD09 (Bitfield-Mask: 0x01)                       */
43298  #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Pos     (10UL)         /*!< MSTPCRD10 (Bit 10)                                    */
43299  #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Msk     (0x400UL)      /*!< MSTPCRD10 (Bitfield-Mask: 0x01)                       */
43300  #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Pos     (11UL)         /*!< MSTPCRD11 (Bit 11)                                    */
43301  #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Msk     (0x800UL)      /*!< MSTPCRD11 (Bitfield-Mask: 0x01)                       */
43302 /* ========================================================  MSTPCRE  ======================================================== */
43303  #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Pos     (0UL)          /*!< MSTPCRE00 (Bit 0)                                     */
43304  #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Msk     (0x1UL)        /*!< MSTPCRE00 (Bitfield-Mask: 0x01)                       */
43305  #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Pos     (1UL)          /*!< MSTPCRE01 (Bit 1)                                     */
43306  #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Msk     (0x2UL)        /*!< MSTPCRE01 (Bitfield-Mask: 0x01)                       */
43307  #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Pos     (2UL)          /*!< MSTPCRE02 (Bit 2)                                     */
43308  #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Msk     (0x4UL)        /*!< MSTPCRE02 (Bitfield-Mask: 0x01)                       */
43309  #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Pos     (3UL)          /*!< MSTPCRE03 (Bit 3)                                     */
43310  #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Msk     (0x8UL)        /*!< MSTPCRE03 (Bitfield-Mask: 0x01)                       */
43311  #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Pos     (8UL)          /*!< MSTPCRE08 (Bit 8)                                     */
43312  #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Msk     (0x100UL)      /*!< MSTPCRE08 (Bitfield-Mask: 0x01)                       */
43313 /* ========================================================  MD_MON  ========================================================= */
43314  #define R_SYSC_NS_MD_MON_MDDMON_Pos         (0UL)          /*!< MDDMON (Bit 0)                                        */
43315  #define R_SYSC_NS_MD_MON_MDDMON_Msk         (0x1UL)        /*!< MDDMON (Bitfield-Mask: 0x01)                          */
43316  #define R_SYSC_NS_MD_MON_MDP_Pos            (8UL)          /*!< MDP (Bit 8)                                           */
43317  #define R_SYSC_NS_MD_MON_MDP_Msk            (0x100UL)      /*!< MDP (Bitfield-Mask: 0x01)                             */
43318  #define R_SYSC_NS_MD_MON_MD0MON_Pos         (12UL)         /*!< MD0MON (Bit 12)                                       */
43319  #define R_SYSC_NS_MD_MON_MD0MON_Msk         (0x1000UL)     /*!< MD0MON (Bitfield-Mask: 0x01)                          */
43320  #define R_SYSC_NS_MD_MON_MD1MON_Pos         (13UL)         /*!< MD1MON (Bit 13)                                       */
43321  #define R_SYSC_NS_MD_MON_MD1MON_Msk         (0x2000UL)     /*!< MD1MON (Bitfield-Mask: 0x01)                          */
43322  #define R_SYSC_NS_MD_MON_MD2MON_Pos         (14UL)         /*!< MD2MON (Bit 14)                                       */
43323  #define R_SYSC_NS_MD_MON_MD2MON_Msk         (0x4000UL)     /*!< MD2MON (Bitfield-Mask: 0x01)                          */
43324  #define R_SYSC_NS_MD_MON_MDV0MON_Pos        (16UL)         /*!< MDV0MON (Bit 16)                                      */
43325  #define R_SYSC_NS_MD_MON_MDV0MON_Msk        (0x10000UL)    /*!< MDV0MON (Bitfield-Mask: 0x01)                         */
43326  #define R_SYSC_NS_MD_MON_MDV1MON_Pos        (17UL)         /*!< MDV1MON (Bit 17)                                      */
43327  #define R_SYSC_NS_MD_MON_MDV1MON_Msk        (0x20000UL)    /*!< MDV1MON (Bitfield-Mask: 0x01)                         */
43328  #define R_SYSC_NS_MD_MON_MDV2MON_Pos        (18UL)         /*!< MDV2MON (Bit 18)                                      */
43329  #define R_SYSC_NS_MD_MON_MDV2MON_Msk        (0x40000UL)    /*!< MDV2MON (Bitfield-Mask: 0x01)                         */
43330  #define R_SYSC_NS_MD_MON_MDV3MON_Pos        (19UL)         /*!< MDV3MON (Bit 19)                                      */
43331  #define R_SYSC_NS_MD_MON_MDV3MON_Msk        (0x80000UL)    /*!< MDV3MON (Bitfield-Mask: 0x01)                         */
43332  #define R_SYSC_NS_MD_MON_MDV4MON_Pos        (20UL)         /*!< MDV4MON (Bit 20)                                      */
43333  #define R_SYSC_NS_MD_MON_MDV4MON_Msk        (0x100000UL)   /*!< MDV4MON (Bitfield-Mask: 0x01)                         */
43334 
43335 /* =========================================================================================================================== */
43336 /* ================                                           R_ELO                                           ================ */
43337 /* =========================================================================================================================== */
43338 
43339 /* =========================================================  ELOPA  ========================================================= */
43340  #define R_ELO_ELOPA_MTU0MD_Pos    (0UL)    /*!< MTU0MD (Bit 0)                                        */
43341  #define R_ELO_ELOPA_MTU0MD_Msk    (0x3UL)  /*!< MTU0MD (Bitfield-Mask: 0x03)                          */
43342  #define R_ELO_ELOPA_MTU3MD_Pos    (6UL)    /*!< MTU3MD (Bit 6)                                        */
43343  #define R_ELO_ELOPA_MTU3MD_Msk    (0xc0UL) /*!< MTU3MD (Bitfield-Mask: 0x03)                          */
43344 /* =========================================================  ELOPB  ========================================================= */
43345  #define R_ELO_ELOPB_MTU4MD_Pos    (0UL)    /*!< MTU4MD (Bit 0)                                        */
43346  #define R_ELO_ELOPB_MTU4MD_Msk    (0x3UL)  /*!< MTU4MD (Bitfield-Mask: 0x03)                          */
43347 
43348 /* =========================================================================================================================== */
43349 /* ================                                         R_RWP_NS                                          ================ */
43350 /* =========================================================================================================================== */
43351 
43352 /* =========================================================  PRCRN  ========================================================= */
43353  #define R_RWP_NS_PRCRN_PRC0_Pos     (0UL)      /*!< PRC0 (Bit 0)                                          */
43354  #define R_RWP_NS_PRCRN_PRC0_Msk     (0x1UL)    /*!< PRC0 (Bitfield-Mask: 0x01)                            */
43355  #define R_RWP_NS_PRCRN_PRC1_Pos     (1UL)      /*!< PRC1 (Bit 1)                                          */
43356  #define R_RWP_NS_PRCRN_PRC1_Msk     (0x2UL)    /*!< PRC1 (Bitfield-Mask: 0x01)                            */
43357  #define R_RWP_NS_PRCRN_PRC2_Pos     (2UL)      /*!< PRC2 (Bit 2)                                          */
43358  #define R_RWP_NS_PRCRN_PRC2_Msk     (0x4UL)    /*!< PRC2 (Bitfield-Mask: 0x01)                            */
43359  #define R_RWP_NS_PRCRN_PRKEY_Pos    (8UL)      /*!< PRKEY (Bit 8)                                         */
43360  #define R_RWP_NS_PRCRN_PRKEY_Msk    (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
43361 
43362 /* =========================================================================================================================== */
43363 /* ================                                           R_RTC                                           ================ */
43364 /* =========================================================================================================================== */
43365 
43366 /* =======================================================  RTCA0CTL0  ======================================================= */
43367  #define R_RTC_RTCA0CTL0_RTCA0SLSB_Pos      (4UL)          /*!< RTCA0SLSB (Bit 4)                                     */
43368  #define R_RTC_RTCA0CTL0_RTCA0SLSB_Msk      (0x10UL)       /*!< RTCA0SLSB (Bitfield-Mask: 0x01)                       */
43369  #define R_RTC_RTCA0CTL0_RTCA0AMPM_Pos      (5UL)          /*!< RTCA0AMPM (Bit 5)                                     */
43370  #define R_RTC_RTCA0CTL0_RTCA0AMPM_Msk      (0x20UL)       /*!< RTCA0AMPM (Bitfield-Mask: 0x01)                       */
43371  #define R_RTC_RTCA0CTL0_RTCA0CEST_Pos      (6UL)          /*!< RTCA0CEST (Bit 6)                                     */
43372  #define R_RTC_RTCA0CTL0_RTCA0CEST_Msk      (0x40UL)       /*!< RTCA0CEST (Bitfield-Mask: 0x01)                       */
43373  #define R_RTC_RTCA0CTL0_RTCA0CE_Pos        (7UL)          /*!< RTCA0CE (Bit 7)                                       */
43374  #define R_RTC_RTCA0CTL0_RTCA0CE_Msk        (0x80UL)       /*!< RTCA0CE (Bitfield-Mask: 0x01)                         */
43375 /* =======================================================  RTCA0CTL1  ======================================================= */
43376  #define R_RTC_RTCA0CTL1_RTCA0CT_Pos        (0UL)          /*!< RTCA0CT (Bit 0)                                       */
43377  #define R_RTC_RTCA0CTL1_RTCA0CT_Msk        (0x7UL)        /*!< RTCA0CT (Bitfield-Mask: 0x07)                         */
43378  #define R_RTC_RTCA0CTL1_RTCA01SE_Pos       (3UL)          /*!< RTCA01SE (Bit 3)                                      */
43379  #define R_RTC_RTCA0CTL1_RTCA01SE_Msk       (0x8UL)        /*!< RTCA01SE (Bitfield-Mask: 0x01)                        */
43380  #define R_RTC_RTCA0CTL1_RTCA0ALME_Pos      (4UL)          /*!< RTCA0ALME (Bit 4)                                     */
43381  #define R_RTC_RTCA0CTL1_RTCA0ALME_Msk      (0x10UL)       /*!< RTCA0ALME (Bitfield-Mask: 0x01)                       */
43382  #define R_RTC_RTCA0CTL1_RTCA01HZE_Pos      (5UL)          /*!< RTCA01HZE (Bit 5)                                     */
43383  #define R_RTC_RTCA0CTL1_RTCA01HZE_Msk      (0x20UL)       /*!< RTCA01HZE (Bitfield-Mask: 0x01)                       */
43384 /* =======================================================  RTCA0CTL2  ======================================================= */
43385  #define R_RTC_RTCA0CTL2_RTCA0WAIT_Pos      (0UL)          /*!< RTCA0WAIT (Bit 0)                                     */
43386  #define R_RTC_RTCA0CTL2_RTCA0WAIT_Msk      (0x1UL)        /*!< RTCA0WAIT (Bitfield-Mask: 0x01)                       */
43387  #define R_RTC_RTCA0CTL2_RTCA0WST_Pos       (1UL)          /*!< RTCA0WST (Bit 1)                                      */
43388  #define R_RTC_RTCA0CTL2_RTCA0WST_Msk       (0x2UL)        /*!< RTCA0WST (Bitfield-Mask: 0x01)                        */
43389  #define R_RTC_RTCA0CTL2_RTCA0RSUB_Pos      (2UL)          /*!< RTCA0RSUB (Bit 2)                                     */
43390  #define R_RTC_RTCA0CTL2_RTCA0RSUB_Msk      (0x4UL)        /*!< RTCA0RSUB (Bitfield-Mask: 0x01)                       */
43391  #define R_RTC_RTCA0CTL2_RTCA0RSST_Pos      (3UL)          /*!< RTCA0RSST (Bit 3)                                     */
43392  #define R_RTC_RTCA0CTL2_RTCA0RSST_Msk      (0x8UL)        /*!< RTCA0RSST (Bitfield-Mask: 0x01)                       */
43393  #define R_RTC_RTCA0CTL2_RTCA0WSST_Pos      (4UL)          /*!< RTCA0WSST (Bit 4)                                     */
43394  #define R_RTC_RTCA0CTL2_RTCA0WSST_Msk      (0x10UL)       /*!< RTCA0WSST (Bitfield-Mask: 0x01)                       */
43395 /* =======================================================  RTCA0SUBC  ======================================================= */
43396  #define R_RTC_RTCA0SUBC_RTCA0SUBC_Pos      (0UL)          /*!< RTCA0SUBC (Bit 0)                                     */
43397  #define R_RTC_RTCA0SUBC_RTCA0SUBC_Msk      (0x3fffffUL)   /*!< RTCA0SUBC (Bitfield-Mask: 0x3fffff)                   */
43398 /* =======================================================  RTCA0SRBU  ======================================================= */
43399  #define R_RTC_RTCA0SRBU_RTCA0SRBU_Pos      (0UL)          /*!< RTCA0SRBU (Bit 0)                                     */
43400  #define R_RTC_RTCA0SRBU_RTCA0SRBU_Msk      (0x3fffffUL)   /*!< RTCA0SRBU (Bitfield-Mask: 0x3fffff)                   */
43401 /* =======================================================  RTCA0SEC  ======================================================== */
43402  #define R_RTC_RTCA0SEC_RTCA0SEC_Pos        (0UL)          /*!< RTCA0SEC (Bit 0)                                      */
43403  #define R_RTC_RTCA0SEC_RTCA0SEC_Msk        (0x7fUL)       /*!< RTCA0SEC (Bitfield-Mask: 0x7f)                        */
43404 /* =======================================================  RTCA0MIN  ======================================================== */
43405  #define R_RTC_RTCA0MIN_RTCA0MIN_Pos        (0UL)          /*!< RTCA0MIN (Bit 0)                                      */
43406  #define R_RTC_RTCA0MIN_RTCA0MIN_Msk        (0x7fUL)       /*!< RTCA0MIN (Bitfield-Mask: 0x7f)                        */
43407 /* =======================================================  RTCA0HOUR  ======================================================= */
43408  #define R_RTC_RTCA0HOUR_RTCA0HOUR_Pos      (0UL)          /*!< RTCA0HOUR (Bit 0)                                     */
43409  #define R_RTC_RTCA0HOUR_RTCA0HOUR_Msk      (0x3fUL)       /*!< RTCA0HOUR (Bitfield-Mask: 0x3f)                       */
43410 /* =======================================================  RTCA0WEEK  ======================================================= */
43411  #define R_RTC_RTCA0WEEK_RTCA0WEEK_Pos      (0UL)          /*!< RTCA0WEEK (Bit 0)                                     */
43412  #define R_RTC_RTCA0WEEK_RTCA0WEEK_Msk      (0x7UL)        /*!< RTCA0WEEK (Bitfield-Mask: 0x07)                       */
43413 /* =======================================================  RTCA0DAY  ======================================================== */
43414  #define R_RTC_RTCA0DAY_RTCA0DAY_Pos        (0UL)          /*!< RTCA0DAY (Bit 0)                                      */
43415  #define R_RTC_RTCA0DAY_RTCA0DAY_Msk        (0x3fUL)       /*!< RTCA0DAY (Bitfield-Mask: 0x3f)                        */
43416 /* ======================================================  RTCA0MONTH  ======================================================= */
43417  #define R_RTC_RTCA0MONTH_RTCA0MONTH_Pos    (0UL)          /*!< RTCA0MONTH (Bit 0)                                    */
43418  #define R_RTC_RTCA0MONTH_RTCA0MONTH_Msk    (0x1fUL)       /*!< RTCA0MONTH (Bitfield-Mask: 0x1f)                      */
43419 /* =======================================================  RTCA0YEAR  ======================================================= */
43420  #define R_RTC_RTCA0YEAR_RTCA0YEAR_Pos      (0UL)          /*!< RTCA0YEAR (Bit 0)                                     */
43421  #define R_RTC_RTCA0YEAR_RTCA0YEAR_Msk      (0xffUL)       /*!< RTCA0YEAR (Bitfield-Mask: 0xff)                       */
43422 /* =======================================================  RTCA0TIME  ======================================================= */
43423  #define R_RTC_RTCA0TIME_RTCA0SEC_Pos       (0UL)          /*!< RTCA0SEC (Bit 0)                                      */
43424  #define R_RTC_RTCA0TIME_RTCA0SEC_Msk       (0xffUL)       /*!< RTCA0SEC (Bitfield-Mask: 0xff)                        */
43425  #define R_RTC_RTCA0TIME_RTCA0MIN_Pos       (8UL)          /*!< RTCA0MIN (Bit 8)                                      */
43426  #define R_RTC_RTCA0TIME_RTCA0MIN_Msk       (0xff00UL)     /*!< RTCA0MIN (Bitfield-Mask: 0xff)                        */
43427  #define R_RTC_RTCA0TIME_RTCA0HOUR_Pos      (16UL)         /*!< RTCA0HOUR (Bit 16)                                    */
43428  #define R_RTC_RTCA0TIME_RTCA0HOUR_Msk      (0xff0000UL)   /*!< RTCA0HOUR (Bitfield-Mask: 0xff)                       */
43429 /* =======================================================  RTCA0CAL  ======================================================== */
43430  #define R_RTC_RTCA0CAL_RTCA0WEEK_Pos       (0UL)          /*!< RTCA0WEEK (Bit 0)                                     */
43431  #define R_RTC_RTCA0CAL_RTCA0WEEK_Msk       (0xffUL)       /*!< RTCA0WEEK (Bitfield-Mask: 0xff)                       */
43432  #define R_RTC_RTCA0CAL_RTCA0DAY_Pos        (8UL)          /*!< RTCA0DAY (Bit 8)                                      */
43433  #define R_RTC_RTCA0CAL_RTCA0DAY_Msk        (0xff00UL)     /*!< RTCA0DAY (Bitfield-Mask: 0xff)                        */
43434  #define R_RTC_RTCA0CAL_RTCA0MONTH_Pos      (16UL)         /*!< RTCA0MONTH (Bit 16)                                   */
43435  #define R_RTC_RTCA0CAL_RTCA0MONTH_Msk      (0xff0000UL)   /*!< RTCA0MONTH (Bitfield-Mask: 0xff)                      */
43436  #define R_RTC_RTCA0CAL_RTCA0YEAR_Pos       (24UL)         /*!< RTCA0YEAR (Bit 24)                                    */
43437  #define R_RTC_RTCA0CAL_RTCA0YEAR_Msk       (0xff000000UL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff)                       */
43438 /* =======================================================  RTCA0SCMP  ======================================================= */
43439  #define R_RTC_RTCA0SCMP_RTCA0SCMP_Pos      (0UL)          /*!< RTCA0SCMP (Bit 0)                                     */
43440  #define R_RTC_RTCA0SCMP_RTCA0SCMP_Msk      (0x3fffffUL)   /*!< RTCA0SCMP (Bitfield-Mask: 0x3fffff)                   */
43441 /* =======================================================  RTCA0ALM  ======================================================== */
43442  #define R_RTC_RTCA0ALM_RTCA0ALM_Pos        (0UL)          /*!< RTCA0ALM (Bit 0)                                      */
43443  #define R_RTC_RTCA0ALM_RTCA0ALM_Msk        (0x7fUL)       /*!< RTCA0ALM (Bitfield-Mask: 0x7f)                        */
43444 /* =======================================================  RTCA0ALH  ======================================================== */
43445  #define R_RTC_RTCA0ALH_RTCA0ALH_Pos        (0UL)          /*!< RTCA0ALH (Bit 0)                                      */
43446  #define R_RTC_RTCA0ALH_RTCA0ALH_Msk        (0x3fUL)       /*!< RTCA0ALH (Bitfield-Mask: 0x3f)                        */
43447 /* =======================================================  RTCA0ALW  ======================================================== */
43448  #define R_RTC_RTCA0ALW_RTCA0ALW0_Pos       (0UL)          /*!< RTCA0ALW0 (Bit 0)                                     */
43449  #define R_RTC_RTCA0ALW_RTCA0ALW0_Msk       (0x1UL)        /*!< RTCA0ALW0 (Bitfield-Mask: 0x01)                       */
43450  #define R_RTC_RTCA0ALW_RTCA0ALW1_Pos       (1UL)          /*!< RTCA0ALW1 (Bit 1)                                     */
43451  #define R_RTC_RTCA0ALW_RTCA0ALW1_Msk       (0x2UL)        /*!< RTCA0ALW1 (Bitfield-Mask: 0x01)                       */
43452  #define R_RTC_RTCA0ALW_RTCA0ALW2_Pos       (2UL)          /*!< RTCA0ALW2 (Bit 2)                                     */
43453  #define R_RTC_RTCA0ALW_RTCA0ALW2_Msk       (0x4UL)        /*!< RTCA0ALW2 (Bitfield-Mask: 0x01)                       */
43454  #define R_RTC_RTCA0ALW_RTCA0ALW3_Pos       (3UL)          /*!< RTCA0ALW3 (Bit 3)                                     */
43455  #define R_RTC_RTCA0ALW_RTCA0ALW3_Msk       (0x8UL)        /*!< RTCA0ALW3 (Bitfield-Mask: 0x01)                       */
43456  #define R_RTC_RTCA0ALW_RTCA0ALW4_Pos       (4UL)          /*!< RTCA0ALW4 (Bit 4)                                     */
43457  #define R_RTC_RTCA0ALW_RTCA0ALW4_Msk       (0x10UL)       /*!< RTCA0ALW4 (Bitfield-Mask: 0x01)                       */
43458  #define R_RTC_RTCA0ALW_RTCA0ALW5_Pos       (5UL)          /*!< RTCA0ALW5 (Bit 5)                                     */
43459  #define R_RTC_RTCA0ALW_RTCA0ALW5_Msk       (0x20UL)       /*!< RTCA0ALW5 (Bitfield-Mask: 0x01)                       */
43460  #define R_RTC_RTCA0ALW_RTCA0ALW6_Pos       (6UL)          /*!< RTCA0ALW6 (Bit 6)                                     */
43461  #define R_RTC_RTCA0ALW_RTCA0ALW6_Msk       (0x40UL)       /*!< RTCA0ALW6 (Bitfield-Mask: 0x01)                       */
43462 /* =======================================================  RTCA0SECC  ======================================================= */
43463  #define R_RTC_RTCA0SECC_RTCA0SECC_Pos      (0UL)          /*!< RTCA0SECC (Bit 0)                                     */
43464  #define R_RTC_RTCA0SECC_RTCA0SECC_Msk      (0x7fUL)       /*!< RTCA0SECC (Bitfield-Mask: 0x7f)                       */
43465 /* =======================================================  RTCA0MINC  ======================================================= */
43466  #define R_RTC_RTCA0MINC_RTCA0MINC_Pos      (0UL)          /*!< RTCA0MINC (Bit 0)                                     */
43467  #define R_RTC_RTCA0MINC_RTCA0MINC_Msk      (0x7fUL)       /*!< RTCA0MINC (Bitfield-Mask: 0x7f)                       */
43468 /* ======================================================  RTCA0HOURC  ======================================================= */
43469  #define R_RTC_RTCA0HOURC_RTCA0HOURC_Pos    (0UL)          /*!< RTCA0HOURC (Bit 0)                                    */
43470  #define R_RTC_RTCA0HOURC_RTCA0HOURC_Msk    (0x3fUL)       /*!< RTCA0HOURC (Bitfield-Mask: 0x3f)                      */
43471 /* ======================================================  RTCA0WEEKC  ======================================================= */
43472  #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Pos    (0UL)          /*!< RTCA0WEEKC (Bit 0)                                    */
43473  #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Msk    (0x7UL)        /*!< RTCA0WEEKC (Bitfield-Mask: 0x07)                      */
43474 /* =======================================================  RTCA0DAYC  ======================================================= */
43475  #define R_RTC_RTCA0DAYC_RTCA0DAYC_Pos      (0UL)          /*!< RTCA0DAYC (Bit 0)                                     */
43476  #define R_RTC_RTCA0DAYC_RTCA0DAYC_Msk      (0x3fUL)       /*!< RTCA0DAYC (Bitfield-Mask: 0x3f)                       */
43477 /* =======================================================  RTCA0MONC  ======================================================= */
43478  #define R_RTC_RTCA0MONC_RTCA0MONC_Pos      (0UL)          /*!< RTCA0MONC (Bit 0)                                     */
43479  #define R_RTC_RTCA0MONC_RTCA0MONC_Msk      (0x1fUL)       /*!< RTCA0MONC (Bitfield-Mask: 0x1f)                       */
43480 /* ======================================================  RTCA0YEARC  ======================================================= */
43481  #define R_RTC_RTCA0YEARC_RTCA0YEARC_Pos    (0UL)          /*!< RTCA0YEARC (Bit 0)                                    */
43482  #define R_RTC_RTCA0YEARC_RTCA0YEARC_Msk    (0xffUL)       /*!< RTCA0YEARC (Bitfield-Mask: 0xff)                      */
43483 /* ======================================================  RTCA0TIMEC  ======================================================= */
43484  #define R_RTC_RTCA0TIMEC_RTCA0SECC_Pos     (0UL)          /*!< RTCA0SECC (Bit 0)                                     */
43485  #define R_RTC_RTCA0TIMEC_RTCA0SECC_Msk     (0xffUL)       /*!< RTCA0SECC (Bitfield-Mask: 0xff)                       */
43486  #define R_RTC_RTCA0TIMEC_RTCA0MINC_Pos     (8UL)          /*!< RTCA0MINC (Bit 8)                                     */
43487  #define R_RTC_RTCA0TIMEC_RTCA0MINC_Msk     (0xff00UL)     /*!< RTCA0MINC (Bitfield-Mask: 0xff)                       */
43488  #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Pos    (16UL)         /*!< RTCA0HOURC (Bit 16)                                   */
43489  #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Msk    (0xff0000UL)   /*!< RTCA0HOURC (Bitfield-Mask: 0xff)                      */
43490 /* =======================================================  RTCA0CALC  ======================================================= */
43491  #define R_RTC_RTCA0CALC_RTCA0WEEKC_Pos     (0UL)          /*!< RTCA0WEEKC (Bit 0)                                    */
43492  #define R_RTC_RTCA0CALC_RTCA0WEEKC_Msk     (0xffUL)       /*!< RTCA0WEEKC (Bitfield-Mask: 0xff)                      */
43493  #define R_RTC_RTCA0CALC_RTCA0DAYC_Pos      (8UL)          /*!< RTCA0DAYC (Bit 8)                                     */
43494  #define R_RTC_RTCA0CALC_RTCA0DAYC_Msk      (0xff00UL)     /*!< RTCA0DAYC (Bitfield-Mask: 0xff)                       */
43495  #define R_RTC_RTCA0CALC_RTCA0MONC_Pos      (16UL)         /*!< RTCA0MONC (Bit 16)                                    */
43496  #define R_RTC_RTCA0CALC_RTCA0MONC_Msk      (0xff0000UL)   /*!< RTCA0MONC (Bitfield-Mask: 0xff)                       */
43497  #define R_RTC_RTCA0CALC_RTCA0YEARC_Pos     (24UL)         /*!< RTCA0YEARC (Bit 24)                                   */
43498  #define R_RTC_RTCA0CALC_RTCA0YEARC_Msk     (0xff000000UL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff)                      */
43499 
43500 /* =========================================================================================================================== */
43501 /* ================                                          R_POEG2                                          ================ */
43502 /* =========================================================================================================================== */
43503 
43504 /* ========================================================  POEG2GA  ======================================================== */
43505  #define R_POEG2_POEG2GA_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
43506  #define R_POEG2_POEG2GA_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
43507  #define R_POEG2_POEG2GA_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
43508  #define R_POEG2_POEG2GA_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
43509  #define R_POEG2_POEG2GA_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
43510  #define R_POEG2_POEG2GA_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
43511  #define R_POEG2_POEG2GA_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
43512  #define R_POEG2_POEG2GA_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
43513  #define R_POEG2_POEG2GA_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
43514  #define R_POEG2_POEG2GA_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
43515  #define R_POEG2_POEG2GA_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
43516  #define R_POEG2_POEG2GA_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
43517  #define R_POEG2_POEG2GA_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
43518  #define R_POEG2_POEG2GA_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
43519  #define R_POEG2_POEG2GA_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
43520  #define R_POEG2_POEG2GA_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
43521  #define R_POEG2_POEG2GA_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
43522  #define R_POEG2_POEG2GA_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
43523  #define R_POEG2_POEG2GA_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
43524  #define R_POEG2_POEG2GA_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
43525  #define R_POEG2_POEG2GA_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
43526  #define R_POEG2_POEG2GA_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
43527 /* ========================================================  POEG2GB  ======================================================== */
43528  #define R_POEG2_POEG2GB_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
43529  #define R_POEG2_POEG2GB_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
43530  #define R_POEG2_POEG2GB_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
43531  #define R_POEG2_POEG2GB_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
43532  #define R_POEG2_POEG2GB_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
43533  #define R_POEG2_POEG2GB_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
43534  #define R_POEG2_POEG2GB_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
43535  #define R_POEG2_POEG2GB_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
43536  #define R_POEG2_POEG2GB_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
43537  #define R_POEG2_POEG2GB_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
43538  #define R_POEG2_POEG2GB_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
43539  #define R_POEG2_POEG2GB_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
43540  #define R_POEG2_POEG2GB_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
43541  #define R_POEG2_POEG2GB_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
43542  #define R_POEG2_POEG2GB_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
43543  #define R_POEG2_POEG2GB_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
43544  #define R_POEG2_POEG2GB_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
43545  #define R_POEG2_POEG2GB_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
43546  #define R_POEG2_POEG2GB_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
43547  #define R_POEG2_POEG2GB_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
43548  #define R_POEG2_POEG2GB_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
43549  #define R_POEG2_POEG2GB_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
43550 /* ========================================================  POEG2GC  ======================================================== */
43551  #define R_POEG2_POEG2GC_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
43552  #define R_POEG2_POEG2GC_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
43553  #define R_POEG2_POEG2GC_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
43554  #define R_POEG2_POEG2GC_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
43555  #define R_POEG2_POEG2GC_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
43556  #define R_POEG2_POEG2GC_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
43557  #define R_POEG2_POEG2GC_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
43558  #define R_POEG2_POEG2GC_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
43559  #define R_POEG2_POEG2GC_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
43560  #define R_POEG2_POEG2GC_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
43561  #define R_POEG2_POEG2GC_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
43562  #define R_POEG2_POEG2GC_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
43563  #define R_POEG2_POEG2GC_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
43564  #define R_POEG2_POEG2GC_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
43565  #define R_POEG2_POEG2GC_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
43566  #define R_POEG2_POEG2GC_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
43567  #define R_POEG2_POEG2GC_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
43568  #define R_POEG2_POEG2GC_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
43569  #define R_POEG2_POEG2GC_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
43570  #define R_POEG2_POEG2GC_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
43571  #define R_POEG2_POEG2GC_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
43572  #define R_POEG2_POEG2GC_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
43573 /* ========================================================  POEG2GD  ======================================================== */
43574  #define R_POEG2_POEG2GD_PIDF_Pos     (0UL)          /*!< PIDF (Bit 0)                                          */
43575  #define R_POEG2_POEG2GD_PIDF_Msk     (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
43576  #define R_POEG2_POEG2GD_IOCF_Pos     (1UL)          /*!< IOCF (Bit 1)                                          */
43577  #define R_POEG2_POEG2GD_IOCF_Msk     (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
43578  #define R_POEG2_POEG2GD_OSTPF_Pos    (2UL)          /*!< OSTPF (Bit 2)                                         */
43579  #define R_POEG2_POEG2GD_OSTPF_Msk    (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
43580  #define R_POEG2_POEG2GD_SSF_Pos      (3UL)          /*!< SSF (Bit 3)                                           */
43581  #define R_POEG2_POEG2GD_SSF_Msk      (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
43582  #define R_POEG2_POEG2GD_PIDE_Pos     (4UL)          /*!< PIDE (Bit 4)                                          */
43583  #define R_POEG2_POEG2GD_PIDE_Msk     (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
43584  #define R_POEG2_POEG2GD_IOCE_Pos     (5UL)          /*!< IOCE (Bit 5)                                          */
43585  #define R_POEG2_POEG2GD_IOCE_Msk     (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
43586  #define R_POEG2_POEG2GD_OSTPE_Pos    (6UL)          /*!< OSTPE (Bit 6)                                         */
43587  #define R_POEG2_POEG2GD_OSTPE_Msk    (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
43588  #define R_POEG2_POEG2GD_ST_Pos       (16UL)         /*!< ST (Bit 16)                                           */
43589  #define R_POEG2_POEG2GD_ST_Msk       (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
43590  #define R_POEG2_POEG2GD_INV_Pos      (28UL)         /*!< INV (Bit 28)                                          */
43591  #define R_POEG2_POEG2GD_INV_Msk      (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
43592  #define R_POEG2_POEG2GD_NFEN_Pos     (29UL)         /*!< NFEN (Bit 29)                                         */
43593  #define R_POEG2_POEG2GD_NFEN_Msk     (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
43594  #define R_POEG2_POEG2GD_NFCS_Pos     (30UL)         /*!< NFCS (Bit 30)                                         */
43595  #define R_POEG2_POEG2GD_NFCS_Msk     (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
43596 
43597 /* =========================================================================================================================== */
43598 /* ================                                           R_OTP                                           ================ */
43599 /* =========================================================================================================================== */
43600 
43601 /* ========================================================  OTPPWR  ========================================================= */
43602  #define R_OTP_OTPPWR_PWR_Pos            (0UL)      /*!< PWR (Bit 0)                                           */
43603  #define R_OTP_OTPPWR_PWR_Msk            (0x1UL)    /*!< PWR (Bitfield-Mask: 0x01)                             */
43604  #define R_OTP_OTPPWR_ACCL_Pos           (4UL)      /*!< ACCL (Bit 4)                                          */
43605  #define R_OTP_OTPPWR_ACCL_Msk           (0x10UL)   /*!< ACCL (Bitfield-Mask: 0x01)                            */
43606 /* ========================================================  OTPSTR  ========================================================= */
43607  #define R_OTP_OTPSTR_CMD_RDY_Pos        (0UL)      /*!< CMD_RDY (Bit 0)                                       */
43608  #define R_OTP_OTPSTR_CMD_RDY_Msk        (0x1UL)    /*!< CMD_RDY (Bitfield-Mask: 0x01)                         */
43609  #define R_OTP_OTPSTR_ERR_WR_Pos         (1UL)      /*!< ERR_WR (Bit 1)                                        */
43610  #define R_OTP_OTPSTR_ERR_WR_Msk         (0x6UL)    /*!< ERR_WR (Bitfield-Mask: 0x03)                          */
43611  #define R_OTP_OTPSTR_ERR_WP_Pos         (3UL)      /*!< ERR_WP (Bit 3)                                        */
43612  #define R_OTP_OTPSTR_ERR_WP_Msk         (0x8UL)    /*!< ERR_WP (Bitfield-Mask: 0x01)                          */
43613  #define R_OTP_OTPSTR_ERR_RP_Pos         (4UL)      /*!< ERR_RP (Bit 4)                                        */
43614  #define R_OTP_OTPSTR_ERR_RP_Msk         (0x10UL)   /*!< ERR_RP (Bitfield-Mask: 0x01)                          */
43615  #define R_OTP_OTPSTR_ERR_RDY_WR_Pos     (8UL)      /*!< ERR_RDY_WR (Bit 8)                                    */
43616  #define R_OTP_OTPSTR_ERR_RDY_WR_Msk     (0x100UL)  /*!< ERR_RDY_WR (Bitfield-Mask: 0x01)                      */
43617  #define R_OTP_OTPSTR_ERR_RDY_RD_Pos     (9UL)      /*!< ERR_RDY_RD (Bit 9)                                    */
43618  #define R_OTP_OTPSTR_ERR_RDY_RD_Msk     (0x200UL)  /*!< ERR_RDY_RD (Bitfield-Mask: 0x01)                      */
43619  #define R_OTP_OTPSTR_CNT_ST_IDLE_Pos    (15UL)     /*!< CNT_ST_IDLE (Bit 15)                                  */
43620  #define R_OTP_OTPSTR_CNT_ST_IDLE_Msk    (0x8000UL) /*!< CNT_ST_IDLE (Bitfield-Mask: 0x01)                     */
43621 /* =======================================================  OTPSTAWR  ======================================================== */
43622  #define R_OTP_OTPSTAWR_STAWR_Pos        (0UL)      /*!< STAWR (Bit 0)                                         */
43623  #define R_OTP_OTPSTAWR_STAWR_Msk        (0x1UL)    /*!< STAWR (Bitfield-Mask: 0x01)                           */
43624 /* =======================================================  OTPADRWR  ======================================================== */
43625  #define R_OTP_OTPADRWR_ADRWR_Pos        (0UL)      /*!< ADRWR (Bit 0)                                         */
43626  #define R_OTP_OTPADRWR_ADRWR_Msk        (0x1ffUL)  /*!< ADRWR (Bitfield-Mask: 0x1ff)                          */
43627 /* =======================================================  OTPDATAWR  ======================================================= */
43628  #define R_OTP_OTPDATAWR_DATAWR_Pos      (0UL)      /*!< DATAWR (Bit 0)                                        */
43629  #define R_OTP_OTPDATAWR_DATAWR_Msk      (0xffffUL) /*!< DATAWR (Bitfield-Mask: 0xffff)                        */
43630 /* =======================================================  OTPADRRD  ======================================================== */
43631  #define R_OTP_OTPADRRD_ADRRD_Pos        (0UL)      /*!< ADRRD (Bit 0)                                         */
43632  #define R_OTP_OTPADRRD_ADRRD_Msk        (0x1ffUL)  /*!< ADRRD (Bitfield-Mask: 0x1ff)                          */
43633 /* =======================================================  OTPDATARD  ======================================================= */
43634  #define R_OTP_OTPDATARD_DATARD_Pos      (0UL)      /*!< DATARD (Bit 0)                                        */
43635  #define R_OTP_OTPDATARD_DATARD_Msk      (0xffffUL) /*!< DATARD (Bitfield-Mask: 0xffff)                        */
43636 
43637 /* =========================================================================================================================== */
43638 /* ================                                          R_PTADR                                          ================ */
43639 /* =========================================================================================================================== */
43640 
43641 /* =========================================================  RSELP  ========================================================= */
43642  #define R_PTADR_RSELP_RS0_Pos    (0UL)    /*!< RS0 (Bit 0)                                           */
43643  #define R_PTADR_RSELP_RS0_Msk    (0x1UL)  /*!< RS0 (Bitfield-Mask: 0x01)                             */
43644  #define R_PTADR_RSELP_RS1_Pos    (1UL)    /*!< RS1 (Bit 1)                                           */
43645  #define R_PTADR_RSELP_RS1_Msk    (0x2UL)  /*!< RS1 (Bitfield-Mask: 0x01)                             */
43646  #define R_PTADR_RSELP_RS2_Pos    (2UL)    /*!< RS2 (Bit 2)                                           */
43647  #define R_PTADR_RSELP_RS2_Msk    (0x4UL)  /*!< RS2 (Bitfield-Mask: 0x01)                             */
43648  #define R_PTADR_RSELP_RS3_Pos    (3UL)    /*!< RS3 (Bit 3)                                           */
43649  #define R_PTADR_RSELP_RS3_Msk    (0x8UL)  /*!< RS3 (Bitfield-Mask: 0x01)                             */
43650  #define R_PTADR_RSELP_RS4_Pos    (4UL)    /*!< RS4 (Bit 4)                                           */
43651  #define R_PTADR_RSELP_RS4_Msk    (0x10UL) /*!< RS4 (Bitfield-Mask: 0x01)                             */
43652  #define R_PTADR_RSELP_RS5_Pos    (5UL)    /*!< RS5 (Bit 5)                                           */
43653  #define R_PTADR_RSELP_RS5_Msk    (0x20UL) /*!< RS5 (Bitfield-Mask: 0x01)                             */
43654  #define R_PTADR_RSELP_RS6_Pos    (6UL)    /*!< RS6 (Bit 6)                                           */
43655  #define R_PTADR_RSELP_RS6_Msk    (0x40UL) /*!< RS6 (Bitfield-Mask: 0x01)                             */
43656  #define R_PTADR_RSELP_RS7_Pos    (7UL)    /*!< RS7 (Bit 7)                                           */
43657  #define R_PTADR_RSELP_RS7_Msk    (0x80UL) /*!< RS7 (Bitfield-Mask: 0x01)                             */
43658 
43659 /* =========================================================================================================================== */
43660 /* ================                                         R_SYSRAM0                                         ================ */
43661 /* =========================================================================================================================== */
43662 
43663 /* =========================================================================================================================== */
43664 /* ================                                           R_ICU                                           ================ */
43665 /* =========================================================================================================================== */
43666 
43667 /* ========================================================  S_SWINT  ======================================================== */
43668  #define R_ICU_S_SWINT_IC6_Pos                 (0UL)          /*!< IC6 (Bit 0)                                           */
43669  #define R_ICU_S_SWINT_IC6_Msk                 (0x1UL)        /*!< IC6 (Bitfield-Mask: 0x01)                             */
43670  #define R_ICU_S_SWINT_IC7_Pos                 (1UL)          /*!< IC7 (Bit 1)                                           */
43671  #define R_ICU_S_SWINT_IC7_Msk                 (0x2UL)        /*!< IC7 (Bitfield-Mask: 0x01)                             */
43672 /* ====================================================  S_PORTNF_FLTSEL  ==================================================== */
43673  #define R_ICU_S_PORTNF_FLTSEL_FLT14_Pos       (0UL)          /*!< FLT14 (Bit 0)                                         */
43674  #define R_ICU_S_PORTNF_FLTSEL_FLT14_Msk       (0x1UL)        /*!< FLT14 (Bitfield-Mask: 0x01)                           */
43675  #define R_ICU_S_PORTNF_FLTSEL_FLT15_Pos       (1UL)          /*!< FLT15 (Bit 1)                                         */
43676  #define R_ICU_S_PORTNF_FLTSEL_FLT15_Msk       (0x2UL)        /*!< FLT15 (Bitfield-Mask: 0x01)                           */
43677  #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Pos      (2UL)          /*!< FLTNMI (Bit 2)                                        */
43678  #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Msk      (0x4UL)        /*!< FLTNMI (Bitfield-Mask: 0x01)                          */
43679 /* ====================================================  S_PORTNF_CLKSEL  ==================================================== */
43680  #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Pos     (0UL)          /*!< CKSEL14 (Bit 0)                                       */
43681  #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Msk     (0x3UL)        /*!< CKSEL14 (Bitfield-Mask: 0x03)                         */
43682  #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Pos     (2UL)          /*!< CKSEL15 (Bit 2)                                       */
43683  #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Msk     (0xcUL)        /*!< CKSEL15 (Bitfield-Mask: 0x03)                         */
43684  #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Pos    (4UL)          /*!< CKSELNMI (Bit 4)                                      */
43685  #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Msk    (0x30UL)       /*!< CKSELNMI (Bitfield-Mask: 0x03)                        */
43686 /* ======================================================  S_PORTNF_MD  ====================================================== */
43687  #define R_ICU_S_PORTNF_MD_MD14_Pos            (0UL)          /*!< MD14 (Bit 0)                                          */
43688  #define R_ICU_S_PORTNF_MD_MD14_Msk            (0x3UL)        /*!< MD14 (Bitfield-Mask: 0x03)                            */
43689  #define R_ICU_S_PORTNF_MD_MD15_Pos            (2UL)          /*!< MD15 (Bit 2)                                          */
43690  #define R_ICU_S_PORTNF_MD_MD15_Msk            (0xcUL)        /*!< MD15 (Bitfield-Mask: 0x03)                            */
43691  #define R_ICU_S_PORTNF_MD_MDNMI_Pos           (4UL)          /*!< MDNMI (Bit 4)                                         */
43692  #define R_ICU_S_PORTNF_MD_MDNMI_Msk           (0x30UL)       /*!< MDNMI (Bitfield-Mask: 0x03)                           */
43693 /* =====================================================  CPU0ERR_STAT  ====================================================== */
43694  #define R_ICU_CPU0ERR_STAT_ER_ST0_Pos         (0UL)          /*!< ER_ST0 (Bit 0)                                        */
43695  #define R_ICU_CPU0ERR_STAT_ER_ST0_Msk         (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
43696  #define R_ICU_CPU0ERR_STAT_ER_ST1_Pos         (1UL)          /*!< ER_ST1 (Bit 1)                                        */
43697  #define R_ICU_CPU0ERR_STAT_ER_ST1_Msk         (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
43698  #define R_ICU_CPU0ERR_STAT_ER_ST2_Pos         (2UL)          /*!< ER_ST2 (Bit 2)                                        */
43699  #define R_ICU_CPU0ERR_STAT_ER_ST2_Msk         (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
43700  #define R_ICU_CPU0ERR_STAT_ER_ST3_Pos         (3UL)          /*!< ER_ST3 (Bit 3)                                        */
43701  #define R_ICU_CPU0ERR_STAT_ER_ST3_Msk         (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
43702  #define R_ICU_CPU0ERR_STAT_ER_ST4_Pos         (4UL)          /*!< ER_ST4 (Bit 4)                                        */
43703  #define R_ICU_CPU0ERR_STAT_ER_ST4_Msk         (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
43704  #define R_ICU_CPU0ERR_STAT_ER_ST5_Pos         (5UL)          /*!< ER_ST5 (Bit 5)                                        */
43705  #define R_ICU_CPU0ERR_STAT_ER_ST5_Msk         (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
43706  #define R_ICU_CPU0ERR_STAT_ER_ST6_Pos         (6UL)          /*!< ER_ST6 (Bit 6)                                        */
43707  #define R_ICU_CPU0ERR_STAT_ER_ST6_Msk         (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
43708  #define R_ICU_CPU0ERR_STAT_ER_ST7_Pos         (7UL)          /*!< ER_ST7 (Bit 7)                                        */
43709  #define R_ICU_CPU0ERR_STAT_ER_ST7_Msk         (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
43710  #define R_ICU_CPU0ERR_STAT_ER_ST8_Pos         (8UL)          /*!< ER_ST8 (Bit 8)                                        */
43711  #define R_ICU_CPU0ERR_STAT_ER_ST8_Msk         (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
43712  #define R_ICU_CPU0ERR_STAT_ER_ST9_Pos         (9UL)          /*!< ER_ST9 (Bit 9)                                        */
43713  #define R_ICU_CPU0ERR_STAT_ER_ST9_Msk         (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
43714  #define R_ICU_CPU0ERR_STAT_ER_ST10_Pos        (10UL)         /*!< ER_ST10 (Bit 10)                                      */
43715  #define R_ICU_CPU0ERR_STAT_ER_ST10_Msk        (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
43716  #define R_ICU_CPU0ERR_STAT_ER_ST11_Pos        (11UL)         /*!< ER_ST11 (Bit 11)                                      */
43717  #define R_ICU_CPU0ERR_STAT_ER_ST11_Msk        (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
43718  #define R_ICU_CPU0ERR_STAT_ER_ST12_Pos        (12UL)         /*!< ER_ST12 (Bit 12)                                      */
43719  #define R_ICU_CPU0ERR_STAT_ER_ST12_Msk        (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
43720  #define R_ICU_CPU0ERR_STAT_ER_ST13_Pos        (13UL)         /*!< ER_ST13 (Bit 13)                                      */
43721  #define R_ICU_CPU0ERR_STAT_ER_ST13_Msk        (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
43722  #define R_ICU_CPU0ERR_STAT_ER_ST14_Pos        (14UL)         /*!< ER_ST14 (Bit 14)                                      */
43723  #define R_ICU_CPU0ERR_STAT_ER_ST14_Msk        (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
43724  #define R_ICU_CPU0ERR_STAT_ER_ST15_Pos        (15UL)         /*!< ER_ST15 (Bit 15)                                      */
43725  #define R_ICU_CPU0ERR_STAT_ER_ST15_Msk        (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
43726  #define R_ICU_CPU0ERR_STAT_ER_ST16_Pos        (16UL)         /*!< ER_ST16 (Bit 16)                                      */
43727  #define R_ICU_CPU0ERR_STAT_ER_ST16_Msk        (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
43728  #define R_ICU_CPU0ERR_STAT_ER_ST17_Pos        (17UL)         /*!< ER_ST17 (Bit 17)                                      */
43729  #define R_ICU_CPU0ERR_STAT_ER_ST17_Msk        (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
43730  #define R_ICU_CPU0ERR_STAT_ER_ST18_Pos        (18UL)         /*!< ER_ST18 (Bit 18)                                      */
43731  #define R_ICU_CPU0ERR_STAT_ER_ST18_Msk        (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
43732  #define R_ICU_CPU0ERR_STAT_ER_ST19_Pos        (19UL)         /*!< ER_ST19 (Bit 19)                                      */
43733  #define R_ICU_CPU0ERR_STAT_ER_ST19_Msk        (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
43734  #define R_ICU_CPU0ERR_STAT_ER_ST20_Pos        (20UL)         /*!< ER_ST20 (Bit 20)                                      */
43735  #define R_ICU_CPU0ERR_STAT_ER_ST20_Msk        (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
43736  #define R_ICU_CPU0ERR_STAT_ER_ST21_Pos        (21UL)         /*!< ER_ST21 (Bit 21)                                      */
43737  #define R_ICU_CPU0ERR_STAT_ER_ST21_Msk        (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
43738  #define R_ICU_CPU0ERR_STAT_ER_ST22_Pos        (22UL)         /*!< ER_ST22 (Bit 22)                                      */
43739  #define R_ICU_CPU0ERR_STAT_ER_ST22_Msk        (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
43740  #define R_ICU_CPU0ERR_STAT_ER_ST23_Pos        (23UL)         /*!< ER_ST23 (Bit 23)                                      */
43741  #define R_ICU_CPU0ERR_STAT_ER_ST23_Msk        (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
43742  #define R_ICU_CPU0ERR_STAT_ER_ST24_Pos        (24UL)         /*!< ER_ST24 (Bit 24)                                      */
43743  #define R_ICU_CPU0ERR_STAT_ER_ST24_Msk        (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
43744  #define R_ICU_CPU0ERR_STAT_ER_ST25_Pos        (25UL)         /*!< ER_ST25 (Bit 25)                                      */
43745  #define R_ICU_CPU0ERR_STAT_ER_ST25_Msk        (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
43746 /* =====================================================  PERIERR_STAT0  ===================================================== */
43747  #define R_ICU_PERIERR_STAT0_ER_ST0_Pos        (0UL)          /*!< ER_ST0 (Bit 0)                                        */
43748  #define R_ICU_PERIERR_STAT0_ER_ST0_Msk        (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
43749  #define R_ICU_PERIERR_STAT0_ER_ST1_Pos        (1UL)          /*!< ER_ST1 (Bit 1)                                        */
43750  #define R_ICU_PERIERR_STAT0_ER_ST1_Msk        (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
43751  #define R_ICU_PERIERR_STAT0_ER_ST2_Pos        (2UL)          /*!< ER_ST2 (Bit 2)                                        */
43752  #define R_ICU_PERIERR_STAT0_ER_ST2_Msk        (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
43753  #define R_ICU_PERIERR_STAT0_ER_ST3_Pos        (3UL)          /*!< ER_ST3 (Bit 3)                                        */
43754  #define R_ICU_PERIERR_STAT0_ER_ST3_Msk        (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
43755  #define R_ICU_PERIERR_STAT0_ER_ST4_Pos        (4UL)          /*!< ER_ST4 (Bit 4)                                        */
43756  #define R_ICU_PERIERR_STAT0_ER_ST4_Msk        (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
43757  #define R_ICU_PERIERR_STAT0_ER_ST5_Pos        (5UL)          /*!< ER_ST5 (Bit 5)                                        */
43758  #define R_ICU_PERIERR_STAT0_ER_ST5_Msk        (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
43759  #define R_ICU_PERIERR_STAT0_ER_ST6_Pos        (6UL)          /*!< ER_ST6 (Bit 6)                                        */
43760  #define R_ICU_PERIERR_STAT0_ER_ST6_Msk        (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
43761  #define R_ICU_PERIERR_STAT0_ER_ST7_Pos        (7UL)          /*!< ER_ST7 (Bit 7)                                        */
43762  #define R_ICU_PERIERR_STAT0_ER_ST7_Msk        (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
43763  #define R_ICU_PERIERR_STAT0_ER_ST9_Pos        (9UL)          /*!< ER_ST9 (Bit 9)                                        */
43764  #define R_ICU_PERIERR_STAT0_ER_ST9_Msk        (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
43765  #define R_ICU_PERIERR_STAT0_ER_ST10_Pos       (10UL)         /*!< ER_ST10 (Bit 10)                                      */
43766  #define R_ICU_PERIERR_STAT0_ER_ST10_Msk       (0x400UL)      /*!< ER_ST10 (Bitfield-Mask: 0x01)                         */
43767  #define R_ICU_PERIERR_STAT0_ER_ST11_Pos       (11UL)         /*!< ER_ST11 (Bit 11)                                      */
43768  #define R_ICU_PERIERR_STAT0_ER_ST11_Msk       (0x800UL)      /*!< ER_ST11 (Bitfield-Mask: 0x01)                         */
43769  #define R_ICU_PERIERR_STAT0_ER_ST12_Pos       (12UL)         /*!< ER_ST12 (Bit 12)                                      */
43770  #define R_ICU_PERIERR_STAT0_ER_ST12_Msk       (0x1000UL)     /*!< ER_ST12 (Bitfield-Mask: 0x01)                         */
43771  #define R_ICU_PERIERR_STAT0_ER_ST13_Pos       (13UL)         /*!< ER_ST13 (Bit 13)                                      */
43772  #define R_ICU_PERIERR_STAT0_ER_ST13_Msk       (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
43773  #define R_ICU_PERIERR_STAT0_ER_ST14_Pos       (14UL)         /*!< ER_ST14 (Bit 14)                                      */
43774  #define R_ICU_PERIERR_STAT0_ER_ST14_Msk       (0x4000UL)     /*!< ER_ST14 (Bitfield-Mask: 0x01)                         */
43775  #define R_ICU_PERIERR_STAT0_ER_ST15_Pos       (15UL)         /*!< ER_ST15 (Bit 15)                                      */
43776  #define R_ICU_PERIERR_STAT0_ER_ST15_Msk       (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
43777  #define R_ICU_PERIERR_STAT0_ER_ST16_Pos       (16UL)         /*!< ER_ST16 (Bit 16)                                      */
43778  #define R_ICU_PERIERR_STAT0_ER_ST16_Msk       (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
43779  #define R_ICU_PERIERR_STAT0_ER_ST17_Pos       (17UL)         /*!< ER_ST17 (Bit 17)                                      */
43780  #define R_ICU_PERIERR_STAT0_ER_ST17_Msk       (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
43781  #define R_ICU_PERIERR_STAT0_ER_ST18_Pos       (18UL)         /*!< ER_ST18 (Bit 18)                                      */
43782  #define R_ICU_PERIERR_STAT0_ER_ST18_Msk       (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
43783  #define R_ICU_PERIERR_STAT0_ER_ST19_Pos       (19UL)         /*!< ER_ST19 (Bit 19)                                      */
43784  #define R_ICU_PERIERR_STAT0_ER_ST19_Msk       (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
43785  #define R_ICU_PERIERR_STAT0_ER_ST20_Pos       (20UL)         /*!< ER_ST20 (Bit 20)                                      */
43786  #define R_ICU_PERIERR_STAT0_ER_ST20_Msk       (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
43787  #define R_ICU_PERIERR_STAT0_ER_ST21_Pos       (21UL)         /*!< ER_ST21 (Bit 21)                                      */
43788  #define R_ICU_PERIERR_STAT0_ER_ST21_Msk       (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
43789  #define R_ICU_PERIERR_STAT0_ER_ST22_Pos       (22UL)         /*!< ER_ST22 (Bit 22)                                      */
43790  #define R_ICU_PERIERR_STAT0_ER_ST22_Msk       (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
43791  #define R_ICU_PERIERR_STAT0_ER_ST23_Pos       (23UL)         /*!< ER_ST23 (Bit 23)                                      */
43792  #define R_ICU_PERIERR_STAT0_ER_ST23_Msk       (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
43793  #define R_ICU_PERIERR_STAT0_ER_ST24_Pos       (24UL)         /*!< ER_ST24 (Bit 24)                                      */
43794  #define R_ICU_PERIERR_STAT0_ER_ST24_Msk       (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
43795  #define R_ICU_PERIERR_STAT0_ER_ST25_Pos       (25UL)         /*!< ER_ST25 (Bit 25)                                      */
43796  #define R_ICU_PERIERR_STAT0_ER_ST25_Msk       (0x2000000UL)  /*!< ER_ST25 (Bitfield-Mask: 0x01)                         */
43797  #define R_ICU_PERIERR_STAT0_ER_ST26_Pos       (26UL)         /*!< ER_ST26 (Bit 26)                                      */
43798  #define R_ICU_PERIERR_STAT0_ER_ST26_Msk       (0x4000000UL)  /*!< ER_ST26 (Bitfield-Mask: 0x01)                         */
43799  #define R_ICU_PERIERR_STAT0_ER_ST27_Pos       (27UL)         /*!< ER_ST27 (Bit 27)                                      */
43800  #define R_ICU_PERIERR_STAT0_ER_ST27_Msk       (0x8000000UL)  /*!< ER_ST27 (Bitfield-Mask: 0x01)                         */
43801  #define R_ICU_PERIERR_STAT0_ER_ST28_Pos       (28UL)         /*!< ER_ST28 (Bit 28)                                      */
43802  #define R_ICU_PERIERR_STAT0_ER_ST28_Msk       (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01)                         */
43803  #define R_ICU_PERIERR_STAT0_ER_ST29_Pos       (29UL)         /*!< ER_ST29 (Bit 29)                                      */
43804  #define R_ICU_PERIERR_STAT0_ER_ST29_Msk       (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01)                         */
43805  #define R_ICU_PERIERR_STAT0_ER_ST30_Pos       (30UL)         /*!< ER_ST30 (Bit 30)                                      */
43806  #define R_ICU_PERIERR_STAT0_ER_ST30_Msk       (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01)                         */
43807  #define R_ICU_PERIERR_STAT0_ER_ST31_Pos       (31UL)         /*!< ER_ST31 (Bit 31)                                      */
43808  #define R_ICU_PERIERR_STAT0_ER_ST31_Msk       (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01)                         */
43809 /* =====================================================  PERIERR_STAT1  ===================================================== */
43810  #define R_ICU_PERIERR_STAT1_ER_ST0_Pos        (0UL)          /*!< ER_ST0 (Bit 0)                                        */
43811  #define R_ICU_PERIERR_STAT1_ER_ST0_Msk        (0x1UL)        /*!< ER_ST0 (Bitfield-Mask: 0x01)                          */
43812  #define R_ICU_PERIERR_STAT1_ER_ST1_Pos        (1UL)          /*!< ER_ST1 (Bit 1)                                        */
43813  #define R_ICU_PERIERR_STAT1_ER_ST1_Msk        (0x2UL)        /*!< ER_ST1 (Bitfield-Mask: 0x01)                          */
43814  #define R_ICU_PERIERR_STAT1_ER_ST2_Pos        (2UL)          /*!< ER_ST2 (Bit 2)                                        */
43815  #define R_ICU_PERIERR_STAT1_ER_ST2_Msk        (0x4UL)        /*!< ER_ST2 (Bitfield-Mask: 0x01)                          */
43816  #define R_ICU_PERIERR_STAT1_ER_ST3_Pos        (3UL)          /*!< ER_ST3 (Bit 3)                                        */
43817  #define R_ICU_PERIERR_STAT1_ER_ST3_Msk        (0x8UL)        /*!< ER_ST3 (Bitfield-Mask: 0x01)                          */
43818  #define R_ICU_PERIERR_STAT1_ER_ST4_Pos        (4UL)          /*!< ER_ST4 (Bit 4)                                        */
43819  #define R_ICU_PERIERR_STAT1_ER_ST4_Msk        (0x10UL)       /*!< ER_ST4 (Bitfield-Mask: 0x01)                          */
43820  #define R_ICU_PERIERR_STAT1_ER_ST5_Pos        (5UL)          /*!< ER_ST5 (Bit 5)                                        */
43821  #define R_ICU_PERIERR_STAT1_ER_ST5_Msk        (0x20UL)       /*!< ER_ST5 (Bitfield-Mask: 0x01)                          */
43822  #define R_ICU_PERIERR_STAT1_ER_ST6_Pos        (6UL)          /*!< ER_ST6 (Bit 6)                                        */
43823  #define R_ICU_PERIERR_STAT1_ER_ST6_Msk        (0x40UL)       /*!< ER_ST6 (Bitfield-Mask: 0x01)                          */
43824  #define R_ICU_PERIERR_STAT1_ER_ST7_Pos        (7UL)          /*!< ER_ST7 (Bit 7)                                        */
43825  #define R_ICU_PERIERR_STAT1_ER_ST7_Msk        (0x80UL)       /*!< ER_ST7 (Bitfield-Mask: 0x01)                          */
43826  #define R_ICU_PERIERR_STAT1_ER_ST8_Pos        (8UL)          /*!< ER_ST8 (Bit 8)                                        */
43827  #define R_ICU_PERIERR_STAT1_ER_ST8_Msk        (0x100UL)      /*!< ER_ST8 (Bitfield-Mask: 0x01)                          */
43828  #define R_ICU_PERIERR_STAT1_ER_ST9_Pos        (9UL)          /*!< ER_ST9 (Bit 9)                                        */
43829  #define R_ICU_PERIERR_STAT1_ER_ST9_Msk        (0x200UL)      /*!< ER_ST9 (Bitfield-Mask: 0x01)                          */
43830  #define R_ICU_PERIERR_STAT1_ER_ST13_Pos       (13UL)         /*!< ER_ST13 (Bit 13)                                      */
43831  #define R_ICU_PERIERR_STAT1_ER_ST13_Msk       (0x2000UL)     /*!< ER_ST13 (Bitfield-Mask: 0x01)                         */
43832  #define R_ICU_PERIERR_STAT1_ER_ST15_Pos       (15UL)         /*!< ER_ST15 (Bit 15)                                      */
43833  #define R_ICU_PERIERR_STAT1_ER_ST15_Msk       (0x8000UL)     /*!< ER_ST15 (Bitfield-Mask: 0x01)                         */
43834  #define R_ICU_PERIERR_STAT1_ER_ST16_Pos       (16UL)         /*!< ER_ST16 (Bit 16)                                      */
43835  #define R_ICU_PERIERR_STAT1_ER_ST16_Msk       (0x10000UL)    /*!< ER_ST16 (Bitfield-Mask: 0x01)                         */
43836  #define R_ICU_PERIERR_STAT1_ER_ST17_Pos       (17UL)         /*!< ER_ST17 (Bit 17)                                      */
43837  #define R_ICU_PERIERR_STAT1_ER_ST17_Msk       (0x20000UL)    /*!< ER_ST17 (Bitfield-Mask: 0x01)                         */
43838  #define R_ICU_PERIERR_STAT1_ER_ST18_Pos       (18UL)         /*!< ER_ST18 (Bit 18)                                      */
43839  #define R_ICU_PERIERR_STAT1_ER_ST18_Msk       (0x40000UL)    /*!< ER_ST18 (Bitfield-Mask: 0x01)                         */
43840  #define R_ICU_PERIERR_STAT1_ER_ST19_Pos       (19UL)         /*!< ER_ST19 (Bit 19)                                      */
43841  #define R_ICU_PERIERR_STAT1_ER_ST19_Msk       (0x80000UL)    /*!< ER_ST19 (Bitfield-Mask: 0x01)                         */
43842  #define R_ICU_PERIERR_STAT1_ER_ST20_Pos       (20UL)         /*!< ER_ST20 (Bit 20)                                      */
43843  #define R_ICU_PERIERR_STAT1_ER_ST20_Msk       (0x100000UL)   /*!< ER_ST20 (Bitfield-Mask: 0x01)                         */
43844  #define R_ICU_PERIERR_STAT1_ER_ST21_Pos       (21UL)         /*!< ER_ST21 (Bit 21)                                      */
43845  #define R_ICU_PERIERR_STAT1_ER_ST21_Msk       (0x200000UL)   /*!< ER_ST21 (Bitfield-Mask: 0x01)                         */
43846  #define R_ICU_PERIERR_STAT1_ER_ST22_Pos       (22UL)         /*!< ER_ST22 (Bit 22)                                      */
43847  #define R_ICU_PERIERR_STAT1_ER_ST22_Msk       (0x400000UL)   /*!< ER_ST22 (Bitfield-Mask: 0x01)                         */
43848  #define R_ICU_PERIERR_STAT1_ER_ST23_Pos       (23UL)         /*!< ER_ST23 (Bit 23)                                      */
43849  #define R_ICU_PERIERR_STAT1_ER_ST23_Msk       (0x800000UL)   /*!< ER_ST23 (Bitfield-Mask: 0x01)                         */
43850  #define R_ICU_PERIERR_STAT1_ER_ST24_Pos       (24UL)         /*!< ER_ST24 (Bit 24)                                      */
43851  #define R_ICU_PERIERR_STAT1_ER_ST24_Msk       (0x1000000UL)  /*!< ER_ST24 (Bitfield-Mask: 0x01)                         */
43852  #define R_ICU_PERIERR_STAT1_ER_ST27_Pos       (27UL)         /*!< ER_ST27 (Bit 27)                                      */
43853  #define R_ICU_PERIERR_STAT1_ER_ST27_Msk       (0x8000000UL)  /*!< ER_ST27 (Bitfield-Mask: 0x01)                         */
43854  #define R_ICU_PERIERR_STAT1_ER_ST28_Pos       (28UL)         /*!< ER_ST28 (Bit 28)                                      */
43855  #define R_ICU_PERIERR_STAT1_ER_ST28_Msk       (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01)                         */
43856 /* ======================================================  CPU0ERR_CLR  ====================================================== */
43857  #define R_ICU_CPU0ERR_CLR_ER_CL0_Pos          (0UL)          /*!< ER_CL0 (Bit 0)                                        */
43858  #define R_ICU_CPU0ERR_CLR_ER_CL0_Msk          (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
43859  #define R_ICU_CPU0ERR_CLR_ER_CL1_Pos          (1UL)          /*!< ER_CL1 (Bit 1)                                        */
43860  #define R_ICU_CPU0ERR_CLR_ER_CL1_Msk          (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
43861  #define R_ICU_CPU0ERR_CLR_ER_CL2_Pos          (2UL)          /*!< ER_CL2 (Bit 2)                                        */
43862  #define R_ICU_CPU0ERR_CLR_ER_CL2_Msk          (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
43863  #define R_ICU_CPU0ERR_CLR_ER_CL3_Pos          (3UL)          /*!< ER_CL3 (Bit 3)                                        */
43864  #define R_ICU_CPU0ERR_CLR_ER_CL3_Msk          (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
43865  #define R_ICU_CPU0ERR_CLR_ER_CL4_Pos          (4UL)          /*!< ER_CL4 (Bit 4)                                        */
43866  #define R_ICU_CPU0ERR_CLR_ER_CL4_Msk          (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
43867  #define R_ICU_CPU0ERR_CLR_ER_CL5_Pos          (5UL)          /*!< ER_CL5 (Bit 5)                                        */
43868  #define R_ICU_CPU0ERR_CLR_ER_CL5_Msk          (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
43869  #define R_ICU_CPU0ERR_CLR_ER_CL6_Pos          (6UL)          /*!< ER_CL6 (Bit 6)                                        */
43870  #define R_ICU_CPU0ERR_CLR_ER_CL6_Msk          (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
43871  #define R_ICU_CPU0ERR_CLR_ER_CL7_Pos          (7UL)          /*!< ER_CL7 (Bit 7)                                        */
43872  #define R_ICU_CPU0ERR_CLR_ER_CL7_Msk          (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
43873  #define R_ICU_CPU0ERR_CLR_ER_CL8_Pos          (8UL)          /*!< ER_CL8 (Bit 8)                                        */
43874  #define R_ICU_CPU0ERR_CLR_ER_CL8_Msk          (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
43875  #define R_ICU_CPU0ERR_CLR_ER_CL9_Pos          (9UL)          /*!< ER_CL9 (Bit 9)                                        */
43876  #define R_ICU_CPU0ERR_CLR_ER_CL9_Msk          (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
43877  #define R_ICU_CPU0ERR_CLR_ER_CL10_Pos         (10UL)         /*!< ER_CL10 (Bit 10)                                      */
43878  #define R_ICU_CPU0ERR_CLR_ER_CL10_Msk         (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
43879  #define R_ICU_CPU0ERR_CLR_ER_CL11_Pos         (11UL)         /*!< ER_CL11 (Bit 11)                                      */
43880  #define R_ICU_CPU0ERR_CLR_ER_CL11_Msk         (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
43881  #define R_ICU_CPU0ERR_CLR_ER_CL12_Pos         (12UL)         /*!< ER_CL12 (Bit 12)                                      */
43882  #define R_ICU_CPU0ERR_CLR_ER_CL12_Msk         (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
43883  #define R_ICU_CPU0ERR_CLR_ER_CL13_Pos         (13UL)         /*!< ER_CL13 (Bit 13)                                      */
43884  #define R_ICU_CPU0ERR_CLR_ER_CL13_Msk         (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
43885  #define R_ICU_CPU0ERR_CLR_ER_CL14_Pos         (14UL)         /*!< ER_CL14 (Bit 14)                                      */
43886  #define R_ICU_CPU0ERR_CLR_ER_CL14_Msk         (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
43887  #define R_ICU_CPU0ERR_CLR_ER_CL15_Pos         (15UL)         /*!< ER_CL15 (Bit 15)                                      */
43888  #define R_ICU_CPU0ERR_CLR_ER_CL15_Msk         (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
43889  #define R_ICU_CPU0ERR_CLR_ER_CL16_Pos         (16UL)         /*!< ER_CL16 (Bit 16)                                      */
43890  #define R_ICU_CPU0ERR_CLR_ER_CL16_Msk         (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
43891  #define R_ICU_CPU0ERR_CLR_ER_CL17_Pos         (17UL)         /*!< ER_CL17 (Bit 17)                                      */
43892  #define R_ICU_CPU0ERR_CLR_ER_CL17_Msk         (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
43893  #define R_ICU_CPU0ERR_CLR_ER_CL18_Pos         (18UL)         /*!< ER_CL18 (Bit 18)                                      */
43894  #define R_ICU_CPU0ERR_CLR_ER_CL18_Msk         (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
43895  #define R_ICU_CPU0ERR_CLR_ER_CL19_Pos         (19UL)         /*!< ER_CL19 (Bit 19)                                      */
43896  #define R_ICU_CPU0ERR_CLR_ER_CL19_Msk         (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
43897  #define R_ICU_CPU0ERR_CLR_ER_CL20_Pos         (20UL)         /*!< ER_CL20 (Bit 20)                                      */
43898  #define R_ICU_CPU0ERR_CLR_ER_CL20_Msk         (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
43899  #define R_ICU_CPU0ERR_CLR_ER_CL21_Pos         (21UL)         /*!< ER_CL21 (Bit 21)                                      */
43900  #define R_ICU_CPU0ERR_CLR_ER_CL21_Msk         (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
43901  #define R_ICU_CPU0ERR_CLR_ER_CL22_Pos         (22UL)         /*!< ER_CL22 (Bit 22)                                      */
43902  #define R_ICU_CPU0ERR_CLR_ER_CL22_Msk         (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
43903  #define R_ICU_CPU0ERR_CLR_ER_CL23_Pos         (23UL)         /*!< ER_CL23 (Bit 23)                                      */
43904  #define R_ICU_CPU0ERR_CLR_ER_CL23_Msk         (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
43905  #define R_ICU_CPU0ERR_CLR_ER_CL24_Pos         (24UL)         /*!< ER_CL24 (Bit 24)                                      */
43906  #define R_ICU_CPU0ERR_CLR_ER_CL24_Msk         (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
43907  #define R_ICU_CPU0ERR_CLR_ER_CL25_Pos         (25UL)         /*!< ER_CL25 (Bit 25)                                      */
43908  #define R_ICU_CPU0ERR_CLR_ER_CL25_Msk         (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
43909 /* =====================================================  PERIERR_CLR0  ====================================================== */
43910  #define R_ICU_PERIERR_CLR0_ER_CL0_Pos         (0UL)          /*!< ER_CL0 (Bit 0)                                        */
43911  #define R_ICU_PERIERR_CLR0_ER_CL0_Msk         (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
43912  #define R_ICU_PERIERR_CLR0_ER_CL1_Pos         (1UL)          /*!< ER_CL1 (Bit 1)                                        */
43913  #define R_ICU_PERIERR_CLR0_ER_CL1_Msk         (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
43914  #define R_ICU_PERIERR_CLR0_ER_CL2_Pos         (2UL)          /*!< ER_CL2 (Bit 2)                                        */
43915  #define R_ICU_PERIERR_CLR0_ER_CL2_Msk         (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
43916  #define R_ICU_PERIERR_CLR0_ER_CL3_Pos         (3UL)          /*!< ER_CL3 (Bit 3)                                        */
43917  #define R_ICU_PERIERR_CLR0_ER_CL3_Msk         (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
43918  #define R_ICU_PERIERR_CLR0_ER_CL4_Pos         (4UL)          /*!< ER_CL4 (Bit 4)                                        */
43919  #define R_ICU_PERIERR_CLR0_ER_CL4_Msk         (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
43920  #define R_ICU_PERIERR_CLR0_ER_CL5_Pos         (5UL)          /*!< ER_CL5 (Bit 5)                                        */
43921  #define R_ICU_PERIERR_CLR0_ER_CL5_Msk         (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
43922  #define R_ICU_PERIERR_CLR0_ER_CL6_Pos         (6UL)          /*!< ER_CL6 (Bit 6)                                        */
43923  #define R_ICU_PERIERR_CLR0_ER_CL6_Msk         (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
43924  #define R_ICU_PERIERR_CLR0_ER_CL7_Pos         (7UL)          /*!< ER_CL7 (Bit 7)                                        */
43925  #define R_ICU_PERIERR_CLR0_ER_CL7_Msk         (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
43926  #define R_ICU_PERIERR_CLR0_ER_CL9_Pos         (9UL)          /*!< ER_CL9 (Bit 9)                                        */
43927  #define R_ICU_PERIERR_CLR0_ER_CL9_Msk         (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
43928  #define R_ICU_PERIERR_CLR0_ER_CL10_Pos        (10UL)         /*!< ER_CL10 (Bit 10)                                      */
43929  #define R_ICU_PERIERR_CLR0_ER_CL10_Msk        (0x400UL)      /*!< ER_CL10 (Bitfield-Mask: 0x01)                         */
43930  #define R_ICU_PERIERR_CLR0_ER_CL11_Pos        (11UL)         /*!< ER_CL11 (Bit 11)                                      */
43931  #define R_ICU_PERIERR_CLR0_ER_CL11_Msk        (0x800UL)      /*!< ER_CL11 (Bitfield-Mask: 0x01)                         */
43932  #define R_ICU_PERIERR_CLR0_ER_CL12_Pos        (12UL)         /*!< ER_CL12 (Bit 12)                                      */
43933  #define R_ICU_PERIERR_CLR0_ER_CL12_Msk        (0x1000UL)     /*!< ER_CL12 (Bitfield-Mask: 0x01)                         */
43934  #define R_ICU_PERIERR_CLR0_ER_CL13_Pos        (13UL)         /*!< ER_CL13 (Bit 13)                                      */
43935  #define R_ICU_PERIERR_CLR0_ER_CL13_Msk        (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
43936  #define R_ICU_PERIERR_CLR0_ER_CL14_Pos        (14UL)         /*!< ER_CL14 (Bit 14)                                      */
43937  #define R_ICU_PERIERR_CLR0_ER_CL14_Msk        (0x4000UL)     /*!< ER_CL14 (Bitfield-Mask: 0x01)                         */
43938  #define R_ICU_PERIERR_CLR0_ER_CL15_Pos        (15UL)         /*!< ER_CL15 (Bit 15)                                      */
43939  #define R_ICU_PERIERR_CLR0_ER_CL15_Msk        (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
43940  #define R_ICU_PERIERR_CLR0_ER_CL16_Pos        (16UL)         /*!< ER_CL16 (Bit 16)                                      */
43941  #define R_ICU_PERIERR_CLR0_ER_CL16_Msk        (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
43942  #define R_ICU_PERIERR_CLR0_ER_CL17_Pos        (17UL)         /*!< ER_CL17 (Bit 17)                                      */
43943  #define R_ICU_PERIERR_CLR0_ER_CL17_Msk        (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
43944  #define R_ICU_PERIERR_CLR0_ER_CL18_Pos        (18UL)         /*!< ER_CL18 (Bit 18)                                      */
43945  #define R_ICU_PERIERR_CLR0_ER_CL18_Msk        (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
43946  #define R_ICU_PERIERR_CLR0_ER_CL19_Pos        (19UL)         /*!< ER_CL19 (Bit 19)                                      */
43947  #define R_ICU_PERIERR_CLR0_ER_CL19_Msk        (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
43948  #define R_ICU_PERIERR_CLR0_ER_CL20_Pos        (20UL)         /*!< ER_CL20 (Bit 20)                                      */
43949  #define R_ICU_PERIERR_CLR0_ER_CL20_Msk        (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
43950  #define R_ICU_PERIERR_CLR0_ER_CL21_Pos        (21UL)         /*!< ER_CL21 (Bit 21)                                      */
43951  #define R_ICU_PERIERR_CLR0_ER_CL21_Msk        (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
43952  #define R_ICU_PERIERR_CLR0_ER_CL22_Pos        (22UL)         /*!< ER_CL22 (Bit 22)                                      */
43953  #define R_ICU_PERIERR_CLR0_ER_CL22_Msk        (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
43954  #define R_ICU_PERIERR_CLR0_ER_CL23_Pos        (23UL)         /*!< ER_CL23 (Bit 23)                                      */
43955  #define R_ICU_PERIERR_CLR0_ER_CL23_Msk        (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
43956  #define R_ICU_PERIERR_CLR0_ER_CL24_Pos        (24UL)         /*!< ER_CL24 (Bit 24)                                      */
43957  #define R_ICU_PERIERR_CLR0_ER_CL24_Msk        (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
43958  #define R_ICU_PERIERR_CLR0_ER_CL25_Pos        (25UL)         /*!< ER_CL25 (Bit 25)                                      */
43959  #define R_ICU_PERIERR_CLR0_ER_CL25_Msk        (0x2000000UL)  /*!< ER_CL25 (Bitfield-Mask: 0x01)                         */
43960  #define R_ICU_PERIERR_CLR0_ER_CL26_Pos        (26UL)         /*!< ER_CL26 (Bit 26)                                      */
43961  #define R_ICU_PERIERR_CLR0_ER_CL26_Msk        (0x4000000UL)  /*!< ER_CL26 (Bitfield-Mask: 0x01)                         */
43962  #define R_ICU_PERIERR_CLR0_ER_CL27_Pos        (27UL)         /*!< ER_CL27 (Bit 27)                                      */
43963  #define R_ICU_PERIERR_CLR0_ER_CL27_Msk        (0x8000000UL)  /*!< ER_CL27 (Bitfield-Mask: 0x01)                         */
43964  #define R_ICU_PERIERR_CLR0_ER_CL28_Pos        (28UL)         /*!< ER_CL28 (Bit 28)                                      */
43965  #define R_ICU_PERIERR_CLR0_ER_CL28_Msk        (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01)                         */
43966  #define R_ICU_PERIERR_CLR0_ER_CL29_Pos        (29UL)         /*!< ER_CL29 (Bit 29)                                      */
43967  #define R_ICU_PERIERR_CLR0_ER_CL29_Msk        (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01)                         */
43968  #define R_ICU_PERIERR_CLR0_ER_CL30_Pos        (30UL)         /*!< ER_CL30 (Bit 30)                                      */
43969  #define R_ICU_PERIERR_CLR0_ER_CL30_Msk        (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01)                         */
43970  #define R_ICU_PERIERR_CLR0_ER_CL31_Pos        (31UL)         /*!< ER_CL31 (Bit 31)                                      */
43971  #define R_ICU_PERIERR_CLR0_ER_CL31_Msk        (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01)                         */
43972 /* =====================================================  PERIERR_CLR1  ====================================================== */
43973  #define R_ICU_PERIERR_CLR1_ER_CL0_Pos         (0UL)          /*!< ER_CL0 (Bit 0)                                        */
43974  #define R_ICU_PERIERR_CLR1_ER_CL0_Msk         (0x1UL)        /*!< ER_CL0 (Bitfield-Mask: 0x01)                          */
43975  #define R_ICU_PERIERR_CLR1_ER_CL1_Pos         (1UL)          /*!< ER_CL1 (Bit 1)                                        */
43976  #define R_ICU_PERIERR_CLR1_ER_CL1_Msk         (0x2UL)        /*!< ER_CL1 (Bitfield-Mask: 0x01)                          */
43977  #define R_ICU_PERIERR_CLR1_ER_CL2_Pos         (2UL)          /*!< ER_CL2 (Bit 2)                                        */
43978  #define R_ICU_PERIERR_CLR1_ER_CL2_Msk         (0x4UL)        /*!< ER_CL2 (Bitfield-Mask: 0x01)                          */
43979  #define R_ICU_PERIERR_CLR1_ER_CL3_Pos         (3UL)          /*!< ER_CL3 (Bit 3)                                        */
43980  #define R_ICU_PERIERR_CLR1_ER_CL3_Msk         (0x8UL)        /*!< ER_CL3 (Bitfield-Mask: 0x01)                          */
43981  #define R_ICU_PERIERR_CLR1_ER_CL4_Pos         (4UL)          /*!< ER_CL4 (Bit 4)                                        */
43982  #define R_ICU_PERIERR_CLR1_ER_CL4_Msk         (0x10UL)       /*!< ER_CL4 (Bitfield-Mask: 0x01)                          */
43983  #define R_ICU_PERIERR_CLR1_ER_CL5_Pos         (5UL)          /*!< ER_CL5 (Bit 5)                                        */
43984  #define R_ICU_PERIERR_CLR1_ER_CL5_Msk         (0x20UL)       /*!< ER_CL5 (Bitfield-Mask: 0x01)                          */
43985  #define R_ICU_PERIERR_CLR1_ER_CL6_Pos         (6UL)          /*!< ER_CL6 (Bit 6)                                        */
43986  #define R_ICU_PERIERR_CLR1_ER_CL6_Msk         (0x40UL)       /*!< ER_CL6 (Bitfield-Mask: 0x01)                          */
43987  #define R_ICU_PERIERR_CLR1_ER_CL7_Pos         (7UL)          /*!< ER_CL7 (Bit 7)                                        */
43988  #define R_ICU_PERIERR_CLR1_ER_CL7_Msk         (0x80UL)       /*!< ER_CL7 (Bitfield-Mask: 0x01)                          */
43989  #define R_ICU_PERIERR_CLR1_ER_CL8_Pos         (8UL)          /*!< ER_CL8 (Bit 8)                                        */
43990  #define R_ICU_PERIERR_CLR1_ER_CL8_Msk         (0x100UL)      /*!< ER_CL8 (Bitfield-Mask: 0x01)                          */
43991  #define R_ICU_PERIERR_CLR1_ER_CL9_Pos         (9UL)          /*!< ER_CL9 (Bit 9)                                        */
43992  #define R_ICU_PERIERR_CLR1_ER_CL9_Msk         (0x200UL)      /*!< ER_CL9 (Bitfield-Mask: 0x01)                          */
43993  #define R_ICU_PERIERR_CLR1_ER_CL13_Pos        (13UL)         /*!< ER_CL13 (Bit 13)                                      */
43994  #define R_ICU_PERIERR_CLR1_ER_CL13_Msk        (0x2000UL)     /*!< ER_CL13 (Bitfield-Mask: 0x01)                         */
43995  #define R_ICU_PERIERR_CLR1_ER_CL15_Pos        (15UL)         /*!< ER_CL15 (Bit 15)                                      */
43996  #define R_ICU_PERIERR_CLR1_ER_CL15_Msk        (0x8000UL)     /*!< ER_CL15 (Bitfield-Mask: 0x01)                         */
43997  #define R_ICU_PERIERR_CLR1_ER_CL16_Pos        (16UL)         /*!< ER_CL16 (Bit 16)                                      */
43998  #define R_ICU_PERIERR_CLR1_ER_CL16_Msk        (0x10000UL)    /*!< ER_CL16 (Bitfield-Mask: 0x01)                         */
43999  #define R_ICU_PERIERR_CLR1_ER_CL17_Pos        (17UL)         /*!< ER_CL17 (Bit 17)                                      */
44000  #define R_ICU_PERIERR_CLR1_ER_CL17_Msk        (0x20000UL)    /*!< ER_CL17 (Bitfield-Mask: 0x01)                         */
44001  #define R_ICU_PERIERR_CLR1_ER_CL18_Pos        (18UL)         /*!< ER_CL18 (Bit 18)                                      */
44002  #define R_ICU_PERIERR_CLR1_ER_CL18_Msk        (0x40000UL)    /*!< ER_CL18 (Bitfield-Mask: 0x01)                         */
44003  #define R_ICU_PERIERR_CLR1_ER_CL19_Pos        (19UL)         /*!< ER_CL19 (Bit 19)                                      */
44004  #define R_ICU_PERIERR_CLR1_ER_CL19_Msk        (0x80000UL)    /*!< ER_CL19 (Bitfield-Mask: 0x01)                         */
44005  #define R_ICU_PERIERR_CLR1_ER_CL20_Pos        (20UL)         /*!< ER_CL20 (Bit 20)                                      */
44006  #define R_ICU_PERIERR_CLR1_ER_CL20_Msk        (0x100000UL)   /*!< ER_CL20 (Bitfield-Mask: 0x01)                         */
44007  #define R_ICU_PERIERR_CLR1_ER_CL21_Pos        (21UL)         /*!< ER_CL21 (Bit 21)                                      */
44008  #define R_ICU_PERIERR_CLR1_ER_CL21_Msk        (0x200000UL)   /*!< ER_CL21 (Bitfield-Mask: 0x01)                         */
44009  #define R_ICU_PERIERR_CLR1_ER_CL22_Pos        (22UL)         /*!< ER_CL22 (Bit 22)                                      */
44010  #define R_ICU_PERIERR_CLR1_ER_CL22_Msk        (0x400000UL)   /*!< ER_CL22 (Bitfield-Mask: 0x01)                         */
44011  #define R_ICU_PERIERR_CLR1_ER_CL23_Pos        (23UL)         /*!< ER_CL23 (Bit 23)                                      */
44012  #define R_ICU_PERIERR_CLR1_ER_CL23_Msk        (0x800000UL)   /*!< ER_CL23 (Bitfield-Mask: 0x01)                         */
44013  #define R_ICU_PERIERR_CLR1_ER_CL24_Pos        (24UL)         /*!< ER_CL24 (Bit 24)                                      */
44014  #define R_ICU_PERIERR_CLR1_ER_CL24_Msk        (0x1000000UL)  /*!< ER_CL24 (Bitfield-Mask: 0x01)                         */
44015  #define R_ICU_PERIERR_CLR1_ER_CL27_Pos        (27UL)         /*!< ER_CL27 (Bit 27)                                      */
44016  #define R_ICU_PERIERR_CLR1_ER_CL27_Msk        (0x8000000UL)  /*!< ER_CL27 (Bitfield-Mask: 0x01)                         */
44017  #define R_ICU_PERIERR_CLR1_ER_CL28_Pos        (28UL)         /*!< ER_CL28 (Bit 28)                                      */
44018  #define R_ICU_PERIERR_CLR1_ER_CL28_Msk        (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01)                         */
44019 /* ====================================================  CPU0ERR_RSTMSK  ===================================================== */
44020  #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Pos       (0UL)          /*!< RS_MK0 (Bit 0)                                        */
44021  #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Msk       (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
44022  #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Pos       (1UL)          /*!< RS_MK1 (Bit 1)                                        */
44023  #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Msk       (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
44024  #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Pos       (2UL)          /*!< RS_MK2 (Bit 2)                                        */
44025  #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Msk       (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
44026  #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Pos       (3UL)          /*!< RS_MK3 (Bit 3)                                        */
44027  #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Msk       (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
44028  #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Pos       (4UL)          /*!< RS_MK4 (Bit 4)                                        */
44029  #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Msk       (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
44030  #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Pos       (5UL)          /*!< RS_MK5 (Bit 5)                                        */
44031  #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Msk       (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
44032  #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Pos       (6UL)          /*!< RS_MK6 (Bit 6)                                        */
44033  #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Msk       (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
44034  #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Pos       (7UL)          /*!< RS_MK7 (Bit 7)                                        */
44035  #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Msk       (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
44036  #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Pos       (8UL)          /*!< RS_MK8 (Bit 8)                                        */
44037  #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Msk       (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
44038  #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Pos       (9UL)          /*!< RS_MK9 (Bit 9)                                        */
44039  #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Msk       (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
44040  #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Pos      (10UL)         /*!< RS_MK10 (Bit 10)                                      */
44041  #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Msk      (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
44042  #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Pos      (11UL)         /*!< RS_MK11 (Bit 11)                                      */
44043  #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Msk      (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
44044  #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Pos      (12UL)         /*!< RS_MK12 (Bit 12)                                      */
44045  #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Msk      (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
44046  #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Pos      (13UL)         /*!< RS_MK13 (Bit 13)                                      */
44047  #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Msk      (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
44048  #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Pos      (14UL)         /*!< RS_MK14 (Bit 14)                                      */
44049  #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Msk      (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
44050  #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Pos      (15UL)         /*!< RS_MK15 (Bit 15)                                      */
44051  #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Msk      (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
44052  #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Pos      (16UL)         /*!< RS_MK16 (Bit 16)                                      */
44053  #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Msk      (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
44054  #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Pos      (17UL)         /*!< RS_MK17 (Bit 17)                                      */
44055  #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Msk      (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
44056  #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Pos      (18UL)         /*!< RS_MK18 (Bit 18)                                      */
44057  #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Msk      (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
44058  #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Pos      (19UL)         /*!< RS_MK19 (Bit 19)                                      */
44059  #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Msk      (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
44060  #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Pos      (20UL)         /*!< RS_MK20 (Bit 20)                                      */
44061  #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Msk      (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
44062  #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Pos      (21UL)         /*!< RS_MK21 (Bit 21)                                      */
44063  #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Msk      (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
44064  #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Pos      (22UL)         /*!< RS_MK22 (Bit 22)                                      */
44065  #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Msk      (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
44066  #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Pos      (23UL)         /*!< RS_MK23 (Bit 23)                                      */
44067  #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Msk      (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
44068  #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Pos      (24UL)         /*!< RS_MK24 (Bit 24)                                      */
44069  #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Msk      (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
44070  #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Pos      (25UL)         /*!< RS_MK25 (Bit 25)                                      */
44071  #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Msk      (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
44072 /* ====================================================  PERIERR_RSTMSK0  ==================================================== */
44073  #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Pos      (0UL)          /*!< RS_MK0 (Bit 0)                                        */
44074  #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Msk      (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
44075  #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Pos      (1UL)          /*!< RS_MK1 (Bit 1)                                        */
44076  #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Msk      (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
44077  #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Pos      (2UL)          /*!< RS_MK2 (Bit 2)                                        */
44078  #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Msk      (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
44079  #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Pos      (3UL)          /*!< RS_MK3 (Bit 3)                                        */
44080  #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Msk      (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
44081  #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Pos      (4UL)          /*!< RS_MK4 (Bit 4)                                        */
44082  #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Msk      (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
44083  #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Pos      (5UL)          /*!< RS_MK5 (Bit 5)                                        */
44084  #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Msk      (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
44085  #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Pos      (6UL)          /*!< RS_MK6 (Bit 6)                                        */
44086  #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Msk      (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
44087  #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Pos      (7UL)          /*!< RS_MK7 (Bit 7)                                        */
44088  #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Msk      (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
44089  #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Pos      (9UL)          /*!< RS_MK9 (Bit 9)                                        */
44090  #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Msk      (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
44091  #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Pos     (10UL)         /*!< RS_MK10 (Bit 10)                                      */
44092  #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Msk     (0x400UL)      /*!< RS_MK10 (Bitfield-Mask: 0x01)                         */
44093  #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Pos     (11UL)         /*!< RS_MK11 (Bit 11)                                      */
44094  #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Msk     (0x800UL)      /*!< RS_MK11 (Bitfield-Mask: 0x01)                         */
44095  #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Pos     (12UL)         /*!< RS_MK12 (Bit 12)                                      */
44096  #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Msk     (0x1000UL)     /*!< RS_MK12 (Bitfield-Mask: 0x01)                         */
44097  #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Pos     (13UL)         /*!< RS_MK13 (Bit 13)                                      */
44098  #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Msk     (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
44099  #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Pos     (14UL)         /*!< RS_MK14 (Bit 14)                                      */
44100  #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Msk     (0x4000UL)     /*!< RS_MK14 (Bitfield-Mask: 0x01)                         */
44101  #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Pos     (15UL)         /*!< RS_MK15 (Bit 15)                                      */
44102  #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Msk     (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
44103  #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Pos     (16UL)         /*!< RS_MK16 (Bit 16)                                      */
44104  #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Msk     (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
44105  #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Pos     (17UL)         /*!< RS_MK17 (Bit 17)                                      */
44106  #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Msk     (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
44107  #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Pos     (18UL)         /*!< RS_MK18 (Bit 18)                                      */
44108  #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Msk     (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
44109  #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Pos     (19UL)         /*!< RS_MK19 (Bit 19)                                      */
44110  #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Msk     (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
44111  #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Pos     (20UL)         /*!< RS_MK20 (Bit 20)                                      */
44112  #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Msk     (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
44113  #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Pos     (21UL)         /*!< RS_MK21 (Bit 21)                                      */
44114  #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Msk     (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
44115  #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Pos     (22UL)         /*!< RS_MK22 (Bit 22)                                      */
44116  #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Msk     (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
44117  #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Pos     (23UL)         /*!< RS_MK23 (Bit 23)                                      */
44118  #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Msk     (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
44119  #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Pos     (24UL)         /*!< RS_MK24 (Bit 24)                                      */
44120  #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Msk     (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
44121  #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Pos     (25UL)         /*!< RS_MK25 (Bit 25)                                      */
44122  #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Msk     (0x2000000UL)  /*!< RS_MK25 (Bitfield-Mask: 0x01)                         */
44123  #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Pos     (26UL)         /*!< RS_MK26 (Bit 26)                                      */
44124  #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Msk     (0x4000000UL)  /*!< RS_MK26 (Bitfield-Mask: 0x01)                         */
44125  #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Pos     (27UL)         /*!< RS_MK27 (Bit 27)                                      */
44126  #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Msk     (0x8000000UL)  /*!< RS_MK27 (Bitfield-Mask: 0x01)                         */
44127  #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Pos     (28UL)         /*!< RS_MK28 (Bit 28)                                      */
44128  #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Msk     (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01)                         */
44129  #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Pos     (29UL)         /*!< RS_MK29 (Bit 29)                                      */
44130  #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Msk     (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01)                         */
44131  #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Pos     (30UL)         /*!< RS_MK30 (Bit 30)                                      */
44132  #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Msk     (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01)                         */
44133  #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Pos     (31UL)         /*!< RS_MK31 (Bit 31)                                      */
44134  #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Msk     (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01)                         */
44135 /* ====================================================  PERIERR_RSTMSK1  ==================================================== */
44136  #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Pos      (0UL)          /*!< RS_MK0 (Bit 0)                                        */
44137  #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Msk      (0x1UL)        /*!< RS_MK0 (Bitfield-Mask: 0x01)                          */
44138  #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Pos      (1UL)          /*!< RS_MK1 (Bit 1)                                        */
44139  #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Msk      (0x2UL)        /*!< RS_MK1 (Bitfield-Mask: 0x01)                          */
44140  #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Pos      (2UL)          /*!< RS_MK2 (Bit 2)                                        */
44141  #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Msk      (0x4UL)        /*!< RS_MK2 (Bitfield-Mask: 0x01)                          */
44142  #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Pos      (3UL)          /*!< RS_MK3 (Bit 3)                                        */
44143  #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Msk      (0x8UL)        /*!< RS_MK3 (Bitfield-Mask: 0x01)                          */
44144  #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Pos      (4UL)          /*!< RS_MK4 (Bit 4)                                        */
44145  #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Msk      (0x10UL)       /*!< RS_MK4 (Bitfield-Mask: 0x01)                          */
44146  #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Pos      (5UL)          /*!< RS_MK5 (Bit 5)                                        */
44147  #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Msk      (0x20UL)       /*!< RS_MK5 (Bitfield-Mask: 0x01)                          */
44148  #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Pos      (6UL)          /*!< RS_MK6 (Bit 6)                                        */
44149  #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Msk      (0x40UL)       /*!< RS_MK6 (Bitfield-Mask: 0x01)                          */
44150  #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Pos      (7UL)          /*!< RS_MK7 (Bit 7)                                        */
44151  #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Msk      (0x80UL)       /*!< RS_MK7 (Bitfield-Mask: 0x01)                          */
44152  #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Pos      (8UL)          /*!< RS_MK8 (Bit 8)                                        */
44153  #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Msk      (0x100UL)      /*!< RS_MK8 (Bitfield-Mask: 0x01)                          */
44154  #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Pos      (9UL)          /*!< RS_MK9 (Bit 9)                                        */
44155  #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Msk      (0x200UL)      /*!< RS_MK9 (Bitfield-Mask: 0x01)                          */
44156  #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Pos     (13UL)         /*!< RS_MK13 (Bit 13)                                      */
44157  #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Msk     (0x2000UL)     /*!< RS_MK13 (Bitfield-Mask: 0x01)                         */
44158  #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Pos     (15UL)         /*!< RS_MK15 (Bit 15)                                      */
44159  #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Msk     (0x8000UL)     /*!< RS_MK15 (Bitfield-Mask: 0x01)                         */
44160  #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Pos     (16UL)         /*!< RS_MK16 (Bit 16)                                      */
44161  #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Msk     (0x10000UL)    /*!< RS_MK16 (Bitfield-Mask: 0x01)                         */
44162  #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Pos     (17UL)         /*!< RS_MK17 (Bit 17)                                      */
44163  #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Msk     (0x20000UL)    /*!< RS_MK17 (Bitfield-Mask: 0x01)                         */
44164  #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Pos     (18UL)         /*!< RS_MK18 (Bit 18)                                      */
44165  #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Msk     (0x40000UL)    /*!< RS_MK18 (Bitfield-Mask: 0x01)                         */
44166  #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Pos     (19UL)         /*!< RS_MK19 (Bit 19)                                      */
44167  #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Msk     (0x80000UL)    /*!< RS_MK19 (Bitfield-Mask: 0x01)                         */
44168  #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Pos     (20UL)         /*!< RS_MK20 (Bit 20)                                      */
44169  #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Msk     (0x100000UL)   /*!< RS_MK20 (Bitfield-Mask: 0x01)                         */
44170  #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Pos     (21UL)         /*!< RS_MK21 (Bit 21)                                      */
44171  #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Msk     (0x200000UL)   /*!< RS_MK21 (Bitfield-Mask: 0x01)                         */
44172  #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Pos     (22UL)         /*!< RS_MK22 (Bit 22)                                      */
44173  #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Msk     (0x400000UL)   /*!< RS_MK22 (Bitfield-Mask: 0x01)                         */
44174  #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Pos     (23UL)         /*!< RS_MK23 (Bit 23)                                      */
44175  #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Msk     (0x800000UL)   /*!< RS_MK23 (Bitfield-Mask: 0x01)                         */
44176  #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Pos     (24UL)         /*!< RS_MK24 (Bit 24)                                      */
44177  #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Msk     (0x1000000UL)  /*!< RS_MK24 (Bitfield-Mask: 0x01)                         */
44178  #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Pos     (27UL)         /*!< RS_MK27 (Bit 27)                                      */
44179  #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Msk     (0x8000000UL)  /*!< RS_MK27 (Bitfield-Mask: 0x01)                         */
44180  #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Pos     (28UL)         /*!< RS_MK28 (Bit 28)                                      */
44181  #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Msk     (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01)                         */
44182 /* =====================================================  CPU0ERR_E0MSK  ===================================================== */
44183  #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Pos        (0UL)          /*!< E0_MK0 (Bit 0)                                        */
44184  #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Msk        (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
44185  #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Pos        (1UL)          /*!< E0_MK1 (Bit 1)                                        */
44186  #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Msk        (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
44187  #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Pos        (2UL)          /*!< E0_MK2 (Bit 2)                                        */
44188  #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Msk        (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
44189  #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Pos        (3UL)          /*!< E0_MK3 (Bit 3)                                        */
44190  #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Msk        (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
44191  #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Pos        (4UL)          /*!< E0_MK4 (Bit 4)                                        */
44192  #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Msk        (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
44193  #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Pos        (5UL)          /*!< E0_MK5 (Bit 5)                                        */
44194  #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Msk        (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
44195  #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Pos        (6UL)          /*!< E0_MK6 (Bit 6)                                        */
44196  #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Msk        (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
44197  #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Pos        (7UL)          /*!< E0_MK7 (Bit 7)                                        */
44198  #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Msk        (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
44199  #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Pos        (8UL)          /*!< E0_MK8 (Bit 8)                                        */
44200  #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Msk        (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
44201  #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Pos        (9UL)          /*!< E0_MK9 (Bit 9)                                        */
44202  #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Msk        (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
44203  #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Pos       (10UL)         /*!< E0_MK10 (Bit 10)                                      */
44204  #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Msk       (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
44205  #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Pos       (11UL)         /*!< E0_MK11 (Bit 11)                                      */
44206  #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Msk       (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
44207  #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Pos       (12UL)         /*!< E0_MK12 (Bit 12)                                      */
44208  #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Msk       (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
44209  #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Pos       (13UL)         /*!< E0_MK13 (Bit 13)                                      */
44210  #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Msk       (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
44211  #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Pos       (14UL)         /*!< E0_MK14 (Bit 14)                                      */
44212  #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Msk       (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
44213  #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Pos       (15UL)         /*!< E0_MK15 (Bit 15)                                      */
44214  #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Msk       (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
44215  #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Pos       (16UL)         /*!< E0_MK16 (Bit 16)                                      */
44216  #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Msk       (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
44217  #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Pos       (17UL)         /*!< E0_MK17 (Bit 17)                                      */
44218  #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Msk       (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
44219  #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Pos       (18UL)         /*!< E0_MK18 (Bit 18)                                      */
44220  #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Msk       (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
44221  #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Pos       (19UL)         /*!< E0_MK19 (Bit 19)                                      */
44222  #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Msk       (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
44223  #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Pos       (20UL)         /*!< E0_MK20 (Bit 20)                                      */
44224  #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Msk       (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
44225  #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Pos       (21UL)         /*!< E0_MK21 (Bit 21)                                      */
44226  #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Msk       (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
44227  #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Pos       (22UL)         /*!< E0_MK22 (Bit 22)                                      */
44228  #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Msk       (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
44229  #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Pos       (23UL)         /*!< E0_MK23 (Bit 23)                                      */
44230  #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Msk       (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
44231  #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Pos       (24UL)         /*!< E0_MK24 (Bit 24)                                      */
44232  #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Msk       (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
44233  #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Pos       (25UL)         /*!< E0_MK25 (Bit 25)                                      */
44234  #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Msk       (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
44235 /* ====================================================  PERIERR_E0MSK0  ===================================================== */
44236  #define R_ICU_PERIERR_E0MSK0_E0_MK0_Pos       (0UL)          /*!< E0_MK0 (Bit 0)                                        */
44237  #define R_ICU_PERIERR_E0MSK0_E0_MK0_Msk       (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
44238  #define R_ICU_PERIERR_E0MSK0_E0_MK1_Pos       (1UL)          /*!< E0_MK1 (Bit 1)                                        */
44239  #define R_ICU_PERIERR_E0MSK0_E0_MK1_Msk       (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
44240  #define R_ICU_PERIERR_E0MSK0_E0_MK2_Pos       (2UL)          /*!< E0_MK2 (Bit 2)                                        */
44241  #define R_ICU_PERIERR_E0MSK0_E0_MK2_Msk       (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
44242  #define R_ICU_PERIERR_E0MSK0_E0_MK3_Pos       (3UL)          /*!< E0_MK3 (Bit 3)                                        */
44243  #define R_ICU_PERIERR_E0MSK0_E0_MK3_Msk       (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
44244  #define R_ICU_PERIERR_E0MSK0_E0_MK4_Pos       (4UL)          /*!< E0_MK4 (Bit 4)                                        */
44245  #define R_ICU_PERIERR_E0MSK0_E0_MK4_Msk       (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
44246  #define R_ICU_PERIERR_E0MSK0_E0_MK5_Pos       (5UL)          /*!< E0_MK5 (Bit 5)                                        */
44247  #define R_ICU_PERIERR_E0MSK0_E0_MK5_Msk       (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
44248  #define R_ICU_PERIERR_E0MSK0_E0_MK6_Pos       (6UL)          /*!< E0_MK6 (Bit 6)                                        */
44249  #define R_ICU_PERIERR_E0MSK0_E0_MK6_Msk       (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
44250  #define R_ICU_PERIERR_E0MSK0_E0_MK7_Pos       (7UL)          /*!< E0_MK7 (Bit 7)                                        */
44251  #define R_ICU_PERIERR_E0MSK0_E0_MK7_Msk       (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
44252  #define R_ICU_PERIERR_E0MSK0_E0_MK9_Pos       (9UL)          /*!< E0_MK9 (Bit 9)                                        */
44253  #define R_ICU_PERIERR_E0MSK0_E0_MK9_Msk       (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
44254  #define R_ICU_PERIERR_E0MSK0_E0_MK10_Pos      (10UL)         /*!< E0_MK10 (Bit 10)                                      */
44255  #define R_ICU_PERIERR_E0MSK0_E0_MK10_Msk      (0x400UL)      /*!< E0_MK10 (Bitfield-Mask: 0x01)                         */
44256  #define R_ICU_PERIERR_E0MSK0_E0_MK11_Pos      (11UL)         /*!< E0_MK11 (Bit 11)                                      */
44257  #define R_ICU_PERIERR_E0MSK0_E0_MK11_Msk      (0x800UL)      /*!< E0_MK11 (Bitfield-Mask: 0x01)                         */
44258  #define R_ICU_PERIERR_E0MSK0_E0_MK12_Pos      (12UL)         /*!< E0_MK12 (Bit 12)                                      */
44259  #define R_ICU_PERIERR_E0MSK0_E0_MK12_Msk      (0x1000UL)     /*!< E0_MK12 (Bitfield-Mask: 0x01)                         */
44260  #define R_ICU_PERIERR_E0MSK0_E0_MK13_Pos      (13UL)         /*!< E0_MK13 (Bit 13)                                      */
44261  #define R_ICU_PERIERR_E0MSK0_E0_MK13_Msk      (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
44262  #define R_ICU_PERIERR_E0MSK0_E0_MK14_Pos      (14UL)         /*!< E0_MK14 (Bit 14)                                      */
44263  #define R_ICU_PERIERR_E0MSK0_E0_MK14_Msk      (0x4000UL)     /*!< E0_MK14 (Bitfield-Mask: 0x01)                         */
44264  #define R_ICU_PERIERR_E0MSK0_E0_MK15_Pos      (15UL)         /*!< E0_MK15 (Bit 15)                                      */
44265  #define R_ICU_PERIERR_E0MSK0_E0_MK15_Msk      (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
44266  #define R_ICU_PERIERR_E0MSK0_E0_MK16_Pos      (16UL)         /*!< E0_MK16 (Bit 16)                                      */
44267  #define R_ICU_PERIERR_E0MSK0_E0_MK16_Msk      (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
44268  #define R_ICU_PERIERR_E0MSK0_E0_MK17_Pos      (17UL)         /*!< E0_MK17 (Bit 17)                                      */
44269  #define R_ICU_PERIERR_E0MSK0_E0_MK17_Msk      (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
44270  #define R_ICU_PERIERR_E0MSK0_E0_MK18_Pos      (18UL)         /*!< E0_MK18 (Bit 18)                                      */
44271  #define R_ICU_PERIERR_E0MSK0_E0_MK18_Msk      (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
44272  #define R_ICU_PERIERR_E0MSK0_E0_MK19_Pos      (19UL)         /*!< E0_MK19 (Bit 19)                                      */
44273  #define R_ICU_PERIERR_E0MSK0_E0_MK19_Msk      (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
44274  #define R_ICU_PERIERR_E0MSK0_E0_MK20_Pos      (20UL)         /*!< E0_MK20 (Bit 20)                                      */
44275  #define R_ICU_PERIERR_E0MSK0_E0_MK20_Msk      (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
44276  #define R_ICU_PERIERR_E0MSK0_E0_MK21_Pos      (21UL)         /*!< E0_MK21 (Bit 21)                                      */
44277  #define R_ICU_PERIERR_E0MSK0_E0_MK21_Msk      (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
44278  #define R_ICU_PERIERR_E0MSK0_E0_MK22_Pos      (22UL)         /*!< E0_MK22 (Bit 22)                                      */
44279  #define R_ICU_PERIERR_E0MSK0_E0_MK22_Msk      (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
44280  #define R_ICU_PERIERR_E0MSK0_E0_MK23_Pos      (23UL)         /*!< E0_MK23 (Bit 23)                                      */
44281  #define R_ICU_PERIERR_E0MSK0_E0_MK23_Msk      (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
44282  #define R_ICU_PERIERR_E0MSK0_E0_MK24_Pos      (24UL)         /*!< E0_MK24 (Bit 24)                                      */
44283  #define R_ICU_PERIERR_E0MSK0_E0_MK24_Msk      (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
44284  #define R_ICU_PERIERR_E0MSK0_E0_MK25_Pos      (25UL)         /*!< E0_MK25 (Bit 25)                                      */
44285  #define R_ICU_PERIERR_E0MSK0_E0_MK25_Msk      (0x2000000UL)  /*!< E0_MK25 (Bitfield-Mask: 0x01)                         */
44286  #define R_ICU_PERIERR_E0MSK0_E0_MK26_Pos      (26UL)         /*!< E0_MK26 (Bit 26)                                      */
44287  #define R_ICU_PERIERR_E0MSK0_E0_MK26_Msk      (0x4000000UL)  /*!< E0_MK26 (Bitfield-Mask: 0x01)                         */
44288  #define R_ICU_PERIERR_E0MSK0_E0_MK27_Pos      (27UL)         /*!< E0_MK27 (Bit 27)                                      */
44289  #define R_ICU_PERIERR_E0MSK0_E0_MK27_Msk      (0x8000000UL)  /*!< E0_MK27 (Bitfield-Mask: 0x01)                         */
44290  #define R_ICU_PERIERR_E0MSK0_E0_MK28_Pos      (28UL)         /*!< E0_MK28 (Bit 28)                                      */
44291  #define R_ICU_PERIERR_E0MSK0_E0_MK28_Msk      (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01)                         */
44292  #define R_ICU_PERIERR_E0MSK0_E0_MK29_Pos      (29UL)         /*!< E0_MK29 (Bit 29)                                      */
44293  #define R_ICU_PERIERR_E0MSK0_E0_MK29_Msk      (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01)                         */
44294  #define R_ICU_PERIERR_E0MSK0_E0_MK30_Pos      (30UL)         /*!< E0_MK30 (Bit 30)                                      */
44295  #define R_ICU_PERIERR_E0MSK0_E0_MK30_Msk      (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01)                         */
44296  #define R_ICU_PERIERR_E0MSK0_E0_MK31_Pos      (31UL)         /*!< E0_MK31 (Bit 31)                                      */
44297  #define R_ICU_PERIERR_E0MSK0_E0_MK31_Msk      (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01)                         */
44298 /* ====================================================  PERIERR_E0MSK1  ===================================================== */
44299  #define R_ICU_PERIERR_E0MSK1_E0_MK0_Pos       (0UL)          /*!< E0_MK0 (Bit 0)                                        */
44300  #define R_ICU_PERIERR_E0MSK1_E0_MK0_Msk       (0x1UL)        /*!< E0_MK0 (Bitfield-Mask: 0x01)                          */
44301  #define R_ICU_PERIERR_E0MSK1_E0_MK1_Pos       (1UL)          /*!< E0_MK1 (Bit 1)                                        */
44302  #define R_ICU_PERIERR_E0MSK1_E0_MK1_Msk       (0x2UL)        /*!< E0_MK1 (Bitfield-Mask: 0x01)                          */
44303  #define R_ICU_PERIERR_E0MSK1_E0_MK2_Pos       (2UL)          /*!< E0_MK2 (Bit 2)                                        */
44304  #define R_ICU_PERIERR_E0MSK1_E0_MK2_Msk       (0x4UL)        /*!< E0_MK2 (Bitfield-Mask: 0x01)                          */
44305  #define R_ICU_PERIERR_E0MSK1_E0_MK3_Pos       (3UL)          /*!< E0_MK3 (Bit 3)                                        */
44306  #define R_ICU_PERIERR_E0MSK1_E0_MK3_Msk       (0x8UL)        /*!< E0_MK3 (Bitfield-Mask: 0x01)                          */
44307  #define R_ICU_PERIERR_E0MSK1_E0_MK4_Pos       (4UL)          /*!< E0_MK4 (Bit 4)                                        */
44308  #define R_ICU_PERIERR_E0MSK1_E0_MK4_Msk       (0x10UL)       /*!< E0_MK4 (Bitfield-Mask: 0x01)                          */
44309  #define R_ICU_PERIERR_E0MSK1_E0_MK5_Pos       (5UL)          /*!< E0_MK5 (Bit 5)                                        */
44310  #define R_ICU_PERIERR_E0MSK1_E0_MK5_Msk       (0x20UL)       /*!< E0_MK5 (Bitfield-Mask: 0x01)                          */
44311  #define R_ICU_PERIERR_E0MSK1_E0_MK6_Pos       (6UL)          /*!< E0_MK6 (Bit 6)                                        */
44312  #define R_ICU_PERIERR_E0MSK1_E0_MK6_Msk       (0x40UL)       /*!< E0_MK6 (Bitfield-Mask: 0x01)                          */
44313  #define R_ICU_PERIERR_E0MSK1_E0_MK7_Pos       (7UL)          /*!< E0_MK7 (Bit 7)                                        */
44314  #define R_ICU_PERIERR_E0MSK1_E0_MK7_Msk       (0x80UL)       /*!< E0_MK7 (Bitfield-Mask: 0x01)                          */
44315  #define R_ICU_PERIERR_E0MSK1_E0_MK8_Pos       (8UL)          /*!< E0_MK8 (Bit 8)                                        */
44316  #define R_ICU_PERIERR_E0MSK1_E0_MK8_Msk       (0x100UL)      /*!< E0_MK8 (Bitfield-Mask: 0x01)                          */
44317  #define R_ICU_PERIERR_E0MSK1_E0_MK9_Pos       (9UL)          /*!< E0_MK9 (Bit 9)                                        */
44318  #define R_ICU_PERIERR_E0MSK1_E0_MK9_Msk       (0x200UL)      /*!< E0_MK9 (Bitfield-Mask: 0x01)                          */
44319  #define R_ICU_PERIERR_E0MSK1_E0_MK13_Pos      (13UL)         /*!< E0_MK13 (Bit 13)                                      */
44320  #define R_ICU_PERIERR_E0MSK1_E0_MK13_Msk      (0x2000UL)     /*!< E0_MK13 (Bitfield-Mask: 0x01)                         */
44321  #define R_ICU_PERIERR_E0MSK1_E0_MK15_Pos      (15UL)         /*!< E0_MK15 (Bit 15)                                      */
44322  #define R_ICU_PERIERR_E0MSK1_E0_MK15_Msk      (0x8000UL)     /*!< E0_MK15 (Bitfield-Mask: 0x01)                         */
44323  #define R_ICU_PERIERR_E0MSK1_E0_MK16_Pos      (16UL)         /*!< E0_MK16 (Bit 16)                                      */
44324  #define R_ICU_PERIERR_E0MSK1_E0_MK16_Msk      (0x10000UL)    /*!< E0_MK16 (Bitfield-Mask: 0x01)                         */
44325  #define R_ICU_PERIERR_E0MSK1_E0_MK17_Pos      (17UL)         /*!< E0_MK17 (Bit 17)                                      */
44326  #define R_ICU_PERIERR_E0MSK1_E0_MK17_Msk      (0x20000UL)    /*!< E0_MK17 (Bitfield-Mask: 0x01)                         */
44327  #define R_ICU_PERIERR_E0MSK1_E0_MK18_Pos      (18UL)         /*!< E0_MK18 (Bit 18)                                      */
44328  #define R_ICU_PERIERR_E0MSK1_E0_MK18_Msk      (0x40000UL)    /*!< E0_MK18 (Bitfield-Mask: 0x01)                         */
44329  #define R_ICU_PERIERR_E0MSK1_E0_MK19_Pos      (19UL)         /*!< E0_MK19 (Bit 19)                                      */
44330  #define R_ICU_PERIERR_E0MSK1_E0_MK19_Msk      (0x80000UL)    /*!< E0_MK19 (Bitfield-Mask: 0x01)                         */
44331  #define R_ICU_PERIERR_E0MSK1_E0_MK20_Pos      (20UL)         /*!< E0_MK20 (Bit 20)                                      */
44332  #define R_ICU_PERIERR_E0MSK1_E0_MK20_Msk      (0x100000UL)   /*!< E0_MK20 (Bitfield-Mask: 0x01)                         */
44333  #define R_ICU_PERIERR_E0MSK1_E0_MK21_Pos      (21UL)         /*!< E0_MK21 (Bit 21)                                      */
44334  #define R_ICU_PERIERR_E0MSK1_E0_MK21_Msk      (0x200000UL)   /*!< E0_MK21 (Bitfield-Mask: 0x01)                         */
44335  #define R_ICU_PERIERR_E0MSK1_E0_MK22_Pos      (22UL)         /*!< E0_MK22 (Bit 22)                                      */
44336  #define R_ICU_PERIERR_E0MSK1_E0_MK22_Msk      (0x400000UL)   /*!< E0_MK22 (Bitfield-Mask: 0x01)                         */
44337  #define R_ICU_PERIERR_E0MSK1_E0_MK23_Pos      (23UL)         /*!< E0_MK23 (Bit 23)                                      */
44338  #define R_ICU_PERIERR_E0MSK1_E0_MK23_Msk      (0x800000UL)   /*!< E0_MK23 (Bitfield-Mask: 0x01)                         */
44339  #define R_ICU_PERIERR_E0MSK1_E0_MK24_Pos      (24UL)         /*!< E0_MK24 (Bit 24)                                      */
44340  #define R_ICU_PERIERR_E0MSK1_E0_MK24_Msk      (0x1000000UL)  /*!< E0_MK24 (Bitfield-Mask: 0x01)                         */
44341  #define R_ICU_PERIERR_E0MSK1_E0_MK27_Pos      (27UL)         /*!< E0_MK27 (Bit 27)                                      */
44342  #define R_ICU_PERIERR_E0MSK1_E0_MK27_Msk      (0x8000000UL)  /*!< E0_MK27 (Bitfield-Mask: 0x01)                         */
44343  #define R_ICU_PERIERR_E0MSK1_E0_MK28_Pos      (28UL)         /*!< E0_MK28 (Bit 28)                                      */
44344  #define R_ICU_PERIERR_E0MSK1_E0_MK28_Msk      (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01)                         */
44345 /* =====================================================  CPU0ERR_E1MSK  ===================================================== */
44346  #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Pos        (0UL)          /*!< E1_MK0 (Bit 0)                                        */
44347  #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Msk        (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
44348  #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Pos        (1UL)          /*!< E1_MK1 (Bit 1)                                        */
44349  #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Msk        (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
44350  #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Pos        (2UL)          /*!< E1_MK2 (Bit 2)                                        */
44351  #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Msk        (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
44352  #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Pos        (3UL)          /*!< E1_MK3 (Bit 3)                                        */
44353  #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Msk        (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
44354  #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Pos        (4UL)          /*!< E1_MK4 (Bit 4)                                        */
44355  #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Msk        (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
44356  #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Pos        (5UL)          /*!< E1_MK5 (Bit 5)                                        */
44357  #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Msk        (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
44358  #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Pos        (6UL)          /*!< E1_MK6 (Bit 6)                                        */
44359  #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Msk        (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
44360  #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Pos        (7UL)          /*!< E1_MK7 (Bit 7)                                        */
44361  #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Msk        (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
44362  #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Pos        (8UL)          /*!< E1_MK8 (Bit 8)                                        */
44363  #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Msk        (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
44364  #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Pos        (9UL)          /*!< E1_MK9 (Bit 9)                                        */
44365  #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Msk        (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
44366  #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Pos       (10UL)         /*!< E1_MK10 (Bit 10)                                      */
44367  #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Msk       (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
44368  #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Pos       (11UL)         /*!< E1_MK11 (Bit 11)                                      */
44369  #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Msk       (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
44370  #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Pos       (12UL)         /*!< E1_MK12 (Bit 12)                                      */
44371  #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Msk       (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
44372  #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Pos       (13UL)         /*!< E1_MK13 (Bit 13)                                      */
44373  #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Msk       (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
44374  #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Pos       (14UL)         /*!< E1_MK14 (Bit 14)                                      */
44375  #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Msk       (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
44376  #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Pos       (15UL)         /*!< E1_MK15 (Bit 15)                                      */
44377  #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Msk       (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
44378  #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Pos       (16UL)         /*!< E1_MK16 (Bit 16)                                      */
44379  #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Msk       (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
44380  #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Pos       (17UL)         /*!< E1_MK17 (Bit 17)                                      */
44381  #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Msk       (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
44382  #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Pos       (18UL)         /*!< E1_MK18 (Bit 18)                                      */
44383  #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Msk       (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
44384  #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Pos       (19UL)         /*!< E1_MK19 (Bit 19)                                      */
44385  #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Msk       (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
44386  #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Pos       (20UL)         /*!< E1_MK20 (Bit 20)                                      */
44387  #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Msk       (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
44388  #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Pos       (21UL)         /*!< E1_MK21 (Bit 21)                                      */
44389  #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Msk       (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
44390  #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Pos       (22UL)         /*!< E1_MK22 (Bit 22)                                      */
44391  #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Msk       (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
44392  #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Pos       (23UL)         /*!< E1_MK23 (Bit 23)                                      */
44393  #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Msk       (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
44394  #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Pos       (24UL)         /*!< E1_MK24 (Bit 24)                                      */
44395  #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Msk       (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
44396  #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Pos       (25UL)         /*!< E1_MK25 (Bit 25)                                      */
44397  #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Msk       (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
44398 /* ====================================================  PERIERR_E1MSK0  ===================================================== */
44399  #define R_ICU_PERIERR_E1MSK0_E1_MK0_Pos       (0UL)          /*!< E1_MK0 (Bit 0)                                        */
44400  #define R_ICU_PERIERR_E1MSK0_E1_MK0_Msk       (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
44401  #define R_ICU_PERIERR_E1MSK0_E1_MK1_Pos       (1UL)          /*!< E1_MK1 (Bit 1)                                        */
44402  #define R_ICU_PERIERR_E1MSK0_E1_MK1_Msk       (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
44403  #define R_ICU_PERIERR_E1MSK0_E1_MK2_Pos       (2UL)          /*!< E1_MK2 (Bit 2)                                        */
44404  #define R_ICU_PERIERR_E1MSK0_E1_MK2_Msk       (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
44405  #define R_ICU_PERIERR_E1MSK0_E1_MK3_Pos       (3UL)          /*!< E1_MK3 (Bit 3)                                        */
44406  #define R_ICU_PERIERR_E1MSK0_E1_MK3_Msk       (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
44407  #define R_ICU_PERIERR_E1MSK0_E1_MK4_Pos       (4UL)          /*!< E1_MK4 (Bit 4)                                        */
44408  #define R_ICU_PERIERR_E1MSK0_E1_MK4_Msk       (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
44409  #define R_ICU_PERIERR_E1MSK0_E1_MK5_Pos       (5UL)          /*!< E1_MK5 (Bit 5)                                        */
44410  #define R_ICU_PERIERR_E1MSK0_E1_MK5_Msk       (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
44411  #define R_ICU_PERIERR_E1MSK0_E1_MK6_Pos       (6UL)          /*!< E1_MK6 (Bit 6)                                        */
44412  #define R_ICU_PERIERR_E1MSK0_E1_MK6_Msk       (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
44413  #define R_ICU_PERIERR_E1MSK0_E1_MK7_Pos       (7UL)          /*!< E1_MK7 (Bit 7)                                        */
44414  #define R_ICU_PERIERR_E1MSK0_E1_MK7_Msk       (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
44415  #define R_ICU_PERIERR_E1MSK0_E1_MK9_Pos       (9UL)          /*!< E1_MK9 (Bit 9)                                        */
44416  #define R_ICU_PERIERR_E1MSK0_E1_MK9_Msk       (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
44417  #define R_ICU_PERIERR_E1MSK0_E1_MK10_Pos      (10UL)         /*!< E1_MK10 (Bit 10)                                      */
44418  #define R_ICU_PERIERR_E1MSK0_E1_MK10_Msk      (0x400UL)      /*!< E1_MK10 (Bitfield-Mask: 0x01)                         */
44419  #define R_ICU_PERIERR_E1MSK0_E1_MK11_Pos      (11UL)         /*!< E1_MK11 (Bit 11)                                      */
44420  #define R_ICU_PERIERR_E1MSK0_E1_MK11_Msk      (0x800UL)      /*!< E1_MK11 (Bitfield-Mask: 0x01)                         */
44421  #define R_ICU_PERIERR_E1MSK0_E1_MK12_Pos      (12UL)         /*!< E1_MK12 (Bit 12)                                      */
44422  #define R_ICU_PERIERR_E1MSK0_E1_MK12_Msk      (0x1000UL)     /*!< E1_MK12 (Bitfield-Mask: 0x01)                         */
44423  #define R_ICU_PERIERR_E1MSK0_E1_MK13_Pos      (13UL)         /*!< E1_MK13 (Bit 13)                                      */
44424  #define R_ICU_PERIERR_E1MSK0_E1_MK13_Msk      (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
44425  #define R_ICU_PERIERR_E1MSK0_E1_MK14_Pos      (14UL)         /*!< E1_MK14 (Bit 14)                                      */
44426  #define R_ICU_PERIERR_E1MSK0_E1_MK14_Msk      (0x4000UL)     /*!< E1_MK14 (Bitfield-Mask: 0x01)                         */
44427  #define R_ICU_PERIERR_E1MSK0_E1_MK15_Pos      (15UL)         /*!< E1_MK15 (Bit 15)                                      */
44428  #define R_ICU_PERIERR_E1MSK0_E1_MK15_Msk      (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
44429  #define R_ICU_PERIERR_E1MSK0_E1_MK16_Pos      (16UL)         /*!< E1_MK16 (Bit 16)                                      */
44430  #define R_ICU_PERIERR_E1MSK0_E1_MK16_Msk      (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
44431  #define R_ICU_PERIERR_E1MSK0_E1_MK17_Pos      (17UL)         /*!< E1_MK17 (Bit 17)                                      */
44432  #define R_ICU_PERIERR_E1MSK0_E1_MK17_Msk      (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
44433  #define R_ICU_PERIERR_E1MSK0_E1_MK18_Pos      (18UL)         /*!< E1_MK18 (Bit 18)                                      */
44434  #define R_ICU_PERIERR_E1MSK0_E1_MK18_Msk      (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
44435  #define R_ICU_PERIERR_E1MSK0_E1_MK19_Pos      (19UL)         /*!< E1_MK19 (Bit 19)                                      */
44436  #define R_ICU_PERIERR_E1MSK0_E1_MK19_Msk      (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
44437  #define R_ICU_PERIERR_E1MSK0_E1_MK20_Pos      (20UL)         /*!< E1_MK20 (Bit 20)                                      */
44438  #define R_ICU_PERIERR_E1MSK0_E1_MK20_Msk      (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
44439  #define R_ICU_PERIERR_E1MSK0_E1_MK21_Pos      (21UL)         /*!< E1_MK21 (Bit 21)                                      */
44440  #define R_ICU_PERIERR_E1MSK0_E1_MK21_Msk      (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
44441  #define R_ICU_PERIERR_E1MSK0_E1_MK22_Pos      (22UL)         /*!< E1_MK22 (Bit 22)                                      */
44442  #define R_ICU_PERIERR_E1MSK0_E1_MK22_Msk      (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
44443  #define R_ICU_PERIERR_E1MSK0_E1_MK23_Pos      (23UL)         /*!< E1_MK23 (Bit 23)                                      */
44444  #define R_ICU_PERIERR_E1MSK0_E1_MK23_Msk      (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
44445  #define R_ICU_PERIERR_E1MSK0_E1_MK24_Pos      (24UL)         /*!< E1_MK24 (Bit 24)                                      */
44446  #define R_ICU_PERIERR_E1MSK0_E1_MK24_Msk      (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
44447  #define R_ICU_PERIERR_E1MSK0_E1_MK25_Pos      (25UL)         /*!< E1_MK25 (Bit 25)                                      */
44448  #define R_ICU_PERIERR_E1MSK0_E1_MK25_Msk      (0x2000000UL)  /*!< E1_MK25 (Bitfield-Mask: 0x01)                         */
44449  #define R_ICU_PERIERR_E1MSK0_E1_MK26_Pos      (26UL)         /*!< E1_MK26 (Bit 26)                                      */
44450  #define R_ICU_PERIERR_E1MSK0_E1_MK26_Msk      (0x4000000UL)  /*!< E1_MK26 (Bitfield-Mask: 0x01)                         */
44451  #define R_ICU_PERIERR_E1MSK0_E1_MK27_Pos      (27UL)         /*!< E1_MK27 (Bit 27)                                      */
44452  #define R_ICU_PERIERR_E1MSK0_E1_MK27_Msk      (0x8000000UL)  /*!< E1_MK27 (Bitfield-Mask: 0x01)                         */
44453  #define R_ICU_PERIERR_E1MSK0_E1_MK28_Pos      (28UL)         /*!< E1_MK28 (Bit 28)                                      */
44454  #define R_ICU_PERIERR_E1MSK0_E1_MK28_Msk      (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01)                         */
44455  #define R_ICU_PERIERR_E1MSK0_E1_MK29_Pos      (29UL)         /*!< E1_MK29 (Bit 29)                                      */
44456  #define R_ICU_PERIERR_E1MSK0_E1_MK29_Msk      (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01)                         */
44457  #define R_ICU_PERIERR_E1MSK0_E1_MK30_Pos      (30UL)         /*!< E1_MK30 (Bit 30)                                      */
44458  #define R_ICU_PERIERR_E1MSK0_E1_MK30_Msk      (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01)                         */
44459  #define R_ICU_PERIERR_E1MSK0_E1_MK31_Pos      (31UL)         /*!< E1_MK31 (Bit 31)                                      */
44460  #define R_ICU_PERIERR_E1MSK0_E1_MK31_Msk      (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01)                         */
44461 /* ====================================================  PERIERR_E1MSK1  ===================================================== */
44462  #define R_ICU_PERIERR_E1MSK1_E1_MK0_Pos       (0UL)          /*!< E1_MK0 (Bit 0)                                        */
44463  #define R_ICU_PERIERR_E1MSK1_E1_MK0_Msk       (0x1UL)        /*!< E1_MK0 (Bitfield-Mask: 0x01)                          */
44464  #define R_ICU_PERIERR_E1MSK1_E1_MK1_Pos       (1UL)          /*!< E1_MK1 (Bit 1)                                        */
44465  #define R_ICU_PERIERR_E1MSK1_E1_MK1_Msk       (0x2UL)        /*!< E1_MK1 (Bitfield-Mask: 0x01)                          */
44466  #define R_ICU_PERIERR_E1MSK1_E1_MK2_Pos       (2UL)          /*!< E1_MK2 (Bit 2)                                        */
44467  #define R_ICU_PERIERR_E1MSK1_E1_MK2_Msk       (0x4UL)        /*!< E1_MK2 (Bitfield-Mask: 0x01)                          */
44468  #define R_ICU_PERIERR_E1MSK1_E1_MK3_Pos       (3UL)          /*!< E1_MK3 (Bit 3)                                        */
44469  #define R_ICU_PERIERR_E1MSK1_E1_MK3_Msk       (0x8UL)        /*!< E1_MK3 (Bitfield-Mask: 0x01)                          */
44470  #define R_ICU_PERIERR_E1MSK1_E1_MK4_Pos       (4UL)          /*!< E1_MK4 (Bit 4)                                        */
44471  #define R_ICU_PERIERR_E1MSK1_E1_MK4_Msk       (0x10UL)       /*!< E1_MK4 (Bitfield-Mask: 0x01)                          */
44472  #define R_ICU_PERIERR_E1MSK1_E1_MK5_Pos       (5UL)          /*!< E1_MK5 (Bit 5)                                        */
44473  #define R_ICU_PERIERR_E1MSK1_E1_MK5_Msk       (0x20UL)       /*!< E1_MK5 (Bitfield-Mask: 0x01)                          */
44474  #define R_ICU_PERIERR_E1MSK1_E1_MK6_Pos       (6UL)          /*!< E1_MK6 (Bit 6)                                        */
44475  #define R_ICU_PERIERR_E1MSK1_E1_MK6_Msk       (0x40UL)       /*!< E1_MK6 (Bitfield-Mask: 0x01)                          */
44476  #define R_ICU_PERIERR_E1MSK1_E1_MK7_Pos       (7UL)          /*!< E1_MK7 (Bit 7)                                        */
44477  #define R_ICU_PERIERR_E1MSK1_E1_MK7_Msk       (0x80UL)       /*!< E1_MK7 (Bitfield-Mask: 0x01)                          */
44478  #define R_ICU_PERIERR_E1MSK1_E1_MK8_Pos       (8UL)          /*!< E1_MK8 (Bit 8)                                        */
44479  #define R_ICU_PERIERR_E1MSK1_E1_MK8_Msk       (0x100UL)      /*!< E1_MK8 (Bitfield-Mask: 0x01)                          */
44480  #define R_ICU_PERIERR_E1MSK1_E1_MK9_Pos       (9UL)          /*!< E1_MK9 (Bit 9)                                        */
44481  #define R_ICU_PERIERR_E1MSK1_E1_MK9_Msk       (0x200UL)      /*!< E1_MK9 (Bitfield-Mask: 0x01)                          */
44482  #define R_ICU_PERIERR_E1MSK1_E1_MK13_Pos      (13UL)         /*!< E1_MK13 (Bit 13)                                      */
44483  #define R_ICU_PERIERR_E1MSK1_E1_MK13_Msk      (0x2000UL)     /*!< E1_MK13 (Bitfield-Mask: 0x01)                         */
44484  #define R_ICU_PERIERR_E1MSK1_E1_MK15_Pos      (15UL)         /*!< E1_MK15 (Bit 15)                                      */
44485  #define R_ICU_PERIERR_E1MSK1_E1_MK15_Msk      (0x8000UL)     /*!< E1_MK15 (Bitfield-Mask: 0x01)                         */
44486  #define R_ICU_PERIERR_E1MSK1_E1_MK16_Pos      (16UL)         /*!< E1_MK16 (Bit 16)                                      */
44487  #define R_ICU_PERIERR_E1MSK1_E1_MK16_Msk      (0x10000UL)    /*!< E1_MK16 (Bitfield-Mask: 0x01)                         */
44488  #define R_ICU_PERIERR_E1MSK1_E1_MK17_Pos      (17UL)         /*!< E1_MK17 (Bit 17)                                      */
44489  #define R_ICU_PERIERR_E1MSK1_E1_MK17_Msk      (0x20000UL)    /*!< E1_MK17 (Bitfield-Mask: 0x01)                         */
44490  #define R_ICU_PERIERR_E1MSK1_E1_MK18_Pos      (18UL)         /*!< E1_MK18 (Bit 18)                                      */
44491  #define R_ICU_PERIERR_E1MSK1_E1_MK18_Msk      (0x40000UL)    /*!< E1_MK18 (Bitfield-Mask: 0x01)                         */
44492  #define R_ICU_PERIERR_E1MSK1_E1_MK19_Pos      (19UL)         /*!< E1_MK19 (Bit 19)                                      */
44493  #define R_ICU_PERIERR_E1MSK1_E1_MK19_Msk      (0x80000UL)    /*!< E1_MK19 (Bitfield-Mask: 0x01)                         */
44494  #define R_ICU_PERIERR_E1MSK1_E1_MK20_Pos      (20UL)         /*!< E1_MK20 (Bit 20)                                      */
44495  #define R_ICU_PERIERR_E1MSK1_E1_MK20_Msk      (0x100000UL)   /*!< E1_MK20 (Bitfield-Mask: 0x01)                         */
44496  #define R_ICU_PERIERR_E1MSK1_E1_MK21_Pos      (21UL)         /*!< E1_MK21 (Bit 21)                                      */
44497  #define R_ICU_PERIERR_E1MSK1_E1_MK21_Msk      (0x200000UL)   /*!< E1_MK21 (Bitfield-Mask: 0x01)                         */
44498  #define R_ICU_PERIERR_E1MSK1_E1_MK22_Pos      (22UL)         /*!< E1_MK22 (Bit 22)                                      */
44499  #define R_ICU_PERIERR_E1MSK1_E1_MK22_Msk      (0x400000UL)   /*!< E1_MK22 (Bitfield-Mask: 0x01)                         */
44500  #define R_ICU_PERIERR_E1MSK1_E1_MK23_Pos      (23UL)         /*!< E1_MK23 (Bit 23)                                      */
44501  #define R_ICU_PERIERR_E1MSK1_E1_MK23_Msk      (0x800000UL)   /*!< E1_MK23 (Bitfield-Mask: 0x01)                         */
44502  #define R_ICU_PERIERR_E1MSK1_E1_MK24_Pos      (24UL)         /*!< E1_MK24 (Bit 24)                                      */
44503  #define R_ICU_PERIERR_E1MSK1_E1_MK24_Msk      (0x1000000UL)  /*!< E1_MK24 (Bitfield-Mask: 0x01)                         */
44504  #define R_ICU_PERIERR_E1MSK1_E1_MK27_Pos      (27UL)         /*!< E1_MK27 (Bit 27)                                      */
44505  #define R_ICU_PERIERR_E1MSK1_E1_MK27_Msk      (0x8000000UL)  /*!< E1_MK27 (Bitfield-Mask: 0x01)                         */
44506  #define R_ICU_PERIERR_E1MSK1_E1_MK28_Pos      (28UL)         /*!< E1_MK28 (Bit 28)                                      */
44507  #define R_ICU_PERIERR_E1MSK1_E1_MK28_Msk      (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01)                         */
44508 
44509 /* =========================================================================================================================== */
44510 /* ================                                         R_SYSC_S                                          ================ */
44511 /* =========================================================================================================================== */
44512 
44513 /* ========================================================  SCKCR2  ========================================================= */
44514  #define R_SYSC_S_SCKCR2_FSELCPU0_Pos        (0UL)          /*!< FSELCPU0 (Bit 0)                                      */
44515  #define R_SYSC_S_SCKCR2_FSELCPU0_Msk        (0x1UL)        /*!< FSELCPU0 (Bitfield-Mask: 0x01)                        */
44516  #define R_SYSC_S_SCKCR2_DIVSELSUB_Pos       (5UL)          /*!< DIVSELSUB (Bit 5)                                     */
44517  #define R_SYSC_S_SCKCR2_DIVSELSUB_Msk       (0x20UL)       /*!< DIVSELSUB (Bitfield-Mask: 0x01)                       */
44518  #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Pos    (24UL)         /*!< SPI3ASYNCSEL (Bit 24)                                 */
44519  #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Msk    (0x1000000UL)  /*!< SPI3ASYNCSEL (Bitfield-Mask: 0x01)                    */
44520  #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Pos    (25UL)         /*!< SCI5ASYNCSEL (Bit 25)                                 */
44521  #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Msk    (0x2000000UL)  /*!< SCI5ASYNCSEL (Bitfield-Mask: 0x01)                    */
44522 /* ========================================================  PLL0MON  ======================================================== */
44523  #define R_SYSC_S_PLL0MON_PLL0MON_Pos        (0UL)          /*!< PLL0MON (Bit 0)                                       */
44524  #define R_SYSC_S_PLL0MON_PLL0MON_Msk        (0x1UL)        /*!< PLL0MON (Bitfield-Mask: 0x01)                         */
44525 /* ========================================================  PLL1MON  ======================================================== */
44526  #define R_SYSC_S_PLL1MON_PLL1MON_Pos        (0UL)          /*!< PLL1MON (Bit 0)                                       */
44527  #define R_SYSC_S_PLL1MON_PLL1MON_Msk        (0x1UL)        /*!< PLL1MON (Bitfield-Mask: 0x01)                         */
44528 /* ========================================================  PLL1EN  ========================================================= */
44529  #define R_SYSC_S_PLL1EN_PLL1EN_Pos          (0UL)          /*!< PLL1EN (Bit 0)                                        */
44530  #define R_SYSC_S_PLL1EN_PLL1EN_Msk          (0x1UL)        /*!< PLL1EN (Bitfield-Mask: 0x01)                          */
44531 /* ========================================================  LOCOCR  ========================================================= */
44532  #define R_SYSC_S_LOCOCR_LCSTP_Pos           (0UL)          /*!< LCSTP (Bit 0)                                         */
44533  #define R_SYSC_S_LOCOCR_LCSTP_Msk           (0x1UL)        /*!< LCSTP (Bitfield-Mask: 0x01)                           */
44534 /* =======================================================  HIZCTRLEN  ======================================================= */
44535  #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Pos    (0UL)          /*!< CLMA3MASK (Bit 0)                                     */
44536  #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Msk    (0x1UL)        /*!< CLMA3MASK (Bitfield-Mask: 0x01)                       */
44537  #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Pos    (1UL)          /*!< CLMA0MASK (Bit 1)                                     */
44538  #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Msk    (0x2UL)        /*!< CLMA0MASK (Bitfield-Mask: 0x01)                       */
44539  #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Pos    (2UL)          /*!< CLMA1MASK (Bit 2)                                     */
44540  #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Msk    (0x4UL)        /*!< CLMA1MASK (Bitfield-Mask: 0x01)                       */
44541 /* ========================================================  SWRSYS  ========================================================= */
44542  #define R_SYSC_S_SWRSYS_SWR_Pos             (0UL)          /*!< SWR (Bit 0)                                           */
44543  #define R_SYSC_S_SWRSYS_SWR_Msk             (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
44544 /* ========================================================  SWRCPU0  ======================================================== */
44545  #define R_SYSC_S_SWRCPU0_SWR_Pos            (0UL)          /*!< SWR (Bit 0)                                           */
44546  #define R_SYSC_S_SWRCPU0_SWR_Msk            (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff)                       */
44547 /* ========================================================  MRCTLI  ========================================================= */
44548  #define R_SYSC_S_MRCTLI_MRCTLI00_Pos        (0UL)          /*!< MRCTLI00 (Bit 0)                                      */
44549  #define R_SYSC_S_MRCTLI_MRCTLI00_Msk        (0x1UL)        /*!< MRCTLI00 (Bitfield-Mask: 0x01)                        */
44550  #define R_SYSC_S_MRCTLI_MRCTLI01_Pos        (1UL)          /*!< MRCTLI01 (Bit 1)                                      */
44551  #define R_SYSC_S_MRCTLI_MRCTLI01_Msk        (0x2UL)        /*!< MRCTLI01 (Bitfield-Mask: 0x01)                        */
44552  #define R_SYSC_S_MRCTLI_MRCTLI02_Pos        (2UL)          /*!< MRCTLI02 (Bit 2)                                      */
44553  #define R_SYSC_S_MRCTLI_MRCTLI02_Msk        (0x4UL)        /*!< MRCTLI02 (Bitfield-Mask: 0x01)                        */
44554  #define R_SYSC_S_MRCTLI_MRCTLI03_Pos        (3UL)          /*!< MRCTLI03 (Bit 3)                                      */
44555  #define R_SYSC_S_MRCTLI_MRCTLI03_Msk        (0x8UL)        /*!< MRCTLI03 (Bitfield-Mask: 0x01)                        */
44556 /* ========================================================  MSTPCRF  ======================================================== */
44557  #define R_SYSC_S_MSTPCRF_MSTPCRF00_Pos      (0UL)          /*!< MSTPCRF00 (Bit 0)                                     */
44558  #define R_SYSC_S_MSTPCRF_MSTPCRF00_Msk      (0x1UL)        /*!< MSTPCRF00 (Bitfield-Mask: 0x01)                       */
44559 /* ========================================================  MSTPCRG  ======================================================== */
44560  #define R_SYSC_S_MSTPCRG_MSTPCRG00_Pos      (0UL)          /*!< MSTPCRG00 (Bit 0)                                     */
44561  #define R_SYSC_S_MSTPCRG_MSTPCRG00_Msk      (0x1UL)        /*!< MSTPCRG00 (Bitfield-Mask: 0x01)                       */
44562  #define R_SYSC_S_MSTPCRG_MSTPCRG01_Pos      (1UL)          /*!< MSTPCRG01 (Bit 1)                                     */
44563  #define R_SYSC_S_MSTPCRG_MSTPCRG01_Msk      (0x2UL)        /*!< MSTPCRG01 (Bitfield-Mask: 0x01)                       */
44564  #define R_SYSC_S_MSTPCRG_MSTPCRG02_Pos      (2UL)          /*!< MSTPCRG02 (Bit 2)                                     */
44565  #define R_SYSC_S_MSTPCRG_MSTPCRG02_Msk      (0x4UL)        /*!< MSTPCRG02 (Bitfield-Mask: 0x01)                       */
44566  #define R_SYSC_S_MSTPCRG_MSTPCRG03_Pos      (3UL)          /*!< MSTPCRG03 (Bit 3)                                     */
44567  #define R_SYSC_S_MSTPCRG_MSTPCRG03_Msk      (0x8UL)        /*!< MSTPCRG03 (Bitfield-Mask: 0x01)                       */
44568  #define R_SYSC_S_MSTPCRG_MSTPCRG04_Pos      (4UL)          /*!< MSTPCRG04 (Bit 4)                                     */
44569  #define R_SYSC_S_MSTPCRG_MSTPCRG04_Msk      (0x10UL)       /*!< MSTPCRG04 (Bitfield-Mask: 0x01)                       */
44570  #define R_SYSC_S_MSTPCRG_MSTPCRG05_Pos      (5UL)          /*!< MSTPCRG05 (Bit 5)                                     */
44571  #define R_SYSC_S_MSTPCRG_MSTPCRG05_Msk      (0x20UL)       /*!< MSTPCRG05 (Bitfield-Mask: 0x01)                       */
44572  #define R_SYSC_S_MSTPCRG_MSTPCRG08_Pos      (8UL)          /*!< MSTPCRG08 (Bit 8)                                     */
44573  #define R_SYSC_S_MSTPCRG_MSTPCRG08_Msk      (0x100UL)      /*!< MSTPCRG08 (Bitfield-Mask: 0x01)                       */
44574  #define R_SYSC_S_MSTPCRG_MSTPCRG09_Pos      (9UL)          /*!< MSTPCRG09 (Bit 9)                                     */
44575  #define R_SYSC_S_MSTPCRG_MSTPCRG09_Msk      (0x200UL)      /*!< MSTPCRG09 (Bitfield-Mask: 0x01)                       */
44576  #define R_SYSC_S_MSTPCRG_MSTPCRG10_Pos      (10UL)         /*!< MSTPCRG10 (Bit 10)                                    */
44577  #define R_SYSC_S_MSTPCRG_MSTPCRG10_Msk      (0x400UL)      /*!< MSTPCRG10 (Bitfield-Mask: 0x01)                       */
44578  #define R_SYSC_S_MSTPCRG_MSTPCRG11_Pos      (11UL)         /*!< MSTPCRG11 (Bit 11)                                    */
44579  #define R_SYSC_S_MSTPCRG_MSTPCRG11_Msk      (0x800UL)      /*!< MSTPCRG11 (Bitfield-Mask: 0x01)                       */
44580 /* ========================================================  MSTPCRI  ======================================================== */
44581  #define R_SYSC_S_MSTPCRI_MSTPCRI00_Pos      (0UL)          /*!< MSTPCRI00 (Bit 0)                                     */
44582  #define R_SYSC_S_MSTPCRI_MSTPCRI00_Msk      (0x1UL)        /*!< MSTPCRI00 (Bitfield-Mask: 0x01)                       */
44583  #define R_SYSC_S_MSTPCRI_MSTPCRI01_Pos      (1UL)          /*!< MSTPCRI01 (Bit 1)                                     */
44584  #define R_SYSC_S_MSTPCRI_MSTPCRI01_Msk      (0x2UL)        /*!< MSTPCRI01 (Bitfield-Mask: 0x01)                       */
44585 
44586 /* =========================================================================================================================== */
44587 /* ================                                          R_CLMA0                                          ================ */
44588 /* =========================================================================================================================== */
44589 
44590 /* =========================================================  CTL0  ========================================================== */
44591  #define R_CLMA0_CTL0_CLME_Pos       (0UL)     /*!< CLME (Bit 0)                                          */
44592  #define R_CLMA0_CTL0_CLME_Msk       (0x1UL)   /*!< CLME (Bitfield-Mask: 0x01)                            */
44593 /* =========================================================  CMPL  ========================================================== */
44594  #define R_CLMA0_CMPL_CMPL_Pos       (0UL)     /*!< CMPL (Bit 0)                                          */
44595  #define R_CLMA0_CMPL_CMPL_Msk       (0xfffUL) /*!< CMPL (Bitfield-Mask: 0xfff)                           */
44596 /* =========================================================  CMPH  ========================================================== */
44597  #define R_CLMA0_CMPH_CMPH_Pos       (0UL)     /*!< CMPH (Bit 0)                                          */
44598  #define R_CLMA0_CMPH_CMPH_Msk       (0xfffUL) /*!< CMPH (Bitfield-Mask: 0xfff)                           */
44599 /* =========================================================  PCMD  ========================================================== */
44600 /* ========================================================  PROTSR  ========================================================= */
44601  #define R_CLMA0_PROTSR_PRERR_Pos    (0UL)     /*!< PRERR (Bit 0)                                         */
44602  #define R_CLMA0_PROTSR_PRERR_Msk    (0x1UL)   /*!< PRERR (Bitfield-Mask: 0x01)                           */
44603 
44604 /* =========================================================================================================================== */
44605 /* ================                                          R_MPU0                                           ================ */
44606 /* =========================================================================================================================== */
44607 
44608 /* =======================================================  ERRINF_R  ======================================================== */
44609  #define R_MPU0_ERRINF_R_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
44610  #define R_MPU0_ERRINF_R_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
44611  #define R_MPU0_ERRINF_R_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
44612  #define R_MPU0_ERRINF_R_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
44613  #define R_MPU0_ERRINF_R_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
44614  #define R_MPU0_ERRINF_R_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
44615 /* =======================================================  ERRINF_W  ======================================================== */
44616  #define R_MPU0_ERRINF_W_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
44617  #define R_MPU0_ERRINF_W_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
44618  #define R_MPU0_ERRINF_W_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
44619  #define R_MPU0_ERRINF_W_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
44620  #define R_MPU0_ERRINF_W_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
44621  #define R_MPU0_ERRINF_W_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
44622 
44623 /* =========================================================================================================================== */
44624 /* ================                                          R_MPU3                                           ================ */
44625 /* =========================================================================================================================== */
44626 
44627 /* ========================================================  ERRINF  ========================================================= */
44628  #define R_MPU3_ERRINF_VALID_Pos      (0UL)          /*!< VALID (Bit 0)                                         */
44629  #define R_MPU3_ERRINF_VALID_Msk      (0x1UL)        /*!< VALID (Bitfield-Mask: 0x01)                           */
44630  #define R_MPU3_ERRINF_RW_Pos         (1UL)          /*!< RW (Bit 1)                                            */
44631  #define R_MPU3_ERRINF_RW_Msk         (0x2UL)        /*!< RW (Bitfield-Mask: 0x01)                              */
44632  #define R_MPU3_ERRINF_ERRADDR_Pos    (2UL)          /*!< ERRADDR (Bit 2)                                       */
44633  #define R_MPU3_ERRINF_ERRADDR_Msk    (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff)                   */
44634 
44635 /* =========================================================================================================================== */
44636 /* ================                                       R_SYSRAM_CTL                                        ================ */
44637 /* =========================================================================================================================== */
44638 
44639 /* =====================================================  SYSRAM_CTRL0  ====================================================== */
44640  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
44641  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
44642  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
44643  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
44644  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
44645  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
44646  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
44647  #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
44648  #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
44649  #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
44650 /* =====================================================  SYSRAM_CTRL1  ====================================================== */
44651  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
44652  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
44653  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
44654  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
44655  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
44656  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
44657  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
44658  #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
44659  #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
44660  #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
44661 /* =====================================================  SYSRAM_CTRL2  ====================================================== */
44662  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Pos          (0UL)         /*!< VECEN (Bit 0)                                         */
44663  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Msk          (0x1UL)       /*!< VECEN (Bitfield-Mask: 0x01)                           */
44664  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Pos          (16UL)        /*!< VRWEN (Bit 16)                                        */
44665  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Msk          (0xf0000UL)   /*!< VRWEN (Bitfield-Mask: 0x0f)                           */
44666  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Pos           (20UL)        /*!< VCEN (Bit 20)                                         */
44667  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Msk           (0x100000UL)  /*!< VCEN (Bitfield-Mask: 0x01)                            */
44668  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Pos          (21UL)        /*!< VLWEN (Bit 21)                                        */
44669  #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Msk          (0x200000UL)  /*!< VLWEN (Bitfield-Mask: 0x01)                           */
44670  #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Pos    (24UL)        /*!< MKICCAXIERR (Bit 24)                                  */
44671  #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Msk    (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01)                     */
44672 
44673 /* =========================================================================================================================== */
44674 /* ================                                       R_SHOSTIF_CFG                                       ================ */
44675 /* =========================================================================================================================== */
44676 
44677 /* =========================================================  SHCFG  ========================================================= */
44678  #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Pos       (0UL)          /*!< SPIMODE (Bit 0)                                       */
44679  #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Msk       (0x3UL)        /*!< SPIMODE (Bitfield-Mask: 0x03)                         */
44680  #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Pos      (2UL)          /*!< BYTESWAP (Bit 2)                                      */
44681  #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Msk      (0x4UL)        /*!< BYTESWAP (Bitfield-Mask: 0x01)                        */
44682  #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Pos    (3UL)          /*!< ADDRESSING (Bit 3)                                    */
44683  #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Msk    (0x8UL)        /*!< ADDRESSING (Bitfield-Mask: 0x01)                      */
44684  #define R_SHOSTIF_CFG_SHCFG_SLEEP_Pos         (4UL)          /*!< SLEEP (Bit 4)                                         */
44685  #define R_SHOSTIF_CFG_SHCFG_SLEEP_Msk         (0x10UL)       /*!< SLEEP (Bitfield-Mask: 0x01)                           */
44686  #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Pos      (16UL)         /*!< INTMASKI (Bit 16)                                     */
44687  #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Msk      (0x3f0000UL)   /*!< INTMASKI (Bitfield-Mask: 0x3f)                        */
44688  #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Pos      (24UL)         /*!< INTMASKE (Bit 24)                                     */
44689  #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Msk      (0x3f000000UL) /*!< INTMASKE (Bitfield-Mask: 0x3f)                        */
44690 
44691 /* =========================================================================================================================== */
44692 /* ================                                       R_PHOSTIF_CFG                                       ================ */
44693 /* =========================================================================================================================== */
44694 
44695 /* =========================================================  PHCFG  ========================================================= */
44696  #define R_PHOSTIF_CFG_PHCFG_MEMIFSEL_Pos      (0UL)        /*!< MEMIFSEL (Bit 0)                                      */
44697  #define R_PHOSTIF_CFG_PHCFG_MEMIFSEL_Msk      (0x1UL)      /*!< MEMIFSEL (Bitfield-Mask: 0x01)                        */
44698  #define R_PHOSTIF_CFG_PHCFG_BUSSSEL_Pos       (4UL)        /*!< BUSSSEL (Bit 4)                                       */
44699  #define R_PHOSTIF_CFG_PHCFG_BUSSSEL_Msk       (0x10UL)     /*!< BUSSSEL (Bitfield-Mask: 0x01)                         */
44700  #define R_PHOSTIF_CFG_PHCFG_HIFSYNC_Pos       (8UL)        /*!< HIFSYNC (Bit 8)                                       */
44701  #define R_PHOSTIF_CFG_PHCFG_HIFSYNC_Msk       (0x100UL)    /*!< HIFSYNC (Bitfield-Mask: 0x01)                         */
44702  #define R_PHOSTIF_CFG_PHCFG_MEMCSEL_Pos       (12UL)       /*!< MEMCSEL (Bit 12)                                      */
44703  #define R_PHOSTIF_CFG_PHCFG_MEMCSEL_Msk       (0x1000UL)   /*!< MEMCSEL (Bitfield-Mask: 0x01)                         */
44704  #define R_PHOSTIF_CFG_PHCFG_HWRZSEL_Pos       (16UL)       /*!< HWRZSEL (Bit 16)                                      */
44705  #define R_PHOSTIF_CFG_PHCFG_HWRZSEL_Msk       (0x10000UL)  /*!< HWRZSEL (Bitfield-Mask: 0x01)                         */
44706  #define R_PHOSTIF_CFG_PHCFG_ADMUXMODE_Pos     (20UL)       /*!< ADMUXMODE (Bit 20)                                    */
44707  #define R_PHOSTIF_CFG_PHCFG_ADMUXMODE_Msk     (0x100000UL) /*!< ADMUXMODE (Bitfield-Mask: 0x01)                       */
44708 /* =========================================================  PHACC  ========================================================= */
44709  #define R_PHOSTIF_CFG_PHACC_HIFRDYSEL_Pos     (0UL)        /*!< HIFRDYSEL (Bit 0)                                     */
44710  #define R_PHOSTIF_CFG_PHACC_HIFRDYSEL_Msk     (0x1UL)      /*!< HIFRDYSEL (Bitfield-Mask: 0x01)                       */
44711  #define R_PHOSTIF_CFG_PHACC_HIFBCCSEL_Pos     (8UL)        /*!< HIFBCCSEL (Bit 8)                                     */
44712  #define R_PHOSTIF_CFG_PHACC_HIFBCCSEL_Msk     (0x100UL)    /*!< HIFBCCSEL (Bitfield-Mask: 0x01)                       */
44713  #define R_PHOSTIF_CFG_PHACC_HIFBTCSEL_Pos     (9UL)        /*!< HIFBTCSEL (Bit 9)                                     */
44714  #define R_PHOSTIF_CFG_PHACC_HIFBTCSEL_Msk     (0x200UL)    /*!< HIFBTCSEL (Bitfield-Mask: 0x01)                       */
44715  #define R_PHOSTIF_CFG_PHACC_HIFPRCSEL_Pos     (10UL)       /*!< HIFPRCSEL (Bit 10)                                    */
44716  #define R_PHOSTIF_CFG_PHACC_HIFPRCSEL_Msk     (0x400UL)    /*!< HIFPRCSEL (Bitfield-Mask: 0x01)                       */
44717  #define R_PHOSTIF_CFG_PHACC_HIFIRCSEL_Pos     (11UL)       /*!< HIFIRCSEL (Bit 11)                                    */
44718  #define R_PHOSTIF_CFG_PHACC_HIFIRCSEL_Msk     (0x800UL)    /*!< HIFIRCSEL (Bitfield-Mask: 0x01)                       */
44719  #define R_PHOSTIF_CFG_PHACC_HIFXALSEL_Pos     (12UL)       /*!< HIFXALSEL (Bit 12)                                    */
44720  #define R_PHOSTIF_CFG_PHACC_HIFXALSEL_Msk     (0x1000UL)   /*!< HIFXALSEL (Bitfield-Mask: 0x01)                       */
44721  #define R_PHOSTIF_CFG_PHACC_HIFXAHSEL_Pos     (13UL)       /*!< HIFXAHSEL (Bit 13)                                    */
44722  #define R_PHOSTIF_CFG_PHACC_HIFXAHSEL_Msk     (0x2000UL)   /*!< HIFXAHSEL (Bitfield-Mask: 0x01)                       */
44723  #define R_PHOSTIF_CFG_PHACC_HIFEXT0SEL_Pos    (14UL)       /*!< HIFEXT0SEL (Bit 14)                                   */
44724  #define R_PHOSTIF_CFG_PHACC_HIFEXT0SEL_Msk    (0x4000UL)   /*!< HIFEXT0SEL (Bitfield-Mask: 0x01)                      */
44725  #define R_PHOSTIF_CFG_PHACC_HIFEXT1SEL_Pos    (15UL)       /*!< HIFEXT1SEL (Bit 15)                                   */
44726  #define R_PHOSTIF_CFG_PHACC_HIFEXT1SEL_Msk    (0x8000UL)   /*!< HIFEXT1SEL (Bitfield-Mask: 0x01)                      */
44727  #define R_PHOSTIF_CFG_PHACC_CSSWAP_Pos        (16UL)       /*!< CSSWAP (Bit 16)                                       */
44728  #define R_PHOSTIF_CFG_PHACC_CSSWAP_Msk        (0x10000UL)  /*!< CSSWAP (Bitfield-Mask: 0x01)                          */
44729  #define R_PHOSTIF_CFG_PHACC_BSCADMUX_Pos      (17UL)       /*!< BSCADMUX (Bit 17)                                     */
44730  #define R_PHOSTIF_CFG_PHACC_BSCADMUX_Msk      (0x20000UL)  /*!< BSCADMUX (Bitfield-Mask: 0x01)                        */
44731 
44732 /* =========================================================================================================================== */
44733 /* ================                                          R_RWP_S                                          ================ */
44734 /* =========================================================================================================================== */
44735 
44736 /* =========================================================  PRCRS  ========================================================= */
44737  #define R_RWP_S_PRCRS_PRC0_Pos     (0UL)      /*!< PRC0 (Bit 0)                                          */
44738  #define R_RWP_S_PRCRS_PRC0_Msk     (0x1UL)    /*!< PRC0 (Bitfield-Mask: 0x01)                            */
44739  #define R_RWP_S_PRCRS_PRC1_Pos     (1UL)      /*!< PRC1 (Bit 1)                                          */
44740  #define R_RWP_S_PRCRS_PRC1_Msk     (0x2UL)    /*!< PRC1 (Bitfield-Mask: 0x01)                            */
44741  #define R_RWP_S_PRCRS_PRC2_Pos     (2UL)      /*!< PRC2 (Bit 2)                                          */
44742  #define R_RWP_S_PRCRS_PRC2_Msk     (0x4UL)    /*!< PRC2 (Bitfield-Mask: 0x01)                            */
44743  #define R_RWP_S_PRCRS_PRC3_Pos     (3UL)      /*!< PRC3 (Bit 3)                                          */
44744  #define R_RWP_S_PRCRS_PRC3_Msk     (0x8UL)    /*!< PRC3 (Bitfield-Mask: 0x01)                            */
44745  #define R_RWP_S_PRCRS_PRKEY_Pos    (8UL)      /*!< PRKEY (Bit 8)                                         */
44746  #define R_RWP_S_PRCRS_PRKEY_Msk    (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff)                           */
44747 
44748 /* =========================================================================================================================== */
44749 /* ================                                           R_MTU                                           ================ */
44750 /* =========================================================================================================================== */
44751 
44752 /* =========================================================  TOERA  ========================================================= */
44753  #define R_MTU_TOERA_OE3B_Pos      (0UL)    /*!< OE3B (Bit 0)                                          */
44754  #define R_MTU_TOERA_OE3B_Msk      (0x1UL)  /*!< OE3B (Bitfield-Mask: 0x01)                            */
44755  #define R_MTU_TOERA_OE4A_Pos      (1UL)    /*!< OE4A (Bit 1)                                          */
44756  #define R_MTU_TOERA_OE4A_Msk      (0x2UL)  /*!< OE4A (Bitfield-Mask: 0x01)                            */
44757  #define R_MTU_TOERA_OE4B_Pos      (2UL)    /*!< OE4B (Bit 2)                                          */
44758  #define R_MTU_TOERA_OE4B_Msk      (0x4UL)  /*!< OE4B (Bitfield-Mask: 0x01)                            */
44759  #define R_MTU_TOERA_OE3D_Pos      (3UL)    /*!< OE3D (Bit 3)                                          */
44760  #define R_MTU_TOERA_OE3D_Msk      (0x8UL)  /*!< OE3D (Bitfield-Mask: 0x01)                            */
44761  #define R_MTU_TOERA_OE4C_Pos      (4UL)    /*!< OE4C (Bit 4)                                          */
44762  #define R_MTU_TOERA_OE4C_Msk      (0x10UL) /*!< OE4C (Bitfield-Mask: 0x01)                            */
44763  #define R_MTU_TOERA_OE4D_Pos      (5UL)    /*!< OE4D (Bit 5)                                          */
44764  #define R_MTU_TOERA_OE4D_Msk      (0x20UL) /*!< OE4D (Bitfield-Mask: 0x01)                            */
44765 /* =========================================================  TGCRA  ========================================================= */
44766  #define R_MTU_TGCRA_UF_Pos        (0UL)    /*!< UF (Bit 0)                                            */
44767  #define R_MTU_TGCRA_UF_Msk        (0x1UL)  /*!< UF (Bitfield-Mask: 0x01)                              */
44768  #define R_MTU_TGCRA_VF_Pos        (1UL)    /*!< VF (Bit 1)                                            */
44769  #define R_MTU_TGCRA_VF_Msk        (0x2UL)  /*!< VF (Bitfield-Mask: 0x01)                              */
44770  #define R_MTU_TGCRA_WF_Pos        (2UL)    /*!< WF (Bit 2)                                            */
44771  #define R_MTU_TGCRA_WF_Msk        (0x4UL)  /*!< WF (Bitfield-Mask: 0x01)                              */
44772  #define R_MTU_TGCRA_FB_Pos        (3UL)    /*!< FB (Bit 3)                                            */
44773  #define R_MTU_TGCRA_FB_Msk        (0x8UL)  /*!< FB (Bitfield-Mask: 0x01)                              */
44774  #define R_MTU_TGCRA_P_Pos         (4UL)    /*!< P (Bit 4)                                             */
44775  #define R_MTU_TGCRA_P_Msk         (0x10UL) /*!< P (Bitfield-Mask: 0x01)                               */
44776  #define R_MTU_TGCRA_N_Pos         (5UL)    /*!< N (Bit 5)                                             */
44777  #define R_MTU_TGCRA_N_Msk         (0x20UL) /*!< N (Bitfield-Mask: 0x01)                               */
44778  #define R_MTU_TGCRA_BDC_Pos       (6UL)    /*!< BDC (Bit 6)                                           */
44779  #define R_MTU_TGCRA_BDC_Msk       (0x40UL) /*!< BDC (Bitfield-Mask: 0x01)                             */
44780 /* ========================================================  TOCR1A  ========================================================= */
44781  #define R_MTU_TOCR1A_OLSP_Pos     (0UL)    /*!< OLSP (Bit 0)                                          */
44782  #define R_MTU_TOCR1A_OLSP_Msk     (0x1UL)  /*!< OLSP (Bitfield-Mask: 0x01)                            */
44783  #define R_MTU_TOCR1A_OLSN_Pos     (1UL)    /*!< OLSN (Bit 1)                                          */
44784  #define R_MTU_TOCR1A_OLSN_Msk     (0x2UL)  /*!< OLSN (Bitfield-Mask: 0x01)                            */
44785  #define R_MTU_TOCR1A_TOCS_Pos     (2UL)    /*!< TOCS (Bit 2)                                          */
44786  #define R_MTU_TOCR1A_TOCS_Msk     (0x4UL)  /*!< TOCS (Bitfield-Mask: 0x01)                            */
44787  #define R_MTU_TOCR1A_TOCL_Pos     (3UL)    /*!< TOCL (Bit 3)                                          */
44788  #define R_MTU_TOCR1A_TOCL_Msk     (0x8UL)  /*!< TOCL (Bitfield-Mask: 0x01)                            */
44789  #define R_MTU_TOCR1A_PSYE_Pos     (6UL)    /*!< PSYE (Bit 6)                                          */
44790  #define R_MTU_TOCR1A_PSYE_Msk     (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01)                            */
44791 /* ========================================================  TOCR2A  ========================================================= */
44792  #define R_MTU_TOCR2A_OLS1P_Pos    (0UL)    /*!< OLS1P (Bit 0)                                         */
44793  #define R_MTU_TOCR2A_OLS1P_Msk    (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
44794  #define R_MTU_TOCR2A_OLS1N_Pos    (1UL)    /*!< OLS1N (Bit 1)                                         */
44795  #define R_MTU_TOCR2A_OLS1N_Msk    (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
44796  #define R_MTU_TOCR2A_OLS2P_Pos    (2UL)    /*!< OLS2P (Bit 2)                                         */
44797  #define R_MTU_TOCR2A_OLS2P_Msk    (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
44798  #define R_MTU_TOCR2A_OLS2N_Pos    (3UL)    /*!< OLS2N (Bit 3)                                         */
44799  #define R_MTU_TOCR2A_OLS2N_Msk    (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
44800  #define R_MTU_TOCR2A_OLS3P_Pos    (4UL)    /*!< OLS3P (Bit 4)                                         */
44801  #define R_MTU_TOCR2A_OLS3P_Msk    (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
44802  #define R_MTU_TOCR2A_OLS3N_Pos    (5UL)    /*!< OLS3N (Bit 5)                                         */
44803  #define R_MTU_TOCR2A_OLS3N_Msk    (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
44804  #define R_MTU_TOCR2A_BF_Pos       (6UL)    /*!< BF (Bit 6)                                            */
44805  #define R_MTU_TOCR2A_BF_Msk       (0xc0UL) /*!< BF (Bitfield-Mask: 0x03)                              */
44806 /* =========================================================  TCDRA  ========================================================= */
44807 /* =========================================================  TDDRA  ========================================================= */
44808 /* ========================================================  TCNTSA  ========================================================= */
44809 /* =========================================================  TCBRA  ========================================================= */
44810 /* ========================================================  TITCR1A  ======================================================== */
44811  #define R_MTU_TITCR1A_T4VCOR_Pos      (0UL)    /*!< T4VCOR (Bit 0)                                        */
44812  #define R_MTU_TITCR1A_T4VCOR_Msk      (0x7UL)  /*!< T4VCOR (Bitfield-Mask: 0x07)                          */
44813  #define R_MTU_TITCR1A_T4VEN_Pos       (3UL)    /*!< T4VEN (Bit 3)                                         */
44814  #define R_MTU_TITCR1A_T4VEN_Msk       (0x8UL)  /*!< T4VEN (Bitfield-Mask: 0x01)                           */
44815  #define R_MTU_TITCR1A_T3ACOR_Pos      (4UL)    /*!< T3ACOR (Bit 4)                                        */
44816  #define R_MTU_TITCR1A_T3ACOR_Msk      (0x70UL) /*!< T3ACOR (Bitfield-Mask: 0x07)                          */
44817  #define R_MTU_TITCR1A_T3AEN_Pos       (7UL)    /*!< T3AEN (Bit 7)                                         */
44818  #define R_MTU_TITCR1A_T3AEN_Msk       (0x80UL) /*!< T3AEN (Bitfield-Mask: 0x01)                           */
44819 /* =======================================================  TITCNT1A  ======================================================== */
44820  #define R_MTU_TITCNT1A_T4VCNT_Pos     (0UL)    /*!< T4VCNT (Bit 0)                                        */
44821  #define R_MTU_TITCNT1A_T4VCNT_Msk     (0x7UL)  /*!< T4VCNT (Bitfield-Mask: 0x07)                          */
44822  #define R_MTU_TITCNT1A_T3ACNT_Pos     (4UL)    /*!< T3ACNT (Bit 4)                                        */
44823  #define R_MTU_TITCNT1A_T3ACNT_Msk     (0x70UL) /*!< T3ACNT (Bitfield-Mask: 0x07)                          */
44824 /* ========================================================  TBTERA  ========================================================= */
44825  #define R_MTU_TBTERA_BTE_Pos          (0UL)    /*!< BTE (Bit 0)                                           */
44826  #define R_MTU_TBTERA_BTE_Msk          (0x3UL)  /*!< BTE (Bitfield-Mask: 0x03)                             */
44827 /* =========================================================  TDERA  ========================================================= */
44828  #define R_MTU_TDERA_TDER_Pos          (0UL)    /*!< TDER (Bit 0)                                          */
44829  #define R_MTU_TDERA_TDER_Msk          (0x1UL)  /*!< TDER (Bitfield-Mask: 0x01)                            */
44830 /* ========================================================  TOLBRA  ========================================================= */
44831  #define R_MTU_TOLBRA_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
44832  #define R_MTU_TOLBRA_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
44833  #define R_MTU_TOLBRA_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
44834  #define R_MTU_TOLBRA_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
44835  #define R_MTU_TOLBRA_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
44836  #define R_MTU_TOLBRA_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
44837  #define R_MTU_TOLBRA_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
44838  #define R_MTU_TOLBRA_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
44839  #define R_MTU_TOLBRA_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
44840  #define R_MTU_TOLBRA_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
44841  #define R_MTU_TOLBRA_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
44842  #define R_MTU_TOLBRA_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
44843 /* ========================================================  TITMRA  ========================================================= */
44844  #define R_MTU_TITMRA_TITM_Pos         (0UL)    /*!< TITM (Bit 0)                                          */
44845  #define R_MTU_TITMRA_TITM_Msk         (0x1UL)  /*!< TITM (Bitfield-Mask: 0x01)                            */
44846 /* ========================================================  TITCR2A  ======================================================== */
44847  #define R_MTU_TITCR2A_TRG4COR_Pos     (0UL)    /*!< TRG4COR (Bit 0)                                       */
44848  #define R_MTU_TITCR2A_TRG4COR_Msk     (0x7UL)  /*!< TRG4COR (Bitfield-Mask: 0x07)                         */
44849 /* =======================================================  TITCNT2A  ======================================================== */
44850  #define R_MTU_TITCNT2A_TRG4CNT_Pos    (0UL)    /*!< TRG4CNT (Bit 0)                                       */
44851  #define R_MTU_TITCNT2A_TRG4CNT_Msk    (0x7UL)  /*!< TRG4CNT (Bitfield-Mask: 0x07)                         */
44852 /* =========================================================  TWCRA  ========================================================= */
44853  #define R_MTU_TWCRA_WRE_Pos           (0UL)    /*!< WRE (Bit 0)                                           */
44854  #define R_MTU_TWCRA_WRE_Msk           (0x1UL)  /*!< WRE (Bitfield-Mask: 0x01)                             */
44855  #define R_MTU_TWCRA_SCC_Pos           (1UL)    /*!< SCC (Bit 1)                                           */
44856  #define R_MTU_TWCRA_SCC_Msk           (0x2UL)  /*!< SCC (Bitfield-Mask: 0x01)                             */
44857  #define R_MTU_TWCRA_CCE_Pos           (7UL)    /*!< CCE (Bit 7)                                           */
44858  #define R_MTU_TWCRA_CCE_Msk           (0x80UL) /*!< CCE (Bitfield-Mask: 0x01)                             */
44859 /* ========================================================  TMDR2A  ========================================================= */
44860  #define R_MTU_TMDR2A_DRS_Pos          (0UL)    /*!< DRS (Bit 0)                                           */
44861  #define R_MTU_TMDR2A_DRS_Msk          (0x1UL)  /*!< DRS (Bitfield-Mask: 0x01)                             */
44862 /* =========================================================  TSTRA  ========================================================= */
44863  #define R_MTU_TSTRA_CST0_Pos          (0UL)    /*!< CST0 (Bit 0)                                          */
44864  #define R_MTU_TSTRA_CST0_Msk          (0x1UL)  /*!< CST0 (Bitfield-Mask: 0x01)                            */
44865  #define R_MTU_TSTRA_CST1_Pos          (1UL)    /*!< CST1 (Bit 1)                                          */
44866  #define R_MTU_TSTRA_CST1_Msk          (0x2UL)  /*!< CST1 (Bitfield-Mask: 0x01)                            */
44867  #define R_MTU_TSTRA_CST2_Pos          (2UL)    /*!< CST2 (Bit 2)                                          */
44868  #define R_MTU_TSTRA_CST2_Msk          (0x4UL)  /*!< CST2 (Bitfield-Mask: 0x01)                            */
44869  #define R_MTU_TSTRA_CST8_Pos          (3UL)    /*!< CST8 (Bit 3)                                          */
44870  #define R_MTU_TSTRA_CST8_Msk          (0x8UL)  /*!< CST8 (Bitfield-Mask: 0x01)                            */
44871  #define R_MTU_TSTRA_CST3_Pos          (6UL)    /*!< CST3 (Bit 6)                                          */
44872  #define R_MTU_TSTRA_CST3_Msk          (0x40UL) /*!< CST3 (Bitfield-Mask: 0x01)                            */
44873  #define R_MTU_TSTRA_CST4_Pos          (7UL)    /*!< CST4 (Bit 7)                                          */
44874  #define R_MTU_TSTRA_CST4_Msk          (0x80UL) /*!< CST4 (Bitfield-Mask: 0x01)                            */
44875 /* =========================================================  TSYRA  ========================================================= */
44876  #define R_MTU_TSYRA_SYNC0_Pos         (0UL)    /*!< SYNC0 (Bit 0)                                         */
44877  #define R_MTU_TSYRA_SYNC0_Msk         (0x1UL)  /*!< SYNC0 (Bitfield-Mask: 0x01)                           */
44878  #define R_MTU_TSYRA_SYNC1_Pos         (1UL)    /*!< SYNC1 (Bit 1)                                         */
44879  #define R_MTU_TSYRA_SYNC1_Msk         (0x2UL)  /*!< SYNC1 (Bitfield-Mask: 0x01)                           */
44880  #define R_MTU_TSYRA_SYNC2_Pos         (2UL)    /*!< SYNC2 (Bit 2)                                         */
44881  #define R_MTU_TSYRA_SYNC2_Msk         (0x4UL)  /*!< SYNC2 (Bitfield-Mask: 0x01)                           */
44882  #define R_MTU_TSYRA_SYNC3_Pos         (6UL)    /*!< SYNC3 (Bit 6)                                         */
44883  #define R_MTU_TSYRA_SYNC3_Msk         (0x40UL) /*!< SYNC3 (Bitfield-Mask: 0x01)                           */
44884  #define R_MTU_TSYRA_SYNC4_Pos         (7UL)    /*!< SYNC4 (Bit 7)                                         */
44885  #define R_MTU_TSYRA_SYNC4_Msk         (0x80UL) /*!< SYNC4 (Bitfield-Mask: 0x01)                           */
44886 /* ========================================================  TCSYSTR  ======================================================== */
44887  #define R_MTU_TCSYSTR_SCH7_Pos        (0UL)    /*!< SCH7 (Bit 0)                                          */
44888  #define R_MTU_TCSYSTR_SCH7_Msk        (0x1UL)  /*!< SCH7 (Bitfield-Mask: 0x01)                            */
44889  #define R_MTU_TCSYSTR_SCH6_Pos        (1UL)    /*!< SCH6 (Bit 1)                                          */
44890  #define R_MTU_TCSYSTR_SCH6_Msk        (0x2UL)  /*!< SCH6 (Bitfield-Mask: 0x01)                            */
44891  #define R_MTU_TCSYSTR_SCH4_Pos        (3UL)    /*!< SCH4 (Bit 3)                                          */
44892  #define R_MTU_TCSYSTR_SCH4_Msk        (0x8UL)  /*!< SCH4 (Bitfield-Mask: 0x01)                            */
44893  #define R_MTU_TCSYSTR_SCH3_Pos        (4UL)    /*!< SCH3 (Bit 4)                                          */
44894  #define R_MTU_TCSYSTR_SCH3_Msk        (0x10UL) /*!< SCH3 (Bitfield-Mask: 0x01)                            */
44895  #define R_MTU_TCSYSTR_SCH2_Pos        (5UL)    /*!< SCH2 (Bit 5)                                          */
44896  #define R_MTU_TCSYSTR_SCH2_Msk        (0x20UL) /*!< SCH2 (Bitfield-Mask: 0x01)                            */
44897  #define R_MTU_TCSYSTR_SCH1_Pos        (6UL)    /*!< SCH1 (Bit 6)                                          */
44898  #define R_MTU_TCSYSTR_SCH1_Msk        (0x40UL) /*!< SCH1 (Bitfield-Mask: 0x01)                            */
44899  #define R_MTU_TCSYSTR_SCH0_Pos        (7UL)    /*!< SCH0 (Bit 7)                                          */
44900  #define R_MTU_TCSYSTR_SCH0_Msk        (0x80UL) /*!< SCH0 (Bitfield-Mask: 0x01)                            */
44901 /* ========================================================  TRWERA  ========================================================= */
44902  #define R_MTU_TRWERA_RWE_Pos          (0UL)    /*!< RWE (Bit 0)                                           */
44903  #define R_MTU_TRWERA_RWE_Msk          (0x1UL)  /*!< RWE (Bitfield-Mask: 0x01)                             */
44904 /* =========================================================  TOERB  ========================================================= */
44905  #define R_MTU_TOERB_OE6B_Pos          (0UL)    /*!< OE6B (Bit 0)                                          */
44906  #define R_MTU_TOERB_OE6B_Msk          (0x1UL)  /*!< OE6B (Bitfield-Mask: 0x01)                            */
44907  #define R_MTU_TOERB_OE7A_Pos          (1UL)    /*!< OE7A (Bit 1)                                          */
44908  #define R_MTU_TOERB_OE7A_Msk          (0x2UL)  /*!< OE7A (Bitfield-Mask: 0x01)                            */
44909  #define R_MTU_TOERB_OE7B_Pos          (2UL)    /*!< OE7B (Bit 2)                                          */
44910  #define R_MTU_TOERB_OE7B_Msk          (0x4UL)  /*!< OE7B (Bitfield-Mask: 0x01)                            */
44911  #define R_MTU_TOERB_OE6D_Pos          (3UL)    /*!< OE6D (Bit 3)                                          */
44912  #define R_MTU_TOERB_OE6D_Msk          (0x8UL)  /*!< OE6D (Bitfield-Mask: 0x01)                            */
44913  #define R_MTU_TOERB_OE7C_Pos          (4UL)    /*!< OE7C (Bit 4)                                          */
44914  #define R_MTU_TOERB_OE7C_Msk          (0x10UL) /*!< OE7C (Bitfield-Mask: 0x01)                            */
44915  #define R_MTU_TOERB_OE7D_Pos          (5UL)    /*!< OE7D (Bit 5)                                          */
44916  #define R_MTU_TOERB_OE7D_Msk          (0x20UL) /*!< OE7D (Bitfield-Mask: 0x01)                            */
44917 /* ========================================================  TOCR1B  ========================================================= */
44918  #define R_MTU_TOCR1B_OLSP_Pos         (0UL)    /*!< OLSP (Bit 0)                                          */
44919  #define R_MTU_TOCR1B_OLSP_Msk         (0x1UL)  /*!< OLSP (Bitfield-Mask: 0x01)                            */
44920  #define R_MTU_TOCR1B_OLSN_Pos         (1UL)    /*!< OLSN (Bit 1)                                          */
44921  #define R_MTU_TOCR1B_OLSN_Msk         (0x2UL)  /*!< OLSN (Bitfield-Mask: 0x01)                            */
44922  #define R_MTU_TOCR1B_TOCS_Pos         (2UL)    /*!< TOCS (Bit 2)                                          */
44923  #define R_MTU_TOCR1B_TOCS_Msk         (0x4UL)  /*!< TOCS (Bitfield-Mask: 0x01)                            */
44924  #define R_MTU_TOCR1B_TOCL_Pos         (3UL)    /*!< TOCL (Bit 3)                                          */
44925  #define R_MTU_TOCR1B_TOCL_Msk         (0x8UL)  /*!< TOCL (Bitfield-Mask: 0x01)                            */
44926  #define R_MTU_TOCR1B_PSYE_Pos         (6UL)    /*!< PSYE (Bit 6)                                          */
44927  #define R_MTU_TOCR1B_PSYE_Msk         (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01)                            */
44928 /* ========================================================  TOCR2B  ========================================================= */
44929  #define R_MTU_TOCR2B_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
44930  #define R_MTU_TOCR2B_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
44931  #define R_MTU_TOCR2B_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
44932  #define R_MTU_TOCR2B_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
44933  #define R_MTU_TOCR2B_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
44934  #define R_MTU_TOCR2B_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
44935  #define R_MTU_TOCR2B_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
44936  #define R_MTU_TOCR2B_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
44937  #define R_MTU_TOCR2B_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
44938  #define R_MTU_TOCR2B_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
44939  #define R_MTU_TOCR2B_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
44940  #define R_MTU_TOCR2B_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
44941  #define R_MTU_TOCR2B_BF_Pos           (6UL)    /*!< BF (Bit 6)                                            */
44942  #define R_MTU_TOCR2B_BF_Msk           (0xc0UL) /*!< BF (Bitfield-Mask: 0x03)                              */
44943 /* =========================================================  TCDRB  ========================================================= */
44944 /* =========================================================  TDDRB  ========================================================= */
44945 /* ========================================================  TCNTSB  ========================================================= */
44946 /* =========================================================  TCBRB  ========================================================= */
44947 /* ========================================================  TITCR1B  ======================================================== */
44948  #define R_MTU_TITCR1B_T7VCOR_Pos      (0UL)    /*!< T7VCOR (Bit 0)                                        */
44949  #define R_MTU_TITCR1B_T7VCOR_Msk      (0x7UL)  /*!< T7VCOR (Bitfield-Mask: 0x07)                          */
44950  #define R_MTU_TITCR1B_T7VEN_Pos       (3UL)    /*!< T7VEN (Bit 3)                                         */
44951  #define R_MTU_TITCR1B_T7VEN_Msk       (0x8UL)  /*!< T7VEN (Bitfield-Mask: 0x01)                           */
44952  #define R_MTU_TITCR1B_T6ACOR_Pos      (4UL)    /*!< T6ACOR (Bit 4)                                        */
44953  #define R_MTU_TITCR1B_T6ACOR_Msk      (0x70UL) /*!< T6ACOR (Bitfield-Mask: 0x07)                          */
44954  #define R_MTU_TITCR1B_T6AEN_Pos       (7UL)    /*!< T6AEN (Bit 7)                                         */
44955  #define R_MTU_TITCR1B_T6AEN_Msk       (0x80UL) /*!< T6AEN (Bitfield-Mask: 0x01)                           */
44956 /* =======================================================  TITCNT1B  ======================================================== */
44957  #define R_MTU_TITCNT1B_T7VCNT_Pos     (0UL)    /*!< T7VCNT (Bit 0)                                        */
44958  #define R_MTU_TITCNT1B_T7VCNT_Msk     (0x7UL)  /*!< T7VCNT (Bitfield-Mask: 0x07)                          */
44959  #define R_MTU_TITCNT1B_T6ACNT_Pos     (4UL)    /*!< T6ACNT (Bit 4)                                        */
44960  #define R_MTU_TITCNT1B_T6ACNT_Msk     (0x70UL) /*!< T6ACNT (Bitfield-Mask: 0x07)                          */
44961 /* ========================================================  TBTERB  ========================================================= */
44962  #define R_MTU_TBTERB_BTE_Pos          (0UL)    /*!< BTE (Bit 0)                                           */
44963  #define R_MTU_TBTERB_BTE_Msk          (0x3UL)  /*!< BTE (Bitfield-Mask: 0x03)                             */
44964 /* =========================================================  TDERB  ========================================================= */
44965  #define R_MTU_TDERB_TDER_Pos          (0UL)    /*!< TDER (Bit 0)                                          */
44966  #define R_MTU_TDERB_TDER_Msk          (0x1UL)  /*!< TDER (Bitfield-Mask: 0x01)                            */
44967 /* ========================================================  TOLBRB  ========================================================= */
44968  #define R_MTU_TOLBRB_OLS1P_Pos        (0UL)    /*!< OLS1P (Bit 0)                                         */
44969  #define R_MTU_TOLBRB_OLS1P_Msk        (0x1UL)  /*!< OLS1P (Bitfield-Mask: 0x01)                           */
44970  #define R_MTU_TOLBRB_OLS1N_Pos        (1UL)    /*!< OLS1N (Bit 1)                                         */
44971  #define R_MTU_TOLBRB_OLS1N_Msk        (0x2UL)  /*!< OLS1N (Bitfield-Mask: 0x01)                           */
44972  #define R_MTU_TOLBRB_OLS2P_Pos        (2UL)    /*!< OLS2P (Bit 2)                                         */
44973  #define R_MTU_TOLBRB_OLS2P_Msk        (0x4UL)  /*!< OLS2P (Bitfield-Mask: 0x01)                           */
44974  #define R_MTU_TOLBRB_OLS2N_Pos        (3UL)    /*!< OLS2N (Bit 3)                                         */
44975  #define R_MTU_TOLBRB_OLS2N_Msk        (0x8UL)  /*!< OLS2N (Bitfield-Mask: 0x01)                           */
44976  #define R_MTU_TOLBRB_OLS3P_Pos        (4UL)    /*!< OLS3P (Bit 4)                                         */
44977  #define R_MTU_TOLBRB_OLS3P_Msk        (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01)                           */
44978  #define R_MTU_TOLBRB_OLS3N_Pos        (5UL)    /*!< OLS3N (Bit 5)                                         */
44979  #define R_MTU_TOLBRB_OLS3N_Msk        (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01)                           */
44980 /* ========================================================  TITMRB  ========================================================= */
44981  #define R_MTU_TITMRB_TITM_Pos         (0UL)    /*!< TITM (Bit 0)                                          */
44982  #define R_MTU_TITMRB_TITM_Msk         (0x1UL)  /*!< TITM (Bitfield-Mask: 0x01)                            */
44983 /* ========================================================  TITCR2B  ======================================================== */
44984  #define R_MTU_TITCR2B_TRG7COR_Pos     (0UL)    /*!< TRG7COR (Bit 0)                                       */
44985  #define R_MTU_TITCR2B_TRG7COR_Msk     (0x7UL)  /*!< TRG7COR (Bitfield-Mask: 0x07)                         */
44986 /* =======================================================  TITCNT2B  ======================================================== */
44987  #define R_MTU_TITCNT2B_TRG7CNT_Pos    (0UL)    /*!< TRG7CNT (Bit 0)                                       */
44988  #define R_MTU_TITCNT2B_TRG7CNT_Msk    (0x7UL)  /*!< TRG7CNT (Bitfield-Mask: 0x07)                         */
44989 /* =========================================================  TWCRB  ========================================================= */
44990  #define R_MTU_TWCRB_WRE_Pos           (0UL)    /*!< WRE (Bit 0)                                           */
44991  #define R_MTU_TWCRB_WRE_Msk           (0x1UL)  /*!< WRE (Bitfield-Mask: 0x01)                             */
44992  #define R_MTU_TWCRB_SCC_Pos           (1UL)    /*!< SCC (Bit 1)                                           */
44993  #define R_MTU_TWCRB_SCC_Msk           (0x2UL)  /*!< SCC (Bitfield-Mask: 0x01)                             */
44994  #define R_MTU_TWCRB_CCE_Pos           (7UL)    /*!< CCE (Bit 7)                                           */
44995  #define R_MTU_TWCRB_CCE_Msk           (0x80UL) /*!< CCE (Bitfield-Mask: 0x01)                             */
44996 /* ========================================================  TMDR2B  ========================================================= */
44997  #define R_MTU_TMDR2B_DRS_Pos          (0UL)    /*!< DRS (Bit 0)                                           */
44998  #define R_MTU_TMDR2B_DRS_Msk          (0x1UL)  /*!< DRS (Bitfield-Mask: 0x01)                             */
44999 /* =========================================================  TSTRB  ========================================================= */
45000  #define R_MTU_TSTRB_CST6_Pos          (6UL)    /*!< CST6 (Bit 6)                                          */
45001  #define R_MTU_TSTRB_CST6_Msk          (0x40UL) /*!< CST6 (Bitfield-Mask: 0x01)                            */
45002  #define R_MTU_TSTRB_CST7_Pos          (7UL)    /*!< CST7 (Bit 7)                                          */
45003  #define R_MTU_TSTRB_CST7_Msk          (0x80UL) /*!< CST7 (Bitfield-Mask: 0x01)                            */
45004 /* =========================================================  TSYRB  ========================================================= */
45005  #define R_MTU_TSYRB_SYNC6_Pos         (6UL)    /*!< SYNC6 (Bit 6)                                         */
45006  #define R_MTU_TSYRB_SYNC6_Msk         (0x40UL) /*!< SYNC6 (Bitfield-Mask: 0x01)                           */
45007  #define R_MTU_TSYRB_SYNC7_Pos         (7UL)    /*!< SYNC7 (Bit 7)                                         */
45008  #define R_MTU_TSYRB_SYNC7_Msk         (0x80UL) /*!< SYNC7 (Bitfield-Mask: 0x01)                           */
45009 /* ========================================================  TRWERB  ========================================================= */
45010  #define R_MTU_TRWERB_RWE_Pos          (0UL)    /*!< RWE (Bit 0)                                           */
45011  #define R_MTU_TRWERB_RWE_Msk          (0x1UL)  /*!< RWE (Bitfield-Mask: 0x01)                             */
45012 
45013 /* =========================================================================================================================== */
45014 /* ================                                          R_MTU3                                           ================ */
45015 /* =========================================================================================================================== */
45016 
45017 /* ==========================================================  TCR  ========================================================== */
45018  #define R_MTU3_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
45019  #define R_MTU3_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45020  #define R_MTU3_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
45021  #define R_MTU3_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45022  #define R_MTU3_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
45023  #define R_MTU3_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45024 /* =========================================================  TMDR1  ========================================================= */
45025  #define R_MTU3_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
45026  #define R_MTU3_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45027  #define R_MTU3_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
45028  #define R_MTU3_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
45029  #define R_MTU3_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
45030  #define R_MTU3_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
45031 /* =========================================================  TIORH  ========================================================= */
45032  #define R_MTU3_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
45033  #define R_MTU3_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45034  #define R_MTU3_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
45035  #define R_MTU3_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45036 /* =========================================================  TIORL  ========================================================= */
45037  #define R_MTU3_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
45038  #define R_MTU3_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
45039  #define R_MTU3_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
45040  #define R_MTU3_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
45041 /* =========================================================  TIER  ========================================================== */
45042  #define R_MTU3_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
45043  #define R_MTU3_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45044  #define R_MTU3_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
45045  #define R_MTU3_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45046  #define R_MTU3_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
45047  #define R_MTU3_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
45048  #define R_MTU3_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
45049  #define R_MTU3_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
45050  #define R_MTU3_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
45051  #define R_MTU3_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45052  #define R_MTU3_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
45053  #define R_MTU3_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
45054 /* =========================================================  TCNT  ========================================================== */
45055 /* =========================================================  TGRA  ========================================================== */
45056 /* =========================================================  TGRB  ========================================================== */
45057 /* =========================================================  TGRC  ========================================================== */
45058 /* =========================================================  TGRD  ========================================================== */
45059 /* ==========================================================  TSR  ========================================================== */
45060  #define R_MTU3_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
45061  #define R_MTU3_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
45062  #define R_MTU3_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
45063  #define R_MTU3_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
45064  #define R_MTU3_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
45065  #define R_MTU3_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
45066  #define R_MTU3_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
45067  #define R_MTU3_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
45068  #define R_MTU3_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
45069  #define R_MTU3_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
45070  #define R_MTU3_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
45071  #define R_MTU3_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
45072  #define R_MTU3_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
45073  #define R_MTU3_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
45074 /* =========================================================  TBTM  ========================================================== */
45075  #define R_MTU3_TBTM_TTSA_Pos     (0UL)    /*!< TTSA (Bit 0)                                          */
45076  #define R_MTU3_TBTM_TTSA_Msk     (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
45077  #define R_MTU3_TBTM_TTSB_Pos     (1UL)    /*!< TTSB (Bit 1)                                          */
45078  #define R_MTU3_TBTM_TTSB_Msk     (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
45079 /* =========================================================  TCR2  ========================================================== */
45080  #define R_MTU3_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
45081  #define R_MTU3_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45082 /* =========================================================  TGRE  ========================================================== */
45083 
45084 /* =========================================================================================================================== */
45085 /* ================                                          R_MTU4                                           ================ */
45086 /* =========================================================================================================================== */
45087 
45088 /* ==========================================================  TCR  ========================================================== */
45089  #define R_MTU4_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
45090  #define R_MTU4_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45091  #define R_MTU4_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
45092  #define R_MTU4_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45093  #define R_MTU4_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
45094  #define R_MTU4_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45095 /* =========================================================  TMDR1  ========================================================= */
45096  #define R_MTU4_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
45097  #define R_MTU4_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45098  #define R_MTU4_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
45099  #define R_MTU4_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
45100  #define R_MTU4_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
45101  #define R_MTU4_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
45102 /* =========================================================  TIORH  ========================================================= */
45103  #define R_MTU4_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
45104  #define R_MTU4_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45105  #define R_MTU4_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
45106  #define R_MTU4_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45107 /* =========================================================  TIORL  ========================================================= */
45108  #define R_MTU4_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
45109  #define R_MTU4_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
45110  #define R_MTU4_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
45111  #define R_MTU4_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
45112 /* =========================================================  TIER  ========================================================== */
45113  #define R_MTU4_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
45114  #define R_MTU4_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45115  #define R_MTU4_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
45116  #define R_MTU4_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45117  #define R_MTU4_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
45118  #define R_MTU4_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
45119  #define R_MTU4_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
45120  #define R_MTU4_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
45121  #define R_MTU4_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
45122  #define R_MTU4_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45123  #define R_MTU4_TIER_TTGE2_Pos    (6UL)    /*!< TTGE2 (Bit 6)                                         */
45124  #define R_MTU4_TIER_TTGE2_Msk    (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
45125  #define R_MTU4_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
45126  #define R_MTU4_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
45127 /* =========================================================  TCNT  ========================================================== */
45128 /* =========================================================  TGRA  ========================================================== */
45129 /* =========================================================  TGRB  ========================================================== */
45130 /* =========================================================  TGRC  ========================================================== */
45131 /* =========================================================  TGRD  ========================================================== */
45132 /* ==========================================================  TSR  ========================================================== */
45133  #define R_MTU4_TSR_TGFA_Pos        (0UL)      /*!< TGFA (Bit 0)                                          */
45134  #define R_MTU4_TSR_TGFA_Msk        (0x1UL)    /*!< TGFA (Bitfield-Mask: 0x01)                            */
45135  #define R_MTU4_TSR_TGFB_Pos        (1UL)      /*!< TGFB (Bit 1)                                          */
45136  #define R_MTU4_TSR_TGFB_Msk        (0x2UL)    /*!< TGFB (Bitfield-Mask: 0x01)                            */
45137  #define R_MTU4_TSR_TGFC_Pos        (2UL)      /*!< TGFC (Bit 2)                                          */
45138  #define R_MTU4_TSR_TGFC_Msk        (0x4UL)    /*!< TGFC (Bitfield-Mask: 0x01)                            */
45139  #define R_MTU4_TSR_TGFD_Pos        (3UL)      /*!< TGFD (Bit 3)                                          */
45140  #define R_MTU4_TSR_TGFD_Msk        (0x8UL)    /*!< TGFD (Bitfield-Mask: 0x01)                            */
45141  #define R_MTU4_TSR_TCFV_Pos        (4UL)      /*!< TCFV (Bit 4)                                          */
45142  #define R_MTU4_TSR_TCFV_Msk        (0x10UL)   /*!< TCFV (Bitfield-Mask: 0x01)                            */
45143  #define R_MTU4_TSR_TCFU_Pos        (5UL)      /*!< TCFU (Bit 5)                                          */
45144  #define R_MTU4_TSR_TCFU_Msk        (0x20UL)   /*!< TCFU (Bitfield-Mask: 0x01)                            */
45145  #define R_MTU4_TSR_TCFD_Pos        (7UL)      /*!< TCFD (Bit 7)                                          */
45146  #define R_MTU4_TSR_TCFD_Msk        (0x80UL)   /*!< TCFD (Bitfield-Mask: 0x01)                            */
45147 /* =========================================================  TBTM  ========================================================== */
45148  #define R_MTU4_TBTM_TTSA_Pos       (0UL)      /*!< TTSA (Bit 0)                                          */
45149  #define R_MTU4_TBTM_TTSA_Msk       (0x1UL)    /*!< TTSA (Bitfield-Mask: 0x01)                            */
45150  #define R_MTU4_TBTM_TTSB_Pos       (1UL)      /*!< TTSB (Bit 1)                                          */
45151  #define R_MTU4_TBTM_TTSB_Msk       (0x2UL)    /*!< TTSB (Bitfield-Mask: 0x01)                            */
45152 /* =========================================================  TADCR  ========================================================= */
45153  #define R_MTU4_TADCR_ITB4VE_Pos    (0UL)      /*!< ITB4VE (Bit 0)                                        */
45154  #define R_MTU4_TADCR_ITB4VE_Msk    (0x1UL)    /*!< ITB4VE (Bitfield-Mask: 0x01)                          */
45155  #define R_MTU4_TADCR_ITB3AE_Pos    (1UL)      /*!< ITB3AE (Bit 1)                                        */
45156  #define R_MTU4_TADCR_ITB3AE_Msk    (0x2UL)    /*!< ITB3AE (Bitfield-Mask: 0x01)                          */
45157  #define R_MTU4_TADCR_ITA4VE_Pos    (2UL)      /*!< ITA4VE (Bit 2)                                        */
45158  #define R_MTU4_TADCR_ITA4VE_Msk    (0x4UL)    /*!< ITA4VE (Bitfield-Mask: 0x01)                          */
45159  #define R_MTU4_TADCR_ITA3AE_Pos    (3UL)      /*!< ITA3AE (Bit 3)                                        */
45160  #define R_MTU4_TADCR_ITA3AE_Msk    (0x8UL)    /*!< ITA3AE (Bitfield-Mask: 0x01)                          */
45161  #define R_MTU4_TADCR_DT4BE_Pos     (4UL)      /*!< DT4BE (Bit 4)                                         */
45162  #define R_MTU4_TADCR_DT4BE_Msk     (0x10UL)   /*!< DT4BE (Bitfield-Mask: 0x01)                           */
45163  #define R_MTU4_TADCR_UT4BE_Pos     (5UL)      /*!< UT4BE (Bit 5)                                         */
45164  #define R_MTU4_TADCR_UT4BE_Msk     (0x20UL)   /*!< UT4BE (Bitfield-Mask: 0x01)                           */
45165  #define R_MTU4_TADCR_DT4AE_Pos     (6UL)      /*!< DT4AE (Bit 6)                                         */
45166  #define R_MTU4_TADCR_DT4AE_Msk     (0x40UL)   /*!< DT4AE (Bitfield-Mask: 0x01)                           */
45167  #define R_MTU4_TADCR_UT4AE_Pos     (7UL)      /*!< UT4AE (Bit 7)                                         */
45168  #define R_MTU4_TADCR_UT4AE_Msk     (0x80UL)   /*!< UT4AE (Bitfield-Mask: 0x01)                           */
45169  #define R_MTU4_TADCR_BF_Pos        (14UL)     /*!< BF (Bit 14)                                           */
45170  #define R_MTU4_TADCR_BF_Msk        (0xc000UL) /*!< BF (Bitfield-Mask: 0x03)                              */
45171 /* ========================================================  TADCORA  ======================================================== */
45172 /* ========================================================  TADCORB  ======================================================== */
45173 /* =======================================================  TADCOBRA  ======================================================== */
45174 /* =======================================================  TADCOBRB  ======================================================== */
45175 /* =========================================================  TCR2  ========================================================== */
45176  #define R_MTU4_TCR2_TPSC2_Pos    (0UL)   /*!< TPSC2 (Bit 0)                                         */
45177  #define R_MTU4_TCR2_TPSC2_Msk    (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45178 /* =========================================================  TGRE  ========================================================== */
45179 /* =========================================================  TGRF  ========================================================== */
45180 
45181 /* =========================================================================================================================== */
45182 /* ================                                         R_MTU_NF                                          ================ */
45183 /* =========================================================================================================================== */
45184 
45185 /* =========================================================  NFCR0  ========================================================= */
45186  #define R_MTU_NF_NFCR0_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45187  #define R_MTU_NF_NFCR0_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45188  #define R_MTU_NF_NFCR0_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45189  #define R_MTU_NF_NFCR0_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45190  #define R_MTU_NF_NFCR0_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
45191  #define R_MTU_NF_NFCR0_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
45192  #define R_MTU_NF_NFCR0_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
45193  #define R_MTU_NF_NFCR0_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
45194  #define R_MTU_NF_NFCR0_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45195  #define R_MTU_NF_NFCR0_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45196 /* =========================================================  NFCR1  ========================================================= */
45197  #define R_MTU_NF_NFCR1_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45198  #define R_MTU_NF_NFCR1_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45199  #define R_MTU_NF_NFCR1_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45200  #define R_MTU_NF_NFCR1_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45201  #define R_MTU_NF_NFCR1_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45202  #define R_MTU_NF_NFCR1_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45203 /* =========================================================  NFCR2  ========================================================= */
45204  #define R_MTU_NF_NFCR2_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45205  #define R_MTU_NF_NFCR2_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45206  #define R_MTU_NF_NFCR2_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45207  #define R_MTU_NF_NFCR2_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45208  #define R_MTU_NF_NFCR2_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45209  #define R_MTU_NF_NFCR2_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45210 /* =========================================================  NFCR3  ========================================================= */
45211  #define R_MTU_NF_NFCR3_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45212  #define R_MTU_NF_NFCR3_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45213  #define R_MTU_NF_NFCR3_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45214  #define R_MTU_NF_NFCR3_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45215  #define R_MTU_NF_NFCR3_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
45216  #define R_MTU_NF_NFCR3_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
45217  #define R_MTU_NF_NFCR3_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
45218  #define R_MTU_NF_NFCR3_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
45219  #define R_MTU_NF_NFCR3_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45220  #define R_MTU_NF_NFCR3_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45221 /* =========================================================  NFCR4  ========================================================= */
45222  #define R_MTU_NF_NFCR4_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45223  #define R_MTU_NF_NFCR4_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45224  #define R_MTU_NF_NFCR4_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45225  #define R_MTU_NF_NFCR4_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45226  #define R_MTU_NF_NFCR4_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
45227  #define R_MTU_NF_NFCR4_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
45228  #define R_MTU_NF_NFCR4_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
45229  #define R_MTU_NF_NFCR4_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
45230  #define R_MTU_NF_NFCR4_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45231  #define R_MTU_NF_NFCR4_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45232 /* =========================================================  NFCR8  ========================================================= */
45233  #define R_MTU_NF_NFCR8_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45234  #define R_MTU_NF_NFCR8_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45235  #define R_MTU_NF_NFCR8_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45236  #define R_MTU_NF_NFCR8_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45237  #define R_MTU_NF_NFCR8_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
45238  #define R_MTU_NF_NFCR8_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
45239  #define R_MTU_NF_NFCR8_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
45240  #define R_MTU_NF_NFCR8_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
45241  #define R_MTU_NF_NFCR8_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45242  #define R_MTU_NF_NFCR8_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45243 /* =========================================================  NFCRC  ========================================================= */
45244  #define R_MTU_NF_NFCRC_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45245  #define R_MTU_NF_NFCRC_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45246  #define R_MTU_NF_NFCRC_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45247  #define R_MTU_NF_NFCRC_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45248  #define R_MTU_NF_NFCRC_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
45249  #define R_MTU_NF_NFCRC_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
45250  #define R_MTU_NF_NFCRC_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
45251  #define R_MTU_NF_NFCRC_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
45252  #define R_MTU_NF_NFCRC_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45253  #define R_MTU_NF_NFCRC_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45254 /* =========================================================  NFCR6  ========================================================= */
45255  #define R_MTU_NF_NFCR6_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45256  #define R_MTU_NF_NFCR6_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45257  #define R_MTU_NF_NFCR6_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45258  #define R_MTU_NF_NFCR6_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45259  #define R_MTU_NF_NFCR6_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
45260  #define R_MTU_NF_NFCR6_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
45261  #define R_MTU_NF_NFCR6_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
45262  #define R_MTU_NF_NFCR6_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
45263  #define R_MTU_NF_NFCR6_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45264  #define R_MTU_NF_NFCR6_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45265 /* =========================================================  NFCR7  ========================================================= */
45266  #define R_MTU_NF_NFCR7_NFAEN_Pos    (0UL)    /*!< NFAEN (Bit 0)                                         */
45267  #define R_MTU_NF_NFCR7_NFAEN_Msk    (0x1UL)  /*!< NFAEN (Bitfield-Mask: 0x01)                           */
45268  #define R_MTU_NF_NFCR7_NFBEN_Pos    (1UL)    /*!< NFBEN (Bit 1)                                         */
45269  #define R_MTU_NF_NFCR7_NFBEN_Msk    (0x2UL)  /*!< NFBEN (Bitfield-Mask: 0x01)                           */
45270  #define R_MTU_NF_NFCR7_NFCEN_Pos    (2UL)    /*!< NFCEN (Bit 2)                                         */
45271  #define R_MTU_NF_NFCR7_NFCEN_Msk    (0x4UL)  /*!< NFCEN (Bitfield-Mask: 0x01)                           */
45272  #define R_MTU_NF_NFCR7_NFDEN_Pos    (3UL)    /*!< NFDEN (Bit 3)                                         */
45273  #define R_MTU_NF_NFCR7_NFDEN_Msk    (0x8UL)  /*!< NFDEN (Bitfield-Mask: 0x01)                           */
45274  #define R_MTU_NF_NFCR7_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45275  #define R_MTU_NF_NFCR7_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45276 /* =========================================================  NFCR5  ========================================================= */
45277  #define R_MTU_NF_NFCR5_NFUEN_Pos    (0UL)    /*!< NFUEN (Bit 0)                                         */
45278  #define R_MTU_NF_NFCR5_NFUEN_Msk    (0x1UL)  /*!< NFUEN (Bitfield-Mask: 0x01)                           */
45279  #define R_MTU_NF_NFCR5_NFVEN_Pos    (1UL)    /*!< NFVEN (Bit 1)                                         */
45280  #define R_MTU_NF_NFCR5_NFVEN_Msk    (0x2UL)  /*!< NFVEN (Bitfield-Mask: 0x01)                           */
45281  #define R_MTU_NF_NFCR5_NFWEN_Pos    (2UL)    /*!< NFWEN (Bit 2)                                         */
45282  #define R_MTU_NF_NFCR5_NFWEN_Msk    (0x4UL)  /*!< NFWEN (Bitfield-Mask: 0x01)                           */
45283  #define R_MTU_NF_NFCR5_NFCS_Pos     (4UL)    /*!< NFCS (Bit 4)                                          */
45284  #define R_MTU_NF_NFCR5_NFCS_Msk     (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
45285 
45286 /* =========================================================================================================================== */
45287 /* ================                                          R_MTU0                                           ================ */
45288 /* =========================================================================================================================== */
45289 
45290 /* ==========================================================  TCR  ========================================================== */
45291  #define R_MTU0_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
45292  #define R_MTU0_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45293  #define R_MTU0_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
45294  #define R_MTU0_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45295  #define R_MTU0_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
45296  #define R_MTU0_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45297 /* =========================================================  TMDR1  ========================================================= */
45298  #define R_MTU0_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
45299  #define R_MTU0_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45300  #define R_MTU0_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
45301  #define R_MTU0_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
45302  #define R_MTU0_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
45303  #define R_MTU0_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
45304  #define R_MTU0_TMDR1_BFE_Pos     (6UL)    /*!< BFE (Bit 6)                                           */
45305  #define R_MTU0_TMDR1_BFE_Msk     (0x40UL) /*!< BFE (Bitfield-Mask: 0x01)                             */
45306 /* =========================================================  TIORH  ========================================================= */
45307  #define R_MTU0_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
45308  #define R_MTU0_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45309  #define R_MTU0_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
45310  #define R_MTU0_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45311 /* =========================================================  TIORL  ========================================================= */
45312  #define R_MTU0_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
45313  #define R_MTU0_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
45314  #define R_MTU0_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
45315  #define R_MTU0_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
45316 /* =========================================================  TIER  ========================================================== */
45317  #define R_MTU0_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
45318  #define R_MTU0_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45319  #define R_MTU0_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
45320  #define R_MTU0_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45321  #define R_MTU0_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
45322  #define R_MTU0_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
45323  #define R_MTU0_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
45324  #define R_MTU0_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
45325  #define R_MTU0_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
45326  #define R_MTU0_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45327  #define R_MTU0_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
45328  #define R_MTU0_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
45329 /* =========================================================  TCNT  ========================================================== */
45330 /* =========================================================  TGRA  ========================================================== */
45331 /* =========================================================  TGRB  ========================================================== */
45332 /* =========================================================  TGRC  ========================================================== */
45333 /* =========================================================  TGRD  ========================================================== */
45334 /* =========================================================  TGRE  ========================================================== */
45335 /* =========================================================  TGRF  ========================================================== */
45336 /* =========================================================  TIER2  ========================================================= */
45337  #define R_MTU0_TIER2_TGIEE_Pos    (0UL)    /*!< TGIEE (Bit 0)                                         */
45338  #define R_MTU0_TIER2_TGIEE_Msk    (0x1UL)  /*!< TGIEE (Bitfield-Mask: 0x01)                           */
45339  #define R_MTU0_TIER2_TGIEF_Pos    (1UL)    /*!< TGIEF (Bit 1)                                         */
45340  #define R_MTU0_TIER2_TGIEF_Msk    (0x2UL)  /*!< TGIEF (Bitfield-Mask: 0x01)                           */
45341  #define R_MTU0_TIER2_TTGE2_Pos    (7UL)    /*!< TTGE2 (Bit 7)                                         */
45342  #define R_MTU0_TIER2_TTGE2_Msk    (0x80UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
45343 /* =========================================================  TBTM  ========================================================== */
45344  #define R_MTU0_TBTM_TTSA_Pos      (0UL)    /*!< TTSA (Bit 0)                                          */
45345  #define R_MTU0_TBTM_TTSA_Msk      (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
45346  #define R_MTU0_TBTM_TTSB_Pos      (1UL)    /*!< TTSB (Bit 1)                                          */
45347  #define R_MTU0_TBTM_TTSB_Msk      (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
45348  #define R_MTU0_TBTM_TTSE_Pos      (2UL)    /*!< TTSE (Bit 2)                                          */
45349  #define R_MTU0_TBTM_TTSE_Msk      (0x4UL)  /*!< TTSE (Bitfield-Mask: 0x01)                            */
45350 /* =========================================================  TCR2  ========================================================== */
45351  #define R_MTU0_TCR2_TPSC2_Pos     (0UL)    /*!< TPSC2 (Bit 0)                                         */
45352  #define R_MTU0_TCR2_TPSC2_Msk     (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45353 
45354 /* =========================================================================================================================== */
45355 /* ================                                          R_MTU1                                           ================ */
45356 /* =========================================================================================================================== */
45357 
45358 /* ==========================================================  TCR  ========================================================== */
45359  #define R_MTU1_TCR_TPSC_Pos         (0UL)    /*!< TPSC (Bit 0)                                          */
45360  #define R_MTU1_TCR_TPSC_Msk         (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45361  #define R_MTU1_TCR_CKEG_Pos         (3UL)    /*!< CKEG (Bit 3)                                          */
45362  #define R_MTU1_TCR_CKEG_Msk         (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45363  #define R_MTU1_TCR_CCLR_Pos         (5UL)    /*!< CCLR (Bit 5)                                          */
45364  #define R_MTU1_TCR_CCLR_Msk         (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45365 /* =========================================================  TMDR1  ========================================================= */
45366  #define R_MTU1_TMDR1_MD_Pos         (0UL)    /*!< MD (Bit 0)                                            */
45367  #define R_MTU1_TMDR1_MD_Msk         (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45368 /* =========================================================  TIOR  ========================================================== */
45369  #define R_MTU1_TIOR_IOA_Pos         (0UL)    /*!< IOA (Bit 0)                                           */
45370  #define R_MTU1_TIOR_IOA_Msk         (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45371  #define R_MTU1_TIOR_IOB_Pos         (4UL)    /*!< IOB (Bit 4)                                           */
45372  #define R_MTU1_TIOR_IOB_Msk         (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45373 /* =========================================================  TIER  ========================================================== */
45374  #define R_MTU1_TIER_TGIEA_Pos       (0UL)    /*!< TGIEA (Bit 0)                                         */
45375  #define R_MTU1_TIER_TGIEA_Msk       (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45376  #define R_MTU1_TIER_TGIEB_Pos       (1UL)    /*!< TGIEB (Bit 1)                                         */
45377  #define R_MTU1_TIER_TGIEB_Msk       (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45378  #define R_MTU1_TIER_TCIEV_Pos       (4UL)    /*!< TCIEV (Bit 4)                                         */
45379  #define R_MTU1_TIER_TCIEV_Msk       (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45380  #define R_MTU1_TIER_TCIEU_Pos       (5UL)    /*!< TCIEU (Bit 5)                                         */
45381  #define R_MTU1_TIER_TCIEU_Msk       (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01)                           */
45382  #define R_MTU1_TIER_TTGE_Pos        (7UL)    /*!< TTGE (Bit 7)                                          */
45383  #define R_MTU1_TIER_TTGE_Msk        (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
45384 /* ==========================================================  TSR  ========================================================== */
45385  #define R_MTU1_TSR_TGFA_Pos         (0UL)    /*!< TGFA (Bit 0)                                          */
45386  #define R_MTU1_TSR_TGFA_Msk         (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
45387  #define R_MTU1_TSR_TGFB_Pos         (1UL)    /*!< TGFB (Bit 1)                                          */
45388  #define R_MTU1_TSR_TGFB_Msk         (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
45389  #define R_MTU1_TSR_TGFC_Pos         (2UL)    /*!< TGFC (Bit 2)                                          */
45390  #define R_MTU1_TSR_TGFC_Msk         (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
45391  #define R_MTU1_TSR_TGFD_Pos         (3UL)    /*!< TGFD (Bit 3)                                          */
45392  #define R_MTU1_TSR_TGFD_Msk         (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
45393  #define R_MTU1_TSR_TCFV_Pos         (4UL)    /*!< TCFV (Bit 4)                                          */
45394  #define R_MTU1_TSR_TCFV_Msk         (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
45395  #define R_MTU1_TSR_TCFU_Pos         (5UL)    /*!< TCFU (Bit 5)                                          */
45396  #define R_MTU1_TSR_TCFU_Msk         (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
45397  #define R_MTU1_TSR_TCFD_Pos         (7UL)    /*!< TCFD (Bit 7)                                          */
45398  #define R_MTU1_TSR_TCFD_Msk         (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
45399 /* =========================================================  TCNT  ========================================================== */
45400 /* =========================================================  TGRA  ========================================================== */
45401 /* =========================================================  TGRB  ========================================================== */
45402 /* =========================================================  TICCR  ========================================================= */
45403  #define R_MTU1_TICCR_I1AE_Pos       (0UL)    /*!< I1AE (Bit 0)                                          */
45404  #define R_MTU1_TICCR_I1AE_Msk       (0x1UL)  /*!< I1AE (Bitfield-Mask: 0x01)                            */
45405  #define R_MTU1_TICCR_I1BE_Pos       (1UL)    /*!< I1BE (Bit 1)                                          */
45406  #define R_MTU1_TICCR_I1BE_Msk       (0x2UL)  /*!< I1BE (Bitfield-Mask: 0x01)                            */
45407  #define R_MTU1_TICCR_I2AE_Pos       (2UL)    /*!< I2AE (Bit 2)                                          */
45408  #define R_MTU1_TICCR_I2AE_Msk       (0x4UL)  /*!< I2AE (Bitfield-Mask: 0x01)                            */
45409  #define R_MTU1_TICCR_I2BE_Pos       (3UL)    /*!< I2BE (Bit 3)                                          */
45410  #define R_MTU1_TICCR_I2BE_Msk       (0x8UL)  /*!< I2BE (Bitfield-Mask: 0x01)                            */
45411 /* =========================================================  TMDR3  ========================================================= */
45412  #define R_MTU1_TMDR3_LWA_Pos        (0UL)    /*!< LWA (Bit 0)                                           */
45413  #define R_MTU1_TMDR3_LWA_Msk        (0x1UL)  /*!< LWA (Bitfield-Mask: 0x01)                             */
45414  #define R_MTU1_TMDR3_PHCKSEL_Pos    (1UL)    /*!< PHCKSEL (Bit 1)                                       */
45415  #define R_MTU1_TMDR3_PHCKSEL_Msk    (0x2UL)  /*!< PHCKSEL (Bitfield-Mask: 0x01)                         */
45416 /* =========================================================  TCR2  ========================================================== */
45417  #define R_MTU1_TCR2_TPSC2_Pos       (0UL)    /*!< TPSC2 (Bit 0)                                         */
45418  #define R_MTU1_TCR2_TPSC2_Msk       (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45419  #define R_MTU1_TCR2_PCB_Pos         (3UL)    /*!< PCB (Bit 3)                                           */
45420  #define R_MTU1_TCR2_PCB_Msk         (0x18UL) /*!< PCB (Bitfield-Mask: 0x03)                             */
45421 /* ========================================================  TCNTLW  ========================================================= */
45422 /* ========================================================  TGRALW  ========================================================= */
45423 /* ========================================================  TGRBLW  ========================================================= */
45424 
45425 /* =========================================================================================================================== */
45426 /* ================                                          R_MTU2                                           ================ */
45427 /* =========================================================================================================================== */
45428 
45429 /* ==========================================================  TCR  ========================================================== */
45430  #define R_MTU2_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
45431  #define R_MTU2_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45432  #define R_MTU2_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
45433  #define R_MTU2_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45434  #define R_MTU2_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
45435  #define R_MTU2_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45436 /* =========================================================  TMDR1  ========================================================= */
45437  #define R_MTU2_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
45438  #define R_MTU2_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45439 /* =========================================================  TIOR  ========================================================== */
45440  #define R_MTU2_TIOR_IOA_Pos      (0UL)    /*!< IOA (Bit 0)                                           */
45441  #define R_MTU2_TIOR_IOA_Msk      (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45442  #define R_MTU2_TIOR_IOB_Pos      (4UL)    /*!< IOB (Bit 4)                                           */
45443  #define R_MTU2_TIOR_IOB_Msk      (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45444 /* =========================================================  TIER  ========================================================== */
45445  #define R_MTU2_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
45446  #define R_MTU2_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45447  #define R_MTU2_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
45448  #define R_MTU2_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45449  #define R_MTU2_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
45450  #define R_MTU2_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45451  #define R_MTU2_TIER_TCIEU_Pos    (5UL)    /*!< TCIEU (Bit 5)                                         */
45452  #define R_MTU2_TIER_TCIEU_Msk    (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01)                           */
45453  #define R_MTU2_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
45454  #define R_MTU2_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
45455 /* ==========================================================  TSR  ========================================================== */
45456  #define R_MTU2_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
45457  #define R_MTU2_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
45458  #define R_MTU2_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
45459  #define R_MTU2_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
45460  #define R_MTU2_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
45461  #define R_MTU2_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
45462  #define R_MTU2_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
45463  #define R_MTU2_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
45464  #define R_MTU2_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
45465  #define R_MTU2_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
45466  #define R_MTU2_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
45467  #define R_MTU2_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
45468  #define R_MTU2_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
45469  #define R_MTU2_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
45470 /* =========================================================  TCNT  ========================================================== */
45471 /* =========================================================  TGRA  ========================================================== */
45472 /* =========================================================  TGRB  ========================================================== */
45473 /* =========================================================  TCR2  ========================================================== */
45474  #define R_MTU2_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
45475  #define R_MTU2_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45476  #define R_MTU2_TCR2_PCB_Pos      (3UL)    /*!< PCB (Bit 3)                                           */
45477  #define R_MTU2_TCR2_PCB_Msk      (0x18UL) /*!< PCB (Bitfield-Mask: 0x03)                             */
45478 
45479 /* =========================================================================================================================== */
45480 /* ================                                          R_MTU8                                           ================ */
45481 /* =========================================================================================================================== */
45482 
45483 /* ==========================================================  TCR  ========================================================== */
45484  #define R_MTU8_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
45485  #define R_MTU8_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45486  #define R_MTU8_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
45487  #define R_MTU8_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45488  #define R_MTU8_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
45489  #define R_MTU8_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45490 /* =========================================================  TMDR1  ========================================================= */
45491  #define R_MTU8_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
45492  #define R_MTU8_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45493  #define R_MTU8_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
45494  #define R_MTU8_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
45495  #define R_MTU8_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
45496  #define R_MTU8_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
45497 /* =========================================================  TIORH  ========================================================= */
45498  #define R_MTU8_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
45499  #define R_MTU8_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45500  #define R_MTU8_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
45501  #define R_MTU8_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45502 /* =========================================================  TIORL  ========================================================= */
45503  #define R_MTU8_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
45504  #define R_MTU8_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
45505  #define R_MTU8_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
45506  #define R_MTU8_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
45507 /* =========================================================  TIER  ========================================================== */
45508  #define R_MTU8_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
45509  #define R_MTU8_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45510  #define R_MTU8_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
45511  #define R_MTU8_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45512  #define R_MTU8_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
45513  #define R_MTU8_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
45514  #define R_MTU8_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
45515  #define R_MTU8_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
45516  #define R_MTU8_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
45517  #define R_MTU8_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45518 /* =========================================================  TCR2  ========================================================== */
45519  #define R_MTU8_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
45520  #define R_MTU8_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45521 /* =========================================================  TCNT  ========================================================== */
45522 /* =========================================================  TGRA  ========================================================== */
45523 /* =========================================================  TGRB  ========================================================== */
45524 /* =========================================================  TGRC  ========================================================== */
45525 /* =========================================================  TGRD  ========================================================== */
45526 
45527 /* =========================================================================================================================== */
45528 /* ================                                          R_MTU6                                           ================ */
45529 /* =========================================================================================================================== */
45530 
45531 /* ==========================================================  TCR  ========================================================== */
45532  #define R_MTU6_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
45533  #define R_MTU6_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45534  #define R_MTU6_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
45535  #define R_MTU6_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45536  #define R_MTU6_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
45537  #define R_MTU6_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45538 /* =========================================================  TMDR1  ========================================================= */
45539  #define R_MTU6_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
45540  #define R_MTU6_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45541  #define R_MTU6_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
45542  #define R_MTU6_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
45543  #define R_MTU6_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
45544  #define R_MTU6_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
45545 /* =========================================================  TIORH  ========================================================= */
45546  #define R_MTU6_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
45547  #define R_MTU6_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45548  #define R_MTU6_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
45549  #define R_MTU6_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45550 /* =========================================================  TIORL  ========================================================= */
45551  #define R_MTU6_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
45552  #define R_MTU6_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
45553  #define R_MTU6_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
45554  #define R_MTU6_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
45555 /* =========================================================  TIER  ========================================================== */
45556  #define R_MTU6_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
45557  #define R_MTU6_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45558  #define R_MTU6_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
45559  #define R_MTU6_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45560  #define R_MTU6_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
45561  #define R_MTU6_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
45562  #define R_MTU6_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
45563  #define R_MTU6_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
45564  #define R_MTU6_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
45565  #define R_MTU6_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45566  #define R_MTU6_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
45567  #define R_MTU6_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
45568 /* =========================================================  TCNT  ========================================================== */
45569 /* =========================================================  TGRA  ========================================================== */
45570 /* =========================================================  TGRB  ========================================================== */
45571 /* =========================================================  TGRC  ========================================================== */
45572 /* =========================================================  TGRD  ========================================================== */
45573 /* ==========================================================  TSR  ========================================================== */
45574  #define R_MTU6_TSR_TGFA_Pos      (0UL)    /*!< TGFA (Bit 0)                                          */
45575  #define R_MTU6_TSR_TGFA_Msk      (0x1UL)  /*!< TGFA (Bitfield-Mask: 0x01)                            */
45576  #define R_MTU6_TSR_TGFB_Pos      (1UL)    /*!< TGFB (Bit 1)                                          */
45577  #define R_MTU6_TSR_TGFB_Msk      (0x2UL)  /*!< TGFB (Bitfield-Mask: 0x01)                            */
45578  #define R_MTU6_TSR_TGFC_Pos      (2UL)    /*!< TGFC (Bit 2)                                          */
45579  #define R_MTU6_TSR_TGFC_Msk      (0x4UL)  /*!< TGFC (Bitfield-Mask: 0x01)                            */
45580  #define R_MTU6_TSR_TGFD_Pos      (3UL)    /*!< TGFD (Bit 3)                                          */
45581  #define R_MTU6_TSR_TGFD_Msk      (0x8UL)  /*!< TGFD (Bitfield-Mask: 0x01)                            */
45582  #define R_MTU6_TSR_TCFV_Pos      (4UL)    /*!< TCFV (Bit 4)                                          */
45583  #define R_MTU6_TSR_TCFV_Msk      (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01)                            */
45584  #define R_MTU6_TSR_TCFU_Pos      (5UL)    /*!< TCFU (Bit 5)                                          */
45585  #define R_MTU6_TSR_TCFU_Msk      (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01)                            */
45586  #define R_MTU6_TSR_TCFD_Pos      (7UL)    /*!< TCFD (Bit 7)                                          */
45587  #define R_MTU6_TSR_TCFD_Msk      (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01)                            */
45588 /* =========================================================  TBTM  ========================================================== */
45589  #define R_MTU6_TBTM_TTSA_Pos     (0UL)    /*!< TTSA (Bit 0)                                          */
45590  #define R_MTU6_TBTM_TTSA_Msk     (0x1UL)  /*!< TTSA (Bitfield-Mask: 0x01)                            */
45591  #define R_MTU6_TBTM_TTSB_Pos     (1UL)    /*!< TTSB (Bit 1)                                          */
45592  #define R_MTU6_TBTM_TTSB_Msk     (0x2UL)  /*!< TTSB (Bitfield-Mask: 0x01)                            */
45593 /* =========================================================  TCR2  ========================================================== */
45594  #define R_MTU6_TCR2_TPSC2_Pos    (0UL)    /*!< TPSC2 (Bit 0)                                         */
45595  #define R_MTU6_TCR2_TPSC2_Msk    (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45596 /* =========================================================  TSYCR  ========================================================= */
45597  #define R_MTU6_TSYCR_CE2B_Pos    (0UL)    /*!< CE2B (Bit 0)                                          */
45598  #define R_MTU6_TSYCR_CE2B_Msk    (0x1UL)  /*!< CE2B (Bitfield-Mask: 0x01)                            */
45599  #define R_MTU6_TSYCR_CE2A_Pos    (1UL)    /*!< CE2A (Bit 1)                                          */
45600  #define R_MTU6_TSYCR_CE2A_Msk    (0x2UL)  /*!< CE2A (Bitfield-Mask: 0x01)                            */
45601  #define R_MTU6_TSYCR_CE1B_Pos    (2UL)    /*!< CE1B (Bit 2)                                          */
45602  #define R_MTU6_TSYCR_CE1B_Msk    (0x4UL)  /*!< CE1B (Bitfield-Mask: 0x01)                            */
45603  #define R_MTU6_TSYCR_CE1A_Pos    (3UL)    /*!< CE1A (Bit 3)                                          */
45604  #define R_MTU6_TSYCR_CE1A_Msk    (0x8UL)  /*!< CE1A (Bitfield-Mask: 0x01)                            */
45605  #define R_MTU6_TSYCR_CE0D_Pos    (4UL)    /*!< CE0D (Bit 4)                                          */
45606  #define R_MTU6_TSYCR_CE0D_Msk    (0x10UL) /*!< CE0D (Bitfield-Mask: 0x01)                            */
45607  #define R_MTU6_TSYCR_CE0C_Pos    (5UL)    /*!< CE0C (Bit 5)                                          */
45608  #define R_MTU6_TSYCR_CE0C_Msk    (0x20UL) /*!< CE0C (Bitfield-Mask: 0x01)                            */
45609  #define R_MTU6_TSYCR_CE0B_Pos    (6UL)    /*!< CE0B (Bit 6)                                          */
45610  #define R_MTU6_TSYCR_CE0B_Msk    (0x40UL) /*!< CE0B (Bitfield-Mask: 0x01)                            */
45611  #define R_MTU6_TSYCR_CE0A_Pos    (7UL)    /*!< CE0A (Bit 7)                                          */
45612  #define R_MTU6_TSYCR_CE0A_Msk    (0x80UL) /*!< CE0A (Bitfield-Mask: 0x01)                            */
45613 /* =========================================================  TGRE  ========================================================== */
45614 
45615 /* =========================================================================================================================== */
45616 /* ================                                          R_MTU7                                           ================ */
45617 /* =========================================================================================================================== */
45618 
45619 /* ==========================================================  TCR  ========================================================== */
45620  #define R_MTU7_TCR_TPSC_Pos      (0UL)    /*!< TPSC (Bit 0)                                          */
45621  #define R_MTU7_TCR_TPSC_Msk      (0x7UL)  /*!< TPSC (Bitfield-Mask: 0x07)                            */
45622  #define R_MTU7_TCR_CKEG_Pos      (3UL)    /*!< CKEG (Bit 3)                                          */
45623  #define R_MTU7_TCR_CKEG_Msk      (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45624  #define R_MTU7_TCR_CCLR_Pos      (5UL)    /*!< CCLR (Bit 5)                                          */
45625  #define R_MTU7_TCR_CCLR_Msk      (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07)                            */
45626 /* =========================================================  TMDR1  ========================================================= */
45627  #define R_MTU7_TMDR1_MD_Pos      (0UL)    /*!< MD (Bit 0)                                            */
45628  #define R_MTU7_TMDR1_MD_Msk      (0xfUL)  /*!< MD (Bitfield-Mask: 0x0f)                              */
45629  #define R_MTU7_TMDR1_BFA_Pos     (4UL)    /*!< BFA (Bit 4)                                           */
45630  #define R_MTU7_TMDR1_BFA_Msk     (0x10UL) /*!< BFA (Bitfield-Mask: 0x01)                             */
45631  #define R_MTU7_TMDR1_BFB_Pos     (5UL)    /*!< BFB (Bit 5)                                           */
45632  #define R_MTU7_TMDR1_BFB_Msk     (0x20UL) /*!< BFB (Bitfield-Mask: 0x01)                             */
45633 /* =========================================================  TIORH  ========================================================= */
45634  #define R_MTU7_TIORH_IOA_Pos     (0UL)    /*!< IOA (Bit 0)                                           */
45635  #define R_MTU7_TIORH_IOA_Msk     (0xfUL)  /*!< IOA (Bitfield-Mask: 0x0f)                             */
45636  #define R_MTU7_TIORH_IOB_Pos     (4UL)    /*!< IOB (Bit 4)                                           */
45637  #define R_MTU7_TIORH_IOB_Msk     (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f)                             */
45638 /* =========================================================  TIORL  ========================================================= */
45639  #define R_MTU7_TIORL_IOC_Pos     (0UL)    /*!< IOC (Bit 0)                                           */
45640  #define R_MTU7_TIORL_IOC_Msk     (0xfUL)  /*!< IOC (Bitfield-Mask: 0x0f)                             */
45641  #define R_MTU7_TIORL_IOD_Pos     (4UL)    /*!< IOD (Bit 4)                                           */
45642  #define R_MTU7_TIORL_IOD_Msk     (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f)                             */
45643 /* =========================================================  TIER  ========================================================== */
45644  #define R_MTU7_TIER_TGIEA_Pos    (0UL)    /*!< TGIEA (Bit 0)                                         */
45645  #define R_MTU7_TIER_TGIEA_Msk    (0x1UL)  /*!< TGIEA (Bitfield-Mask: 0x01)                           */
45646  #define R_MTU7_TIER_TGIEB_Pos    (1UL)    /*!< TGIEB (Bit 1)                                         */
45647  #define R_MTU7_TIER_TGIEB_Msk    (0x2UL)  /*!< TGIEB (Bitfield-Mask: 0x01)                           */
45648  #define R_MTU7_TIER_TGIEC_Pos    (2UL)    /*!< TGIEC (Bit 2)                                         */
45649  #define R_MTU7_TIER_TGIEC_Msk    (0x4UL)  /*!< TGIEC (Bitfield-Mask: 0x01)                           */
45650  #define R_MTU7_TIER_TGIED_Pos    (3UL)    /*!< TGIED (Bit 3)                                         */
45651  #define R_MTU7_TIER_TGIED_Msk    (0x8UL)  /*!< TGIED (Bitfield-Mask: 0x01)                           */
45652  #define R_MTU7_TIER_TCIEV_Pos    (4UL)    /*!< TCIEV (Bit 4)                                         */
45653  #define R_MTU7_TIER_TCIEV_Msk    (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01)                           */
45654  #define R_MTU7_TIER_TTGE2_Pos    (6UL)    /*!< TTGE2 (Bit 6)                                         */
45655  #define R_MTU7_TIER_TTGE2_Msk    (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01)                           */
45656  #define R_MTU7_TIER_TTGE_Pos     (7UL)    /*!< TTGE (Bit 7)                                          */
45657  #define R_MTU7_TIER_TTGE_Msk     (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01)                            */
45658 /* =========================================================  TCNT  ========================================================== */
45659 /* =========================================================  TGRA  ========================================================== */
45660 /* =========================================================  TGRB  ========================================================== */
45661 /* =========================================================  TGRC  ========================================================== */
45662 /* =========================================================  TGRD  ========================================================== */
45663 /* ==========================================================  TSR  ========================================================== */
45664  #define R_MTU7_TSR_TGFA_Pos        (0UL)      /*!< TGFA (Bit 0)                                          */
45665  #define R_MTU7_TSR_TGFA_Msk        (0x1UL)    /*!< TGFA (Bitfield-Mask: 0x01)                            */
45666  #define R_MTU7_TSR_TGFB_Pos        (1UL)      /*!< TGFB (Bit 1)                                          */
45667  #define R_MTU7_TSR_TGFB_Msk        (0x2UL)    /*!< TGFB (Bitfield-Mask: 0x01)                            */
45668  #define R_MTU7_TSR_TGFC_Pos        (2UL)      /*!< TGFC (Bit 2)                                          */
45669  #define R_MTU7_TSR_TGFC_Msk        (0x4UL)    /*!< TGFC (Bitfield-Mask: 0x01)                            */
45670  #define R_MTU7_TSR_TGFD_Pos        (3UL)      /*!< TGFD (Bit 3)                                          */
45671  #define R_MTU7_TSR_TGFD_Msk        (0x8UL)    /*!< TGFD (Bitfield-Mask: 0x01)                            */
45672  #define R_MTU7_TSR_TCFV_Pos        (4UL)      /*!< TCFV (Bit 4)                                          */
45673  #define R_MTU7_TSR_TCFV_Msk        (0x10UL)   /*!< TCFV (Bitfield-Mask: 0x01)                            */
45674  #define R_MTU7_TSR_TCFU_Pos        (5UL)      /*!< TCFU (Bit 5)                                          */
45675  #define R_MTU7_TSR_TCFU_Msk        (0x20UL)   /*!< TCFU (Bitfield-Mask: 0x01)                            */
45676  #define R_MTU7_TSR_TCFD_Pos        (7UL)      /*!< TCFD (Bit 7)                                          */
45677  #define R_MTU7_TSR_TCFD_Msk        (0x80UL)   /*!< TCFD (Bitfield-Mask: 0x01)                            */
45678 /* =========================================================  TBTM  ========================================================== */
45679  #define R_MTU7_TBTM_TTSA_Pos       (0UL)      /*!< TTSA (Bit 0)                                          */
45680  #define R_MTU7_TBTM_TTSA_Msk       (0x1UL)    /*!< TTSA (Bitfield-Mask: 0x01)                            */
45681  #define R_MTU7_TBTM_TTSB_Pos       (1UL)      /*!< TTSB (Bit 1)                                          */
45682  #define R_MTU7_TBTM_TTSB_Msk       (0x2UL)    /*!< TTSB (Bitfield-Mask: 0x01)                            */
45683 /* =========================================================  TADCR  ========================================================= */
45684  #define R_MTU7_TADCR_ITB7VE_Pos    (0UL)      /*!< ITB7VE (Bit 0)                                        */
45685  #define R_MTU7_TADCR_ITB7VE_Msk    (0x1UL)    /*!< ITB7VE (Bitfield-Mask: 0x01)                          */
45686  #define R_MTU7_TADCR_ITB6AE_Pos    (1UL)      /*!< ITB6AE (Bit 1)                                        */
45687  #define R_MTU7_TADCR_ITB6AE_Msk    (0x2UL)    /*!< ITB6AE (Bitfield-Mask: 0x01)                          */
45688  #define R_MTU7_TADCR_ITA7VE_Pos    (2UL)      /*!< ITA7VE (Bit 2)                                        */
45689  #define R_MTU7_TADCR_ITA7VE_Msk    (0x4UL)    /*!< ITA7VE (Bitfield-Mask: 0x01)                          */
45690  #define R_MTU7_TADCR_ITA6AE_Pos    (3UL)      /*!< ITA6AE (Bit 3)                                        */
45691  #define R_MTU7_TADCR_ITA6AE_Msk    (0x8UL)    /*!< ITA6AE (Bitfield-Mask: 0x01)                          */
45692  #define R_MTU7_TADCR_DT7BE_Pos     (4UL)      /*!< DT7BE (Bit 4)                                         */
45693  #define R_MTU7_TADCR_DT7BE_Msk     (0x10UL)   /*!< DT7BE (Bitfield-Mask: 0x01)                           */
45694  #define R_MTU7_TADCR_UT7BE_Pos     (5UL)      /*!< UT7BE (Bit 5)                                         */
45695  #define R_MTU7_TADCR_UT7BE_Msk     (0x20UL)   /*!< UT7BE (Bitfield-Mask: 0x01)                           */
45696  #define R_MTU7_TADCR_DT7AE_Pos     (6UL)      /*!< DT7AE (Bit 6)                                         */
45697  #define R_MTU7_TADCR_DT7AE_Msk     (0x40UL)   /*!< DT7AE (Bitfield-Mask: 0x01)                           */
45698  #define R_MTU7_TADCR_UT7AE_Pos     (7UL)      /*!< UT7AE (Bit 7)                                         */
45699  #define R_MTU7_TADCR_UT7AE_Msk     (0x80UL)   /*!< UT7AE (Bitfield-Mask: 0x01)                           */
45700  #define R_MTU7_TADCR_BF_Pos        (14UL)     /*!< BF (Bit 14)                                           */
45701  #define R_MTU7_TADCR_BF_Msk        (0xc000UL) /*!< BF (Bitfield-Mask: 0x03)                              */
45702 /* ========================================================  TADCORA  ======================================================== */
45703 /* ========================================================  TADCORB  ======================================================== */
45704 /* =======================================================  TADCOBRA  ======================================================== */
45705 /* =======================================================  TADCOBRB  ======================================================== */
45706 /* =========================================================  TCR2  ========================================================== */
45707  #define R_MTU7_TCR2_TPSC2_Pos    (0UL)   /*!< TPSC2 (Bit 0)                                         */
45708  #define R_MTU7_TCR2_TPSC2_Msk    (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45709 /* =========================================================  TGRE  ========================================================== */
45710 /* =========================================================  TGRF  ========================================================== */
45711 
45712 /* =========================================================================================================================== */
45713 /* ================                                          R_MTU5                                           ================ */
45714 /* =========================================================================================================================== */
45715 
45716 /* =========================================================  TCNTU  ========================================================= */
45717 /* =========================================================  TGRU  ========================================================== */
45718 /* =========================================================  TCRU  ========================================================== */
45719  #define R_MTU5_TCRU_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
45720  #define R_MTU5_TCRU_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
45721 /* =========================================================  TCR2U  ========================================================= */
45722  #define R_MTU5_TCR2U_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
45723  #define R_MTU5_TCR2U_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45724  #define R_MTU5_TCR2U_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
45725  #define R_MTU5_TCR2U_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45726 /* =========================================================  TIORU  ========================================================= */
45727  #define R_MTU5_TIORU_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
45728  #define R_MTU5_TIORU_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
45729 /* =========================================================  TCNTV  ========================================================= */
45730 /* =========================================================  TGRV  ========================================================== */
45731 /* =========================================================  TCRV  ========================================================== */
45732  #define R_MTU5_TCRV_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
45733  #define R_MTU5_TCRV_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
45734 /* =========================================================  TCR2V  ========================================================= */
45735  #define R_MTU5_TCR2V_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
45736  #define R_MTU5_TCR2V_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45737  #define R_MTU5_TCR2V_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
45738  #define R_MTU5_TCR2V_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45739 /* =========================================================  TIORV  ========================================================= */
45740  #define R_MTU5_TIORV_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
45741  #define R_MTU5_TIORV_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
45742 /* =========================================================  TCNTW  ========================================================= */
45743 /* =========================================================  TGRW  ========================================================== */
45744 /* =========================================================  TCRW  ========================================================== */
45745  #define R_MTU5_TCRW_TPSC_Pos              (0UL)    /*!< TPSC (Bit 0)                                          */
45746  #define R_MTU5_TCRW_TPSC_Msk              (0x3UL)  /*!< TPSC (Bitfield-Mask: 0x03)                            */
45747 /* =========================================================  TCR2W  ========================================================= */
45748  #define R_MTU5_TCR2W_TPSC2_Pos            (0UL)    /*!< TPSC2 (Bit 0)                                         */
45749  #define R_MTU5_TCR2W_TPSC2_Msk            (0x7UL)  /*!< TPSC2 (Bitfield-Mask: 0x07)                           */
45750  #define R_MTU5_TCR2W_CKEG_Pos             (3UL)    /*!< CKEG (Bit 3)                                          */
45751  #define R_MTU5_TCR2W_CKEG_Msk             (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03)                            */
45752 /* =========================================================  TIORW  ========================================================= */
45753  #define R_MTU5_TIORW_IOC_Pos              (0UL)    /*!< IOC (Bit 0)                                           */
45754  #define R_MTU5_TIORW_IOC_Msk              (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f)                             */
45755 /* =========================================================  TIER  ========================================================== */
45756  #define R_MTU5_TIER_TGIE5W_Pos            (0UL)    /*!< TGIE5W (Bit 0)                                        */
45757  #define R_MTU5_TIER_TGIE5W_Msk            (0x1UL)  /*!< TGIE5W (Bitfield-Mask: 0x01)                          */
45758  #define R_MTU5_TIER_TGIE5V_Pos            (1UL)    /*!< TGIE5V (Bit 1)                                        */
45759  #define R_MTU5_TIER_TGIE5V_Msk            (0x2UL)  /*!< TGIE5V (Bitfield-Mask: 0x01)                          */
45760  #define R_MTU5_TIER_TGIE5U_Pos            (2UL)    /*!< TGIE5U (Bit 2)                                        */
45761  #define R_MTU5_TIER_TGIE5U_Msk            (0x4UL)  /*!< TGIE5U (Bitfield-Mask: 0x01)                          */
45762 /* =========================================================  TSTR  ========================================================== */
45763  #define R_MTU5_TSTR_CSTW5_Pos             (0UL)    /*!< CSTW5 (Bit 0)                                         */
45764  #define R_MTU5_TSTR_CSTW5_Msk             (0x1UL)  /*!< CSTW5 (Bitfield-Mask: 0x01)                           */
45765  #define R_MTU5_TSTR_CSTV5_Pos             (1UL)    /*!< CSTV5 (Bit 1)                                         */
45766  #define R_MTU5_TSTR_CSTV5_Msk             (0x2UL)  /*!< CSTV5 (Bitfield-Mask: 0x01)                           */
45767  #define R_MTU5_TSTR_CSTU5_Pos             (2UL)    /*!< CSTU5 (Bit 2)                                         */
45768  #define R_MTU5_TSTR_CSTU5_Msk             (0x4UL)  /*!< CSTU5 (Bitfield-Mask: 0x01)                           */
45769 /* ======================================================  TCNTCMPCLR  ======================================================= */
45770  #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Pos    (0UL)    /*!< CMPCLR5W (Bit 0)                                      */
45771  #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Msk    (0x1UL)  /*!< CMPCLR5W (Bitfield-Mask: 0x01)                        */
45772  #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Pos    (1UL)    /*!< CMPCLR5V (Bit 1)                                      */
45773  #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Msk    (0x2UL)  /*!< CMPCLR5V (Bitfield-Mask: 0x01)                        */
45774  #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Pos    (2UL)    /*!< CMPCLR5U (Bit 2)                                      */
45775  #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Msk    (0x4UL)  /*!< CMPCLR5U (Bitfield-Mask: 0x01)                        */
45776 
45777 /* =========================================================================================================================== */
45778 /* ================                                           R_TFU                                           ================ */
45779 /* =========================================================================================================================== */
45780 
45781 /* ========================================================  TRGSTS  ========================================================= */
45782  #define R_TFU_TRGSTS_BSYF_Pos    (0UL)          /*!< BSYF (Bit 0)                                          */
45783  #define R_TFU_TRGSTS_BSYF_Msk    (0x1UL)        /*!< BSYF (Bitfield-Mask: 0x01)                            */
45784  #define R_TFU_TRGSTS_ERRF_Pos    (1UL)          /*!< ERRF (Bit 1)                                          */
45785  #define R_TFU_TRGSTS_ERRF_Msk    (0x2UL)        /*!< ERRF (Bitfield-Mask: 0x01)                            */
45786 /* =========================================================  SCDT0  ========================================================= */
45787  #define R_TFU_SCDT0_SCDT0_Pos    (0UL)          /*!< SCDT0 (Bit 0)                                         */
45788  #define R_TFU_SCDT0_SCDT0_Msk    (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff)                     */
45789 /* =========================================================  SCDT1  ========================================================= */
45790  #define R_TFU_SCDT1_SCDT1_Pos    (0UL)          /*!< SCDT1 (Bit 0)                                         */
45791  #define R_TFU_SCDT1_SCDT1_Msk    (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff)                     */
45792 /* =========================================================  ATDT0  ========================================================= */
45793  #define R_TFU_ATDT0_ATDT0_Pos    (0UL)          /*!< ATDT0 (Bit 0)                                         */
45794  #define R_TFU_ATDT0_ATDT0_Msk    (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff)                     */
45795 /* =========================================================  ATDT1  ========================================================= */
45796  #define R_TFU_ATDT1_ATDT1_Pos    (0UL)          /*!< ATDT1 (Bit 0)                                         */
45797  #define R_TFU_ATDT1_ATDT1_Msk    (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff)                     */
45798 
45799 /* =========================================================================================================================== */
45800 /* ================                                          R_POE3                                           ================ */
45801 /* =========================================================================================================================== */
45802 
45803 /* =========================================================  ICSR1  ========================================================= */
45804  #define R_POE3_ICSR1_POE0M_Pos            (0UL)      /*!< POE0M (Bit 0)                                         */
45805  #define R_POE3_ICSR1_POE0M_Msk            (0x3UL)    /*!< POE0M (Bitfield-Mask: 0x03)                           */
45806  #define R_POE3_ICSR1_PIE1_Pos             (8UL)      /*!< PIE1 (Bit 8)                                          */
45807  #define R_POE3_ICSR1_PIE1_Msk             (0x100UL)  /*!< PIE1 (Bitfield-Mask: 0x01)                            */
45808  #define R_POE3_ICSR1_POE0F_Pos            (12UL)     /*!< POE0F (Bit 12)                                        */
45809  #define R_POE3_ICSR1_POE0F_Msk            (0x1000UL) /*!< POE0F (Bitfield-Mask: 0x01)                           */
45810 /* =========================================================  OCSR1  ========================================================= */
45811  #define R_POE3_OCSR1_OIE1_Pos             (8UL)      /*!< OIE1 (Bit 8)                                          */
45812  #define R_POE3_OCSR1_OIE1_Msk             (0x100UL)  /*!< OIE1 (Bitfield-Mask: 0x01)                            */
45813  #define R_POE3_OCSR1_OCE1_Pos             (9UL)      /*!< OCE1 (Bit 9)                                          */
45814  #define R_POE3_OCSR1_OCE1_Msk             (0x200UL)  /*!< OCE1 (Bitfield-Mask: 0x01)                            */
45815  #define R_POE3_OCSR1_OSF1_Pos             (15UL)     /*!< OSF1 (Bit 15)                                         */
45816  #define R_POE3_OCSR1_OSF1_Msk             (0x8000UL) /*!< OSF1 (Bitfield-Mask: 0x01)                            */
45817 /* =========================================================  ICSR2  ========================================================= */
45818  #define R_POE3_ICSR2_POE4M_Pos            (0UL)      /*!< POE4M (Bit 0)                                         */
45819  #define R_POE3_ICSR2_POE4M_Msk            (0x3UL)    /*!< POE4M (Bitfield-Mask: 0x03)                           */
45820  #define R_POE3_ICSR2_PIE2_Pos             (8UL)      /*!< PIE2 (Bit 8)                                          */
45821  #define R_POE3_ICSR2_PIE2_Msk             (0x100UL)  /*!< PIE2 (Bitfield-Mask: 0x01)                            */
45822  #define R_POE3_ICSR2_POE4F_Pos            (12UL)     /*!< POE4F (Bit 12)                                        */
45823  #define R_POE3_ICSR2_POE4F_Msk            (0x1000UL) /*!< POE4F (Bitfield-Mask: 0x01)                           */
45824 /* =========================================================  OCSR2  ========================================================= */
45825  #define R_POE3_OCSR2_OIE2_Pos             (8UL)      /*!< OIE2 (Bit 8)                                          */
45826  #define R_POE3_OCSR2_OIE2_Msk             (0x100UL)  /*!< OIE2 (Bitfield-Mask: 0x01)                            */
45827  #define R_POE3_OCSR2_OCE2_Pos             (9UL)      /*!< OCE2 (Bit 9)                                          */
45828  #define R_POE3_OCSR2_OCE2_Msk             (0x200UL)  /*!< OCE2 (Bitfield-Mask: 0x01)                            */
45829  #define R_POE3_OCSR2_OSF2_Pos             (15UL)     /*!< OSF2 (Bit 15)                                         */
45830  #define R_POE3_OCSR2_OSF2_Msk             (0x8000UL) /*!< OSF2 (Bitfield-Mask: 0x01)                            */
45831 /* =========================================================  ICSR3  ========================================================= */
45832  #define R_POE3_ICSR3_POE8M_Pos            (0UL)      /*!< POE8M (Bit 0)                                         */
45833  #define R_POE3_ICSR3_POE8M_Msk            (0x3UL)    /*!< POE8M (Bitfield-Mask: 0x03)                           */
45834  #define R_POE3_ICSR3_PIE3_Pos             (8UL)      /*!< PIE3 (Bit 8)                                          */
45835  #define R_POE3_ICSR3_PIE3_Msk             (0x100UL)  /*!< PIE3 (Bitfield-Mask: 0x01)                            */
45836  #define R_POE3_ICSR3_POE8E_Pos            (9UL)      /*!< POE8E (Bit 9)                                         */
45837  #define R_POE3_ICSR3_POE8E_Msk            (0x200UL)  /*!< POE8E (Bitfield-Mask: 0x01)                           */
45838  #define R_POE3_ICSR3_POE8F_Pos            (12UL)     /*!< POE8F (Bit 12)                                        */
45839  #define R_POE3_ICSR3_POE8F_Msk            (0x1000UL) /*!< POE8F (Bitfield-Mask: 0x01)                           */
45840 /* =========================================================  SPOER  ========================================================= */
45841  #define R_POE3_SPOER_MTUCH34HIZ_Pos       (0UL)      /*!< MTUCH34HIZ (Bit 0)                                    */
45842  #define R_POE3_SPOER_MTUCH34HIZ_Msk       (0x1UL)    /*!< MTUCH34HIZ (Bitfield-Mask: 0x01)                      */
45843  #define R_POE3_SPOER_MTUCH67HIZ_Pos       (1UL)      /*!< MTUCH67HIZ (Bit 1)                                    */
45844  #define R_POE3_SPOER_MTUCH67HIZ_Msk       (0x2UL)    /*!< MTUCH67HIZ (Bitfield-Mask: 0x01)                      */
45845  #define R_POE3_SPOER_MTUCH0HIZ_Pos        (2UL)      /*!< MTUCH0HIZ (Bit 2)                                     */
45846  #define R_POE3_SPOER_MTUCH0HIZ_Msk        (0x4UL)    /*!< MTUCH0HIZ (Bitfield-Mask: 0x01)                       */
45847 /* ========================================================  POECR1  ========================================================= */
45848  #define R_POE3_POECR1_MTU0AZE_Pos         (0UL)      /*!< MTU0AZE (Bit 0)                                       */
45849  #define R_POE3_POECR1_MTU0AZE_Msk         (0x1UL)    /*!< MTU0AZE (Bitfield-Mask: 0x01)                         */
45850  #define R_POE3_POECR1_MTU0BZE_Pos         (1UL)      /*!< MTU0BZE (Bit 1)                                       */
45851  #define R_POE3_POECR1_MTU0BZE_Msk         (0x2UL)    /*!< MTU0BZE (Bitfield-Mask: 0x01)                         */
45852  #define R_POE3_POECR1_MTU0CZE_Pos         (2UL)      /*!< MTU0CZE (Bit 2)                                       */
45853  #define R_POE3_POECR1_MTU0CZE_Msk         (0x4UL)    /*!< MTU0CZE (Bitfield-Mask: 0x01)                         */
45854  #define R_POE3_POECR1_MTU0DZE_Pos         (3UL)      /*!< MTU0DZE (Bit 3)                                       */
45855  #define R_POE3_POECR1_MTU0DZE_Msk         (0x8UL)    /*!< MTU0DZE (Bitfield-Mask: 0x01)                         */
45856 /* ========================================================  POECR2  ========================================================= */
45857  #define R_POE3_POECR2_MTU7BDZE_Pos        (0UL)      /*!< MTU7BDZE (Bit 0)                                      */
45858  #define R_POE3_POECR2_MTU7BDZE_Msk        (0x1UL)    /*!< MTU7BDZE (Bitfield-Mask: 0x01)                        */
45859  #define R_POE3_POECR2_MTU7ACZE_Pos        (1UL)      /*!< MTU7ACZE (Bit 1)                                      */
45860  #define R_POE3_POECR2_MTU7ACZE_Msk        (0x2UL)    /*!< MTU7ACZE (Bitfield-Mask: 0x01)                        */
45861  #define R_POE3_POECR2_MTU6BDZE_Pos        (2UL)      /*!< MTU6BDZE (Bit 2)                                      */
45862  #define R_POE3_POECR2_MTU6BDZE_Msk        (0x4UL)    /*!< MTU6BDZE (Bitfield-Mask: 0x01)                        */
45863  #define R_POE3_POECR2_MTU4BDZE_Pos        (8UL)      /*!< MTU4BDZE (Bit 8)                                      */
45864  #define R_POE3_POECR2_MTU4BDZE_Msk        (0x100UL)  /*!< MTU4BDZE (Bitfield-Mask: 0x01)                        */
45865  #define R_POE3_POECR2_MTU4ACZE_Pos        (9UL)      /*!< MTU4ACZE (Bit 9)                                      */
45866  #define R_POE3_POECR2_MTU4ACZE_Msk        (0x200UL)  /*!< MTU4ACZE (Bitfield-Mask: 0x01)                        */
45867  #define R_POE3_POECR2_MTU3BDZE_Pos        (10UL)     /*!< MTU3BDZE (Bit 10)                                     */
45868  #define R_POE3_POECR2_MTU3BDZE_Msk        (0x400UL)  /*!< MTU3BDZE (Bitfield-Mask: 0x01)                        */
45869 /* ========================================================  POECR4  ========================================================= */
45870  #define R_POE3_POECR4_IC2ADDMT34ZE_Pos    (2UL)      /*!< IC2ADDMT34ZE (Bit 2)                                  */
45871  #define R_POE3_POECR4_IC2ADDMT34ZE_Msk    (0x4UL)    /*!< IC2ADDMT34ZE (Bitfield-Mask: 0x01)                    */
45872  #define R_POE3_POECR4_IC3ADDMT34ZE_Pos    (3UL)      /*!< IC3ADDMT34ZE (Bit 3)                                  */
45873  #define R_POE3_POECR4_IC3ADDMT34ZE_Msk    (0x8UL)    /*!< IC3ADDMT34ZE (Bitfield-Mask: 0x01)                    */
45874  #define R_POE3_POECR4_IC4ADDMT34ZE_Pos    (4UL)      /*!< IC4ADDMT34ZE (Bit 4)                                  */
45875  #define R_POE3_POECR4_IC4ADDMT34ZE_Msk    (0x10UL)   /*!< IC4ADDMT34ZE (Bitfield-Mask: 0x01)                    */
45876  #define R_POE3_POECR4_IC5ADDMT34ZE_Pos    (5UL)      /*!< IC5ADDMT34ZE (Bit 5)                                  */
45877  #define R_POE3_POECR4_IC5ADDMT34ZE_Msk    (0x20UL)   /*!< IC5ADDMT34ZE (Bitfield-Mask: 0x01)                    */
45878  #define R_POE3_POECR4_DE0ADDMT34ZE_Pos    (6UL)      /*!< DE0ADDMT34ZE (Bit 6)                                  */
45879  #define R_POE3_POECR4_DE0ADDMT34ZE_Msk    (0x40UL)   /*!< DE0ADDMT34ZE (Bitfield-Mask: 0x01)                    */
45880  #define R_POE3_POECR4_DE1ADDMT34ZE_Pos    (7UL)      /*!< DE1ADDMT34ZE (Bit 7)                                  */
45881  #define R_POE3_POECR4_DE1ADDMT34ZE_Msk    (0x80UL)   /*!< DE1ADDMT34ZE (Bitfield-Mask: 0x01)                    */
45882  #define R_POE3_POECR4_IC1ADDMT67ZE_Pos    (9UL)      /*!< IC1ADDMT67ZE (Bit 9)                                  */
45883  #define R_POE3_POECR4_IC1ADDMT67ZE_Msk    (0x200UL)  /*!< IC1ADDMT67ZE (Bitfield-Mask: 0x01)                    */
45884  #define R_POE3_POECR4_IC3ADDMT67ZE_Pos    (11UL)     /*!< IC3ADDMT67ZE (Bit 11)                                 */
45885  #define R_POE3_POECR4_IC3ADDMT67ZE_Msk    (0x800UL)  /*!< IC3ADDMT67ZE (Bitfield-Mask: 0x01)                    */
45886  #define R_POE3_POECR4_IC4ADDMT67ZE_Pos    (12UL)     /*!< IC4ADDMT67ZE (Bit 12)                                 */
45887  #define R_POE3_POECR4_IC4ADDMT67ZE_Msk    (0x1000UL) /*!< IC4ADDMT67ZE (Bitfield-Mask: 0x01)                    */
45888  #define R_POE3_POECR4_IC5ADDMT67ZE_Pos    (13UL)     /*!< IC5ADDMT67ZE (Bit 13)                                 */
45889  #define R_POE3_POECR4_IC5ADDMT67ZE_Msk    (0x2000UL) /*!< IC5ADDMT67ZE (Bitfield-Mask: 0x01)                    */
45890  #define R_POE3_POECR4_DE0ADDMT67ZE_Pos    (14UL)     /*!< DE0ADDMT67ZE (Bit 14)                                 */
45891  #define R_POE3_POECR4_DE0ADDMT67ZE_Msk    (0x4000UL) /*!< DE0ADDMT67ZE (Bitfield-Mask: 0x01)                    */
45892  #define R_POE3_POECR4_DE1ADDMT67ZE_Pos    (15UL)     /*!< DE1ADDMT67ZE (Bit 15)                                 */
45893  #define R_POE3_POECR4_DE1ADDMT67ZE_Msk    (0x8000UL) /*!< DE1ADDMT67ZE (Bitfield-Mask: 0x01)                    */
45894 /* ========================================================  POECR5  ========================================================= */
45895  #define R_POE3_POECR5_IC1ADDMT0ZE_Pos     (1UL)      /*!< IC1ADDMT0ZE (Bit 1)                                   */
45896  #define R_POE3_POECR5_IC1ADDMT0ZE_Msk     (0x2UL)    /*!< IC1ADDMT0ZE (Bitfield-Mask: 0x01)                     */
45897  #define R_POE3_POECR5_IC2ADDMT0ZE_Pos     (2UL)      /*!< IC2ADDMT0ZE (Bit 2)                                   */
45898  #define R_POE3_POECR5_IC2ADDMT0ZE_Msk     (0x4UL)    /*!< IC2ADDMT0ZE (Bitfield-Mask: 0x01)                     */
45899  #define R_POE3_POECR5_IC4ADDMT0ZE_Pos     (4UL)      /*!< IC4ADDMT0ZE (Bit 4)                                   */
45900  #define R_POE3_POECR5_IC4ADDMT0ZE_Msk     (0x10UL)   /*!< IC4ADDMT0ZE (Bitfield-Mask: 0x01)                     */
45901  #define R_POE3_POECR5_IC5ADDMT0ZE_Pos     (5UL)      /*!< IC5ADDMT0ZE (Bit 5)                                   */
45902  #define R_POE3_POECR5_IC5ADDMT0ZE_Msk     (0x20UL)   /*!< IC5ADDMT0ZE (Bitfield-Mask: 0x01)                     */
45903  #define R_POE3_POECR5_DE0ADDMT0ZE_Pos     (6UL)      /*!< DE0ADDMT0ZE (Bit 6)                                   */
45904  #define R_POE3_POECR5_DE0ADDMT0ZE_Msk     (0x40UL)   /*!< DE0ADDMT0ZE (Bitfield-Mask: 0x01)                     */
45905  #define R_POE3_POECR5_DE1ADDMT0ZE_Pos     (7UL)      /*!< DE1ADDMT0ZE (Bit 7)                                   */
45906  #define R_POE3_POECR5_DE1ADDMT0ZE_Msk     (0x80UL)   /*!< DE1ADDMT0ZE (Bitfield-Mask: 0x01)                     */
45907 /* =========================================================  ICSR4  ========================================================= */
45908  #define R_POE3_ICSR4_POE10M_Pos           (0UL)      /*!< POE10M (Bit 0)                                        */
45909  #define R_POE3_ICSR4_POE10M_Msk           (0x3UL)    /*!< POE10M (Bitfield-Mask: 0x03)                          */
45910  #define R_POE3_ICSR4_PIE4_Pos             (8UL)      /*!< PIE4 (Bit 8)                                          */
45911  #define R_POE3_ICSR4_PIE4_Msk             (0x100UL)  /*!< PIE4 (Bitfield-Mask: 0x01)                            */
45912  #define R_POE3_ICSR4_POE10E_Pos           (9UL)      /*!< POE10E (Bit 9)                                        */
45913  #define R_POE3_ICSR4_POE10E_Msk           (0x200UL)  /*!< POE10E (Bitfield-Mask: 0x01)                          */
45914  #define R_POE3_ICSR4_POE10F_Pos           (12UL)     /*!< POE10F (Bit 12)                                       */
45915  #define R_POE3_ICSR4_POE10F_Msk           (0x1000UL) /*!< POE10F (Bitfield-Mask: 0x01)                          */
45916 /* =========================================================  ICSR5  ========================================================= */
45917  #define R_POE3_ICSR5_POE11M_Pos           (0UL)      /*!< POE11M (Bit 0)                                        */
45918  #define R_POE3_ICSR5_POE11M_Msk           (0x3UL)    /*!< POE11M (Bitfield-Mask: 0x03)                          */
45919  #define R_POE3_ICSR5_PIE5_Pos             (8UL)      /*!< PIE5 (Bit 8)                                          */
45920  #define R_POE3_ICSR5_PIE5_Msk             (0x100UL)  /*!< PIE5 (Bitfield-Mask: 0x01)                            */
45921  #define R_POE3_ICSR5_POE11E_Pos           (9UL)      /*!< POE11E (Bit 9)                                        */
45922  #define R_POE3_ICSR5_POE11E_Msk           (0x200UL)  /*!< POE11E (Bitfield-Mask: 0x01)                          */
45923  #define R_POE3_ICSR5_POE11F_Pos           (12UL)     /*!< POE11F (Bit 12)                                       */
45924  #define R_POE3_ICSR5_POE11F_Msk           (0x1000UL) /*!< POE11F (Bitfield-Mask: 0x01)                          */
45925 /* =========================================================  ALR1  ========================================================== */
45926  #define R_POE3_ALR1_OLSG0A_Pos            (0UL)      /*!< OLSG0A (Bit 0)                                        */
45927  #define R_POE3_ALR1_OLSG0A_Msk            (0x1UL)    /*!< OLSG0A (Bitfield-Mask: 0x01)                          */
45928  #define R_POE3_ALR1_OLSG0B_Pos            (1UL)      /*!< OLSG0B (Bit 1)                                        */
45929  #define R_POE3_ALR1_OLSG0B_Msk            (0x2UL)    /*!< OLSG0B (Bitfield-Mask: 0x01)                          */
45930  #define R_POE3_ALR1_OLSG1A_Pos            (2UL)      /*!< OLSG1A (Bit 2)                                        */
45931  #define R_POE3_ALR1_OLSG1A_Msk            (0x4UL)    /*!< OLSG1A (Bitfield-Mask: 0x01)                          */
45932  #define R_POE3_ALR1_OLSG1B_Pos            (3UL)      /*!< OLSG1B (Bit 3)                                        */
45933  #define R_POE3_ALR1_OLSG1B_Msk            (0x8UL)    /*!< OLSG1B (Bitfield-Mask: 0x01)                          */
45934  #define R_POE3_ALR1_OLSG2A_Pos            (4UL)      /*!< OLSG2A (Bit 4)                                        */
45935  #define R_POE3_ALR1_OLSG2A_Msk            (0x10UL)   /*!< OLSG2A (Bitfield-Mask: 0x01)                          */
45936  #define R_POE3_ALR1_OLSG2B_Pos            (5UL)      /*!< OLSG2B (Bit 5)                                        */
45937  #define R_POE3_ALR1_OLSG2B_Msk            (0x20UL)   /*!< OLSG2B (Bitfield-Mask: 0x01)                          */
45938  #define R_POE3_ALR1_OLSEN_Pos             (7UL)      /*!< OLSEN (Bit 7)                                         */
45939  #define R_POE3_ALR1_OLSEN_Msk             (0x80UL)   /*!< OLSEN (Bitfield-Mask: 0x01)                           */
45940 /* =========================================================  ICSR6  ========================================================= */
45941  #define R_POE3_ICSR6_OSTSTE_Pos           (9UL)      /*!< OSTSTE (Bit 9)                                        */
45942  #define R_POE3_ICSR6_OSTSTE_Msk           (0x200UL)  /*!< OSTSTE (Bitfield-Mask: 0x01)                          */
45943  #define R_POE3_ICSR6_OSTSTF_Pos           (12UL)     /*!< OSTSTF (Bit 12)                                       */
45944  #define R_POE3_ICSR6_OSTSTF_Msk           (0x1000UL) /*!< OSTSTF (Bitfield-Mask: 0x01)                          */
45945 /* =========================================================  ICSR7  ========================================================= */
45946  #define R_POE3_ICSR7_DERR0IE_Pos          (6UL)      /*!< DERR0IE (Bit 6)                                       */
45947  #define R_POE3_ICSR7_DERR0IE_Msk          (0x40UL)   /*!< DERR0IE (Bitfield-Mask: 0x01)                         */
45948  #define R_POE3_ICSR7_DERR1IE_Pos          (7UL)      /*!< DERR1IE (Bit 7)                                       */
45949  #define R_POE3_ICSR7_DERR1IE_Msk          (0x80UL)   /*!< DERR1IE (Bitfield-Mask: 0x01)                         */
45950  #define R_POE3_ICSR7_DERR0ST_Pos          (13UL)     /*!< DERR0ST (Bit 13)                                      */
45951  #define R_POE3_ICSR7_DERR0ST_Msk          (0x2000UL) /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
45952  #define R_POE3_ICSR7_DERR1ST_Pos          (14UL)     /*!< DERR1ST (Bit 14)                                      */
45953  #define R_POE3_ICSR7_DERR1ST_Msk          (0x4000UL) /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
45954 /* ========================================================  M0SELR1  ======================================================== */
45955  #define R_POE3_M0SELR1_M0ASEL_Pos         (0UL)      /*!< M0ASEL (Bit 0)                                        */
45956  #define R_POE3_M0SELR1_M0ASEL_Msk         (0xfUL)    /*!< M0ASEL (Bitfield-Mask: 0x0f)                          */
45957  #define R_POE3_M0SELR1_M0BSEL_Pos         (4UL)      /*!< M0BSEL (Bit 4)                                        */
45958  #define R_POE3_M0SELR1_M0BSEL_Msk         (0xf0UL)   /*!< M0BSEL (Bitfield-Mask: 0x0f)                          */
45959 /* ========================================================  M0SELR2  ======================================================== */
45960  #define R_POE3_M0SELR2_M0CSEL_Pos         (0UL)      /*!< M0CSEL (Bit 0)                                        */
45961  #define R_POE3_M0SELR2_M0CSEL_Msk         (0xfUL)    /*!< M0CSEL (Bitfield-Mask: 0x0f)                          */
45962  #define R_POE3_M0SELR2_M0DSEL_Pos         (4UL)      /*!< M0DSEL (Bit 4)                                        */
45963  #define R_POE3_M0SELR2_M0DSEL_Msk         (0xf0UL)   /*!< M0DSEL (Bitfield-Mask: 0x0f)                          */
45964 /* ========================================================  M3SELR  ========================================================= */
45965  #define R_POE3_M3SELR_M3BSEL_Pos          (0UL)      /*!< M3BSEL (Bit 0)                                        */
45966  #define R_POE3_M3SELR_M3BSEL_Msk          (0xfUL)    /*!< M3BSEL (Bitfield-Mask: 0x0f)                          */
45967  #define R_POE3_M3SELR_M3DSEL_Pos          (4UL)      /*!< M3DSEL (Bit 4)                                        */
45968  #define R_POE3_M3SELR_M3DSEL_Msk          (0xf0UL)   /*!< M3DSEL (Bitfield-Mask: 0x0f)                          */
45969 /* ========================================================  M4SELR1  ======================================================== */
45970  #define R_POE3_M4SELR1_M4ASEL_Pos         (0UL)      /*!< M4ASEL (Bit 0)                                        */
45971  #define R_POE3_M4SELR1_M4ASEL_Msk         (0xfUL)    /*!< M4ASEL (Bitfield-Mask: 0x0f)                          */
45972  #define R_POE3_M4SELR1_M4CSEL_Pos         (4UL)      /*!< M4CSEL (Bit 4)                                        */
45973  #define R_POE3_M4SELR1_M4CSEL_Msk         (0xf0UL)   /*!< M4CSEL (Bitfield-Mask: 0x0f)                          */
45974 /* ========================================================  M4SELR2  ======================================================== */
45975  #define R_POE3_M4SELR2_M4BSEL_Pos         (0UL)      /*!< M4BSEL (Bit 0)                                        */
45976  #define R_POE3_M4SELR2_M4BSEL_Msk         (0xfUL)    /*!< M4BSEL (Bitfield-Mask: 0x0f)                          */
45977  #define R_POE3_M4SELR2_M4DSEL_Pos         (4UL)      /*!< M4DSEL (Bit 4)                                        */
45978  #define R_POE3_M4SELR2_M4DSEL_Msk         (0xf0UL)   /*!< M4DSEL (Bitfield-Mask: 0x0f)                          */
45979 /* ========================================================  M6SELR  ========================================================= */
45980  #define R_POE3_M6SELR_M6BSEL_Pos          (0UL)      /*!< M6BSEL (Bit 0)                                        */
45981  #define R_POE3_M6SELR_M6BSEL_Msk          (0xfUL)    /*!< M6BSEL (Bitfield-Mask: 0x0f)                          */
45982  #define R_POE3_M6SELR_M6DSEL_Pos          (4UL)      /*!< M6DSEL (Bit 4)                                        */
45983  #define R_POE3_M6SELR_M6DSEL_Msk          (0xf0UL)   /*!< M6DSEL (Bitfield-Mask: 0x0f)                          */
45984 /* ========================================================  M7SELR1  ======================================================== */
45985  #define R_POE3_M7SELR1_M7ASEL_Pos         (0UL)      /*!< M7ASEL (Bit 0)                                        */
45986  #define R_POE3_M7SELR1_M7ASEL_Msk         (0xfUL)    /*!< M7ASEL (Bitfield-Mask: 0x0f)                          */
45987  #define R_POE3_M7SELR1_M7CSEL_Pos         (4UL)      /*!< M7CSEL (Bit 4)                                        */
45988  #define R_POE3_M7SELR1_M7CSEL_Msk         (0xf0UL)   /*!< M7CSEL (Bitfield-Mask: 0x0f)                          */
45989 /* ========================================================  M7SELR2  ======================================================== */
45990  #define R_POE3_M7SELR2_M7BSEL_Pos         (0UL)      /*!< M7BSEL (Bit 0)                                        */
45991  #define R_POE3_M7SELR2_M7BSEL_Msk         (0xfUL)    /*!< M7BSEL (Bitfield-Mask: 0x0f)                          */
45992  #define R_POE3_M7SELR2_M7DSEL_Pos         (4UL)      /*!< M7DSEL (Bit 4)                                        */
45993  #define R_POE3_M7SELR2_M7DSEL_Msk         (0xf0UL)   /*!< M7DSEL (Bitfield-Mask: 0x0f)                          */
45994 
45995 /* =========================================================================================================================== */
45996 /* ================                                          R_POEG0                                          ================ */
45997 /* =========================================================================================================================== */
45998 
45999 /* ========================================================  POEG0GA  ======================================================== */
46000  #define R_POEG0_POEG0GA_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
46001  #define R_POEG0_POEG0GA_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
46002  #define R_POEG0_POEG0GA_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
46003  #define R_POEG0_POEG0GA_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
46004  #define R_POEG0_POEG0GA_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
46005  #define R_POEG0_POEG0GA_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
46006  #define R_POEG0_POEG0GA_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
46007  #define R_POEG0_POEG0GA_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
46008  #define R_POEG0_POEG0GA_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
46009  #define R_POEG0_POEG0GA_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
46010  #define R_POEG0_POEG0GA_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
46011  #define R_POEG0_POEG0GA_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
46012  #define R_POEG0_POEG0GA_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
46013  #define R_POEG0_POEG0GA_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
46014  #define R_POEG0_POEG0GA_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
46015  #define R_POEG0_POEG0GA_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
46016  #define R_POEG0_POEG0GA_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
46017  #define R_POEG0_POEG0GA_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
46018  #define R_POEG0_POEG0GA_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
46019  #define R_POEG0_POEG0GA_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
46020  #define R_POEG0_POEG0GA_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
46021  #define R_POEG0_POEG0GA_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
46022  #define R_POEG0_POEG0GA_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
46023  #define R_POEG0_POEG0GA_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
46024  #define R_POEG0_POEG0GA_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
46025  #define R_POEG0_POEG0GA_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
46026  #define R_POEG0_POEG0GA_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
46027  #define R_POEG0_POEG0GA_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
46028  #define R_POEG0_POEG0GA_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
46029  #define R_POEG0_POEG0GA_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
46030 /* ========================================================  POEG0GB  ======================================================== */
46031  #define R_POEG0_POEG0GB_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
46032  #define R_POEG0_POEG0GB_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
46033  #define R_POEG0_POEG0GB_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
46034  #define R_POEG0_POEG0GB_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
46035  #define R_POEG0_POEG0GB_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
46036  #define R_POEG0_POEG0GB_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
46037  #define R_POEG0_POEG0GB_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
46038  #define R_POEG0_POEG0GB_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
46039  #define R_POEG0_POEG0GB_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
46040  #define R_POEG0_POEG0GB_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
46041  #define R_POEG0_POEG0GB_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
46042  #define R_POEG0_POEG0GB_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
46043  #define R_POEG0_POEG0GB_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
46044  #define R_POEG0_POEG0GB_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
46045  #define R_POEG0_POEG0GB_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
46046  #define R_POEG0_POEG0GB_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
46047  #define R_POEG0_POEG0GB_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
46048  #define R_POEG0_POEG0GB_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
46049  #define R_POEG0_POEG0GB_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
46050  #define R_POEG0_POEG0GB_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
46051  #define R_POEG0_POEG0GB_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
46052  #define R_POEG0_POEG0GB_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
46053  #define R_POEG0_POEG0GB_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
46054  #define R_POEG0_POEG0GB_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
46055  #define R_POEG0_POEG0GB_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
46056  #define R_POEG0_POEG0GB_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
46057  #define R_POEG0_POEG0GB_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
46058  #define R_POEG0_POEG0GB_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
46059  #define R_POEG0_POEG0GB_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
46060  #define R_POEG0_POEG0GB_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
46061 /* ========================================================  POEG0GC  ======================================================== */
46062  #define R_POEG0_POEG0GC_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
46063  #define R_POEG0_POEG0GC_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
46064  #define R_POEG0_POEG0GC_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
46065  #define R_POEG0_POEG0GC_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
46066  #define R_POEG0_POEG0GC_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
46067  #define R_POEG0_POEG0GC_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
46068  #define R_POEG0_POEG0GC_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
46069  #define R_POEG0_POEG0GC_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
46070  #define R_POEG0_POEG0GC_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
46071  #define R_POEG0_POEG0GC_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
46072  #define R_POEG0_POEG0GC_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
46073  #define R_POEG0_POEG0GC_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
46074  #define R_POEG0_POEG0GC_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
46075  #define R_POEG0_POEG0GC_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
46076  #define R_POEG0_POEG0GC_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
46077  #define R_POEG0_POEG0GC_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
46078  #define R_POEG0_POEG0GC_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
46079  #define R_POEG0_POEG0GC_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
46080  #define R_POEG0_POEG0GC_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
46081  #define R_POEG0_POEG0GC_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
46082  #define R_POEG0_POEG0GC_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
46083  #define R_POEG0_POEG0GC_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
46084  #define R_POEG0_POEG0GC_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
46085  #define R_POEG0_POEG0GC_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
46086  #define R_POEG0_POEG0GC_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
46087  #define R_POEG0_POEG0GC_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
46088  #define R_POEG0_POEG0GC_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
46089  #define R_POEG0_POEG0GC_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
46090  #define R_POEG0_POEG0GC_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
46091  #define R_POEG0_POEG0GC_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
46092 /* ========================================================  POEG0GD  ======================================================== */
46093  #define R_POEG0_POEG0GD_PIDF_Pos       (0UL)          /*!< PIDF (Bit 0)                                          */
46094  #define R_POEG0_POEG0GD_PIDF_Msk       (0x1UL)        /*!< PIDF (Bitfield-Mask: 0x01)                            */
46095  #define R_POEG0_POEG0GD_IOCF_Pos       (1UL)          /*!< IOCF (Bit 1)                                          */
46096  #define R_POEG0_POEG0GD_IOCF_Msk       (0x2UL)        /*!< IOCF (Bitfield-Mask: 0x01)                            */
46097  #define R_POEG0_POEG0GD_OSTPF_Pos      (2UL)          /*!< OSTPF (Bit 2)                                         */
46098  #define R_POEG0_POEG0GD_OSTPF_Msk      (0x4UL)        /*!< OSTPF (Bitfield-Mask: 0x01)                           */
46099  #define R_POEG0_POEG0GD_SSF_Pos        (3UL)          /*!< SSF (Bit 3)                                           */
46100  #define R_POEG0_POEG0GD_SSF_Msk        (0x8UL)        /*!< SSF (Bitfield-Mask: 0x01)                             */
46101  #define R_POEG0_POEG0GD_PIDE_Pos       (4UL)          /*!< PIDE (Bit 4)                                          */
46102  #define R_POEG0_POEG0GD_PIDE_Msk       (0x10UL)       /*!< PIDE (Bitfield-Mask: 0x01)                            */
46103  #define R_POEG0_POEG0GD_IOCE_Pos       (5UL)          /*!< IOCE (Bit 5)                                          */
46104  #define R_POEG0_POEG0GD_IOCE_Msk       (0x20UL)       /*!< IOCE (Bitfield-Mask: 0x01)                            */
46105  #define R_POEG0_POEG0GD_OSTPE_Pos      (6UL)          /*!< OSTPE (Bit 6)                                         */
46106  #define R_POEG0_POEG0GD_OSTPE_Msk      (0x40UL)       /*!< OSTPE (Bitfield-Mask: 0x01)                           */
46107  #define R_POEG0_POEG0GD_ST_Pos         (16UL)         /*!< ST (Bit 16)                                           */
46108  #define R_POEG0_POEG0GD_ST_Msk         (0x10000UL)    /*!< ST (Bitfield-Mask: 0x01)                              */
46109  #define R_POEG0_POEG0GD_DERR0ST_Pos    (24UL)         /*!< DERR0ST (Bit 24)                                      */
46110  #define R_POEG0_POEG0GD_DERR0ST_Msk    (0x1000000UL)  /*!< DERR0ST (Bitfield-Mask: 0x01)                         */
46111  #define R_POEG0_POEG0GD_DERR1ST_Pos    (25UL)         /*!< DERR1ST (Bit 25)                                      */
46112  #define R_POEG0_POEG0GD_DERR1ST_Msk    (0x2000000UL)  /*!< DERR1ST (Bitfield-Mask: 0x01)                         */
46113  #define R_POEG0_POEG0GD_DERR0E_Pos     (26UL)         /*!< DERR0E (Bit 26)                                       */
46114  #define R_POEG0_POEG0GD_DERR0E_Msk     (0x4000000UL)  /*!< DERR0E (Bitfield-Mask: 0x01)                          */
46115  #define R_POEG0_POEG0GD_DERR1E_Pos     (27UL)         /*!< DERR1E (Bit 27)                                       */
46116  #define R_POEG0_POEG0GD_DERR1E_Msk     (0x8000000UL)  /*!< DERR1E (Bitfield-Mask: 0x01)                          */
46117  #define R_POEG0_POEG0GD_INV_Pos        (28UL)         /*!< INV (Bit 28)                                          */
46118  #define R_POEG0_POEG0GD_INV_Msk        (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01)                             */
46119  #define R_POEG0_POEG0GD_NFEN_Pos       (29UL)         /*!< NFEN (Bit 29)                                         */
46120  #define R_POEG0_POEG0GD_NFEN_Msk       (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01)                            */
46121  #define R_POEG0_POEG0GD_NFCS_Pos       (30UL)         /*!< NFCS (Bit 30)                                         */
46122  #define R_POEG0_POEG0GD_NFCS_Msk       (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03)                            */
46123 
46124 /* =========================================================================================================================== */
46125 /* ================                                         R_DSMIF0                                          ================ */
46126 /* =========================================================================================================================== */
46127 
46128 /* ========================================================  DSSEICR  ======================================================== */
46129  #define R_DSMIF0_DSSEICR_ISEL_Pos          (0UL)       /*!< ISEL (Bit 0)                                          */
46130  #define R_DSMIF0_DSSEICR_ISEL_Msk          (0x1UL)     /*!< ISEL (Bitfield-Mask: 0x01)                            */
46131  #define R_DSMIF0_DSSEICR_ISEH_Pos          (1UL)       /*!< ISEH (Bit 1)                                          */
46132  #define R_DSMIF0_DSSEICR_ISEH_Msk          (0x2UL)     /*!< ISEH (Bitfield-Mask: 0x01)                            */
46133 /* ========================================================  DSSECSR  ======================================================== */
46134  #define R_DSMIF0_DSSECSR_SEDM_Pos          (0UL)       /*!< SEDM (Bit 0)                                          */
46135  #define R_DSMIF0_DSSECSR_SEDM_Msk          (0x7UL)     /*!< SEDM (Bitfield-Mask: 0x07)                            */
46136 /* ========================================================  DSSELTR  ======================================================== */
46137  #define R_DSMIF0_DSSELTR_SCMPTBL_Pos       (0UL)       /*!< SCMPTBL (Bit 0)                                       */
46138  #define R_DSMIF0_DSSELTR_SCMPTBL_Msk       (0x3ffffUL) /*!< SCMPTBL (Bitfield-Mask: 0x3ffff)                      */
46139 /* ========================================================  DSSEHTR  ======================================================== */
46140  #define R_DSMIF0_DSSEHTR_SCMPTBH_Pos       (0UL)       /*!< SCMPTBH (Bit 0)                                       */
46141  #define R_DSMIF0_DSSEHTR_SCMPTBH_Msk       (0x3ffffUL) /*!< SCMPTBH (Bitfield-Mask: 0x3ffff)                      */
46142 /* ========================================================  DSSECR  ========================================================= */
46143  #define R_DSMIF0_DSSECR_SEEL_Pos           (0UL)       /*!< SEEL (Bit 0)                                          */
46144  #define R_DSMIF0_DSSECR_SEEL_Msk           (0x1UL)     /*!< SEEL (Bitfield-Mask: 0x01)                            */
46145  #define R_DSMIF0_DSSECR_SEEH_Pos           (1UL)       /*!< SEEH (Bit 1)                                          */
46146  #define R_DSMIF0_DSSECR_SEEH_Msk           (0x2UL)     /*!< SEEH (Bitfield-Mask: 0x01)                            */
46147 /* ========================================================  DSSECDR  ======================================================== */
46148  #define R_DSMIF0_DSSECDR_SECDR_Pos         (0UL)       /*!< SECDR (Bit 0)                                         */
46149  #define R_DSMIF0_DSSECDR_SECDR_Msk         (0xffffUL)  /*!< SECDR (Bitfield-Mask: 0xffff)                         */
46150 /* =======================================================  DSCSTRTR  ======================================================== */
46151  #define R_DSMIF0_DSCSTRTR_STRTRG0_Pos      (0UL)       /*!< STRTRG0 (Bit 0)                                       */
46152  #define R_DSMIF0_DSCSTRTR_STRTRG0_Msk      (0x1UL)     /*!< STRTRG0 (Bitfield-Mask: 0x01)                         */
46153  #define R_DSMIF0_DSCSTRTR_STRTRG1_Pos      (1UL)       /*!< STRTRG1 (Bit 1)                                       */
46154  #define R_DSMIF0_DSCSTRTR_STRTRG1_Msk      (0x2UL)     /*!< STRTRG1 (Bitfield-Mask: 0x01)                         */
46155  #define R_DSMIF0_DSCSTRTR_STRTRG2_Pos      (2UL)       /*!< STRTRG2 (Bit 2)                                       */
46156  #define R_DSMIF0_DSCSTRTR_STRTRG2_Msk      (0x4UL)     /*!< STRTRG2 (Bitfield-Mask: 0x01)                         */
46157 /* =======================================================  DSCSTPTR  ======================================================== */
46158  #define R_DSMIF0_DSCSTPTR_STPTRG0_Pos      (0UL)       /*!< STPTRG0 (Bit 0)                                       */
46159  #define R_DSMIF0_DSCSTPTR_STPTRG0_Msk      (0x1UL)     /*!< STPTRG0 (Bitfield-Mask: 0x01)                         */
46160  #define R_DSMIF0_DSCSTPTR_STPTRG1_Pos      (1UL)       /*!< STPTRG1 (Bit 1)                                       */
46161  #define R_DSMIF0_DSCSTPTR_STPTRG1_Msk      (0x2UL)     /*!< STPTRG1 (Bitfield-Mask: 0x01)                         */
46162  #define R_DSMIF0_DSCSTPTR_STPTRG2_Pos      (2UL)       /*!< STPTRG2 (Bit 2)                                       */
46163  #define R_DSMIF0_DSCSTPTR_STPTRG2_Msk      (0x4UL)     /*!< STPTRG2 (Bitfield-Mask: 0x01)                         */
46164 /* ========================================================  DSCESR  ========================================================= */
46165  #define R_DSMIF0_DSCESR_OCFL0_Pos          (0UL)       /*!< OCFL0 (Bit 0)                                         */
46166  #define R_DSMIF0_DSCESR_OCFL0_Msk          (0x1UL)     /*!< OCFL0 (Bitfield-Mask: 0x01)                           */
46167  #define R_DSMIF0_DSCESR_OCFL1_Pos          (1UL)       /*!< OCFL1 (Bit 1)                                         */
46168  #define R_DSMIF0_DSCESR_OCFL1_Msk          (0x2UL)     /*!< OCFL1 (Bitfield-Mask: 0x01)                           */
46169  #define R_DSMIF0_DSCESR_OCFL2_Pos          (2UL)       /*!< OCFL2 (Bit 2)                                         */
46170  #define R_DSMIF0_DSCESR_OCFL2_Msk          (0x4UL)     /*!< OCFL2 (Bitfield-Mask: 0x01)                           */
46171  #define R_DSMIF0_DSCESR_OCFH0_Pos          (4UL)       /*!< OCFH0 (Bit 4)                                         */
46172  #define R_DSMIF0_DSCESR_OCFH0_Msk          (0x10UL)    /*!< OCFH0 (Bitfield-Mask: 0x01)                           */
46173  #define R_DSMIF0_DSCESR_OCFH1_Pos          (5UL)       /*!< OCFH1 (Bit 5)                                         */
46174  #define R_DSMIF0_DSCESR_OCFH1_Msk          (0x20UL)    /*!< OCFH1 (Bitfield-Mask: 0x01)                           */
46175  #define R_DSMIF0_DSCESR_OCFH2_Pos          (6UL)       /*!< OCFH2 (Bit 6)                                         */
46176  #define R_DSMIF0_DSCESR_OCFH2_Msk          (0x40UL)    /*!< OCFH2 (Bitfield-Mask: 0x01)                           */
46177  #define R_DSMIF0_DSCESR_SCF0_Pos           (8UL)       /*!< SCF0 (Bit 8)                                          */
46178  #define R_DSMIF0_DSCESR_SCF0_Msk           (0x100UL)   /*!< SCF0 (Bitfield-Mask: 0x01)                            */
46179  #define R_DSMIF0_DSCESR_SCF1_Pos           (9UL)       /*!< SCF1 (Bit 9)                                          */
46180  #define R_DSMIF0_DSCESR_SCF1_Msk           (0x200UL)   /*!< SCF1 (Bitfield-Mask: 0x01)                            */
46181  #define R_DSMIF0_DSCESR_SCF2_Pos           (10UL)      /*!< SCF2 (Bit 10)                                         */
46182  #define R_DSMIF0_DSCESR_SCF2_Msk           (0x400UL)   /*!< SCF2 (Bitfield-Mask: 0x01)                            */
46183  #define R_DSMIF0_DSCESR_SUMERRL_Pos        (16UL)      /*!< SUMERRL (Bit 16)                                      */
46184  #define R_DSMIF0_DSCESR_SUMERRL_Msk        (0x10000UL) /*!< SUMERRL (Bitfield-Mask: 0x01)                         */
46185  #define R_DSMIF0_DSCESR_SUMERRH_Pos        (17UL)      /*!< SUMERRH (Bit 17)                                      */
46186  #define R_DSMIF0_DSCESR_SUMERRH_Msk        (0x20000UL) /*!< SUMERRH (Bitfield-Mask: 0x01)                         */
46187 /* =========================================================  DSCSR  ========================================================= */
46188  #define R_DSMIF0_DSCSR_DUF0_Pos            (0UL)       /*!< DUF0 (Bit 0)                                          */
46189  #define R_DSMIF0_DSCSR_DUF0_Msk            (0x1UL)     /*!< DUF0 (Bitfield-Mask: 0x01)                            */
46190  #define R_DSMIF0_DSCSR_DUF1_Pos            (1UL)       /*!< DUF1 (Bit 1)                                          */
46191  #define R_DSMIF0_DSCSR_DUF1_Msk            (0x2UL)     /*!< DUF1 (Bitfield-Mask: 0x01)                            */
46192  #define R_DSMIF0_DSCSR_DUF2_Pos            (2UL)       /*!< DUF2 (Bit 2)                                          */
46193  #define R_DSMIF0_DSCSR_DUF2_Msk            (0x4UL)     /*!< DUF2 (Bitfield-Mask: 0x01)                            */
46194 /* ========================================================  DSCSSR  ========================================================= */
46195  #define R_DSMIF0_DSCSSR_CHSTATE0_Pos       (0UL)       /*!< CHSTATE0 (Bit 0)                                      */
46196  #define R_DSMIF0_DSCSSR_CHSTATE0_Msk       (0x1UL)     /*!< CHSTATE0 (Bitfield-Mask: 0x01)                        */
46197  #define R_DSMIF0_DSCSSR_CHSTATE1_Pos       (4UL)       /*!< CHSTATE1 (Bit 4)                                      */
46198  #define R_DSMIF0_DSCSSR_CHSTATE1_Msk       (0x10UL)    /*!< CHSTATE1 (Bitfield-Mask: 0x01)                        */
46199  #define R_DSMIF0_DSCSSR_CHSTATE2_Pos       (8UL)       /*!< CHSTATE2 (Bit 8)                                      */
46200  #define R_DSMIF0_DSCSSR_CHSTATE2_Msk       (0x100UL)   /*!< CHSTATE2 (Bitfield-Mask: 0x01)                        */
46201 /* ========================================================  DSCESCR  ======================================================== */
46202  #define R_DSMIF0_DSCESCR_CLROCFL0_Pos      (0UL)       /*!< CLROCFL0 (Bit 0)                                      */
46203  #define R_DSMIF0_DSCESCR_CLROCFL0_Msk      (0x1UL)     /*!< CLROCFL0 (Bitfield-Mask: 0x01)                        */
46204  #define R_DSMIF0_DSCESCR_CLROCFL1_Pos      (1UL)       /*!< CLROCFL1 (Bit 1)                                      */
46205  #define R_DSMIF0_DSCESCR_CLROCFL1_Msk      (0x2UL)     /*!< CLROCFL1 (Bitfield-Mask: 0x01)                        */
46206  #define R_DSMIF0_DSCESCR_CLROCFL2_Pos      (2UL)       /*!< CLROCFL2 (Bit 2)                                      */
46207  #define R_DSMIF0_DSCESCR_CLROCFL2_Msk      (0x4UL)     /*!< CLROCFL2 (Bitfield-Mask: 0x01)                        */
46208  #define R_DSMIF0_DSCESCR_CLROCFH0_Pos      (4UL)       /*!< CLROCFH0 (Bit 4)                                      */
46209  #define R_DSMIF0_DSCESCR_CLROCFH0_Msk      (0x10UL)    /*!< CLROCFH0 (Bitfield-Mask: 0x01)                        */
46210  #define R_DSMIF0_DSCESCR_CLROCFH1_Pos      (5UL)       /*!< CLROCFH1 (Bit 5)                                      */
46211  #define R_DSMIF0_DSCESCR_CLROCFH1_Msk      (0x20UL)    /*!< CLROCFH1 (Bitfield-Mask: 0x01)                        */
46212  #define R_DSMIF0_DSCESCR_CLROCFH2_Pos      (6UL)       /*!< CLROCFH2 (Bit 6)                                      */
46213  #define R_DSMIF0_DSCESCR_CLROCFH2_Msk      (0x40UL)    /*!< CLROCFH2 (Bitfield-Mask: 0x01)                        */
46214  #define R_DSMIF0_DSCESCR_CLRSCF0_Pos       (8UL)       /*!< CLRSCF0 (Bit 8)                                       */
46215  #define R_DSMIF0_DSCESCR_CLRSCF0_Msk       (0x100UL)   /*!< CLRSCF0 (Bitfield-Mask: 0x01)                         */
46216  #define R_DSMIF0_DSCESCR_CLRSCF1_Pos       (9UL)       /*!< CLRSCF1 (Bit 9)                                       */
46217  #define R_DSMIF0_DSCESCR_CLRSCF1_Msk       (0x200UL)   /*!< CLRSCF1 (Bitfield-Mask: 0x01)                         */
46218  #define R_DSMIF0_DSCESCR_CLRSCF2_Pos       (10UL)      /*!< CLRSCF2 (Bit 10)                                      */
46219  #define R_DSMIF0_DSCESCR_CLRSCF2_Msk       (0x400UL)   /*!< CLRSCF2 (Bitfield-Mask: 0x01)                         */
46220  #define R_DSMIF0_DSCESCR_CLRSUMERRL_Pos    (16UL)      /*!< CLRSUMERRL (Bit 16)                                   */
46221  #define R_DSMIF0_DSCESCR_CLRSUMERRL_Msk    (0x10000UL) /*!< CLRSUMERRL (Bitfield-Mask: 0x01)                      */
46222  #define R_DSMIF0_DSCESCR_CLRSUMERRH_Pos    (17UL)      /*!< CLRSUMERRH (Bit 17)                                   */
46223  #define R_DSMIF0_DSCESCR_CLRSUMERRH_Msk    (0x20000UL) /*!< CLRSUMERRH (Bitfield-Mask: 0x01)                      */
46224 /* ========================================================  DSCSCR  ========================================================= */
46225  #define R_DSMIF0_DSCSCR_CLRDUF0_Pos        (0UL)       /*!< CLRDUF0 (Bit 0)                                       */
46226  #define R_DSMIF0_DSCSCR_CLRDUF0_Msk        (0x1UL)     /*!< CLRDUF0 (Bitfield-Mask: 0x01)                         */
46227  #define R_DSMIF0_DSCSCR_CLRDUF1_Pos        (1UL)       /*!< CLRDUF1 (Bit 1)                                       */
46228  #define R_DSMIF0_DSCSCR_CLRDUF1_Msk        (0x2UL)     /*!< CLRDUF1 (Bitfield-Mask: 0x01)                         */
46229  #define R_DSMIF0_DSCSCR_CLRDUF2_Pos        (2UL)       /*!< CLRDUF2 (Bit 2)                                       */
46230  #define R_DSMIF0_DSCSCR_CLRDUF2_Msk        (0x4UL)     /*!< CLRDUF2 (Bitfield-Mask: 0x01)                         */
46231 
46232 /* =========================================================================================================================== */
46233 /* ================                                           R_GSC                                           ================ */
46234 /* =========================================================================================================================== */
46235 
46236 /* =========================================================  CNTCR  ========================================================= */
46237  #define R_GSC_CNTCR_EN_Pos              (0UL)          /*!< EN (Bit 0)                                            */
46238  #define R_GSC_CNTCR_EN_Msk              (0x1UL)        /*!< EN (Bitfield-Mask: 0x01)                              */
46239  #define R_GSC_CNTCR_HDBG_Pos            (1UL)          /*!< HDBG (Bit 1)                                          */
46240  #define R_GSC_CNTCR_HDBG_Msk            (0x2UL)        /*!< HDBG (Bitfield-Mask: 0x01)                            */
46241 /* =========================================================  CNTSR  ========================================================= */
46242  #define R_GSC_CNTSR_DBGH_Pos            (1UL)          /*!< DBGH (Bit 1)                                          */
46243  #define R_GSC_CNTSR_DBGH_Msk            (0x2UL)        /*!< DBGH (Bitfield-Mask: 0x01)                            */
46244 /* ========================================================  CNTCVL  ========================================================= */
46245  #define R_GSC_CNTCVL_CNTCVL_L_32_Pos    (0UL)          /*!< CNTCVL_L_32 (Bit 0)                                   */
46246  #define R_GSC_CNTCVL_CNTCVL_L_32_Msk    (0xffffffffUL) /*!< CNTCVL_L_32 (Bitfield-Mask: 0xffffffff)               */
46247 /* ========================================================  CNTCVU  ========================================================= */
46248  #define R_GSC_CNTCVU_CNTCVU_U_32_Pos    (0UL)          /*!< CNTCVU_U_32 (Bit 0)                                   */
46249  #define R_GSC_CNTCVU_CNTCVU_U_32_Msk    (0xffffffffUL) /*!< CNTCVU_U_32 (Bitfield-Mask: 0xffffffff)               */
46250 /* ========================================================  CNTFID0  ======================================================== */
46251  #define R_GSC_CNTFID0_FREQ_Pos          (0UL)          /*!< FREQ (Bit 0)                                          */
46252  #define R_GSC_CNTFID0_FREQ_Msk          (0xffffffffUL) /*!< FREQ (Bitfield-Mask: 0xffffffff)                      */
46253 
46254 /** @} */ /* End of group PosMask_peripherals */
46255 
46256  #ifdef __cplusplus
46257 }
46258  #endif
46259 
46260 #endif                                 /* R9A07G084_H */
46261 
46262 /** @} */ /* End of group R9A07G084 */
46263 
46264 /** @} */ /* End of group Renesas Electronics Corporation */
46265