1 /* 2 * Copyright (c) 2016 Piotr Mienkowski 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 /** @file 7 * @brief Atmel SAM MCU family Ethernet MAC (GMAC) driver. 8 */ 9 10 #ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SAM_GMAC_PRIV_H_ 11 #define ZEPHYR_DRIVERS_ETHERNET_ETH_SAM_GMAC_PRIV_H_ 12 13 #include <zephyr/types.h> 14 15 #define ATMEL_OUI_B0 0x00 16 #define ATMEL_OUI_B1 0x04 17 #define ATMEL_OUI_B2 0x25 18 19 /* This option enables support to push multiple packets to the DMA engine. 20 * This currently doesn't work given the current version of net_pkt or 21 * net_buf does not allowed access from multiple threads. This option is 22 * therefore currently disabled. 23 */ 24 #define GMAC_MULTIPLE_TX_PACKETS 0 25 26 #define GMAC_MTU NET_ETH_MTU 27 #define GMAC_FRAME_SIZE_MAX (GMAC_MTU + 18) 28 29 /** Cache alignment */ 30 #define GMAC_DCACHE_ALIGNMENT 32 31 /** Memory alignment of the RX/TX Buffer Descriptor List */ 32 #define GMAC_DESC_ALIGNMENT 4 33 /** Total number of queues supported by GMAC hardware module */ 34 #define GMAC_QUEUE_NUM DT_INST_PROP(0, num_queues) 35 #define GMAC_PRIORITY_QUEUE_NUM (GMAC_QUEUE_NUM - 1) 36 #if (GMAC_PRIORITY_QUEUE_NUM >= 1) 37 BUILD_ASSERT(ARRAY_SIZE(GMAC->GMAC_TBQBAPQ) + 1 == GMAC_QUEUE_NUM, 38 "GMAC_QUEUE_NUM doesn't match soc header"); 39 #endif 40 /** Number of priority queues used */ 41 #define GMAC_ACTIVE_QUEUE_NUM (CONFIG_ETH_SAM_GMAC_QUEUES) 42 #define GMAC_ACTIVE_PRIORITY_QUEUE_NUM (GMAC_ACTIVE_QUEUE_NUM - 1) 43 44 /** RX descriptors count for main queue */ 45 #define MAIN_QUEUE_RX_DESC_COUNT (CONFIG_ETH_SAM_GMAC_BUF_RX_COUNT + 1) 46 /** TX descriptors count for main queue */ 47 #define MAIN_QUEUE_TX_DESC_COUNT (CONFIG_NET_BUF_TX_COUNT + 1) 48 49 /** RX/TX descriptors count for priority queues */ 50 #if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 1 51 #define PRIORITY_QUEUE1_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT 52 #define PRIORITY_QUEUE1_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT 53 #else 54 #define PRIORITY_QUEUE1_RX_DESC_COUNT 1 55 #define PRIORITY_QUEUE1_TX_DESC_COUNT 1 56 #endif 57 58 #if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2 59 #define PRIORITY_QUEUE2_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT 60 #define PRIORITY_QUEUE2_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT 61 #else 62 #define PRIORITY_QUEUE2_RX_DESC_COUNT 1 63 #define PRIORITY_QUEUE2_TX_DESC_COUNT 1 64 #endif 65 66 #if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 3 67 #define PRIORITY_QUEUE3_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT 68 #define PRIORITY_QUEUE3_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT 69 #else 70 #define PRIORITY_QUEUE3_RX_DESC_COUNT 1 71 #define PRIORITY_QUEUE3_TX_DESC_COUNT 1 72 #endif 73 74 #if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 4 75 #define PRIORITY_QUEUE4_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT 76 #define PRIORITY_QUEUE4_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT 77 #else 78 #define PRIORITY_QUEUE4_RX_DESC_COUNT 1 79 #define PRIORITY_QUEUE4_TX_DESC_COUNT 1 80 #endif 81 82 #if GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 5 83 #define PRIORITY_QUEUE5_RX_DESC_COUNT MAIN_QUEUE_RX_DESC_COUNT 84 #define PRIORITY_QUEUE5_TX_DESC_COUNT MAIN_QUEUE_TX_DESC_COUNT 85 #else 86 #define PRIORITY_QUEUE5_RX_DESC_COUNT 1 87 #define PRIORITY_QUEUE5_TX_DESC_COUNT 1 88 #endif 89 90 /* 91 * Receive buffer descriptor bit field definitions 92 */ 93 94 /** Buffer ownership, needs to be 0 for the GMAC to write data to the buffer */ 95 #define GMAC_RXW0_OWNERSHIP (0x1u << 0) 96 /** Last descriptor in the receive buffer descriptor list */ 97 #define GMAC_RXW0_WRAP (0x1u << 1) 98 /** Address of beginning of buffer */ 99 #define GMAC_RXW0_ADDR (0x3FFFFFFFu << 2) 100 101 /** Receive frame length including FCS */ 102 #define GMAC_RXW1_LEN (0x1FFFu << 0) 103 /** FCS status */ 104 #define GMAC_RXW1_FCS_STATUS (0x1u << 13) 105 /** Start of frame */ 106 #define GMAC_RXW1_SOF (0x1u << 14) 107 /** End of frame */ 108 #define GMAC_RXW1_EOF (0x1u << 15) 109 /** Canonical Format Indicator */ 110 #define GMAC_RXW1_CFI (0x1u << 16) 111 /** VLAN priority (if VLAN detected) */ 112 #define GMAC_RXW1_VLANPRIORITY (0x7u << 17) 113 /** Priority tag detected */ 114 #define GMAC_RXW1_PRIORITYDETECTED (0x1u << 20) 115 /** VLAN tag detected */ 116 #define GMAC_RXW1_VLANDETECTED (0x1u << 21) 117 /** Type ID match */ 118 #define GMAC_RXW1_TYPEIDMATCH (0x3u << 22) 119 /** Type ID register match found */ 120 #define GMAC_RXW1_TYPEIDFOUND (0x1u << 24) 121 /** Specific Address Register match */ 122 #define GMAC_RXW1_ADDRMATCH (0x3u << 25) 123 /** Specific Address Register match found */ 124 #define GMAC_RXW1_ADDRFOUND (0x1u << 27) 125 /** Unicast hash match */ 126 #define GMAC_RXW1_UNIHASHMATCH (0x1u << 29) 127 /** Multicast hash match */ 128 #define GMAC_RXW1_MULTIHASHMATCH (0x1u << 30) 129 /** Global all ones broadcast address detected */ 130 #define GMAC_RXW1_BROADCASTDETECTED (0x1u << 31) 131 132 /* 133 * Transmit buffer descriptor bit field definitions 134 */ 135 136 /** Transmit buffer length */ 137 #define GMAC_TXW1_LEN (0x3FFFu << 0) 138 /** Last buffer in the current frame */ 139 #define GMAC_TXW1_LASTBUFFER (0x1u << 15) 140 /** No CRC */ 141 #define GMAC_TXW1_NOCRC (0x1u << 16) 142 /** Transmit IP/TCP/UDP checksum generation offload errors */ 143 #define GMAC_TXW1_CHKSUMERR (0x7u << 20) 144 /** Late collision, transmit error detected */ 145 #define GMAC_TXW1_LATECOLERR (0x1u << 26) 146 /** Transmit frame corruption due to AHB error */ 147 #define GMAC_TXW1_TRANSERR (0x1u << 27) 148 /** Retry limit exceeded, transmit error detected */ 149 #define GMAC_TXW1_RETRYEXC (0x1u << 29) 150 /** Last descriptor in Transmit Descriptor list */ 151 #define GMAC_TXW1_WRAP (0x1u << 30) 152 /** Buffer used, must be 0 for the GMAC to read data to the transmit buffer */ 153 #define GMAC_TXW1_USED (0x1u << 31) 154 155 /* 156 * Interrupt Status/Enable/Disable/Mask register bit field definitions 157 */ 158 159 #define GMAC_INT_RX_ERR_BITS \ 160 (GMAC_IER_RXUBR | GMAC_IER_ROVR) 161 #define GMAC_INT_TX_ERR_BITS \ 162 (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC) 163 #define GMAC_INT_EN_FLAGS \ 164 (GMAC_IER_RCOMP | GMAC_INT_RX_ERR_BITS | \ 165 GMAC_IER_TCOMP | GMAC_INT_TX_ERR_BITS | GMAC_IER_HRESP) 166 167 #define GMAC_INTPQ_RX_ERR_BITS \ 168 (GMAC_IERPQ_RXUBR | GMAC_IERPQ_ROVR) 169 #define GMAC_INTPQ_TX_ERR_BITS \ 170 (GMAC_IERPQ_RLEX | GMAC_IERPQ_TFC) 171 #define GMAC_INTPQ_EN_FLAGS \ 172 (GMAC_IERPQ_RCOMP | GMAC_INTPQ_RX_ERR_BITS | \ 173 GMAC_IERPQ_TCOMP | GMAC_INTPQ_TX_ERR_BITS | GMAC_IERPQ_HRESP) 174 175 /** GMAC Priority Queues DMA flags */ 176 #if GMAC_PRIORITY_QUEUE_NUM >= 1 177 /* 4 kB Receiver Packet Buffer Memory Size */ 178 /* 4 kB Transmitter Packet Buffer Memory Size */ 179 /* Transmitter Checksum Generation Offload Enable */ 180 #define GMAC_DMA_QUEUE_FLAGS \ 181 (GMAC_DCFGR_RXBMS_FULL | GMAC_DCFGR_TXPBMS | \ 182 GMAC_DCFGR_TXCOEN) 183 #else 184 #define GMAC_DMA_QUEUE_FLAGS (0) 185 #endif 186 187 /** List of GMAC queues */ 188 enum queue_idx { 189 GMAC_QUE_0, /** Main queue */ 190 GMAC_QUE_1, /** Priority queue 1 */ 191 GMAC_QUE_2, /** Priority queue 2 */ 192 GMAC_QUE_3, /** Priority queue 3 */ 193 GMAC_QUE_4, /** Priority queue 4 */ 194 GMAC_QUE_5, /** Priority queue 5 */ 195 }; 196 197 #if (DT_INST_PROP(0, max_frame_size) == 1518) 198 /* Maximum frame length is 1518 bytes */ 199 #define GMAC_MAX_FRAME_SIZE 0 200 #elif (DT_INST_PROP(0, max_frame_size) == 1536) 201 /* Enable Max Frame Size of 1536 */ 202 #define GMAC_MAX_FRAME_SIZE GMAC_NCFGR_MAXFS 203 #elif (DT_INST_PROP(0, max_frame_size) == 10240) 204 /* Jumbo Frame Enable */ 205 #define GMAC_MAX_FRAME_SIZE GMAC_NCFGR_JFRAME 206 #else 207 #error "GMAC_MAX_FRAME_SIZE is invalid, fix it at device tree." 208 #endif 209 210 /** Minimal ring buffer implementation */ 211 struct ring_buf { 212 uint32_t *buf; 213 uint16_t len; 214 uint16_t head; 215 uint16_t tail; 216 }; 217 218 /** Receive/transmit buffer descriptor */ 219 struct gmac_desc { 220 uint32_t w0; 221 uint32_t w1; 222 }; 223 224 /** Ring list of receive/transmit buffer descriptors */ 225 struct gmac_desc_list { 226 struct gmac_desc *buf; 227 uint16_t len; 228 uint16_t head; 229 uint16_t tail; 230 }; 231 232 /** GMAC Queue data */ 233 struct gmac_queue { 234 struct gmac_desc_list rx_desc_list; 235 struct gmac_desc_list tx_desc_list; 236 #if GMAC_MULTIPLE_TX_PACKETS == 1 237 struct k_sem tx_desc_sem; 238 #else 239 struct k_sem tx_sem; 240 #endif 241 242 struct net_buf **rx_frag_list; 243 244 #if GMAC_MULTIPLE_TX_PACKETS == 1 245 struct ring_buf tx_frag_list; 246 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC) 247 struct ring_buf tx_frames; 248 #endif 249 #endif 250 251 /** Number of RX frames dropped by the driver */ 252 volatile uint32_t err_rx_frames_dropped; 253 /** Number of times receive queue was flushed */ 254 volatile uint32_t err_rx_flushed_count; 255 /** Number of times transmit queue was flushed */ 256 volatile uint32_t err_tx_flushed_count; 257 258 enum queue_idx que_idx; 259 }; 260 261 /* Device constant configuration parameters */ 262 struct eth_sam_dev_cfg { 263 Gmac *regs; 264 #ifdef CONFIG_SOC_FAMILY_SAM 265 const struct atmel_sam_pmc_config clock_cfg; 266 #endif 267 const struct pinctrl_dev_config *pcfg; 268 void (*config_func)(void); 269 const struct device *phy_dev; 270 }; 271 272 /* Device run time data */ 273 struct eth_sam_dev_data { 274 struct net_if *iface; 275 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC) 276 const struct device *ptp_clock; 277 #endif 278 uint8_t mac_addr[6]; 279 bool link_up; 280 struct gmac_queue queue_list[GMAC_QUEUE_NUM]; 281 }; 282 283 #endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_SAM_GMAC_PRIV_H_ */ 284
