1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : M33_EPPB 10 // Version : 1 11 // Bus type : apb 12 // Description : Cortex-M33 EPPB vendor register block for RP2350 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_M33_EPPB_H 15 #define _HARDWARE_REGS_M33_EPPB_H 16 // ============================================================================= 17 // Register : M33_EPPB_NMI_MASK0 18 // Description : NMI mask for IRQs 0 through 31. This register is core-local, 19 // and is reset by a processor warm reset. 20 #define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000) 21 #define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff) 22 #define M33_EPPB_NMI_MASK0_RESET _u(0x00000000) 23 #define M33_EPPB_NMI_MASK0_MSB _u(31) 24 #define M33_EPPB_NMI_MASK0_LSB _u(0) 25 #define M33_EPPB_NMI_MASK0_ACCESS "RW" 26 // ============================================================================= 27 // Register : M33_EPPB_NMI_MASK1 28 // Description : NMI mask for IRQs 0 though 51. This register is core-local, and 29 // is reset by a processor warm reset. 30 #define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004) 31 #define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff) 32 #define M33_EPPB_NMI_MASK1_RESET _u(0x00000000) 33 #define M33_EPPB_NMI_MASK1_MSB _u(19) 34 #define M33_EPPB_NMI_MASK1_LSB _u(0) 35 #define M33_EPPB_NMI_MASK1_ACCESS "RW" 36 // ============================================================================= 37 // Register : M33_EPPB_SLEEPCTRL 38 // Description : Nonstandard sleep control register 39 #define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008) 40 #define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007) 41 #define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002) 42 // ----------------------------------------------------------------------------- 43 // Field : M33_EPPB_SLEEPCTRL_WICENACK 44 // Description : Status signal from the processor's interrupt controller. 45 // Changes to WICENREQ are eventually reflected in WICENACK. 46 #define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0) 47 #define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004) 48 #define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2) 49 #define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2) 50 #define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO" 51 // ----------------------------------------------------------------------------- 52 // Field : M33_EPPB_SLEEPCTRL_WICENREQ 53 // Description : Request that the next processor deep sleep is a WIC sleep. 54 // After setting this bit, before sleeping, poll WICENACK to 55 // ensure the processor interrupt controller has acknowledged the 56 // change. 57 #define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1) 58 #define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002) 59 #define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1) 60 #define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1) 61 #define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW" 62 // ----------------------------------------------------------------------------- 63 // Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP 64 // Description : By default, any processor sleep will deassert the system-level 65 // clock request. Reenabling the clocks incurs 5 cycles of 66 // additional latency on wakeup. 67 // 68 // Setting LIGHT_SLEEP to 1 keeps the clock request asserted 69 // during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster 70 // wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not 71 // affected, and will always deassert the system-level clock 72 // request. 73 #define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0) 74 #define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001) 75 #define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0) 76 #define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0) 77 #define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW" 78 // ============================================================================= 79 #endif // _HARDWARE_REGS_M33_EPPB_H 80 81
