1 /** 2 * 3 * \file 4 * 5 * \brief This module contains NMC1500 ASIC specific internal APIs. 6 * 7 * Copyright (c) 2016-2017 Atmel Corporation. All rights reserved. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions are met: 15 * 16 * 1. Redistributions of source code must retain the above copyright notice, 17 * this list of conditions and the following disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above copyright notice, 20 * this list of conditions and the following disclaimer in the documentation 21 * and/or other materials provided with the distribution. 22 * 23 * 3. The name of Atmel may not be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 29 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * \asf_license_stop 39 * 40 */ 41 #ifndef _NMASIC_H_ 42 #define _NMASIC_H_ 43 44 #include "common/include/nm_common.h" 45 46 #define NMI_PERIPH_REG_BASE 0x1000 47 #define NMI_CHIPID (NMI_PERIPH_REG_BASE) 48 #define rNMI_GP_REG_0 (0x149c) 49 #define rNMI_GP_REG_1 (0x14A0) 50 #define rNMI_GP_REG_2 (0xc0008) 51 #define rNMI_GLB_RESET (0x1400) 52 #define rNMI_BOOT_RESET_MUX (0x1118) 53 #define NMI_STATE_REG (0x108c) 54 #define BOOTROM_REG (0xc000c) 55 #define NMI_REV_REG (0x207ac) /*Also, Used to load ATE firmware from SPI Flash and to ensure that it is running too*/ 56 #define NMI_REV_REG_ATE (0x1048) /*Revision info register in case of ATE FW*/ 57 #define M2M_WAIT_FOR_HOST_REG (0x207bc) 58 #define M2M_FINISH_INIT_STATE 0x02532636UL 59 #define M2M_FINISH_BOOT_ROM 0x10add09eUL 60 #define M2M_START_FIRMWARE 0xef522f61UL 61 #define M2M_START_PS_FIRMWARE 0x94992610UL 62 63 #define M2M_ATE_FW_START_VALUE (0x3C1CD57D) /*Also, Change this value in boot_firmware if it will be changed here*/ 64 #define M2M_ATE_FW_IS_UP_VALUE (0xD75DC1C3) /*Also, Change this value in ATE (Burst) firmware if it will be changed here*/ 65 66 #define REV_2B0 (0x2B0) 67 #define REV_B0 (0x2B0) 68 #define REV_3A0 (0x3A0) 69 #define GET_CHIPID() nmi_get_chipid() 70 #define ISNMC1000(id) ((((id) & 0xfffff000) == 0x100000) ? 1 : 0) 71 #define ISNMC1500(id) ((((id) & 0xfffff000) == 0x150000) ? 1 : 0) 72 #define ISNMC3000(id) ((((id) & 0xfff00000) == 0x300000) ? 1 : 0) 73 #define REV(id) (((id) & 0x00000fff )) 74 #define EFUSED_MAC(value) (value & 0xffff0000) 75 76 #define rHAVE_SDIO_IRQ_GPIO_BIT (NBIT0) 77 #define rHAVE_USE_PMU_BIT (NBIT1) 78 #define rHAVE_SLEEP_CLK_SRC_RTC_BIT (NBIT2) 79 #define rHAVE_SLEEP_CLK_SRC_XO_BIT (NBIT3) 80 #define rHAVE_EXT_PA_INV_TX_RX (NBIT4) 81 #define rHAVE_LEGACY_RF_SETTINGS (NBIT5) 82 #define rHAVE_LOGS_DISABLED_BIT (NBIT6) 83 #define rHAVE_ETHERNET_MODE_BIT (NBIT7) 84 #define rHAVE_RESERVED1_BIT (NBIT8) 85 86 typedef struct{ 87 uint32 u32Mac_efuse_mib; 88 uint32 u32Firmware_Ota_rev; 89 }tstrGpRegs; 90 91 #ifdef __cplusplus 92 extern "C" { 93 #endif 94 95 /* 96 * @fn cpu_halt 97 * @brief 98 */ 99 sint8 cpu_halt(void); 100 /* 101 * @fn chip_sleep 102 * @brief 103 */ 104 sint8 chip_sleep(void); 105 /* 106 * @fn chip_wake 107 * @brief 108 */ 109 sint8 chip_wake(void); 110 /* 111 * @fn chip_idle 112 * @brief 113 */ 114 void chip_idle(void); 115 /* 116 * @fn enable_interrupts 117 * @brief 118 */ 119 sint8 enable_interrupts(void); 120 /* 121 * @fn cpu_start 122 * @brief 123 */ 124 sint8 cpu_start(void); 125 /* 126 * @fn nmi_get_chipid 127 * @brief 128 */ 129 uint32 nmi_get_chipid(void); 130 /* 131 * @fn nmi_get_rfrevid 132 * @brief 133 */ 134 uint32 nmi_get_rfrevid(void); 135 /* 136 * @fn restore_pmu_settings_after_global_reset 137 * @brief 138 */ 139 void restore_pmu_settings_after_global_reset(void); 140 /* 141 * @fn nmi_update_pll 142 * @brief 143 */ 144 void nmi_update_pll(void); 145 /* 146 * @fn nmi_set_sys_clk_src_to_xo 147 * @brief 148 */ 149 void nmi_set_sys_clk_src_to_xo(void); 150 /* 151 * @fn chip_reset 152 * @brief 153 */ 154 sint8 chip_reset(void); 155 /* 156 * @fn wait_for_bootrom 157 * @brief 158 */ 159 sint8 wait_for_bootrom(uint8); 160 /* 161 * @fn wait_for_firmware_start 162 * @brief 163 */ 164 sint8 wait_for_firmware_start(uint8); 165 /* 166 * @fn chip_deinit 167 * @brief 168 */ 169 sint8 chip_deinit(void); 170 /* 171 * @fn chip_reset_and_cpu_halt 172 * @brief 173 */ 174 sint8 chip_reset_and_cpu_halt(void); 175 /* 176 * @fn set_gpio_dir 177 * @brief 178 */ 179 sint8 set_gpio_dir(uint8 gpio, uint8 dir); 180 /* 181 * @fn set_gpio_val 182 * @brief 183 */ 184 sint8 set_gpio_val(uint8 gpio, uint8 val); 185 /* 186 * @fn get_gpio_val 187 * @brief 188 */ 189 sint8 get_gpio_val(uint8 gpio, uint8* val); 190 /* 191 * @fn pullup_ctrl 192 * @brief 193 */ 194 sint8 pullup_ctrl(uint32 pinmask, uint8 enable); 195 /* 196 * @fn nmi_get_otp_mac_address 197 * @brief 198 */ 199 sint8 nmi_get_otp_mac_address(uint8 *pu8MacAddr, uint8 * pu8IsValid); 200 /* 201 * @fn nmi_get_mac_address 202 * @brief 203 */ 204 sint8 nmi_get_mac_address(uint8 *pu8MacAddr); 205 /* 206 * @fn chip_apply_conf 207 * @brief 208 */ 209 sint8 chip_apply_conf(uint32 u32conf); 210 211 #ifdef __cplusplus 212 } 213 #endif 214 215 #endif /*_NMASIC_H_*/ 216
