1 /** 2 ****************************************************************************** 3 * @file stm32n6xx_hal_eth_ex.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL Extended module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2023 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32N6xx_HAL_ETH_EX_H 21 #define STM32N6xx_HAL_ETH_EX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(ETH1) 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32n6xx_hal_def.h" 31 32 /** @addtogroup STM32N6xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup ETHEx 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup ETHEx_Exported_Types ETHEx Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief ETH RX VLAN structure definition 47 */ 48 typedef struct 49 { 50 FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */ 51 52 uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive 53 This parameter can be a value of 54 @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */ 55 56 FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */ 57 58 FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */ 59 60 FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */ 61 62 FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */ 63 64 uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive 65 This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */ 66 67 uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check 68 This parameter can be a value of @ref ETHEx_VLAN_Type_Check */ 69 70 FunctionalState VLANTagInverseMatch; /*!< Enable or disable VLAN Tag Inverse Match */ 71 72 FunctionalState BitVLANcomparison; /*!< Enable 12-Bit VLAN Tag Comparison */ 73 74 uint32_t VLANcomparison; /*!< 12-bit or 16-bit VLAN comparison */ 75 76 FunctionalState VLANTagEnable; /*!< VLAN Tag Enable */ 77 78 uint32_t VLANTagID; /*!< VLAN Tag ID */ 79 80 uint32_t RxDMAChannelNumber; /*!< Rx DMA Channel Number */ 81 82 FunctionalState DMAChannelNumberEnable; /*!< Enable Rx DMA Channel Number */ 83 } ETH_RxVLANConfigTypeDef; 84 /** 85 * 86 */ 87 88 /** 89 * @brief ETH MAC TMRQR INDIRECT REG enum definition 90 */ 91 typedef enum 92 { 93 ETH_IND_REG_0 = 0x00000000U, /*!< Indirect register 0 */ 94 ETH_IND_REG_1 = 0x00000001U, /*!< Indirect register 1 */ 95 ETH_IND_REG_2 = 0x00000002U, /*!< Indirect register 2 */ 96 ETH_IND_REG_3 = 0x00000003U, /*!< Indirect register 3 */ 97 ETH_IND_REG_4 = 0x00000004U, /*!< Indirect register 4 */ 98 ETH_IND_REG_5 = 0x00000005U, /*!< Indirect register 5 */ 99 ETH_IND_REG_6 = 0x00000006U, /*!< Indirect register 6 */ 100 ETH_IND_REG_7 = 0x00000007U /*!< Indirect register 7 */ 101 } ETH_IDRegTypeDef; 102 /** 103 * 104 */ 105 /** 106 * @brief ETH MAC_MTL Mapping Configuration Structure definition 107 */ 108 typedef struct 109 { 110 uint32_t VLANTagFilterFailPacketsQueue; /*!< Specifies the Rx queue to which the tagged packets fail DA/SA/VLANtag filter must be routed to */ 111 112 FunctionalState VLANTagFilterFailPacketsQueuingEnable; /*!< Enables routing the tagged packets fail DA/SA/VLANtag filter to Rx queue */ 113 114 uint32_t MulticastAddFilterFailPacketsQueue; /*!< Specifies the Rx queue to which the Multicast packets fail the DA/SA filter are routed to */ 115 116 FunctionalState MulticastAddrFilterFailPacketsQueuingEnable; /*!< Enables routing Multicast Packets fail DA/SA filter to Rx Queue programmed in MFFQ */ 117 118 uint32_t UnicastAddrFilterFailPacketsQueue; /*!< Specifies the Rx queue to which the Unicast packets fail the DA/SA filter are routed to */ 119 120 FunctionalState UnicastAddrFilterFailPacketsQueuingEnable; /*!< Enables routing Unicast Packets fail DA/SA filter to Rx Queue programmed in UFFQ */ 121 122 FunctionalState TypeFieldBasedRxQueuingEnable; /*!< Enables Type field based Rx queuing */ 123 124 uint32_t OverridingMCBCQueuePrioritySelect; /*!< Select the Overriding MC-BC queue priority */ 125 126 uint32_t FramePreemptionResidueQueue; /*!< Specifies the Rx queue to which the residual preemption frames must be forwarded */ 127 128 uint32_t TaggedPTPoEPacketsQueuingControl; /*!< Specifies the routing of the VLAN tagged PTPoE packets */ 129 130 FunctionalState TaggedAVControlPacketsQueuingEnable; /*!< Enable MAC routes the received Tagged AV control packets to Rx queue specified by AVCPQ field */ 131 132 FunctionalState MulticastBroadcastQueueEnable; /*!< Specifies that Multicast or Broadcast packets routing to the Rx queue is enabled */ 133 134 uint32_t MulticastBroadcastQueue; /*!< Specifies the Rx queue onto which Multicast or Broadcast packets are routed */ 135 136 uint32_t UntaggedPacketQueue; /*!< Specifies the Rx queue to which Untagged Packets are to be routed */ 137 138 uint32_t PTPPacketsQueue; /*!< Specifies the Rx queue on which the PTP packets sent over the Ethernet payload */ 139 140 uint32_t AVUntaggedControlPacketsQueue; /*!< Specifies the Receive queue to receive AV untagged control packets */ 141 142 uint32_t PrioritiesSelectedRxQ0; /*!< Specifies the Priorities Selected in the Receive Queue 0 @ref ETHEx_Rx_VLAN_PRIO */ 143 144 uint32_t PrioritiesSelectedRxQ1; /*!< Specifies the Priorities Selected in the Receive Queue 1 @ref ETHEx_Rx_VLAN_PRIO */ 145 146 147 } ETH_MACMTLMappingTypeDef; 148 /** 149 * 150 */ 151 152 /** 153 * @brief ETH MTL Queue Configuration Structure definition 154 */ 155 typedef struct 156 { 157 uint32_t QueueOpMode; /*!< Queue Disabled, Enabled or AV Mode. */ 158 159 uint32_t AVAlgorithm; /*!< Queue Disabled, Enabled or AV Mode. */ 160 161 uint32_t TxQueueSize; /*!< Specifies the Tx Queue Size */ 162 163 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode.*/ 164 } MTL_TxQueueInstance_t; 165 /** 166 * 167 */ 168 169 /** 170 * @brief ETH MTL Queue Configuration Structure definition 171 */ 172 typedef struct 173 { 174 uint32_t QueueOpMode; /*!< Queue Disabled, Enabled or AV Mode. */ 175 176 uint32_t RxQueueSize; /*!< Specifies the Rx Queue Size */ 177 178 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets.*/ 179 180 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */ 181 182 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/ 183 184 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode */ 185 186 uint32_t MappedToDMACh; /*!< Specifies the DMA Channel to which MTL Q is mapped */ 187 188 } MTL_RxQueueInstance_t; 189 /** 190 * 191 */ 192 193 /** 194 * @brief ETH MTL Configuration Structure definition 195 */ 196 typedef struct 197 { 198 uint32_t TxSchedulingAlgorithm; /*!< Specifies the algorithm for Tx scheduling */ 199 200 uint32_t ReceiveArbitrationAlgorithm; /*!< Specifies the arbitration algorithm for the Rx side */ 201 202 MTL_TxQueueInstance_t TxQ[ETH_MTL_TX_Q_CNT]; /*!< MTL Tx Queue Configuration */ 203 204 MTL_RxQueueInstance_t RxQ[ETH_MTL_RX_Q_CNT]; /*!< MTL Rx Queue Configuration */ 205 206 FunctionalState TransmitStatus; /*!< Enables or disables forwarding Tx Packet Status to the application. */ 207 208 } ETH_MTLConfigTypeDef; 209 /** 210 * 211 */ 212 213 /** 214 * @brief ETH Packet TYPE Queue Configuration structure definition 215 */ 216 typedef struct 217 { 218 ETH_IDRegTypeDef Address; /*!< Sets Address Offset for indirect accesses to ETH_MAC_TMRQR */ 219 220 uint32_t Type; /*!< Indicates the type value of packet that needs to be compared with the received packet. */ 221 222 uint32_t Queue; /*!< Indicates the receive queue number to which the packet needs to be forwarded */ 223 224 uint32_t Preemption; /*!< Preemption or Express Packet 225 This parameter can be a value of @ref ETHEx_Preemption_Packet */ 226 } ETH_PacketTypeQueueConfigTypeDef; 227 /** 228 * 229 */ 230 231 /** 232 * @brief ETH TX VLAN structure definition 233 */ 234 typedef struct 235 { 236 FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */ 237 238 FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */ 239 240 uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets 241 This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */ 242 } ETH_TxVLANConfigTypeDef; 243 /** 244 * 245 */ 246 247 /** 248 * @brief ETH L3 filter structure definition 249 */ 250 typedef struct 251 { 252 uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6 253 This parameter can be a value of @ref ETHEx_L3_Protocol */ 254 255 uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match 256 This parameter can be a value of @ref ETHEx_L3_Source_Match */ 257 258 uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match 259 This parameter can be a value of @ref ETHEx_L3_Destination_Match */ 260 261 uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match 262 This parameter can be a value from 0 to 31 */ 263 264 uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match 265 This parameter can be a value from 0 to 31 */ 266 267 uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used 268 This parameter can be a value from 0x0 to 0xFFFFFFFF */ 269 270 uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used 271 This parameter can be a value from 0 to 0xFFFFFFFF */ 272 273 uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used 274 This parameter must be a table of 4 words (4* 32 bits) */ 275 } ETH_L3FilterConfigTypeDef; 276 /** 277 * 278 */ 279 280 /** 281 * @brief ETH L4 filter structure definition 282 */ 283 typedef struct 284 { 285 uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP 286 This parameter can be a value of @ref ETHEx_L4_Protocol */ 287 288 uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match 289 This parameter can be a value of @ref ETHEx_L4_Source_Match */ 290 291 uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match 292 This parameter can be a value of @ref ETHEx_L4_Destination_Match */ 293 294 uint32_t SourcePort; /*!< Sets the L4 filter source port 295 This parameter must be a value from 0x0 to 0xFFFF */ 296 297 uint32_t DestinationPort; /*!< Sets the L4 filter destination port 298 This parameter must be a value from 0x0 to 0xFFFF */ 299 } ETH_L4FilterConfigTypeDef; 300 /** 301 * 302 */ 303 304 #ifdef HAL_ETH_USE_CBS 305 /** 306 * @brief ETH CBS Algorithm components 307 */ 308 typedef struct 309 { 310 uint32_t QueueIdx; /*!< Specifies the queue Index to be configured */ 311 312 uint32_t SlotCount; /*!< Specifies number of slots */ 313 314 uint32_t CreditControl; /*!< Specifies Credit Control mode */ 315 316 uint32_t IdleSlope; /*!< idleSlopeCredit value required for the CBS algorithm */ 317 318 uint32_t SendSlope; /*!< sendSlope value required for the CBS algorithm */ 319 320 uint32_t HiCredit; /*!< hiCredit value required for the CBS algorithm */ 321 322 uint32_t LoCredit; /*!< loCredit value required for the CBS algorithm */ 323 324 } ETH_CBSConfigTypeDef; 325 /** 326 * 327 */ 328 329 #endif /* HAL_ETH_USE_CBS */ 330 331 #ifdef HAL_ETH_USE_TAS 332 /** 333 * @brief ETH TAS Operation components 334 */ 335 typedef struct 336 { 337 uint32_t Gate; /*! Gate status Open or Closed */ 338 339 uint32_t Interval; /*! Time interval valid gate control */ 340 341 } ETH_TASOperationConfigTypeDef; 342 343 /** 344 * @brief ETH TAS Operation components 345 */ 346 typedef struct 347 { 348 uint64_t BaseTimeRegister; /*! Base Time 32 bits seconds 32 bits nanoseconds */ 349 350 uint64_t CycleTimeRegister; /*! Cycle Time 32 bits seconds 32 bits nanoseconds */ 351 352 uint32_t TimeExtensionRegister; /*! Time Extension 32 bits seconds 32 bits nanoseconds */ 353 354 uint32_t ListLengthRegister; /*! GCL list Length */ 355 356 ETH_TASOperationConfigTypeDef *opList; /*! Pointer to GCL list size */ 357 358 } ETH_GCLConfigTypeDef; 359 360 /** 361 * @brief ETH Enhancements to Scheduled Traffic components 362 */ 363 typedef struct 364 { 365 uint32_t SwitchToSWOL; /*! Switch to S/W owned list */ 366 367 uint32_t PTPTimeOffset; /*! PTP Time Offset Value */ 368 369 uint32_t CurrentTimeOffset; /*! Current Time Offset Value */ 370 371 uint32_t TimeIntervalLeftShift; /*! Time Interval Left Shift Amount */ 372 373 uint32_t LoopCountSchedulingError; /*! Loop Count to report Scheduling Error */ 374 375 FunctionalState DropFramesCausingError; /*! Drop Frames causing Scheduling Error */ 376 377 FunctionalState NotDropFramesDuringFrameSizeError; /*! Drop Frames causing Scheduling Error */ 378 379 uint32_t OverheadBytesValue; /*! Overhead Bytes Value */ 380 381 ETH_GCLConfigTypeDef GCLRegisters; /*! Pointer to GCL Registers */ 382 383 } ETH_ESTConfigTypeDef; 384 /** 385 * 386 */ 387 #endif /* HAL_ETH_USE_TAS */ 388 389 #ifdef HAL_ETH_USE_FPE 390 /** 391 * @brief ETH Frame Preemption components 392 */ 393 typedef struct 394 { 395 uint32_t AdditionalFragmentSize; /*! Additional Fragment Size */ 396 397 uint32_t PreemptionClassification; /*! Preemption Classification 398 This parameter can be a combination of @ref ETHEx_FPE_Preemption_Classification*/ 399 400 uint32_t HoldReleaseStatus; /*! Hold/Release Status */ 401 402 FunctionalState SendVerifymPacket; /*! Send Verify mPacket */ 403 404 FunctionalState SendRespondmPacket; /*! Send Respond mPacket */ 405 406 uint32_t HoldAdvance; /*! The maximum time in nanoseconds that can elapse between issuing a 407 HOLD to the MAC and the MAC ceasing to transmit any preemptible frame */ 408 uint32_t ReleaseAdvance; /*! The maximum time in nanoseconds that can elapse between issuing a 409 RELEASE to the MAC and the MAC being ready to resume transmission of preemptible frames */ 410 } ETH_FPEConfigTypeDef; 411 /** 412 * 413 */ 414 #endif /* HAL_ETH_USE_FPE */ 415 /** 416 * @} 417 */ 418 419 /* Exported constants --------------------------------------------------------*/ 420 /** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants 421 * @{ 422 */ 423 424 /** @defgroup ETHEx_LPI_Event ETHEx LPI Event 425 * @{ 426 */ 427 #define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN 428 #define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX 429 #define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN 430 #define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX 431 /** 432 * @} 433 */ 434 435 /** @defgroup ETHEx_L3_Filter ETHEx L3 Filter 436 * @{ 437 */ 438 #define ETH_L3_FILTER_0 0x00000000U 439 #define ETH_L3_FILTER_1 0x0000000CU 440 /** 441 * @} 442 */ 443 444 /** @defgroup ETHEx_L4_Filter ETHEx L4 Filter 445 * @{ 446 */ 447 #define ETH_L4_FILTER_0 0x00000000U 448 #define ETH_L4_FILTER_1 0x0000000CU 449 /** 450 * @} 451 */ 452 453 /** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol 454 * @{ 455 */ 456 #define ETH_L3_IPV6_MATCH ETH_MACL3L4C0R_L3PEN0 457 #define ETH_L3_IPV4_MATCH 0x00000000U 458 /** 459 * @} 460 */ 461 462 /** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match 463 * @{ 464 */ 465 #define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4C0R_L3SAM0 466 #define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4C0R_L3SAM0 | ETH_MACL3L4C0R_L3SAIM0) 467 #define ETH_L3_SRC_ADDR_MATCH_DISABLE 0x00000000U 468 /** 469 * @} 470 */ 471 472 /** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match 473 * @{ 474 */ 475 #define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4C0R_L3DAM0 476 #define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4C0R_L3DAM0 | ETH_MACL3L4C0R_L3DAIM0) 477 #define ETH_L3_DEST_ADDR_MATCH_DISABLE 0x00000000U 478 /** 479 * @} 480 */ 481 482 /** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol 483 * @{ 484 */ 485 #define ETH_L4_UDP_MATCH ETH_MACL3L4C0R_L4PEN0 486 #define ETH_L4_TCP_MATCH 0x00000000U 487 /** 488 * @} 489 */ 490 491 /** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match 492 * @{ 493 */ 494 #define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4C0R_L4SPM0 495 #define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4C0R_L4SPM0 |ETH_MACL3L4C0R_L4SPIM0) 496 #define ETH_L4_SRC_PORT_MATCH_DISABLE 0x00000000U 497 /** 498 * @} 499 */ 500 501 /** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match 502 * @{ 503 */ 504 #define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4C0R_L4DPM0 505 #define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4C0R_L4DPM0 | ETH_MACL3L4C0R_L4DPIM0) 506 #define ETH_L4_DEST_PORT_MATCH_DISABLE 0x00000000U 507 /** 508 * @} 509 */ 510 511 /** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping 512 * @{ 513 */ 514 #define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTCR_EIVLS_DONOTSTRIP 515 #define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTCR_EIVLS_STRIPIFPASS 516 #define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTCR_EIVLS_STRIPIFFAILS 517 #define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTCR_EIVLS_ALWAYSSTRIP 518 /** 519 * @} 520 */ 521 522 /** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping 523 * @{ 524 */ 525 #define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTCR_EVLS_DONOTSTRIP 526 #define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTCR_EVLS_STRIPIFPASS 527 #define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTCR_EVLS_STRIPIFFAILS 528 #define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTCR_EVLS_ALWAYSSTRIP 529 /** 530 * @} 531 */ 532 533 /** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check 534 * @{ 535 */ 536 #define ETH_VLANTYPECHECK_DISABLE ETH_MACVTCR_DOVLTC 537 #define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTCR_ERSVLM | ETH_MACVTCR_ESVL) 538 #define ETH_VLANTYPECHECK_CVLAN 0x00000000U 539 /** 540 * @} 541 */ 542 543 /** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control 544 * @{ 545 */ 546 #define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG) 547 #define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE) 548 #define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT) 549 #define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE) 550 /** 551 * @} 552 */ 553 554 /** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag 555 * @{ 556 */ 557 #define ETH_INNER_TX_VLANTAG 0x00000001U 558 #define ETH_OUTER_TX_VLANTAG 0x00000000U 559 /** 560 * @} 561 */ 562 563 /** @defgroup ETHEx_Rx_VLAN_PRIO ETHEx Rx VLAN PRIO 564 * @{ 565 */ 566 #define ETH_RX_QUEUE_PRIO_0 0x00000001U /*!< Rx VLAN User Tag Priority 0 */ 567 #define ETH_RX_QUEUE_PRIO_1 0x00000002U /*!< Rx VLAN User Tag Priority 1 */ 568 #define ETH_RX_QUEUE_PRIO_2 0x00000004U /*!< Rx VLAN User Tag Priority 2 */ 569 #define ETH_RX_QUEUE_PRIO_3 0x00000008U /*!< Rx VLAN User Tag Priority 3 */ 570 #define ETH_RX_QUEUE_PRIO_4 0x00000010U /*!< Rx VLAN User Tag Priority 4 */ 571 #define ETH_RX_QUEUE_PRIO_5 0x00000020U /*!< Rx VLAN User Tag Priority 5 */ 572 #define ETH_RX_QUEUE_PRIO_6 0x00000040U /*!< Rx VLAN User Tag Priority 6 */ 573 #define ETH_RX_QUEUE_PRIO_7 0x00000080U /*!< Rx VLAN User Tag Priority 7 */ 574 /** 575 * 576 */ 577 578 /** @defgroup ETHEx_Preemption_Packet ETHEx Preemption Packet 579 * @{ 580 */ 581 #define ETH_EXPRESS_PACKET 0x00000000U 582 #define ETH_PREEMPTION_PACKET ETH_MACTMRQR_PFEX 583 /** 584 * @} 585 */ 586 587 /** @defgroup ETHEx_Command_Type ETHEx Command Type 588 * @{ 589 */ 590 #define ETH_WRITE_OPERATION 0x00000000U 591 #define ETH_READ_OPERATION ETH_MACIACR_COM 592 /** 593 * @} 594 */ 595 596 #ifdef HAL_ETH_USE_CBS 597 /** @defgroup ETHEx_CBS_Credit_Control ETHEx CBS Credit Control 598 * @{ 599 */ 600 #define ETH_ENABLE_CBS_CREDIT_CONTROL ETH_MTLTXQ1ECR_CC 601 #define ETH_DISABLE_CBS_CREDIT_CONTROL 0x00000000U 602 /** 603 * @} 604 */ 605 #endif /* HAL_ETH_USE_CBS */ 606 607 #ifdef HAL_ETH_USE_TAS 608 #ifndef ETH_HWRESET_TIMEOUT 609 #define ETH_HWRESET_TIMEOUT 1000U 610 #endif /* ETH_SWRESET_TIMEOUT */ 611 #endif /* HAL_ETH_USE_TAS */ 612 613 #ifdef HAL_ETH_USE_FPE 614 /** @defgroup ETHEx_FPE_Preemption_Classification ETHEx FPE Preemption Classification 615 * @{ 616 */ 617 #define ETH_QUEUE0_EXPRESS 0x00000000U 618 #define ETH_QUEUE0_PREEMPTABLE 0x00000100U 619 #define ETH_QUEUE1_EXPRESS 0x00000000U 620 #define ETH_QUEUE1_PREEMPTABLE 0x00000200U 621 /** 622 * @} 623 */ 624 #endif /* HAL_ETH_USE_FPE */ 625 /** 626 * @} 627 */ 628 629 /* Exported functions --------------------------------------------------------*/ 630 /** @addtogroup ETHEx_Exported_Functions 631 * @{ 632 */ 633 634 /** @addtogroup ETHEx_Exported_Functions_Group1 635 * @{ 636 */ 637 /* MAC ARP Offloading APIs ***************************************************/ 638 void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth); 639 void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth); 640 void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); 641 642 /* MAC L3 L4 Filtering APIs ***************************************************/ 643 void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth); 644 void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth); 645 HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, 646 ETH_L3FilterConfigTypeDef *pL3FilterConfig); 647 HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter, 648 ETH_L4FilterConfigTypeDef *pL4FilterConfig); 649 HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, 650 const ETH_L3FilterConfigTypeDef *pL3FilterConfig); 651 HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, 652 const ETH_L4FilterConfigTypeDef *pL4FilterConfig); 653 654 /* MAC VLAN Processing APIs ************************************************/ 655 void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth); 656 void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth); 657 HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); 658 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig); 659 void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable); 660 HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag, 661 ETH_TxVLANConfigTypeDef *pVlanConfig); 662 HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag, 663 const ETH_TxVLANConfigTypeDef *pVlanConfig); 664 void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier); 665 666 /* Energy Efficient Ethernet APIs *********************************************/ 667 void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, 668 FunctionalState TxClockStop); 669 void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth); 670 uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth); 671 /* Multi-Queue Ethernet APIs *********************************************/ 672 uint32_t HAL_ETHEx_GetRxDMAChNumber(const ETH_HandleTypeDef *heth); 673 uint32_t HAL_ETHEx_GetTxDMAChNumber(const ETH_HandleTypeDef *heth); 674 uint32_t HAL_ETHEx_GetRxMTLQNumber(const ETH_HandleTypeDef *heth); 675 uint32_t HAL_ETHEx_GetTxMTLQNumber(const ETH_HandleTypeDef *heth); 676 HAL_StatusTypeDef HAL_ETHEx_GetMTLConfig(const ETH_HandleTypeDef *heth, ETH_MTLConfigTypeDef *mtlconf); 677 HAL_StatusTypeDef HAL_ETHEx_SetMTLConfig(ETH_HandleTypeDef *heth, ETH_MTLConfigTypeDef *mtlconf); 678 HAL_StatusTypeDef HAL_ETHEx_SetMACMTLMappingConfig(ETH_HandleTypeDef *heth, const ETH_MACMTLMappingTypeDef *macmtlconf); 679 HAL_StatusTypeDef HAL_ETHEx_GetMACMTLMappingConfig(const ETH_HandleTypeDef *heth, ETH_MACMTLMappingTypeDef *macmtlconf); 680 void ETHEx_SetMTLConfig(ETH_HandleTypeDef *heth, const ETH_MTLConfigTypeDef *mtlconf); 681 HAL_StatusTypeDef ETHEx_SetMACMTLMappingConfig(ETH_HandleTypeDef *heth, const ETH_MACMTLMappingTypeDef *macmtlconf); 682 HAL_StatusTypeDef HAL_ETHEx_SetUserTagPriorityQueue(ETH_HandleTypeDef *heth, uint32_t psrq, uint32_t queue); 683 HAL_StatusTypeDef HAL_ETHEx_GetUserTagPriorityQueue(const ETH_HandleTypeDef *heth, uint32_t *psrq, 684 uint32_t queue); 685 HAL_StatusTypeDef HAL_ETHEx_SetPacketTypeQueue(ETH_HandleTypeDef *heth, 686 const ETH_PacketTypeQueueConfigTypeDef *typequeueconf); 687 HAL_StatusTypeDef HAL_ETHEx_GetPacketTypeQueue(ETH_HandleTypeDef *heth, 688 ETH_PacketTypeQueueConfigTypeDef *typequeueconf); 689 #ifdef HAL_ETH_USE_CBS 690 HAL_StatusTypeDef HAL_ETHEx_SetCBSConfig(ETH_HandleTypeDef *heth, ETH_CBSConfigTypeDef *cbsconf); 691 HAL_StatusTypeDef HAL_ETHEx_GetCBSConfig(const ETH_HandleTypeDef *heth, 692 ETH_CBSConfigTypeDef *pCBSConfig, uint8_t queueIndex); 693 HAL_StatusTypeDef HAL_ETHEx_EnableCBS(ETH_HandleTypeDef *heth, uint8_t queueIndex); 694 #endif /* HAL_ETH_USE_CBS */ 695 #ifdef HAL_ETH_USE_TAS 696 uint32_t HAL_ETHEx_GetGCLDepth(const ETH_HandleTypeDef *heth); 697 uint32_t HAL_ETHEx_GetGCLWidthTimeInterval(const ETH_HandleTypeDef *heth); 698 HAL_StatusTypeDef HAL_ETHEx_EnableEST(ETH_HandleTypeDef *heth); 699 HAL_StatusTypeDef HAL_ETHEx_DisableEST(ETH_HandleTypeDef *heth); 700 HAL_StatusTypeDef HAL_ETHEx_SetESTConfig(ETH_HandleTypeDef *heth, ETH_ESTConfigTypeDef *estconf); 701 HAL_StatusTypeDef HAL_ETHEx_SetGCLRegisters(ETH_HandleTypeDef *heth, const ETH_GCLConfigTypeDef *gclconf); 702 HAL_StatusTypeDef HAL_ETHEx_SetGCLConfig(ETH_HandleTypeDef *heth, ETH_GCLConfigTypeDef *gclconf); 703 HAL_StatusTypeDef HAL_ETHEx_GetGCLRegisters(ETH_HandleTypeDef *heth, ETH_GCLConfigTypeDef *gclconf); 704 #endif /* HAL_ETH_USE_TAS */ 705 #ifdef HAL_ETH_USE_FPE 706 HAL_StatusTypeDef HAL_ETHEx_EnableFPE(ETH_HandleTypeDef *heth); 707 HAL_StatusTypeDef HAL_ETHEx_DisableFPE(ETH_HandleTypeDef *heth); 708 HAL_StatusTypeDef HAL_ETHEx_GetFPEConfig(ETH_HandleTypeDef *heth, ETH_FPEConfigTypeDef *fpeconf); 709 HAL_StatusTypeDef HAL_ETHEx_SetFPEConfig(ETH_HandleTypeDef *heth, ETH_FPEConfigTypeDef *fpeconf); 710 #endif /* HAL_ETH_USE_FPE */ 711 712 /** 713 * @} 714 */ 715 716 /** 717 * @} 718 */ 719 720 /** 721 * @} 722 */ 723 724 /** 725 * @} 726 */ 727 728 /** 729 * @} 730 */ 731 732 #endif /* ETH1 */ 733 734 #ifdef __cplusplus 735 } 736 #endif 737 738 #endif /* STM32N6xx_HAL_ETH_EX_H */ 739
