1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Lcu_Ip.c
9 *
10 * @version 3.0.0
11 *
12 * @brief AUTOSAR Mcl - Lcu Ip driver source file.
13 * @details
14 *
15 * @addtogroup LCU_IP_DRIVER LCU IP Driver
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 #include "Lcu_Ip.h"
24 #include "Lcu_Ip_Irq.h"
25 #include "Lcu_Ip_Hw_Access.h"
26 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
27 #include "Lcu_Ip_Multicore.h"
28 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
29
30 #include "SchM_Mcl.h"
31
32 /*==================================================================================================
33 SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define LCU_IP_VENDOR_ID_C 43
36 #define LCU_IP_AR_RELEASE_MAJOR_VERSION_C 4
37 #define LCU_IP_AR_RELEASE_MINOR_VERSION_C 7
38 #define LCU_IP_AR_RELEASE_REVISION_VERSION_C 0
39 #define LCU_IP_SW_MAJOR_VERSION_C 3
40 #define LCU_IP_SW_MINOR_VERSION_C 0
41 #define LCU_IP_SW_PATCH_VERSION_C 0
42
43 /*==================================================================================================
44 FILE VERSION CHECKS
45 ==================================================================================================*/
46 /* Check if Lcu_Ip.c file and "Lcu_Ip.h" file are of the same vendor */
47 #if (LCU_IP_VENDOR_ID_C != LCU_IP_VENDOR_ID)
48 #error "Lcu_Ip.c and "Lcu_Ip.h" have different vendor ids"
49 #endif
50
51 /* Check if Lcu_Ip.c file and "Lcu_Ip.h" file are of the same Autosar version */
52 #if ((LCU_IP_AR_RELEASE_MAJOR_VERSION_C != LCU_IP_AR_RELEASE_MAJOR_VERSION) || \
53 (LCU_IP_AR_RELEASE_MINOR_VERSION_C != LCU_IP_AR_RELEASE_MINOR_VERSION) || \
54 (LCU_IP_AR_RELEASE_REVISION_VERSION_C != LCU_IP_AR_RELEASE_REVISION_VERSION) \
55 )
56 #error "AutoSar Version Numbers of Lcu_Ip.c and "Lcu_Ip.h" are different"
57 #endif
58
59 /* Check if Lcu_Ip.c file and "Lcu_Ip.h" file are of the same Software version */
60 #if ((LCU_IP_SW_MAJOR_VERSION_C != LCU_IP_SW_MAJOR_VERSION) || \
61 (LCU_IP_SW_MINOR_VERSION_C != LCU_IP_SW_MINOR_VERSION) || \
62 (LCU_IP_SW_PATCH_VERSION_C != LCU_IP_SW_PATCH_VERSION) \
63 )
64 #error "Software Version Numbers of Lcu_Ip.c and "Lcu_Ip.h" are different"
65 #endif
66
67 /* Check if Lcu_Ip.c file and Lcu_Ip_Hw_Access.h file are of the same vendor */
68 #if (LCU_IP_VENDOR_ID_C != LCU_IP_HW_ACCESS_VENDOR_ID)
69 #error "Lcu_Ip.c and Lcu_Ip_Hw_Access.h have different vendor ids"
70 #endif
71
72 /* Check if Lcu_Ip.c file and Lcu_Ip_Hw_Access.h file are of the same Autosar version */
73 #if ((LCU_IP_AR_RELEASE_MAJOR_VERSION_C != LCU_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION) || \
74 (LCU_IP_AR_RELEASE_MINOR_VERSION_C != LCU_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION) || \
75 (LCU_IP_AR_RELEASE_REVISION_VERSION_C != LCU_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION) \
76 )
77 #error "AutoSar Version Numbers of Lcu_Ip.c and Lcu_Ip_Hw_Access.h are different"
78 #endif
79
80 /* Check if Lcu_Ip.c file and Lcu_Ip_Hw_Access.h file are of the same Software version */
81 #if ((LCU_IP_SW_MAJOR_VERSION_C != LCU_IP_HW_ACCESS_SW_MAJOR_VERSION) || \
82 (LCU_IP_SW_MINOR_VERSION_C != LCU_IP_HW_ACCESS_SW_MINOR_VERSION) || \
83 (LCU_IP_SW_PATCH_VERSION_C != LCU_IP_HW_ACCESS_SW_PATCH_VERSION) \
84 )
85 #error "Software Version Numbers of Lcu_Ip.c and Lcu_Ip_Hw_Access.h are different"
86 #endif
87
88 /* Check if Lcu_Ip.c file and "Lcu_Ip_Irq.h" file are of the same vendor */
89 #if (LCU_IP_VENDOR_ID_C != LCU_IP_IRQ_VENDOR_ID)
90 #error "Lcu_Ip.c and "Lcu_Ip_Irq.h" have different vendor ids"
91 #endif
92
93 /* Check if Lcu_Ip.c file and "Lcu_Ip_Irq.h" file are of the same Autosar version */
94 #if ((LCU_IP_AR_RELEASE_MAJOR_VERSION_C != LCU_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
95 (LCU_IP_AR_RELEASE_MINOR_VERSION_C != LCU_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
96 (LCU_IP_AR_RELEASE_REVISION_VERSION_C != LCU_IP_IRQ_AR_RELEASE_REVISION_VERSION) \
97 )
98 #error "AutoSar Version Numbers of Lcu_Ip.c and "Lcu_Ip_Irq.h" are different"
99 #endif
100
101 /* Check if Lcu_Ip.c file and "Lcu_Ip_Irq.h" file are of the same Software version */
102 #if ((LCU_IP_SW_MAJOR_VERSION_C != LCU_IP_IRQ_SW_MAJOR_VERSION) || \
103 (LCU_IP_SW_MINOR_VERSION_C != LCU_IP_IRQ_SW_MINOR_VERSION) || \
104 (LCU_IP_SW_PATCH_VERSION_C != LCU_IP_IRQ_SW_PATCH_VERSION) \
105 )
106 #error "Software Version Numbers of Lcu_Ip.c and "Lcu_Ip_Irq.h" are different"
107 #endif
108
109 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
110 /* Check if Lcu_Ip.c file and "Lcu_Ip_Multicore.h" file are of the same vendor */
111 #if (LCU_IP_VENDOR_ID_C != LCU_IP_MULTICORE_VENDOR_ID)
112 #error "Lcu_Ip.c and "Lcu_Ip_Multicore.h" have different vendor ids"
113 #endif
114
115 /* Check if Lcu_Ip.c file and "Lcu_Ip_Multicore.h" file are of the same Autosar version */
116 #if ((LCU_IP_AR_RELEASE_MAJOR_VERSION_C != LCU_IP_MULTICORE_AR_RELEASE_MAJOR_VERSION) || \
117 (LCU_IP_AR_RELEASE_MINOR_VERSION_C != LCU_IP_MULTICORE_AR_RELEASE_MINOR_VERSION) || \
118 (LCU_IP_AR_RELEASE_REVISION_VERSION_C != LCU_IP_MULTICORE_AR_RELEASE_REVISION_VERSION) \
119 )
120 #error "AutoSar Version Numbers of Lcu_Ip.c and "Lcu_Ip_Multicore.h" are different"
121 #endif
122
123 /* Check if Lcu_Ip.c file and "Lcu_Ip_Multicore.h" file are of the same Software version */
124 #if ((LCU_IP_SW_MAJOR_VERSION_C != LCU_IP_MULTICORE_SW_MAJOR_VERSION) || \
125 (LCU_IP_SW_MINOR_VERSION_C != LCU_IP_MULTICORE_SW_MINOR_VERSION) || \
126 (LCU_IP_SW_PATCH_VERSION_C != LCU_IP_MULTICORE_SW_PATCH_VERSION) \
127 )
128 #error "Software Version Numbers of Lcu_Ip.c and "Lcu_Ip_Multicore.h" are different"
129 #endif
130 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
131
132 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
133 /* Check if Lcu_Ip.c file and SchM_Mcl header file are of the same Autosar version */
134 #if ((LCU_IP_AR_RELEASE_MAJOR_VERSION_C != SCHM_MCL_AR_RELEASE_MAJOR_VERSION) || \
135 (LCU_IP_AR_RELEASE_MINOR_VERSION_C != SCHM_MCL_AR_RELEASE_MINOR_VERSION))
136 #error "AutoSar Version Numbers of Lcu_Ip.c and SchM_Mcl.h are different"
137 #endif
138 #endif /* DISABLE_MCAL_INTERMODULE_ASR_CHECK */
139
140
141 #if (STD_ON == LCU_IP_IS_AVAILABLE)
142 /*==================================================================================================
143 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
144 ==================================================================================================*/
145
146 /*==================================================================================================
147 * LOCAL MACROS
148 ==================================================================================================*/
149
150 /*==================================================================================================
151 * LOCAL CONSTANTS
152 ==================================================================================================*/
153
154 /*==================================================================================================
155 * LOCAL VARIABLES
156 ==================================================================================================*/
157
158 /*==================================================================================================
159 * GLOBAL CONSTANTS
160 ==================================================================================================*/
161
162 /*==================================================================================================
163 * GLOBAL VARIABLES
164 ==================================================================================================*/
165 #define MCL_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
166 #include "Mcl_MemMap.h"
167
168 /* Pointer to the LCU Initialization Configuration. Based on this configuration pointer,
169 the LCU Driver obtains all information for the Logic Cell and corresponding
170 Cell Configurations.
171 The Pointer is loaded when Lcu_Ip_Init() is called. */
172 VAR_SEC_NOCACHE(Lcu_Ip_pxInit) static const Lcu_Ip_InitType * Lcu_Ip_pxInit;
173
174 #define MCL_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
175 #include "Mcl_MemMap.h"
176
177 /*==================================================================================================
178 * LOCAL FUNCTION PROTOTYPES
179 ==================================================================================================*/
180 #define MCL_START_SEC_CODE
181 #include "Mcl_MemMap.h"
182
183 /* Initializes the LCU inputs */
184 static void Lcu_Ip_LogicInputInit(const uint8 LogicInput, const Lcu_Ip_LogicInputConfigType * const pConfig);
185
186 /* Initializes the LCU outputs */
187 static void Lcu_Ip_LogicOutputInit(const uint8 LogicOutput, const Lcu_Ip_LogicOutputConfigType * const pConfig);
188
189 /* Initializes the LCU Instance */
190 static void Lcu_Ip_LogicInstanceInit(const Lcu_Ip_LogicInstanceType * pConfig);
191
192 /* Reset all configurations for Logic Instance */
193 static void Lcu_Ip_LogicInstanceReset(uint8 LogicInstace);
194
195 /* Clear all bit for status register */
196 static void Lcu_Ip_ClearAllStatus(uint8 LogicInstace);
197
198 static void Lcu_Ip_SetSwOverrideDisable(uint8 LogicInput);
199
200 static void Lcu_Ip_SetOutputDisable(uint8 LogicOutput);
201
202 static void Lcu_Ip_SetHwOutputCallbackState(uint8 LogicOutput);
203
204 #define MCL_STOP_SEC_CODE
205 #include "Mcl_MemMap.h"
206
207 /*==================================================================================================
208 * LOCAL FUNCTIONS
209 ==================================================================================================*/
210
211 /*==================================================================================================
212 * GLOBAL FUNCTIONS
213 ==================================================================================================*/
214
215 /*==================================================================================================
216 * LCU LOGIC INSTANCE FUNCTIONS
217 ==================================================================================================*/
218 #define MCL_START_SEC_CODE
219 #include "Mcl_MemMap.h"
220
Lcu_Ip_Init(const Lcu_Ip_InitType * const pxLcuInit)221 Lcu_Ip_ReturnType Lcu_Ip_Init(const Lcu_Ip_InitType * const pxLcuInit)
222 {
223 uint8 CfgIdx;
224 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
225
226 LCU_IP_DEV_ASSERT(NULL_PTR != pxLcuInit);
227 LCU_IP_DEV_ASSERT(NULL_PTR != pxLcuInit->ppxLogicOutputConfigArray);
228 LCU_IP_DEV_ASSERT(NULL_PTR != pxLcuInit->ppxLogicInputConfigArray);
229
230
231 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
232 LocStatus = Lcu_Ip_ValidateCoreInit(pxLcuInit);
233 if (LocStatus == LCU_IP_STATUS_SUCCESS)
234 {
235 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
236 /* Save pointer to initialization structure */
237 Lcu_Ip_pxInit = pxLcuInit;
238
239 (void)Lcu_Ip_Deinit();
240
241 /* Load input configuration */
242 for (CfgIdx = 0U; CfgIdx < LCU_IP_NOF_CFG_LOGIC_INPUTS; CfgIdx++)
243 {
244 Lcu_Ip_LogicInputInit(CfgIdx, Lcu_Ip_pxInit->ppxLogicInputConfigArray[CfgIdx]->pxLcInputConfig);
245 }
246
247 /* Load output configuration */
248 for (CfgIdx = 0U; CfgIdx < LCU_IP_NOF_CFG_LOGIC_OUTPUTS; CfgIdx++)
249 {
250 Lcu_Ip_LogicOutputInit(CfgIdx, Lcu_Ip_pxInit->ppxLogicOutputConfigArray[CfgIdx]->pxLcOutputConfig);
251 Lcu_Ip_SetHwOutputCallbackState(CfgIdx);
252 }
253
254 /* Load input configuration */
255 for (CfgIdx = 0U; CfgIdx < LCU_IP_NOF_CFG_LOGIC_INSTANCES; CfgIdx++)
256 {
257 Lcu_Ip_LogicInstanceInit(Lcu_Ip_pxInit->ppxLogicInstanceConfigArray[CfgIdx]);
258 }
259
260 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
261 }
262 else
263 {
264 /* Do nothing */
265 }
266 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
267
268 return LocStatus;
269 }
270
Lcu_Ip_SetHwOutputCallbackState(uint8 LogicOutput)271 static void Lcu_Ip_SetHwOutputCallbackState(uint8 LogicOutput)
272 {
273 uint8 HwInstance;
274 uint8 HwLcOutputId;
275 Lcu_Ip_Callback Callback;
276
277 Lcu_Ip_HwOutputStateType * ppxCallback = Lcu_Ip_pxInit->ppxHwOutputStateArray[LogicOutput];
278
279 const Lcu_Ip_LogicOutputIdType * ppxLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]->xLogicOutputId);
280
281 HwInstance = ppxLogicOutput->HwInstId;
282 HwLcOutputId = ppxLogicOutput->HwLcOutputId;
283 Callback = ppxLogicOutput->IntCallback;
284
285 /* Set hardware output */
286 HwAcc_Lcu_SetHwOutputSetState(HwInstance, HwLcOutputId, ppxCallback);
287
288 HwAcc_Lcu_SetHwOutputCallbackState(HwInstance, HwLcOutputId, Callback);
289 }
290
Lcu_Ip_LogicInstanceInit(const Lcu_Ip_LogicInstanceType * pConfig)291 static void Lcu_Ip_LogicInstanceInit(const Lcu_Ip_LogicInstanceType * pConfig)
292 {
293 uint8 CfgIdx;
294 uint8 HwInstance;
295 uint8 HwLogicCell;
296 const Lcu_Ip_LogicCellType * ppxLocLogicCell;
297 uint8 LocNumLogicCell;
298 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
299 uint8 LocCoreRef = 0U;
300 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
301
302 LCU_IP_DEV_ASSERT(NULL_PTR != pConfig);
303
304 HwInstance = pConfig->HwInstId;
305 LocNumLogicCell = pConfig->NumLogicCellConfig;
306
307 HwAcc_Lcu_SetInstanceOperationMode(HwInstance, pConfig-> OperationMode);
308
309 if (LocNumLogicCell > 0U)
310 {
311 for (CfgIdx = 0U; CfgIdx < LocNumLogicCell; CfgIdx++)
312 {
313 ppxLocLogicCell = pConfig->ppxLogicCellConfigArray[CfgIdx];
314 HwLogicCell = ppxLocLogicCell->HwLcId;
315
316 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
317 LocCoreRef = ppxLocLogicCell->CoreRef;
318 Lcu_Ip_SetCoreRef(HwInstance, HwLogicCell, LocCoreRef);
319 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
320
321
322 HwAcc_Lcu_SetForceFilter(HwInstance, HwLogicCell, ppxLocLogicCell->ForceFilter);
323 HwAcc_Lcu_SetForcePolarity(HwInstance, HwLogicCell, ppxLocLogicCell->ForcePolarity);
324 HwAcc_Lcu_SetCombineEnable(HwInstance, HwLogicCell, ppxLocLogicCell->CombEn);
325 HwAcc_Lcu_SetSwSyncSelect(HwInstance, HwLogicCell, ppxLocLogicCell->SwSyncSel);
326 }
327 }
328 }
329
Lcu_Ip_SetWriteProtect(const uint8 LogicInstance)330 Lcu_Ip_ReturnType Lcu_Ip_SetWriteProtect(const uint8 LogicInstance)
331 {
332 uint8 HwInstance = Lcu_Ip_pxInit->ppxLogicInstanceConfigArray[LogicInstance]->HwInstId;
333 Lcu_Ip_ReturnType ReturnValue = Lcu_Ip_GetWriteProtect(HwInstance);
334
335 if (LCU_IP_STATUS_SUCCESS == ReturnValue)
336 {
337 /* Set write protect */
338 HwAcc_Lcu_SetWriteProtect(HwInstance);
339 }
340
341 return ReturnValue;
342 }
343
Lcu_Ip_GetWriteProtect(const uint8 LogicInstance)344 Lcu_Ip_ReturnType Lcu_Ip_GetWriteProtect(const uint8 LogicInstance)
345 {
346 uint8 HwInstance = Lcu_Ip_pxInit->ppxLogicInstanceConfigArray[LogicInstance]->HwInstId;
347
348 /* Get write protect */
349 return HwAcc_Lcu_GetWriteProtect(HwInstance);
350 }
351
352
353 #if (STD_ON == LCU_IP_SYNC_FUNC_IS_AVAILABLE)
Lcu_Ip_SetSyncInputSwOverrideEnable(const Lcu_Ip_SyncInputValueType List[],const uint8 Dimension)354 Lcu_Ip_ReturnType Lcu_Ip_SetSyncInputSwOverrideEnable(const Lcu_Ip_SyncInputValueType List[], const uint8 Dimension)
355 {
356 uint8 LocHwLcu;
357 uint8 LocHwLcInputId;
358 uint8 LocLogicInputId;
359 uint8 LocIndex;
360 uint32 RegValue;
361 uint32 MaskValue[LCU_INSTANCE_COUNT];
362 uint32 DataValue[LCU_INSTANCE_COUNT];
363 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
364
365 #if (LCU_INSTANCE_COUNT >= 1U)
366 MaskValue[LCU_IP_HW_INST_0] = 0U;
367 DataValue[LCU_IP_HW_INST_0] = 0U;
368 #endif
369 #if (LCU_INSTANCE_COUNT >= 2U)
370 MaskValue[LCU_IP_HW_INST_1] = 0U;
371 DataValue[LCU_IP_HW_INST_1] = 0U;
372 #endif
373
374 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
375 {
376 /* Get the logic output value */
377 LocLogicInputId = List[LocIndex].LogicInputId;
378 /* Get the hardware output value */
379 LocHwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwInstId;
380 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwLcInputId;
381
382 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
383 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
384 if (LocStatus == LCU_IP_STATUS_SUCCESS)
385 {
386 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
387
388 MaskValue[LocHwLcu] |= (uint32)((uint32)1U << LocHwLcInputId);
389 DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcInputId);
390
391 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
392 }
393 else
394 {
395 break;
396 }
397 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
398 }
399
400 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
401 if (LocStatus == LCU_IP_STATUS_SUCCESS)
402 {
403 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
404
405 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_22();
406 #if (LCU_INSTANCE_COUNT >= 1U)
407 if(0U != MaskValue[LCU_IP_HW_INST_0])
408 {
409 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->SWEN;
410 RegValue &= ~MaskValue[LCU_IP_HW_INST_0];
411 RegValue |= DataValue[LCU_IP_HW_INST_0];
412 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->SWEN = RegValue;
413 }
414 else
415 {
416 /* Do nothing */
417 }
418 #endif
419 #if (LCU_INSTANCE_COUNT >= 2U)
420 if(0U != MaskValue[LCU_IP_HW_INST_1])
421 {
422 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->SWEN;
423 RegValue &= ~MaskValue[LCU_IP_HW_INST_1];
424 RegValue |= DataValue[LCU_IP_HW_INST_1];
425 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->SWEN = RegValue;
426 }
427 else
428 {
429 /* Do nothing */
430 }
431 #endif
432 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_22();
433
434 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
435 }
436 else
437 {
438 /* Do nothing */
439 }
440 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
441
442 return LocStatus;
443 }
444
445
Lcu_Ip_SetSyncInputSwOverrideValue(const Lcu_Ip_SyncInputValueType List[],const uint8 Dimension)446 Lcu_Ip_ReturnType Lcu_Ip_SetSyncInputSwOverrideValue(const Lcu_Ip_SyncInputValueType List[], const uint8 Dimension)
447 {
448 uint8 LocHwLcu;
449 uint8 LocHwLcInputId;
450 uint8 LocLogicInputId;
451 uint8 LocIndex;
452 uint32 RegValue;
453 uint32 MaskValue[LCU_INSTANCE_COUNT];
454 uint32 DataValue[LCU_INSTANCE_COUNT];
455 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
456
457 #if (LCU_INSTANCE_COUNT >= 1U)
458 MaskValue[LCU_IP_HW_INST_0] = 0U;
459 DataValue[LCU_IP_HW_INST_0] = 0U;
460 #endif
461 #if (LCU_INSTANCE_COUNT >= 2U)
462 MaskValue[LCU_IP_HW_INST_1] = 0U;
463 DataValue[LCU_IP_HW_INST_1] = 0U;
464 #endif
465
466 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
467 {
468 /* Get the logic output value */
469 LocLogicInputId = List[LocIndex].LogicInputId;
470 /* Get the hardware output value */
471 LocHwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwInstId;
472 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwLcInputId;
473
474 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
475 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
476 if (LocStatus == LCU_IP_STATUS_SUCCESS)
477 {
478 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
479
480 MaskValue[LocHwLcu] |= (uint32)((uint32)1U << LocHwLcInputId);
481 DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcInputId);
482
483 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
484 }
485 else
486 {
487 break;
488 }
489 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
490 }
491
492 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
493 if (LocStatus == LCU_IP_STATUS_SUCCESS)
494 {
495 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
496
497 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_23();
498 #if (LCU_INSTANCE_COUNT >= 1U)
499 if(0U != MaskValue[LCU_IP_HW_INST_0])
500 {
501 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->SWVALUE;
502 RegValue &= ~MaskValue[LCU_IP_HW_INST_0];
503 RegValue |= DataValue[LCU_IP_HW_INST_0];
504 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->SWVALUE = RegValue;
505 }
506 else
507 {
508 /* Do nothing */
509 }
510 #endif
511 #if (LCU_INSTANCE_COUNT >= 2U)
512 if(0U != MaskValue[LCU_IP_HW_INST_1])
513 {
514 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->SWVALUE;
515 RegValue &= ~MaskValue[LCU_IP_HW_INST_1];
516 RegValue |= DataValue[LCU_IP_HW_INST_1];
517 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->SWVALUE = RegValue;
518 }
519 else
520 {
521 /* Do nothing */
522 }
523 #endif
524 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_23();
525
526 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
527 }
528 else
529 {
530 /* Do nothing */
531 }
532 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
533
534 return LocStatus;
535 }
536
Lcu_Ip_SetSyncInputMuxSelect(const Lcu_Ip_SyncInputValueType List[],const uint8 Dimension)537 Lcu_Ip_ReturnType Lcu_Ip_SetSyncInputMuxSelect(const Lcu_Ip_SyncInputValueType List[], const uint8 Dimension)
538 {
539 uint8 LocHwLcu;
540 uint8 MaskValue;
541 uint8 LocHwLcInputId;
542 uint8 LocIndex;
543 uint8 LocLogicInputId;
544 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
545
546 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
547 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
548 {
549 /* Get the logic input value */
550 LocLogicInputId = List[LocIndex].LogicInputId;
551 /* Get the hardware input value */
552 LocHwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwInstId;
553 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwLcInputId;
554
555 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
556 if (LocStatus != LCU_IP_STATUS_SUCCESS)
557 {
558 break;
559 }
560 else
561 {
562 /* Do Nothing */
563 }
564 }
565 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
566
567 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
568 if (LocStatus == LCU_IP_STATUS_SUCCESS)
569 {
570 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
571
572 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
573 {
574 /* Get the logic input value */
575 LocLogicInputId = List[LocIndex].LogicInputId;
576 /* Get the hardware input value */
577 LocHwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwInstId;
578 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwLcInputId;
579
580 /* Set register value for hardware input */
581 MaskValue = ((List[LocIndex].Value) & LCU_MUXSEL_MUXSEL_MASK);
582 HwAcc_Lcu_AsyncSetInputMuxSelect(LocHwLcu, LocHwLcInputId, MaskValue);
583 }
584 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
585 }
586 else
587 {
588 /* Do Nothing */
589 }
590 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
591
592 return LocStatus;
593 }
594
Lcu_Ip_SetSyncInputSwSyncMode(const Lcu_Ip_SyncInputValueType List[],const uint8 Dimension)595 Lcu_Ip_ReturnType Lcu_Ip_SetSyncInputSwSyncMode(const Lcu_Ip_SyncInputValueType List[], const uint8 Dimension)
596 {
597 uint8 LocHwLcu;
598 uint8 MaskValue;
599 uint8 LocHwLcInputId;
600 uint8 LocIndex;
601 uint8 LocLogicInputId;
602 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
603
604 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
605 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
606 {
607 /* Get the logic input value */
608 LocLogicInputId = List[LocIndex].LogicInputId;
609 /* Get the hardware input value */
610 LocHwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwInstId;
611 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwLcInputId;
612
613 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
614 if (LocStatus != LCU_IP_STATUS_SUCCESS)
615 {
616 break;
617 }
618 else
619 {
620 /* Do Nothing */
621 }
622 }
623 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
624
625 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
626 if (LocStatus == LCU_IP_STATUS_SUCCESS)
627 {
628 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
629
630 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_24();
631 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
632 {
633 /* Get the logic input value */
634 LocLogicInputId = List[LocIndex].LogicInputId;
635 /* Get the hardware input value */
636 LocHwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwInstId;
637 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LocLogicInputId]->xLogicInputId.HwLcInputId;
638
639 /* Set register value for hardware input */
640 MaskValue = ((List[LocIndex].Value) & 1U);
641 HwAcc_Lcu_AsyncSetInputSwSyncMode(LocHwLcu, LocHwLcInputId, MaskValue);
642 }
643 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_24();
644
645 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
646 }
647 else
648 {
649 /* Do Nothing */
650 }
651 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
652
653 return LocStatus;
654 }
655
Lcu_Ip_SetSyncOutputDebugMode(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)656 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputDebugMode(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
657 {
658 uint8 LocHwLcu;
659 uint8 LocHwLcOutputId;
660 uint8 LocIndex;
661 uint8 LocLogicOutputId;
662 uint32 RegValue;
663 uint32 MaskValue[LCU_INSTANCE_COUNT];
664 uint32 DataValue[LCU_INSTANCE_COUNT];
665 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
666
667 #if (LCU_INSTANCE_COUNT >= 1U)
668 MaskValue[LCU_IP_HW_INST_0] = 0U;
669 DataValue[LCU_IP_HW_INST_0] = 0U;
670 #endif
671 #if (LCU_INSTANCE_COUNT >= 2U)
672 MaskValue[LCU_IP_HW_INST_1] = 0U;
673 DataValue[LCU_IP_HW_INST_1] = 0U;
674 #endif
675
676 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
677 {
678 /* Get the logic output value */
679 LocLogicOutputId = List[LocIndex].LogicOutputId;
680 /* Get the hardware output value */
681 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
682 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
683
684 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
685 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
686 if (LocStatus == LCU_IP_STATUS_SUCCESS)
687 {
688 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
689
690 MaskValue[LocHwLcu] |= (uint32)((uint32)1U << LocHwLcOutputId);
691 DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcOutputId);
692
693 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
694 }
695 else
696 {
697 break;
698 }
699 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
700 }
701
702 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
703 if (LocStatus == LCU_IP_STATUS_SUCCESS)
704 {
705 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
706
707 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_25();
708 #if (LCU_INSTANCE_COUNT >= 1U)
709 if(0U != MaskValue[LCU_IP_HW_INST_0])
710 {
711 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->DBGEN;
712 RegValue &= ~MaskValue[LCU_IP_HW_INST_0];
713 RegValue |= DataValue[LCU_IP_HW_INST_0];
714 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->DBGEN = RegValue;
715 }
716 else
717 {
718 /* Do nothing */
719 }
720 #endif
721 #if (LCU_INSTANCE_COUNT >= 2U)
722 if(0U != MaskValue[LCU_IP_HW_INST_1])
723 {
724 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->DBGEN;
725 RegValue &= ~MaskValue[LCU_IP_HW_INST_1];
726 RegValue |= DataValue[LCU_IP_HW_INST_1];
727 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->DBGEN = RegValue;
728 }
729 else
730 {
731 /* Do nothing */
732 }
733 #endif
734 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_25();
735
736 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
737 }
738 else
739 {
740 /* Do nothing */
741 }
742 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
743
744 return LocStatus;
745 }
746
Lcu_Ip_SetSyncOutputEnable(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)747 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputEnable(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
748 {
749 uint8 LocHwLcu;
750 uint8 LocHwLcOutputId;
751 uint8 LocIndex;
752 uint8 LocLogicOutputId;
753 uint32 RegValue;
754 uint32 MaskValue[LCU_INSTANCE_COUNT];
755 uint32 DataValue[LCU_INSTANCE_COUNT];
756 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
757
758 #if (LCU_INSTANCE_COUNT >= 1U)
759 MaskValue[LCU_IP_HW_INST_0] = 0U;
760 DataValue[LCU_IP_HW_INST_0] = 0U;
761 #endif
762 #if (LCU_INSTANCE_COUNT >= 2U)
763 MaskValue[LCU_IP_HW_INST_1] = 0U;
764 DataValue[LCU_IP_HW_INST_1] = 0U;
765 #endif
766
767 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
768 {
769 /* Get the logic output value */
770 LocLogicOutputId = List[LocIndex].LogicOutputId;
771 /* Get the hardware output value */
772 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
773 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
774
775 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
776 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
777 if (LocStatus == LCU_IP_STATUS_SUCCESS)
778 {
779 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
780
781 MaskValue[LocHwLcu] |= (uint32)((uint32)1U << LocHwLcOutputId);
782 DataValue[LocHwLcu] |= (uint32)(((uint32)(List[LocIndex].Value) & 1U) << LocHwLcOutputId);
783
784 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
785 }
786 else
787 {
788 break;
789 }
790 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
791 }
792
793 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
794 if (LocStatus == LCU_IP_STATUS_SUCCESS)
795 {
796 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
797
798 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_38();
799 #if (LCU_INSTANCE_COUNT >= 1U)
800 if(0U != MaskValue[LCU_IP_HW_INST_0])
801 {
802 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->OUTEN;
803 RegValue &= ~MaskValue[LCU_IP_HW_INST_0];
804 RegValue |= DataValue[LCU_IP_HW_INST_0];
805 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->OUTEN = RegValue;
806 }
807 else
808 {
809 /* Do nothing */
810 }
811 #endif
812 #if (LCU_INSTANCE_COUNT >= 2U)
813 if(0U != MaskValue[LCU_IP_HW_INST_1])
814 {
815 RegValue = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->OUTEN;
816 RegValue &= ~MaskValue[LCU_IP_HW_INST_1];
817 RegValue |= DataValue[LCU_IP_HW_INST_1];
818 Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->OUTEN = RegValue;
819 }
820 else
821 {
822 /* Do nothing */
823 }
824 #endif
825 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_38();
826
827 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
828 }
829 else
830 {
831 /* Do nothing */
832 }
833 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
834
835 return LocStatus;
836 }
837
Lcu_Ip_SetSyncOutputForceInputSensitivity(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)838 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputForceInputSensitivity(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
839 {
840 uint8 LocHwLcu;
841 uint8 LocHwLcOutputId;
842 uint16 MaskValue;
843 uint8 LocIndex;
844 uint8 LocLogicOutputId;
845 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
846
847 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
848 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
849 {
850 /* Get the logic output value */
851 LocLogicOutputId = List[LocIndex].LogicOutputId;
852 /* Get the hardware output value */
853 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
854 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
855
856 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
857 if (LocStatus != LCU_IP_STATUS_SUCCESS)
858 {
859 break;
860 }
861 else
862 {
863 /* Do Nothing */
864 }
865 }
866 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
867
868 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
869 if (LocStatus == LCU_IP_STATUS_SUCCESS)
870 {
871 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
872
873 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_26();
874 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
875 {
876 /* Get the logic output value */
877 LocLogicOutputId = List[LocIndex].LogicOutputId;
878 /* Get the hardware output value */
879 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
880 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
881
882 /* Set register value for hardware output */
883 MaskValue = ((List[LocIndex].Value) & LCU_FCTRL_FORCE_SENSE_COMMON_MASK);
884 (void)HwAcc_Lcu_AsyncSetOutputForceInputSensitivity(LocHwLcu, LocHwLcOutputId, MaskValue);
885 }
886 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_26();
887
888 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
889 }
890 else
891 {
892 /* Do Nothing */
893 }
894
895 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
896
897 return LocStatus;
898 }
899
Lcu_Ip_SetSyncOutputForceClearingMode(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)900 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputForceClearingMode(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
901 {
902 uint8 LocHwLcu;
903 uint8 LocHwLcOutputId;
904 uint16 MaskValue;
905 uint8 LocIndex;
906 uint8 LocLogicOutputId;
907 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
908
909 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
910 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
911 {
912 /* Get the logic output value */
913 LocLogicOutputId = List[LocIndex].LogicOutputId;
914 /* Get the hardware output value */
915 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
916 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
917
918 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
919 if (LocStatus != LCU_IP_STATUS_SUCCESS)
920 {
921 break;
922 }
923 else
924 {
925 /* Do Nothing */
926 }
927 }
928 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
929
930 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
931 if (LocStatus == LCU_IP_STATUS_SUCCESS)
932 {
933 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
934
935 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_27();
936 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
937 {
938 /* Get the logic output value */
939 LocLogicOutputId = List[LocIndex].LogicOutputId;
940 /* Get the hardware output value */
941 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
942 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
943
944 /* Set register value for hardware output */
945 MaskValue = ((List[LocIndex].Value) & LCU_FCTRL_FORCE_MODE_COMMON_MASK);
946 (void)HwAcc_Lcu_AsyncSetOutputForceClearingMode(LocHwLcu, LocHwLcOutputId, MaskValue);
947 }
948 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_27();
949
950 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
951 }
952 else
953 {
954 /* Do Nothing */
955 }
956 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
957
958 return LocStatus;
959 }
960
Lcu_Ip_SetSyncOutputForceSyncSelect(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)961 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputForceSyncSelect(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
962 {
963 uint8 LocHwLcu;
964 uint8 LocHwLcOutputId;
965 uint16 MaskValue;
966 uint8 LocIndex;
967 uint8 LocLogicOutputId;
968 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
969
970 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
971 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
972 {
973 /* Get the logic output value */
974 LocLogicOutputId = List[LocIndex].LogicOutputId;
975 /* Get the hardware output value */
976 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
977 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
978
979 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
980 if (LocStatus != LCU_IP_STATUS_SUCCESS)
981 {
982 break;
983 }
984 else
985 {
986 /* Do Nothing */
987 }
988 }
989 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
990
991 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
992 if (LocStatus == LCU_IP_STATUS_SUCCESS)
993 {
994 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
995
996 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_28();
997 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
998 {
999 /* Get the logic output value */
1000 LocLogicOutputId = List[LocIndex].LogicOutputId;
1001 /* Get the hardware output value */
1002 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1003 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1004
1005 /* Set register value for hardware output */
1006 MaskValue = ((List[LocIndex].Value) & LCU_FCTRL_SYNC_SEL_COMMON_MASK);
1007 (void)HwAcc_Lcu_AsyncSetOutputForceSyncSelect(LocHwLcu, LocHwLcOutputId, MaskValue);
1008 }
1009 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_28();
1010
1011 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1012 }
1013 else
1014 {
1015 /* Do Nothing */
1016 }
1017 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1018
1019 return LocStatus;
1020 }
1021
Lcu_Ip_SetSyncOutputPolarity(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1022 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputPolarity(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1023 {
1024 uint8 LocHwLcu;
1025 uint8 LocHwLcOutputId;
1026 uint16 MaskValue;
1027 uint8 LocIndex;
1028 uint8 LocLogicOutputId;
1029 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1030
1031 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1032 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1033 {
1034 /* Get the logic output value */
1035 LocLogicOutputId = List[LocIndex].LogicOutputId;
1036 /* Get the hardware output value */
1037 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1038 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1039
1040 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1041 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1042 {
1043 break;
1044 }
1045 else
1046 {
1047 /* Do Nothing */
1048 }
1049 }
1050 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1051
1052 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1053 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1054 {
1055 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1056
1057 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_29();
1058 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1059 {
1060 /* Get the logic output value */
1061 LocLogicOutputId = List[LocIndex].LogicOutputId;
1062 /* Get the hardware output value */
1063 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1064 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1065
1066 /* Set register value for hardware output */
1067 MaskValue = ((List[LocIndex].Value) & 1U);
1068 (void)HwAcc_Lcu_AsyncSetOutputPolarity(LocHwLcu, LocHwLcOutputId, MaskValue);
1069 }
1070 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_29();
1071
1072 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1073 }
1074 else
1075 {
1076 /* Do Nothing */
1077 }
1078 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1079
1080 return LocStatus;
1081 }
1082
Lcu_Ip_SetSyncOutputForceDma(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1083 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputForceDma(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1084 {
1085 uint8 LocHwLcu;
1086 uint8 LocHwLcOutputId;
1087 uint16 MaskValue;
1088 uint8 LocIndex;
1089 uint8 LocLogicOutputId;
1090 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1091
1092 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1093 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1094 {
1095 /* Get the logic output value */
1096 LocLogicOutputId = List[LocIndex].LogicOutputId;
1097 /* Get the hardware output value */
1098 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1099 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1100
1101 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1102 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1103 {
1104 break;
1105 }
1106 else
1107 {
1108 /* Do Nothing */
1109 }
1110 }
1111 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1112
1113 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1114 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1115 {
1116 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1117
1118 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_30();
1119 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1120 {
1121 /* Get the logic output value */
1122 LocLogicOutputId = List[LocIndex].LogicOutputId;
1123 /* Get the hardware output value */
1124 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1125 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1126
1127 /* Set register value for hardware output */
1128 MaskValue = ((List[LocIndex].Value) & 1U);
1129 (void)HwAcc_Lcu_AsyncSetOutputForceDma(LocHwLcu, LocHwLcOutputId, MaskValue);
1130 }
1131 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_30();
1132
1133 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1134 }
1135 else
1136 {
1137 /* Do Nothing */
1138 }
1139 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1140
1141 return LocStatus;
1142 }
1143
Lcu_Ip_SetSyncOutputForceInt(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1144 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputForceInt(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1145 {
1146 uint8 LocHwLcu;
1147 uint8 LocHwLcOutputId;
1148 uint16 MaskValue;
1149 uint8 LocIndex;
1150 uint8 LocLogicOutputId;
1151 boolean LocVerifyMode;
1152 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1153
1154 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1155 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1156 {
1157 /* Get the logic output value */
1158 LocLogicOutputId = List[LocIndex].LogicOutputId;
1159 /* Get the hardware output value */
1160 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1161 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1162
1163 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1164 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1165 {
1166 break;
1167 }
1168 else
1169 {
1170 /* Do Nothing */
1171 }
1172 }
1173 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1174
1175 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1176 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1177 {
1178 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1179
1180 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_31();
1181 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1182 {
1183 /* Get the logic output value */
1184 LocLogicOutputId = List[LocIndex].LogicOutputId;
1185 /* Get the hardware output value */
1186 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1187 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1188
1189 /* Set register value for hardware output */
1190 MaskValue = ((List[LocIndex].Value) & 1U);
1191 LocVerifyMode = HwAcc_Lcu_AsyncSetOutputForceInt(LocHwLcu, LocHwLcOutputId, MaskValue);
1192 if (LocVerifyMode == FALSE)
1193 {
1194 LocStatus = LCU_IP_STATUS_ERROR;
1195 break;
1196 }
1197 else
1198 {
1199 /* Do Nothing*/
1200 }
1201 }
1202 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_31();
1203
1204 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1205 }
1206 else
1207 {
1208 /* Do Nothing */
1209 }
1210 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1211
1212 return LocStatus;
1213 }
1214
Lcu_Ip_SetSyncOutputLutDma(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1215 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputLutDma(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1216 {
1217 uint8 LocHwLcu;
1218 uint8 LocHwLcOutputId;
1219 uint16 MaskValue;
1220 uint8 LocIndex;
1221 uint8 LocLogicOutputId;
1222 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1223
1224 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1225 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1226 {
1227 /* Get the logic output value */
1228 LocLogicOutputId = List[LocIndex].LogicOutputId;
1229 /* Get the hardware output value */
1230 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1231 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1232
1233 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1234 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1235 {
1236 break;
1237 }
1238 else
1239 {
1240 /* Do Nothing */
1241 }
1242 }
1243 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1244
1245 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1246 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1247 {
1248 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1249
1250 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_32();
1251 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1252 {
1253 /* Get the logic output value */
1254 LocLogicOutputId = List[LocIndex].LogicOutputId;
1255 /* Get the hardware output value */
1256 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1257 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1258
1259 /* Set register value for hardware output */
1260 MaskValue = ((List[LocIndex].Value) & 1U);
1261 (void)HwAcc_Lcu_AsyncSetOutputLutDma(LocHwLcu, LocHwLcOutputId, MaskValue);
1262 }
1263 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_32();
1264
1265 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1266 }
1267 else
1268 {
1269 /* Do Nothing */
1270 }
1271 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1272
1273 return LocStatus;
1274 }
1275
Lcu_Ip_SetSyncOutputLutInt(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1276 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputLutInt(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1277 {
1278 uint8 LocHwLcu;
1279 uint8 LocHwLcOutputId;
1280 uint16 MaskValue;
1281 uint8 LocIndex;
1282 uint8 LocLogicOutputId;
1283 boolean LocVerifyMode;
1284 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1285
1286 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1287 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1288 {
1289 /* Get the logic output value */
1290 LocLogicOutputId = List[LocIndex].LogicOutputId;
1291 /* Get the hardware output value */
1292 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1293 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1294
1295 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1296 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1297 {
1298 break;
1299 }
1300 else
1301 {
1302 /* Do Nothing */
1303 }
1304 }
1305 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1306
1307 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1308 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1309 {
1310 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1311
1312 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_33();
1313 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1314 {
1315 /* Get the logic output value */
1316 LocLogicOutputId = List[LocIndex].LogicOutputId;
1317 /* Get the hardware output value */
1318 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1319 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1320
1321 /* Set register value for hardware output */
1322 MaskValue = ((List[LocIndex].Value) & 1U);
1323 LocVerifyMode = HwAcc_Lcu_AsyncSetOutputLutInt(LocHwLcu, LocHwLcOutputId, MaskValue);
1324 if (LocVerifyMode == FALSE)
1325 {
1326 LocStatus = LCU_IP_STATUS_ERROR;
1327 break;
1328 }
1329 else
1330 {
1331 /* Do Nothing */
1332 }
1333 }
1334 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_33();
1335
1336 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1337 }
1338 else
1339 {
1340 /* Do Nothing */
1341 }
1342 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1343
1344 return LocStatus;
1345 }
1346
Lcu_Ip_SetSyncOutputFallFilter(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1347 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputFallFilter(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1348 {
1349 uint8 LocHwLcu;
1350 uint8 LocHwLcOutputId;
1351 uint16 MaskValue;
1352 uint8 LocIndex;
1353 uint8 LocLogicOutputId;
1354 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1355
1356 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1357 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1358 {
1359 /* Get the logic output value */
1360 LocLogicOutputId = List[LocIndex].LogicOutputId;
1361 /* Get the hardware output value */
1362 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1363 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1364
1365 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1366 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1367 {
1368 break;
1369 }
1370 else
1371 {
1372 /* Do Nothing */
1373 }
1374 }
1375 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1376
1377 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1378 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1379 {
1380 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1381
1382 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_34();
1383 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1384 {
1385 /* Get the logic output value */
1386 LocLogicOutputId = List[LocIndex].LogicOutputId;
1387 /* Get the hardware output value */
1388 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1389 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1390
1391 /* Set register value for hardware output */
1392 MaskValue = (List[LocIndex].Value & LCU_FILT_LUT_FALL_FILT_MASK);
1393 (void)HwAcc_Lcu_AsyncSetOutputFallFilter(LocHwLcu, LocHwLcOutputId, MaskValue);
1394 }
1395 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_34();
1396
1397 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1398 }
1399 else
1400 {
1401 /* Do Nothing */
1402 }
1403 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1404
1405 return LocStatus;
1406 }
1407
Lcu_Ip_SetSyncOutputRiseFilter(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1408 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputRiseFilter(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1409 {
1410 uint8 LocHwLcu;
1411 uint8 LocHwLcOutputId;
1412 uint8 LocIndex;
1413 uint8 LocLogicOutputId;
1414 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1415
1416 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1417 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1418 {
1419 /* Get the logic output value */
1420 LocLogicOutputId = List[LocIndex].LogicOutputId;
1421 /* Get the hardware output value */
1422 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1423 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1424
1425 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1426 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1427 {
1428 break;
1429 }
1430 else
1431 {
1432 /* Do Nothing */
1433 }
1434 }
1435 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1436
1437 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1438 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1439 {
1440 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1441
1442 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_35();
1443 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1444 {
1445 /* Get the logic output value */
1446 LocLogicOutputId = List[LocIndex].LogicOutputId;
1447 /* Get the hardware output value */
1448 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1449 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1450
1451 /* Set register value for hardware output */
1452 (void)HwAcc_Lcu_AsyncSetOutputRiseFilter(LocHwLcu, LocHwLcOutputId, List[LocIndex].Value);
1453 }
1454 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_35();
1455
1456 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1457 }
1458 else
1459 {
1460 /* Do Nothing */
1461 }
1462 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1463
1464 return LocStatus;
1465 }
1466
Lcu_Ip_SetSyncOutputLutControl(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1467 Lcu_Ip_ReturnType Lcu_Ip_SetSyncOutputLutControl(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1468 {
1469 uint8 LocHwLcu;
1470 uint8 LocHwLcOutputId;
1471 uint16 MaskValue;
1472 uint8 LocIndex;
1473 uint8 LocLogicOutputId;
1474 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1475
1476 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1477 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1478 {
1479 /* Get the logic output value */
1480 LocLogicOutputId = List[LocIndex].LogicOutputId;
1481 /* Get the hardware output value */
1482 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1483 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1484
1485 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1486 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1487 {
1488 break;
1489 }
1490 else
1491 {
1492 /* Do Nothing */
1493 }
1494 }
1495 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1496
1497 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1498 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1499 {
1500 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1501 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1502 {
1503 /* Get the logic output value */
1504 LocLogicOutputId = List[LocIndex].LogicOutputId;
1505 /* Get the hardware output value */
1506 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1507 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1508
1509 /* Set register value for hardware output */
1510 MaskValue = (List[LocIndex].Value & LCU_LUTCTRL_LUTCTRL_MASK);
1511 (void)HwAcc_Lcu_AsyncSetOutputLutControl(LocHwLcu, LocHwLcOutputId, MaskValue);
1512 }
1513 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1514 }
1515 else
1516 {
1517 /* Do Nothing */
1518 }
1519 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1520
1521 return LocStatus;
1522 }
1523
Lcu_Ip_ClearSyncOutputForceEvent(const Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1524 Lcu_Ip_ReturnType Lcu_Ip_ClearSyncOutputForceEvent(const Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1525 {
1526 uint8 LocHwLcu;
1527 uint8 LocHwLcOutputId;
1528 uint8 LocIndex;
1529 uint8 LocLogicOutputId;
1530 uint16 MaskValue = 0U;
1531 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1532
1533 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1534 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1535 {
1536 /* Get the logic output value */
1537 LocLogicOutputId = List[LocIndex].LogicOutputId;
1538 /* Get the hardware output value */
1539 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1540 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1541
1542 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1543 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1544 {
1545 break;
1546 }
1547 else
1548 {
1549 /* Do Nothing */
1550 }
1551 }
1552 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1553
1554 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1555 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1556 {
1557 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1558 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1559 {
1560 /* Get the logic output value */
1561 LocLogicOutputId = List[LocIndex].LogicOutputId;
1562 /* Get the hardware output value */
1563 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwLcOutputId;
1564 LocHwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LocLogicOutputId]->xLogicOutputId.HwInstId;
1565
1566 /* Set register value for hardware output */
1567 (void)HwAcc_Lcu_AsyncClearOutputForceEvent(LocHwLcu, LocHwLcOutputId, MaskValue);
1568 }
1569 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1570 }
1571 else
1572 {
1573 /* Do Nothing */
1574 }
1575 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1576
1577 return LocStatus;
1578 }
1579
Lcu_Ip_GetSyncLogicInput(Lcu_Ip_SyncInputValueType List[],const uint8 Dimension)1580 Lcu_Ip_ReturnType Lcu_Ip_GetSyncLogicInput(Lcu_Ip_SyncInputValueType List[], const uint8 Dimension)
1581 {
1582 uint8 LocIndex;
1583 Lcu_Ip_LogicInputIdType pxLocLogicInput;
1584 uint8 LocHwLcu;
1585 uint8 LocHwLcInputId;
1586 uint32 regLCU[LCU_INSTANCE_COUNT];
1587 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1588
1589 #if (LCU_INSTANCE_COUNT >= 1U)
1590 regLCU[LCU_IP_HW_INST_0] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->LCIN;
1591 #endif
1592 #if (LCU_INSTANCE_COUNT >= 2U)
1593 regLCU[LCU_IP_HW_INST_1] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->LCIN;
1594 #endif
1595
1596 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1597 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1598 {
1599 /* Get the hardware output value */
1600 pxLocLogicInput = Lcu_Ip_pxInit->ppxLogicInputConfigArray[(List[LocIndex].LogicInputId)]->xLogicInputId;
1601 LocHwLcu = pxLocLogicInput.HwInstId;
1602 LocHwLcInputId = pxLocLogicInput.HwLcInputId;
1603
1604 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
1605 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1606 {
1607 break;
1608 }
1609 else
1610 {
1611 /* Do Nothing */
1612 }
1613 }
1614 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1615
1616 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1617 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1618 {
1619 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1620 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1621 {
1622 /* Get the hardware output value */
1623 pxLocLogicInput = Lcu_Ip_pxInit->ppxLogicInputConfigArray[(List[LocIndex].LogicInputId)]->xLogicInputId;
1624 LocHwLcu = pxLocLogicInput.HwInstId;
1625 LocHwLcInputId = pxLocLogicInput.HwLcInputId;
1626
1627 List[LocIndex].Value = (uint8)((regLCU[LocHwLcu] >> LocHwLcInputId) & 1U);
1628 }
1629 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1630 }
1631 else
1632 {
1633 /* Do Nothing */
1634 }
1635 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1636
1637 return LocStatus;
1638 }
1639
Lcu_Ip_GetSyncSwOverrideInput(Lcu_Ip_SyncInputValueType List[],const uint8 Dimension)1640 Lcu_Ip_ReturnType Lcu_Ip_GetSyncSwOverrideInput(Lcu_Ip_SyncInputValueType List[], const uint8 Dimension)
1641 {
1642 uint8 LocIndex;
1643 const Lcu_Ip_LogicInputIdType * pxLocLogicInput;
1644 uint8 LocHwLcu;
1645 uint8 LocHwLcInputId;
1646 uint32 regLCU[LCU_INSTANCE_COUNT];
1647 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1648
1649 #if (LCU_INSTANCE_COUNT >= 1U)
1650 regLCU[LCU_IP_HW_INST_0] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->SWOUT;
1651 #endif
1652 #if (LCU_INSTANCE_COUNT >= 2U)
1653 regLCU[LCU_IP_HW_INST_1] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->SWOUT;
1654 #endif
1655
1656 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1657 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1658 {
1659 /* Get the hardware output value */
1660 pxLocLogicInput = &(Lcu_Ip_pxInit->ppxLogicInputConfigArray[(List[LocIndex].LogicInputId)]->xLogicInputId);
1661 LocHwLcu = pxLocLogicInput->HwInstId;
1662 LocHwLcInputId = pxLocLogicInput->HwLcInputId;
1663
1664 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
1665 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1666 {
1667 break;
1668 }
1669 else
1670 {
1671 /* Do Nothing */
1672 }
1673 }
1674 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1675
1676 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1677 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1678 {
1679 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1680
1681 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1682 {
1683 /* Get the hardware output value */
1684 pxLocLogicInput = &(Lcu_Ip_pxInit->ppxLogicInputConfigArray[(List[LocIndex].LogicInputId)]->xLogicInputId);
1685 LocHwLcu = pxLocLogicInput->HwInstId;
1686 LocHwLcInputId = pxLocLogicInput->HwLcInputId;
1687
1688 List[LocIndex].Value = (uint8)((regLCU[LocHwLcu] >> LocHwLcInputId) & 1U);
1689 }
1690 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1691 }
1692 else
1693 {
1694 /* Do Nothing */
1695 }
1696 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1697
1698 return LocStatus;
1699 }
1700
Lcu_Ip_GetSyncLogicOutput(Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1701 Lcu_Ip_ReturnType Lcu_Ip_GetSyncLogicOutput(Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1702 {
1703 uint8 LocIndex;
1704 const Lcu_Ip_LogicOutputIdType * pxLocLogicOutput;
1705 uint8 LocHwLcu;
1706 uint8 LocHwLcOutputId;
1707 uint32 regLCU[LCU_INSTANCE_COUNT];
1708 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1709
1710 #if (LCU_INSTANCE_COUNT >= 1U)
1711 regLCU[LCU_IP_HW_INST_0] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->LCOUT;
1712 #endif
1713 #if (LCU_INSTANCE_COUNT >= 2U)
1714 regLCU[LCU_IP_HW_INST_1] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->LCOUT;
1715 #endif
1716
1717 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1718 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1719 {
1720 /* Get the hardware output value */
1721 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1722 LocHwLcu = pxLocLogicOutput->HwInstId;
1723 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1724
1725 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1726 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1727 {
1728 break;
1729 }
1730 else
1731 {
1732 /* Do Nothing */
1733 }
1734 }
1735 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1736
1737 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1738 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1739 {
1740 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1741 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1742 {
1743 /* Get the hardware output value */
1744 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1745 LocHwLcu = pxLocLogicOutput->HwInstId;
1746 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1747
1748 List[LocIndex].Value = (uint8)((regLCU[LocHwLcu] >> LocHwLcOutputId) & 1U);
1749 }
1750 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1751 }
1752 else
1753 {
1754 /* Do Nothing */
1755 }
1756 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1757
1758 return LocStatus;
1759 }
1760
Lcu_Ip_GetSyncForceOutput(Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1761 Lcu_Ip_ReturnType Lcu_Ip_GetSyncForceOutput(Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1762 {
1763 uint8 LocIndex;
1764 const Lcu_Ip_LogicOutputIdType * pxLocLogicOutput;
1765 uint8 LocHwLcu;
1766 uint8 LocHwLcOutputId;
1767 uint32 regLCU[LCU_INSTANCE_COUNT];
1768 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1769
1770 #if (LCU_INSTANCE_COUNT >= 1U)
1771 regLCU[LCU_IP_HW_INST_0] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->FORCEOUT;
1772 #endif
1773 #if (LCU_INSTANCE_COUNT >= 2U)
1774 regLCU[LCU_IP_HW_INST_1] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->FORCEOUT;
1775 #endif
1776
1777 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1778 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1779 {
1780 /* Get the hardware output value */
1781 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1782 LocHwLcu = pxLocLogicOutput->HwInstId;
1783 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1784
1785 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1786 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1787 {
1788 break;
1789 }
1790 else
1791 {
1792 /* Do Nothing */
1793 }
1794 }
1795 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1796
1797 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1798 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1799 {
1800 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1801 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1802 {
1803 /* Get the hardware output value */
1804 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1805 LocHwLcu = pxLocLogicOutput->HwInstId;
1806 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1807
1808 List[LocIndex].Value = (uint8)((regLCU[LocHwLcu] >> LocHwLcOutputId) & 1U);
1809 }
1810 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1811 }
1812 else
1813 {
1814 /* Do Nothing */
1815 }
1816 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1817
1818 return LocStatus;
1819 }
1820
Lcu_Ip_GetSyncForceStatus(Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1821 Lcu_Ip_ReturnType Lcu_Ip_GetSyncForceStatus(Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1822 {
1823 uint8 LocIndex;
1824 const Lcu_Ip_LogicOutputIdType * pxLocLogicOutput;
1825 uint8 LocHwLcu;
1826 uint8 LocHwLcOutputId;
1827 uint32 regLCU[LCU_INSTANCE_COUNT];
1828 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1829
1830 #if (LCU_INSTANCE_COUNT >= 1U)
1831 regLCU[LCU_IP_HW_INST_0] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_0]->FORCESTS;
1832 #endif
1833 #if (LCU_INSTANCE_COUNT >= 2U)
1834 regLCU[LCU_IP_HW_INST_1] = Lcu_Ip_paxBaseInst[LCU_IP_HW_INST_1]->FORCESTS;
1835 #endif
1836
1837 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1838 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1839 {
1840 /* Get the hardware output value */
1841 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1842 LocHwLcu = pxLocLogicOutput->HwInstId;
1843 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1844
1845 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1846 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1847 {
1848 break;
1849 }
1850 else
1851 {
1852 /* Do Nothing */
1853 }
1854 }
1855 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1856
1857 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1858 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1859 {
1860 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1861 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1862 {
1863 /* Get the hardware output value */
1864 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1865 LocHwLcu = pxLocLogicOutput->HwInstId;
1866 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1867
1868 List[LocIndex].Value = (uint8)((regLCU[LocHwLcu] >> LocHwLcOutputId) & 1U);
1869 }
1870 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1871 }
1872 else
1873 {
1874 /* Do Nothing */
1875 }
1876 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1877
1878 return LocStatus;
1879 }
1880
Lcu_Ip_GetSyncCombineForceInput(Lcu_Ip_SyncOutputValueType List[],const uint8 Dimension)1881 Lcu_Ip_ReturnType Lcu_Ip_GetSyncCombineForceInput(Lcu_Ip_SyncOutputValueType List[], const uint8 Dimension)
1882 {
1883 uint8 LocIndex;
1884 const Lcu_Ip_LogicOutputIdType * pxLocLogicOutput;
1885 uint8 LocHwLcu;
1886 uint8 LocHwLcOutputId;
1887 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1888
1889 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1890 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1891 {
1892 /* Get the hardware output value */
1893 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1894 LocHwLcu = pxLocLogicOutput->HwInstId;
1895 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1896
1897 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
1898 if (LocStatus != LCU_IP_STATUS_SUCCESS)
1899 {
1900 break;
1901 }
1902 else
1903 {
1904 /* Do Nothing */
1905 }
1906 }
1907 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1908
1909 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1910 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1911 {
1912 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1913 for (LocIndex = 0U; LocIndex < Dimension; LocIndex++)
1914 {
1915 /* Get the hardware output value */
1916 pxLocLogicOutput = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[(List[LocIndex].LogicOutputId)]->xLogicOutputId);
1917 LocHwLcu = pxLocLogicOutput->HwInstId;
1918 LocHwLcOutputId = pxLocLogicOutput->HwLcOutputId;
1919
1920 List[LocIndex].Value = HwAcc_Lcu_AsyncGetCombineForceInput(LocHwLcu, LocHwLcOutputId);
1921 }
1922 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1923 }
1924 else
1925 {
1926 /* Do Nothing */
1927 }
1928 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1929
1930 return LocStatus;
1931 }
1932 #endif /* #if (STD_ON == LCU_IP_SYNC_FUNC_IS_AVAILABLE) */
1933
Lcu_Ip_LogicInputInit(const uint8 LogicInput,const Lcu_Ip_LogicInputConfigType * const pConfig)1934 static void Lcu_Ip_LogicInputInit(const uint8 LogicInput, const Lcu_Ip_LogicInputConfigType * const pConfig)
1935 {
1936 uint8 HwLcu;
1937 uint8 LocHwLcInputId;
1938
1939 LCU_IP_DEV_ASSERT(NULL_PTR != pConfig);
1940
1941 /* Get the hardware output value */
1942 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]->xLogicInputId.HwLcInputId;
1943 HwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]->xLogicInputId.HwInstId;
1944
1945 HwAcc_Lcu_AsyncSetInputMuxSelect(HwLcu, LocHwLcInputId, pConfig->MuxSel);
1946 HwAcc_Lcu_AsyncSetInputSwSyncMode(HwLcu, LocHwLcInputId, (pConfig->SwSynMode ? 1U : 0U));
1947 HwAcc_Lcu_AsyncSetInputSwOverrideValue(HwLcu, LocHwLcInputId, (pConfig->SwValue & 1U));
1948
1949 }
1950
Lcu_Ip_LogicOutputInit(const uint8 LogicOutput,const Lcu_Ip_LogicOutputConfigType * const pConfig)1951 static void Lcu_Ip_LogicOutputInit(const uint8 LogicOutput, const Lcu_Ip_LogicOutputConfigType * const pConfig)
1952 {
1953 uint8 HwLcu;
1954 uint8 LocHwLcOutputId;
1955
1956 LCU_IP_DEV_ASSERT(NULL_PTR != pConfig);
1957
1958 /* Get the hardware output value */
1959 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]->xLogicOutputId.HwLcOutputId;
1960 HwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]->xLogicOutputId.HwInstId;
1961
1962 (void)HwAcc_Lcu_AsyncSetOutputDebugMode(HwLcu, LocHwLcOutputId, (pConfig->EnDebugMode ? 1U : 0U));
1963 (void)HwAcc_Lcu_AsyncSetOutputLutControl(HwLcu, LocHwLcOutputId, pConfig->LutControl);
1964 (void)HwAcc_Lcu_AsyncSetOutputRiseFilter(HwLcu, LocHwLcOutputId, pConfig->LutRiseFilt);
1965 (void)HwAcc_Lcu_AsyncSetOutputFallFilter(HwLcu, LocHwLcOutputId, pConfig->LutFallFilt);
1966 (void)HwAcc_Lcu_AsyncSetOutputLutDma(HwLcu, LocHwLcOutputId, (pConfig->EnLutDma ? 1U : 0U));
1967 (void)HwAcc_Lcu_AsyncSetOutputForceDma(HwLcu, LocHwLcOutputId, (pConfig->EnForceDma ? 1U : 0U));
1968 (void)HwAcc_Lcu_AsyncSetOutputLutInt(HwLcu, LocHwLcOutputId, (pConfig->EnLutInt ? 1U : 0U));
1969 (void)HwAcc_Lcu_AsyncSetOutputForceInt(HwLcu, LocHwLcOutputId, (pConfig->EnForceInt ? 1U : 0U));
1970 (void)HwAcc_Lcu_AsyncSetOutputPolarity(HwLcu, LocHwLcOutputId, (pConfig->InvertOutput ? 1U : 0U));
1971 HwAcc_Lcu_SetLcForceControl(HwLcu, LocHwLcOutputId, pConfig);
1972
1973 }
1974
Lcu_Ip_Deinit(void)1975 Lcu_Ip_ReturnType Lcu_Ip_Deinit(void)
1976 {
1977 uint8 CfgIdx;
1978 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
1979
1980 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit);
1981 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit->pxLogicOutputResetConfigArray);
1982 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit->pxLogicInputResetConfigArray);
1983
1984 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
1985 LocStatus = Lcu_Ip_ValidateCoreInit(Lcu_Ip_pxInit);
1986 if (LocStatus == LCU_IP_STATUS_SUCCESS)
1987 {
1988 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
1989
1990 /* Reset all common configuration for Input */
1991 for (CfgIdx = 0U; CfgIdx < LCU_IP_NOF_CFG_LOGIC_INPUTS; CfgIdx++)
1992 {
1993 Lcu_Ip_LogicInputInit(CfgIdx, Lcu_Ip_pxInit->pxLogicInputResetConfigArray);
1994 Lcu_Ip_SetSwOverrideDisable(CfgIdx);
1995 }
1996
1997 /* Reset all common configuration for Output */
1998 for (CfgIdx = 0U; CfgIdx < LCU_IP_NOF_CFG_LOGIC_OUTPUTS; CfgIdx++)
1999 {
2000 Lcu_Ip_LogicOutputInit(CfgIdx, Lcu_Ip_pxInit->pxLogicOutputResetConfigArray);
2001 Lcu_Ip_SetOutputDisable(CfgIdx);
2002 }
2003
2004 /* Reset all common configuration for Instance and status */
2005 for (CfgIdx = 0U; CfgIdx < LCU_IP_NOF_CFG_LOGIC_INSTANCES; CfgIdx++)
2006 {
2007 /* Reset all configurations for Logic Instance */
2008 Lcu_Ip_LogicInstanceReset(CfgIdx);
2009 /* Clear all bit for status register */
2010 Lcu_Ip_ClearAllStatus(CfgIdx);
2011 }
2012
2013 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2014 }
2015 else
2016 {
2017 /* Do nothing */
2018 }
2019 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2020
2021 return LocStatus;
2022 }
2023
2024 /* Reset all configurations for Logic Instance */
Lcu_Ip_LogicInstanceReset(uint8 LogicInstace)2025 static void Lcu_Ip_LogicInstanceReset(uint8 LogicInstace)
2026 {
2027 uint8 LcIndex;
2028 uint8 HwInstance = Lcu_Ip_pxInit->ppxLogicInstanceConfigArray[LogicInstace]->HwInstId;
2029
2030 for (LcIndex = 0U; LcIndex < LCU_LC_COUNT; LcIndex++)
2031 {
2032 HwAcc_Lcu_SetForceFilter(HwInstance, LcIndex, FORCE_FILTER_RESET_VALUE);
2033 HwAcc_Lcu_SetForcePolarity(HwInstance, LcIndex, FORCE_POLARITY_RESET_VALUE);
2034 HwAcc_Lcu_SetCombineEnable(HwInstance, LcIndex, COMBEN_RESET_VALUE);
2035 HwAcc_Lcu_SetSwSyncSelect(HwInstance, LcIndex, SW_SYNC_SEL_RESET_VALUE);
2036 }
2037 }
2038 /* Clear all bit for status register */
Lcu_Ip_ClearAllStatus(uint8 LogicInstace)2039 static void Lcu_Ip_ClearAllStatus(uint8 LogicInstace)
2040 {
2041 uint8 LcIndex;
2042 uint8 HwInstance = Lcu_Ip_pxInit->ppxLogicInstanceConfigArray[LogicInstace]->HwInstId;
2043
2044 for (LcIndex = 0U; LcIndex < LCU_LC_COUNT; LcIndex++)
2045 {
2046 HwAcc_Lcu_AsyncClearAllForceEvent(HwInstance, LcIndex);
2047 HwAcc_Lcu_AsyncClearAllLutEvent(HwInstance, LcIndex);
2048 }
2049 }
2050
Lcu_Ip_SetSwOverrideDisable(uint8 LogicInput)2051 static void Lcu_Ip_SetSwOverrideDisable(uint8 LogicInput)
2052 {
2053 uint8 HwLcu = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]->xLogicInputId.HwInstId;
2054 uint8 LocHwLcInputId = Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]->xLogicInputId.HwLcInputId;
2055 /* Set input software override enable */
2056 HwAcc_Lcu_AsyncSetInputSwOverrideEnable(HwLcu, LocHwLcInputId, LCU_IP_SW_OVERRIDE_DISABLE);
2057 }
2058
Lcu_Ip_SetOutputDisable(uint8 LogicOutput)2059 static void Lcu_Ip_SetOutputDisable(uint8 LogicOutput)
2060 {
2061 uint8 HwLcu = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]->xLogicOutputId.HwInstId;
2062 uint8 LocHwLcOutputId = Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]->xLogicOutputId.HwLcOutputId;
2063 /* Set output enable */
2064 (void)HwAcc_Lcu_AsyncSetOutputEnable(HwLcu, LocHwLcOutputId, LCU_IP_OUTPUT_DISABLE);
2065 }
2066
Lcu_Ip_IrqHandler(const uint8 HwInstance,const uint8 HwLogicCell,const uint8 HwOutput,const Lcu_Ip_Event Event)2067 void Lcu_Ip_IrqHandler(const uint8 HwInstance, const uint8 HwLogicCell, const uint8 HwOutput, const Lcu_Ip_Event Event)
2068 {
2069 Lcu_Ip_HwOutputStateType * LocHwOutputState = HwAcc_Lcu_GetHwOutputStatePointer(HwInstance, HwLogicCell, HwOutput);
2070
2071 if (NULL_PTR != LocHwOutputState)
2072 {
2073 if (NULL_PTR != LocHwOutputState->Callback)
2074 {
2075 /* Set callback */
2076 LocHwOutputState->Callback(Event);
2077 }
2078 }
2079 }
2080
2081 #if (STD_ON == LCU_IP_ASYNC_FUNC_IS_AVAILABLE)
Lcu_Ip_SetAsyncInputList(const uint8 LogicInput,const Lcu_Ip_AsyncInputValueType List[],const uint8 Dimension)2082 Lcu_Ip_ReturnType Lcu_Ip_SetAsyncInputList(const uint8 LogicInput, const Lcu_Ip_AsyncInputValueType List[], const uint8 Dimension)
2083 {
2084 uint8 Index;
2085 uint8 LocHwLcu;
2086 uint8 LocHwLcInputId;
2087 const Lcu_Ip_LogicInputIdType * pxLocLogicInputId;
2088 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
2089
2090 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit);
2091 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]);
2092 LCU_IP_DEV_ASSERT(LCU_IP_NOF_CFG_LOGIC_INPUTS > LogicInput);
2093 LCU_IP_DEV_ASSERT(LCU_IP_INPUT_SET_SW_VALUE >= Dimension);
2094
2095 pxLocLogicInputId = &(Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]->xLogicInputId);
2096
2097 LocHwLcu = pxLocLogicInputId->HwInstId;
2098 LocHwLcInputId = pxLocLogicInputId->HwLcInputId;
2099
2100 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2101 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
2102 if (LocStatus == LCU_IP_STATUS_SUCCESS)
2103 {
2104 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2105
2106 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_36();
2107 for (Index = 0U; Index < Dimension; Index++)
2108 {
2109 LCU_IP_DEV_ASSERT(LCU_IP_INPUT_SET_SW_VALUE >= List[Index].Param);
2110 HwAcc_Lcu_AsyncSetInputList((uint32)(List[Index].Param), LocHwLcu, LocHwLcInputId, List[Index].Value);
2111 }
2112 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_36();
2113
2114 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2115 }
2116 else
2117 {
2118 /* Do Nothing */
2119 }
2120 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2121
2122 return LocStatus;
2123 }
2124
Lcu_Ip_SetAsyncOutputList(const uint8 LogicOutput,const Lcu_Ip_AsyncOutputValueType List[],const uint8 Dimension)2125 Lcu_Ip_ReturnType Lcu_Ip_SetAsyncOutputList(const uint8 LogicOutput, const Lcu_Ip_AsyncOutputValueType List[], const uint8 Dimension)
2126 {
2127 uint8 Index;
2128 uint8 LocHwLcu;
2129 uint8 LocHwLcOutputId;
2130 const Lcu_Ip_LogicOutputIdType * pxLocLogicOutputId;
2131 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
2132 boolean LocVerifyMode;
2133
2134 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit);
2135 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]);
2136 LCU_IP_DEV_ASSERT(LCU_IP_NOF_CFG_LOGIC_OUTPUTS > LogicOutput);
2137 LCU_IP_DEV_ASSERT(LCU_IP_OUTPUT_CLEAR_FORCE_STS >= Dimension);
2138
2139 pxLocLogicOutputId = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]->xLogicOutputId);
2140
2141 LocHwLcu = pxLocLogicOutputId->HwInstId;
2142 LocHwLcOutputId = pxLocLogicOutputId->HwLcOutputId;
2143
2144 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2145 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
2146 if (LocStatus == LCU_IP_STATUS_SUCCESS)
2147 {
2148 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2149
2150 SchM_Enter_Mcl_MCL_EXCLUSIVE_AREA_37();
2151 for (Index = 0U; Index < Dimension; Index++)
2152 {
2153 LCU_IP_DEV_ASSERT(LCU_IP_OUTPUT_CLEAR_FORCE_STS >= List[Index].Param);
2154 LocVerifyMode = HwAcc_Lcu_AsyncSetOutputList((uint32)(List[Index].Param), LocHwLcu, LocHwLcOutputId, List[Index].Value);
2155 if (FALSE == LocVerifyMode)
2156 {
2157 LocStatus = LCU_IP_STATUS_ERROR;
2158 break;
2159 }
2160 else
2161 {
2162 /* Do Nothing*/
2163 }
2164 }
2165 SchM_Exit_Mcl_MCL_EXCLUSIVE_AREA_37();
2166
2167 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2168 }
2169 else
2170 {
2171 /* Do Nothing */
2172 }
2173 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2174
2175 return LocStatus;
2176 }
2177
Lcu_Ip_GetAsyncLogicInputInfo(const uint8 LogicInput,const Lcu_Ip_LogicInputInfoParamType Param,uint8 * const Value)2178 Lcu_Ip_ReturnType Lcu_Ip_GetAsyncLogicInputInfo(const uint8 LogicInput, const Lcu_Ip_LogicInputInfoParamType Param, uint8 * const Value)
2179 {
2180 uint8 LocHwLcu;
2181 uint8 LocHwLcInputId;
2182 const Lcu_Ip_LogicInputIdType * pxLocLogicInputId;
2183 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
2184
2185 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit);
2186 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]);
2187 LCU_IP_DEV_ASSERT(LCU_IP_NOF_CFG_LOGIC_INPUTS > LogicInput);
2188 LCU_IP_DEV_ASSERT(LCU_IP_INPUT_GET_SW_OVERRIDE_STATE >= Param);
2189
2190 pxLocLogicInputId = &(Lcu_Ip_pxInit->ppxLogicInputConfigArray[LogicInput]->xLogicInputId);
2191
2192 LocHwLcu = pxLocLogicInputId->HwInstId;
2193 LocHwLcInputId = pxLocLogicInputId->HwLcInputId;
2194
2195 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2196 LocStatus = Lcu_Ip_InputValidateCore(LocHwLcu, LocHwLcInputId);
2197 if (LocStatus == LCU_IP_STATUS_SUCCESS)
2198 {
2199 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2200
2201 HwAcc_Lcu_AsynGetInputInfo((uint8)Param, LocHwLcu, LocHwLcInputId, Value);
2202
2203 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2204 }
2205 else
2206 {
2207 /* Do Nothing */
2208 }
2209 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2210
2211 return LocStatus;
2212 }
2213
Lcu_Ip_GetAsyncLogicOutputInfo(const uint8 LogicOutput,const Lcu_Ip_LogicOutputInfoParamType Param,uint8 * const Value)2214 Lcu_Ip_ReturnType Lcu_Ip_GetAsyncLogicOutputInfo(const uint8 LogicOutput, const Lcu_Ip_LogicOutputInfoParamType Param, uint8 * const Value)
2215 {
2216 uint8 LocHwLcu;
2217 uint8 LocHwLcOutputId;
2218 const Lcu_Ip_LogicOutputIdType * pxLocLogicOutputId;
2219 Lcu_Ip_ReturnType LocStatus = LCU_IP_STATUS_SUCCESS;
2220
2221 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit);
2222 LCU_IP_DEV_ASSERT(NULL_PTR != Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]);
2223 LCU_IP_DEV_ASSERT(LCU_IP_NOF_CFG_LOGIC_OUTPUTS > LogicOutput);
2224 LCU_IP_DEV_ASSERT(LCU_IP_OUTPUT_GET_COMBINE_FORCE_INPUT >= Param);
2225
2226 pxLocLogicOutputId = &(Lcu_Ip_pxInit->ppxLogicOutputConfigArray[LogicOutput]->xLogicOutputId);
2227
2228 LocHwLcu = pxLocLogicOutputId->HwInstId;
2229 LocHwLcOutputId = pxLocLogicOutputId->HwLcOutputId;
2230
2231 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2232 LocStatus = Lcu_Ip_OutputValidateCore(LocHwLcu, LocHwLcOutputId);
2233 if (LocStatus == LCU_IP_STATUS_SUCCESS)
2234 {
2235 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2236
2237 HwAcc_Lcu_AsynGetOutputInfo((uint8)Param, LocHwLcu, LocHwLcOutputId, Value);
2238
2239 #if (STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE)
2240 }
2241 else
2242 {
2243 /* Do Nothing */
2244 }
2245 #endif /* STD_ON == LCU_IP_MULTICORE_IS_AVAILABLE */
2246
2247 return LocStatus;
2248 }
2249 #endif /* #if (STD_ON == LCU_IP_ASYNC_FUNC_IS_AVAILABLE) */
2250
2251 #define MCL_STOP_SEC_CODE
2252 #include "Mcl_MemMap.h"
2253
2254 #endif /* #ifdef LCU_IP_IS_AVAILABLE */
2255
2256 #ifdef __cplusplus
2257 }
2258 #endif
2259
2260 /** @} */
2261
