1 /* Copyright (c) 2023 Intel Corporation 2 * SPDX-License-Identifier: Apache-2.0 3 */ 4 5 #ifndef __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__ 6 #define __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__ 7 8 #ifdef _ASMLANGUAGE 9 10 #define HSPGCTL0 0x71D10 11 #define HSRMCTL0 0x71D14 12 #define HSPGISTS0 0x71D18 13 14 #define LSPGCTL 0x71D50 15 #define LSRMCTL 0x71D54 16 #define LSPGISTS 0x71D58 17 18 #define SHIM_HSPGCTL(x) (HSPGCTL0 + 0x10 * (x)) 19 #define SHIM_HSPGISTS(x) (HSPGISTS0 + 0x10 * (x)) 20 21 #define LPSRAM_MASK 0x1 22 /** 23 * Macro powers down entire HPSRAM. On entry literals and code for section from 24 * where this code is executed need to be placed in memory which is not 25 * HPSRAM (in case when this code is located in HPSRAM, lock memory in L1$ or 26 * L1 SRAM) 27 */ 28 .macro m_cavs_hpsram_power_down_entire ax, ay, az 29 /* SEGMENT #0 */ 30 movi \az, SHIM_HSPGCTL(0) 31 movi \ax, SHIM_HSPGISTS(0) 32 movi \ay, 0x1FFFFFFF /* HPSRAM_MASK(0) */ 33 s32i \ay, \ax, 0 34 memw 35 1 : 36 l32i \ax, \az, 0 37 bne \ax, \ay, 1b 38 39 /* SEGMENT #1 */ 40 movi \az, SHIM_HSPGCTL(1) 41 movi \ax, SHIM_HSPGISTS(1) 42 movi \ay, 0x0FFFFFFF /* HPSRAM_MASK(1) */ 43 s32i \ay, \ax, 0 44 memw 45 1 : 46 l32i \ax, \az, 0 47 bne \ax, \ay, 1b 48 .endm 49 50 .macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az 51 movi \ax, SHIM_HSPGCTL(\segment_index) 52 movi \ay, SHIM_HSPGISTS(\segment_index) 53 s32i \mask, \ax, 0 54 memw 55 /* assumed that HDA shared dma buffer will be in LPSRAM */ 56 1 : 57 l32i \ax, \ay, 0 58 bne \ax, \mask, 1b 59 .endm 60 61 .macro m_cavs_lpsram_power_down_entire ax, ay, az, loop_cnt_addr 62 movi \az, LSPGISTS 63 movi \ax, LSPGCTL 64 movi \ay, LPSRAM_MASK 65 s32i \ay, \ax, 0 66 memw 67 /* assumed that HDA shared dma buffer will be in LPSRAM */ 68 movi \ax, \loop_cnt_addr 69 l32i \ax, \ax, 0 70 1 : 71 addi \ax, \ax, -1 72 bnez \ax, 1b 73 .endm 74 75 #endif 76 #endif 77
