1 /** 2 ****************************************************************************** 3 * @file lsm6dsv16x_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsv16x_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2022 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSV16X_REGS_H 23 #define LSM6DSV16X_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSV16X 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSV16X_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSV16X_I2C_ADD_L 0xD5U 173 #define LSM6DSV16X_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSV16X_ID 0x70U 177 178 /** 179 * @} 180 * 181 */ 182 183 /** @defgroup bitfields page main 184 * @{ 185 * 186 */ 187 188 #define LSM6DSV16X_FUNC_CFG_ACCESS 0x1U 189 typedef struct 190 { 191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 192 uint8_t ois_ctrl_from_ui : 1; 193 uint8_t spi2_reset : 1; 194 uint8_t sw_por : 1; 195 uint8_t fsm_wr_ctrl_en : 1; 196 uint8_t not_used0 : 2; 197 uint8_t shub_reg_access : 1; 198 uint8_t emb_func_reg_access : 1; 199 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 200 uint8_t emb_func_reg_access : 1; 201 uint8_t shub_reg_access : 1; 202 uint8_t not_used0 : 2; 203 uint8_t fsm_wr_ctrl_en : 1; 204 uint8_t sw_por : 1; 205 uint8_t spi2_reset : 1; 206 uint8_t ois_ctrl_from_ui : 1; 207 #endif /* DRV_BYTE_ORDER */ 208 } lsm6dsv16x_func_cfg_access_t; 209 210 #define LSM6DSV16X_PIN_CTRL 0x2U 211 typedef struct 212 { 213 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 214 uint8_t not_used0 : 5; 215 uint8_t ibhr_por_en : 1; 216 uint8_t sdo_pu_en : 1; 217 uint8_t ois_pu_dis : 1; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t ois_pu_dis : 1; 220 uint8_t sdo_pu_en : 1; 221 uint8_t ibhr_por_en : 1; 222 uint8_t not_used0 : 5; 223 #endif /* DRV_BYTE_ORDER */ 224 } lsm6dsv16x_pin_ctrl_t; 225 226 #define LSM6DSV16X_IF_CFG 0x3U 227 typedef struct 228 { 229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 230 uint8_t i2c_i3c_disable : 1; 231 uint8_t not_used0 : 1; 232 uint8_t sim : 1; 233 uint8_t pp_od : 1; 234 uint8_t h_lactive : 1; 235 uint8_t asf_ctrl : 1; 236 uint8_t shub_pu_en : 1; 237 uint8_t sda_pu_en : 1; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t sda_pu_en : 1; 240 uint8_t shub_pu_en : 1; 241 uint8_t asf_ctrl : 1; 242 uint8_t h_lactive : 1; 243 uint8_t pp_od : 1; 244 uint8_t sim : 1; 245 uint8_t not_used0 : 1; 246 uint8_t i2c_i3c_disable : 1; 247 #endif /* DRV_BYTE_ORDER */ 248 } lsm6dsv16x_if_cfg_t; 249 250 #define LSM6DSV16X_ODR_TRIG_CFG 0x6U 251 typedef struct 252 { 253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 254 uint8_t odr_trig_nodr : 8; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t odr_trig_nodr : 8; 257 #endif /* DRV_BYTE_ORDER */ 258 } lsm6dsv16x_odr_trig_cfg_t; 259 260 #define LSM6DSV16X_FIFO_CTRL1 0x7U 261 typedef struct 262 { 263 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 264 uint8_t wtm : 8; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t wtm : 8; 267 #endif /* DRV_BYTE_ORDER */ 268 } lsm6dsv16x_fifo_ctrl1_t; 269 270 #define LSM6DSV16X_FIFO_CTRL2 0x8U 271 typedef struct 272 { 273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 274 uint8_t xl_dualc_batch_from_fsm : 1; 275 uint8_t uncompr_rate : 2; 276 uint8_t not_used0 : 1; 277 uint8_t odr_chg_en : 1; 278 uint8_t not_used1 : 1; 279 uint8_t fifo_compr_rt_en : 1; 280 uint8_t stop_on_wtm : 1; 281 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 282 uint8_t stop_on_wtm : 1; 283 uint8_t fifo_compr_rt_en : 1; 284 uint8_t not_used1 : 1; 285 uint8_t odr_chg_en : 1; 286 uint8_t not_used0 : 1; 287 uint8_t uncompr_rate : 2; 288 uint8_t xl_dualc_batch_from_fsm : 1; 289 #endif /* DRV_BYTE_ORDER */ 290 } lsm6dsv16x_fifo_ctrl2_t; 291 292 #define LSM6DSV16X_FIFO_CTRL3 0x9U 293 typedef struct 294 { 295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 296 uint8_t bdr_xl : 4; 297 uint8_t bdr_gy : 4; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t bdr_gy : 4; 300 uint8_t bdr_xl : 4; 301 #endif /* DRV_BYTE_ORDER */ 302 } lsm6dsv16x_fifo_ctrl3_t; 303 304 #define LSM6DSV16X_FIFO_CTRL4 0x0AU 305 typedef struct 306 { 307 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 308 uint8_t fifo_mode : 3; 309 uint8_t g_eis_fifo_en : 1; 310 uint8_t odr_t_batch : 2; 311 uint8_t dec_ts_batch : 2; 312 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 313 uint8_t dec_ts_batch : 2; 314 uint8_t odr_t_batch : 2; 315 uint8_t g_eis_fifo_en : 1; 316 uint8_t fifo_mode : 3; 317 #endif /* DRV_BYTE_ORDER */ 318 } lsm6dsv16x_fifo_ctrl4_t; 319 320 #define LSM6DSV16X_COUNTER_BDR_REG1 0x0BU 321 typedef struct 322 { 323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 324 uint8_t cnt_bdr_th : 2; 325 uint8_t not_used0 : 3; 326 uint8_t trig_counter_bdr : 2; 327 uint8_t not_used1 : 1; 328 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 329 uint8_t not_used1 : 1; 330 uint8_t trig_counter_bdr : 2; 331 uint8_t not_used0 : 3; 332 uint8_t cnt_bdr_th : 2; 333 #endif /* DRV_BYTE_ORDER */ 334 } lsm6dsv16x_counter_bdr_reg1_t; 335 336 #define LSM6DSV16X_COUNTER_BDR_REG2 0x0CU 337 typedef struct 338 { 339 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 340 uint8_t cnt_bdr_th : 8; 341 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 342 uint8_t cnt_bdr_th : 8; 343 #endif /* DRV_BYTE_ORDER */ 344 } lsm6dsv16x_counter_bdr_reg2_t; 345 346 #define LSM6DSV16X_INT1_CTRL 0x0DU 347 typedef struct 348 { 349 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 350 uint8_t int1_drdy_xl : 1; 351 uint8_t int1_drdy_g : 1; 352 uint8_t not_used0 : 1; 353 uint8_t int1_fifo_th : 1; 354 uint8_t int1_fifo_ovr : 1; 355 uint8_t int1_fifo_full : 1; 356 uint8_t int1_cnt_bdr : 1; 357 uint8_t not_used1 : 1; 358 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 359 uint8_t not_used1 : 1; 360 uint8_t int1_cnt_bdr : 1; 361 uint8_t int1_fifo_full : 1; 362 uint8_t int1_fifo_ovr : 1; 363 uint8_t int1_fifo_th : 1; 364 uint8_t not_used0 : 1; 365 uint8_t int1_drdy_g : 1; 366 uint8_t int1_drdy_xl : 1; 367 #endif /* DRV_BYTE_ORDER */ 368 } lsm6dsv16x_int1_ctrl_t; 369 370 #define LSM6DSV16X_INT2_CTRL 0x0EU 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t int2_drdy_xl : 1; 375 uint8_t int2_drdy_g : 1; 376 uint8_t int2_drdy_g_eis : 1; 377 uint8_t int2_fifo_th : 1; 378 uint8_t int2_fifo_ovr : 1; 379 uint8_t int2_fifo_full : 1; 380 uint8_t int2_cnt_bdr : 1; 381 uint8_t int2_emb_func_endop : 1; 382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 383 uint8_t int2_emb_func_endop : 1; 384 uint8_t int2_cnt_bdr : 1; 385 uint8_t int2_fifo_full : 1; 386 uint8_t int2_fifo_ovr : 1; 387 uint8_t int2_fifo_th : 1; 388 uint8_t int2_drdy_g_eis : 1; 389 uint8_t int2_drdy_g : 1; 390 uint8_t int2_drdy_xl : 1; 391 #endif /* DRV_BYTE_ORDER */ 392 } lsm6dsv16x_int2_ctrl_t; 393 394 #define LSM6DSV16X_WHO_AM_I 0x0FU 395 typedef struct 396 { 397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 398 uint8_t id : 8; 399 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 400 uint8_t id : 8; 401 #endif /* DRV_BYTE_ORDER */ 402 } lsm6dsv16x_who_am_i_t; 403 404 #define LSM6DSV16X_CTRL1 0x10U 405 typedef struct 406 { 407 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 408 uint8_t odr_xl : 4; 409 uint8_t op_mode_xl : 3; 410 uint8_t not_used0 : 1; 411 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 412 uint8_t not_used0 : 1; 413 uint8_t op_mode_xl : 3; 414 uint8_t odr_xl : 4; 415 #endif /* DRV_BYTE_ORDER */ 416 } lsm6dsv16x_ctrl1_t; 417 418 #define LSM6DSV16X_CTRL2 0x11U 419 typedef struct 420 { 421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 422 uint8_t odr_g : 4; 423 uint8_t op_mode_g : 3; 424 uint8_t not_used0 : 1; 425 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 426 uint8_t not_used0 : 1; 427 uint8_t op_mode_g : 3; 428 uint8_t odr_g : 4; 429 #endif /* DRV_BYTE_ORDER */ 430 } lsm6dsv16x_ctrl2_t; 431 432 #define LSM6DSV16X_CTRL3 0x12U 433 typedef struct 434 { 435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 436 uint8_t sw_reset : 1; 437 uint8_t not_used0 : 1; 438 uint8_t if_inc : 1; 439 uint8_t not_used1 : 3; 440 uint8_t bdu : 1; 441 uint8_t boot : 1; 442 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 443 uint8_t boot : 1; 444 uint8_t bdu : 1; 445 uint8_t not_used1 : 3; 446 uint8_t if_inc : 1; 447 uint8_t not_used0 : 1; 448 uint8_t sw_reset : 1; 449 #endif /* DRV_BYTE_ORDER */ 450 } lsm6dsv16x_ctrl3_t; 451 452 #define LSM6DSV16X_CTRL4 0x13U 453 typedef struct 454 { 455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 456 uint8_t int2_in_lh : 1; 457 uint8_t drdy_pulsed : 1; 458 uint8_t int2_drdy_temp : 1; 459 uint8_t drdy_mask : 1; 460 uint8_t int2_on_int1 : 1; 461 uint8_t not_used0 : 3; 462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 463 uint8_t not_used0 : 3; 464 uint8_t int2_on_int1 : 1; 465 uint8_t drdy_mask : 1; 466 uint8_t int2_drdy_temp : 1; 467 uint8_t drdy_pulsed : 1; 468 uint8_t int2_in_lh : 1; 469 #endif /* DRV_BYTE_ORDER */ 470 } lsm6dsv16x_ctrl4_t; 471 472 #define LSM6DSV16X_CTRL5 0x14U 473 typedef struct 474 { 475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 476 uint8_t int_en_i3c : 1; 477 uint8_t bus_act_sel : 2; 478 uint8_t not_used0 : 5; 479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 480 uint8_t not_used0 : 5; 481 uint8_t bus_act_sel : 2; 482 uint8_t int_en_i3c : 1; 483 #endif /* DRV_BYTE_ORDER */ 484 } lsm6dsv16x_ctrl5_t; 485 486 #define LSM6DSV16X_CTRL6 0x15U 487 typedef struct 488 { 489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 490 uint8_t fs_g : 4; 491 uint8_t lpf1_g_bw : 3; 492 uint8_t not_used0 : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t not_used0 : 1; 495 uint8_t lpf1_g_bw : 3; 496 uint8_t fs_g : 4; 497 #endif /* DRV_BYTE_ORDER */ 498 } lsm6dsv16x_ctrl6_t; 499 500 #define LSM6DSV16X_CTRL7 0x16U 501 typedef struct 502 { 503 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 504 uint8_t lpf1_g_en : 1; 505 uint8_t not_used0 : 3; 506 uint8_t ah_qvar_c_zin : 2; 507 uint8_t int2_drdy_ah_qvar : 1; 508 uint8_t ah_qvar_en : 1; 509 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 510 uint8_t ah_qvar_en : 1; 511 uint8_t int2_drdy_ah_qvar : 1; 512 uint8_t ah_qvar_c_zin : 2; 513 uint8_t not_used0 : 3; 514 uint8_t lpf1_g_en : 1; 515 #endif /* DRV_BYTE_ORDER */ 516 } lsm6dsv16x_ctrl7_t; 517 518 #define LSM6DSV16X_CTRL8 0x17U 519 typedef struct 520 { 521 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 522 uint8_t fs_xl : 2; 523 uint8_t not_used0 : 1; 524 uint8_t xl_dualc_en : 1; 525 uint8_t not_used1 : 1; 526 uint8_t hp_lpf2_xl_bw : 3; 527 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 528 uint8_t hp_lpf2_xl_bw : 3; 529 uint8_t not_used1 : 1; 530 uint8_t xl_dualc_en : 1; 531 uint8_t not_used0 : 1; 532 uint8_t fs_xl : 2; 533 #endif /* DRV_BYTE_ORDER */ 534 } lsm6dsv16x_ctrl8_t; 535 536 #define LSM6DSV16X_CTRL9 0x18U 537 typedef struct 538 { 539 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 540 uint8_t usr_off_on_out : 1; 541 uint8_t usr_off_w : 1; 542 uint8_t not_used0 : 1; 543 uint8_t lpf2_xl_en : 1; 544 uint8_t hp_slope_xl_en : 1; 545 uint8_t xl_fastsettl_mode : 1; 546 uint8_t hp_ref_mode_xl : 1; 547 uint8_t not_used1 : 1; 548 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 549 uint8_t not_used1 : 1; 550 uint8_t hp_ref_mode_xl : 1; 551 uint8_t xl_fastsettl_mode : 1; 552 uint8_t hp_slope_xl_en : 1; 553 uint8_t lpf2_xl_en : 1; 554 uint8_t not_used0 : 1; 555 uint8_t usr_off_w : 1; 556 uint8_t usr_off_on_out : 1; 557 #endif /* DRV_BYTE_ORDER */ 558 } lsm6dsv16x_ctrl9_t; 559 560 #define LSM6DSV16X_CTRL10 0x19U 561 typedef struct 562 { 563 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 564 uint8_t st_xl : 2; 565 uint8_t st_g : 2; 566 uint8_t not_used0 : 2; 567 uint8_t emb_func_debug : 1; 568 uint8_t not_used1 : 1; 569 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 570 uint8_t not_used1 : 1; 571 uint8_t emb_func_debug : 1; 572 uint8_t not_used0 : 2; 573 uint8_t st_g : 2; 574 uint8_t st_xl : 2; 575 #endif /* DRV_BYTE_ORDER */ 576 } lsm6dsv16x_ctrl10_t; 577 578 #define LSM6DSV16X_CTRL_STATUS 0x1AU 579 typedef struct 580 { 581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 582 uint8_t not_used0 : 2; 583 uint8_t fsm_wr_ctrl_status : 1; 584 uint8_t not_used1 : 5; 585 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 586 uint8_t not_used1 : 5; 587 uint8_t fsm_wr_ctrl_status : 1; 588 uint8_t not_used0 : 2; 589 #endif /* DRV_BYTE_ORDER */ 590 } lsm6dsv16x_ctrl_status_t; 591 592 #define LSM6DSV16X_FIFO_STATUS1 0x1BU 593 typedef struct 594 { 595 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 596 uint8_t diff_fifo : 8; 597 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 598 uint8_t diff_fifo : 8; 599 #endif /* DRV_BYTE_ORDER */ 600 } lsm6dsv16x_fifo_status1_t; 601 602 #define LSM6DSV16X_FIFO_STATUS2 0x1CU 603 typedef struct 604 { 605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 606 uint8_t diff_fifo : 1; 607 uint8_t not_used0 : 2; 608 uint8_t fifo_ovr_latched : 1; 609 uint8_t counter_bdr_ia : 1; 610 uint8_t fifo_full_ia : 1; 611 uint8_t fifo_ovr_ia : 1; 612 uint8_t fifo_wtm_ia : 1; 613 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 614 uint8_t fifo_wtm_ia : 1; 615 uint8_t fifo_ovr_ia : 1; 616 uint8_t fifo_full_ia : 1; 617 uint8_t counter_bdr_ia : 1; 618 uint8_t fifo_ovr_latched : 1; 619 uint8_t not_used0 : 2; 620 uint8_t diff_fifo : 1; 621 #endif /* DRV_BYTE_ORDER */ 622 } lsm6dsv16x_fifo_status2_t; 623 624 #define LSM6DSV16X_ALL_INT_SRC 0x1DU 625 typedef struct 626 { 627 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 628 uint8_t ff_ia : 1; 629 uint8_t wu_ia : 1; 630 uint8_t tap_ia : 1; 631 uint8_t not_used0 : 1; 632 uint8_t d6d_ia : 1; 633 uint8_t sleep_change_ia : 1; 634 uint8_t shub_ia : 1; 635 uint8_t emb_func_ia : 1; 636 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 637 uint8_t emb_func_ia : 1; 638 uint8_t shub_ia : 1; 639 uint8_t sleep_change_ia : 1; 640 uint8_t d6d_ia : 1; 641 uint8_t not_used0 : 1; 642 uint8_t tap_ia : 1; 643 uint8_t wu_ia : 1; 644 uint8_t ff_ia : 1; 645 #endif /* DRV_BYTE_ORDER */ 646 } lsm6dsv16x_all_int_src_t; 647 648 #define LSM6DSV16X_STATUS_REG 0x1EU 649 typedef struct 650 { 651 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 652 uint8_t xlda : 1; 653 uint8_t gda : 1; 654 uint8_t tda : 1; 655 uint8_t ah_qvarda : 1; 656 uint8_t gda_eis : 1; 657 uint8_t ois_drdy : 1; 658 uint8_t not_used0 : 1; 659 uint8_t timestamp_endcount : 1; 660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 661 uint8_t timestamp_endcount : 1; 662 uint8_t not_used0 : 1; 663 uint8_t ois_drdy : 1; 664 uint8_t gda_eis : 1; 665 uint8_t ah_qvarda : 1; 666 uint8_t tda : 1; 667 uint8_t gda : 1; 668 uint8_t xlda : 1; 669 #endif /* DRV_BYTE_ORDER */ 670 } lsm6dsv16x_status_reg_t; 671 672 #define LSM6DSV16X_OUT_TEMP_L 0x20U 673 typedef struct 674 { 675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 676 uint8_t temp : 8; 677 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 678 uint8_t temp : 8; 679 #endif /* DRV_BYTE_ORDER */ 680 } lsm6dsv16x_out_temp_l_t; 681 682 #define LSM6DSV16X_OUT_TEMP_H 0x21U 683 typedef struct 684 { 685 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 686 uint8_t temp : 8; 687 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 688 uint8_t temp : 8; 689 #endif /* DRV_BYTE_ORDER */ 690 } lsm6dsv16x_out_temp_h_t; 691 692 #define LSM6DSV16X_OUTX_L_G 0x22U 693 typedef struct 694 { 695 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 696 uint8_t outx_g : 8; 697 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 698 uint8_t outx_g : 8; 699 #endif /* DRV_BYTE_ORDER */ 700 } lsm6dsv16x_outx_l_g_t; 701 702 #define LSM6DSV16X_OUTX_H_G 0x23U 703 typedef struct 704 { 705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 706 uint8_t outx_g : 8; 707 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 708 uint8_t outx_g : 8; 709 #endif /* DRV_BYTE_ORDER */ 710 } lsm6dsv16x_outx_h_g_t; 711 712 #define LSM6DSV16X_OUTY_L_G 0x24U 713 typedef struct 714 { 715 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 716 uint8_t outy_g : 8; 717 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 718 uint8_t outy_g : 8; 719 #endif /* DRV_BYTE_ORDER */ 720 } lsm6dsv16x_outy_l_g_t; 721 722 #define LSM6DSV16X_OUTY_H_G 0x25U 723 typedef struct 724 { 725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 726 uint8_t outy_g : 8; 727 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 728 uint8_t outy_g : 8; 729 #endif /* DRV_BYTE_ORDER */ 730 } lsm6dsv16x_outy_h_g_t; 731 732 #define LSM6DSV16X_OUTZ_L_G 0x26U 733 typedef struct 734 { 735 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 736 uint8_t outz_g : 8; 737 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 738 uint8_t outz_g : 8; 739 #endif /* DRV_BYTE_ORDER */ 740 } lsm6dsv16x_outz_l_g_t; 741 742 #define LSM6DSV16X_OUTZ_H_G 0x27U 743 typedef struct 744 { 745 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 746 uint8_t outz_g : 8; 747 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 748 uint8_t outz_g : 8; 749 #endif /* DRV_BYTE_ORDER */ 750 } lsm6dsv16x_outz_h_g_t; 751 752 #define LSM6DSV16X_OUTX_L_A 0x28U 753 typedef struct 754 { 755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 756 uint8_t outx_a : 8; 757 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 758 uint8_t outx_a : 8; 759 #endif /* DRV_BYTE_ORDER */ 760 } lsm6dsv16x_outx_l_a_t; 761 762 #define LSM6DSV16X_OUTX_H_A 0x29U 763 typedef struct 764 { 765 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 766 uint8_t outx_a : 8; 767 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 768 uint8_t outx_a : 8; 769 #endif /* DRV_BYTE_ORDER */ 770 } lsm6dsv16x_outx_h_a_t; 771 772 #define LSM6DSV16X_OUTY_L_A 0x2AU 773 typedef struct 774 { 775 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 776 uint8_t outy_a : 8; 777 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 778 uint8_t outy_a : 8; 779 #endif /* DRV_BYTE_ORDER */ 780 } lsm6dsv16x_outy_l_a_t; 781 782 #define LSM6DSV16X_OUTY_H_A 0x2BU 783 typedef struct 784 { 785 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 786 uint8_t outy_a : 8; 787 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 788 uint8_t outy_a : 8; 789 #endif /* DRV_BYTE_ORDER */ 790 } lsm6dsv16x_outy_h_a_t; 791 792 #define LSM6DSV16X_OUTZ_L_A 0x2CU 793 typedef struct 794 { 795 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 796 uint8_t outz_a : 8; 797 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 798 uint8_t outz_a : 8; 799 #endif /* DRV_BYTE_ORDER */ 800 } lsm6dsv16x_outz_l_a_t; 801 802 #define LSM6DSV16X_OUTZ_H_A 0x2DU 803 typedef struct 804 { 805 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 806 uint8_t outz_a : 8; 807 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 808 uint8_t outz_a : 8; 809 #endif /* DRV_BYTE_ORDER */ 810 } lsm6dsv16x_outz_h_a_t; 811 812 #define LSM6DSV16X_UI_OUTX_L_G_OIS_EIS 0x2EU 813 typedef struct 814 { 815 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 816 uint8_t ui_outx_g_ois_eis : 8; 817 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 818 uint8_t ui_outx_g_ois_eis : 8; 819 #endif /* DRV_BYTE_ORDER */ 820 } lsm6dsv16x_ui_outx_l_g_ois_eis_t; 821 822 #define LSM6DSV16X_UI_OUTX_H_G_OIS_EIS 0x2FU 823 typedef struct 824 { 825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 826 uint8_t ui_outx_g_ois_eis : 8; 827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 828 uint8_t ui_outx_g_ois_eis : 8; 829 #endif /* DRV_BYTE_ORDER */ 830 } lsm6dsv16x_ui_outx_h_g_ois_eis_t; 831 832 #define LSM6DSV16X_UI_OUTY_L_G_OIS_EIS 0x30U 833 typedef struct 834 { 835 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 836 uint8_t ui_outy_g_ois_eis : 8; 837 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 838 uint8_t ui_outy_g_ois_eis : 8; 839 #endif /* DRV_BYTE_ORDER */ 840 } lsm6dsv16x_ui_outy_l_g_ois_eis_t; 841 842 #define LSM6DSV16X_UI_OUTY_H_G_OIS_EIS 0x31U 843 typedef struct 844 { 845 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 846 uint8_t ui_outy_g_ois_eis : 8; 847 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 848 uint8_t ui_outy_g_ois_eis : 8; 849 #endif /* DRV_BYTE_ORDER */ 850 } lsm6dsv16x_ui_outy_h_g_ois_eis_t; 851 852 #define LSM6DSV16X_UI_OUTZ_L_G_OIS_EIS 0x32U 853 typedef struct 854 { 855 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 856 uint8_t ui_outz_g_ois_eis : 8; 857 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 858 uint8_t ui_outz_g_ois_eis : 8; 859 #endif /* DRV_BYTE_ORDER */ 860 } lsm6dsv16x_ui_outz_l_g_ois_eis_t; 861 862 #define LSM6DSV16X_UI_OUTZ_H_G_OIS_EIS 0x33U 863 typedef struct 864 { 865 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 866 uint8_t ui_outz_g_ois_eis : 8; 867 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 868 uint8_t ui_outz_g_ois_eis : 8; 869 #endif /* DRV_BYTE_ORDER */ 870 } lsm6dsv16x_ui_outz_h_g_ois_eis_t; 871 872 #define LSM6DSV16X_UI_OUTX_L_A_OIS_DUALC 0x34U 873 typedef struct 874 { 875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 876 uint8_t ui_outx_a_ois_dualc : 8; 877 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 878 uint8_t ui_outx_a_ois_dualc : 8; 879 #endif /* DRV_BYTE_ORDER */ 880 } lsm6dsv16x_ui_outx_l_a_ois_dualc_t; 881 882 #define LSM6DSV16X_UI_OUTX_H_A_OIS_DUALC 0x35U 883 typedef struct 884 { 885 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 886 uint8_t ui_outx_a_ois_dualc : 8; 887 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 888 uint8_t ui_outx_a_ois_dualc : 8; 889 #endif /* DRV_BYTE_ORDER */ 890 } lsm6dsv16x_ui_outx_h_a_ois_dualc_t; 891 892 #define LSM6DSV16X_UI_OUTY_L_A_OIS_DUALC 0x36U 893 typedef struct 894 { 895 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 896 uint8_t ui_outy_a_ois_dualc : 8; 897 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 898 uint8_t ui_outy_a_ois_dualc : 8; 899 #endif /* DRV_BYTE_ORDER */ 900 } lsm6dsv16x_ui_outy_l_a_ois_dualc_t; 901 902 #define LSM6DSV16X_UI_OUTY_H_A_OIS_DUALC 0x37U 903 typedef struct 904 { 905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 906 uint8_t ui_outy_a_ois_dualc : 8; 907 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 908 uint8_t ui_outy_a_ois_dualc : 8; 909 #endif /* DRV_BYTE_ORDER */ 910 } lsm6dsv16x_ui_outy_h_a_ois_dualc_t; 911 912 #define LSM6DSV16X_UI_OUTZ_L_A_OIS_DUALC 0x38U 913 typedef struct 914 { 915 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 916 uint8_t ui_outz_a_ois_dualc : 8; 917 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 918 uint8_t ui_outz_a_ois_dualc : 8; 919 #endif /* DRV_BYTE_ORDER */ 920 } lsm6dsv16x_ui_outz_l_a_ois_dualc_t; 921 922 #define LSM6DSV16X_UI_OUTZ_H_A_OIS_DUALC 0x39U 923 typedef struct 924 { 925 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 926 uint8_t ui_outz_a_ois_dualc : 8; 927 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 928 uint8_t ui_outz_a_ois_dualc : 8; 929 #endif /* DRV_BYTE_ORDER */ 930 } lsm6dsv16x_ui_outz_h_a_ois_dualc_t; 931 932 #define LSM6DSV16X_AH_QVAR_OUT_L 0x3AU 933 typedef struct 934 { 935 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 936 uint8_t ah_qvar : 8; 937 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 938 uint8_t ah_qvar : 8; 939 #endif /* DRV_BYTE_ORDER */ 940 } lsm6dsv16x_ah_qvar_out_l_t; 941 942 #define LSM6DSV16X_AH_QVAR_OUT_H 0x3BU 943 typedef struct 944 { 945 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 946 uint8_t ah_qvar : 8; 947 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 948 uint8_t ah_qvar : 8; 949 #endif /* DRV_BYTE_ORDER */ 950 } lsm6dsv16x_ah_qvar_out_h_t; 951 952 #define LSM6DSV16X_TIMESTAMP0 0x40U 953 typedef struct 954 { 955 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 956 uint8_t timestamp : 8; 957 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 958 uint8_t timestamp : 8; 959 #endif /* DRV_BYTE_ORDER */ 960 } lsm6dsv16x_timestamp0_t; 961 962 #define LSM6DSV16X_TIMESTAMP1 0x41U 963 typedef struct 964 { 965 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 966 uint8_t timestamp : 8; 967 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 968 uint8_t timestamp : 8; 969 #endif /* DRV_BYTE_ORDER */ 970 } lsm6dsv16x_timestamp1_t; 971 972 #define LSM6DSV16X_TIMESTAMP2 0x42U 973 typedef struct 974 { 975 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 976 uint8_t timestamp : 8; 977 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 978 uint8_t timestamp : 8; 979 #endif /* DRV_BYTE_ORDER */ 980 } lsm6dsv16x_timestamp2_t; 981 982 #define LSM6DSV16X_TIMESTAMP3 0x43U 983 typedef struct 984 { 985 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 986 uint8_t timestamp : 8; 987 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 988 uint8_t timestamp : 8; 989 #endif /* DRV_BYTE_ORDER */ 990 } lsm6dsv16x_timestamp3_t; 991 992 #define LSM6DSV16X_UI_STATUS_REG_OIS 0x44U 993 typedef struct 994 { 995 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 996 uint8_t xlda_ois : 1; 997 uint8_t gda_ois : 1; 998 uint8_t gyro_settling : 1; 999 uint8_t not_used0 : 5; 1000 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1001 uint8_t not_used0 : 5; 1002 uint8_t gyro_settling : 1; 1003 uint8_t gda_ois : 1; 1004 uint8_t xlda_ois : 1; 1005 #endif /* DRV_BYTE_ORDER */ 1006 } lsm6dsv16x_ui_status_reg_ois_t; 1007 1008 #define LSM6DSV16X_WAKE_UP_SRC 0x45U 1009 typedef struct 1010 { 1011 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1012 uint8_t z_wu : 1; 1013 uint8_t y_wu : 1; 1014 uint8_t x_wu : 1; 1015 uint8_t wu_ia : 1; 1016 uint8_t sleep_state : 1; 1017 uint8_t ff_ia : 1; 1018 uint8_t sleep_change_ia : 1; 1019 uint8_t not_used0 : 1; 1020 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1021 uint8_t not_used0 : 1; 1022 uint8_t sleep_change_ia : 1; 1023 uint8_t ff_ia : 1; 1024 uint8_t sleep_state : 1; 1025 uint8_t wu_ia : 1; 1026 uint8_t x_wu : 1; 1027 uint8_t y_wu : 1; 1028 uint8_t z_wu : 1; 1029 #endif /* DRV_BYTE_ORDER */ 1030 } lsm6dsv16x_wake_up_src_t; 1031 1032 #define LSM6DSV16X_TAP_SRC 0x46U 1033 typedef struct 1034 { 1035 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1036 uint8_t z_tap : 1; 1037 uint8_t y_tap : 1; 1038 uint8_t x_tap : 1; 1039 uint8_t tap_sign : 1; 1040 uint8_t double_tap : 1; 1041 uint8_t single_tap : 1; 1042 uint8_t tap_ia : 1; 1043 uint8_t not_used0 : 1; 1044 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1045 uint8_t not_used0 : 1; 1046 uint8_t tap_ia : 1; 1047 uint8_t single_tap : 1; 1048 uint8_t double_tap : 1; 1049 uint8_t tap_sign : 1; 1050 uint8_t x_tap : 1; 1051 uint8_t y_tap : 1; 1052 uint8_t z_tap : 1; 1053 #endif /* DRV_BYTE_ORDER */ 1054 } lsm6dsv16x_tap_src_t; 1055 1056 #define LSM6DSV16X_D6D_SRC 0x47U 1057 typedef struct 1058 { 1059 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1060 uint8_t xl : 1; 1061 uint8_t xh : 1; 1062 uint8_t yl : 1; 1063 uint8_t yh : 1; 1064 uint8_t zl : 1; 1065 uint8_t zh : 1; 1066 uint8_t d6d_ia : 1; 1067 uint8_t not_used0 : 1; 1068 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1069 uint8_t not_used0 : 1; 1070 uint8_t d6d_ia : 1; 1071 uint8_t zh : 1; 1072 uint8_t zl : 1; 1073 uint8_t yh : 1; 1074 uint8_t yl : 1; 1075 uint8_t xh : 1; 1076 uint8_t xl : 1; 1077 #endif /* DRV_BYTE_ORDER */ 1078 } lsm6dsv16x_d6d_src_t; 1079 1080 #define LSM6DSV16X_STATUS_MASTER_MAINPAGE 0x48U 1081 typedef struct 1082 { 1083 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1084 uint8_t sens_hub_endop : 1; 1085 uint8_t not_used0 : 2; 1086 uint8_t slave0_nack : 1; 1087 uint8_t slave1_nack : 1; 1088 uint8_t slave2_nack : 1; 1089 uint8_t slave3_nack : 1; 1090 uint8_t wr_once_done : 1; 1091 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1092 uint8_t wr_once_done : 1; 1093 uint8_t slave3_nack : 1; 1094 uint8_t slave2_nack : 1; 1095 uint8_t slave1_nack : 1; 1096 uint8_t slave0_nack : 1; 1097 uint8_t not_used0 : 2; 1098 uint8_t sens_hub_endop : 1; 1099 #endif /* DRV_BYTE_ORDER */ 1100 } lsm6dsv16x_status_master_mainpage_t; 1101 1102 #define LSM6DSV16X_EMB_FUNC_STATUS_MAINPAGE 0x49U 1103 typedef struct 1104 { 1105 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1106 uint8_t not_used0 : 3; 1107 uint8_t is_step_det : 1; 1108 uint8_t is_tilt : 1; 1109 uint8_t is_sigmot : 1; 1110 uint8_t not_used1 : 1; 1111 uint8_t is_fsm_lc : 1; 1112 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1113 uint8_t is_fsm_lc : 1; 1114 uint8_t not_used1 : 1; 1115 uint8_t is_sigmot : 1; 1116 uint8_t is_tilt : 1; 1117 uint8_t is_step_det : 1; 1118 uint8_t not_used0 : 3; 1119 #endif /* DRV_BYTE_ORDER */ 1120 } lsm6dsv16x_emb_func_status_mainpage_t; 1121 1122 #define LSM6DSV16X_FSM_STATUS_MAINPAGE 0x4AU 1123 typedef struct 1124 { 1125 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1126 uint8_t is_fsm1 : 1; 1127 uint8_t is_fsm2 : 1; 1128 uint8_t is_fsm3 : 1; 1129 uint8_t is_fsm4 : 1; 1130 uint8_t is_fsm5 : 1; 1131 uint8_t is_fsm6 : 1; 1132 uint8_t is_fsm7 : 1; 1133 uint8_t is_fsm8 : 1; 1134 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1135 uint8_t is_fsm8 : 1; 1136 uint8_t is_fsm7 : 1; 1137 uint8_t is_fsm6 : 1; 1138 uint8_t is_fsm5 : 1; 1139 uint8_t is_fsm4 : 1; 1140 uint8_t is_fsm3 : 1; 1141 uint8_t is_fsm2 : 1; 1142 uint8_t is_fsm1 : 1; 1143 #endif /* DRV_BYTE_ORDER */ 1144 } lsm6dsv16x_fsm_status_mainpage_t; 1145 1146 #define LSM6DSV16X_MLC_STATUS_MAINPAGE 0x4BU 1147 typedef struct 1148 { 1149 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1150 uint8_t is_mlc1 : 1; 1151 uint8_t is_mlc2 : 1; 1152 uint8_t is_mlc3 : 1; 1153 uint8_t is_mlc4 : 1; 1154 uint8_t not_used0 : 4; 1155 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1156 uint8_t not_used0 : 4; 1157 uint8_t is_mlc4 : 1; 1158 uint8_t is_mlc3 : 1; 1159 uint8_t is_mlc2 : 1; 1160 uint8_t is_mlc1 : 1; 1161 #endif /* DRV_BYTE_ORDER */ 1162 } lsm6dsv16x_mlc_status_mainpage_t; 1163 1164 #define LSM6DSV16X_INTERNAL_FREQ 0x4FU 1165 typedef struct 1166 { 1167 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1168 uint8_t freq_fine : 8; 1169 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1170 uint8_t freq_fine : 8; 1171 #endif /* DRV_BYTE_ORDER */ 1172 } lsm6dsv16x_internal_freq_t; 1173 1174 #define LSM6DSV16X_FUNCTIONS_ENABLE 0x50U 1175 typedef struct 1176 { 1177 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1178 uint8_t inact_en : 2; 1179 uint8_t not_used0 : 1; 1180 uint8_t dis_rst_lir_all_int : 1; 1181 uint8_t not_used1 : 2; 1182 uint8_t timestamp_en : 1; 1183 uint8_t interrupts_enable : 1; 1184 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1185 uint8_t interrupts_enable : 1; 1186 uint8_t timestamp_en : 1; 1187 uint8_t not_used1 : 2; 1188 uint8_t dis_rst_lir_all_int : 1; 1189 uint8_t not_used0 : 1; 1190 uint8_t inact_en : 2; 1191 #endif /* DRV_BYTE_ORDER */ 1192 } lsm6dsv16x_functions_enable_t; 1193 1194 #define LSM6DSV16X_DEN 0x51U 1195 typedef struct 1196 { 1197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1198 uint8_t den_xl_g : 1; 1199 uint8_t den_z : 1; 1200 uint8_t den_y : 1; 1201 uint8_t den_x : 1; 1202 uint8_t den_xl_en : 1; 1203 uint8_t lvl2_en : 1; 1204 uint8_t lvl1_en : 1; 1205 uint8_t not_used0 : 1; 1206 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1207 uint8_t not_used0 : 1; 1208 uint8_t lvl1_en : 1; 1209 uint8_t lvl2_en : 1; 1210 uint8_t den_xl_en : 1; 1211 uint8_t den_x : 1; 1212 uint8_t den_y : 1; 1213 uint8_t den_z : 1; 1214 uint8_t den_xl_g : 1; 1215 #endif /* DRV_BYTE_ORDER */ 1216 } lsm6dsv16x_den_t; 1217 1218 #define LSM6DSV16X_INACTIVITY_DUR 0x54U 1219 typedef struct 1220 { 1221 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1222 uint8_t inact_dur : 2; 1223 uint8_t xl_inact_odr : 2; 1224 uint8_t wu_inact_ths_w : 3; 1225 uint8_t sleep_status_on_int : 1; 1226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1227 uint8_t sleep_status_on_int : 1; 1228 uint8_t wu_inact_ths_w : 3; 1229 uint8_t xl_inact_odr : 2; 1230 uint8_t inact_dur : 2; 1231 #endif /* DRV_BYTE_ORDER */ 1232 } lsm6dsv16x_inactivity_dur_t; 1233 1234 #define LSM6DSV16X_INACTIVITY_THS 0x55U 1235 typedef struct 1236 { 1237 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1238 uint8_t inact_ths : 6; 1239 uint8_t not_used0 : 2; 1240 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1241 uint8_t not_used0 : 2; 1242 uint8_t inact_ths : 6; 1243 #endif /* DRV_BYTE_ORDER */ 1244 } lsm6dsv16x_inactivity_ths_t; 1245 1246 #define LSM6DSV16X_TAP_CFG0 0x56U 1247 typedef struct 1248 { 1249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1250 uint8_t lir : 1; 1251 uint8_t tap_z_en : 1; 1252 uint8_t tap_y_en : 1; 1253 uint8_t tap_x_en : 1; 1254 uint8_t slope_fds : 1; 1255 uint8_t hw_func_mask_xl_settl : 1; 1256 uint8_t low_pass_on_6d : 1; 1257 uint8_t not_used1 : 1; 1258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1259 uint8_t not_used1 : 1; 1260 uint8_t low_pass_on_6d : 1; 1261 uint8_t hw_func_mask_xl_settl : 1; 1262 uint8_t slope_fds : 1; 1263 uint8_t tap_x_en : 1; 1264 uint8_t tap_y_en : 1; 1265 uint8_t tap_z_en : 1; 1266 uint8_t lir : 1; 1267 #endif /* DRV_BYTE_ORDER */ 1268 } lsm6dsv16x_tap_cfg0_t; 1269 1270 #define LSM6DSV16X_TAP_CFG1 0x57U 1271 typedef struct 1272 { 1273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1274 uint8_t tap_ths_x : 5; 1275 uint8_t tap_priority : 3; 1276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1277 uint8_t tap_priority : 3; 1278 uint8_t tap_ths_x : 5; 1279 #endif /* DRV_BYTE_ORDER */ 1280 } lsm6dsv16x_tap_cfg1_t; 1281 1282 #define LSM6DSV16X_TAP_CFG2 0x58U 1283 typedef struct 1284 { 1285 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1286 uint8_t tap_ths_y : 5; 1287 uint8_t not_used0 : 3; 1288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1289 uint8_t not_used0 : 3; 1290 uint8_t tap_ths_y : 5; 1291 #endif /* DRV_BYTE_ORDER */ 1292 } lsm6dsv16x_tap_cfg2_t; 1293 1294 #define LSM6DSV16X_TAP_THS_6D 0x59U 1295 typedef struct 1296 { 1297 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1298 uint8_t tap_ths_z : 5; 1299 uint8_t sixd_ths : 2; 1300 uint8_t d4d_en : 1; 1301 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1302 uint8_t d4d_en : 1; 1303 uint8_t sixd_ths : 2; 1304 uint8_t tap_ths_z : 5; 1305 #endif /* DRV_BYTE_ORDER */ 1306 } lsm6dsv16x_tap_ths_6d_t; 1307 1308 #define LSM6DSV16X_TAP_DUR 0x5AU 1309 typedef struct 1310 { 1311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1312 uint8_t shock : 2; 1313 uint8_t quiet : 2; 1314 uint8_t dur : 4; 1315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1316 uint8_t dur : 4; 1317 uint8_t quiet : 2; 1318 uint8_t shock : 2; 1319 #endif /* DRV_BYTE_ORDER */ 1320 } lsm6dsv16x_tap_dur_t; 1321 1322 #define LSM6DSV16X_WAKE_UP_THS 0x5BU 1323 typedef struct 1324 { 1325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1326 uint8_t wk_ths : 6; 1327 uint8_t usr_off_on_wu : 1; 1328 uint8_t single_double_tap : 1; 1329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1330 uint8_t single_double_tap : 1; 1331 uint8_t usr_off_on_wu : 1; 1332 uint8_t wk_ths : 6; 1333 #endif /* DRV_BYTE_ORDER */ 1334 } lsm6dsv16x_wake_up_ths_t; 1335 1336 #define LSM6DSV16X_WAKE_UP_DUR 0x5CU 1337 typedef struct 1338 { 1339 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1340 uint8_t sleep_dur : 4; 1341 uint8_t not_used0 : 1; 1342 uint8_t wake_dur : 2; 1343 uint8_t ff_dur : 1; 1344 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1345 uint8_t ff_dur : 1; 1346 uint8_t wake_dur : 2; 1347 uint8_t not_used0 : 1; 1348 uint8_t sleep_dur : 4; 1349 #endif /* DRV_BYTE_ORDER */ 1350 } lsm6dsv16x_wake_up_dur_t; 1351 1352 #define LSM6DSV16X_FREE_FALL 0x5DU 1353 typedef struct 1354 { 1355 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1356 uint8_t ff_ths : 3; 1357 uint8_t ff_dur : 5; 1358 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1359 uint8_t ff_dur : 5; 1360 uint8_t ff_ths : 3; 1361 #endif /* DRV_BYTE_ORDER */ 1362 } lsm6dsv16x_free_fall_t; 1363 1364 #define LSM6DSV16X_MD1_CFG 0x5EU 1365 typedef struct 1366 { 1367 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1368 uint8_t int1_shub : 1; 1369 uint8_t int1_emb_func : 1; 1370 uint8_t int1_6d : 1; 1371 uint8_t int1_double_tap : 1; 1372 uint8_t int1_ff : 1; 1373 uint8_t int1_wu : 1; 1374 uint8_t int1_single_tap : 1; 1375 uint8_t int1_sleep_change : 1; 1376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1377 uint8_t int1_sleep_change : 1; 1378 uint8_t int1_single_tap : 1; 1379 uint8_t int1_wu : 1; 1380 uint8_t int1_ff : 1; 1381 uint8_t int1_double_tap : 1; 1382 uint8_t int1_6d : 1; 1383 uint8_t int1_emb_func : 1; 1384 uint8_t int1_shub : 1; 1385 #endif /* DRV_BYTE_ORDER */ 1386 } lsm6dsv16x_md1_cfg_t; 1387 1388 #define LSM6DSV16X_MD2_CFG 0x5FU 1389 typedef struct 1390 { 1391 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1392 uint8_t int2_timestamp : 1; 1393 uint8_t int2_emb_func : 1; 1394 uint8_t int2_6d : 1; 1395 uint8_t int2_double_tap : 1; 1396 uint8_t int2_ff : 1; 1397 uint8_t int2_wu : 1; 1398 uint8_t int2_single_tap : 1; 1399 uint8_t int2_sleep_change : 1; 1400 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1401 uint8_t int2_sleep_change : 1; 1402 uint8_t int2_single_tap : 1; 1403 uint8_t int2_wu : 1; 1404 uint8_t int2_ff : 1; 1405 uint8_t int2_double_tap : 1; 1406 uint8_t int2_6d : 1; 1407 uint8_t int2_emb_func : 1; 1408 uint8_t int2_timestamp : 1; 1409 #endif /* DRV_BYTE_ORDER */ 1410 } lsm6dsv16x_md2_cfg_t; 1411 1412 #define LSM6DSV16X_HAODR_CFG 0x62U 1413 typedef struct 1414 { 1415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1416 uint8_t haodr_sel : 2; 1417 uint8_t not_used0 : 6; 1418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1419 uint8_t not_used0 : 6; 1420 uint8_t haodr_sel : 2; 1421 #endif /* DRV_BYTE_ORDER */ 1422 } lsm6dsv16x_haodr_cfg_t; 1423 1424 #define LSM6DSV16X_EMB_FUNC_CFG 0x63U 1425 typedef struct 1426 { 1427 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1428 uint8_t not_used0 : 3; 1429 uint8_t emb_func_disable : 1; 1430 uint8_t emb_func_irq_mask_xl_settl : 1; 1431 uint8_t emb_func_irq_mask_g_settl : 1; 1432 uint8_t not_used1 : 2; 1433 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1434 uint8_t not_used1 : 2; 1435 uint8_t emb_func_irq_mask_g_settl : 1; 1436 uint8_t emb_func_irq_mask_xl_settl : 1; 1437 uint8_t emb_func_disable : 1; 1438 uint8_t not_used0 : 3; 1439 #endif /* DRV_BYTE_ORDER */ 1440 } lsm6dsv16x_emb_func_cfg_t; 1441 1442 #define LSM6DSV16X_UI_HANDSHAKE_CTRL 0x64U 1443 typedef struct 1444 { 1445 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1446 uint8_t ui_shared_req : 1; 1447 uint8_t ui_shared_ack : 1; 1448 uint8_t not_used0 : 6; 1449 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1450 uint8_t not_used0 : 6; 1451 uint8_t ui_shared_ack : 1; 1452 uint8_t ui_shared_req : 1; 1453 #endif /* DRV_BYTE_ORDER */ 1454 } lsm6dsv16x_ui_handshake_ctrl_t; 1455 1456 #define LSM6DSV16X_UI_SPI2_SHARED_0 0x65U 1457 typedef struct 1458 { 1459 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1460 uint8_t ui_spi2_shared : 8; 1461 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1462 uint8_t ui_spi2_shared : 8; 1463 #endif /* DRV_BYTE_ORDER */ 1464 } lsm6dsv16x_ui_spi2_shared_0_t; 1465 1466 #define LSM6DSV16X_UI_SPI2_SHARED_1 0x66U 1467 typedef struct 1468 { 1469 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1470 uint8_t ui_spi2_shared : 8; 1471 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1472 uint8_t ui_spi2_shared : 8; 1473 #endif /* DRV_BYTE_ORDER */ 1474 } lsm6dsv16x_ui_spi2_shared_1_t; 1475 1476 #define LSM6DSV16X_UI_SPI2_SHARED_2 0x67U 1477 typedef struct 1478 { 1479 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1480 uint8_t ui_spi2_shared : 8; 1481 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1482 uint8_t ui_spi2_shared : 8; 1483 #endif /* DRV_BYTE_ORDER */ 1484 } lsm6dsv16x_ui_spi2_shared_2_t; 1485 1486 #define LSM6DSV16X_UI_SPI2_SHARED_3 0x68U 1487 typedef struct 1488 { 1489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1490 uint8_t ui_spi2_shared : 8; 1491 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1492 uint8_t ui_spi2_shared : 8; 1493 #endif /* DRV_BYTE_ORDER */ 1494 } lsm6dsv16x_ui_spi2_shared_3_t; 1495 1496 #define LSM6DSV16X_UI_SPI2_SHARED_4 0x69U 1497 typedef struct 1498 { 1499 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1500 uint8_t ui_spi2_shared : 8; 1501 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1502 uint8_t ui_spi2_shared : 8; 1503 #endif /* DRV_BYTE_ORDER */ 1504 } lsm6dsv16x_ui_spi2_shared_4_t; 1505 1506 #define LSM6DSV16X_UI_SPI2_SHARED_5 0x6AU 1507 typedef struct 1508 { 1509 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1510 uint8_t ui_spi2_shared : 8; 1511 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1512 uint8_t ui_spi2_shared : 8; 1513 #endif /* DRV_BYTE_ORDER */ 1514 } lsm6dsv16x_ui_spi2_shared_5_t; 1515 1516 #define LSM6DSV16X_CTRL_EIS 0x6BU 1517 typedef struct 1518 { 1519 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1520 uint8_t fs_g_eis : 3; 1521 uint8_t g_eis_on_g_ois_out_reg : 1; 1522 uint8_t lpf_g_eis_bw : 1; 1523 uint8_t not_used0 : 1; 1524 uint8_t odr_g_eis : 2; 1525 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1526 uint8_t odr_g_eis : 2; 1527 uint8_t not_used0 : 1; 1528 uint8_t lpf_g_eis_bw : 1; 1529 uint8_t g_eis_on_g_ois_out_reg : 1; 1530 uint8_t fs_g_eis : 3; 1531 #endif /* DRV_BYTE_ORDER */ 1532 } lsm6dsv16x_ctrl_eis_t; 1533 1534 #define LSM6DSV16X_UI_INT_OIS 0x6FU 1535 typedef struct 1536 { 1537 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1538 uint8_t not_used0 : 4; 1539 uint8_t st_ois_clampdis : 1; 1540 uint8_t not_used1 : 1; 1541 uint8_t drdy_mask_ois : 1; 1542 uint8_t int2_drdy_ois : 1; 1543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1544 uint8_t int2_drdy_ois : 1; 1545 uint8_t drdy_mask_ois : 1; 1546 uint8_t not_used1 : 1; 1547 uint8_t st_ois_clampdis : 1; 1548 uint8_t not_used0 : 4; 1549 #endif /* DRV_BYTE_ORDER */ 1550 } lsm6dsv16x_ui_int_ois_t; 1551 1552 #define LSM6DSV16X_UI_CTRL1_OIS 0x70U 1553 typedef struct 1554 { 1555 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1556 uint8_t spi2_read_en : 1; 1557 uint8_t ois_g_en : 1; 1558 uint8_t ois_xl_en : 1; 1559 uint8_t not_used0 : 2; 1560 uint8_t sim_ois : 1; 1561 uint8_t not_used1 : 2; 1562 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1563 uint8_t not_used1 : 2; 1564 uint8_t sim_ois : 1; 1565 uint8_t not_used0 : 2; 1566 uint8_t ois_xl_en : 1; 1567 uint8_t ois_g_en : 1; 1568 uint8_t spi2_read_en : 1; 1569 #endif /* DRV_BYTE_ORDER */ 1570 } lsm6dsv16x_ui_ctrl1_ois_t; 1571 1572 #define LSM6DSV16X_UI_CTRL2_OIS 0x71U 1573 typedef struct 1574 { 1575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1576 uint8_t fs_g_ois : 3; 1577 uint8_t lpf1_g_ois_bw : 2; 1578 uint8_t not_used0 : 3; 1579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1580 uint8_t not_used0 : 3; 1581 uint8_t lpf1_g_ois_bw : 2; 1582 uint8_t fs_g_ois : 3; 1583 #endif /* DRV_BYTE_ORDER */ 1584 } lsm6dsv16x_ui_ctrl2_ois_t; 1585 1586 #define LSM6DSV16X_UI_CTRL3_OIS 0x72U 1587 typedef struct 1588 { 1589 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1590 uint8_t fs_xl_ois : 2; 1591 uint8_t not_used0 : 1; 1592 uint8_t lpf_xl_ois_bw : 3; 1593 uint8_t not_used1 : 2; 1594 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1595 uint8_t not_used1 : 2; 1596 uint8_t lpf_xl_ois_bw : 3; 1597 uint8_t not_used0 : 1; 1598 uint8_t fs_xl_ois : 2; 1599 #endif /* DRV_BYTE_ORDER */ 1600 } lsm6dsv16x_ui_ctrl3_ois_t; 1601 1602 #define LSM6DSV16X_X_OFS_USR 0x73U 1603 typedef struct 1604 { 1605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1606 uint8_t x_ofs_usr : 8; 1607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1608 uint8_t x_ofs_usr : 8; 1609 #endif /* DRV_BYTE_ORDER */ 1610 } lsm6dsv16x_x_ofs_usr_t; 1611 1612 #define LSM6DSV16X_Y_OFS_USR 0x74U 1613 typedef struct 1614 { 1615 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1616 uint8_t y_ofs_usr : 8; 1617 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1618 uint8_t y_ofs_usr : 8; 1619 #endif /* DRV_BYTE_ORDER */ 1620 } lsm6dsv16x_y_ofs_usr_t; 1621 1622 #define LSM6DSV16X_Z_OFS_USR 0x75U 1623 typedef struct 1624 { 1625 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1626 uint8_t z_ofs_usr : 8; 1627 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1628 uint8_t z_ofs_usr : 8; 1629 #endif /* DRV_BYTE_ORDER */ 1630 } lsm6dsv16x_z_ofs_usr_t; 1631 1632 #define LSM6DSV16X_FIFO_DATA_OUT_TAG 0x78U 1633 typedef struct 1634 { 1635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1636 uint8_t not_used0 : 1; 1637 uint8_t tag_cnt : 2; 1638 uint8_t tag_sensor : 5; 1639 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1640 uint8_t tag_sensor : 5; 1641 uint8_t tag_cnt : 2; 1642 uint8_t not_used0 : 1; 1643 #endif /* DRV_BYTE_ORDER */ 1644 } lsm6dsv16x_fifo_data_out_tag_t; 1645 1646 #define LSM6DSV16X_FIFO_DATA_OUT_X_L 0x79U 1647 typedef struct 1648 { 1649 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1650 uint8_t fifo_data_out : 8; 1651 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1652 uint8_t fifo_data_out : 8; 1653 #endif /* DRV_BYTE_ORDER */ 1654 } lsm6dsv16x_fifo_data_out_x_l_t; 1655 1656 #define LSM6DSV16X_FIFO_DATA_OUT_X_H 0x7AU 1657 typedef struct 1658 { 1659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1660 uint8_t fifo_data_out : 8; 1661 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1662 uint8_t fifo_data_out : 8; 1663 #endif /* DRV_BYTE_ORDER */ 1664 } lsm6dsv16x_fifo_data_out_x_h_t; 1665 1666 #define LSM6DSV16X_FIFO_DATA_OUT_Y_L 0x7BU 1667 typedef struct 1668 { 1669 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1670 uint8_t fifo_data_out : 8; 1671 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1672 uint8_t fifo_data_out : 8; 1673 #endif /* DRV_BYTE_ORDER */ 1674 } lsm6dsv16x_fifo_data_out_y_l_t; 1675 1676 #define LSM6DSV16X_FIFO_DATA_OUT_Y_H 0x7CU 1677 typedef struct 1678 { 1679 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1680 uint8_t fifo_data_out : 8; 1681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1682 uint8_t fifo_data_out : 8; 1683 #endif /* DRV_BYTE_ORDER */ 1684 } lsm6dsv16x_fifo_data_out_y_h_t; 1685 1686 #define LSM6DSV16X_FIFO_DATA_OUT_Z_L 0x7DU 1687 typedef struct 1688 { 1689 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1690 uint8_t fifo_data_out : 8; 1691 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1692 uint8_t fifo_data_out : 8; 1693 #endif /* DRV_BYTE_ORDER */ 1694 } lsm6dsv16x_fifo_data_out_z_l_t; 1695 1696 #define LSM6DSV16X_FIFO_DATA_OUT_Z_H 0x7EU 1697 typedef struct 1698 { 1699 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1700 uint8_t fifo_data_out : 8; 1701 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1702 uint8_t fifo_data_out : 8; 1703 #endif /* DRV_BYTE_ORDER */ 1704 } lsm6dsv16x_fifo_data_out_z_h_t; 1705 1706 /** 1707 * @} 1708 * 1709 */ 1710 1711 /** @defgroup bitfields page spi2 1712 * @{ 1713 * 1714 */ 1715 1716 #define LSM6DSV16X_SPI2_WHO_AM_I 0x0FU 1717 typedef struct 1718 { 1719 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1720 uint8_t id : 8; 1721 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1722 uint8_t id : 8; 1723 #endif /* DRV_BYTE_ORDER */ 1724 } lsm6dsv16x_spi2_who_am_i_t; 1725 1726 #define LSM6DSV16X_SPI2_STATUS_REG_OIS 0x1EU 1727 typedef struct 1728 { 1729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1730 uint8_t xlda : 1; 1731 uint8_t gda : 1; 1732 uint8_t gyro_settling : 1; 1733 uint8_t not_used0 : 5; 1734 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1735 uint8_t not_used0 : 5; 1736 uint8_t gyro_settling : 1; 1737 uint8_t gda : 1; 1738 uint8_t xlda : 1; 1739 #endif /* DRV_BYTE_ORDER */ 1740 } lsm6dsv16x_spi2_status_reg_ois_t; 1741 1742 #define LSM6DSV16X_SPI2_OUT_TEMP_L 0x20U 1743 typedef struct 1744 { 1745 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1746 uint8_t temp : 8; 1747 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1748 uint8_t temp : 8; 1749 #endif /* DRV_BYTE_ORDER */ 1750 } lsm6dsv16x_spi2_out_temp_l_t; 1751 1752 #define LSM6DSV16X_SPI2_OUT_TEMP_H 0x21U 1753 typedef struct 1754 { 1755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1756 uint8_t temp : 8; 1757 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1758 uint8_t temp : 8; 1759 #endif /* DRV_BYTE_ORDER */ 1760 } lsm6dsv16x_spi2_out_temp_h_t; 1761 1762 #define LSM6DSV16X_SPI2_OUTX_L_G_OIS 0x22U 1763 typedef struct 1764 { 1765 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1766 uint8_t spi2_outx_g_ois : 8; 1767 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1768 uint8_t spi2_outx_g_ois : 8; 1769 #endif /* DRV_BYTE_ORDER */ 1770 } lsm6dsv16x_spi2_outx_l_g_ois_t; 1771 1772 #define LSM6DSV16X_SPI2_OUTX_H_G_OIS 0x23U 1773 typedef struct 1774 { 1775 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1776 uint8_t spi2_outx_g_ois : 8; 1777 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1778 uint8_t spi2_outx_g_ois : 8; 1779 #endif /* DRV_BYTE_ORDER */ 1780 } lsm6dsv16x_spi2_outx_h_g_ois_t; 1781 1782 #define LSM6DSV16X_SPI2_OUTY_L_G_OIS 0x24U 1783 typedef struct 1784 { 1785 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1786 uint8_t spi2_outy_g_ois : 8; 1787 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1788 uint8_t spi2_outy_g_ois : 8; 1789 #endif /* DRV_BYTE_ORDER */ 1790 } lsm6dsv16x_spi2_outy_l_g_ois_t; 1791 1792 #define LSM6DSV16X_SPI2_OUTY_H_G_OIS 0x25U 1793 typedef struct 1794 { 1795 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1796 uint8_t spi2_outy_g_ois : 8; 1797 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1798 uint8_t spi2_outy_g_ois : 8; 1799 #endif /* DRV_BYTE_ORDER */ 1800 } lsm6dsv16x_spi2_outy_h_g_ois_t; 1801 1802 #define LSM6DSV16X_SPI2_OUTZ_L_G_OIS 0x26U 1803 typedef struct 1804 { 1805 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1806 uint8_t spi2_outz_g_ois : 8; 1807 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1808 uint8_t spi2_outz_g_ois : 8; 1809 #endif /* DRV_BYTE_ORDER */ 1810 } lsm6dsv16x_spi2_outz_l_g_ois_t; 1811 1812 #define LSM6DSV16X_SPI2_OUTZ_H_G_OIS 0x27U 1813 typedef struct 1814 { 1815 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1816 uint8_t spi2_outz_g_ois : 8; 1817 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1818 uint8_t spi2_outz_g_ois : 8; 1819 #endif /* DRV_BYTE_ORDER */ 1820 } lsm6dsv16x_spi2_outz_h_g_ois_t; 1821 1822 #define LSM6DSV16X_SPI2_OUTX_L_A_OIS 0x28U 1823 typedef struct 1824 { 1825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1826 uint8_t spi2_outx_a_ois : 8; 1827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1828 uint8_t spi2_outx_a_ois : 8; 1829 #endif /* DRV_BYTE_ORDER */ 1830 } lsm6dsv16x_spi2_outx_l_a_ois_t; 1831 1832 #define LSM6DSV16X_SPI2_OUTX_H_A_OIS 0x29U 1833 typedef struct 1834 { 1835 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1836 uint8_t spi2_outx_a_ois : 8; 1837 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1838 uint8_t spi2_outx_a_ois : 8; 1839 #endif /* DRV_BYTE_ORDER */ 1840 } lsm6dsv16x_spi2_outx_h_a_ois_t; 1841 1842 #define LSM6DSV16X_SPI2_OUTY_L_A_OIS 0x2AU 1843 typedef struct 1844 { 1845 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1846 uint8_t spi2_outy_a_ois : 8; 1847 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1848 uint8_t spi2_outy_a_ois : 8; 1849 #endif /* DRV_BYTE_ORDER */ 1850 } lsm6dsv16x_spi2_outy_l_a_ois_t; 1851 1852 #define LSM6DSV16X_SPI2_OUTY_H_A_OIS 0x2BU 1853 typedef struct 1854 { 1855 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1856 uint8_t spi2_outy_a_ois : 8; 1857 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1858 uint8_t spi2_outy_a_ois : 8; 1859 #endif /* DRV_BYTE_ORDER */ 1860 } lsm6dsv16x_spi2_outy_h_a_ois_t; 1861 1862 #define LSM6DSV16X_SPI2_OUTZ_L_A_OIS 0x2CU 1863 typedef struct 1864 { 1865 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1866 uint8_t spi2_outz_a_ois : 8; 1867 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1868 uint8_t spi2_outz_a_ois : 8; 1869 #endif /* DRV_BYTE_ORDER */ 1870 } lsm6dsv16x_spi2_outz_l_a_ois_t; 1871 1872 #define LSM6DSV16X_SPI2_OUTZ_H_A_OIS 0x2DU 1873 typedef struct 1874 { 1875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1876 uint8_t spi2_outz_a_ois : 8; 1877 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1878 uint8_t spi2_outz_a_ois : 8; 1879 #endif /* DRV_BYTE_ORDER */ 1880 } lsm6dsv16x_spi2_outz_h_a_ois_t; 1881 1882 #define LSM6DSV16X_SPI2_HANDSHAKE_CTRL 0x6EU 1883 typedef struct 1884 { 1885 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1886 uint8_t spi2_shared_ack : 1; 1887 uint8_t spi2_shared_req : 1; 1888 uint8_t not_used0 : 6; 1889 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1890 uint8_t not_used0 : 6; 1891 uint8_t spi2_shared_req : 1; 1892 uint8_t spi2_shared_ack : 1; 1893 #endif /* DRV_BYTE_ORDER */ 1894 } lsm6dsv16x_spi2_handshake_ctrl_t; 1895 1896 #define LSM6DSV16X_SPI2_INT_OIS 0x6FU 1897 typedef struct 1898 { 1899 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1900 uint8_t st_xl_ois : 2; 1901 uint8_t st_g_ois : 2; 1902 uint8_t st_ois_clampdis : 1; 1903 uint8_t not_used0 : 1; 1904 uint8_t drdy_mask_ois : 1; 1905 uint8_t int2_drdy_ois : 1; 1906 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1907 uint8_t int2_drdy_ois : 1; 1908 uint8_t drdy_mask_ois : 1; 1909 uint8_t not_used0 : 1; 1910 uint8_t st_ois_clampdis : 1; 1911 uint8_t st_g_ois : 2; 1912 uint8_t st_xl_ois : 2; 1913 #endif /* DRV_BYTE_ORDER */ 1914 } lsm6dsv16x_spi2_int_ois_t; 1915 1916 #define LSM6DSV16X_SPI2_CTRL1_OIS 0x70U 1917 typedef struct 1918 { 1919 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1920 uint8_t spi2_read_en : 1; 1921 uint8_t ois_g_en : 1; 1922 uint8_t ois_xl_en : 1; 1923 uint8_t not_used0 : 2; 1924 uint8_t sim_ois : 1; 1925 uint8_t not_used1 : 2; 1926 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1927 uint8_t not_used1 : 2; 1928 uint8_t sim_ois : 1; 1929 uint8_t not_used0 : 2; 1930 uint8_t ois_xl_en : 1; 1931 uint8_t ois_g_en : 1; 1932 uint8_t spi2_read_en : 1; 1933 #endif /* DRV_BYTE_ORDER */ 1934 } lsm6dsv16x_spi2_ctrl1_ois_t; 1935 1936 #define LSM6DSV16X_SPI2_CTRL2_OIS 0x71U 1937 typedef struct 1938 { 1939 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1940 uint8_t fs_g_ois : 3; 1941 uint8_t lpf1_g_ois_bw : 2; 1942 uint8_t not_used0 : 3; 1943 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1944 uint8_t not_used0 : 3; 1945 uint8_t lpf1_g_ois_bw : 2; 1946 uint8_t fs_g_ois : 3; 1947 #endif /* DRV_BYTE_ORDER */ 1948 } lsm6dsv16x_spi2_ctrl2_ois_t; 1949 1950 #define LSM6DSV16X_SPI2_CTRL3_OIS 0x72U 1951 typedef struct 1952 { 1953 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1954 uint8_t fs_xl_ois : 2; 1955 uint8_t not_used0 : 1; 1956 uint8_t lpf_xl_ois_bw : 3; 1957 uint8_t not_used1 : 2; 1958 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1959 uint8_t not_used1 : 2; 1960 uint8_t lpf_xl_ois_bw : 3; 1961 uint8_t not_used0 : 1; 1962 uint8_t fs_xl_ois : 2; 1963 #endif /* DRV_BYTE_ORDER */ 1964 } lsm6dsv16x_spi2_ctrl3_ois_t; 1965 1966 /** 1967 * @} 1968 * 1969 */ 1970 1971 /** @defgroup bitfields page embedded 1972 * @{ 1973 * 1974 */ 1975 1976 #define LSM6DSV16X_PAGE_SEL 0x2U 1977 typedef struct 1978 { 1979 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1980 uint8_t not_used0 : 4; 1981 uint8_t page_sel : 4; 1982 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1983 uint8_t page_sel : 4; 1984 uint8_t not_used0 : 4; 1985 #endif /* DRV_BYTE_ORDER */ 1986 } lsm6dsv16x_page_sel_t; 1987 1988 #define LSM6DSV16X_EMB_FUNC_EN_A 0x4U 1989 typedef struct 1990 { 1991 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1992 uint8_t not_used0 : 1; 1993 uint8_t sflp_game_en : 1; 1994 uint8_t not_used2 : 1; 1995 uint8_t pedo_en : 1; 1996 uint8_t tilt_en : 1; 1997 uint8_t sign_motion_en : 1; 1998 uint8_t not_used1 : 1; 1999 uint8_t mlc_before_fsm_en : 1; 2000 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2001 uint8_t mlc_before_fsm_en : 1; 2002 uint8_t not_used1 : 1; 2003 uint8_t sign_motion_en : 1; 2004 uint8_t tilt_en : 1; 2005 uint8_t pedo_en : 1; 2006 uint8_t not_used2 : 1; 2007 uint8_t sflp_game_en : 1; 2008 uint8_t not_used0 : 1; 2009 #endif /* DRV_BYTE_ORDER */ 2010 } lsm6dsv16x_emb_func_en_a_t; 2011 2012 #define LSM6DSV16X_EMB_FUNC_EN_B 0x5U 2013 typedef struct 2014 { 2015 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2016 uint8_t fsm_en : 1; 2017 uint8_t not_used0 : 2; 2018 uint8_t fifo_compr_en : 1; 2019 uint8_t mlc_en : 1; 2020 uint8_t not_used1 : 3; 2021 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2022 uint8_t not_used1 : 3; 2023 uint8_t mlc_en : 1; 2024 uint8_t fifo_compr_en : 1; 2025 uint8_t not_used0 : 2; 2026 uint8_t fsm_en : 1; 2027 #endif /* DRV_BYTE_ORDER */ 2028 } lsm6dsv16x_emb_func_en_b_t; 2029 2030 #define LSM6DSV16X_EMB_FUNC_EXEC_STATUS 0x7U 2031 typedef struct 2032 { 2033 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2034 uint8_t emb_func_endop : 1; 2035 uint8_t emb_func_exec_ovr : 1; 2036 uint8_t not_used0 : 6; 2037 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2038 uint8_t not_used0 : 6; 2039 uint8_t emb_func_exec_ovr : 1; 2040 uint8_t emb_func_endop : 1; 2041 #endif /* DRV_BYTE_ORDER */ 2042 } lsm6dsv16x_emb_func_exec_status_t; 2043 2044 #define LSM6DSV16X_PAGE_ADDRESS 0x8U 2045 typedef struct 2046 { 2047 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2048 uint8_t page_addr : 8; 2049 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2050 uint8_t page_addr : 8; 2051 #endif /* DRV_BYTE_ORDER */ 2052 } lsm6dsv16x_page_address_t; 2053 2054 #define LSM6DSV16X_PAGE_VALUE 0x9U 2055 typedef struct 2056 { 2057 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2058 uint8_t page_value : 8; 2059 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2060 uint8_t page_value : 8; 2061 #endif /* DRV_BYTE_ORDER */ 2062 } lsm6dsv16x_page_value_t; 2063 2064 #define LSM6DSV16X_EMB_FUNC_INT1 0x0AU 2065 typedef struct 2066 { 2067 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2068 uint8_t not_used0 : 3; 2069 uint8_t int1_step_detector : 1; 2070 uint8_t int1_tilt : 1; 2071 uint8_t int1_sig_mot : 1; 2072 uint8_t not_used1 : 1; 2073 uint8_t int1_fsm_lc : 1; 2074 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2075 uint8_t int1_fsm_lc : 1; 2076 uint8_t not_used1 : 1; 2077 uint8_t int1_sig_mot : 1; 2078 uint8_t int1_tilt : 1; 2079 uint8_t int1_step_detector : 1; 2080 uint8_t not_used0 : 3; 2081 #endif /* DRV_BYTE_ORDER */ 2082 } lsm6dsv16x_emb_func_int1_t; 2083 2084 #define LSM6DSV16X_FSM_INT1 0x0BU 2085 typedef struct 2086 { 2087 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2088 uint8_t int1_fsm1 : 1; 2089 uint8_t int1_fsm2 : 1; 2090 uint8_t int1_fsm3 : 1; 2091 uint8_t int1_fsm4 : 1; 2092 uint8_t int1_fsm5 : 1; 2093 uint8_t int1_fsm6 : 1; 2094 uint8_t int1_fsm7 : 1; 2095 uint8_t int1_fsm8 : 1; 2096 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2097 uint8_t int1_fsm8 : 1; 2098 uint8_t int1_fsm7 : 1; 2099 uint8_t int1_fsm6 : 1; 2100 uint8_t int1_fsm5 : 1; 2101 uint8_t int1_fsm4 : 1; 2102 uint8_t int1_fsm3 : 1; 2103 uint8_t int1_fsm2 : 1; 2104 uint8_t int1_fsm1 : 1; 2105 #endif /* DRV_BYTE_ORDER */ 2106 } lsm6dsv16x_fsm_int1_t; 2107 2108 #define LSM6DSV16X_MLC_INT1 0x0DU 2109 typedef struct 2110 { 2111 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2112 uint8_t int1_mlc1 : 1; 2113 uint8_t int1_mlc2 : 1; 2114 uint8_t int1_mlc3 : 1; 2115 uint8_t int1_mlc4 : 1; 2116 uint8_t not_used0 : 4; 2117 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2118 uint8_t not_used0 : 4; 2119 uint8_t int1_mlc4 : 1; 2120 uint8_t int1_mlc3 : 1; 2121 uint8_t int1_mlc2 : 1; 2122 uint8_t int1_mlc1 : 1; 2123 #endif /* DRV_BYTE_ORDER */ 2124 } lsm6dsv16x_mlc_int1_t; 2125 2126 #define LSM6DSV16X_EMB_FUNC_INT2 0x0EU 2127 typedef struct 2128 { 2129 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2130 uint8_t not_used0 : 3; 2131 uint8_t int2_step_detector : 1; 2132 uint8_t int2_tilt : 1; 2133 uint8_t int2_sig_mot : 1; 2134 uint8_t not_used1 : 1; 2135 uint8_t int2_fsm_lc : 1; 2136 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2137 uint8_t int2_fsm_lc : 1; 2138 uint8_t not_used1 : 1; 2139 uint8_t int2_sig_mot : 1; 2140 uint8_t int2_tilt : 1; 2141 uint8_t int2_step_detector : 1; 2142 uint8_t not_used0 : 3; 2143 #endif /* DRV_BYTE_ORDER */ 2144 } lsm6dsv16x_emb_func_int2_t; 2145 2146 #define LSM6DSV16X_FSM_INT2 0x0FU 2147 typedef struct 2148 { 2149 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2150 uint8_t int2_fsm1 : 1; 2151 uint8_t int2_fsm2 : 1; 2152 uint8_t int2_fsm3 : 1; 2153 uint8_t int2_fsm4 : 1; 2154 uint8_t int2_fsm5 : 1; 2155 uint8_t int2_fsm6 : 1; 2156 uint8_t int2_fsm7 : 1; 2157 uint8_t int2_fsm8 : 1; 2158 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2159 uint8_t int2_fsm8 : 1; 2160 uint8_t int2_fsm7 : 1; 2161 uint8_t int2_fsm6 : 1; 2162 uint8_t int2_fsm5 : 1; 2163 uint8_t int2_fsm4 : 1; 2164 uint8_t int2_fsm3 : 1; 2165 uint8_t int2_fsm2 : 1; 2166 uint8_t int2_fsm1 : 1; 2167 #endif /* DRV_BYTE_ORDER */ 2168 } lsm6dsv16x_fsm_int2_t; 2169 2170 #define LSM6DSV16X_MLC_INT2 0x11U 2171 typedef struct 2172 { 2173 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2174 uint8_t int2_mlc1 : 1; 2175 uint8_t int2_mlc2 : 1; 2176 uint8_t int2_mlc3 : 1; 2177 uint8_t int2_mlc4 : 1; 2178 uint8_t not_used0 : 4; 2179 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2180 uint8_t not_used0 : 4; 2181 uint8_t int2_mlc4 : 1; 2182 uint8_t int2_mlc3 : 1; 2183 uint8_t int2_mlc2 : 1; 2184 uint8_t int2_mlc1 : 1; 2185 #endif /* DRV_BYTE_ORDER */ 2186 } lsm6dsv16x_mlc_int2_t; 2187 2188 #define LSM6DSV16X_EMB_FUNC_STATUS 0x12U 2189 typedef struct 2190 { 2191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2192 uint8_t not_used0 : 3; 2193 uint8_t is_step_det : 1; 2194 uint8_t is_tilt : 1; 2195 uint8_t is_sigmot : 1; 2196 uint8_t not_used1 : 1; 2197 uint8_t is_fsm_lc : 1; 2198 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2199 uint8_t is_fsm_lc : 1; 2200 uint8_t not_used1 : 1; 2201 uint8_t is_sigmot : 1; 2202 uint8_t is_tilt : 1; 2203 uint8_t is_step_det : 1; 2204 uint8_t not_used0 : 3; 2205 #endif /* DRV_BYTE_ORDER */ 2206 } lsm6dsv16x_emb_func_status_t; 2207 2208 #define LSM6DSV16X_FSM_STATUS 0x13U 2209 typedef struct 2210 { 2211 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2212 uint8_t is_fsm1 : 1; 2213 uint8_t is_fsm2 : 1; 2214 uint8_t is_fsm3 : 1; 2215 uint8_t is_fsm4 : 1; 2216 uint8_t is_fsm5 : 1; 2217 uint8_t is_fsm6 : 1; 2218 uint8_t is_fsm7 : 1; 2219 uint8_t is_fsm8 : 1; 2220 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2221 uint8_t is_fsm8 : 1; 2222 uint8_t is_fsm7 : 1; 2223 uint8_t is_fsm6 : 1; 2224 uint8_t is_fsm5 : 1; 2225 uint8_t is_fsm4 : 1; 2226 uint8_t is_fsm3 : 1; 2227 uint8_t is_fsm2 : 1; 2228 uint8_t is_fsm1 : 1; 2229 #endif /* DRV_BYTE_ORDER */ 2230 } lsm6dsv16x_fsm_status_t; 2231 2232 #define LSM6DSV16X_MLC_STATUS 0x15U 2233 typedef struct 2234 { 2235 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2236 uint8_t is_mlc1 : 1; 2237 uint8_t is_mlc2 : 1; 2238 uint8_t is_mlc3 : 1; 2239 uint8_t is_mlc4 : 1; 2240 uint8_t not_used0 : 4; 2241 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2242 uint8_t not_used0 : 4; 2243 uint8_t is_mlc4 : 1; 2244 uint8_t is_mlc3 : 1; 2245 uint8_t is_mlc2 : 1; 2246 uint8_t is_mlc1 : 1; 2247 #endif /* DRV_BYTE_ORDER */ 2248 } lsm6dsv16x_mlc_status_t; 2249 2250 #define LSM6DSV16X_PAGE_RW 0x17U 2251 typedef struct 2252 { 2253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2254 uint8_t not_used0 : 5; 2255 uint8_t page_read : 1; 2256 uint8_t page_write : 1; 2257 uint8_t emb_func_lir : 1; 2258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2259 uint8_t emb_func_lir : 1; 2260 uint8_t page_write : 1; 2261 uint8_t page_read : 1; 2262 uint8_t not_used0 : 5; 2263 #endif /* DRV_BYTE_ORDER */ 2264 } lsm6dsv16x_page_rw_t; 2265 2266 #define LSM6DSV16X_EMB_FUNC_FIFO_EN_A 0x44U 2267 typedef struct 2268 { 2269 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2270 uint8_t not_used0 : 1; 2271 uint8_t sflp_game_fifo_en : 1; 2272 uint8_t not_used1 : 2; 2273 uint8_t sflp_gravity_fifo_en : 1; 2274 uint8_t sflp_gbias_fifo_en : 1; 2275 uint8_t step_counter_fifo_en : 1; 2276 uint8_t mlc_fifo_en : 1; 2277 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2278 uint8_t mlc_fifo_en : 1; 2279 uint8_t step_counter_fifo_en : 1; 2280 uint8_t sflp_gbias_fifo_en : 1; 2281 uint8_t sflp_gravity_fifo_en : 1; 2282 uint8_t not_used1 : 2; 2283 uint8_t sflp_game_fifo_en : 1; 2284 uint8_t not_used0 : 1; 2285 #endif /* DRV_BYTE_ORDER */ 2286 } lsm6dsv16x_emb_func_fifo_en_a_t; 2287 2288 #define LSM6DSV16X_EMB_FUNC_FIFO_EN_B 0x45U 2289 typedef struct 2290 { 2291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2292 uint8_t not_used0 : 1; 2293 uint8_t mlc_filter_feature_fifo_en : 1; 2294 uint8_t not_used1 : 6; 2295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2296 uint8_t not_used1 : 6; 2297 uint8_t mlc_filter_feature_fifo_en : 1; 2298 uint8_t not_used0 : 1; 2299 #endif /* DRV_BYTE_ORDER */ 2300 } lsm6dsv16x_emb_func_fifo_en_b_t; 2301 2302 #define LSM6DSV16X_FSM_ENABLE 0x46U 2303 typedef struct 2304 { 2305 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2306 uint8_t fsm1_en : 1; 2307 uint8_t fsm2_en : 1; 2308 uint8_t fsm3_en : 1; 2309 uint8_t fsm4_en : 1; 2310 uint8_t fsm5_en : 1; 2311 uint8_t fsm6_en : 1; 2312 uint8_t fsm7_en : 1; 2313 uint8_t fsm8_en : 1; 2314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2315 uint8_t fsm8_en : 1; 2316 uint8_t fsm7_en : 1; 2317 uint8_t fsm6_en : 1; 2318 uint8_t fsm5_en : 1; 2319 uint8_t fsm4_en : 1; 2320 uint8_t fsm3_en : 1; 2321 uint8_t fsm2_en : 1; 2322 uint8_t fsm1_en : 1; 2323 #endif /* DRV_BYTE_ORDER */ 2324 } lsm6dsv16x_fsm_enable_t; 2325 2326 #define LSM6DSV16X_FSM_LONG_COUNTER_L 0x48U 2327 typedef struct 2328 { 2329 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2330 uint8_t fsm_lc : 8; 2331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2332 uint8_t fsm_lc : 8; 2333 #endif /* DRV_BYTE_ORDER */ 2334 } lsm6dsv16x_fsm_long_counter_l_t; 2335 2336 #define LSM6DSV16X_FSM_LONG_COUNTER_H 0x49U 2337 typedef struct 2338 { 2339 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2340 uint8_t fsm_lc : 8; 2341 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2342 uint8_t fsm_lc : 8; 2343 #endif /* DRV_BYTE_ORDER */ 2344 } lsm6dsv16x_fsm_long_counter_h_t; 2345 2346 #define LSM6DSV16X_INT_ACK_MASK 0x4BU 2347 typedef struct 2348 { 2349 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2350 uint8_t iack_mask : 8; 2351 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2352 uint8_t iack_mask : 8; 2353 #endif /* DRV_BYTE_ORDER */ 2354 } lsm6dsv16x_int_ack_mask_t; 2355 2356 #define LSM6DSV16X_FSM_OUTS1 0x4CU 2357 typedef struct 2358 { 2359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2360 uint8_t fsm1_n_v : 1; 2361 uint8_t fsm1_p_v : 1; 2362 uint8_t fsm1_n_z : 1; 2363 uint8_t fsm1_p_z : 1; 2364 uint8_t fsm1_n_y : 1; 2365 uint8_t fsm1_p_y : 1; 2366 uint8_t fsm1_n_x : 1; 2367 uint8_t fsm1_p_x : 1; 2368 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2369 uint8_t fsm1_p_x : 1; 2370 uint8_t fsm1_n_x : 1; 2371 uint8_t fsm1_p_y : 1; 2372 uint8_t fsm1_n_y : 1; 2373 uint8_t fsm1_p_z : 1; 2374 uint8_t fsm1_n_z : 1; 2375 uint8_t fsm1_p_v : 1; 2376 uint8_t fsm1_n_v : 1; 2377 #endif /* DRV_BYTE_ORDER */ 2378 } lsm6dsv16x_fsm_outs1_t; 2379 2380 #define LSM6DSV16X_FSM_OUTS2 0x4DU 2381 typedef struct 2382 { 2383 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2384 uint8_t fsm2_n_v : 1; 2385 uint8_t fsm2_p_v : 1; 2386 uint8_t fsm2_n_z : 1; 2387 uint8_t fsm2_p_z : 1; 2388 uint8_t fsm2_n_y : 1; 2389 uint8_t fsm2_p_y : 1; 2390 uint8_t fsm2_n_x : 1; 2391 uint8_t fsm2_p_x : 1; 2392 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2393 uint8_t fsm2_p_x : 1; 2394 uint8_t fsm2_n_x : 1; 2395 uint8_t fsm2_p_y : 1; 2396 uint8_t fsm2_n_y : 1; 2397 uint8_t fsm2_p_z : 1; 2398 uint8_t fsm2_n_z : 1; 2399 uint8_t fsm2_p_v : 1; 2400 uint8_t fsm2_n_v : 1; 2401 #endif /* DRV_BYTE_ORDER */ 2402 } lsm6dsv16x_fsm_outs2_t; 2403 2404 #define LSM6DSV16X_FSM_OUTS3 0x4EU 2405 typedef struct 2406 { 2407 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2408 uint8_t fsm3_n_v : 1; 2409 uint8_t fsm3_p_v : 1; 2410 uint8_t fsm3_n_z : 1; 2411 uint8_t fsm3_p_z : 1; 2412 uint8_t fsm3_n_y : 1; 2413 uint8_t fsm3_p_y : 1; 2414 uint8_t fsm3_n_x : 1; 2415 uint8_t fsm3_p_x : 1; 2416 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2417 uint8_t fsm3_p_x : 1; 2418 uint8_t fsm3_n_x : 1; 2419 uint8_t fsm3_p_y : 1; 2420 uint8_t fsm3_n_y : 1; 2421 uint8_t fsm3_p_z : 1; 2422 uint8_t fsm3_n_z : 1; 2423 uint8_t fsm3_p_v : 1; 2424 uint8_t fsm3_n_v : 1; 2425 #endif /* DRV_BYTE_ORDER */ 2426 } lsm6dsv16x_fsm_outs3_t; 2427 2428 #define LSM6DSV16X_FSM_OUTS4 0x4FU 2429 typedef struct 2430 { 2431 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2432 uint8_t fsm4_n_v : 1; 2433 uint8_t fsm4_p_v : 1; 2434 uint8_t fsm4_n_z : 1; 2435 uint8_t fsm4_p_z : 1; 2436 uint8_t fsm4_n_y : 1; 2437 uint8_t fsm4_p_y : 1; 2438 uint8_t fsm4_n_x : 1; 2439 uint8_t fsm4_p_x : 1; 2440 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2441 uint8_t fsm4_p_x : 1; 2442 uint8_t fsm4_n_x : 1; 2443 uint8_t fsm4_p_y : 1; 2444 uint8_t fsm4_n_y : 1; 2445 uint8_t fsm4_p_z : 1; 2446 uint8_t fsm4_n_z : 1; 2447 uint8_t fsm4_p_v : 1; 2448 uint8_t fsm4_n_v : 1; 2449 #endif /* DRV_BYTE_ORDER */ 2450 } lsm6dsv16x_fsm_outs4_t; 2451 2452 #define LSM6DSV16X_FSM_OUTS5 0x50U 2453 typedef struct 2454 { 2455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2456 uint8_t fsm5_n_v : 1; 2457 uint8_t fsm5_p_v : 1; 2458 uint8_t fsm5_n_z : 1; 2459 uint8_t fsm5_p_z : 1; 2460 uint8_t fsm5_n_y : 1; 2461 uint8_t fsm5_p_y : 1; 2462 uint8_t fsm5_n_x : 1; 2463 uint8_t fsm5_p_x : 1; 2464 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2465 uint8_t fsm5_p_x : 1; 2466 uint8_t fsm5_n_x : 1; 2467 uint8_t fsm5_p_y : 1; 2468 uint8_t fsm5_n_y : 1; 2469 uint8_t fsm5_p_z : 1; 2470 uint8_t fsm5_n_z : 1; 2471 uint8_t fsm5_p_v : 1; 2472 uint8_t fsm5_n_v : 1; 2473 #endif /* DRV_BYTE_ORDER */ 2474 } lsm6dsv16x_fsm_outs5_t; 2475 2476 #define LSM6DSV16X_FSM_OUTS6 0x51U 2477 typedef struct 2478 { 2479 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2480 uint8_t fsm6_n_v : 1; 2481 uint8_t fsm6_p_v : 1; 2482 uint8_t fsm6_n_z : 1; 2483 uint8_t fsm6_p_z : 1; 2484 uint8_t fsm6_n_y : 1; 2485 uint8_t fsm6_p_y : 1; 2486 uint8_t fsm6_n_x : 1; 2487 uint8_t fsm6_p_x : 1; 2488 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2489 uint8_t fsm6_p_x : 1; 2490 uint8_t fsm6_n_x : 1; 2491 uint8_t fsm6_p_y : 1; 2492 uint8_t fsm6_n_y : 1; 2493 uint8_t fsm6_p_z : 1; 2494 uint8_t fsm6_n_z : 1; 2495 uint8_t fsm6_p_v : 1; 2496 uint8_t fsm6_n_v : 1; 2497 #endif /* DRV_BYTE_ORDER */ 2498 } lsm6dsv16x_fsm_outs6_t; 2499 2500 #define LSM6DSV16X_FSM_OUTS7 0x52U 2501 typedef struct 2502 { 2503 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2504 uint8_t fsm7_n_v : 1; 2505 uint8_t fsm7_p_v : 1; 2506 uint8_t fsm7_n_z : 1; 2507 uint8_t fsm7_p_z : 1; 2508 uint8_t fsm7_n_y : 1; 2509 uint8_t fsm7_p_y : 1; 2510 uint8_t fsm7_n_x : 1; 2511 uint8_t fsm7_p_x : 1; 2512 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2513 uint8_t fsm7_p_x : 1; 2514 uint8_t fsm7_n_x : 1; 2515 uint8_t fsm7_p_y : 1; 2516 uint8_t fsm7_n_y : 1; 2517 uint8_t fsm7_p_z : 1; 2518 uint8_t fsm7_n_z : 1; 2519 uint8_t fsm7_p_v : 1; 2520 uint8_t fsm7_n_v : 1; 2521 #endif /* DRV_BYTE_ORDER */ 2522 } lsm6dsv16x_fsm_outs7_t; 2523 2524 #define LSM6DSV16X_FSM_OUTS8 0x53U 2525 typedef struct 2526 { 2527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2528 uint8_t fsm8_n_v : 1; 2529 uint8_t fsm8_p_v : 1; 2530 uint8_t fsm8_n_z : 1; 2531 uint8_t fsm8_p_z : 1; 2532 uint8_t fsm8_n_y : 1; 2533 uint8_t fsm8_p_y : 1; 2534 uint8_t fsm8_n_x : 1; 2535 uint8_t fsm8_p_x : 1; 2536 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2537 uint8_t fsm8_p_x : 1; 2538 uint8_t fsm8_n_x : 1; 2539 uint8_t fsm8_p_y : 1; 2540 uint8_t fsm8_n_y : 1; 2541 uint8_t fsm8_p_z : 1; 2542 uint8_t fsm8_n_z : 1; 2543 uint8_t fsm8_p_v : 1; 2544 uint8_t fsm8_n_v : 1; 2545 #endif /* DRV_BYTE_ORDER */ 2546 } lsm6dsv16x_fsm_outs8_t; 2547 2548 #define LSM6DSV16X_SFLP_ODR 0x5EU 2549 typedef struct 2550 { 2551 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2552 uint8_t not_used0 : 3; 2553 uint8_t sflp_game_odr : 3; 2554 uint8_t not_used1 : 2; 2555 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2556 uint8_t not_used1 : 2; 2557 uint8_t sflp_game_odr : 3; 2558 uint8_t not_used0 : 3; 2559 #endif /* DRV_BYTE_ORDER */ 2560 } lsm6dsv16x_sflp_odr_t; 2561 2562 #define LSM6DSV16X_FSM_ODR 0x5FU 2563 typedef struct 2564 { 2565 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2566 uint8_t not_used0 : 3; 2567 uint8_t fsm_odr : 3; 2568 uint8_t not_used1 : 2; 2569 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2570 uint8_t not_used1 : 2; 2571 uint8_t fsm_odr : 3; 2572 uint8_t not_used0 : 3; 2573 #endif /* DRV_BYTE_ORDER */ 2574 } lsm6dsv16x_fsm_odr_t; 2575 2576 #define LSM6DSV16X_MLC_ODR 0x60U 2577 typedef struct 2578 { 2579 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2580 uint8_t not_used0 : 4; 2581 uint8_t mlc_odr : 3; 2582 uint8_t not_used1 : 1; 2583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2584 uint8_t not_used1 : 1; 2585 uint8_t mlc_odr : 3; 2586 uint8_t not_used0 : 4; 2587 #endif /* DRV_BYTE_ORDER */ 2588 } lsm6dsv16x_mlc_odr_t; 2589 2590 #define LSM6DSV16X_STEP_COUNTER_L 0x62U 2591 typedef struct 2592 { 2593 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2594 uint8_t step : 8; 2595 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2596 uint8_t step : 8; 2597 #endif /* DRV_BYTE_ORDER */ 2598 } lsm6dsv16x_step_counter_l_t; 2599 2600 #define LSM6DSV16X_STEP_COUNTER_H 0x63U 2601 typedef struct 2602 { 2603 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2604 uint8_t step : 8; 2605 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2606 uint8_t step : 8; 2607 #endif /* DRV_BYTE_ORDER */ 2608 } lsm6dsv16x_step_counter_h_t; 2609 2610 #define LSM6DSV16X_EMB_FUNC_SRC 0x64U 2611 typedef struct 2612 { 2613 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2614 uint8_t not_used0 : 2; 2615 uint8_t stepcounter_bit_set : 1; 2616 uint8_t step_overflow : 1; 2617 uint8_t step_count_delta_ia : 1; 2618 uint8_t step_detected : 1; 2619 uint8_t not_used1 : 1; 2620 uint8_t pedo_rst_step : 1; 2621 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2622 uint8_t pedo_rst_step : 1; 2623 uint8_t not_used1 : 1; 2624 uint8_t step_detected : 1; 2625 uint8_t step_count_delta_ia : 1; 2626 uint8_t step_overflow : 1; 2627 uint8_t stepcounter_bit_set : 1; 2628 uint8_t not_used0 : 2; 2629 #endif /* DRV_BYTE_ORDER */ 2630 } lsm6dsv16x_emb_func_src_t; 2631 2632 #define LSM6DSV16X_EMB_FUNC_INIT_A 0x66U 2633 typedef struct 2634 { 2635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2636 uint8_t not_used0 : 1; 2637 uint8_t sflp_game_init : 1; 2638 uint8_t not_used2 : 1; 2639 uint8_t step_det_init : 1; 2640 uint8_t tilt_init : 1; 2641 uint8_t sig_mot_init : 1; 2642 uint8_t not_used1 : 1; 2643 uint8_t mlc_before_fsm_init : 1; 2644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2645 uint8_t mlc_before_fsm_init : 1; 2646 uint8_t not_used1 : 1; 2647 uint8_t sig_mot_init : 1; 2648 uint8_t tilt_init : 1; 2649 uint8_t step_det_init : 1; 2650 uint8_t not_used2 : 1; 2651 uint8_t sflp_game_init : 1; 2652 uint8_t not_used0 : 1; 2653 #endif /* DRV_BYTE_ORDER */ 2654 } lsm6dsv16x_emb_func_init_a_t; 2655 2656 #define LSM6DSV16X_EMB_FUNC_INIT_B 0x67U 2657 typedef struct 2658 { 2659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2660 uint8_t fsm_init : 1; 2661 uint8_t not_used0 : 2; 2662 uint8_t fifo_compr_init : 1; 2663 uint8_t mlc_init : 1; 2664 uint8_t not_used1 : 3; 2665 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2666 uint8_t not_used1 : 3; 2667 uint8_t mlc_init : 1; 2668 uint8_t fifo_compr_init : 1; 2669 uint8_t not_used0 : 2; 2670 uint8_t fsm_init : 1; 2671 #endif /* DRV_BYTE_ORDER */ 2672 } lsm6dsv16x_emb_func_init_b_t; 2673 2674 #define LSM6DSV16X_MLC1_SRC 0x70U 2675 typedef struct 2676 { 2677 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2678 uint8_t mlc1_src : 8; 2679 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2680 uint8_t mlc1_src : 8; 2681 #endif /* DRV_BYTE_ORDER */ 2682 } lsm6dsv16x_mlc1_src_t; 2683 2684 #define LSM6DSV16X_MLC2_SRC 0x71U 2685 typedef struct 2686 { 2687 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2688 uint8_t mlc2_src : 8; 2689 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2690 uint8_t mlc2_src : 8; 2691 #endif /* DRV_BYTE_ORDER */ 2692 } lsm6dsv16x_mlc2_src_t; 2693 2694 #define LSM6DSV16X_MLC3_SRC 0x72U 2695 typedef struct 2696 { 2697 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2698 uint8_t mlc3_src : 8; 2699 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2700 uint8_t mlc3_src : 8; 2701 #endif /* DRV_BYTE_ORDER */ 2702 } lsm6dsv16x_mlc3_src_t; 2703 2704 #define LSM6DSV16X_MLC4_SRC 0x73U 2705 typedef struct 2706 { 2707 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2708 uint8_t mlc4_src : 8; 2709 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2710 uint8_t mlc4_src : 8; 2711 #endif /* DRV_BYTE_ORDER */ 2712 } lsm6dsv16x_mlc4_src_t; 2713 2714 /** 2715 * @} 2716 * 2717 */ 2718 2719 /** @defgroup bitfields page pg0_emb_adv 2720 * @{ 2721 * 2722 */ 2723 #define LSM6DSV16X_EMB_ADV_PG_0 0x000U 2724 2725 #define LSM6DSV16X_SFLP_GAME_GBIASX_L 0x6EU 2726 typedef struct 2727 { 2728 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2729 uint8_t gbiasx : 8; 2730 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2731 uint8_t gbiasx : 8; 2732 #endif /* DRV_BYTE_ORDER */ 2733 } lsm6dsv16x_sflp_game_gbiasx_l_t; 2734 2735 #define LSM6DSV16X_SFLP_GAME_GBIASX_H 0x6FU 2736 typedef struct 2737 { 2738 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2739 uint8_t gbiasx : 8; 2740 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2741 uint8_t gbiasx : 8; 2742 #endif /* DRV_BYTE_ORDER */ 2743 } lsm6dsv16x_sflp_game_gbiasx_h_t; 2744 2745 #define LSM6DSV16X_SFLP_GAME_GBIASY_L 0x70U 2746 typedef struct 2747 { 2748 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2749 uint8_t gbiasy : 8; 2750 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2751 uint8_t gbiasy : 8; 2752 #endif /* DRV_BYTE_ORDER */ 2753 } lsm6dsv16x_sflp_game_gbiasy_l_t; 2754 2755 #define LSM6DSV16X_SFLP_GAME_GBIASY_H 0x71U 2756 typedef struct 2757 { 2758 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2759 uint8_t gbiasy : 8; 2760 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2761 uint8_t gbiasy : 8; 2762 #endif /* DRV_BYTE_ORDER */ 2763 } lsm6dsv16x_sflp_game_gbiasy_h_t; 2764 2765 #define LSM6DSV16X_SFLP_GAME_GBIASZ_L 0x72U 2766 typedef struct 2767 { 2768 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2769 uint8_t gbiasz : 8; 2770 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2771 uint8_t gbiasz : 8; 2772 #endif /* DRV_BYTE_ORDER */ 2773 } lsm6dsv16x_sflp_game_gbiasz_l_t; 2774 2775 #define LSM6DSV16X_SFLP_GAME_GBIASZ_H 0x73U 2776 typedef struct 2777 { 2778 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2779 uint8_t gbiasz : 8; 2780 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2781 uint8_t gbiasz : 8; 2782 #endif /* DRV_BYTE_ORDER */ 2783 } lsm6dsv16x_sflp_game_gbiasz_h_t; 2784 2785 #define LSM6DSV16X_FSM_EXT_SENSITIVITY_L 0xBAU 2786 typedef struct 2787 { 2788 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2789 uint8_t fsm_ext_s : 8; 2790 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2791 uint8_t fsm_ext_s : 8; 2792 #endif /* DRV_BYTE_ORDER */ 2793 } lsm6dsv16x_fsm_ext_sensitivity_l_t; 2794 2795 #define LSM6DSV16X_FSM_EXT_SENSITIVITY_H 0xBBU 2796 typedef struct 2797 { 2798 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2799 uint8_t fsm_ext_s : 8; 2800 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2801 uint8_t fsm_ext_s : 8; 2802 #endif /* DRV_BYTE_ORDER */ 2803 } lsm6dsv16x_fsm_ext_sensitivity_h_t; 2804 2805 #define LSM6DSV16X_FSM_EXT_OFFX_L 0xC0U 2806 typedef struct 2807 { 2808 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2809 uint8_t fsm_ext_offx : 8; 2810 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2811 uint8_t fsm_ext_offx : 8; 2812 #endif /* DRV_BYTE_ORDER */ 2813 } lsm6dsv16x_fsm_ext_offx_l_t; 2814 2815 #define LSM6DSV16X_FSM_EXT_OFFX_H 0xC1U 2816 typedef struct 2817 { 2818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2819 uint8_t fsm_ext_offx : 8; 2820 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2821 uint8_t fsm_ext_offx : 8; 2822 #endif /* DRV_BYTE_ORDER */ 2823 } lsm6dsv16x_fsm_ext_offx_h_t; 2824 2825 #define LSM6DSV16X_FSM_EXT_OFFY_L 0xC2U 2826 typedef struct 2827 { 2828 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2829 uint8_t fsm_ext_offy : 8; 2830 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2831 uint8_t fsm_ext_offy : 8; 2832 #endif /* DRV_BYTE_ORDER */ 2833 } lsm6dsv16x_fsm_ext_offy_l_t; 2834 2835 #define LSM6DSV16X_FSM_EXT_OFFY_H 0xC3U 2836 typedef struct 2837 { 2838 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2839 uint8_t fsm_ext_offy : 8; 2840 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2841 uint8_t fsm_ext_offy : 8; 2842 #endif /* DRV_BYTE_ORDER */ 2843 } lsm6dsv16x_fsm_ext_offy_h_t; 2844 2845 #define LSM6DSV16X_FSM_EXT_OFFZ_L 0xC4U 2846 typedef struct 2847 { 2848 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2849 uint8_t fsm_ext_offz : 8; 2850 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2851 uint8_t fsm_ext_offz : 8; 2852 #endif /* DRV_BYTE_ORDER */ 2853 } lsm6dsv16x_fsm_ext_offz_l_t; 2854 2855 #define LSM6DSV16X_FSM_EXT_OFFZ_H 0xC5U 2856 typedef struct 2857 { 2858 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2859 uint8_t fsm_ext_offz : 8; 2860 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2861 uint8_t fsm_ext_offz : 8; 2862 #endif /* DRV_BYTE_ORDER */ 2863 } lsm6dsv16x_fsm_ext_offz_h_t; 2864 2865 #define LSM6DSV16X_FSM_EXT_MATRIX_XX_L 0xC6U 2866 typedef struct 2867 { 2868 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2869 uint8_t fsm_ext_mat_xx : 8; 2870 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2871 uint8_t fsm_ext_mat_xx : 8; 2872 #endif /* DRV_BYTE_ORDER */ 2873 } lsm6dsv16x_fsm_ext_matrix_xx_l_t; 2874 2875 #define LSM6DSV16X_FSM_EXT_MATRIX_XX_H 0xC7U 2876 typedef struct 2877 { 2878 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2879 uint8_t fsm_ext_mat_xx : 8; 2880 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2881 uint8_t fsm_ext_mat_xx : 8; 2882 #endif /* DRV_BYTE_ORDER */ 2883 } lsm6dsv16x_fsm_ext_matrix_xx_h_t; 2884 2885 #define LSM6DSV16X_FSM_EXT_MATRIX_XY_L 0xC8U 2886 typedef struct 2887 { 2888 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2889 uint8_t fsm_ext_mat_xy : 8; 2890 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2891 uint8_t fsm_ext_mat_xy : 8; 2892 #endif /* DRV_BYTE_ORDER */ 2893 } lsm6dsv16x_fsm_ext_matrix_xy_l_t; 2894 2895 #define LSM6DSV16X_FSM_EXT_MATRIX_XY_H 0xC9U 2896 typedef struct 2897 { 2898 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2899 uint8_t fsm_ext_mat_xy : 8; 2900 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2901 uint8_t fsm_ext_mat_xy : 8; 2902 #endif /* DRV_BYTE_ORDER */ 2903 } lsm6dsv16x_fsm_ext_matrix_xy_h_t; 2904 2905 #define LSM6DSV16X_FSM_EXT_MATRIX_XZ_L 0xCAU 2906 typedef struct 2907 { 2908 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2909 uint8_t fsm_ext_mat_xz : 8; 2910 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2911 uint8_t fsm_ext_mat_xz : 8; 2912 #endif /* DRV_BYTE_ORDER */ 2913 } lsm6dsv16x_fsm_ext_matrix_xz_l_t; 2914 2915 #define LSM6DSV16X_FSM_EXT_MATRIX_XZ_H 0xCBU 2916 typedef struct 2917 { 2918 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2919 uint8_t fsm_ext_mat_xz : 8; 2920 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2921 uint8_t fsm_ext_mat_xz : 8; 2922 #endif /* DRV_BYTE_ORDER */ 2923 } lsm6dsv16x_fsm_ext_matrix_xz_h_t; 2924 2925 #define LSM6DSV16X_FSM_EXT_MATRIX_YY_L 0xCCU 2926 typedef struct 2927 { 2928 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2929 uint8_t fsm_ext_mat_yy : 8; 2930 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2931 uint8_t fsm_ext_mat_yy : 8; 2932 #endif /* DRV_BYTE_ORDER */ 2933 } lsm6dsv16x_fsm_ext_matrix_yy_l_t; 2934 2935 #define LSM6DSV16X_FSM_EXT_MATRIX_YY_H 0xCDU 2936 typedef struct 2937 { 2938 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2939 uint8_t fsm_ext_mat_yy : 8; 2940 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2941 uint8_t fsm_ext_mat_yy : 8; 2942 #endif /* DRV_BYTE_ORDER */ 2943 } lsm6dsv16x_fsm_ext_matrix_yy_h_t; 2944 2945 #define LSM6DSV16X_FSM_EXT_MATRIX_YZ_L 0xCEU 2946 typedef struct 2947 { 2948 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2949 uint8_t fsm_ext_mat_yz : 8; 2950 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2951 uint8_t fsm_ext_mat_yz : 8; 2952 #endif /* DRV_BYTE_ORDER */ 2953 } lsm6dsv16x_fsm_ext_matrix_yz_l_t; 2954 2955 #define LSM6DSV16X_FSM_EXT_MATRIX_YZ_H 0xCFU 2956 typedef struct 2957 { 2958 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2959 uint8_t fsm_ext_mat_yz : 8; 2960 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2961 uint8_t fsm_ext_mat_yz : 8; 2962 #endif /* DRV_BYTE_ORDER */ 2963 } lsm6dsv16x_fsm_ext_matrix_yz_h_t; 2964 2965 #define LSM6DSV16X_FSM_EXT_MATRIX_ZZ_L 0xD0U 2966 typedef struct 2967 { 2968 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2969 uint8_t fsm_ext_mat_zz : 8; 2970 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2971 uint8_t fsm_ext_mat_zz : 8; 2972 #endif /* DRV_BYTE_ORDER */ 2973 } lsm6dsv16x_fsm_ext_matrix_zz_l_t; 2974 2975 #define LSM6DSV16X_FSM_EXT_MATRIX_ZZ_H 0xD1U 2976 typedef struct 2977 { 2978 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2979 uint8_t fsm_ext_mat_zz : 8; 2980 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2981 uint8_t fsm_ext_mat_zz : 8; 2982 #endif /* DRV_BYTE_ORDER */ 2983 } lsm6dsv16x_fsm_ext_matrix_zz_h_t; 2984 2985 #define LSM6DSV16X_EXT_CFG_A 0xD4U 2986 typedef struct 2987 { 2988 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2989 uint8_t ext_z_axis : 3; 2990 uint8_t not_used0 : 1; 2991 uint8_t ext_y_axis : 3; 2992 uint8_t not_used1 : 1; 2993 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2994 uint8_t not_used1 : 1; 2995 uint8_t ext_y_axis : 3; 2996 uint8_t not_used0 : 1; 2997 uint8_t ext_z_axis : 3; 2998 #endif /* DRV_BYTE_ORDER */ 2999 } lsm6dsv16x_ext_cfg_a_t; 3000 3001 #define LSM6DSV16X_EXT_CFG_B 0xD5U 3002 typedef struct 3003 { 3004 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3005 uint8_t ext_x_axis : 3; 3006 uint8_t not_used0 : 5; 3007 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3008 uint8_t not_used0 : 5; 3009 uint8_t ext_x_axis : 3; 3010 #endif /* DRV_BYTE_ORDER */ 3011 } lsm6dsv16x_ext_cfg_b_t; 3012 3013 /** 3014 * @} 3015 * 3016 */ 3017 3018 /** @defgroup bitfields page pg1_emb_adv 3019 * @{ 3020 * 3021 */ 3022 #define LSM6DSV16X_EMB_ADV_PG_1 0x100U 3023 3024 #define LSM6DSV16X_FSM_LC_TIMEOUT_L 0x7AU 3025 typedef struct 3026 { 3027 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3028 uint8_t fsm_lc_timeout : 8; 3029 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3030 uint8_t fsm_lc_timeout : 8; 3031 #endif /* DRV_BYTE_ORDER */ 3032 } lsm6dsv16x_fsm_lc_timeout_l_t; 3033 3034 #define LSM6DSV16X_FSM_LC_TIMEOUT_H 0x7BU 3035 typedef struct 3036 { 3037 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3038 uint8_t fsm_lc_timeout : 8; 3039 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3040 uint8_t fsm_lc_timeout : 8; 3041 #endif /* DRV_BYTE_ORDER */ 3042 } lsm6dsv16x_fsm_lc_timeout_h_t; 3043 3044 #define LSM6DSV16X_FSM_PROGRAMS 0x7CU 3045 typedef struct 3046 { 3047 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3048 uint8_t fsm_n_prog : 8; 3049 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3050 uint8_t fsm_n_prog : 8; 3051 #endif /* DRV_BYTE_ORDER */ 3052 } lsm6dsv16x_fsm_programs_t; 3053 3054 #define LSM6DSV16X_FSM_START_ADD_L 0x7EU 3055 typedef struct 3056 { 3057 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3058 uint8_t fsm_start : 8; 3059 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3060 uint8_t fsm_start : 8; 3061 #endif /* DRV_BYTE_ORDER */ 3062 } lsm6dsv16x_fsm_start_add_l_t; 3063 3064 #define LSM6DSV16X_FSM_START_ADD_H 0x7FU 3065 typedef struct 3066 { 3067 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3068 uint8_t fsm_start : 8; 3069 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3070 uint8_t fsm_start : 8; 3071 #endif /* DRV_BYTE_ORDER */ 3072 } lsm6dsv16x_fsm_start_add_h_t; 3073 3074 #define LSM6DSV16X_PEDO_CMD_REG 0x83U 3075 typedef struct 3076 { 3077 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3078 uint8_t not_used0 : 2; 3079 uint8_t fp_rejection_en : 1; 3080 uint8_t carry_count_en : 1; 3081 uint8_t not_used1 : 4; 3082 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3083 uint8_t not_used1 : 4; 3084 uint8_t carry_count_en : 1; 3085 uint8_t fp_rejection_en : 1; 3086 uint8_t not_used0 : 2; 3087 #endif /* DRV_BYTE_ORDER */ 3088 } lsm6dsv16x_pedo_cmd_reg_t; 3089 3090 #define LSM6DSV16X_PEDO_DEB_STEPS_CONF 0x84U 3091 typedef struct 3092 { 3093 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3094 uint8_t deb_step : 8; 3095 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3096 uint8_t deb_step : 8; 3097 #endif /* DRV_BYTE_ORDER */ 3098 } lsm6dsv16x_pedo_deb_steps_conf_t; 3099 3100 #define LSM6DSV16X_PEDO_SC_DELTAT_L 0xD0U 3101 typedef struct 3102 { 3103 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3104 uint8_t pd_sc : 8; 3105 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3106 uint8_t pd_sc : 8; 3107 #endif /* DRV_BYTE_ORDER */ 3108 } lsm6dsv16x_pedo_sc_deltat_l_t; 3109 3110 #define LSM6DSV16X_PEDO_SC_DELTAT_H 0xD1U 3111 typedef struct 3112 { 3113 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3114 uint8_t pd_sc : 8; 3115 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3116 uint8_t pd_sc : 8; 3117 #endif /* DRV_BYTE_ORDER */ 3118 } lsm6dsv16x_pedo_sc_deltat_h_t; 3119 3120 #define LSM6DSV16X_MLC_EXT_SENSITIVITY_L 0xE8U 3121 typedef struct 3122 { 3123 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3124 uint8_t mlc_ext_s : 8; 3125 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3126 uint8_t mlc_ext_s : 8; 3127 #endif /* DRV_BYTE_ORDER */ 3128 } lsm6dsv16x_mlc_ext_sensitivity_l_t; 3129 3130 #define LSM6DSV16X_MLC_EXT_SENSITIVITY_H 0xE9U 3131 typedef struct 3132 { 3133 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3134 uint8_t mlc_ext_s : 8; 3135 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3136 uint8_t mlc_ext_s : 8; 3137 #endif /* DRV_BYTE_ORDER */ 3138 } lsm6dsv16x_mlc_ext_sensitivity_h_t; 3139 3140 /** @defgroup bitfields page pg2_emb_adv 3141 * @{ 3142 * 3143 */ 3144 #define LSM6DSV16X_EMB_ADV_PG_2 0x200U 3145 3146 #define LSM6DSV16X_EXT_FORMAT 0x00 3147 typedef struct 3148 { 3149 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3150 uint8_t not_used0 : 2; 3151 uint8_t ext_format_sel : 1; 3152 uint8_t not_used1 : 5; 3153 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3154 uint8_t not_used1 : 5; 3155 uint8_t ext_format_sel : 1; 3156 uint8_t not_used0 : 2; 3157 #endif /* DRV_BYTE_ORDER */ 3158 } lsm6dsv16x_ext_format_t; 3159 3160 #define LSM6DSV16X_EXT_3BYTE_SENSITIVITY_L 0x02U 3161 typedef struct 3162 { 3163 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3164 uint8_t ext_3byte_s : 8; 3165 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3166 uint8_t ext_3byte_s : 8; 3167 #endif /* DRV_BYTE_ORDER */ 3168 } lsm6dsv16x_ext_3byte_sensitivity_l_t; 3169 3170 #define LSM6DSV16X_EXT_3BYTE_SENSITIVITY_H 0x03U 3171 typedef struct 3172 { 3173 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3174 uint8_t ext_3byte_s : 8; 3175 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3176 uint8_t ext_3byte_s : 8; 3177 #endif /* DRV_BYTE_ORDER */ 3178 } lsm6dsv16x_ext_3byte_sensitivity_h_t; 3179 3180 #define LSM6DSV16X_EXT_3BYTE_OFFSET_XL 0x06U 3181 typedef struct 3182 { 3183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3184 uint8_t ext_3byte_off : 8; 3185 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3186 uint8_t ext_3byte_off : 8; 3187 #endif /* DRV_BYTE_ORDER */ 3188 } lsm6dsv16x_ext_3byte_offset_xl_t; 3189 3190 #define LSM6DSV16X_EXT_3BYTE_OFFSET_L 0x07U 3191 typedef struct 3192 { 3193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3194 uint8_t ext_3byte_off : 8; 3195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3196 uint8_t ext_3byte_off : 8; 3197 #endif /* DRV_BYTE_ORDER */ 3198 } lsm6dsv16x_ext_3byte_offset_l_t; 3199 3200 #define LSM6DSV16X_EXT_3BYTE_OFFSET_H 0x08U 3201 typedef struct 3202 { 3203 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3204 uint8_t ext_3byte_off : 8; 3205 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3206 uint8_t ext_3byte_off : 8; 3207 #endif /* DRV_BYTE_ORDER */ 3208 } lsm6dsv16x_ext_3byte_offset_h_t; 3209 3210 /** 3211 * @} 3212 * 3213 */ 3214 3215 /** @defgroup bitfields page sensor_hub 3216 * @{ 3217 * 3218 */ 3219 3220 #define LSM6DSV16X_SENSOR_HUB_1 0x2U 3221 typedef struct 3222 { 3223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3224 uint8_t sensorhub1 : 8; 3225 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3226 uint8_t sensorhub1 : 8; 3227 #endif /* DRV_BYTE_ORDER */ 3228 } lsm6dsv16x_sensor_hub_1_t; 3229 3230 #define LSM6DSV16X_SENSOR_HUB_2 0x3U 3231 typedef struct 3232 { 3233 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3234 uint8_t sensorhub2 : 8; 3235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3236 uint8_t sensorhub2 : 8; 3237 #endif /* DRV_BYTE_ORDER */ 3238 } lsm6dsv16x_sensor_hub_2_t; 3239 3240 #define LSM6DSV16X_SENSOR_HUB_3 0x4U 3241 typedef struct 3242 { 3243 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3244 uint8_t sensorhub3 : 8; 3245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3246 uint8_t sensorhub3 : 8; 3247 #endif /* DRV_BYTE_ORDER */ 3248 } lsm6dsv16x_sensor_hub_3_t; 3249 3250 #define LSM6DSV16X_SENSOR_HUB_4 0x5U 3251 typedef struct 3252 { 3253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3254 uint8_t sensorhub4 : 8; 3255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3256 uint8_t sensorhub4 : 8; 3257 #endif /* DRV_BYTE_ORDER */ 3258 } lsm6dsv16x_sensor_hub_4_t; 3259 3260 #define LSM6DSV16X_SENSOR_HUB_5 0x6U 3261 typedef struct 3262 { 3263 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3264 uint8_t sensorhub5 : 8; 3265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3266 uint8_t sensorhub5 : 8; 3267 #endif /* DRV_BYTE_ORDER */ 3268 } lsm6dsv16x_sensor_hub_5_t; 3269 3270 #define LSM6DSV16X_SENSOR_HUB_6 0x7U 3271 typedef struct 3272 { 3273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3274 uint8_t sensorhub6 : 8; 3275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3276 uint8_t sensorhub6 : 8; 3277 #endif /* DRV_BYTE_ORDER */ 3278 } lsm6dsv16x_sensor_hub_6_t; 3279 3280 #define LSM6DSV16X_SENSOR_HUB_7 0x8U 3281 typedef struct 3282 { 3283 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3284 uint8_t sensorhub7 : 8; 3285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3286 uint8_t sensorhub7 : 8; 3287 #endif /* DRV_BYTE_ORDER */ 3288 } lsm6dsv16x_sensor_hub_7_t; 3289 3290 #define LSM6DSV16X_SENSOR_HUB_8 0x9U 3291 typedef struct 3292 { 3293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3294 uint8_t sensorhub8 : 8; 3295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3296 uint8_t sensorhub8 : 8; 3297 #endif /* DRV_BYTE_ORDER */ 3298 } lsm6dsv16x_sensor_hub_8_t; 3299 3300 #define LSM6DSV16X_SENSOR_HUB_9 0x0AU 3301 typedef struct 3302 { 3303 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3304 uint8_t sensorhub9 : 8; 3305 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3306 uint8_t sensorhub9 : 8; 3307 #endif /* DRV_BYTE_ORDER */ 3308 } lsm6dsv16x_sensor_hub_9_t; 3309 3310 #define LSM6DSV16X_SENSOR_HUB_10 0x0BU 3311 typedef struct 3312 { 3313 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3314 uint8_t sensorhub10 : 8; 3315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3316 uint8_t sensorhub10 : 8; 3317 #endif /* DRV_BYTE_ORDER */ 3318 } lsm6dsv16x_sensor_hub_10_t; 3319 3320 #define LSM6DSV16X_SENSOR_HUB_11 0x0CU 3321 typedef struct 3322 { 3323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3324 uint8_t sensorhub11 : 8; 3325 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3326 uint8_t sensorhub11 : 8; 3327 #endif /* DRV_BYTE_ORDER */ 3328 } lsm6dsv16x_sensor_hub_11_t; 3329 3330 #define LSM6DSV16X_SENSOR_HUB_12 0x0DU 3331 typedef struct 3332 { 3333 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3334 uint8_t sensorhub12 : 8; 3335 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3336 uint8_t sensorhub12 : 8; 3337 #endif /* DRV_BYTE_ORDER */ 3338 } lsm6dsv16x_sensor_hub_12_t; 3339 3340 #define LSM6DSV16X_SENSOR_HUB_13 0x0EU 3341 typedef struct 3342 { 3343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3344 uint8_t sensorhub13 : 8; 3345 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3346 uint8_t sensorhub13 : 8; 3347 #endif /* DRV_BYTE_ORDER */ 3348 } lsm6dsv16x_sensor_hub_13_t; 3349 3350 #define LSM6DSV16X_SENSOR_HUB_14 0x0FU 3351 typedef struct 3352 { 3353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3354 uint8_t sensorhub14 : 8; 3355 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3356 uint8_t sensorhub14 : 8; 3357 #endif /* DRV_BYTE_ORDER */ 3358 } lsm6dsv16x_sensor_hub_14_t; 3359 3360 #define LSM6DSV16X_SENSOR_HUB_15 0x10U 3361 typedef struct 3362 { 3363 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3364 uint8_t sensorhub15 : 8; 3365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3366 uint8_t sensorhub15 : 8; 3367 #endif /* DRV_BYTE_ORDER */ 3368 } lsm6dsv16x_sensor_hub_15_t; 3369 3370 #define LSM6DSV16X_SENSOR_HUB_16 0x11U 3371 typedef struct 3372 { 3373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3374 uint8_t sensorhub16 : 8; 3375 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3376 uint8_t sensorhub16 : 8; 3377 #endif /* DRV_BYTE_ORDER */ 3378 } lsm6dsv16x_sensor_hub_16_t; 3379 3380 #define LSM6DSV16X_SENSOR_HUB_17 0x12U 3381 typedef struct 3382 { 3383 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3384 uint8_t sensorhub17 : 8; 3385 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3386 uint8_t sensorhub17 : 8; 3387 #endif /* DRV_BYTE_ORDER */ 3388 } lsm6dsv16x_sensor_hub_17_t; 3389 3390 #define LSM6DSV16X_SENSOR_HUB_18 0x13U 3391 typedef struct 3392 { 3393 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3394 uint8_t sensorhub18 : 8; 3395 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3396 uint8_t sensorhub18 : 8; 3397 #endif /* DRV_BYTE_ORDER */ 3398 } lsm6dsv16x_sensor_hub_18_t; 3399 3400 #define LSM6DSV16X_MASTER_CONFIG 0x14U 3401 typedef struct 3402 { 3403 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3404 uint8_t aux_sens_on : 2; 3405 uint8_t master_on : 1; 3406 uint8_t not_used0 : 1; 3407 uint8_t pass_through_mode : 1; 3408 uint8_t start_config : 1; 3409 uint8_t write_once : 1; 3410 uint8_t rst_master_regs : 1; 3411 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3412 uint8_t rst_master_regs : 1; 3413 uint8_t write_once : 1; 3414 uint8_t start_config : 1; 3415 uint8_t pass_through_mode : 1; 3416 uint8_t not_used0 : 1; 3417 uint8_t master_on : 1; 3418 uint8_t aux_sens_on : 2; 3419 #endif /* DRV_BYTE_ORDER */ 3420 } lsm6dsv16x_master_config_t; 3421 3422 #define LSM6DSV16X_SLV0_ADD 0x15U 3423 typedef struct 3424 { 3425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3426 uint8_t rw_0 : 1; 3427 uint8_t slave0_add : 7; 3428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3429 uint8_t slave0_add : 7; 3430 uint8_t rw_0 : 1; 3431 #endif /* DRV_BYTE_ORDER */ 3432 } lsm6dsv16x_slv0_add_t; 3433 3434 #define LSM6DSV16X_SLV0_SUBADD 0x16U 3435 typedef struct 3436 { 3437 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3438 uint8_t slave0_reg : 8; 3439 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3440 uint8_t slave0_reg : 8; 3441 #endif /* DRV_BYTE_ORDER */ 3442 } lsm6dsv16x_slv0_subadd_t; 3443 3444 #define LSM6DSV16X_SLV0_CONFIG 0x17U 3445 typedef struct 3446 { 3447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3448 uint8_t slave0_numop : 3; 3449 uint8_t batch_ext_sens_0_en : 1; 3450 uint8_t not_used0 : 1; 3451 uint8_t shub_odr : 3; 3452 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3453 uint8_t shub_odr : 3; 3454 uint8_t not_used0 : 1; 3455 uint8_t batch_ext_sens_0_en : 1; 3456 uint8_t slave0_numop : 3; 3457 #endif /* DRV_BYTE_ORDER */ 3458 } lsm6dsv16x_slv0_config_t; 3459 3460 #define LSM6DSV16X_SLV1_ADD 0x18U 3461 typedef struct 3462 { 3463 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3464 uint8_t r_1 : 1; 3465 uint8_t slave1_add : 7; 3466 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3467 uint8_t slave1_add : 7; 3468 uint8_t r_1 : 1; 3469 #endif /* DRV_BYTE_ORDER */ 3470 } lsm6dsv16x_slv1_add_t; 3471 3472 #define LSM6DSV16X_SLV1_SUBADD 0x19U 3473 typedef struct 3474 { 3475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3476 uint8_t slave1_reg : 8; 3477 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3478 uint8_t slave1_reg : 8; 3479 #endif /* DRV_BYTE_ORDER */ 3480 } lsm6dsv16x_slv1_subadd_t; 3481 3482 #define LSM6DSV16X_SLV1_CONFIG 0x1AU 3483 typedef struct 3484 { 3485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3486 uint8_t slave1_numop : 3; 3487 uint8_t batch_ext_sens_1_en : 1; 3488 uint8_t not_used0 : 4; 3489 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3490 uint8_t not_used0 : 4; 3491 uint8_t batch_ext_sens_1_en : 1; 3492 uint8_t slave1_numop : 3; 3493 #endif /* DRV_BYTE_ORDER */ 3494 } lsm6dsv16x_slv1_config_t; 3495 3496 #define LSM6DSV16X_SLV2_ADD 0x1BU 3497 typedef struct 3498 { 3499 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3500 uint8_t r_2 : 1; 3501 uint8_t slave2_add : 7; 3502 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3503 uint8_t slave2_add : 7; 3504 uint8_t r_2 : 1; 3505 #endif /* DRV_BYTE_ORDER */ 3506 } lsm6dsv16x_slv2_add_t; 3507 3508 #define LSM6DSV16X_SLV2_SUBADD 0x1CU 3509 typedef struct 3510 { 3511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3512 uint8_t slave2_reg : 8; 3513 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3514 uint8_t slave2_reg : 8; 3515 #endif /* DRV_BYTE_ORDER */ 3516 } lsm6dsv16x_slv2_subadd_t; 3517 3518 #define LSM6DSV16X_SLV2_CONFIG 0x1DU 3519 typedef struct 3520 { 3521 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3522 uint8_t slave2_numop : 3; 3523 uint8_t batch_ext_sens_2_en : 1; 3524 uint8_t not_used0 : 4; 3525 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3526 uint8_t not_used0 : 4; 3527 uint8_t batch_ext_sens_2_en : 1; 3528 uint8_t slave2_numop : 3; 3529 #endif /* DRV_BYTE_ORDER */ 3530 } lsm6dsv16x_slv2_config_t; 3531 3532 #define LSM6DSV16X_SLV3_ADD 0x1EU 3533 typedef struct 3534 { 3535 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3536 uint8_t r_3 : 1; 3537 uint8_t slave3_add : 7; 3538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3539 uint8_t slave3_add : 7; 3540 uint8_t r_3 : 1; 3541 #endif /* DRV_BYTE_ORDER */ 3542 } lsm6dsv16x_slv3_add_t; 3543 3544 #define LSM6DSV16X_SLV3_SUBADD 0x1FU 3545 typedef struct 3546 { 3547 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3548 uint8_t slave3_reg : 8; 3549 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3550 uint8_t slave3_reg : 8; 3551 #endif /* DRV_BYTE_ORDER */ 3552 } lsm6dsv16x_slv3_subadd_t; 3553 3554 #define LSM6DSV16X_SLV3_CONFIG 0x20U 3555 typedef struct 3556 { 3557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3558 uint8_t slave3_numop : 3; 3559 uint8_t batch_ext_sens_3_en : 1; 3560 uint8_t not_used0 : 4; 3561 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3562 uint8_t not_used0 : 4; 3563 uint8_t batch_ext_sens_3_en : 1; 3564 uint8_t slave3_numop : 3; 3565 #endif /* DRV_BYTE_ORDER */ 3566 } lsm6dsv16x_slv3_config_t; 3567 3568 #define LSM6DSV16X_DATAWRITE_SLV0 0x21U 3569 typedef struct 3570 { 3571 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3572 uint8_t slave0_dataw : 8; 3573 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3574 uint8_t slave0_dataw : 8; 3575 #endif /* DRV_BYTE_ORDER */ 3576 } lsm6dsv16x_datawrite_slv0_t; 3577 3578 #define LSM6DSV16X_STATUS_MASTER 0x22U 3579 typedef struct 3580 { 3581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3582 uint8_t sens_hub_endop : 1; 3583 uint8_t not_used0 : 2; 3584 uint8_t slave0_nack : 1; 3585 uint8_t slave1_nack : 1; 3586 uint8_t slave2_nack : 1; 3587 uint8_t slave3_nack : 1; 3588 uint8_t wr_once_done : 1; 3589 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3590 uint8_t wr_once_done : 1; 3591 uint8_t slave3_nack : 1; 3592 uint8_t slave2_nack : 1; 3593 uint8_t slave1_nack : 1; 3594 uint8_t slave0_nack : 1; 3595 uint8_t not_used0 : 2; 3596 uint8_t sens_hub_endop : 1; 3597 #endif /* DRV_BYTE_ORDER */ 3598 } lsm6dsv16x_status_master_t; 3599 3600 /** 3601 * @} 3602 * 3603 */ 3604 3605 /** 3606 * @defgroup LSM6DSO_Register_Union 3607 * @brief This union group all the registers having a bit-field 3608 * description. 3609 * This union is useful but it's not needed by the driver. 3610 * 3611 * REMOVING this union you are compliant with: 3612 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 3613 * 3614 * @{ 3615 * 3616 */ 3617 typedef union 3618 { 3619 lsm6dsv16x_func_cfg_access_t func_cfg_access; 3620 lsm6dsv16x_pin_ctrl_t pin_ctrl; 3621 lsm6dsv16x_if_cfg_t if_cfg; 3622 lsm6dsv16x_odr_trig_cfg_t odr_trig_cfg; 3623 lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1; 3624 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2; 3625 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3; 3626 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4; 3627 lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1; 3628 lsm6dsv16x_counter_bdr_reg2_t counter_bdr_reg2; 3629 lsm6dsv16x_int1_ctrl_t int1_ctrl; 3630 lsm6dsv16x_int2_ctrl_t int2_ctrl; 3631 lsm6dsv16x_who_am_i_t who_am_i; 3632 lsm6dsv16x_ctrl1_t ctrl1; 3633 lsm6dsv16x_ctrl2_t ctrl2; 3634 lsm6dsv16x_ctrl3_t ctrl3; 3635 lsm6dsv16x_ctrl4_t ctrl4; 3636 lsm6dsv16x_ctrl5_t ctrl5; 3637 lsm6dsv16x_ctrl6_t ctrl6; 3638 lsm6dsv16x_ctrl7_t ctrl7; 3639 lsm6dsv16x_ctrl8_t ctrl8; 3640 lsm6dsv16x_ctrl9_t ctrl9; 3641 lsm6dsv16x_ctrl10_t ctrl10; 3642 lsm6dsv16x_ctrl_status_t ctrl_status; 3643 lsm6dsv16x_fifo_status1_t fifo_status1; 3644 lsm6dsv16x_fifo_status2_t fifo_status2; 3645 lsm6dsv16x_all_int_src_t all_int_src; 3646 lsm6dsv16x_status_reg_t status_reg; 3647 lsm6dsv16x_out_temp_l_t out_temp_l; 3648 lsm6dsv16x_out_temp_h_t out_temp_h; 3649 lsm6dsv16x_outx_l_g_t outx_l_g; 3650 lsm6dsv16x_outx_h_g_t outx_h_g; 3651 lsm6dsv16x_outy_l_g_t outy_l_g; 3652 lsm6dsv16x_outy_h_g_t outy_h_g; 3653 lsm6dsv16x_outz_l_g_t outz_l_g; 3654 lsm6dsv16x_outz_h_g_t outz_h_g; 3655 lsm6dsv16x_outx_l_a_t outx_l_a; 3656 lsm6dsv16x_outx_h_a_t outx_h_a; 3657 lsm6dsv16x_outy_l_a_t outy_l_a; 3658 lsm6dsv16x_outy_h_a_t outy_h_a; 3659 lsm6dsv16x_outz_l_a_t outz_l_a; 3660 lsm6dsv16x_outz_h_a_t outz_h_a; 3661 lsm6dsv16x_ui_outx_l_g_ois_eis_t ui_outx_l_g_ois_eis; 3662 lsm6dsv16x_ui_outx_h_g_ois_eis_t ui_outx_h_g_ois_eis; 3663 lsm6dsv16x_ui_outy_l_g_ois_eis_t ui_outy_l_g_ois_eis; 3664 lsm6dsv16x_ui_outy_h_g_ois_eis_t ui_outy_h_g_ois_eis; 3665 lsm6dsv16x_ui_outz_l_g_ois_eis_t ui_outz_l_g_ois_eis; 3666 lsm6dsv16x_ui_outz_h_g_ois_eis_t ui_outz_h_g_ois_eis; 3667 lsm6dsv16x_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; 3668 lsm6dsv16x_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; 3669 lsm6dsv16x_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; 3670 lsm6dsv16x_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; 3671 lsm6dsv16x_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; 3672 lsm6dsv16x_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; 3673 lsm6dsv16x_ah_qvar_out_l_t ah_qvar_out_l; 3674 lsm6dsv16x_ah_qvar_out_h_t ah_qvar_out_h; 3675 lsm6dsv16x_timestamp0_t timestamp0; 3676 lsm6dsv16x_timestamp1_t timestamp1; 3677 lsm6dsv16x_timestamp2_t timestamp2; 3678 lsm6dsv16x_timestamp3_t timestamp3; 3679 lsm6dsv16x_ui_status_reg_ois_t ui_status_reg_ois; 3680 lsm6dsv16x_wake_up_src_t wake_up_src; 3681 lsm6dsv16x_tap_src_t tap_src; 3682 lsm6dsv16x_d6d_src_t d6d_src; 3683 lsm6dsv16x_status_master_mainpage_t status_master_mainpage; 3684 lsm6dsv16x_emb_func_status_mainpage_t emb_func_status_mainpage; 3685 lsm6dsv16x_fsm_status_mainpage_t fsm_status_mainpage; 3686 lsm6dsv16x_mlc_status_mainpage_t mlc_status_mainpage; 3687 lsm6dsv16x_internal_freq_t internal_freq; 3688 lsm6dsv16x_functions_enable_t functions_enable; 3689 lsm6dsv16x_den_t den; 3690 lsm6dsv16x_inactivity_dur_t inactivity_dur; 3691 lsm6dsv16x_inactivity_ths_t inactivity_ths; 3692 lsm6dsv16x_tap_cfg0_t tap_cfg0; 3693 lsm6dsv16x_tap_cfg1_t tap_cfg1; 3694 lsm6dsv16x_tap_cfg2_t tap_cfg2; 3695 lsm6dsv16x_tap_ths_6d_t tap_ths_6d; 3696 lsm6dsv16x_tap_dur_t tap_dur; 3697 lsm6dsv16x_wake_up_ths_t wake_up_ths; 3698 lsm6dsv16x_wake_up_dur_t wake_up_dur; 3699 lsm6dsv16x_free_fall_t free_fall; 3700 lsm6dsv16x_md1_cfg_t md1_cfg; 3701 lsm6dsv16x_md2_cfg_t md2_cfg; 3702 lsm6dsv16x_emb_func_cfg_t emb_func_cfg; 3703 lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl; 3704 lsm6dsv16x_ui_spi2_shared_0_t ui_spi2_shared_0; 3705 lsm6dsv16x_ui_spi2_shared_1_t ui_spi2_shared_1; 3706 lsm6dsv16x_ui_spi2_shared_2_t ui_spi2_shared_2; 3707 lsm6dsv16x_ui_spi2_shared_3_t ui_spi2_shared_3; 3708 lsm6dsv16x_ui_spi2_shared_4_t ui_spi2_shared_4; 3709 lsm6dsv16x_ui_spi2_shared_5_t ui_spi2_shared_5; 3710 lsm6dsv16x_ctrl_eis_t ctrl_eis; 3711 lsm6dsv16x_ui_int_ois_t ui_int_ois; 3712 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois; 3713 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois; 3714 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois; 3715 lsm6dsv16x_x_ofs_usr_t x_ofs_usr; 3716 lsm6dsv16x_y_ofs_usr_t y_ofs_usr; 3717 lsm6dsv16x_z_ofs_usr_t z_ofs_usr; 3718 lsm6dsv16x_fifo_data_out_tag_t fifo_data_out_tag; 3719 lsm6dsv16x_fifo_data_out_x_l_t fifo_data_out_x_l; 3720 lsm6dsv16x_fifo_data_out_x_h_t fifo_data_out_x_h; 3721 lsm6dsv16x_fifo_data_out_y_l_t fifo_data_out_y_l; 3722 lsm6dsv16x_fifo_data_out_y_h_t fifo_data_out_y_h; 3723 lsm6dsv16x_fifo_data_out_z_l_t fifo_data_out_z_l; 3724 lsm6dsv16x_fifo_data_out_z_h_t fifo_data_out_z_h; 3725 lsm6dsv16x_spi2_who_am_i_t spi2_who_am_i; 3726 lsm6dsv16x_spi2_status_reg_ois_t spi2_status_reg_ois; 3727 lsm6dsv16x_spi2_out_temp_l_t spi2_out_temp_l; 3728 lsm6dsv16x_spi2_out_temp_h_t spi2_out_temp_h; 3729 lsm6dsv16x_spi2_outx_l_g_ois_t spi2_outx_l_g_ois; 3730 lsm6dsv16x_spi2_outx_h_g_ois_t spi2_outx_h_g_ois; 3731 lsm6dsv16x_spi2_outy_l_g_ois_t spi2_outy_l_g_ois; 3732 lsm6dsv16x_spi2_outy_h_g_ois_t spi2_outy_h_g_ois; 3733 lsm6dsv16x_spi2_outz_l_g_ois_t spi2_outz_l_g_ois; 3734 lsm6dsv16x_spi2_outz_h_g_ois_t spi2_outz_h_g_ois; 3735 lsm6dsv16x_spi2_outx_l_a_ois_t spi2_outx_l_a_ois; 3736 lsm6dsv16x_spi2_outx_h_a_ois_t spi2_outx_h_a_ois; 3737 lsm6dsv16x_spi2_outy_l_a_ois_t spi2_outy_l_a_ois; 3738 lsm6dsv16x_spi2_outy_h_a_ois_t spi2_outy_h_a_ois; 3739 lsm6dsv16x_spi2_outz_l_a_ois_t spi2_outz_l_a_ois; 3740 lsm6dsv16x_spi2_outz_h_a_ois_t spi2_outz_h_a_ois; 3741 lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl; 3742 lsm6dsv16x_spi2_int_ois_t spi2_int_ois; 3743 lsm6dsv16x_spi2_ctrl1_ois_t spi2_ctrl1_ois; 3744 lsm6dsv16x_spi2_ctrl2_ois_t spi2_ctrl2_ois; 3745 lsm6dsv16x_spi2_ctrl3_ois_t spi2_ctrl3_ois; 3746 lsm6dsv16x_page_sel_t page_sel; 3747 lsm6dsv16x_emb_func_en_a_t emb_func_en_a; 3748 lsm6dsv16x_emb_func_en_b_t emb_func_en_b; 3749 lsm6dsv16x_emb_func_exec_status_t emb_func_exec_status; 3750 lsm6dsv16x_page_address_t page_address; 3751 lsm6dsv16x_page_value_t page_value; 3752 lsm6dsv16x_emb_func_int1_t emb_func_int1; 3753 lsm6dsv16x_fsm_int1_t fsm_int1; 3754 lsm6dsv16x_mlc_int1_t mlc_int1; 3755 lsm6dsv16x_emb_func_int2_t emb_func_int2; 3756 lsm6dsv16x_fsm_int2_t fsm_int2; 3757 lsm6dsv16x_mlc_int2_t mlc_int2; 3758 lsm6dsv16x_emb_func_status_t emb_func_status; 3759 lsm6dsv16x_fsm_status_t fsm_status; 3760 lsm6dsv16x_mlc_status_t mlc_status; 3761 lsm6dsv16x_page_rw_t page_rw; 3762 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a; 3763 lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b; 3764 lsm6dsv16x_fsm_enable_t fsm_enable; 3765 lsm6dsv16x_fsm_long_counter_l_t fsm_long_counter_l; 3766 lsm6dsv16x_fsm_long_counter_h_t fsm_long_counter_h; 3767 lsm6dsv16x_int_ack_mask_t int_ack_mask; 3768 lsm6dsv16x_fsm_outs1_t fsm_outs1; 3769 lsm6dsv16x_fsm_outs2_t fsm_outs2; 3770 lsm6dsv16x_fsm_outs3_t fsm_outs3; 3771 lsm6dsv16x_fsm_outs4_t fsm_outs4; 3772 lsm6dsv16x_fsm_outs5_t fsm_outs5; 3773 lsm6dsv16x_fsm_outs6_t fsm_outs6; 3774 lsm6dsv16x_fsm_outs7_t fsm_outs7; 3775 lsm6dsv16x_fsm_outs8_t fsm_outs8; 3776 lsm6dsv16x_fsm_odr_t fsm_odr; 3777 lsm6dsv16x_mlc_odr_t mlc_odr; 3778 lsm6dsv16x_step_counter_l_t step_counter_l; 3779 lsm6dsv16x_step_counter_h_t step_counter_h; 3780 lsm6dsv16x_emb_func_src_t emb_func_src; 3781 lsm6dsv16x_emb_func_init_a_t emb_func_init_a; 3782 lsm6dsv16x_emb_func_init_b_t emb_func_init_b; 3783 lsm6dsv16x_mlc1_src_t mlc1_src; 3784 lsm6dsv16x_mlc2_src_t mlc2_src; 3785 lsm6dsv16x_mlc3_src_t mlc3_src; 3786 lsm6dsv16x_mlc4_src_t mlc4_src; 3787 lsm6dsv16x_fsm_ext_sensitivity_l_t fsm_ext_sensitivity_l; 3788 lsm6dsv16x_fsm_ext_sensitivity_h_t fsm_ext_sensitivity_h; 3789 lsm6dsv16x_fsm_ext_offx_l_t fsm_ext_offx_l; 3790 lsm6dsv16x_fsm_ext_offx_h_t fsm_ext_offx_h; 3791 lsm6dsv16x_fsm_ext_offy_l_t fsm_ext_offy_l; 3792 lsm6dsv16x_fsm_ext_offy_h_t fsm_ext_offy_h; 3793 lsm6dsv16x_fsm_ext_offz_l_t fsm_ext_offz_l; 3794 lsm6dsv16x_fsm_ext_offz_h_t fsm_ext_offz_h; 3795 lsm6dsv16x_fsm_ext_matrix_xx_l_t fsm_ext_matrix_xx_l; 3796 lsm6dsv16x_fsm_ext_matrix_xx_h_t fsm_ext_matrix_xx_h; 3797 lsm6dsv16x_fsm_ext_matrix_xy_l_t fsm_ext_matrix_xy_l; 3798 lsm6dsv16x_fsm_ext_matrix_xy_h_t fsm_ext_matrix_xy_h; 3799 lsm6dsv16x_fsm_ext_matrix_xz_l_t fsm_ext_matrix_xz_l; 3800 lsm6dsv16x_fsm_ext_matrix_xz_h_t fsm_ext_matrix_xz_h; 3801 lsm6dsv16x_fsm_ext_matrix_yy_l_t fsm_ext_matrix_yy_l; 3802 lsm6dsv16x_fsm_ext_matrix_yy_h_t fsm_ext_matrix_yy_h; 3803 lsm6dsv16x_fsm_ext_matrix_yz_l_t fsm_ext_matrix_yz_l; 3804 lsm6dsv16x_fsm_ext_matrix_yz_h_t fsm_ext_matrix_yz_h; 3805 lsm6dsv16x_fsm_ext_matrix_zz_l_t fsm_ext_matrix_zz_l; 3806 lsm6dsv16x_fsm_ext_matrix_zz_h_t fsm_ext_matrix_zz_h; 3807 lsm6dsv16x_ext_cfg_a_t ext_cfg_a; 3808 lsm6dsv16x_ext_cfg_b_t ext_cfg_b; 3809 lsm6dsv16x_fsm_lc_timeout_l_t fsm_lc_timeout_l; 3810 lsm6dsv16x_fsm_lc_timeout_h_t fsm_lc_timeout_h; 3811 lsm6dsv16x_fsm_programs_t fsm_programs; 3812 lsm6dsv16x_fsm_start_add_l_t fsm_start_add_l; 3813 lsm6dsv16x_fsm_start_add_h_t fsm_start_add_h; 3814 lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg; 3815 lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf; 3816 lsm6dsv16x_pedo_sc_deltat_l_t pedo_sc_deltat_l; 3817 lsm6dsv16x_pedo_sc_deltat_h_t pedo_sc_deltat_h; 3818 lsm6dsv16x_mlc_ext_sensitivity_l_t mlc_ext_sensitivity_l; 3819 lsm6dsv16x_mlc_ext_sensitivity_h_t mlc_ext_sensitivity_h; 3820 lsm6dsv16x_sensor_hub_1_t sensor_hub_1; 3821 lsm6dsv16x_sensor_hub_2_t sensor_hub_2; 3822 lsm6dsv16x_sensor_hub_3_t sensor_hub_3; 3823 lsm6dsv16x_sensor_hub_4_t sensor_hub_4; 3824 lsm6dsv16x_sensor_hub_5_t sensor_hub_5; 3825 lsm6dsv16x_sensor_hub_6_t sensor_hub_6; 3826 lsm6dsv16x_sensor_hub_7_t sensor_hub_7; 3827 lsm6dsv16x_sensor_hub_8_t sensor_hub_8; 3828 lsm6dsv16x_sensor_hub_9_t sensor_hub_9; 3829 lsm6dsv16x_sensor_hub_10_t sensor_hub_10; 3830 lsm6dsv16x_sensor_hub_11_t sensor_hub_11; 3831 lsm6dsv16x_sensor_hub_12_t sensor_hub_12; 3832 lsm6dsv16x_sensor_hub_13_t sensor_hub_13; 3833 lsm6dsv16x_sensor_hub_14_t sensor_hub_14; 3834 lsm6dsv16x_sensor_hub_15_t sensor_hub_15; 3835 lsm6dsv16x_sensor_hub_16_t sensor_hub_16; 3836 lsm6dsv16x_sensor_hub_17_t sensor_hub_17; 3837 lsm6dsv16x_sensor_hub_18_t sensor_hub_18; 3838 lsm6dsv16x_master_config_t master_config; 3839 lsm6dsv16x_slv0_add_t slv0_add; 3840 lsm6dsv16x_slv0_subadd_t slv0_subadd; 3841 lsm6dsv16x_slv0_config_t slv0_config; 3842 lsm6dsv16x_slv1_add_t slv1_add; 3843 lsm6dsv16x_slv1_subadd_t slv1_subadd; 3844 lsm6dsv16x_slv1_config_t slv1_config; 3845 lsm6dsv16x_slv2_add_t slv2_add; 3846 lsm6dsv16x_slv2_subadd_t slv2_subadd; 3847 lsm6dsv16x_slv2_config_t slv2_config; 3848 lsm6dsv16x_slv3_add_t slv3_add; 3849 lsm6dsv16x_slv3_subadd_t slv3_subadd; 3850 lsm6dsv16x_slv3_config_t slv3_config; 3851 lsm6dsv16x_datawrite_slv0_t datawrite_slv0; 3852 lsm6dsv16x_status_master_t status_master; 3853 bitwise_t bitwise; 3854 uint8_t byte; 3855 } lsm6dsv16x_reg_t; 3856 3857 /** 3858 * @} 3859 * 3860 */ 3861 3862 #ifndef __weak 3863 #define __weak __attribute__((weak)) 3864 #endif /* __weak */ 3865 3866 /* 3867 * These are the basic platform dependent I/O routines to read 3868 * and write device registers connected on a standard bus. 3869 * The driver keeps offering a default implementation based on function 3870 * pointers to read/write routines for backward compatibility. 3871 * The __weak directive allows the final application to overwrite 3872 * them with a custom implementation. 3873 */ 3874 3875 int32_t lsm6dsv16x_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 3876 uint8_t *data, 3877 uint16_t len); 3878 int32_t lsm6dsv16x_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 3879 uint8_t *data, 3880 uint16_t len); 3881 3882 float_t lsm6dsv16x_from_sflp_to_mg(int16_t lsb); 3883 float_t lsm6dsv16x_from_fs2_to_mg(int16_t lsb); 3884 float_t lsm6dsv16x_from_fs4_to_mg(int16_t lsb); 3885 float_t lsm6dsv16x_from_fs8_to_mg(int16_t lsb); 3886 float_t lsm6dsv16x_from_fs16_to_mg(int16_t lsb); 3887 3888 float_t lsm6dsv16x_from_fs125_to_mdps(int16_t lsb); 3889 float_t lsm6dsv16x_from_fs500_to_mdps(int16_t lsb); 3890 float_t lsm6dsv16x_from_fs250_to_mdps(int16_t lsb); 3891 float_t lsm6dsv16x_from_fs1000_to_mdps(int16_t lsb); 3892 float_t lsm6dsv16x_from_fs2000_to_mdps(int16_t lsb); 3893 float_t lsm6dsv16x_from_fs4000_to_mdps(int16_t lsb); 3894 3895 float_t lsm6dsv16x_from_lsb_to_celsius(int16_t lsb); 3896 3897 float_t lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb); 3898 3899 float_t lsm6dsv16x_from_lsb_to_mv(int16_t lsb); 3900 3901 int32_t lsm6dsv16x_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val); 3902 int32_t lsm6dsv16x_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val); 3903 3904 typedef struct 3905 { 3906 float_t z_mg; 3907 float_t y_mg; 3908 float_t x_mg; 3909 } lsm6dsv16x_xl_offset_mg_t; 3910 int32_t lsm6dsv16x_xl_offset_mg_set(stmdev_ctx_t *ctx, 3911 lsm6dsv16x_xl_offset_mg_t val); 3912 int32_t lsm6dsv16x_xl_offset_mg_get(stmdev_ctx_t *ctx, 3913 lsm6dsv16x_xl_offset_mg_t *val); 3914 3915 typedef enum 3916 { 3917 LSM6DSV16X_READY = 0x0, 3918 LSM6DSV16X_GLOBAL_RST = 0x1, 3919 LSM6DSV16X_RESTORE_CAL_PARAM = 0x2, 3920 LSM6DSV16X_RESTORE_CTRL_REGS = 0x4, 3921 } lsm6dsv16x_reset_t; 3922 int32_t lsm6dsv16x_reset_set(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val); 3923 int32_t lsm6dsv16x_reset_get(stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val); 3924 3925 typedef enum 3926 { 3927 LSM6DSV16X_MAIN_MEM_BANK = 0x0, 3928 LSM6DSV16X_EMBED_FUNC_MEM_BANK = 0x1, 3929 LSM6DSV16X_SENSOR_HUB_MEM_BANK = 0x2, 3930 } lsm6dsv16x_mem_bank_t; 3931 int32_t lsm6dsv16x_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val); 3932 int32_t lsm6dsv16x_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val); 3933 3934 int32_t lsm6dsv16x_device_id_get(stmdev_ctx_t *ctx, uint8_t *val); 3935 3936 typedef enum 3937 { 3938 LSM6DSV16X_ODR_OFF = 0x0, 3939 LSM6DSV16X_ODR_AT_1Hz875 = 0x1, 3940 LSM6DSV16X_ODR_AT_7Hz5 = 0x2, 3941 LSM6DSV16X_ODR_AT_15Hz = 0x3, 3942 LSM6DSV16X_ODR_AT_30Hz = 0x4, 3943 LSM6DSV16X_ODR_AT_60Hz = 0x5, 3944 LSM6DSV16X_ODR_AT_120Hz = 0x6, 3945 LSM6DSV16X_ODR_AT_240Hz = 0x7, 3946 LSM6DSV16X_ODR_AT_480Hz = 0x8, 3947 LSM6DSV16X_ODR_AT_960Hz = 0x9, 3948 LSM6DSV16X_ODR_AT_1920Hz = 0xA, 3949 LSM6DSV16X_ODR_AT_3840Hz = 0xB, 3950 LSM6DSV16X_ODR_AT_7680Hz = 0xC, 3951 LSM6DSV16X_ODR_HA01_AT_15Hz625 = 0x13, 3952 LSM6DSV16X_ODR_HA01_AT_31Hz25 = 0x14, 3953 LSM6DSV16X_ODR_HA01_AT_62Hz5 = 0x15, 3954 LSM6DSV16X_ODR_HA01_AT_125Hz = 0x16, 3955 LSM6DSV16X_ODR_HA01_AT_250Hz = 0x17, 3956 LSM6DSV16X_ODR_HA01_AT_500Hz = 0x18, 3957 LSM6DSV16X_ODR_HA01_AT_1000Hz = 0x19, 3958 LSM6DSV16X_ODR_HA01_AT_2000Hz = 0x1A, 3959 LSM6DSV16X_ODR_HA01_AT_4000Hz = 0x1B, 3960 LSM6DSV16X_ODR_HA01_AT_8000Hz = 0x1C, 3961 LSM6DSV16X_ODR_HA02_AT_12Hz5 = 0x23, 3962 LSM6DSV16X_ODR_HA02_AT_25Hz = 0x24, 3963 LSM6DSV16X_ODR_HA02_AT_50Hz = 0x25, 3964 LSM6DSV16X_ODR_HA02_AT_100Hz = 0x26, 3965 LSM6DSV16X_ODR_HA02_AT_200Hz = 0x27, 3966 LSM6DSV16X_ODR_HA02_AT_400Hz = 0x28, 3967 LSM6DSV16X_ODR_HA02_AT_800Hz = 0x29, 3968 LSM6DSV16X_ODR_HA02_AT_1600Hz = 0x2A, 3969 LSM6DSV16X_ODR_HA02_AT_3200Hz = 0x2B, 3970 LSM6DSV16X_ODR_HA02_AT_6400Hz = 0x2C, 3971 } lsm6dsv16x_data_rate_t; 3972 int32_t lsm6dsv16x_xl_data_rate_set(stmdev_ctx_t *ctx, 3973 lsm6dsv16x_data_rate_t val); 3974 int32_t lsm6dsv16x_xl_data_rate_get(stmdev_ctx_t *ctx, 3975 lsm6dsv16x_data_rate_t *val); 3976 int32_t lsm6dsv16x_gy_data_rate_set(stmdev_ctx_t *ctx, 3977 lsm6dsv16x_data_rate_t val); 3978 int32_t lsm6dsv16x_gy_data_rate_get(stmdev_ctx_t *ctx, 3979 lsm6dsv16x_data_rate_t *val); 3980 3981 3982 typedef enum 3983 { 3984 LSM6DSV16X_XL_HIGH_PERFORMANCE_MD = 0x0, 3985 LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD = 0x1, 3986 LSM6DSV16X_XL_ODR_TRIGGERED_MD = 0x3, 3987 LSM6DSV16X_XL_LOW_POWER_2_AVG_MD = 0x4, 3988 LSM6DSV16X_XL_LOW_POWER_4_AVG_MD = 0x5, 3989 LSM6DSV16X_XL_LOW_POWER_8_AVG_MD = 0x6, 3990 LSM6DSV16X_XL_NORMAL_MD = 0x7, 3991 } lsm6dsv16x_xl_mode_t; 3992 int32_t lsm6dsv16x_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val); 3993 int32_t lsm6dsv16x_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val); 3994 3995 typedef enum 3996 { 3997 LSM6DSV16X_GY_HIGH_PERFORMANCE_MD = 0x0, 3998 LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD = 0x1, 3999 LSM6DSV16X_GY_SLEEP_MD = 0x4, 4000 LSM6DSV16X_GY_LOW_POWER_MD = 0x5, 4001 } lsm6dsv16x_gy_mode_t; 4002 int32_t lsm6dsv16x_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val); 4003 int32_t lsm6dsv16x_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val); 4004 4005 int32_t lsm6dsv16x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 4006 int32_t lsm6dsv16x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 4007 4008 int32_t lsm6dsv16x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 4009 int32_t lsm6dsv16x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 4010 4011 int32_t lsm6dsv16x_odr_trig_cfg_set(stmdev_ctx_t *ctx, uint8_t val); 4012 int32_t lsm6dsv16x_odr_trig_cfg_get(stmdev_ctx_t *ctx, uint8_t *val); 4013 4014 typedef enum 4015 { 4016 LSM6DSV16X_DRDY_LATCHED = 0x0, 4017 LSM6DSV16X_DRDY_PULSED = 0x1, 4018 } lsm6dsv16x_data_ready_mode_t; 4019 int32_t lsm6dsv16x_data_ready_mode_set(stmdev_ctx_t *ctx, 4020 lsm6dsv16x_data_ready_mode_t val); 4021 int32_t lsm6dsv16x_data_ready_mode_get(stmdev_ctx_t *ctx, 4022 lsm6dsv16x_data_ready_mode_t *val); 4023 4024 typedef struct 4025 { 4026 uint8_t enable : 1; /* interrupt enable */ 4027 uint8_t lir : 1; /* interrupt pulsed or latched */ 4028 } lsm6dsv16x_interrupt_mode_t; 4029 int32_t lsm6dsv16x_interrupt_enable_set(stmdev_ctx_t *ctx, 4030 lsm6dsv16x_interrupt_mode_t val); 4031 int32_t lsm6dsv16x_interrupt_enable_get(stmdev_ctx_t *ctx, 4032 lsm6dsv16x_interrupt_mode_t *val); 4033 4034 typedef enum 4035 { 4036 LSM6DSV16X_125dps = 0x0, 4037 LSM6DSV16X_250dps = 0x1, 4038 LSM6DSV16X_500dps = 0x2, 4039 LSM6DSV16X_1000dps = 0x3, 4040 LSM6DSV16X_2000dps = 0x4, 4041 LSM6DSV16X_4000dps = 0xc, 4042 } lsm6dsv16x_gy_full_scale_t; 4043 int32_t lsm6dsv16x_gy_full_scale_set(stmdev_ctx_t *ctx, 4044 lsm6dsv16x_gy_full_scale_t val); 4045 int32_t lsm6dsv16x_gy_full_scale_get(stmdev_ctx_t *ctx, 4046 lsm6dsv16x_gy_full_scale_t *val); 4047 4048 typedef enum 4049 { 4050 LSM6DSV16X_2g = 0x0, 4051 LSM6DSV16X_4g = 0x1, 4052 LSM6DSV16X_8g = 0x2, 4053 LSM6DSV16X_16g = 0x3, 4054 } lsm6dsv16x_xl_full_scale_t; 4055 int32_t lsm6dsv16x_xl_full_scale_set(stmdev_ctx_t *ctx, 4056 lsm6dsv16x_xl_full_scale_t val); 4057 int32_t lsm6dsv16x_xl_full_scale_get(stmdev_ctx_t *ctx, 4058 lsm6dsv16x_xl_full_scale_t *val); 4059 4060 int32_t lsm6dsv16x_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val); 4061 int32_t lsm6dsv16x_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val); 4062 4063 typedef enum 4064 { 4065 LSM6DSV16X_XL_ST_DISABLE = 0x0, 4066 LSM6DSV16X_XL_ST_POSITIVE = 0x1, 4067 LSM6DSV16X_XL_ST_NEGATIVE = 0x2, 4068 } lsm6dsv16x_xl_self_test_t; 4069 int32_t lsm6dsv16x_xl_self_test_set(stmdev_ctx_t *ctx, 4070 lsm6dsv16x_xl_self_test_t val); 4071 int32_t lsm6dsv16x_xl_self_test_get(stmdev_ctx_t *ctx, 4072 lsm6dsv16x_xl_self_test_t *val); 4073 4074 typedef enum 4075 { 4076 LSM6DSV16X_OIS_XL_ST_DISABLE = 0x0, 4077 LSM6DSV16X_OIS_XL_ST_POSITIVE = 0x1, 4078 LSM6DSV16X_OIS_XL_ST_NEGATIVE = 0x2, 4079 } lsm6dsv16x_ois_xl_self_test_t; 4080 int32_t lsm6dsv16x_ois_xl_self_test_set(stmdev_ctx_t *ctx, 4081 lsm6dsv16x_ois_xl_self_test_t val); 4082 int32_t lsm6dsv16x_ois_xl_self_test_get(stmdev_ctx_t *ctx, 4083 lsm6dsv16x_ois_xl_self_test_t *val); 4084 4085 typedef enum 4086 { 4087 LSM6DSV16X_GY_ST_DISABLE = 0x0, 4088 LSM6DSV16X_GY_ST_POSITIVE = 0x1, 4089 LSM6DSV16X_GY_ST_NEGATIVE = 0x2, 4090 4091 } lsm6dsv16x_gy_self_test_t; 4092 int32_t lsm6dsv16x_gy_self_test_set(stmdev_ctx_t *ctx, 4093 lsm6dsv16x_gy_self_test_t val); 4094 int32_t lsm6dsv16x_gy_self_test_get(stmdev_ctx_t *ctx, 4095 lsm6dsv16x_gy_self_test_t *val); 4096 4097 typedef enum 4098 { 4099 LSM6DSV16X_OIS_GY_ST_DISABLE = 0x0, 4100 LSM6DSV16X_OIS_GY_ST_POSITIVE = 0x1, 4101 LSM6DSV16X_OIS_GY_ST_NEGATIVE = 0x2, 4102 LSM6DSV16X_OIS_GY_ST_CLAMP_POS = 0x5, 4103 LSM6DSV16X_OIS_GY_ST_CLAMP_NEG = 0x6, 4104 4105 } lsm6dsv16x_ois_gy_self_test_t; 4106 int32_t lsm6dsv16x_ois_gy_self_test_set(stmdev_ctx_t *ctx, 4107 lsm6dsv16x_ois_gy_self_test_t val); 4108 int32_t lsm6dsv16x_ois_gy_self_test_get(stmdev_ctx_t *ctx, 4109 lsm6dsv16x_ois_gy_self_test_t *val); 4110 4111 typedef struct 4112 { 4113 uint8_t drdy_xl : 1; 4114 uint8_t drdy_gy : 1; 4115 uint8_t drdy_temp : 1; 4116 uint8_t drdy_ah_qvar : 1; 4117 uint8_t drdy_eis : 1; 4118 uint8_t drdy_ois : 1; 4119 uint8_t gy_settling : 1; 4120 uint8_t timestamp : 1; 4121 uint8_t free_fall : 1; 4122 uint8_t wake_up : 1; 4123 uint8_t wake_up_z : 1; 4124 uint8_t wake_up_y : 1; 4125 uint8_t wake_up_x : 1; 4126 uint8_t single_tap : 1; 4127 uint8_t double_tap : 1; 4128 uint8_t tap_z : 1; 4129 uint8_t tap_y : 1; 4130 uint8_t tap_x : 1; 4131 uint8_t tap_sign : 1; 4132 uint8_t six_d : 1; 4133 uint8_t six_d_xl : 1; 4134 uint8_t six_d_xh : 1; 4135 uint8_t six_d_yl : 1; 4136 uint8_t six_d_yh : 1; 4137 uint8_t six_d_zl : 1; 4138 uint8_t six_d_zh : 1; 4139 uint8_t sleep_change : 1; 4140 uint8_t sleep_state : 1; 4141 uint8_t step_detector : 1; 4142 uint8_t step_count_inc : 1; 4143 uint8_t step_count_overflow : 1; 4144 uint8_t step_on_delta_time : 1; 4145 uint8_t emb_func_stand_by : 1; 4146 uint8_t emb_func_time_exceed : 1; 4147 uint8_t tilt : 1; 4148 uint8_t sig_mot : 1; 4149 uint8_t fsm_lc : 1; 4150 uint8_t fsm1 : 1; 4151 uint8_t fsm2 : 1; 4152 uint8_t fsm3 : 1; 4153 uint8_t fsm4 : 1; 4154 uint8_t fsm5 : 1; 4155 uint8_t fsm6 : 1; 4156 uint8_t fsm7 : 1; 4157 uint8_t fsm8 : 1; 4158 uint8_t mlc1 : 1; 4159 uint8_t mlc2 : 1; 4160 uint8_t mlc3 : 1; 4161 uint8_t mlc4 : 1; 4162 uint8_t sh_endop : 1; 4163 uint8_t sh_slave0_nack : 1; 4164 uint8_t sh_slave1_nack : 1; 4165 uint8_t sh_slave2_nack : 1; 4166 uint8_t sh_slave3_nack : 1; 4167 uint8_t sh_wr_once : 1; 4168 uint8_t fifo_bdr : 1; 4169 uint8_t fifo_full : 1; 4170 uint8_t fifo_ovr : 1; 4171 uint8_t fifo_th : 1; 4172 } lsm6dsv16x_all_sources_t; 4173 int32_t lsm6dsv16x_all_sources_get(stmdev_ctx_t *ctx, 4174 lsm6dsv16x_all_sources_t *val); 4175 4176 typedef struct 4177 { 4178 uint8_t drdy_xl : 1; 4179 uint8_t drdy_g : 1; 4180 uint8_t drdy_g_eis : 1; 4181 uint8_t fifo_th : 1; 4182 uint8_t fifo_ovr : 1; 4183 uint8_t fifo_full : 1; 4184 uint8_t cnt_bdr : 1; 4185 uint8_t emb_func_endop : 1; 4186 uint8_t timestamp : 1; 4187 uint8_t shub : 1; 4188 uint8_t emb_func : 1; 4189 uint8_t sixd : 1; 4190 uint8_t single_tap : 1; 4191 uint8_t double_tap : 1; 4192 uint8_t wakeup : 1; 4193 uint8_t freefall : 1; 4194 uint8_t sleep_change : 1; 4195 } lsm6dsv16x_pin_int_route_t; 4196 int32_t lsm6dsv16x_pin_int1_route_set(stmdev_ctx_t *ctx, 4197 lsm6dsv16x_pin_int_route_t *val); 4198 int32_t lsm6dsv16x_pin_int1_route_get(stmdev_ctx_t *ctx, 4199 lsm6dsv16x_pin_int_route_t *val); 4200 int32_t lsm6dsv16x_pin_int2_route_set(stmdev_ctx_t *ctx, 4201 lsm6dsv16x_pin_int_route_t *val); 4202 int32_t lsm6dsv16x_pin_int2_route_get(stmdev_ctx_t *ctx, 4203 lsm6dsv16x_pin_int_route_t *val); 4204 4205 typedef struct 4206 { 4207 uint8_t drdy_xl : 1; 4208 uint8_t drdy_gy : 1; 4209 uint8_t drdy_temp : 1; 4210 } lsm6dsv16x_data_ready_t; 4211 int32_t lsm6dsv16x_flag_data_ready_get(stmdev_ctx_t *ctx, 4212 lsm6dsv16x_data_ready_t *val); 4213 4214 int32_t lsm6dsv16x_int_ack_mask_set(stmdev_ctx_t *ctx, uint8_t val); 4215 int32_t lsm6dsv16x_int_ack_mask_get(stmdev_ctx_t *ctx, uint8_t *val); 4216 4217 int32_t lsm6dsv16x_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 4218 4219 int32_t lsm6dsv16x_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 4220 4221 int32_t lsm6dsv16x_ois_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 4222 4223 int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(stmdev_ctx_t *ctx, 4224 int16_t *val); 4225 4226 int32_t lsm6dsv16x_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 4227 4228 int32_t lsm6dsv16x_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 4229 4230 int32_t lsm6dsv16x_ois_dual_acceleration_raw_get(stmdev_ctx_t *ctx, 4231 int16_t *val); 4232 4233 int32_t lsm6dsv16x_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val); 4234 4235 int32_t lsm6dsv16x_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val); 4236 4237 int32_t lsm6dsv16x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 4238 uint8_t *buf, uint8_t len); 4239 int32_t lsm6dsv16x_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, 4240 uint8_t len); 4241 4242 int32_t lsm6dsv16x_emb_function_dbg_set(stmdev_ctx_t *ctx, uint8_t val); 4243 int32_t lsm6dsv16x_emb_function_dbg_get(stmdev_ctx_t *ctx, uint8_t *val); 4244 4245 typedef enum 4246 { 4247 LSM6DSV16X_DEN_ACT_LOW = 0x0, 4248 LSM6DSV16X_DEN_ACT_HIGH = 0x1, 4249 } lsm6dsv16x_den_polarity_t; 4250 int32_t lsm6dsv16x_den_polarity_set(stmdev_ctx_t *ctx, 4251 lsm6dsv16x_den_polarity_t val); 4252 int32_t lsm6dsv16x_den_polarity_get(stmdev_ctx_t *ctx, 4253 lsm6dsv16x_den_polarity_t *val); 4254 4255 typedef struct 4256 { 4257 uint8_t stamp_in_gy_data : 1; 4258 uint8_t stamp_in_xl_data : 1; 4259 uint8_t den_x : 1; 4260 uint8_t den_y : 1; 4261 uint8_t den_z : 1; 4262 enum 4263 { 4264 DEN_NOT_DEFINED = 0x00, 4265 LEVEL_TRIGGER = 0x02, 4266 LEVEL_LATCHED = 0x03, 4267 } mode; 4268 } lsm6dsv16x_den_conf_t; 4269 int32_t lsm6dsv16x_den_conf_set(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val); 4270 int32_t lsm6dsv16x_den_conf_get(stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val); 4271 4272 typedef enum 4273 { 4274 LSM6DSV16X_EIS_125dps = 0x0, 4275 LSM6DSV16X_EIS_250dps = 0x1, 4276 LSM6DSV16X_EIS_500dps = 0x2, 4277 LSM6DSV16X_EIS_1000dps = 0x3, 4278 LSM6DSV16X_EIS_2000dps = 0x4, 4279 } lsm6dsv16x_eis_gy_full_scale_t; 4280 int32_t lsm6dsv16x_eis_gy_full_scale_set(stmdev_ctx_t *ctx, 4281 lsm6dsv16x_eis_gy_full_scale_t val); 4282 int32_t lsm6dsv16x_eis_gy_full_scale_get(stmdev_ctx_t *ctx, 4283 lsm6dsv16x_eis_gy_full_scale_t *val); 4284 4285 int32_t lsm6dsv16x_eis_gy_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); 4286 int32_t lsm6dsv16x_eis_gy_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); 4287 4288 typedef enum 4289 { 4290 LSM6DSV16X_EIS_ODR_OFF = 0x0, 4291 LSM6DSV16X_EIS_1920Hz = 0x1, 4292 LSM6DSV16X_EIS_960Hz = 0x2, 4293 } lsm6dsv16x_gy_eis_data_rate_t; 4294 int32_t lsm6dsv16x_gy_eis_data_rate_set(stmdev_ctx_t *ctx, 4295 lsm6dsv16x_gy_eis_data_rate_t val); 4296 int32_t lsm6dsv16x_gy_eis_data_rate_get(stmdev_ctx_t *ctx, 4297 lsm6dsv16x_gy_eis_data_rate_t *val); 4298 4299 int32_t lsm6dsv16x_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); 4300 int32_t lsm6dsv16x_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); 4301 4302 int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val); 4303 int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 4304 4305 typedef enum 4306 { 4307 LSM6DSV16X_CMP_DISABLE = 0x0, 4308 LSM6DSV16X_CMP_8_TO_1 = 0x1, 4309 LSM6DSV16X_CMP_16_TO_1 = 0x2, 4310 LSM6DSV16X_CMP_32_TO_1 = 0x3, 4311 } lsm6dsv16x_fifo_compress_algo_t; 4312 int32_t lsm6dsv16x_fifo_compress_algo_set(stmdev_ctx_t *ctx, 4313 lsm6dsv16x_fifo_compress_algo_t val); 4314 int32_t lsm6dsv16x_fifo_compress_algo_get(stmdev_ctx_t *ctx, 4315 lsm6dsv16x_fifo_compress_algo_t *val); 4316 4317 int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 4318 uint8_t val); 4319 int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 4320 uint8_t *val); 4321 4322 int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx, 4323 uint8_t val); 4324 int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx, 4325 uint8_t *val); 4326 4327 int32_t lsm6dsv16x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 4328 int32_t lsm6dsv16x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 4329 4330 typedef enum 4331 { 4332 LSM6DSV16X_XL_NOT_BATCHED = 0x0, 4333 LSM6DSV16X_XL_BATCHED_AT_1Hz875 = 0x1, 4334 LSM6DSV16X_XL_BATCHED_AT_7Hz5 = 0x2, 4335 LSM6DSV16X_XL_BATCHED_AT_15Hz = 0x3, 4336 LSM6DSV16X_XL_BATCHED_AT_30Hz = 0x4, 4337 LSM6DSV16X_XL_BATCHED_AT_60Hz = 0x5, 4338 LSM6DSV16X_XL_BATCHED_AT_120Hz = 0x6, 4339 LSM6DSV16X_XL_BATCHED_AT_240Hz = 0x7, 4340 LSM6DSV16X_XL_BATCHED_AT_480Hz = 0x8, 4341 LSM6DSV16X_XL_BATCHED_AT_960Hz = 0x9, 4342 LSM6DSV16X_XL_BATCHED_AT_1920Hz = 0xa, 4343 LSM6DSV16X_XL_BATCHED_AT_3840Hz = 0xb, 4344 LSM6DSV16X_XL_BATCHED_AT_7680Hz = 0xc, 4345 } lsm6dsv16x_fifo_xl_batch_t; 4346 int32_t lsm6dsv16x_fifo_xl_batch_set(stmdev_ctx_t *ctx, 4347 lsm6dsv16x_fifo_xl_batch_t val); 4348 int32_t lsm6dsv16x_fifo_xl_batch_get(stmdev_ctx_t *ctx, 4349 lsm6dsv16x_fifo_xl_batch_t *val); 4350 4351 typedef enum 4352 { 4353 LSM6DSV16X_GY_NOT_BATCHED = 0x0, 4354 LSM6DSV16X_GY_BATCHED_AT_1Hz875 = 0x1, 4355 LSM6DSV16X_GY_BATCHED_AT_7Hz5 = 0x2, 4356 LSM6DSV16X_GY_BATCHED_AT_15Hz = 0x3, 4357 LSM6DSV16X_GY_BATCHED_AT_30Hz = 0x4, 4358 LSM6DSV16X_GY_BATCHED_AT_60Hz = 0x5, 4359 LSM6DSV16X_GY_BATCHED_AT_120Hz = 0x6, 4360 LSM6DSV16X_GY_BATCHED_AT_240Hz = 0x7, 4361 LSM6DSV16X_GY_BATCHED_AT_480Hz = 0x8, 4362 LSM6DSV16X_GY_BATCHED_AT_960Hz = 0x9, 4363 LSM6DSV16X_GY_BATCHED_AT_1920Hz = 0xa, 4364 LSM6DSV16X_GY_BATCHED_AT_3840Hz = 0xb, 4365 LSM6DSV16X_GY_BATCHED_AT_7680Hz = 0xc, 4366 } lsm6dsv16x_fifo_gy_batch_t; 4367 int32_t lsm6dsv16x_fifo_gy_batch_set(stmdev_ctx_t *ctx, 4368 lsm6dsv16x_fifo_gy_batch_t val); 4369 int32_t lsm6dsv16x_fifo_gy_batch_get(stmdev_ctx_t *ctx, 4370 lsm6dsv16x_fifo_gy_batch_t *val); 4371 4372 typedef enum 4373 { 4374 LSM6DSV16X_BYPASS_MODE = 0x0, 4375 LSM6DSV16X_FIFO_MODE = 0x1, 4376 LSM6DSV16X_STREAM_WTM_TO_FULL_MODE = 0x2, 4377 LSM6DSV16X_STREAM_TO_FIFO_MODE = 0x3, 4378 LSM6DSV16X_BYPASS_TO_STREAM_MODE = 0x4, 4379 LSM6DSV16X_STREAM_MODE = 0x6, 4380 LSM6DSV16X_BYPASS_TO_FIFO_MODE = 0x7, 4381 } lsm6dsv16x_fifo_mode_t; 4382 int32_t lsm6dsv16x_fifo_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val); 4383 int32_t lsm6dsv16x_fifo_mode_get(stmdev_ctx_t *ctx, 4384 lsm6dsv16x_fifo_mode_t *val); 4385 4386 int32_t lsm6dsv16x_fifo_gy_eis_batch_set(stmdev_ctx_t *ctx, uint8_t val); 4387 int32_t lsm6dsv16x_fifo_gy_eis_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 4388 4389 typedef enum 4390 { 4391 LSM6DSV16X_TEMP_NOT_BATCHED = 0x0, 4392 LSM6DSV16X_TEMP_BATCHED_AT_1Hz875 = 0x1, 4393 LSM6DSV16X_TEMP_BATCHED_AT_15Hz = 0x2, 4394 LSM6DSV16X_TEMP_BATCHED_AT_60Hz = 0x3, 4395 } lsm6dsv16x_fifo_temp_batch_t; 4396 int32_t lsm6dsv16x_fifo_temp_batch_set(stmdev_ctx_t *ctx, 4397 lsm6dsv16x_fifo_temp_batch_t val); 4398 int32_t lsm6dsv16x_fifo_temp_batch_get(stmdev_ctx_t *ctx, 4399 lsm6dsv16x_fifo_temp_batch_t *val); 4400 4401 typedef enum 4402 { 4403 LSM6DSV16X_TMSTMP_NOT_BATCHED = 0x0, 4404 LSM6DSV16X_TMSTMP_DEC_1 = 0x1, 4405 LSM6DSV16X_TMSTMP_DEC_8 = 0x2, 4406 LSM6DSV16X_TMSTMP_DEC_32 = 0x3, 4407 } lsm6dsv16x_fifo_timestamp_batch_t; 4408 int32_t lsm6dsv16x_fifo_timestamp_batch_set(stmdev_ctx_t *ctx, 4409 lsm6dsv16x_fifo_timestamp_batch_t val); 4410 int32_t lsm6dsv16x_fifo_timestamp_batch_get(stmdev_ctx_t *ctx, 4411 lsm6dsv16x_fifo_timestamp_batch_t *val); 4412 4413 int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx, 4414 uint16_t val); 4415 int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx, 4416 uint16_t *val); 4417 4418 typedef enum 4419 { 4420 LSM6DSV16X_XL_BATCH_EVENT = 0x0, 4421 LSM6DSV16X_GY_BATCH_EVENT = 0x1, 4422 LSM6DSV16X_GY_EIS_BATCH_EVENT = 0x2, 4423 } lsm6dsv16x_fifo_batch_cnt_event_t; 4424 int32_t lsm6dsv16x_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx, 4425 lsm6dsv16x_fifo_batch_cnt_event_t val); 4426 int32_t lsm6dsv16x_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx, 4427 lsm6dsv16x_fifo_batch_cnt_event_t *val); 4428 4429 typedef struct 4430 { 4431 uint16_t fifo_level : 9; 4432 uint8_t fifo_bdr : 1; 4433 uint8_t fifo_full : 1; 4434 uint8_t fifo_ovr : 1; 4435 uint8_t fifo_th : 1; 4436 } lsm6dsv16x_fifo_status_t; 4437 4438 int32_t lsm6dsv16x_fifo_status_get(stmdev_ctx_t *ctx, 4439 lsm6dsv16x_fifo_status_t *val); 4440 4441 typedef struct 4442 { 4443 enum 4444 { 4445 LSM6DSV16X_FIFO_EMPTY = 0x0, 4446 LSM6DSV16X_GY_NC_TAG = 0x1, 4447 LSM6DSV16X_XL_NC_TAG = 0x2, 4448 LSM6DSV16X_TEMPERATURE_TAG = 0x3, 4449 LSM6DSV16X_TIMESTAMP_TAG = 0x4, 4450 LSM6DSV16X_CFG_CHANGE_TAG = 0x5, 4451 LSM6DSV16X_XL_NC_T_2_TAG = 0x6, 4452 LSM6DSV16X_XL_NC_T_1_TAG = 0x7, 4453 LSM6DSV16X_XL_2XC_TAG = 0x8, 4454 LSM6DSV16X_XL_3XC_TAG = 0x9, 4455 LSM6DSV16X_GY_NC_T_2_TAG = 0xA, 4456 LSM6DSV16X_GY_NC_T_1_TAG = 0xB, 4457 LSM6DSV16X_GY_2XC_TAG = 0xC, 4458 LSM6DSV16X_GY_3XC_TAG = 0xD, 4459 LSM6DSV16X_SENSORHUB_SLAVE0_TAG = 0xE, 4460 LSM6DSV16X_SENSORHUB_SLAVE1_TAG = 0xF, 4461 LSM6DSV16X_SENSORHUB_SLAVE2_TAG = 0x10, 4462 LSM6DSV16X_SENSORHUB_SLAVE3_TAG = 0x11, 4463 LSM6DSV16X_STEP_COUNTER_TAG = 0x12, 4464 LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, 4465 LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG = 0x16, 4466 LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG = 0x17, 4467 LSM6DSV16X_SENSORHUB_NACK_TAG = 0x19, 4468 LSM6DSV16X_MLC_RESULT_TAG = 0x1A, 4469 LSM6DSV16X_MLC_FILTER = 0x1B, 4470 LSM6DSV16X_MLC_FEATURE = 0x1C, 4471 LSM6DSV16X_XL_DUAL_CORE = 0x1D, 4472 LSM6DSV16X_GY_ENHANCED_EIS = 0x1E, 4473 } tag; 4474 uint8_t cnt; 4475 uint8_t data[6]; 4476 } lsm6dsv16x_fifo_out_raw_t; 4477 int32_t lsm6dsv16x_fifo_out_raw_get(stmdev_ctx_t *ctx, 4478 lsm6dsv16x_fifo_out_raw_t *val); 4479 4480 int32_t lsm6dsv16x_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val); 4481 int32_t lsm6dsv16x_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 4482 4483 int32_t lsm6dsv16x_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val); 4484 int32_t lsm6dsv16x_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 4485 4486 int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val); 4487 int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 4488 4489 int32_t lsm6dsv16x_fifo_sh_batch_slave_set(stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); 4490 int32_t lsm6dsv16x_fifo_sh_batch_slave_get(stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); 4491 4492 typedef struct 4493 { 4494 uint8_t game_rotation : 1; 4495 uint8_t gravity : 1; 4496 uint8_t gbias : 1; 4497 } lsm6dsv16x_fifo_sflp_raw_t; 4498 int32_t lsm6dsv16x_fifo_sflp_batch_set(stmdev_ctx_t *ctx, 4499 lsm6dsv16x_fifo_sflp_raw_t val); 4500 int32_t lsm6dsv16x_fifo_sflp_batch_get(stmdev_ctx_t *ctx, 4501 lsm6dsv16x_fifo_sflp_raw_t *val); 4502 4503 typedef enum 4504 { 4505 LSM6DSV16X_AUTO = 0x0, 4506 LSM6DSV16X_ALWAYS_ACTIVE = 0x1, 4507 } lsm6dsv16x_filt_anti_spike_t; 4508 int32_t lsm6dsv16x_filt_anti_spike_set(stmdev_ctx_t *ctx, 4509 lsm6dsv16x_filt_anti_spike_t val); 4510 int32_t lsm6dsv16x_filt_anti_spike_get(stmdev_ctx_t *ctx, 4511 lsm6dsv16x_filt_anti_spike_t *val); 4512 4513 typedef struct 4514 { 4515 uint8_t drdy : 1; 4516 uint8_t ois_drdy : 1; 4517 uint8_t irq_xl : 1; 4518 uint8_t irq_g : 1; 4519 } lsm6dsv16x_filt_settling_mask_t; 4520 int32_t lsm6dsv16x_filt_settling_mask_set(stmdev_ctx_t *ctx, 4521 lsm6dsv16x_filt_settling_mask_t val); 4522 int32_t lsm6dsv16x_filt_settling_mask_get(stmdev_ctx_t *ctx, 4523 lsm6dsv16x_filt_settling_mask_t *val); 4524 4525 typedef struct 4526 { 4527 uint8_t ois_drdy : 1; 4528 } lsm6dsv16x_filt_ois_settling_mask_t; 4529 int32_t lsm6dsv16x_filt_ois_settling_mask_set(stmdev_ctx_t *ctx, 4530 lsm6dsv16x_filt_ois_settling_mask_t val); 4531 int32_t lsm6dsv16x_filt_ois_settling_mask_get(stmdev_ctx_t *ctx, 4532 lsm6dsv16x_filt_ois_settling_mask_t *val); 4533 4534 typedef enum 4535 { 4536 LSM6DSV16X_GY_ULTRA_LIGHT = 0x0, 4537 LSM6DSV16X_GY_VERY_LIGHT = 0x1, 4538 LSM6DSV16X_GY_LIGHT = 0x2, 4539 LSM6DSV16X_GY_MEDIUM = 0x3, 4540 LSM6DSV16X_GY_STRONG = 0x4, 4541 LSM6DSV16X_GY_VERY_STRONG = 0x5, 4542 LSM6DSV16X_GY_AGGRESSIVE = 0x6, 4543 LSM6DSV16X_GY_XTREME = 0x7, 4544 } lsm6dsv16x_filt_gy_lp1_bandwidth_t; 4545 int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 4546 lsm6dsv16x_filt_gy_lp1_bandwidth_t val); 4547 int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 4548 lsm6dsv16x_filt_gy_lp1_bandwidth_t *val); 4549 4550 int32_t lsm6dsv16x_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 4551 int32_t lsm6dsv16x_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 4552 4553 typedef enum 4554 { 4555 LSM6DSV16X_XL_ULTRA_LIGHT = 0x0, 4556 LSM6DSV16X_XL_VERY_LIGHT = 0x1, 4557 LSM6DSV16X_XL_LIGHT = 0x2, 4558 LSM6DSV16X_XL_MEDIUM = 0x3, 4559 LSM6DSV16X_XL_STRONG = 0x4, 4560 LSM6DSV16X_XL_VERY_STRONG = 0x5, 4561 LSM6DSV16X_XL_AGGRESSIVE = 0x6, 4562 LSM6DSV16X_XL_XTREME = 0x7, 4563 } lsm6dsv16x_filt_xl_lp2_bandwidth_t; 4564 int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, 4565 lsm6dsv16x_filt_xl_lp2_bandwidth_t val); 4566 int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, 4567 lsm6dsv16x_filt_xl_lp2_bandwidth_t *val); 4568 4569 int32_t lsm6dsv16x_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 4570 int32_t lsm6dsv16x_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 4571 4572 int32_t lsm6dsv16x_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val); 4573 int32_t lsm6dsv16x_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val); 4574 4575 int32_t lsm6dsv16x_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); 4576 int32_t lsm6dsv16x_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); 4577 4578 typedef enum 4579 { 4580 LSM6DSV16X_HP_MD_NORMAL = 0x0, 4581 LSM6DSV16X_HP_MD_REFERENCE = 0x1, 4582 } lsm6dsv16x_filt_xl_hp_mode_t; 4583 int32_t lsm6dsv16x_filt_xl_hp_mode_set(stmdev_ctx_t *ctx, 4584 lsm6dsv16x_filt_xl_hp_mode_t val); 4585 int32_t lsm6dsv16x_filt_xl_hp_mode_get(stmdev_ctx_t *ctx, 4586 lsm6dsv16x_filt_xl_hp_mode_t *val); 4587 4588 typedef enum 4589 { 4590 LSM6DSV16X_WK_FEED_SLOPE = 0x0, 4591 LSM6DSV16X_WK_FEED_HIGH_PASS = 0x1, 4592 LSM6DSV16X_WK_FEED_LP_WITH_OFFSET = 0x2, 4593 } lsm6dsv16x_filt_wkup_act_feed_t; 4594 int32_t lsm6dsv16x_filt_wkup_act_feed_set(stmdev_ctx_t *ctx, 4595 lsm6dsv16x_filt_wkup_act_feed_t val); 4596 int32_t lsm6dsv16x_filt_wkup_act_feed_get(stmdev_ctx_t *ctx, 4597 lsm6dsv16x_filt_wkup_act_feed_t *val); 4598 4599 int32_t lsm6dsv16x_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val); 4600 int32_t lsm6dsv16x_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val); 4601 4602 typedef enum 4603 { 4604 LSM6DSV16X_SIXD_FEED_ODR_DIV_2 = 0x0, 4605 LSM6DSV16X_SIXD_FEED_LOW_PASS = 0x1, 4606 } lsm6dsv16x_filt_sixd_feed_t; 4607 int32_t lsm6dsv16x_filt_sixd_feed_set(stmdev_ctx_t *ctx, 4608 lsm6dsv16x_filt_sixd_feed_t val); 4609 int32_t lsm6dsv16x_filt_sixd_feed_get(stmdev_ctx_t *ctx, 4610 lsm6dsv16x_filt_sixd_feed_t *val); 4611 4612 typedef enum 4613 { 4614 LSM6DSV16X_EIS_LP_NORMAL = 0x0, 4615 LSM6DSV16X_EIS_LP_LIGHT = 0x1, 4616 } lsm6dsv16x_filt_gy_eis_lp_bandwidth_t; 4617 int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(stmdev_ctx_t *ctx, 4618 lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val); 4619 int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(stmdev_ctx_t *ctx, 4620 lsm6dsv16x_filt_gy_eis_lp_bandwidth_t *val); 4621 4622 typedef enum 4623 { 4624 LSM6DSV16X_OIS_GY_LP_NORMAL = 0x0, 4625 LSM6DSV16X_OIS_GY_LP_STRONG = 0x1, 4626 LSM6DSV16X_OIS_GY_LP_AGGRESSIVE = 0x2, 4627 LSM6DSV16X_OIS_GY_LP_LIGHT = 0x3, 4628 } lsm6dsv16x_filt_gy_ois_lp_bandwidth_t; 4629 int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, 4630 lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val); 4631 int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, 4632 lsm6dsv16x_filt_gy_ois_lp_bandwidth_t *val); 4633 4634 typedef enum 4635 { 4636 LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT = 0x0, 4637 LSM6DSV16X_OIS_XL_LP_VERY_LIGHT = 0x1, 4638 LSM6DSV16X_OIS_XL_LP_LIGHT = 0x2, 4639 LSM6DSV16X_OIS_XL_LP_NORMAL = 0x3, 4640 LSM6DSV16X_OIS_XL_LP_STRONG = 0x4, 4641 LSM6DSV16X_OIS_XL_LP_VERY_STRONG = 0x5, 4642 LSM6DSV16X_OIS_XL_LP_AGGRESSIVE = 0x6, 4643 LSM6DSV16X_OIS_XL_LP_XTREME = 0x7, 4644 } lsm6dsv16x_filt_xl_ois_lp_bandwidth_t; 4645 int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(stmdev_ctx_t *ctx, 4646 lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val); 4647 int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(stmdev_ctx_t *ctx, 4648 lsm6dsv16x_filt_xl_ois_lp_bandwidth_t *val); 4649 4650 typedef enum 4651 { 4652 LSM6DSV16X_PROTECT_CTRL_REGS = 0x0, 4653 LSM6DSV16X_WRITE_CTRL_REG = 0x1, 4654 } lsm6dsv16x_fsm_permission_t; 4655 int32_t lsm6dsv16x_fsm_permission_set(stmdev_ctx_t *ctx, 4656 lsm6dsv16x_fsm_permission_t val); 4657 int32_t lsm6dsv16x_fsm_permission_get(stmdev_ctx_t *ctx, 4658 lsm6dsv16x_fsm_permission_t *val); 4659 int32_t lsm6dsv16x_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val); 4660 4661 typedef struct 4662 { 4663 uint8_t fsm1_en : 1; 4664 uint8_t fsm2_en : 1; 4665 uint8_t fsm3_en : 1; 4666 uint8_t fsm4_en : 1; 4667 uint8_t fsm5_en : 1; 4668 uint8_t fsm6_en : 1; 4669 uint8_t fsm7_en : 1; 4670 uint8_t fsm8_en : 1; 4671 } lsm6dsv16x_fsm_mode_t; 4672 int32_t lsm6dsv16x_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val); 4673 int32_t lsm6dsv16x_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val); 4674 4675 int32_t lsm6dsv16x_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 4676 int32_t lsm6dsv16x_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 4677 4678 4679 typedef struct 4680 { 4681 uint8_t fsm_outs1; 4682 uint8_t fsm_outs2; 4683 uint8_t fsm_outs3; 4684 uint8_t fsm_outs4; 4685 uint8_t fsm_outs5; 4686 uint8_t fsm_outs6; 4687 uint8_t fsm_outs7; 4688 uint8_t fsm_outs8; 4689 } lsm6dsv16x_fsm_out_t; 4690 int32_t lsm6dsv16x_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val); 4691 4692 typedef enum 4693 { 4694 LSM6DSV16X_FSM_15Hz = 0x0, 4695 LSM6DSV16X_FSM_30Hz = 0x1, 4696 LSM6DSV16X_FSM_60Hz = 0x2, 4697 LSM6DSV16X_FSM_120Hz = 0x3, 4698 LSM6DSV16X_FSM_240Hz = 0x4, 4699 LSM6DSV16X_FSM_480Hz = 0x5, 4700 LSM6DSV16X_FSM_960Hz = 0x6, 4701 } lsm6dsv16x_fsm_data_rate_t; 4702 int32_t lsm6dsv16x_fsm_data_rate_set(stmdev_ctx_t *ctx, 4703 lsm6dsv16x_fsm_data_rate_t val); 4704 int32_t lsm6dsv16x_fsm_data_rate_get(stmdev_ctx_t *ctx, 4705 lsm6dsv16x_fsm_data_rate_t *val); 4706 4707 int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, 4708 uint16_t val); 4709 int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, 4710 uint16_t *val); 4711 4712 typedef struct 4713 { 4714 uint16_t z; 4715 uint16_t y; 4716 uint16_t x; 4717 } lsm6dsv16x_xl_fsm_ext_sens_offset_t; 4718 int32_t lsm6dsv16x_fsm_ext_sens_offset_set(stmdev_ctx_t *ctx, 4719 lsm6dsv16x_xl_fsm_ext_sens_offset_t val); 4720 int32_t lsm6dsv16x_fsm_ext_sens_offset_get(stmdev_ctx_t *ctx, 4721 lsm6dsv16x_xl_fsm_ext_sens_offset_t *val); 4722 4723 typedef struct 4724 { 4725 uint16_t xx; 4726 uint16_t xy; 4727 uint16_t xz; 4728 uint16_t yy; 4729 uint16_t yz; 4730 uint16_t zz; 4731 } lsm6dsv16x_xl_fsm_ext_sens_matrix_t; 4732 int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(stmdev_ctx_t *ctx, 4733 lsm6dsv16x_xl_fsm_ext_sens_matrix_t val); 4734 int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(stmdev_ctx_t *ctx, 4735 lsm6dsv16x_xl_fsm_ext_sens_matrix_t *val); 4736 4737 typedef enum 4738 { 4739 LSM6DSV16X_Z_EQ_Y = 0x0, 4740 LSM6DSV16X_Z_EQ_MIN_Y = 0x1, 4741 LSM6DSV16X_Z_EQ_X = 0x2, 4742 LSM6DSV16X_Z_EQ_MIN_X = 0x3, 4743 LSM6DSV16X_Z_EQ_MIN_Z = 0x4, 4744 LSM6DSV16X_Z_EQ_Z = 0x5, 4745 } lsm6dsv16x_fsm_ext_sens_z_orient_t; 4746 int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(stmdev_ctx_t *ctx, 4747 lsm6dsv16x_fsm_ext_sens_z_orient_t val); 4748 int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(stmdev_ctx_t *ctx, 4749 lsm6dsv16x_fsm_ext_sens_z_orient_t *val); 4750 4751 typedef enum 4752 { 4753 LSM6DSV16X_Y_EQ_Y = 0x0, 4754 LSM6DSV16X_Y_EQ_MIN_Y = 0x1, 4755 LSM6DSV16X_Y_EQ_X = 0x2, 4756 LSM6DSV16X_Y_EQ_MIN_X = 0x3, 4757 LSM6DSV16X_Y_EQ_MIN_Z = 0x4, 4758 LSM6DSV16X_Y_EQ_Z = 0x5, 4759 } lsm6dsv16x_fsm_ext_sens_y_orient_t; 4760 int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(stmdev_ctx_t *ctx, 4761 lsm6dsv16x_fsm_ext_sens_y_orient_t val); 4762 int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(stmdev_ctx_t *ctx, 4763 lsm6dsv16x_fsm_ext_sens_y_orient_t *val); 4764 4765 typedef enum 4766 { 4767 LSM6DSV16X_X_EQ_Y = 0x0, 4768 LSM6DSV16X_X_EQ_MIN_Y = 0x1, 4769 LSM6DSV16X_X_EQ_X = 0x2, 4770 LSM6DSV16X_X_EQ_MIN_X = 0x3, 4771 LSM6DSV16X_X_EQ_MIN_Z = 0x4, 4772 LSM6DSV16X_X_EQ_Z = 0x5, 4773 } lsm6dsv16x_fsm_ext_sens_x_orient_t; 4774 int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(stmdev_ctx_t *ctx, 4775 lsm6dsv16x_fsm_ext_sens_x_orient_t val); 4776 int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(stmdev_ctx_t *ctx, 4777 lsm6dsv16x_fsm_ext_sens_x_orient_t *val); 4778 4779 int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val); 4780 int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val); 4781 4782 int32_t lsm6dsv16x_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val); 4783 int32_t lsm6dsv16x_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val); 4784 4785 int32_t lsm6dsv16x_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val); 4786 int32_t lsm6dsv16x_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val); 4787 4788 int32_t lsm6dsv16x_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val); 4789 int32_t lsm6dsv16x_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val); 4790 4791 typedef enum 4792 { 4793 LSM6DSV16X_156_mg = 0x0, 4794 LSM6DSV16X_219_mg = 0x1, 4795 LSM6DSV16X_250_mg = 0x2, 4796 LSM6DSV16X_312_mg = 0x3, 4797 LSM6DSV16X_344_mg = 0x4, 4798 LSM6DSV16X_406_mg = 0x5, 4799 LSM6DSV16X_469_mg = 0x6, 4800 LSM6DSV16X_500_mg = 0x7, 4801 } lsm6dsv16x_ff_thresholds_t; 4802 int32_t lsm6dsv16x_ff_thresholds_set(stmdev_ctx_t *ctx, 4803 lsm6dsv16x_ff_thresholds_t val); 4804 int32_t lsm6dsv16x_ff_thresholds_get(stmdev_ctx_t *ctx, 4805 lsm6dsv16x_ff_thresholds_t *val); 4806 4807 typedef enum 4808 { 4809 LSM6DSV16X_MLC_OFF = 0x0, 4810 LSM6DSV16X_MLC_ON = 0x1, 4811 LSM6DSV16X_MLC_ON_BEFORE_FSM = 0x2, 4812 } lsm6dsv16x_mlc_mode_t; 4813 int32_t lsm6dsv16x_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val); 4814 int32_t lsm6dsv16x_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val); 4815 4816 typedef enum 4817 { 4818 LSM6DSV16X_MLC_15Hz = 0x0, 4819 LSM6DSV16X_MLC_30Hz = 0x1, 4820 LSM6DSV16X_MLC_60Hz = 0x2, 4821 LSM6DSV16X_MLC_120Hz = 0x3, 4822 LSM6DSV16X_MLC_240Hz = 0x4, 4823 LSM6DSV16X_MLC_480Hz = 0x5, 4824 LSM6DSV16X_MLC_960Hz = 0x6, 4825 } lsm6dsv16x_mlc_data_rate_t; 4826 int32_t lsm6dsv16x_mlc_data_rate_set(stmdev_ctx_t *ctx, 4827 lsm6dsv16x_mlc_data_rate_t val); 4828 int32_t lsm6dsv16x_mlc_data_rate_get(stmdev_ctx_t *ctx, 4829 lsm6dsv16x_mlc_data_rate_t *val); 4830 4831 typedef struct 4832 { 4833 uint8_t mlc1_src; 4834 uint8_t mlc2_src; 4835 uint8_t mlc3_src; 4836 uint8_t mlc4_src; 4837 } lsm6dsv16x_mlc_out_t; 4838 int32_t lsm6dsv16x_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val); 4839 4840 int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(stmdev_ctx_t *ctx, 4841 uint16_t val); 4842 int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(stmdev_ctx_t *ctx, 4843 uint16_t *val); 4844 4845 typedef enum 4846 { 4847 LSM6DSV16X_OIS_CTRL_FROM_OIS = 0x0, 4848 LSM6DSV16X_OIS_CTRL_FROM_UI = 0x1, 4849 } lsm6dsv16x_ois_ctrl_mode_t; 4850 int32_t lsm6dsv16x_ois_ctrl_mode_set(stmdev_ctx_t *ctx, 4851 lsm6dsv16x_ois_ctrl_mode_t val); 4852 int32_t lsm6dsv16x_ois_ctrl_mode_get(stmdev_ctx_t *ctx, 4853 lsm6dsv16x_ois_ctrl_mode_t *val); 4854 4855 int32_t lsm6dsv16x_ois_reset_set(stmdev_ctx_t *ctx, int8_t val); 4856 int32_t lsm6dsv16x_ois_reset_get(stmdev_ctx_t *ctx, int8_t *val); 4857 4858 int32_t lsm6dsv16x_ois_interface_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 4859 int32_t lsm6dsv16x_ois_interface_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 4860 4861 typedef struct 4862 { 4863 uint8_t ack : 1; 4864 uint8_t req : 1; 4865 } lsm6dsv16x_ois_handshake_t; 4866 int32_t lsm6dsv16x_ois_handshake_from_ui_set(stmdev_ctx_t *ctx, 4867 lsm6dsv16x_ois_handshake_t val); 4868 int32_t lsm6dsv16x_ois_handshake_from_ui_get(stmdev_ctx_t *ctx, 4869 lsm6dsv16x_ois_handshake_t *val); 4870 int32_t lsm6dsv16x_ois_handshake_from_ois_set(stmdev_ctx_t *ctx, 4871 lsm6dsv16x_ois_handshake_t val); 4872 int32_t lsm6dsv16x_ois_handshake_from_ois_get(stmdev_ctx_t *ctx, 4873 lsm6dsv16x_ois_handshake_t *val); 4874 4875 int32_t lsm6dsv16x_ois_shared_set(stmdev_ctx_t *ctx, uint8_t val[6]); 4876 int32_t lsm6dsv16x_ois_shared_get(stmdev_ctx_t *ctx, uint8_t val[6]); 4877 4878 int32_t lsm6dsv16x_ois_on_spi2_set(stmdev_ctx_t *ctx, uint8_t val); 4879 int32_t lsm6dsv16x_ois_on_spi2_get(stmdev_ctx_t *ctx, uint8_t *val); 4880 4881 typedef struct 4882 { 4883 uint8_t gy : 1; 4884 uint8_t xl : 1; 4885 } lsm6dsv16x_ois_chain_t; 4886 int32_t lsm6dsv16x_ois_chain_set(stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val); 4887 int32_t lsm6dsv16x_ois_chain_get(stmdev_ctx_t *ctx, 4888 lsm6dsv16x_ois_chain_t *val); 4889 4890 typedef enum 4891 { 4892 LSM6DSV16X_OIS_125dps = 0x0, 4893 LSM6DSV16X_OIS_250dps = 0x1, 4894 LSM6DSV16X_OIS_500dps = 0x2, 4895 LSM6DSV16X_OIS_1000dps = 0x3, 4896 LSM6DSV16X_OIS_2000dps = 0x4, 4897 } lsm6dsv16x_ois_gy_full_scale_t; 4898 int32_t lsm6dsv16x_ois_gy_full_scale_set(stmdev_ctx_t *ctx, 4899 lsm6dsv16x_ois_gy_full_scale_t val); 4900 int32_t lsm6dsv16x_ois_gy_full_scale_get(stmdev_ctx_t *ctx, 4901 lsm6dsv16x_ois_gy_full_scale_t *val); 4902 4903 typedef enum 4904 { 4905 LSM6DSV16X_OIS_2g = 0x0, 4906 LSM6DSV16X_OIS_4g = 0x1, 4907 LSM6DSV16X_OIS_8g = 0x2, 4908 LSM6DSV16X_OIS_16g = 0x3, 4909 } lsm6dsv16x_ois_xl_full_scale_t; 4910 int32_t lsm6dsv16x_ois_xl_full_scale_set(stmdev_ctx_t *ctx, 4911 lsm6dsv16x_ois_xl_full_scale_t val); 4912 int32_t lsm6dsv16x_ois_xl_full_scale_get(stmdev_ctx_t *ctx, 4913 lsm6dsv16x_ois_xl_full_scale_t *val); 4914 4915 typedef enum 4916 { 4917 LSM6DSV16X_DEG_80 = 0x0, 4918 LSM6DSV16X_DEG_70 = 0x1, 4919 LSM6DSV16X_DEG_60 = 0x2, 4920 LSM6DSV16X_DEG_50 = 0x3, 4921 } lsm6dsv16x_6d_threshold_t; 4922 int32_t lsm6dsv16x_6d_threshold_set(stmdev_ctx_t *ctx, 4923 lsm6dsv16x_6d_threshold_t val); 4924 int32_t lsm6dsv16x_6d_threshold_get(stmdev_ctx_t *ctx, 4925 lsm6dsv16x_6d_threshold_t *val); 4926 4927 int32_t lsm6dsv16x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 4928 int32_t lsm6dsv16x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 4929 4930 typedef enum 4931 { 4932 LSM6DSV16X_2400MOhm = 0x0, 4933 LSM6DSV16X_730MOhm = 0x1, 4934 LSM6DSV16X_300MOhm = 0x2, 4935 LSM6DSV16X_255MOhm = 0x3, 4936 } lsm6dsv16x_ah_qvar_zin_t; 4937 int32_t lsm6dsv16x_ah_qvar_zin_set(stmdev_ctx_t *ctx, 4938 lsm6dsv16x_ah_qvar_zin_t val); 4939 int32_t lsm6dsv16x_ah_qvar_zin_get(stmdev_ctx_t *ctx, 4940 lsm6dsv16x_ah_qvar_zin_t *val); 4941 4942 typedef struct 4943 { 4944 uint8_t ah_qvar_en : 1; 4945 } lsm6dsv16x_ah_qvar_mode_t; 4946 int32_t lsm6dsv16x_ah_qvar_mode_set(stmdev_ctx_t *ctx, 4947 lsm6dsv16x_ah_qvar_mode_t val); 4948 int32_t lsm6dsv16x_ah_qvar_mode_get(stmdev_ctx_t *ctx, 4949 lsm6dsv16x_ah_qvar_mode_t *val); 4950 4951 typedef enum 4952 { 4953 LSM6DSV16X_SW_RST_DYN_ADDRESS_RST = 0x0, 4954 LSM6DSV16X_I3C_GLOBAL_RST = 0x1, 4955 } lsm6dsv16x_i3c_reset_mode_t; 4956 int32_t lsm6dsv16x_i3c_reset_mode_set(stmdev_ctx_t *ctx, 4957 lsm6dsv16x_i3c_reset_mode_t val); 4958 int32_t lsm6dsv16x_i3c_reset_mode_get(stmdev_ctx_t *ctx, 4959 lsm6dsv16x_i3c_reset_mode_t *val); 4960 4961 typedef enum 4962 { 4963 LSM6DSV16X_IBI_2us = 0x0, 4964 LSM6DSV16X_IBI_50us = 0x1, 4965 LSM6DSV16X_IBI_1ms = 0x2, 4966 LSM6DSV16X_IBI_25ms = 0x3, 4967 } lsm6dsv16x_i3c_ibi_time_t; 4968 int32_t lsm6dsv16x_i3c_ibi_time_set(stmdev_ctx_t *ctx, 4969 lsm6dsv16x_i3c_ibi_time_t val); 4970 int32_t lsm6dsv16x_i3c_ibi_time_get(stmdev_ctx_t *ctx, 4971 lsm6dsv16x_i3c_ibi_time_t *val); 4972 4973 int32_t lsm6dsv16x_sh_master_interface_pull_up_set(stmdev_ctx_t *ctx, 4974 uint8_t val); 4975 int32_t lsm6dsv16x_sh_master_interface_pull_up_get(stmdev_ctx_t *ctx, 4976 uint8_t *val); 4977 4978 int32_t lsm6dsv16x_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val, 4979 uint8_t len); 4980 4981 typedef enum 4982 { 4983 LSM6DSV16X_SLV_0 = 0x0, 4984 LSM6DSV16X_SLV_0_1 = 0x1, 4985 LSM6DSV16X_SLV_0_1_2 = 0x2, 4986 LSM6DSV16X_SLV_0_1_2_3 = 0x3, 4987 } lsm6dsv16x_sh_slave_connected_t; 4988 int32_t lsm6dsv16x_sh_slave_connected_set(stmdev_ctx_t *ctx, 4989 lsm6dsv16x_sh_slave_connected_t val); 4990 int32_t lsm6dsv16x_sh_slave_connected_get(stmdev_ctx_t *ctx, 4991 lsm6dsv16x_sh_slave_connected_t *val); 4992 4993 int32_t lsm6dsv16x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 4994 int32_t lsm6dsv16x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 4995 4996 int32_t lsm6dsv16x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 4997 int32_t lsm6dsv16x_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 4998 4999 typedef enum 5000 { 5001 LSM6DSV16X_SH_TRG_XL_GY_DRDY = 0x0, 5002 LSM6DSV16X_SH_TRIG_INT2 = 0x1, 5003 } lsm6dsv16x_sh_syncro_mode_t; 5004 int32_t lsm6dsv16x_sh_syncro_mode_set(stmdev_ctx_t *ctx, 5005 lsm6dsv16x_sh_syncro_mode_t val); 5006 int32_t lsm6dsv16x_sh_syncro_mode_get(stmdev_ctx_t *ctx, 5007 lsm6dsv16x_sh_syncro_mode_t *val); 5008 5009 typedef enum 5010 { 5011 LSM6DSV16X_EACH_SH_CYCLE = 0x0, 5012 LSM6DSV16X_ONLY_FIRST_CYCLE = 0x1, 5013 } lsm6dsv16x_sh_write_mode_t; 5014 int32_t lsm6dsv16x_sh_write_mode_set(stmdev_ctx_t *ctx, 5015 lsm6dsv16x_sh_write_mode_t val); 5016 int32_t lsm6dsv16x_sh_write_mode_get(stmdev_ctx_t *ctx, 5017 lsm6dsv16x_sh_write_mode_t *val); 5018 5019 int32_t lsm6dsv16x_sh_reset_set(stmdev_ctx_t *ctx, uint8_t val); 5020 int32_t lsm6dsv16x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 5021 5022 typedef struct 5023 { 5024 uint8_t slv0_add; 5025 uint8_t slv0_subadd; 5026 uint8_t slv0_data; 5027 } lsm6dsv16x_sh_cfg_write_t; 5028 int32_t lsm6dsv16x_sh_cfg_write(stmdev_ctx_t *ctx, 5029 lsm6dsv16x_sh_cfg_write_t *val); 5030 typedef enum 5031 { 5032 LSM6DSV16X_SH_15Hz = 0x1, 5033 LSM6DSV16X_SH_30Hz = 0x2, 5034 LSM6DSV16X_SH_60Hz = 0x3, 5035 LSM6DSV16X_SH_120Hz = 0x4, 5036 LSM6DSV16X_SH_240Hz = 0x5, 5037 LSM6DSV16X_SH_480Hz = 0x6, 5038 } lsm6dsv16x_sh_data_rate_t; 5039 int32_t lsm6dsv16x_sh_data_rate_set(stmdev_ctx_t *ctx, 5040 lsm6dsv16x_sh_data_rate_t val); 5041 int32_t lsm6dsv16x_sh_data_rate_get(stmdev_ctx_t *ctx, 5042 lsm6dsv16x_sh_data_rate_t *val); 5043 5044 typedef struct 5045 { 5046 uint8_t slv_add; 5047 uint8_t slv_subadd; 5048 uint8_t slv_len; 5049 } lsm6dsv16x_sh_cfg_read_t; 5050 int32_t lsm6dsv16x_sh_slv_cfg_read(stmdev_ctx_t *ctx, uint8_t idx, 5051 lsm6dsv16x_sh_cfg_read_t *val); 5052 5053 int32_t lsm6dsv16x_sh_status_get(stmdev_ctx_t *ctx, 5054 lsm6dsv16x_status_master_t *val); 5055 5056 int32_t lsm6dsv16x_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 5057 int32_t lsm6dsv16x_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 5058 5059 typedef enum 5060 { 5061 LSM6DSV16X_I2C_I3C_ENABLE = 0x0, 5062 LSM6DSV16X_I2C_I3C_DISABLE = 0x1, 5063 } lsm6dsv16x_ui_i2c_i3c_mode_t; 5064 int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx, 5065 lsm6dsv16x_ui_i2c_i3c_mode_t val); 5066 int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx, 5067 lsm6dsv16x_ui_i2c_i3c_mode_t *val); 5068 5069 typedef enum 5070 { 5071 LSM6DSV16X_SPI_4_WIRE = 0x0, 5072 LSM6DSV16X_SPI_3_WIRE = 0x1, 5073 } lsm6dsv16x_spi_mode_t; 5074 int32_t lsm6dsv16x_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val); 5075 int32_t lsm6dsv16x_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val); 5076 5077 int32_t lsm6dsv16x_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val); 5078 int32_t lsm6dsv16x_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val); 5079 5080 typedef enum 5081 { 5082 LSM6DSV16X_SPI2_4_WIRE = 0x0, 5083 LSM6DSV16X_SPI2_3_WIRE = 0x1, 5084 } lsm6dsv16x_spi2_mode_t; 5085 int32_t lsm6dsv16x_spi2_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val); 5086 int32_t lsm6dsv16x_spi2_mode_get(stmdev_ctx_t *ctx, 5087 lsm6dsv16x_spi2_mode_t *val); 5088 5089 int32_t lsm6dsv16x_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val); 5090 int32_t lsm6dsv16x_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 5091 5092 typedef struct 5093 { 5094 uint8_t step_counter_enable : 1; 5095 uint8_t false_step_rej : 1; 5096 } lsm6dsv16x_stpcnt_mode_t; 5097 int32_t lsm6dsv16x_stpcnt_mode_set(stmdev_ctx_t *ctx, 5098 lsm6dsv16x_stpcnt_mode_t val); 5099 int32_t lsm6dsv16x_stpcnt_mode_get(stmdev_ctx_t *ctx, 5100 lsm6dsv16x_stpcnt_mode_t *val); 5101 5102 int32_t lsm6dsv16x_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val); 5103 5104 int32_t lsm6dsv16x_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val); 5105 int32_t lsm6dsv16x_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val); 5106 5107 int32_t lsm6dsv16x_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val); 5108 int32_t lsm6dsv16x_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val); 5109 5110 int32_t lsm6dsv16x_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val); 5111 int32_t lsm6dsv16x_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val); 5112 5113 int32_t lsm6dsv16x_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint8_t val); 5114 int32_t lsm6dsv16x_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint8_t *val); 5115 5116 typedef struct 5117 { 5118 float_t gbias_x; /* dps */ 5119 float_t gbias_y; /* dps */ 5120 float_t gbias_z; /* dps */ 5121 } lsm6dsv16x_sflp_gbias_t; 5122 int32_t lsm6dsv16x_sflp_game_gbias_set(stmdev_ctx_t *ctx, 5123 lsm6dsv16x_sflp_gbias_t *val); 5124 5125 typedef enum 5126 { 5127 LSM6DSV16X_SFLP_15Hz = 0x0, 5128 LSM6DSV16X_SFLP_30Hz = 0x1, 5129 LSM6DSV16X_SFLP_60Hz = 0x2, 5130 LSM6DSV16X_SFLP_120Hz = 0x3, 5131 LSM6DSV16X_SFLP_240Hz = 0x4, 5132 LSM6DSV16X_SFLP_480Hz = 0x5, 5133 } lsm6dsv16x_sflp_data_rate_t; 5134 int32_t lsm6dsv16x_sflp_data_rate_set(stmdev_ctx_t *ctx, 5135 lsm6dsv16x_sflp_data_rate_t val); 5136 int32_t lsm6dsv16x_sflp_data_rate_get(stmdev_ctx_t *ctx, 5137 lsm6dsv16x_sflp_data_rate_t *val); 5138 5139 typedef struct 5140 { 5141 uint8_t tap_x_en : 1; 5142 uint8_t tap_y_en : 1; 5143 uint8_t tap_z_en : 1; 5144 } lsm6dsv16x_tap_detection_t; 5145 int32_t lsm6dsv16x_tap_detection_set(stmdev_ctx_t *ctx, 5146 lsm6dsv16x_tap_detection_t val); 5147 int32_t lsm6dsv16x_tap_detection_get(stmdev_ctx_t *ctx, 5148 lsm6dsv16x_tap_detection_t *val); 5149 5150 typedef struct 5151 { 5152 uint8_t x : 5; 5153 uint8_t y : 5; 5154 uint8_t z : 5; 5155 } lsm6dsv16x_tap_thresholds_t; 5156 int32_t lsm6dsv16x_tap_thresholds_set(stmdev_ctx_t *ctx, 5157 lsm6dsv16x_tap_thresholds_t val); 5158 int32_t lsm6dsv16x_tap_thresholds_get(stmdev_ctx_t *ctx, 5159 lsm6dsv16x_tap_thresholds_t *val); 5160 5161 typedef enum 5162 { 5163 LSM6DSV16X_XYZ = 0x0, 5164 LSM6DSV16X_YXZ = 0x1, 5165 LSM6DSV16X_XZY = 0x2, 5166 LSM6DSV16X_ZYX = 0x3, 5167 LSM6DSV16X_YZX = 0x5, 5168 LSM6DSV16X_ZXY = 0x6, 5169 } lsm6dsv16x_tap_axis_priority_t; 5170 int32_t lsm6dsv16x_tap_axis_priority_set(stmdev_ctx_t *ctx, 5171 lsm6dsv16x_tap_axis_priority_t val); 5172 int32_t lsm6dsv16x_tap_axis_priority_get(stmdev_ctx_t *ctx, 5173 lsm6dsv16x_tap_axis_priority_t *val); 5174 5175 typedef struct 5176 { 5177 uint8_t shock : 2; 5178 uint8_t quiet : 2; 5179 uint8_t tap_gap : 4; 5180 } lsm6dsv16x_tap_time_windows_t; 5181 int32_t lsm6dsv16x_tap_time_windows_set(stmdev_ctx_t *ctx, 5182 lsm6dsv16x_tap_time_windows_t val); 5183 int32_t lsm6dsv16x_tap_time_windows_get(stmdev_ctx_t *ctx, 5184 lsm6dsv16x_tap_time_windows_t *val); 5185 5186 typedef enum 5187 { 5188 LSM6DSV16X_ONLY_SINGLE = 0x0, 5189 LSM6DSV16X_BOTH_SINGLE_DOUBLE = 0x1, 5190 } lsm6dsv16x_tap_mode_t; 5191 int32_t lsm6dsv16x_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val); 5192 int32_t lsm6dsv16x_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val); 5193 5194 int32_t lsm6dsv16x_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val); 5195 int32_t lsm6dsv16x_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 5196 5197 int32_t lsm6dsv16x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 5198 5199 int32_t lsm6dsv16x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 5200 int32_t lsm6dsv16x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 5201 5202 typedef enum 5203 { 5204 LSM6DSV16X_XL_AND_GY_NOT_AFFECTED = 0x0, 5205 LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, 5206 LSM6DSV16X_XL_LOW_POWER_GY_SLEEP = 0x2, 5207 LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN = 0x3, 5208 } lsm6dsv16x_act_mode_t; 5209 int32_t lsm6dsv16x_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val); 5210 int32_t lsm6dsv16x_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val); 5211 5212 typedef enum 5213 { 5214 LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, 5215 LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, 5216 LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, 5217 LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, 5218 } lsm6dsv16x_act_from_sleep_to_act_dur_t; 5219 int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx, 5220 lsm6dsv16x_act_from_sleep_to_act_dur_t val); 5221 int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx, 5222 lsm6dsv16x_act_from_sleep_to_act_dur_t *val); 5223 5224 typedef enum 5225 { 5226 LSM6DSV16X_1Hz875 = 0x0, 5227 LSM6DSV16X_15Hz = 0x1, 5228 LSM6DSV16X_30Hz = 0x2, 5229 LSM6DSV16X_60Hz = 0x3, 5230 } lsm6dsv16x_act_sleep_xl_odr_t; 5231 int32_t lsm6dsv16x_act_sleep_xl_odr_set(stmdev_ctx_t *ctx, 5232 lsm6dsv16x_act_sleep_xl_odr_t val); 5233 int32_t lsm6dsv16x_act_sleep_xl_odr_get(stmdev_ctx_t *ctx, 5234 lsm6dsv16x_act_sleep_xl_odr_t *val); 5235 5236 typedef struct 5237 { 5238 lsm6dsv16x_inactivity_dur_t inactivity_cfg; 5239 uint8_t inactivity_ths; 5240 uint8_t threshold; 5241 uint8_t duration; 5242 } lsm6dsv16x_act_thresholds_t; 5243 int32_t lsm6dsv16x_act_thresholds_set(stmdev_ctx_t *ctx, 5244 lsm6dsv16x_act_thresholds_t *val); 5245 int32_t lsm6dsv16x_act_thresholds_get(stmdev_ctx_t *ctx, 5246 lsm6dsv16x_act_thresholds_t *val); 5247 5248 typedef struct 5249 { 5250 uint8_t shock : 2; 5251 uint8_t quiet : 4; 5252 } lsm6dsv16x_act_wkup_time_windows_t; 5253 int32_t lsm6dsv16x_act_wkup_time_windows_set(stmdev_ctx_t *ctx, 5254 lsm6dsv16x_act_wkup_time_windows_t val); 5255 int32_t lsm6dsv16x_act_wkup_time_windows_get(stmdev_ctx_t *ctx, 5256 lsm6dsv16x_act_wkup_time_windows_t *val); 5257 5258 /** 5259 * @} 5260 * 5261 */ 5262 5263 #ifdef __cplusplus 5264 } 5265 #endif 5266 5267 #endif /*LSM6DSV16X_DRIVER_H */ 5268 5269 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 5270
