1 /** 2 ****************************************************************************** 3 * @file lsm6dsr_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsr_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSR_REGS_H 23 #define LSM6DSR_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSR 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSR Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSR_I2C_ADD_L 0xD5U 173 #define LSM6DSR_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSR_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSR_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 189 2; /* shub_reg_access + func_cfg_access */ 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t reg_access : 192 2; /* shub_reg_access + func_cfg_access */ 193 uint8_t not_used_01 : 6; 194 #endif /* DRV_BYTE_ORDER */ 195 } lsm6dsr_func_cfg_access_t; 196 197 #define LSM6DSR_PIN_CTRL 0x02U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t not_used_01 : 6; 202 uint8_t sdo_pu_en : 1; 203 uint8_t ois_pu_dis : 1; 204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 205 uint8_t ois_pu_dis : 1; 206 uint8_t sdo_pu_en : 1; 207 uint8_t not_used_01 : 6; 208 #endif /* DRV_BYTE_ORDER */ 209 } lsm6dsr_pin_ctrl_t; 210 211 #define LSM6DSR_S4S_TPH_L 0x04U 212 typedef struct 213 { 214 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 215 uint8_t tph_l : 7; 216 uint8_t tph_h_sel : 1; 217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 218 uint8_t tph_h_sel : 1; 219 uint8_t tph_l : 7; 220 #endif /* DRV_BYTE_ORDER */ 221 } lsm6dsr_s4s_tph_l_t; 222 223 #define LSM6DSR_S4S_TPH_H 0x05U 224 typedef struct 225 { 226 uint8_t tph_h : 8; 227 } lsm6dsr_s4s_tph_h_t; 228 229 #define LSM6DSR_S4S_RR 0x06U 230 typedef struct 231 { 232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 233 uint8_t rr : 2; 234 uint8_t not_used_01 : 6; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t not_used_01 : 6; 237 uint8_t rr : 2; 238 #endif /* DRV_BYTE_ORDER */ 239 } lsm6dsr_s4s_rr_t; 240 241 #define LSM6DSR_FIFO_CTRL1 0x07U 242 typedef struct 243 { 244 uint8_t wtm : 8; 245 } lsm6dsr_fifo_ctrl1_t; 246 247 #define LSM6DSR_FIFO_CTRL2 0x08U 248 typedef struct 249 { 250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 251 uint8_t wtm : 1; 252 uint8_t uncoptr_rate : 2; 253 uint8_t not_used_01 : 1; 254 uint8_t odrchg_en : 1; 255 uint8_t not_used_02 : 1; 256 uint8_t fifo_compr_rt_en : 1; 257 uint8_t stop_on_wtm : 1; 258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 259 uint8_t stop_on_wtm : 1; 260 uint8_t fifo_compr_rt_en : 1; 261 uint8_t not_used_02 : 1; 262 uint8_t odrchg_en : 1; 263 uint8_t not_used_01 : 1; 264 uint8_t uncoptr_rate : 2; 265 uint8_t wtm : 1; 266 #endif /* DRV_BYTE_ORDER */ 267 } lsm6dsr_fifo_ctrl2_t; 268 269 #define LSM6DSR_FIFO_CTRL3 0x09U 270 typedef struct 271 { 272 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 273 uint8_t bdr_xl : 4; 274 uint8_t bdr_gy : 4; 275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 276 uint8_t bdr_gy : 4; 277 uint8_t bdr_xl : 4; 278 #endif /* DRV_BYTE_ORDER */ 279 } lsm6dsr_fifo_ctrl3_t; 280 281 #define LSM6DSR_FIFO_CTRL4 0x0AU 282 typedef struct 283 { 284 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 285 uint8_t fifo_mode : 3; 286 uint8_t not_used_01 : 1; 287 uint8_t odr_t_batch : 2; 288 uint8_t odr_ts_batch : 2; 289 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 290 uint8_t odr_ts_batch : 2; 291 uint8_t odr_t_batch : 2; 292 uint8_t not_used_01 : 1; 293 uint8_t fifo_mode : 3; 294 #endif /* DRV_BYTE_ORDER */ 295 } lsm6dsr_fifo_ctrl4_t; 296 297 #define LSM6DSR_COUNTER_BDR_REG1 0x0BU 298 typedef struct 299 { 300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 301 uint8_t cnt_bdr_th : 3; 302 uint8_t not_used_01 : 2; 303 uint8_t trig_counter_bdr : 1; 304 uint8_t rst_counter_bdr : 1; 305 uint8_t dataready_pulsed : 1; 306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 307 uint8_t dataready_pulsed : 1; 308 uint8_t rst_counter_bdr : 1; 309 uint8_t trig_counter_bdr : 1; 310 uint8_t not_used_01 : 2; 311 uint8_t cnt_bdr_th : 3; 312 #endif /* DRV_BYTE_ORDER */ 313 } lsm6dsr_counter_bdr_reg1_t; 314 315 #define LSM6DSR_COUNTER_BDR_REG2 0x0CU 316 typedef struct 317 { 318 uint8_t cnt_bdr_th : 8; 319 } lsm6dsr_counter_bdr_reg2_t; 320 321 #define LSM6DSR_INT1_CTRL 0x0DU 322 typedef struct 323 { 324 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 325 uint8_t int1_drdy_xl : 1; 326 uint8_t int1_drdy_g : 1; 327 uint8_t int1_boot : 1; 328 uint8_t int1_fifo_th : 1; 329 uint8_t int1_fifo_ovr : 1; 330 uint8_t int1_fifo_full : 1; 331 uint8_t int1_cnt_bdr : 1; 332 uint8_t den_drdy_flag : 1; 333 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 334 uint8_t den_drdy_flag : 1; 335 uint8_t int1_cnt_bdr : 1; 336 uint8_t int1_fifo_full : 1; 337 uint8_t int1_fifo_ovr : 1; 338 uint8_t int1_fifo_th : 1; 339 uint8_t int1_boot : 1; 340 uint8_t int1_drdy_g : 1; 341 uint8_t int1_drdy_xl : 1; 342 #endif /* DRV_BYTE_ORDER */ 343 } lsm6dsr_int1_ctrl_t; 344 345 #define LSM6DSR_INT2_CTRL 0x0EU 346 typedef struct 347 { 348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 349 uint8_t int2_drdy_xl : 1; 350 uint8_t int2_drdy_g : 1; 351 uint8_t int2_drdy_temp : 1; 352 uint8_t int2_fifo_th : 1; 353 uint8_t int2_fifo_ovr : 1; 354 uint8_t int2_fifo_full : 1; 355 uint8_t int2_cnt_bdr : 1; 356 uint8_t not_used_01 : 1; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t not_used_01 : 1; 359 uint8_t int2_cnt_bdr : 1; 360 uint8_t int2_fifo_full : 1; 361 uint8_t int2_fifo_ovr : 1; 362 uint8_t int2_fifo_th : 1; 363 uint8_t int2_drdy_temp : 1; 364 uint8_t int2_drdy_g : 1; 365 uint8_t int2_drdy_xl : 1; 366 #endif /* DRV_BYTE_ORDER */ 367 } lsm6dsr_int2_ctrl_t; 368 369 #define LSM6DSR_WHO_AM_I 0x0FU 370 #define LSM6DSR_CTRL1_XL 0x10U 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t not_used_01 : 1; 375 uint8_t lpf2_xl_en : 1; 376 uint8_t fs_xl : 2; 377 uint8_t odr_xl : 4; 378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 379 uint8_t odr_xl : 4; 380 uint8_t fs_xl : 2; 381 uint8_t lpf2_xl_en : 1; 382 uint8_t not_used_01 : 1; 383 #endif /* DRV_BYTE_ORDER */ 384 } lsm6dsr_ctrl1_xl_t; 385 386 #define LSM6DSR_CTRL2_G 0x11U 387 typedef struct 388 { 389 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 390 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 391 uint8_t odr_g : 4; 392 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 393 uint8_t odr_g : 4; 394 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 395 #endif /* DRV_BYTE_ORDER */ 396 } lsm6dsr_ctrl2_g_t; 397 398 #define LSM6DSR_CTRL3_C 0x12U 399 typedef struct 400 { 401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 402 uint8_t sw_reset : 1; 403 uint8_t not_used_01 : 1; 404 uint8_t if_inc : 1; 405 uint8_t sim : 1; 406 uint8_t pp_od : 1; 407 uint8_t h_lactive : 1; 408 uint8_t bdu : 1; 409 uint8_t boot : 1; 410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 411 uint8_t boot : 1; 412 uint8_t bdu : 1; 413 uint8_t h_lactive : 1; 414 uint8_t pp_od : 1; 415 uint8_t sim : 1; 416 uint8_t if_inc : 1; 417 uint8_t not_used_01 : 1; 418 uint8_t sw_reset : 1; 419 #endif /* DRV_BYTE_ORDER */ 420 } lsm6dsr_ctrl3_c_t; 421 422 #define LSM6DSR_CTRL4_C 0x13U 423 typedef struct 424 { 425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 426 uint8_t not_used_01 : 1; 427 uint8_t lpf1_sel_g : 1; 428 uint8_t i2c_disable : 1; 429 uint8_t drdy_mask : 1; 430 uint8_t not_used_02 : 1; 431 uint8_t int2_on_int1 : 1; 432 uint8_t sleep_g : 1; 433 uint8_t not_used_03 : 1; 434 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 435 uint8_t not_used_03 : 1; 436 uint8_t sleep_g : 1; 437 uint8_t int2_on_int1 : 1; 438 uint8_t not_used_02 : 1; 439 uint8_t drdy_mask : 1; 440 uint8_t i2c_disable : 1; 441 uint8_t lpf1_sel_g : 1; 442 uint8_t not_used_01 : 1; 443 #endif /* DRV_BYTE_ORDER */ 444 } lsm6dsr_ctrl4_c_t; 445 446 #define LSM6DSR_CTRL5_C 0x14U 447 typedef struct 448 { 449 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 450 uint8_t st_xl : 2; 451 uint8_t st_g : 2; 452 uint8_t not_used_01 : 1; 453 uint8_t rounding : 2; 454 uint8_t not_used_02 : 1; 455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 456 uint8_t not_used_02 : 1; 457 uint8_t rounding : 2; 458 uint8_t not_used_01 : 1; 459 uint8_t st_g : 2; 460 uint8_t st_xl : 2; 461 #endif /* DRV_BYTE_ORDER */ 462 } lsm6dsr_ctrl5_c_t; 463 464 #define LSM6DSR_CTRL6_C 0x15U 465 typedef struct 466 { 467 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 468 uint8_t ftype : 3; 469 uint8_t usr_off_w : 1; 470 uint8_t xl_hm_mode : 1; 471 uint8_t den_mode : 472 3; /* trig_en + lvl1_en + lvl2_en */ 473 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 474 uint8_t den_mode : 475 3; /* trig_en + lvl1_en + lvl2_en */ 476 uint8_t xl_hm_mode : 1; 477 uint8_t usr_off_w : 1; 478 uint8_t ftype : 3; 479 #endif /* DRV_BYTE_ORDER */ 480 } lsm6dsr_ctrl6_c_t; 481 482 #define LSM6DSR_CTRL7_G 0x16U 483 typedef struct 484 { 485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 486 uint8_t ois_on : 1; 487 uint8_t usr_off_on_out : 1; 488 uint8_t ois_on_en : 1; 489 uint8_t not_used_01 : 1; 490 uint8_t hpm_g : 2; 491 uint8_t hp_en_g : 1; 492 uint8_t g_hm_mode : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t g_hm_mode : 1; 495 uint8_t hp_en_g : 1; 496 uint8_t hpm_g : 2; 497 uint8_t not_used_01 : 1; 498 uint8_t ois_on_en : 1; 499 uint8_t usr_off_on_out : 1; 500 uint8_t ois_on : 1; 501 #endif /* DRV_BYTE_ORDER */ 502 } lsm6dsr_ctrl7_g_t; 503 504 #define LSM6DSR_CTRL8_XL 0x17U 505 typedef struct 506 { 507 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 508 uint8_t low_pass_on_6d : 1; 509 uint8_t not_used_01 : 1; 510 uint8_t hp_slope_xl_en : 1; 511 uint8_t fastsettl_mode_xl : 1; 512 uint8_t hp_ref_mode_xl : 1; 513 uint8_t hpcf_xl : 3; 514 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 515 uint8_t hpcf_xl : 3; 516 uint8_t hp_ref_mode_xl : 1; 517 uint8_t fastsettl_mode_xl : 1; 518 uint8_t hp_slope_xl_en : 1; 519 uint8_t not_used_01 : 1; 520 uint8_t low_pass_on_6d : 1; 521 #endif /* DRV_BYTE_ORDER */ 522 } lsm6dsr_ctrl8_xl_t; 523 524 #define LSM6DSR_CTRL9_XL 0x18U 525 typedef struct 526 { 527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 528 uint8_t not_used_01 : 1; 529 uint8_t i3c_disable : 1; 530 uint8_t den_lh : 1; 531 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 532 uint8_t den_z : 1; 533 uint8_t den_y : 1; 534 uint8_t den_x : 1; 535 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 536 uint8_t den_x : 1; 537 uint8_t den_y : 1; 538 uint8_t den_z : 1; 539 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 540 uint8_t den_lh : 1; 541 uint8_t i3c_disable : 1; 542 uint8_t not_used_01 : 1; 543 #endif /* DRV_BYTE_ORDER */ 544 } lsm6dsr_ctrl9_xl_t; 545 546 #define LSM6DSR_CTRL10_C 0x19U 547 typedef struct 548 { 549 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 550 uint8_t not_used_01 : 5; 551 uint8_t timestamp_en : 1; 552 uint8_t not_used_02 : 2; 553 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 554 uint8_t not_used_02 : 2; 555 uint8_t timestamp_en : 1; 556 uint8_t not_used_01 : 5; 557 #endif /* DRV_BYTE_ORDER */ 558 } lsm6dsr_ctrl10_c_t; 559 560 #define LSM6DSR_ALL_INT_SRC 0x1AU 561 typedef struct 562 { 563 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 564 uint8_t ff_ia : 1; 565 uint8_t wu_ia : 1; 566 uint8_t single_tap : 1; 567 uint8_t double_tap : 1; 568 uint8_t d6d_ia : 1; 569 uint8_t sleep_change_ia : 1; 570 uint8_t not_used_01 : 1; 571 uint8_t timestamp_endcount : 1; 572 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 573 uint8_t timestamp_endcount : 1; 574 uint8_t not_used_01 : 1; 575 uint8_t sleep_change_ia : 1; 576 uint8_t d6d_ia : 1; 577 uint8_t double_tap : 1; 578 uint8_t single_tap : 1; 579 uint8_t wu_ia : 1; 580 uint8_t ff_ia : 1; 581 #endif /* DRV_BYTE_ORDER */ 582 } lsm6dsr_all_int_src_t; 583 584 #define LSM6DSR_WAKE_UP_SRC 0x1BU 585 typedef struct 586 { 587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 588 uint8_t z_wu : 1; 589 uint8_t y_wu : 1; 590 uint8_t x_wu : 1; 591 uint8_t wu_ia : 1; 592 uint8_t sleep_state : 1; 593 uint8_t ff_ia : 1; 594 uint8_t sleep_change_ia : 1; 595 uint8_t not_used_01 : 1; 596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 597 uint8_t not_used_01 : 1; 598 uint8_t sleep_change_ia : 1; 599 uint8_t ff_ia : 1; 600 uint8_t sleep_state : 1; 601 uint8_t wu_ia : 1; 602 uint8_t x_wu : 1; 603 uint8_t y_wu : 1; 604 uint8_t z_wu : 1; 605 #endif /* DRV_BYTE_ORDER */ 606 } lsm6dsr_wake_up_src_t; 607 608 #define LSM6DSR_TAP_SRC 0x1CU 609 typedef struct 610 { 611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 612 uint8_t z_tap : 1; 613 uint8_t y_tap : 1; 614 uint8_t x_tap : 1; 615 uint8_t tap_sign : 1; 616 uint8_t double_tap : 1; 617 uint8_t single_tap : 1; 618 uint8_t tap_ia : 1; 619 uint8_t not_used_01 : 1; 620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 621 uint8_t not_used_01 : 1; 622 uint8_t tap_ia : 1; 623 uint8_t single_tap : 1; 624 uint8_t double_tap : 1; 625 uint8_t tap_sign : 1; 626 uint8_t x_tap : 1; 627 uint8_t y_tap : 1; 628 uint8_t z_tap : 1; 629 #endif /* DRV_BYTE_ORDER */ 630 } lsm6dsr_tap_src_t; 631 632 #define LSM6DSR_D6D_SRC 0x1DU 633 typedef struct 634 { 635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 636 uint8_t xl : 1; 637 uint8_t xh : 1; 638 uint8_t yl : 1; 639 uint8_t yh : 1; 640 uint8_t zl : 1; 641 uint8_t zh : 1; 642 uint8_t d6d_ia : 1; 643 uint8_t den_drdy : 1; 644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 645 uint8_t den_drdy : 1; 646 uint8_t d6d_ia : 1; 647 uint8_t zh : 1; 648 uint8_t zl : 1; 649 uint8_t yh : 1; 650 uint8_t yl : 1; 651 uint8_t xh : 1; 652 uint8_t xl : 1; 653 #endif /* DRV_BYTE_ORDER */ 654 } lsm6dsr_d6d_src_t; 655 656 #define LSM6DSR_STATUS_REG 0x1EU 657 typedef struct 658 { 659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 660 uint8_t xlda : 1; 661 uint8_t gda : 1; 662 uint8_t tda : 1; 663 uint8_t not_used_01 : 5; 664 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 665 uint8_t not_used_01 : 5; 666 uint8_t tda : 1; 667 uint8_t gda : 1; 668 uint8_t xlda : 1; 669 #endif /* DRV_BYTE_ORDER */ 670 } lsm6dsr_status_reg_t; 671 672 #define LSM6DSR_STATUS_SPIAUX 0x1EU 673 typedef struct 674 { 675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 676 uint8_t xlda : 1; 677 uint8_t gda : 1; 678 uint8_t gyro_settling : 1; 679 uint8_t not_used_01 : 5; 680 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 681 uint8_t not_used_01 : 5; 682 uint8_t gyro_settling : 1; 683 uint8_t gda : 1; 684 uint8_t xlda : 1; 685 #endif /* DRV_BYTE_ORDER */ 686 } lsm6dsr_status_spiaux_t; 687 688 #define LSM6DSR_OUT_TEMP_L 0x20U 689 #define LSM6DSR_OUT_TEMP_H 0x21U 690 #define LSM6DSR_OUTX_L_G 0x22U 691 #define LSM6DSR_OUTX_H_G 0x23U 692 #define LSM6DSR_OUTY_L_G 0x24U 693 #define LSM6DSR_OUTY_H_G 0x25U 694 #define LSM6DSR_OUTZ_L_G 0x26U 695 #define LSM6DSR_OUTZ_H_G 0x27U 696 #define LSM6DSR_OUTX_L_A 0x28U 697 #define LSM6DSR_OUTX_H_A 0x29U 698 #define LSM6DSR_OUTY_L_A 0x2AU 699 #define LSM6DSR_OUTY_H_A 0x2BU 700 #define LSM6DSR_OUTZ_L_A 0x2CU 701 #define LSM6DSR_OUTZ_H_A 0x2DU 702 #define LSM6DSR_EMB_FUNC_STATUS_MAINPAGE 0x35U 703 typedef struct 704 { 705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 706 uint8_t not_used_01 : 3; 707 uint8_t is_step_det : 1; 708 uint8_t is_tilt : 1; 709 uint8_t is_sigmot : 1; 710 uint8_t not_used_02 : 1; 711 uint8_t is_fsm_lc : 1; 712 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 713 uint8_t is_fsm_lc : 1; 714 uint8_t not_used_02 : 1; 715 uint8_t is_sigmot : 1; 716 uint8_t is_tilt : 1; 717 uint8_t is_step_det : 1; 718 uint8_t not_used_01 : 3; 719 #endif /* DRV_BYTE_ORDER */ 720 } lsm6dsr_emb_func_status_mainpage_t; 721 722 #define LSM6DSR_FSM_STATUS_A_MAINPAGE 0x36U 723 typedef struct 724 { 725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 726 uint8_t is_fsm1 : 1; 727 uint8_t is_fsm2 : 1; 728 uint8_t is_fsm3 : 1; 729 uint8_t is_fsm4 : 1; 730 uint8_t is_fsm5 : 1; 731 uint8_t is_fsm6 : 1; 732 uint8_t is_fsm7 : 1; 733 uint8_t is_fsm8 : 1; 734 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 735 uint8_t is_fsm8 : 1; 736 uint8_t is_fsm7 : 1; 737 uint8_t is_fsm6 : 1; 738 uint8_t is_fsm5 : 1; 739 uint8_t is_fsm4 : 1; 740 uint8_t is_fsm3 : 1; 741 uint8_t is_fsm2 : 1; 742 uint8_t is_fsm1 : 1; 743 #endif /* DRV_BYTE_ORDER */ 744 } lsm6dsr_fsm_status_a_mainpage_t; 745 746 #define LSM6DSR_FSM_STATUS_B_MAINPAGE 0x37U 747 typedef struct 748 { 749 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 750 uint8_t is_fsm9 : 1; 751 uint8_t is_fsm10 : 1; 752 uint8_t is_fsm11 : 1; 753 uint8_t is_fsm12 : 1; 754 uint8_t is_fsm13 : 1; 755 uint8_t is_fsm14 : 1; 756 uint8_t is_fsm15 : 1; 757 uint8_t is_fsm16 : 1; 758 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 759 uint8_t is_fsm16 : 1; 760 uint8_t is_fsm15 : 1; 761 uint8_t is_fsm14 : 1; 762 uint8_t is_fsm13 : 1; 763 uint8_t is_fsm12 : 1; 764 uint8_t is_fsm11 : 1; 765 uint8_t is_fsm10 : 1; 766 uint8_t is_fsm9 : 1; 767 #endif /* DRV_BYTE_ORDER */ 768 } lsm6dsr_fsm_status_b_mainpage_t; 769 770 #define LSM6DSR_STATUS_MASTER_MAINPAGE 0x39U 771 typedef struct 772 { 773 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 774 uint8_t sens_hub_endop : 1; 775 uint8_t not_used_01 : 2; 776 uint8_t slave0_nack : 1; 777 uint8_t slave1_nack : 1; 778 uint8_t slave2_nack : 1; 779 uint8_t slave3_nack : 1; 780 uint8_t wr_once_done : 1; 781 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 782 uint8_t wr_once_done : 1; 783 uint8_t slave3_nack : 1; 784 uint8_t slave2_nack : 1; 785 uint8_t slave1_nack : 1; 786 uint8_t slave0_nack : 1; 787 uint8_t not_used_01 : 2; 788 uint8_t sens_hub_endop : 1; 789 #endif /* DRV_BYTE_ORDER */ 790 } lsm6dsr_status_master_mainpage_t; 791 792 #define LSM6DSR_FIFO_STATUS1 0x3AU 793 typedef struct 794 { 795 uint8_t diff_fifo : 8; 796 } lsm6dsr_fifo_status1_t; 797 798 #define LSM6DSR_FIFO_STATUS2 0x3BU 799 typedef struct 800 { 801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 802 uint8_t diff_fifo : 2; 803 uint8_t not_used_01 : 1; 804 uint8_t over_run_latched : 1; 805 uint8_t counter_bdr_ia : 1; 806 uint8_t fifo_full_ia : 1; 807 uint8_t fifo_ovr_ia : 1; 808 uint8_t fifo_wtm_ia : 1; 809 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 810 uint8_t fifo_wtm_ia : 1; 811 uint8_t fifo_ovr_ia : 1; 812 uint8_t fifo_full_ia : 1; 813 uint8_t counter_bdr_ia : 1; 814 uint8_t over_run_latched : 1; 815 uint8_t not_used_01 : 1; 816 uint8_t diff_fifo : 2; 817 #endif /* DRV_BYTE_ORDER */ 818 } lsm6dsr_fifo_status2_t; 819 820 #define LSM6DSR_TIMESTAMP0 0x40U 821 #define LSM6DSR_TIMESTAMP1 0x41U 822 #define LSM6DSR_TIMESTAMP2 0x42U 823 #define LSM6DSR_TIMESTAMP3 0x43U 824 #define LSM6DSR_TAP_CFG0 0x56U 825 typedef struct 826 { 827 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 828 uint8_t lir : 1; 829 uint8_t tap_z_en : 1; 830 uint8_t tap_y_en : 1; 831 uint8_t tap_x_en : 1; 832 uint8_t slope_fds : 1; 833 uint8_t sleep_status_on_int : 1; 834 uint8_t int_clr_on_read : 1; 835 uint8_t not_used_01 : 1; 836 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 837 uint8_t not_used_01 : 1; 838 uint8_t int_clr_on_read : 1; 839 uint8_t sleep_status_on_int : 1; 840 uint8_t slope_fds : 1; 841 uint8_t tap_x_en : 1; 842 uint8_t tap_y_en : 1; 843 uint8_t tap_z_en : 1; 844 uint8_t lir : 1; 845 #endif /* DRV_BYTE_ORDER */ 846 } lsm6dsr_tap_cfg0_t; 847 848 #define LSM6DSR_TAP_CFG1 0x57U 849 typedef struct 850 { 851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 852 uint8_t tap_ths_x : 5; 853 uint8_t tap_priority : 3; 854 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 855 uint8_t tap_priority : 3; 856 uint8_t tap_ths_x : 5; 857 #endif /* DRV_BYTE_ORDER */ 858 } lsm6dsr_tap_cfg1_t; 859 860 #define LSM6DSR_TAP_CFG2 0x58U 861 typedef struct 862 { 863 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 864 uint8_t tap_ths_y : 5; 865 uint8_t inact_en : 2; 866 uint8_t interrupts_enable : 1; 867 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 868 uint8_t interrupts_enable : 1; 869 uint8_t inact_en : 2; 870 uint8_t tap_ths_y : 5; 871 #endif /* DRV_BYTE_ORDER */ 872 } lsm6dsr_tap_cfg2_t; 873 874 #define LSM6DSR_TAP_THS_6D 0x59U 875 typedef struct 876 { 877 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 878 uint8_t tap_ths_z : 5; 879 uint8_t sixd_ths : 2; 880 uint8_t d4d_en : 1; 881 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 882 uint8_t d4d_en : 1; 883 uint8_t sixd_ths : 2; 884 uint8_t tap_ths_z : 5; 885 #endif /* DRV_BYTE_ORDER */ 886 } lsm6dsr_tap_ths_6d_t; 887 888 #define LSM6DSR_INT_DUR2 0x5AU 889 typedef struct 890 { 891 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 892 uint8_t shock : 2; 893 uint8_t quiet : 2; 894 uint8_t dur : 4; 895 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 896 uint8_t dur : 4; 897 uint8_t quiet : 2; 898 uint8_t shock : 2; 899 #endif /* DRV_BYTE_ORDER */ 900 } lsm6dsr_int_dur2_t; 901 902 #define LSM6DSR_WAKE_UP_THS 0x5BU 903 typedef struct 904 { 905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 906 uint8_t wk_ths : 6; 907 uint8_t usr_off_on_wu : 1; 908 uint8_t single_double_tap : 1; 909 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 910 uint8_t single_double_tap : 1; 911 uint8_t usr_off_on_wu : 1; 912 uint8_t wk_ths : 6; 913 #endif /* DRV_BYTE_ORDER */ 914 } lsm6dsr_wake_up_ths_t; 915 916 #define LSM6DSR_WAKE_UP_DUR 0x5CU 917 typedef struct 918 { 919 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 920 uint8_t sleep_dur : 4; 921 uint8_t wake_ths_w : 1; 922 uint8_t wake_dur : 2; 923 uint8_t ff_dur : 1; 924 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 925 uint8_t ff_dur : 1; 926 uint8_t wake_dur : 2; 927 uint8_t wake_ths_w : 1; 928 uint8_t sleep_dur : 4; 929 #endif /* DRV_BYTE_ORDER */ 930 } lsm6dsr_wake_up_dur_t; 931 932 #define LSM6DSR_FREE_FALL 0x5DU 933 typedef struct 934 { 935 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 936 uint8_t ff_ths : 3; 937 uint8_t ff_dur : 5; 938 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 939 uint8_t ff_dur : 5; 940 uint8_t ff_ths : 3; 941 #endif /* DRV_BYTE_ORDER */ 942 } lsm6dsr_free_fall_t; 943 944 #define LSM6DSR_MD1_CFG 0x5EU 945 typedef struct 946 { 947 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 948 uint8_t int1_shub : 1; 949 uint8_t int1_emb_func : 1; 950 uint8_t int1_6d : 1; 951 uint8_t int1_double_tap : 1; 952 uint8_t int1_ff : 1; 953 uint8_t int1_wu : 1; 954 uint8_t int1_single_tap : 1; 955 uint8_t int1_sleep_change : 1; 956 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 957 uint8_t int1_sleep_change : 1; 958 uint8_t int1_single_tap : 1; 959 uint8_t int1_wu : 1; 960 uint8_t int1_ff : 1; 961 uint8_t int1_double_tap : 1; 962 uint8_t int1_6d : 1; 963 uint8_t int1_emb_func : 1; 964 uint8_t int1_shub : 1; 965 #endif /* DRV_BYTE_ORDER */ 966 } lsm6dsr_md1_cfg_t; 967 968 #define LSM6DSR_MD2_CFG 0x5FU 969 typedef struct 970 { 971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 972 uint8_t int2_timestamp : 1; 973 uint8_t int2_emb_func : 1; 974 uint8_t int2_6d : 1; 975 uint8_t int2_double_tap : 1; 976 uint8_t int2_ff : 1; 977 uint8_t int2_wu : 1; 978 uint8_t int2_single_tap : 1; 979 uint8_t int2_sleep_change : 1; 980 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 981 uint8_t int2_sleep_change : 1; 982 uint8_t int2_single_tap : 1; 983 uint8_t int2_wu : 1; 984 uint8_t int2_ff : 1; 985 uint8_t int2_double_tap : 1; 986 uint8_t int2_6d : 1; 987 uint8_t int2_emb_func : 1; 988 uint8_t int2_timestamp : 1; 989 #endif /* DRV_BYTE_ORDER */ 990 } lsm6dsr_md2_cfg_t; 991 992 #define LSM6DSR_S4S_ST_CMD_CODE 0x60U 993 typedef struct 994 { 995 uint8_t s4s_st_cmd_code : 8; 996 } lsm6dsr_s4s_st_cmd_code_t; 997 998 #define LSM6DSR_S4S_DT_REG 0x61U 999 typedef struct 1000 { 1001 uint8_t dt : 8; 1002 } lsm6dsr_s4s_dt_reg_t; 1003 1004 #define LSM6DSR_I3C_BUS_AVB 0x62U 1005 typedef struct 1006 { 1007 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1008 uint8_t pd_dis_int1 : 1; 1009 uint8_t not_used_01 : 2; 1010 uint8_t i3c_bus_avb_sel : 2; 1011 uint8_t not_used_02 : 3; 1012 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1013 uint8_t not_used_02 : 3; 1014 uint8_t i3c_bus_avb_sel : 2; 1015 uint8_t not_used_01 : 2; 1016 uint8_t pd_dis_int1 : 1; 1017 #endif /* DRV_BYTE_ORDER */ 1018 } lsm6dsr_i3c_bus_avb_t; 1019 1020 #define LSM6DSR_INTERNAL_FREQ_FINE 0x63U 1021 typedef struct 1022 { 1023 uint8_t freq_fine : 8; 1024 } lsm6dsr_internal_freq_fine_t; 1025 1026 #define LSM6DSR_INT_OIS 0x6FU 1027 typedef struct 1028 { 1029 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1030 uint8_t st_xl_ois : 2; 1031 uint8_t not_used_01 : 3; 1032 uint8_t den_lh_ois : 1; 1033 uint8_t lvl2_ois : 1; 1034 uint8_t int2_drdy_ois : 1; 1035 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1036 uint8_t int2_drdy_ois : 1; 1037 uint8_t lvl2_ois : 1; 1038 uint8_t den_lh_ois : 1; 1039 uint8_t not_used_01 : 3; 1040 uint8_t st_xl_ois : 2; 1041 #endif /* DRV_BYTE_ORDER */ 1042 } lsm6dsr_int_ois_t; 1043 1044 #define LSM6DSR_CTRL1_OIS 0x70U 1045 typedef struct 1046 { 1047 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1048 uint8_t ois_en_spi2 : 1; 1049 uint8_t fs_125_ois : 1; 1050 uint8_t fs_g_ois : 2; 1051 uint8_t mode4_en : 1; 1052 uint8_t sim_ois : 1; 1053 uint8_t lvl1_ois : 1; 1054 uint8_t not_used_01 : 1; 1055 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1056 uint8_t not_used_01 : 1; 1057 uint8_t lvl1_ois : 1; 1058 uint8_t sim_ois : 1; 1059 uint8_t mode4_en : 1; 1060 uint8_t fs_g_ois : 2; 1061 uint8_t fs_125_ois : 1; 1062 uint8_t ois_en_spi2 : 1; 1063 #endif /* DRV_BYTE_ORDER */ 1064 } lsm6dsr_ctrl1_ois_t; 1065 1066 #define LSM6DSR_CTRL2_OIS 0x71U 1067 typedef struct 1068 { 1069 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1070 uint8_t hp_en_ois : 1; 1071 uint8_t ftype_ois : 2; 1072 uint8_t not_used_01 : 1; 1073 uint8_t hpm_ois : 2; 1074 uint8_t not_used_02 : 2; 1075 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1076 uint8_t not_used_02 : 2; 1077 uint8_t hpm_ois : 2; 1078 uint8_t not_used_01 : 1; 1079 uint8_t ftype_ois : 2; 1080 uint8_t hp_en_ois : 1; 1081 #endif /* DRV_BYTE_ORDER */ 1082 } lsm6dsr_ctrl2_ois_t; 1083 1084 #define LSM6DSR_CTRL3_OIS 0x72U 1085 typedef struct 1086 { 1087 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1088 uint8_t st_ois_clampdis : 1; 1089 uint8_t st_ois : 2; 1090 uint8_t filter_xl_conf_ois : 3; 1091 uint8_t fs_xl_ois : 2; 1092 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1093 uint8_t fs_xl_ois : 2; 1094 uint8_t filter_xl_conf_ois : 3; 1095 uint8_t st_ois : 2; 1096 uint8_t st_ois_clampdis : 1; 1097 #endif /* DRV_BYTE_ORDER */ 1098 } lsm6dsr_ctrl3_ois_t; 1099 1100 #define LSM6DSR_X_OFS_USR 0x73U 1101 #define LSM6DSR_Y_OFS_USR 0x74U 1102 #define LSM6DSR_Z_OFS_USR 0x75U 1103 #define LSM6DSR_FIFO_DATA_OUT_TAG 0x78U 1104 typedef struct 1105 { 1106 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1107 uint8_t tag_parity : 1; 1108 uint8_t tag_cnt : 2; 1109 uint8_t tag_sensor : 5; 1110 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1111 uint8_t tag_sensor : 5; 1112 uint8_t tag_cnt : 2; 1113 uint8_t tag_parity : 1; 1114 #endif /* DRV_BYTE_ORDER */ 1115 } lsm6dsr_fifo_data_out_tag_t; 1116 1117 #define LSM6DSR_FIFO_DATA_OUT_X_L 0x79U 1118 #define LSM6DSR_FIFO_DATA_OUT_X_H 0x7AU 1119 #define LSM6DSR_FIFO_DATA_OUT_Y_L 0x7BU 1120 #define LSM6DSR_FIFO_DATA_OUT_Y_H 0x7CU 1121 #define LSM6DSR_FIFO_DATA_OUT_Z_L 0x7DU 1122 #define LSM6DSR_FIFO_DATA_OUT_Z_H 0x7EU 1123 #define LSM6DSR_PAGE_SEL 0x02U 1124 typedef struct 1125 { 1126 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1127 uint8_t not_used_01 : 4; 1128 uint8_t page_sel : 4; 1129 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1130 uint8_t page_sel : 4; 1131 uint8_t not_used_01 : 4; 1132 #endif /* DRV_BYTE_ORDER */ 1133 } lsm6dsr_page_sel_t; 1134 1135 #define LSM6DSR_ADV_PEDO 0x03U 1136 typedef struct 1137 { 1138 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1139 uint8_t not_used_01 : 1; 1140 uint8_t pedo_fpr_adf_dis : 1; 1141 uint8_t not_used_02 : 6; 1142 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1143 uint8_t not_used_02 : 6; 1144 uint8_t pedo_fpr_adf_dis : 1; 1145 uint8_t not_used_01 : 1; 1146 #endif /* DRV_BYTE_ORDER */ 1147 } lsm6dsr_adv_pedo_t; 1148 1149 #define LSM6DSR_EMB_FUNC_EN_A 0x04U 1150 typedef struct 1151 { 1152 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1153 uint8_t not_used_01 : 3; 1154 uint8_t pedo_en : 1; 1155 uint8_t tilt_en : 1; 1156 uint8_t sign_motion_en : 1; 1157 uint8_t not_used_02 : 2; 1158 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1159 uint8_t not_used_02 : 2; 1160 uint8_t sign_motion_en : 1; 1161 uint8_t tilt_en : 1; 1162 uint8_t pedo_en : 1; 1163 uint8_t not_used_01 : 3; 1164 #endif /* DRV_BYTE_ORDER */ 1165 } lsm6dsr_emb_func_en_a_t; 1166 1167 #define LSM6DSR_EMB_FUNC_EN_B 0x05U 1168 typedef struct 1169 { 1170 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1171 uint8_t fsm_en : 1; 1172 uint8_t not_used_01 : 2; 1173 uint8_t fifo_compr_en : 1; 1174 uint8_t pedo_adv_en : 1; 1175 uint8_t not_used_02 : 3; 1176 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1177 uint8_t not_used_02 : 3; 1178 uint8_t pedo_adv_en : 1; 1179 uint8_t fifo_compr_en : 1; 1180 uint8_t not_used_01 : 2; 1181 uint8_t fsm_en : 1; 1182 #endif /* DRV_BYTE_ORDER */ 1183 } lsm6dsr_emb_func_en_b_t; 1184 1185 #define LSM6DSR_PAGE_ADDRESS 0x08U 1186 typedef struct 1187 { 1188 uint8_t page_addr : 8; 1189 } lsm6dsr_page_address_t; 1190 1191 #define LSM6DSR_PAGE_VALUE 0x09U 1192 typedef struct 1193 { 1194 uint8_t page_value : 8; 1195 } lsm6dsr_page_value_t; 1196 1197 #define LSM6DSR_EMB_FUNC_INT1 0x0AU 1198 typedef struct 1199 { 1200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1201 uint8_t not_used_01 : 3; 1202 uint8_t int1_step_detector : 1; 1203 uint8_t int1_tilt : 1; 1204 uint8_t int1_sig_mot : 1; 1205 uint8_t not_used_02 : 1; 1206 uint8_t int1_fsm_lc : 1; 1207 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1208 uint8_t int1_fsm_lc : 1; 1209 uint8_t not_used_02 : 1; 1210 uint8_t int1_sig_mot : 1; 1211 uint8_t int1_tilt : 1; 1212 uint8_t int1_step_detector : 1; 1213 uint8_t not_used_01 : 3; 1214 #endif /* DRV_BYTE_ORDER */ 1215 } lsm6dsr_emb_func_int1_t; 1216 1217 #define LSM6DSR_FSM_INT1_A 0x0BU 1218 typedef struct 1219 { 1220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1221 uint8_t int1_fsm1 : 1; 1222 uint8_t int1_fsm2 : 1; 1223 uint8_t int1_fsm3 : 1; 1224 uint8_t int1_fsm4 : 1; 1225 uint8_t int1_fsm5 : 1; 1226 uint8_t int1_fsm6 : 1; 1227 uint8_t int1_fsm7 : 1; 1228 uint8_t int1_fsm8 : 1; 1229 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1230 uint8_t int1_fsm8 : 1; 1231 uint8_t int1_fsm7 : 1; 1232 uint8_t int1_fsm6 : 1; 1233 uint8_t int1_fsm5 : 1; 1234 uint8_t int1_fsm4 : 1; 1235 uint8_t int1_fsm3 : 1; 1236 uint8_t int1_fsm2 : 1; 1237 uint8_t int1_fsm1 : 1; 1238 #endif /* DRV_BYTE_ORDER */ 1239 } lsm6dsr_fsm_int1_a_t; 1240 1241 #define LSM6DSR_FSM_INT1_B 0x0CU 1242 typedef struct 1243 { 1244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1245 uint8_t int1_fsm9 : 1; 1246 uint8_t int1_fsm10 : 1; 1247 uint8_t int1_fsm11 : 1; 1248 uint8_t int1_fsm12 : 1; 1249 uint8_t int1_fsm13 : 1; 1250 uint8_t int1_fsm14 : 1; 1251 uint8_t int1_fsm15 : 1; 1252 uint8_t int1_fsm16 : 1; 1253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1254 uint8_t int1_fsm16 : 1; 1255 uint8_t int1_fsm15 : 1; 1256 uint8_t int1_fsm14 : 1; 1257 uint8_t int1_fsm13 : 1; 1258 uint8_t int1_fsm12 : 1; 1259 uint8_t int1_fsm11 : 1; 1260 uint8_t int1_fsm10 : 1; 1261 uint8_t int1_fsm9 : 1; 1262 #endif /* DRV_BYTE_ORDER */ 1263 } lsm6dsr_fsm_int1_b_t; 1264 1265 #define LSM6DSR_EMB_FUNC_INT2 0x0EU 1266 typedef struct 1267 { 1268 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1269 uint8_t not_used_01 : 3; 1270 uint8_t int2_step_detector : 1; 1271 uint8_t int2_tilt : 1; 1272 uint8_t int2_sig_mot : 1; 1273 uint8_t not_used_02 : 1; 1274 uint8_t int2_fsm_lc : 1; 1275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1276 uint8_t int2_fsm_lc : 1; 1277 uint8_t not_used_02 : 1; 1278 uint8_t int2_sig_mot : 1; 1279 uint8_t int2_tilt : 1; 1280 uint8_t int2_step_detector : 1; 1281 uint8_t not_used_01 : 3; 1282 #endif /* DRV_BYTE_ORDER */ 1283 } lsm6dsr_emb_func_int2_t; 1284 1285 #define LSM6DSR_FSM_INT2_A 0x0FU 1286 typedef struct 1287 { 1288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1289 uint8_t int2_fsm1 : 1; 1290 uint8_t int2_fsm2 : 1; 1291 uint8_t int2_fsm3 : 1; 1292 uint8_t int2_fsm4 : 1; 1293 uint8_t int2_fsm5 : 1; 1294 uint8_t int2_fsm6 : 1; 1295 uint8_t int2_fsm7 : 1; 1296 uint8_t int2_fsm8 : 1; 1297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1298 uint8_t int2_fsm8 : 1; 1299 uint8_t int2_fsm7 : 1; 1300 uint8_t int2_fsm6 : 1; 1301 uint8_t int2_fsm5 : 1; 1302 uint8_t int2_fsm4 : 1; 1303 uint8_t int2_fsm3 : 1; 1304 uint8_t int2_fsm2 : 1; 1305 uint8_t int2_fsm1 : 1; 1306 #endif /* DRV_BYTE_ORDER */ 1307 } lsm6dsr_fsm_int2_a_t; 1308 1309 #define LSM6DSR_FSM_INT2_B 0x10U 1310 typedef struct 1311 { 1312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1313 uint8_t int2_fsm9 : 1; 1314 uint8_t int2_fsm10 : 1; 1315 uint8_t int2_fsm11 : 1; 1316 uint8_t int2_fsm12 : 1; 1317 uint8_t int2_fsm13 : 1; 1318 uint8_t int2_fsm14 : 1; 1319 uint8_t int2_fsm15 : 1; 1320 uint8_t int2_fsm16 : 1; 1321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1322 uint8_t int2_fsm16 : 1; 1323 uint8_t int2_fsm15 : 1; 1324 uint8_t int2_fsm14 : 1; 1325 uint8_t int2_fsm13 : 1; 1326 uint8_t int2_fsm12 : 1; 1327 uint8_t int2_fsm11 : 1; 1328 uint8_t int2_fsm10 : 1; 1329 uint8_t int2_fsm9 : 1; 1330 #endif /* DRV_BYTE_ORDER */ 1331 } lsm6dsr_fsm_int2_b_t; 1332 1333 #define LSM6DSR_EMB_FUNC_STATUS 0x12U 1334 typedef struct 1335 { 1336 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1337 uint8_t not_used_01 : 3; 1338 uint8_t is_step_det : 1; 1339 uint8_t is_tilt : 1; 1340 uint8_t is_sigmot : 1; 1341 uint8_t not_used_02 : 1; 1342 uint8_t is_fsm_lc : 1; 1343 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1344 uint8_t is_fsm_lc : 1; 1345 uint8_t not_used_02 : 1; 1346 uint8_t is_sigmot : 1; 1347 uint8_t is_tilt : 1; 1348 uint8_t is_step_det : 1; 1349 uint8_t not_used_01 : 3; 1350 #endif /* DRV_BYTE_ORDER */ 1351 } lsm6dsr_emb_func_status_t; 1352 1353 #define LSM6DSR_FSM_STATUS_A 0x13U 1354 typedef struct 1355 { 1356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1357 uint8_t is_fsm1 : 1; 1358 uint8_t is_fsm2 : 1; 1359 uint8_t is_fsm3 : 1; 1360 uint8_t is_fsm4 : 1; 1361 uint8_t is_fsm5 : 1; 1362 uint8_t is_fsm6 : 1; 1363 uint8_t is_fsm7 : 1; 1364 uint8_t is_fsm8 : 1; 1365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1366 uint8_t is_fsm8 : 1; 1367 uint8_t is_fsm7 : 1; 1368 uint8_t is_fsm6 : 1; 1369 uint8_t is_fsm5 : 1; 1370 uint8_t is_fsm4 : 1; 1371 uint8_t is_fsm3 : 1; 1372 uint8_t is_fsm2 : 1; 1373 uint8_t is_fsm1 : 1; 1374 #endif /* DRV_BYTE_ORDER */ 1375 } lsm6dsr_fsm_status_a_t; 1376 1377 #define LSM6DSR_FSM_STATUS_B 0x14U 1378 typedef struct 1379 { 1380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1381 uint8_t is_fsm9 : 1; 1382 uint8_t is_fsm10 : 1; 1383 uint8_t is_fsm11 : 1; 1384 uint8_t is_fsm12 : 1; 1385 uint8_t is_fsm13 : 1; 1386 uint8_t is_fsm14 : 1; 1387 uint8_t is_fsm15 : 1; 1388 uint8_t is_fsm16 : 1; 1389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1390 uint8_t is_fsm16 : 1; 1391 uint8_t is_fsm15 : 1; 1392 uint8_t is_fsm14 : 1; 1393 uint8_t is_fsm13 : 1; 1394 uint8_t is_fsm12 : 1; 1395 uint8_t is_fsm11 : 1; 1396 uint8_t is_fsm10 : 1; 1397 uint8_t is_fsm9 : 1; 1398 #endif /* DRV_BYTE_ORDER */ 1399 } lsm6dsr_fsm_status_b_t; 1400 1401 #define LSM6DSR_PAGE_RW 0x17U 1402 typedef struct 1403 { 1404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1405 uint8_t not_used_01 : 5; 1406 uint8_t page_rw : 2; /* page_write + page_read */ 1407 uint8_t emb_func_lir : 1; 1408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1409 uint8_t emb_func_lir : 1; 1410 uint8_t page_rw : 2; /* page_write + page_read */ 1411 uint8_t not_used_01 : 5; 1412 #endif /* DRV_BYTE_ORDER */ 1413 } lsm6dsr_page_rw_t; 1414 1415 #define LSM6DSR_EMB_FUNC_FIFO_CFG 0x44U 1416 typedef struct 1417 { 1418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1419 uint8_t not_used_01 : 6; 1420 uint8_t pedo_fifo_en : 1; 1421 uint8_t not_used_02 : 1; 1422 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1423 uint8_t not_used_02 : 1; 1424 uint8_t pedo_fifo_en : 1; 1425 uint8_t not_used_01 : 6; 1426 #endif /* DRV_BYTE_ORDER */ 1427 } lsm6dsr_emb_func_fifo_cfg_t; 1428 1429 #define LSM6DSR_FSM_ENABLE_A 0x46U 1430 typedef struct 1431 { 1432 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1433 uint8_t fsm1_en : 1; 1434 uint8_t fsm2_en : 1; 1435 uint8_t fsm3_en : 1; 1436 uint8_t fsm4_en : 1; 1437 uint8_t fsm5_en : 1; 1438 uint8_t fsm6_en : 1; 1439 uint8_t fsm7_en : 1; 1440 uint8_t fsm8_en : 1; 1441 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1442 uint8_t fsm8_en : 1; 1443 uint8_t fsm7_en : 1; 1444 uint8_t fsm6_en : 1; 1445 uint8_t fsm5_en : 1; 1446 uint8_t fsm4_en : 1; 1447 uint8_t fsm3_en : 1; 1448 uint8_t fsm2_en : 1; 1449 uint8_t fsm1_en : 1; 1450 #endif /* DRV_BYTE_ORDER */ 1451 } lsm6dsr_fsm_enable_a_t; 1452 1453 #define LSM6DSR_FSM_ENABLE_B 0x47U 1454 typedef struct 1455 { 1456 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1457 uint8_t fsm9_en : 1; 1458 uint8_t fsm10_en : 1; 1459 uint8_t fsm11_en : 1; 1460 uint8_t fsm12_en : 1; 1461 uint8_t fsm13_en : 1; 1462 uint8_t fsm14_en : 1; 1463 uint8_t fsm15_en : 1; 1464 uint8_t fsm16_en : 1; 1465 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1466 uint8_t fsm16_en : 1; 1467 uint8_t fsm15_en : 1; 1468 uint8_t fsm14_en : 1; 1469 uint8_t fsm13_en : 1; 1470 uint8_t fsm12_en : 1; 1471 uint8_t fsm11_en : 1; 1472 uint8_t fsm10_en : 1; 1473 uint8_t fsm9_en : 1; 1474 #endif /* DRV_BYTE_ORDER */ 1475 } lsm6dsr_fsm_enable_b_t; 1476 1477 #define LSM6DSR_FSM_LONG_COUNTER_L 0x48U 1478 #define LSM6DSR_FSM_LONG_COUNTER_H 0x49U 1479 #define LSM6DSR_FSM_LONG_COUNTER_CLEAR 0x4AU 1480 typedef struct 1481 { 1482 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1483 uint8_t fsm_lc_clr : 1484 2; /* fsm_lc_cleared + fsm_lc_clear */ 1485 uint8_t not_used_01 : 6; 1486 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1487 uint8_t not_used_01 : 6; 1488 uint8_t fsm_lc_clr : 1489 2; /* fsm_lc_cleared + fsm_lc_clear */ 1490 #endif /* DRV_BYTE_ORDER */ 1491 } lsm6dsr_fsm_long_counter_clear_t; 1492 1493 #define LSM6DSR_FSM_OUTS1 0x4CU 1494 typedef struct 1495 { 1496 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1497 uint8_t n_v : 1; 1498 uint8_t p_v : 1; 1499 uint8_t n_z : 1; 1500 uint8_t p_z : 1; 1501 uint8_t n_y : 1; 1502 uint8_t p_y : 1; 1503 uint8_t n_x : 1; 1504 uint8_t p_x : 1; 1505 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1506 uint8_t p_x : 1; 1507 uint8_t n_x : 1; 1508 uint8_t p_y : 1; 1509 uint8_t n_y : 1; 1510 uint8_t p_z : 1; 1511 uint8_t n_z : 1; 1512 uint8_t p_v : 1; 1513 uint8_t n_v : 1; 1514 #endif /* DRV_BYTE_ORDER */ 1515 } lsm6dsr_fsm_outs1_t; 1516 1517 #define LSM6DSR_FSM_OUTS2 0x4DU 1518 typedef struct 1519 { 1520 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1521 uint8_t n_v : 1; 1522 uint8_t p_v : 1; 1523 uint8_t n_z : 1; 1524 uint8_t p_z : 1; 1525 uint8_t n_y : 1; 1526 uint8_t p_y : 1; 1527 uint8_t n_x : 1; 1528 uint8_t p_x : 1; 1529 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1530 uint8_t p_x : 1; 1531 uint8_t n_x : 1; 1532 uint8_t p_y : 1; 1533 uint8_t n_y : 1; 1534 uint8_t p_z : 1; 1535 uint8_t n_z : 1; 1536 uint8_t p_v : 1; 1537 uint8_t n_v : 1; 1538 #endif /* DRV_BYTE_ORDER */ 1539 } lsm6dsr_fsm_outs2_t; 1540 1541 #define LSM6DSR_FSM_OUTS3 0x4EU 1542 typedef struct 1543 { 1544 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1545 uint8_t n_v : 1; 1546 uint8_t p_v : 1; 1547 uint8_t n_z : 1; 1548 uint8_t p_z : 1; 1549 uint8_t n_y : 1; 1550 uint8_t p_y : 1; 1551 uint8_t n_x : 1; 1552 uint8_t p_x : 1; 1553 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1554 uint8_t p_x : 1; 1555 uint8_t n_x : 1; 1556 uint8_t p_y : 1; 1557 uint8_t n_y : 1; 1558 uint8_t p_z : 1; 1559 uint8_t n_z : 1; 1560 uint8_t p_v : 1; 1561 uint8_t n_v : 1; 1562 #endif /* DRV_BYTE_ORDER */ 1563 } lsm6dsr_fsm_outs3_t; 1564 1565 #define LSM6DSR_FSM_OUTS4 0x4FU 1566 typedef struct 1567 { 1568 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1569 uint8_t n_v : 1; 1570 uint8_t p_v : 1; 1571 uint8_t n_z : 1; 1572 uint8_t p_z : 1; 1573 uint8_t n_y : 1; 1574 uint8_t p_y : 1; 1575 uint8_t n_x : 1; 1576 uint8_t p_x : 1; 1577 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1578 uint8_t p_x : 1; 1579 uint8_t n_x : 1; 1580 uint8_t p_y : 1; 1581 uint8_t n_y : 1; 1582 uint8_t p_z : 1; 1583 uint8_t n_z : 1; 1584 uint8_t p_v : 1; 1585 uint8_t n_v : 1; 1586 #endif /* DRV_BYTE_ORDER */ 1587 } lsm6dsr_fsm_outs4_t; 1588 1589 #define LSM6DSR_FSM_OUTS5 0x50U 1590 typedef struct 1591 { 1592 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1593 uint8_t n_v : 1; 1594 uint8_t p_v : 1; 1595 uint8_t n_z : 1; 1596 uint8_t p_z : 1; 1597 uint8_t n_y : 1; 1598 uint8_t p_y : 1; 1599 uint8_t n_x : 1; 1600 uint8_t p_x : 1; 1601 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1602 uint8_t p_x : 1; 1603 uint8_t n_x : 1; 1604 uint8_t p_y : 1; 1605 uint8_t n_y : 1; 1606 uint8_t p_z : 1; 1607 uint8_t n_z : 1; 1608 uint8_t p_v : 1; 1609 uint8_t n_v : 1; 1610 #endif /* DRV_BYTE_ORDER */ 1611 } lsm6dsr_fsm_outs5_t; 1612 1613 #define LSM6DSR_FSM_OUTS6 0x51U 1614 typedef struct 1615 { 1616 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1617 uint8_t n_v : 1; 1618 uint8_t p_v : 1; 1619 uint8_t n_z : 1; 1620 uint8_t p_z : 1; 1621 uint8_t n_y : 1; 1622 uint8_t p_y : 1; 1623 uint8_t n_x : 1; 1624 uint8_t p_x : 1; 1625 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1626 uint8_t p_x : 1; 1627 uint8_t n_x : 1; 1628 uint8_t p_y : 1; 1629 uint8_t n_y : 1; 1630 uint8_t p_z : 1; 1631 uint8_t n_z : 1; 1632 uint8_t p_v : 1; 1633 uint8_t n_v : 1; 1634 #endif /* DRV_BYTE_ORDER */ 1635 } lsm6dsr_fsm_outs6_t; 1636 1637 #define LSM6DSR_FSM_OUTS7 0x52U 1638 typedef struct 1639 { 1640 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1641 uint8_t n_v : 1; 1642 uint8_t p_v : 1; 1643 uint8_t n_z : 1; 1644 uint8_t p_z : 1; 1645 uint8_t n_y : 1; 1646 uint8_t p_y : 1; 1647 uint8_t n_x : 1; 1648 uint8_t p_x : 1; 1649 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1650 uint8_t p_x : 1; 1651 uint8_t n_x : 1; 1652 uint8_t p_y : 1; 1653 uint8_t n_y : 1; 1654 uint8_t p_z : 1; 1655 uint8_t n_z : 1; 1656 uint8_t p_v : 1; 1657 uint8_t n_v : 1; 1658 #endif /* DRV_BYTE_ORDER */ 1659 } lsm6dsr_fsm_outs7_t; 1660 1661 #define LSM6DSR_FSM_OUTS8 0x53U 1662 typedef struct 1663 { 1664 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1665 uint8_t n_v : 1; 1666 uint8_t p_v : 1; 1667 uint8_t n_z : 1; 1668 uint8_t p_z : 1; 1669 uint8_t n_y : 1; 1670 uint8_t p_y : 1; 1671 uint8_t n_x : 1; 1672 uint8_t p_x : 1; 1673 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1674 uint8_t p_x : 1; 1675 uint8_t n_x : 1; 1676 uint8_t p_y : 1; 1677 uint8_t n_y : 1; 1678 uint8_t p_z : 1; 1679 uint8_t n_z : 1; 1680 uint8_t p_v : 1; 1681 uint8_t n_v : 1; 1682 #endif /* DRV_BYTE_ORDER */ 1683 } lsm6dsr_fsm_outs8_t; 1684 1685 #define LSM6DSR_FSM_OUTS9 0x54U 1686 typedef struct 1687 { 1688 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1689 uint8_t n_v : 1; 1690 uint8_t p_v : 1; 1691 uint8_t n_z : 1; 1692 uint8_t p_z : 1; 1693 uint8_t n_y : 1; 1694 uint8_t p_y : 1; 1695 uint8_t n_x : 1; 1696 uint8_t p_x : 1; 1697 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1698 uint8_t p_x : 1; 1699 uint8_t n_x : 1; 1700 uint8_t p_y : 1; 1701 uint8_t n_y : 1; 1702 uint8_t p_z : 1; 1703 uint8_t n_z : 1; 1704 uint8_t p_v : 1; 1705 uint8_t n_v : 1; 1706 #endif /* DRV_BYTE_ORDER */ 1707 } lsm6dsr_fsm_outs9_t; 1708 1709 #define LSM6DSR_FSM_OUTS10 0x55U 1710 typedef struct 1711 { 1712 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1713 uint8_t n_v : 1; 1714 uint8_t p_v : 1; 1715 uint8_t n_z : 1; 1716 uint8_t p_z : 1; 1717 uint8_t n_y : 1; 1718 uint8_t p_y : 1; 1719 uint8_t n_x : 1; 1720 uint8_t p_x : 1; 1721 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1722 uint8_t p_x : 1; 1723 uint8_t n_x : 1; 1724 uint8_t p_y : 1; 1725 uint8_t n_y : 1; 1726 uint8_t p_z : 1; 1727 uint8_t n_z : 1; 1728 uint8_t p_v : 1; 1729 uint8_t n_v : 1; 1730 #endif /* DRV_BYTE_ORDER */ 1731 } lsm6dsr_fsm_outs10_t; 1732 1733 #define LSM6DSR_FSM_OUTS11 0x56U 1734 typedef struct 1735 { 1736 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1737 uint8_t n_v : 1; 1738 uint8_t p_v : 1; 1739 uint8_t n_z : 1; 1740 uint8_t p_z : 1; 1741 uint8_t n_y : 1; 1742 uint8_t p_y : 1; 1743 uint8_t n_x : 1; 1744 uint8_t p_x : 1; 1745 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1746 uint8_t p_x : 1; 1747 uint8_t n_x : 1; 1748 uint8_t p_y : 1; 1749 uint8_t n_y : 1; 1750 uint8_t p_z : 1; 1751 uint8_t n_z : 1; 1752 uint8_t p_v : 1; 1753 uint8_t n_v : 1; 1754 #endif /* DRV_BYTE_ORDER */ 1755 } lsm6dsr_fsm_outs11_t; 1756 1757 #define LSM6DSR_FSM_OUTS12 0x57U 1758 typedef struct 1759 { 1760 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1761 uint8_t n_v : 1; 1762 uint8_t p_v : 1; 1763 uint8_t n_z : 1; 1764 uint8_t p_z : 1; 1765 uint8_t n_y : 1; 1766 uint8_t p_y : 1; 1767 uint8_t n_x : 1; 1768 uint8_t p_x : 1; 1769 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1770 uint8_t p_x : 1; 1771 uint8_t n_x : 1; 1772 uint8_t p_y : 1; 1773 uint8_t n_y : 1; 1774 uint8_t p_z : 1; 1775 uint8_t n_z : 1; 1776 uint8_t p_v : 1; 1777 uint8_t n_v : 1; 1778 #endif /* DRV_BYTE_ORDER */ 1779 } lsm6dsr_fsm_outs12_t; 1780 1781 #define LSM6DSR_FSM_OUTS13 0x58U 1782 typedef struct 1783 { 1784 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1785 uint8_t n_v : 1; 1786 uint8_t p_v : 1; 1787 uint8_t n_z : 1; 1788 uint8_t p_z : 1; 1789 uint8_t n_y : 1; 1790 uint8_t p_y : 1; 1791 uint8_t n_x : 1; 1792 uint8_t p_x : 1; 1793 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1794 uint8_t p_x : 1; 1795 uint8_t n_x : 1; 1796 uint8_t p_y : 1; 1797 uint8_t n_y : 1; 1798 uint8_t p_z : 1; 1799 uint8_t n_z : 1; 1800 uint8_t p_v : 1; 1801 uint8_t n_v : 1; 1802 #endif /* DRV_BYTE_ORDER */ 1803 } lsm6dsr_fsm_outs13_t; 1804 1805 #define LSM6DSR_FSM_OUTS14 0x59U 1806 typedef struct 1807 { 1808 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1809 uint8_t n_v : 1; 1810 uint8_t p_v : 1; 1811 uint8_t n_z : 1; 1812 uint8_t p_z : 1; 1813 uint8_t n_y : 1; 1814 uint8_t p_y : 1; 1815 uint8_t n_x : 1; 1816 uint8_t p_x : 1; 1817 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1818 uint8_t p_x : 1; 1819 uint8_t n_x : 1; 1820 uint8_t p_y : 1; 1821 uint8_t n_y : 1; 1822 uint8_t p_z : 1; 1823 uint8_t n_z : 1; 1824 uint8_t p_v : 1; 1825 uint8_t n_v : 1; 1826 #endif /* DRV_BYTE_ORDER */ 1827 } lsm6dsr_fsm_outs14_t; 1828 1829 #define LSM6DSR_FSM_OUTS15 0x5AU 1830 typedef struct 1831 { 1832 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1833 uint8_t n_v : 1; 1834 uint8_t p_v : 1; 1835 uint8_t n_z : 1; 1836 uint8_t p_z : 1; 1837 uint8_t n_y : 1; 1838 uint8_t p_y : 1; 1839 uint8_t n_x : 1; 1840 uint8_t p_x : 1; 1841 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1842 uint8_t p_x : 1; 1843 uint8_t n_x : 1; 1844 uint8_t p_y : 1; 1845 uint8_t n_y : 1; 1846 uint8_t p_z : 1; 1847 uint8_t n_z : 1; 1848 uint8_t p_v : 1; 1849 uint8_t n_v : 1; 1850 #endif /* DRV_BYTE_ORDER */ 1851 } lsm6dsr_fsm_outs15_t; 1852 1853 #define LSM6DSR_FSM_OUTS16 0x5BU 1854 typedef struct 1855 { 1856 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1857 uint8_t n_v : 1; 1858 uint8_t p_v : 1; 1859 uint8_t n_z : 1; 1860 uint8_t p_z : 1; 1861 uint8_t n_y : 1; 1862 uint8_t p_y : 1; 1863 uint8_t n_x : 1; 1864 uint8_t p_x : 1; 1865 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1866 uint8_t p_x : 1; 1867 uint8_t n_x : 1; 1868 uint8_t p_y : 1; 1869 uint8_t n_y : 1; 1870 uint8_t p_z : 1; 1871 uint8_t n_z : 1; 1872 uint8_t p_v : 1; 1873 uint8_t n_v : 1; 1874 #endif /* DRV_BYTE_ORDER */ 1875 } lsm6dsr_fsm_outs16_t; 1876 1877 #define LSM6DSR_EMB_FUNC_ODR_CFG_B 0x5FU 1878 typedef struct 1879 { 1880 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1881 uint8_t not_used_01 : 3; 1882 uint8_t fsm_odr : 2; 1883 uint8_t not_used_02 : 3; 1884 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1885 uint8_t not_used_02 : 3; 1886 uint8_t fsm_odr : 2; 1887 uint8_t not_used_01 : 3; 1888 #endif /* DRV_BYTE_ORDER */ 1889 } lsm6dsr_emb_func_odr_cfg_b_t; 1890 1891 #define LSM6DSR_STEP_COUNTER_L 0x62U 1892 #define LSM6DSR_STEP_COUNTER_H 0x63U 1893 #define LSM6DSR_EMB_FUNC_SRC 0x64U 1894 typedef struct 1895 { 1896 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1897 uint8_t not_used_01 : 2; 1898 uint8_t stepcounter_bit_set : 1; 1899 uint8_t step_overflow : 1; 1900 uint8_t step_count_delta_ia : 1; 1901 uint8_t step_detected : 1; 1902 uint8_t not_used_02 : 1; 1903 uint8_t pedo_rst_step : 1; 1904 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1905 uint8_t pedo_rst_step : 1; 1906 uint8_t not_used_02 : 1; 1907 uint8_t step_detected : 1; 1908 uint8_t step_count_delta_ia : 1; 1909 uint8_t step_overflow : 1; 1910 uint8_t stepcounter_bit_set : 1; 1911 uint8_t not_used_01 : 2; 1912 #endif /* DRV_BYTE_ORDER */ 1913 } lsm6dsr_emb_func_src_t; 1914 1915 #define LSM6DSR_EMB_FUNC_INIT_A 0x66U 1916 typedef struct 1917 { 1918 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1919 uint8_t not_used_01 : 3; 1920 uint8_t step_det_init : 1; 1921 uint8_t tilt_init : 1; 1922 uint8_t sig_mot_init : 1; 1923 uint8_t not_used_02 : 2; 1924 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1925 uint8_t not_used_02 : 2; 1926 uint8_t sig_mot_init : 1; 1927 uint8_t tilt_init : 1; 1928 uint8_t step_det_init : 1; 1929 uint8_t not_used_01 : 3; 1930 #endif /* DRV_BYTE_ORDER */ 1931 } lsm6dsr_emb_func_init_a_t; 1932 1933 #define LSM6DSR_EMB_FUNC_INIT_B 0x67U 1934 typedef struct 1935 { 1936 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1937 uint8_t fsm_init : 1; 1938 uint8_t not_used_01 : 2; 1939 uint8_t fifo_compr_init : 1; 1940 uint8_t not_used_02 : 4; 1941 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1942 uint8_t not_used_02 : 4; 1943 uint8_t fifo_compr_init : 1; 1944 uint8_t not_used_01 : 2; 1945 uint8_t fsm_init : 1; 1946 #endif /* DRV_BYTE_ORDER */ 1947 } lsm6dsr_emb_func_init_b_t; 1948 1949 #define LSM6DSR_MAG_SENSITIVITY_L 0xBAU 1950 #define LSM6DSR_MAG_SENSITIVITY_H 0xBBU 1951 #define LSM6DSR_MAG_OFFX_L 0xC0U 1952 #define LSM6DSR_MAG_OFFX_H 0xC1U 1953 #define LSM6DSR_MAG_OFFY_L 0xC2U 1954 #define LSM6DSR_MAG_OFFY_H 0xC3U 1955 #define LSM6DSR_MAG_OFFZ_L 0xC4U 1956 #define LSM6DSR_MAG_OFFZ_H 0xC5U 1957 #define LSM6DSR_MAG_SI_XX_L 0xC6U 1958 #define LSM6DSR_MAG_SI_XX_H 0xC7U 1959 #define LSM6DSR_MAG_SI_XY_L 0xC8U 1960 #define LSM6DSR_MAG_SI_XY_H 0xC9U 1961 #define LSM6DSR_MAG_SI_XZ_L 0xCAU 1962 #define LSM6DSR_MAG_SI_XZ_H 0xCBU 1963 #define LSM6DSR_MAG_SI_YY_L 0xCCU 1964 #define LSM6DSR_MAG_SI_YY_H 0xCDU 1965 #define LSM6DSR_MAG_SI_YZ_L 0xCEU 1966 #define LSM6DSR_MAG_SI_YZ_H 0xCFU 1967 #define LSM6DSR_MAG_SI_ZZ_L 0xD0U 1968 #define LSM6DSR_MAG_SI_ZZ_H 0xD1U 1969 #define LSM6DSR_MAG_CFG_A 0xD4U 1970 typedef struct 1971 { 1972 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1973 uint8_t mag_z_axis : 3; 1974 uint8_t not_used_01 : 1; 1975 uint8_t mag_y_axis : 3; 1976 uint8_t not_used_02 : 1; 1977 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1978 uint8_t not_used_02 : 1; 1979 uint8_t mag_y_axis : 3; 1980 uint8_t not_used_01 : 1; 1981 uint8_t mag_z_axis : 3; 1982 #endif /* DRV_BYTE_ORDER */ 1983 } lsm6dsr_mag_cfg_a_t; 1984 1985 #define LSM6DSR_MAG_CFG_B 0xD5U 1986 typedef struct 1987 { 1988 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1989 uint8_t mag_x_axis : 3; 1990 uint8_t not_used_01 : 5; 1991 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1992 uint8_t not_used_01 : 5; 1993 uint8_t mag_x_axis : 3; 1994 #endif /* DRV_BYTE_ORDER */ 1995 } lsm6dsr_mag_cfg_b_t; 1996 1997 #define LSM6DSR_FSM_LC_TIMEOUT_L 0x17AU 1998 #define LSM6DSR_FSM_LC_TIMEOUT_H 0x17BU 1999 #define LSM6DSR_FSM_PROGRAMS 0x17CU 2000 #define LSM6DSR_FSM_START_ADD_L 0x17EU 2001 #define LSM6DSR_FSM_START_ADD_H 0x17FU 2002 #define LSM6DSR_PEDO_CMD_REG 0x183U 2003 typedef struct 2004 { 2005 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2006 uint8_t ad_det_en : 1; 2007 uint8_t not_used_01 : 1; 2008 uint8_t fp_rejection_en : 1; 2009 uint8_t carry_count_en : 1; 2010 uint8_t not_used_02 : 4; 2011 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2012 uint8_t not_used_02 : 4; 2013 uint8_t carry_count_en : 1; 2014 uint8_t fp_rejection_en : 1; 2015 uint8_t not_used_01 : 1; 2016 uint8_t ad_det_en : 1; 2017 #endif /* DRV_BYTE_ORDER */ 2018 } lsm6dsr_pedo_cmd_reg_t; 2019 2020 #define LSM6DSR_PEDO_DEB_STEPS_CONF 0x184U 2021 #define LSM6DSR_PEDO_SC_DELTAT_L 0x1D0U 2022 #define LSM6DSR_PEDO_SC_DELTAT_H 0x1D1U 2023 #define LSM6DSR_SENSOR_HUB_1 0x02U 2024 typedef struct 2025 { 2026 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2027 uint8_t bit0 : 1; 2028 uint8_t bit1 : 1; 2029 uint8_t bit2 : 1; 2030 uint8_t bit3 : 1; 2031 uint8_t bit4 : 1; 2032 uint8_t bit5 : 1; 2033 uint8_t bit6 : 1; 2034 uint8_t bit7 : 1; 2035 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2036 uint8_t bit7 : 1; 2037 uint8_t bit6 : 1; 2038 uint8_t bit5 : 1; 2039 uint8_t bit4 : 1; 2040 uint8_t bit3 : 1; 2041 uint8_t bit2 : 1; 2042 uint8_t bit1 : 1; 2043 uint8_t bit0 : 1; 2044 #endif /* DRV_BYTE_ORDER */ 2045 } lsm6dsr_sensor_hub_1_t; 2046 2047 #define LSM6DSR_SENSOR_HUB_2 0x03U 2048 typedef struct 2049 { 2050 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2051 uint8_t bit0 : 1; 2052 uint8_t bit1 : 1; 2053 uint8_t bit2 : 1; 2054 uint8_t bit3 : 1; 2055 uint8_t bit4 : 1; 2056 uint8_t bit5 : 1; 2057 uint8_t bit6 : 1; 2058 uint8_t bit7 : 1; 2059 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2060 uint8_t bit7 : 1; 2061 uint8_t bit6 : 1; 2062 uint8_t bit5 : 1; 2063 uint8_t bit4 : 1; 2064 uint8_t bit3 : 1; 2065 uint8_t bit2 : 1; 2066 uint8_t bit1 : 1; 2067 uint8_t bit0 : 1; 2068 #endif /* DRV_BYTE_ORDER */ 2069 } lsm6dsr_sensor_hub_2_t; 2070 2071 #define LSM6DSR_SENSOR_HUB_3 0x04U 2072 typedef struct 2073 { 2074 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2075 uint8_t bit0 : 1; 2076 uint8_t bit1 : 1; 2077 uint8_t bit2 : 1; 2078 uint8_t bit3 : 1; 2079 uint8_t bit4 : 1; 2080 uint8_t bit5 : 1; 2081 uint8_t bit6 : 1; 2082 uint8_t bit7 : 1; 2083 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2084 uint8_t bit7 : 1; 2085 uint8_t bit6 : 1; 2086 uint8_t bit5 : 1; 2087 uint8_t bit4 : 1; 2088 uint8_t bit3 : 1; 2089 uint8_t bit2 : 1; 2090 uint8_t bit1 : 1; 2091 uint8_t bit0 : 1; 2092 #endif /* DRV_BYTE_ORDER */ 2093 } lsm6dsr_sensor_hub_3_t; 2094 2095 #define LSM6DSR_SENSOR_HUB_4 0x05U 2096 typedef struct 2097 { 2098 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2099 uint8_t bit0 : 1; 2100 uint8_t bit1 : 1; 2101 uint8_t bit2 : 1; 2102 uint8_t bit3 : 1; 2103 uint8_t bit4 : 1; 2104 uint8_t bit5 : 1; 2105 uint8_t bit6 : 1; 2106 uint8_t bit7 : 1; 2107 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2108 uint8_t bit7 : 1; 2109 uint8_t bit6 : 1; 2110 uint8_t bit5 : 1; 2111 uint8_t bit4 : 1; 2112 uint8_t bit3 : 1; 2113 uint8_t bit2 : 1; 2114 uint8_t bit1 : 1; 2115 uint8_t bit0 : 1; 2116 #endif /* DRV_BYTE_ORDER */ 2117 } lsm6dsr_sensor_hub_4_t; 2118 2119 #define LSM6DSR_SENSOR_HUB_5 0x06U 2120 typedef struct 2121 { 2122 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2123 uint8_t bit0 : 1; 2124 uint8_t bit1 : 1; 2125 uint8_t bit2 : 1; 2126 uint8_t bit3 : 1; 2127 uint8_t bit4 : 1; 2128 uint8_t bit5 : 1; 2129 uint8_t bit6 : 1; 2130 uint8_t bit7 : 1; 2131 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2132 uint8_t bit7 : 1; 2133 uint8_t bit6 : 1; 2134 uint8_t bit5 : 1; 2135 uint8_t bit4 : 1; 2136 uint8_t bit3 : 1; 2137 uint8_t bit2 : 1; 2138 uint8_t bit1 : 1; 2139 uint8_t bit0 : 1; 2140 #endif /* DRV_BYTE_ORDER */ 2141 } lsm6dsr_sensor_hub_5_t; 2142 2143 #define LSM6DSR_SENSOR_HUB_6 0x07U 2144 typedef struct 2145 { 2146 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2147 uint8_t bit0 : 1; 2148 uint8_t bit1 : 1; 2149 uint8_t bit2 : 1; 2150 uint8_t bit3 : 1; 2151 uint8_t bit4 : 1; 2152 uint8_t bit5 : 1; 2153 uint8_t bit6 : 1; 2154 uint8_t bit7 : 1; 2155 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2156 uint8_t bit7 : 1; 2157 uint8_t bit6 : 1; 2158 uint8_t bit5 : 1; 2159 uint8_t bit4 : 1; 2160 uint8_t bit3 : 1; 2161 uint8_t bit2 : 1; 2162 uint8_t bit1 : 1; 2163 uint8_t bit0 : 1; 2164 #endif /* DRV_BYTE_ORDER */ 2165 } lsm6dsr_sensor_hub_6_t; 2166 2167 #define LSM6DSR_SENSOR_HUB_7 0x08U 2168 typedef struct 2169 { 2170 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2171 uint8_t bit0 : 1; 2172 uint8_t bit1 : 1; 2173 uint8_t bit2 : 1; 2174 uint8_t bit3 : 1; 2175 uint8_t bit4 : 1; 2176 uint8_t bit5 : 1; 2177 uint8_t bit6 : 1; 2178 uint8_t bit7 : 1; 2179 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2180 uint8_t bit7 : 1; 2181 uint8_t bit6 : 1; 2182 uint8_t bit5 : 1; 2183 uint8_t bit4 : 1; 2184 uint8_t bit3 : 1; 2185 uint8_t bit2 : 1; 2186 uint8_t bit1 : 1; 2187 uint8_t bit0 : 1; 2188 #endif /* DRV_BYTE_ORDER */ 2189 } lsm6dsr_sensor_hub_7_t; 2190 2191 #define LSM6DSR_SENSOR_HUB_8 0x09U 2192 typedef struct 2193 { 2194 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2195 uint8_t bit0 : 1; 2196 uint8_t bit1 : 1; 2197 uint8_t bit2 : 1; 2198 uint8_t bit3 : 1; 2199 uint8_t bit4 : 1; 2200 uint8_t bit5 : 1; 2201 uint8_t bit6 : 1; 2202 uint8_t bit7 : 1; 2203 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2204 uint8_t bit7 : 1; 2205 uint8_t bit6 : 1; 2206 uint8_t bit5 : 1; 2207 uint8_t bit4 : 1; 2208 uint8_t bit3 : 1; 2209 uint8_t bit2 : 1; 2210 uint8_t bit1 : 1; 2211 uint8_t bit0 : 1; 2212 #endif /* DRV_BYTE_ORDER */ 2213 } lsm6dsr_sensor_hub_8_t; 2214 2215 #define LSM6DSR_SENSOR_HUB_9 0x0AU 2216 typedef struct 2217 { 2218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2219 uint8_t bit0 : 1; 2220 uint8_t bit1 : 1; 2221 uint8_t bit2 : 1; 2222 uint8_t bit3 : 1; 2223 uint8_t bit4 : 1; 2224 uint8_t bit5 : 1; 2225 uint8_t bit6 : 1; 2226 uint8_t bit7 : 1; 2227 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2228 uint8_t bit7 : 1; 2229 uint8_t bit6 : 1; 2230 uint8_t bit5 : 1; 2231 uint8_t bit4 : 1; 2232 uint8_t bit3 : 1; 2233 uint8_t bit2 : 1; 2234 uint8_t bit1 : 1; 2235 uint8_t bit0 : 1; 2236 #endif /* DRV_BYTE_ORDER */ 2237 } lsm6dsr_sensor_hub_9_t; 2238 2239 #define LSM6DSR_SENSOR_HUB_10 0x0BU 2240 typedef struct 2241 { 2242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2243 uint8_t bit0 : 1; 2244 uint8_t bit1 : 1; 2245 uint8_t bit2 : 1; 2246 uint8_t bit3 : 1; 2247 uint8_t bit4 : 1; 2248 uint8_t bit5 : 1; 2249 uint8_t bit6 : 1; 2250 uint8_t bit7 : 1; 2251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2252 uint8_t bit7 : 1; 2253 uint8_t bit6 : 1; 2254 uint8_t bit5 : 1; 2255 uint8_t bit4 : 1; 2256 uint8_t bit3 : 1; 2257 uint8_t bit2 : 1; 2258 uint8_t bit1 : 1; 2259 uint8_t bit0 : 1; 2260 #endif /* DRV_BYTE_ORDER */ 2261 } lsm6dsr_sensor_hub_10_t; 2262 2263 #define LSM6DSR_SENSOR_HUB_11 0x0CU 2264 typedef struct 2265 { 2266 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2267 uint8_t bit0 : 1; 2268 uint8_t bit1 : 1; 2269 uint8_t bit2 : 1; 2270 uint8_t bit3 : 1; 2271 uint8_t bit4 : 1; 2272 uint8_t bit5 : 1; 2273 uint8_t bit6 : 1; 2274 uint8_t bit7 : 1; 2275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2276 uint8_t bit7 : 1; 2277 uint8_t bit6 : 1; 2278 uint8_t bit5 : 1; 2279 uint8_t bit4 : 1; 2280 uint8_t bit3 : 1; 2281 uint8_t bit2 : 1; 2282 uint8_t bit1 : 1; 2283 uint8_t bit0 : 1; 2284 #endif /* DRV_BYTE_ORDER */ 2285 } lsm6dsr_sensor_hub_11_t; 2286 2287 #define LSM6DSR_SENSOR_HUB_12 0x0DU 2288 typedef struct 2289 { 2290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2291 uint8_t bit0 : 1; 2292 uint8_t bit1 : 1; 2293 uint8_t bit2 : 1; 2294 uint8_t bit3 : 1; 2295 uint8_t bit4 : 1; 2296 uint8_t bit5 : 1; 2297 uint8_t bit6 : 1; 2298 uint8_t bit7 : 1; 2299 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2300 uint8_t bit7 : 1; 2301 uint8_t bit6 : 1; 2302 uint8_t bit5 : 1; 2303 uint8_t bit4 : 1; 2304 uint8_t bit3 : 1; 2305 uint8_t bit2 : 1; 2306 uint8_t bit1 : 1; 2307 uint8_t bit0 : 1; 2308 #endif /* DRV_BYTE_ORDER */ 2309 } lsm6dsr_sensor_hub_12_t; 2310 2311 #define LSM6DSR_SENSOR_HUB_13 0x0EU 2312 typedef struct 2313 { 2314 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2315 uint8_t bit0 : 1; 2316 uint8_t bit1 : 1; 2317 uint8_t bit2 : 1; 2318 uint8_t bit3 : 1; 2319 uint8_t bit4 : 1; 2320 uint8_t bit5 : 1; 2321 uint8_t bit6 : 1; 2322 uint8_t bit7 : 1; 2323 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2324 uint8_t bit7 : 1; 2325 uint8_t bit6 : 1; 2326 uint8_t bit5 : 1; 2327 uint8_t bit4 : 1; 2328 uint8_t bit3 : 1; 2329 uint8_t bit2 : 1; 2330 uint8_t bit1 : 1; 2331 uint8_t bit0 : 1; 2332 #endif /* DRV_BYTE_ORDER */ 2333 } lsm6dsr_sensor_hub_13_t; 2334 2335 #define LSM6DSR_SENSOR_HUB_14 0x0FU 2336 typedef struct 2337 { 2338 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2339 uint8_t bit0 : 1; 2340 uint8_t bit1 : 1; 2341 uint8_t bit2 : 1; 2342 uint8_t bit3 : 1; 2343 uint8_t bit4 : 1; 2344 uint8_t bit5 : 1; 2345 uint8_t bit6 : 1; 2346 uint8_t bit7 : 1; 2347 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2348 uint8_t bit7 : 1; 2349 uint8_t bit6 : 1; 2350 uint8_t bit5 : 1; 2351 uint8_t bit4 : 1; 2352 uint8_t bit3 : 1; 2353 uint8_t bit2 : 1; 2354 uint8_t bit1 : 1; 2355 uint8_t bit0 : 1; 2356 #endif /* DRV_BYTE_ORDER */ 2357 } lsm6dsr_sensor_hub_14_t; 2358 2359 #define LSM6DSR_SENSOR_HUB_15 0x10U 2360 typedef struct 2361 { 2362 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2363 uint8_t bit0 : 1; 2364 uint8_t bit1 : 1; 2365 uint8_t bit2 : 1; 2366 uint8_t bit3 : 1; 2367 uint8_t bit4 : 1; 2368 uint8_t bit5 : 1; 2369 uint8_t bit6 : 1; 2370 uint8_t bit7 : 1; 2371 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2372 uint8_t bit7 : 1; 2373 uint8_t bit6 : 1; 2374 uint8_t bit5 : 1; 2375 uint8_t bit4 : 1; 2376 uint8_t bit3 : 1; 2377 uint8_t bit2 : 1; 2378 uint8_t bit1 : 1; 2379 uint8_t bit0 : 1; 2380 #endif /* DRV_BYTE_ORDER */ 2381 } lsm6dsr_sensor_hub_15_t; 2382 2383 #define LSM6DSR_SENSOR_HUB_16 0x11U 2384 typedef struct 2385 { 2386 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2387 uint8_t bit0 : 1; 2388 uint8_t bit1 : 1; 2389 uint8_t bit2 : 1; 2390 uint8_t bit3 : 1; 2391 uint8_t bit4 : 1; 2392 uint8_t bit5 : 1; 2393 uint8_t bit6 : 1; 2394 uint8_t bit7 : 1; 2395 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2396 uint8_t bit7 : 1; 2397 uint8_t bit6 : 1; 2398 uint8_t bit5 : 1; 2399 uint8_t bit4 : 1; 2400 uint8_t bit3 : 1; 2401 uint8_t bit2 : 1; 2402 uint8_t bit1 : 1; 2403 uint8_t bit0 : 1; 2404 #endif /* DRV_BYTE_ORDER */ 2405 } lsm6dsr_sensor_hub_16_t; 2406 2407 #define LSM6DSR_SENSOR_HUB_17 0x12U 2408 typedef struct 2409 { 2410 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2411 uint8_t bit0 : 1; 2412 uint8_t bit1 : 1; 2413 uint8_t bit2 : 1; 2414 uint8_t bit3 : 1; 2415 uint8_t bit4 : 1; 2416 uint8_t bit5 : 1; 2417 uint8_t bit6 : 1; 2418 uint8_t bit7 : 1; 2419 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2420 uint8_t bit7 : 1; 2421 uint8_t bit6 : 1; 2422 uint8_t bit5 : 1; 2423 uint8_t bit4 : 1; 2424 uint8_t bit3 : 1; 2425 uint8_t bit2 : 1; 2426 uint8_t bit1 : 1; 2427 uint8_t bit0 : 1; 2428 #endif /* DRV_BYTE_ORDER */ 2429 } lsm6dsr_sensor_hub_17_t; 2430 2431 #define LSM6DSR_SENSOR_HUB_18 0x13U 2432 typedef struct 2433 { 2434 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2435 uint8_t bit0 : 1; 2436 uint8_t bit1 : 1; 2437 uint8_t bit2 : 1; 2438 uint8_t bit3 : 1; 2439 uint8_t bit4 : 1; 2440 uint8_t bit5 : 1; 2441 uint8_t bit6 : 1; 2442 uint8_t bit7 : 1; 2443 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2444 uint8_t bit7 : 1; 2445 uint8_t bit6 : 1; 2446 uint8_t bit5 : 1; 2447 uint8_t bit4 : 1; 2448 uint8_t bit3 : 1; 2449 uint8_t bit2 : 1; 2450 uint8_t bit1 : 1; 2451 uint8_t bit0 : 1; 2452 #endif /* DRV_BYTE_ORDER */ 2453 } lsm6dsr_sensor_hub_18_t; 2454 2455 #define LSM6DSR_MASTER_CONFIG 0x14U 2456 typedef struct 2457 { 2458 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2459 uint8_t aux_sens_on : 2; 2460 uint8_t master_on : 1; 2461 uint8_t shub_pu_en : 1; 2462 uint8_t pass_through_mode : 1; 2463 uint8_t start_config : 1; 2464 uint8_t write_once : 1; 2465 uint8_t rst_master_regs : 1; 2466 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2467 uint8_t rst_master_regs : 1; 2468 uint8_t write_once : 1; 2469 uint8_t start_config : 1; 2470 uint8_t pass_through_mode : 1; 2471 uint8_t shub_pu_en : 1; 2472 uint8_t master_on : 1; 2473 uint8_t aux_sens_on : 2; 2474 #endif /* DRV_BYTE_ORDER */ 2475 } lsm6dsr_master_config_t; 2476 2477 #define LSM6DSR_SLV0_ADD 0x15U 2478 typedef struct 2479 { 2480 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2481 uint8_t rw_0 : 1; 2482 uint8_t slave0 : 7; 2483 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2484 uint8_t slave0 : 7; 2485 uint8_t rw_0 : 1; 2486 #endif /* DRV_BYTE_ORDER */ 2487 } lsm6dsr_slv0_add_t; 2488 2489 #define LSM6DSR_SLV0_SUBADD 0x16U 2490 typedef struct 2491 { 2492 uint8_t slave0_reg : 8; 2493 } lsm6dsr_slv0_subadd_t; 2494 2495 #define LSM6DSR_SLV0_CONFIG 0x17U 2496 typedef struct 2497 { 2498 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2499 uint8_t slave0_numop : 3; 2500 uint8_t batch_ext_sens_0_en : 1; 2501 uint8_t not_used_01 : 2; 2502 uint8_t shub_odr : 2; 2503 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2504 uint8_t shub_odr : 2; 2505 uint8_t not_used_01 : 2; 2506 uint8_t batch_ext_sens_0_en : 1; 2507 uint8_t slave0_numop : 3; 2508 #endif /* DRV_BYTE_ORDER */ 2509 } lsm6dsr_slv0_config_t; 2510 2511 #define LSM6DSR_SLV1_ADD 0x18U 2512 typedef struct 2513 { 2514 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2515 uint8_t r_1 : 1; 2516 uint8_t slave1_add : 7; 2517 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2518 uint8_t slave1_add : 7; 2519 uint8_t r_1 : 1; 2520 #endif /* DRV_BYTE_ORDER */ 2521 } lsm6dsr_slv1_add_t; 2522 2523 #define LSM6DSR_SLV1_SUBADD 0x19U 2524 typedef struct 2525 { 2526 uint8_t slave1_reg : 8; 2527 } lsm6dsr_slv1_subadd_t; 2528 2529 #define LSM6DSR_SLV1_CONFIG 0x1AU 2530 typedef struct 2531 { 2532 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2533 uint8_t slave1_numop : 3; 2534 uint8_t batch_ext_sens_1_en : 1; 2535 uint8_t not_used_01 : 4; 2536 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2537 uint8_t not_used_01 : 4; 2538 uint8_t batch_ext_sens_1_en : 1; 2539 uint8_t slave1_numop : 3; 2540 #endif /* DRV_BYTE_ORDER */ 2541 } lsm6dsr_slv1_config_t; 2542 2543 #define LSM6DSR_SLV2_ADD 0x1BU 2544 typedef struct 2545 { 2546 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2547 uint8_t r_2 : 1; 2548 uint8_t slave2_add : 7; 2549 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2550 uint8_t slave2_add : 7; 2551 uint8_t r_2 : 1; 2552 #endif /* DRV_BYTE_ORDER */ 2553 } lsm6dsr_slv2_add_t; 2554 2555 #define LSM6DSR_SLV2_SUBADD 0x1CU 2556 typedef struct 2557 { 2558 uint8_t slave2_reg : 8; 2559 } lsm6dsr_slv2_subadd_t; 2560 2561 #define LSM6DSR_SLV2_CONFIG 0x1DU 2562 typedef struct 2563 { 2564 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2565 uint8_t slave2_numop : 3; 2566 uint8_t batch_ext_sens_2_en : 1; 2567 uint8_t not_used_01 : 4; 2568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2569 uint8_t not_used_01 : 4; 2570 uint8_t batch_ext_sens_2_en : 1; 2571 uint8_t slave2_numop : 3; 2572 #endif /* DRV_BYTE_ORDER */ 2573 } lsm6dsr_slv2_config_t; 2574 2575 #define LSM6DSR_SLV3_ADD 0x1EU 2576 typedef struct 2577 { 2578 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2579 uint8_t r_3 : 1; 2580 uint8_t slave3_add : 7; 2581 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2582 uint8_t slave3_add : 7; 2583 uint8_t r_3 : 1; 2584 #endif /* DRV_BYTE_ORDER */ 2585 } lsm6dsr_slv3_add_t; 2586 2587 #define LSM6DSR_SLV3_SUBADD 0x1FU 2588 typedef struct 2589 { 2590 uint8_t slave3_reg : 8; 2591 } lsm6dsr_slv3_subadd_t; 2592 2593 #define LSM6DSR_SLV3_CONFIG 0x20U 2594 typedef struct 2595 { 2596 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2597 uint8_t slave3_numop : 3; 2598 uint8_t batch_ext_sens_3_en : 1; 2599 uint8_t not_used_01 : 4; 2600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2601 uint8_t not_used_01 : 4; 2602 uint8_t batch_ext_sens_3_en : 1; 2603 uint8_t slave3_numop : 3; 2604 #endif /* DRV_BYTE_ORDER */ 2605 } lsm6dsr_slv3_config_t; 2606 2607 #define LSM6DSR_DATAWRITE_SLV0 0x21U 2608 typedef struct 2609 { 2610 uint8_t slave0_dataw : 8; 2611 } lsm6dsr_datawrite_slv0_t; 2612 2613 #define LSM6DSR_STATUS_MASTER 0x22U 2614 typedef struct 2615 { 2616 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2617 uint8_t sens_hub_endop : 1; 2618 uint8_t not_used_01 : 2; 2619 uint8_t slave0_nack : 1; 2620 uint8_t slave1_nack : 1; 2621 uint8_t slave2_nack : 1; 2622 uint8_t slave3_nack : 1; 2623 uint8_t wr_once_done : 1; 2624 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2625 uint8_t wr_once_done : 1; 2626 uint8_t slave3_nack : 1; 2627 uint8_t slave2_nack : 1; 2628 uint8_t slave1_nack : 1; 2629 uint8_t slave0_nack : 1; 2630 uint8_t not_used_01 : 2; 2631 uint8_t sens_hub_endop : 1; 2632 #endif /* DRV_BYTE_ORDER */ 2633 } lsm6dsr_status_master_t; 2634 2635 /** 2636 * @defgroup LSM6DSR_Register_Union 2637 * @brief This union group all the registers having a bit-field 2638 * description. 2639 * This union is useful but it's not needed by the driver. 2640 * 2641 * REMOVING this union you are compliant with: 2642 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2643 * 2644 * @{ 2645 * 2646 */ 2647 typedef union 2648 { 2649 lsm6dsr_func_cfg_access_t func_cfg_access; 2650 lsm6dsr_pin_ctrl_t pin_ctrl; 2651 lsm6dsr_s4s_tph_l_t s4s_tph_l; 2652 lsm6dsr_s4s_tph_h_t s4s_tph_h; 2653 lsm6dsr_s4s_rr_t s4s_rr; 2654 lsm6dsr_fifo_ctrl1_t fifo_ctrl1; 2655 lsm6dsr_fifo_ctrl2_t fifo_ctrl2; 2656 lsm6dsr_fifo_ctrl3_t fifo_ctrl3; 2657 lsm6dsr_fifo_ctrl4_t fifo_ctrl4; 2658 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1; 2659 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2; 2660 lsm6dsr_int1_ctrl_t int1_ctrl; 2661 lsm6dsr_int2_ctrl_t int2_ctrl; 2662 lsm6dsr_ctrl1_xl_t ctrl1_xl; 2663 lsm6dsr_ctrl2_g_t ctrl2_g; 2664 lsm6dsr_ctrl3_c_t ctrl3_c; 2665 lsm6dsr_ctrl4_c_t ctrl4_c; 2666 lsm6dsr_ctrl5_c_t ctrl5_c; 2667 lsm6dsr_ctrl6_c_t ctrl6_c; 2668 lsm6dsr_ctrl7_g_t ctrl7_g; 2669 lsm6dsr_ctrl8_xl_t ctrl8_xl; 2670 lsm6dsr_ctrl9_xl_t ctrl9_xl; 2671 lsm6dsr_ctrl10_c_t ctrl10_c; 2672 lsm6dsr_all_int_src_t all_int_src; 2673 lsm6dsr_wake_up_src_t wake_up_src; 2674 lsm6dsr_tap_src_t tap_src; 2675 lsm6dsr_d6d_src_t d6d_src; 2676 lsm6dsr_status_reg_t status_reg; 2677 lsm6dsr_status_spiaux_t status_spiaux; 2678 lsm6dsr_fifo_status1_t fifo_status1; 2679 lsm6dsr_fifo_status2_t fifo_status2; 2680 lsm6dsr_tap_cfg0_t tap_cfg0; 2681 lsm6dsr_tap_cfg1_t tap_cfg1; 2682 lsm6dsr_tap_cfg2_t tap_cfg2; 2683 lsm6dsr_tap_ths_6d_t tap_ths_6d; 2684 lsm6dsr_int_dur2_t int_dur2; 2685 lsm6dsr_wake_up_ths_t wake_up_ths; 2686 lsm6dsr_wake_up_dur_t wake_up_dur; 2687 lsm6dsr_free_fall_t free_fall; 2688 lsm6dsr_md1_cfg_t md1_cfg; 2689 lsm6dsr_md2_cfg_t md2_cfg; 2690 lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code; 2691 lsm6dsr_s4s_dt_reg_t s4s_dt_reg; 2692 lsm6dsr_i3c_bus_avb_t i3c_bus_avb; 2693 lsm6dsr_internal_freq_fine_t internal_freq_fine; 2694 lsm6dsr_int_ois_t int_ois; 2695 lsm6dsr_ctrl1_ois_t ctrl1_ois; 2696 lsm6dsr_ctrl2_ois_t ctrl2_ois; 2697 lsm6dsr_ctrl3_ois_t ctrl3_ois; 2698 lsm6dsr_fifo_data_out_tag_t fifo_data_out_tag; 2699 lsm6dsr_page_sel_t page_sel; 2700 lsm6dsr_emb_func_en_a_t emb_func_en_a; 2701 lsm6dsr_emb_func_en_b_t emb_func_en_b; 2702 lsm6dsr_page_address_t page_address; 2703 lsm6dsr_page_value_t page_value; 2704 lsm6dsr_emb_func_int1_t emb_func_int1; 2705 lsm6dsr_fsm_int1_a_t fsm_int1_a; 2706 lsm6dsr_fsm_int1_b_t fsm_int1_b; 2707 lsm6dsr_emb_func_int2_t emb_func_int2; 2708 lsm6dsr_fsm_int2_a_t fsm_int2_a; 2709 lsm6dsr_fsm_int2_b_t fsm_int2_b; 2710 lsm6dsr_emb_func_status_t emb_func_status; 2711 lsm6dsr_fsm_status_a_t fsm_status_a; 2712 lsm6dsr_fsm_status_b_t fsm_status_b; 2713 lsm6dsr_page_rw_t page_rw; 2714 lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2715 lsm6dsr_fsm_enable_a_t fsm_enable_a; 2716 lsm6dsr_fsm_enable_b_t fsm_enable_b; 2717 lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear; 2718 lsm6dsr_fsm_outs1_t fsm_outs1; 2719 lsm6dsr_fsm_outs2_t fsm_outs2; 2720 lsm6dsr_fsm_outs3_t fsm_outs3; 2721 lsm6dsr_fsm_outs4_t fsm_outs4; 2722 lsm6dsr_fsm_outs5_t fsm_outs5; 2723 lsm6dsr_fsm_outs6_t fsm_outs6; 2724 lsm6dsr_fsm_outs7_t fsm_outs7; 2725 lsm6dsr_fsm_outs8_t fsm_outs8; 2726 lsm6dsr_fsm_outs9_t fsm_outs9; 2727 lsm6dsr_fsm_outs10_t fsm_outs10; 2728 lsm6dsr_fsm_outs11_t fsm_outs11; 2729 lsm6dsr_fsm_outs12_t fsm_outs12; 2730 lsm6dsr_fsm_outs13_t fsm_outs13; 2731 lsm6dsr_fsm_outs14_t fsm_outs14; 2732 lsm6dsr_fsm_outs15_t fsm_outs15; 2733 lsm6dsr_fsm_outs16_t fsm_outs16; 2734 lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2735 lsm6dsr_emb_func_src_t emb_func_src; 2736 lsm6dsr_emb_func_init_a_t emb_func_init_a; 2737 lsm6dsr_emb_func_init_b_t emb_func_init_b; 2738 lsm6dsr_mag_cfg_a_t mag_cfg_a; 2739 lsm6dsr_mag_cfg_b_t mag_cfg_b; 2740 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg; 2741 lsm6dsr_sensor_hub_1_t sensor_hub_1; 2742 lsm6dsr_sensor_hub_2_t sensor_hub_2; 2743 lsm6dsr_sensor_hub_3_t sensor_hub_3; 2744 lsm6dsr_sensor_hub_4_t sensor_hub_4; 2745 lsm6dsr_sensor_hub_5_t sensor_hub_5; 2746 lsm6dsr_sensor_hub_6_t sensor_hub_6; 2747 lsm6dsr_sensor_hub_7_t sensor_hub_7; 2748 lsm6dsr_sensor_hub_8_t sensor_hub_8; 2749 lsm6dsr_sensor_hub_9_t sensor_hub_9; 2750 lsm6dsr_sensor_hub_10_t sensor_hub_10; 2751 lsm6dsr_sensor_hub_11_t sensor_hub_11; 2752 lsm6dsr_sensor_hub_12_t sensor_hub_12; 2753 lsm6dsr_sensor_hub_13_t sensor_hub_13; 2754 lsm6dsr_sensor_hub_14_t sensor_hub_14; 2755 lsm6dsr_sensor_hub_15_t sensor_hub_15; 2756 lsm6dsr_sensor_hub_16_t sensor_hub_16; 2757 lsm6dsr_sensor_hub_17_t sensor_hub_17; 2758 lsm6dsr_sensor_hub_18_t sensor_hub_18; 2759 lsm6dsr_master_config_t master_config; 2760 lsm6dsr_slv0_add_t slv0_add; 2761 lsm6dsr_slv0_subadd_t slv0_subadd; 2762 lsm6dsr_slv0_config_t slv0_config; 2763 lsm6dsr_slv1_add_t slv1_add; 2764 lsm6dsr_slv1_subadd_t slv1_subadd; 2765 lsm6dsr_slv1_config_t slv1_config; 2766 lsm6dsr_slv2_add_t slv2_add; 2767 lsm6dsr_slv2_subadd_t slv2_subadd; 2768 lsm6dsr_slv2_config_t slv2_config; 2769 lsm6dsr_slv3_add_t slv3_add; 2770 lsm6dsr_slv3_subadd_t slv3_subadd; 2771 lsm6dsr_slv3_config_t slv3_config; 2772 lsm6dsr_datawrite_slv0_t datawrite_slv0; 2773 lsm6dsr_status_master_t status_master; 2774 bitwise_t bitwise; 2775 uint8_t byte; 2776 } lsm6dsr_reg_t; 2777 2778 /** 2779 * @} 2780 * 2781 */ 2782 2783 #ifndef __weak 2784 #define __weak __attribute__((weak)) 2785 #endif /* __weak */ 2786 2787 /* 2788 * These are the basic platform dependent I/O routines to read 2789 * and write device registers connected on a standard bus. 2790 * The driver keeps offering a default implementation based on function 2791 * pointers to read/write routines for backward compatibility. 2792 * The __weak directive allows the final application to overwrite 2793 * them with a custom implementation. 2794 */ 2795 2796 int32_t lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 2797 uint8_t *data, 2798 uint16_t len); 2799 int32_t lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 2800 uint8_t *data, 2801 uint16_t len); 2802 2803 float_t lsm6dsr_from_fs2g_to_mg(int16_t lsb); 2804 float_t lsm6dsr_from_fs4g_to_mg(int16_t lsb); 2805 float_t lsm6dsr_from_fs8g_to_mg(int16_t lsb); 2806 float_t lsm6dsr_from_fs16g_to_mg(int16_t lsb); 2807 2808 float_t lsm6dsr_from_fs125dps_to_mdps(int16_t lsb); 2809 float_t lsm6dsr_from_fs250dps_to_mdps(int16_t lsb); 2810 float_t lsm6dsr_from_fs500dps_to_mdps(int16_t lsb); 2811 float_t lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb); 2812 float_t lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb); 2813 float_t lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb); 2814 2815 float_t lsm6dsr_from_lsb_to_celsius(int16_t lsb); 2816 2817 float_t lsm6dsr_from_lsb_to_nsec(int32_t lsb); 2818 2819 typedef enum 2820 { 2821 LSM6DSR_2g = 0, 2822 LSM6DSR_16g = 1, /* if XL_FS_MODE = '1' -> LSM6DSR_2g */ 2823 LSM6DSR_4g = 2, 2824 LSM6DSR_8g = 3, 2825 } lsm6dsr_fs_xl_t; 2826 int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx, 2827 lsm6dsr_fs_xl_t val); 2828 int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx, 2829 lsm6dsr_fs_xl_t *val); 2830 2831 typedef enum 2832 { 2833 LSM6DSR_XL_ODR_OFF = 0, 2834 LSM6DSR_XL_ODR_12Hz5 = 1, 2835 LSM6DSR_XL_ODR_26Hz = 2, 2836 LSM6DSR_XL_ODR_52Hz = 3, 2837 LSM6DSR_XL_ODR_104Hz = 4, 2838 LSM6DSR_XL_ODR_208Hz = 5, 2839 LSM6DSR_XL_ODR_416Hz = 6, 2840 LSM6DSR_XL_ODR_833Hz = 7, 2841 LSM6DSR_XL_ODR_1666Hz = 8, 2842 LSM6DSR_XL_ODR_3332Hz = 9, 2843 LSM6DSR_XL_ODR_6667Hz = 10, 2844 LSM6DSR_XL_ODR_1Hz6 = 11, /* (low power only) */ 2845 } lsm6dsr_odr_xl_t; 2846 int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx, 2847 lsm6dsr_odr_xl_t val); 2848 int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx, 2849 lsm6dsr_odr_xl_t *val); 2850 2851 typedef enum 2852 { 2853 LSM6DSR_125dps = 2, 2854 LSM6DSR_250dps = 0, 2855 LSM6DSR_500dps = 4, 2856 LSM6DSR_1000dps = 8, 2857 LSM6DSR_2000dps = 12, 2858 LSM6DSR_4000dps = 1, 2859 } lsm6dsr_fs_g_t; 2860 int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx, 2861 lsm6dsr_fs_g_t val); 2862 int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx, 2863 lsm6dsr_fs_g_t *val); 2864 2865 typedef enum 2866 { 2867 LSM6DSR_GY_ODR_OFF = 0, 2868 LSM6DSR_GY_ODR_12Hz5 = 1, 2869 LSM6DSR_GY_ODR_26Hz = 2, 2870 LSM6DSR_GY_ODR_52Hz = 3, 2871 LSM6DSR_GY_ODR_104Hz = 4, 2872 LSM6DSR_GY_ODR_208Hz = 5, 2873 LSM6DSR_GY_ODR_416Hz = 6, 2874 LSM6DSR_GY_ODR_833Hz = 7, 2875 LSM6DSR_GY_ODR_1666Hz = 8, 2876 LSM6DSR_GY_ODR_3332Hz = 9, 2877 LSM6DSR_GY_ODR_6667Hz = 10, 2878 } lsm6dsr_odr_g_t; 2879 int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx, 2880 lsm6dsr_odr_g_t val); 2881 int32_t lsm6dsr_gy_data_rate_get(stmdev_ctx_t *ctx, 2882 lsm6dsr_odr_g_t *val); 2883 2884 int32_t lsm6dsr_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 2885 int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx, 2886 uint8_t *val); 2887 2888 typedef enum 2889 { 2890 LSM6DSR_LSb_1mg = 0, 2891 LSM6DSR_LSb_16mg = 1, 2892 } lsm6dsr_usr_off_w_t; 2893 int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx, 2894 lsm6dsr_usr_off_w_t val); 2895 int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx, 2896 lsm6dsr_usr_off_w_t *val); 2897 2898 typedef enum 2899 { 2900 LSM6DSR_HIGH_PERFORMANCE_MD = 0, 2901 LSM6DSR_LOW_NORMAL_POWER_MD = 1, 2902 } lsm6dsr_xl_hm_mode_t; 2903 int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx, 2904 lsm6dsr_xl_hm_mode_t val); 2905 int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx, 2906 lsm6dsr_xl_hm_mode_t *val); 2907 2908 typedef enum 2909 { 2910 LSM6DSR_GY_HIGH_PERFORMANCE = 0, 2911 LSM6DSR_GY_NORMAL = 1, 2912 } lsm6dsr_g_hm_mode_t; 2913 int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx, 2914 lsm6dsr_g_hm_mode_t val); 2915 int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx, 2916 lsm6dsr_g_hm_mode_t *val); 2917 2918 typedef struct 2919 { 2920 lsm6dsr_all_int_src_t all_int_src; 2921 lsm6dsr_wake_up_src_t wake_up_src; 2922 lsm6dsr_tap_src_t tap_src; 2923 lsm6dsr_d6d_src_t d6d_src; 2924 lsm6dsr_status_reg_t status_reg; 2925 lsm6dsr_emb_func_status_t emb_func_status; 2926 lsm6dsr_fsm_status_a_t fsm_status_a; 2927 lsm6dsr_fsm_status_b_t fsm_status_b; 2928 } lsm6dsr_all_sources_t; 2929 int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx, 2930 lsm6dsr_all_sources_t *val); 2931 2932 int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx, 2933 lsm6dsr_status_reg_t *val); 2934 2935 int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2936 uint8_t *val); 2937 2938 int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 2939 uint8_t *val); 2940 2941 int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 2942 uint8_t *val); 2943 2944 int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff); 2945 int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff); 2946 2947 int32_t lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff); 2948 int32_t lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff); 2949 2950 int32_t lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff); 2951 int32_t lsm6dsr_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff); 2952 2953 int32_t lsm6dsr_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); 2954 int32_t lsm6dsr_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); 2955 2956 int32_t lsm6dsr_timestamp_rst(stmdev_ctx_t *ctx); 2957 2958 int32_t lsm6dsr_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2959 int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2960 2961 int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 2962 2963 typedef enum 2964 { 2965 LSM6DSR_NO_ROUND = 0, 2966 LSM6DSR_ROUND_XL = 1, 2967 LSM6DSR_ROUND_GY = 2, 2968 LSM6DSR_ROUND_GY_XL = 3, 2969 } lsm6dsr_rounding_t; 2970 int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx, 2971 lsm6dsr_rounding_t val); 2972 int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx, 2973 lsm6dsr_rounding_t *val); 2974 2975 int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2976 2977 int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2978 2979 int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2980 2981 int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); 2982 2983 int32_t lsm6dsr_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2984 int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2985 2986 int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val); 2987 2988 int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx); 2989 2990 typedef enum 2991 { 2992 LSM6DSR_USER_BANK = 0, 2993 LSM6DSR_SENSOR_HUB_BANK = 1, 2994 LSM6DSR_EMBEDDED_FUNC_BANK = 2, 2995 } lsm6dsr_reg_access_t; 2996 int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx, 2997 lsm6dsr_reg_access_t val); 2998 int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx, 2999 lsm6dsr_reg_access_t *val); 3000 3001 int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, 3002 uint8_t *val); 3003 int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 3004 uint8_t *buf, uint8_t len); 3005 int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, 3006 uint8_t *val); 3007 int32_t lsm6dsr_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 3008 uint8_t *val); 3009 3010 typedef enum 3011 { 3012 LSM6DSR_DRDY_LATCHED = 0, 3013 LSM6DSR_DRDY_PULSED = 1, 3014 } lsm6dsr_dataready_pulsed_t; 3015 int32_t lsm6dsr_data_ready_mode_set(stmdev_ctx_t *ctx, 3016 lsm6dsr_dataready_pulsed_t val); 3017 int32_t lsm6dsr_data_ready_mode_get(stmdev_ctx_t *ctx, 3018 lsm6dsr_dataready_pulsed_t *val); 3019 3020 int32_t lsm6dsr_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 3021 3022 int32_t lsm6dsr_reset_set(stmdev_ctx_t *ctx, uint8_t val); 3023 int32_t lsm6dsr_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 3024 3025 int32_t lsm6dsr_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 3026 int32_t lsm6dsr_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 3027 3028 int32_t lsm6dsr_boot_set(stmdev_ctx_t *ctx, uint8_t val); 3029 int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 3030 3031 typedef enum 3032 { 3033 LSM6DSR_XL_ST_DISABLE = 0, 3034 LSM6DSR_XL_ST_POSITIVE = 1, 3035 LSM6DSR_XL_ST_NEGATIVE = 2, 3036 } lsm6dsr_st_xl_t; 3037 int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx, 3038 lsm6dsr_st_xl_t val); 3039 int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx, 3040 lsm6dsr_st_xl_t *val); 3041 3042 typedef enum 3043 { 3044 LSM6DSR_GY_ST_DISABLE = 0, 3045 LSM6DSR_GY_ST_POSITIVE = 1, 3046 LSM6DSR_GY_ST_NEGATIVE = 3, 3047 } lsm6dsr_st_g_t; 3048 int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx, 3049 lsm6dsr_st_g_t val); 3050 int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx, 3051 lsm6dsr_st_g_t *val); 3052 3053 int32_t lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 3054 int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 3055 3056 int32_t lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 3057 int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 3058 3059 int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx, 3060 uint8_t val); 3061 int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx, 3062 uint8_t *val); 3063 3064 typedef enum 3065 { 3066 LSM6DSR_ULTRA_LIGHT = 0, 3067 LSM6DSR_VERY_LIGHT = 1, 3068 LSM6DSR_LIGHT = 2, 3069 LSM6DSR_MEDIUM = 3, 3070 LSM6DSR_STRONG = 4, 3071 LSM6DSR_VERY_STRONG = 5, 3072 LSM6DSR_AGGRESSIVE = 6, 3073 LSM6DSR_XTREME = 7, 3074 } lsm6dsr_ftype_t; 3075 int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 3076 lsm6dsr_ftype_t val); 3077 int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 3078 lsm6dsr_ftype_t *val); 3079 3080 int32_t lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); 3081 int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); 3082 3083 typedef enum 3084 { 3085 LSM6DSR_HP_PATH_DISABLE_ON_OUT = 0x00, 3086 LSM6DSR_SLOPE_ODR_DIV_4 = 0x10, 3087 LSM6DSR_HP_ODR_DIV_10 = 0x11, 3088 LSM6DSR_HP_ODR_DIV_20 = 0x12, 3089 LSM6DSR_HP_ODR_DIV_45 = 0x13, 3090 LSM6DSR_HP_ODR_DIV_100 = 0x14, 3091 LSM6DSR_HP_ODR_DIV_200 = 0x15, 3092 LSM6DSR_HP_ODR_DIV_400 = 0x16, 3093 LSM6DSR_HP_ODR_DIV_800 = 0x17, 3094 LSM6DSR_HP_REF_MD_ODR_DIV_10 = 0x31, 3095 LSM6DSR_HP_REF_MD_ODR_DIV_20 = 0x32, 3096 LSM6DSR_HP_REF_MD_ODR_DIV_45 = 0x33, 3097 LSM6DSR_HP_REF_MD_ODR_DIV_100 = 0x34, 3098 LSM6DSR_HP_REF_MD_ODR_DIV_200 = 0x35, 3099 LSM6DSR_HP_REF_MD_ODR_DIV_400 = 0x36, 3100 LSM6DSR_HP_REF_MD_ODR_DIV_800 = 0x37, 3101 LSM6DSR_LP_ODR_DIV_10 = 0x01, 3102 LSM6DSR_LP_ODR_DIV_20 = 0x02, 3103 LSM6DSR_LP_ODR_DIV_45 = 0x03, 3104 LSM6DSR_LP_ODR_DIV_100 = 0x04, 3105 LSM6DSR_LP_ODR_DIV_200 = 0x05, 3106 LSM6DSR_LP_ODR_DIV_400 = 0x06, 3107 LSM6DSR_LP_ODR_DIV_800 = 0x07, 3108 } lsm6dsr_hp_slope_xl_en_t; 3109 int32_t lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, 3110 lsm6dsr_hp_slope_xl_en_t val); 3111 int32_t lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, 3112 lsm6dsr_hp_slope_xl_en_t *val); 3113 3114 int32_t lsm6dsr_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); 3115 int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val); 3116 3117 typedef enum 3118 { 3119 LSM6DSR_USE_SLOPE = 0, 3120 LSM6DSR_USE_HPF = 1, 3121 } lsm6dsr_slope_fds_t; 3122 int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 3123 lsm6dsr_slope_fds_t val); 3124 int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 3125 lsm6dsr_slope_fds_t *val); 3126 3127 typedef enum 3128 { 3129 LSM6DSR_HP_FILTER_NONE = 0x00, 3130 LSM6DSR_HP_FILTER_16mHz = 0x80, 3131 LSM6DSR_HP_FILTER_65mHz = 0x81, 3132 LSM6DSR_HP_FILTER_260mHz = 0x82, 3133 LSM6DSR_HP_FILTER_1Hz04 = 0x83, 3134 } lsm6dsr_hpm_g_t; 3135 int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx, 3136 lsm6dsr_hpm_g_t val); 3137 int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx, 3138 lsm6dsr_hpm_g_t *val); 3139 3140 typedef enum 3141 { 3142 LSM6DSR_AUX_PULL_UP_DISC = 0, 3143 LSM6DSR_AUX_PULL_UP_CONNECT = 1, 3144 } lsm6dsr_ois_pu_dis_t; 3145 int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx, 3146 lsm6dsr_ois_pu_dis_t val); 3147 int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx, 3148 lsm6dsr_ois_pu_dis_t *val); 3149 3150 typedef enum 3151 { 3152 LSM6DSR_AUX_ON = 1, 3153 LSM6DSR_AUX_ON_BY_AUX_INTERFACE = 0, 3154 } lsm6dsr_ois_on_t; 3155 int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx, 3156 lsm6dsr_ois_on_t val); 3157 int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx, 3158 lsm6dsr_ois_on_t *val); 3159 3160 int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx, 3161 lsm6dsr_status_spiaux_t *val); 3162 3163 int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 3164 uint8_t *val); 3165 3166 int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 3167 uint8_t *val); 3168 3169 int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx, 3170 uint8_t *val); 3171 3172 typedef enum 3173 { 3174 LSM6DSR_AUX_XL_DISABLE = 0, 3175 LSM6DSR_AUX_XL_POS = 1, 3176 LSM6DSR_AUX_XL_NEG = 2, 3177 } lsm6dsr_st_xl_ois_t; 3178 int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx, 3179 lsm6dsr_st_xl_ois_t val); 3180 int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx, 3181 lsm6dsr_st_xl_ois_t *val); 3182 3183 typedef enum 3184 { 3185 LSM6DSR_AUX_DEN_ACTIVE_LOW = 0, 3186 LSM6DSR_AUX_DEN_ACTIVE_HIGH = 1, 3187 } lsm6dsr_den_lh_ois_t; 3188 int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx, 3189 lsm6dsr_den_lh_ois_t val); 3190 int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx, 3191 lsm6dsr_den_lh_ois_t *val); 3192 3193 typedef enum 3194 { 3195 LSM6DSR_AUX_DEN_DISABLE = 0, 3196 LSM6DSR_AUX_DEN_LEVEL_LATCH = 3, 3197 LSM6DSR_AUX_DEN_LEVEL_TRIG = 2, 3198 } lsm6dsr_lvl2_ois_t; 3199 int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx, 3200 lsm6dsr_lvl2_ois_t val); 3201 int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx, 3202 lsm6dsr_lvl2_ois_t *val); 3203 3204 int32_t lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val); 3205 int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val); 3206 3207 typedef enum 3208 { 3209 LSM6DSR_AUX_DISABLE = 0, 3210 LSM6DSR_MODE_3_GY = 1, 3211 LSM6DSR_MODE_4_GY_XL = 3, 3212 } lsm6dsr_ois_en_spi2_t; 3213 int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx, 3214 lsm6dsr_ois_en_spi2_t val); 3215 int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx, 3216 lsm6dsr_ois_en_spi2_t *val); 3217 3218 typedef enum 3219 { 3220 LSM6DSR_125dps_AUX = 0x04, 3221 LSM6DSR_250dps_AUX = 0x00, 3222 LSM6DSR_500dps_AUX = 0x01, 3223 LSM6DSR_1000dps_AUX = 0x02, 3224 LSM6DSR_2000dps_AUX = 0x03, 3225 } lsm6dsr_fs_g_ois_t; 3226 int32_t lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t *ctx, 3227 lsm6dsr_fs_g_ois_t val); 3228 int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx, 3229 lsm6dsr_fs_g_ois_t *val); 3230 3231 typedef enum 3232 { 3233 LSM6DSR_AUX_SPI_4_WIRE = 0, 3234 LSM6DSR_AUX_SPI_3_WIRE = 1, 3235 } lsm6dsr_sim_ois_t; 3236 int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx, 3237 lsm6dsr_sim_ois_t val); 3238 int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx, 3239 lsm6dsr_sim_ois_t *val); 3240 3241 typedef enum 3242 { 3243 LSM6DSR_351Hz39 = 0, 3244 LSM6DSR_236Hz63 = 1, 3245 LSM6DSR_172Hz70 = 2, 3246 LSM6DSR_937Hz91 = 3, 3247 } lsm6dsr_ftype_ois_t; 3248 int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 3249 lsm6dsr_ftype_ois_t val); 3250 int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 3251 lsm6dsr_ftype_ois_t *val); 3252 3253 typedef enum 3254 { 3255 LSM6DSR_AUX_HP_DISABLE = 0x00, 3256 LSM6DSR_AUX_HP_Hz016 = 0x10, 3257 LSM6DSR_AUX_HP_Hz065 = 0x11, 3258 LSM6DSR_AUX_HP_Hz260 = 0x12, 3259 LSM6DSR_AUX_HP_1Hz040 = 0x13, 3260 } lsm6dsr_hpm_ois_t; 3261 int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, 3262 lsm6dsr_hpm_ois_t val); 3263 int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, 3264 lsm6dsr_hpm_ois_t *val); 3265 3266 typedef enum 3267 { 3268 LSM6DSR_ENABLE_CLAMP = 0, 3269 LSM6DSR_DISABLE_CLAMP = 1, 3270 } lsm6dsr_st_ois_clampdis_t; 3271 int32_t lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t *ctx, 3272 lsm6dsr_st_ois_clampdis_t val); 3273 int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx, 3274 lsm6dsr_st_ois_clampdis_t *val); 3275 3276 typedef enum 3277 { 3278 LSM6DSR_AUX_GY_DISABLE = 0, 3279 LSM6DSR_AUX_GY_POS = 1, 3280 LSM6DSR_AUX_GY_NEG = 3, 3281 } lsm6dsr_st_ois_t; 3282 int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx, 3283 lsm6dsr_st_ois_t val); 3284 int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx, 3285 lsm6dsr_st_ois_t *val); 3286 3287 typedef enum 3288 { 3289 LSM6DSR_631Hz = 0, 3290 LSM6DSR_295Hz = 1, 3291 LSM6DSR_140Hz = 2, 3292 LSM6DSR_68Hz2 = 3, 3293 LSM6DSR_33Hz6 = 4, 3294 LSM6DSR_16Hz7 = 5, 3295 LSM6DSR_8Hz3 = 6, 3296 LSM6DSR_4Hz11 = 7, 3297 } lsm6dsr_filter_xl_conf_ois_t; 3298 int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx, 3299 lsm6dsr_filter_xl_conf_ois_t val); 3300 int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx, 3301 lsm6dsr_filter_xl_conf_ois_t *val); 3302 3303 typedef enum 3304 { 3305 LSM6DSR_AUX_2g = 0, 3306 LSM6DSR_AUX_16g = 1, 3307 LSM6DSR_AUX_4g = 2, 3308 LSM6DSR_AUX_8g = 3, 3309 } lsm6dsr_fs_xl_ois_t; 3310 int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx, 3311 lsm6dsr_fs_xl_ois_t val); 3312 int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx, 3313 lsm6dsr_fs_xl_ois_t *val); 3314 3315 typedef enum 3316 { 3317 LSM6DSR_PULL_UP_DISC = 0, 3318 LSM6DSR_PULL_UP_CONNECT = 1, 3319 } lsm6dsr_sdo_pu_en_t; 3320 int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 3321 lsm6dsr_sdo_pu_en_t val); 3322 int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 3323 lsm6dsr_sdo_pu_en_t *val); 3324 3325 typedef enum 3326 { 3327 LSM6DSR_PULL_DOWN_CONNECT = 0, 3328 LSM6DSR_PULL_DOWN_DISC = 1, 3329 } lsm6dsr_pd_dis_int1_t; 3330 int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx, 3331 lsm6dsr_pd_dis_int1_t val); 3332 int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx, 3333 lsm6dsr_pd_dis_int1_t *val); 3334 3335 typedef enum 3336 { 3337 LSM6DSR_SPI_4_WIRE = 0, 3338 LSM6DSR_SPI_3_WIRE = 1, 3339 } lsm6dsr_sim_t; 3340 int32_t lsm6dsr_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_t val); 3341 int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val); 3342 3343 typedef enum 3344 { 3345 LSM6DSR_I2C_ENABLE = 0, 3346 LSM6DSR_I2C_DISABLE = 1, 3347 } lsm6dsr_i2c_disable_t; 3348 int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx, 3349 lsm6dsr_i2c_disable_t val); 3350 int32_t lsm6dsr_i2c_interface_get(stmdev_ctx_t *ctx, 3351 lsm6dsr_i2c_disable_t *val); 3352 3353 typedef enum 3354 { 3355 LSM6DSR_I3C_DISABLE = 0x80, 3356 LSM6DSR_I3C_ENABLE_T_50us = 0x00, 3357 LSM6DSR_I3C_ENABLE_T_2us = 0x01, 3358 LSM6DSR_I3C_ENABLE_T_1ms = 0x02, 3359 LSM6DSR_I3C_ENABLE_T_25ms = 0x03, 3360 } lsm6dsr_i3c_disable_t; 3361 int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx, 3362 lsm6dsr_i3c_disable_t val); 3363 int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx, 3364 lsm6dsr_i3c_disable_t *val); 3365 3366 typedef struct 3367 { 3368 lsm6dsr_int1_ctrl_t int1_ctrl; 3369 lsm6dsr_md1_cfg_t md1_cfg; 3370 lsm6dsr_emb_func_int1_t emb_func_int1; 3371 lsm6dsr_fsm_int1_a_t fsm_int1_a; 3372 lsm6dsr_fsm_int1_b_t fsm_int1_b; 3373 } lsm6dsr_pin_int1_route_t; 3374 int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx, 3375 lsm6dsr_pin_int1_route_t *val); 3376 int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx, 3377 lsm6dsr_pin_int1_route_t *val); 3378 3379 typedef struct 3380 { 3381 lsm6dsr_int2_ctrl_t int2_ctrl; 3382 lsm6dsr_md2_cfg_t md2_cfg; 3383 lsm6dsr_emb_func_int2_t emb_func_int2; 3384 lsm6dsr_fsm_int2_a_t fsm_int2_a; 3385 lsm6dsr_fsm_int2_b_t fsm_int2_b; 3386 } lsm6dsr_pin_int2_route_t; 3387 int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx, 3388 lsm6dsr_pin_int2_route_t *val); 3389 int32_t lsm6dsr_pin_int2_route_get(stmdev_ctx_t *ctx, 3390 lsm6dsr_pin_int2_route_t *val); 3391 3392 typedef enum 3393 { 3394 LSM6DSR_PUSH_PULL = 0, 3395 LSM6DSR_OPEN_DRAIN = 1, 3396 } lsm6dsr_pp_od_t; 3397 int32_t lsm6dsr_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val); 3398 int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val); 3399 3400 typedef enum 3401 { 3402 LSM6DSR_ACTIVE_HIGH = 0, 3403 LSM6DSR_ACTIVE_LOW = 1, 3404 } lsm6dsr_h_lactive_t; 3405 int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx, 3406 lsm6dsr_h_lactive_t val); 3407 int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx, 3408 lsm6dsr_h_lactive_t *val); 3409 3410 int32_t lsm6dsr_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 3411 int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 3412 3413 typedef enum 3414 { 3415 LSM6DSR_ALL_INT_PULSED = 0, 3416 LSM6DSR_BASE_LATCHED_EMB_PULSED = 1, 3417 LSM6DSR_BASE_PULSED_EMB_LATCHED = 2, 3418 LSM6DSR_ALL_INT_LATCHED = 3, 3419 } lsm6dsr_lir_t; 3420 int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx, 3421 lsm6dsr_lir_t val); 3422 int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx, 3423 lsm6dsr_lir_t *val); 3424 3425 typedef enum 3426 { 3427 LSM6DSR_LSb_FS_DIV_64 = 0, 3428 LSM6DSR_LSb_FS_DIV_256 = 1, 3429 } lsm6dsr_wake_ths_w_t; 3430 int32_t lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t *ctx, 3431 lsm6dsr_wake_ths_w_t val); 3432 int32_t lsm6dsr_wkup_ths_weight_get(stmdev_ctx_t *ctx, 3433 lsm6dsr_wake_ths_w_t *val); 3434 3435 int32_t lsm6dsr_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 3436 int32_t lsm6dsr_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 3437 3438 int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, 3439 uint8_t val); 3440 int32_t lsm6dsr_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, 3441 uint8_t *val); 3442 3443 int32_t lsm6dsr_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3444 int32_t lsm6dsr_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3445 3446 int32_t lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3447 int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3448 3449 typedef enum 3450 { 3451 LSM6DSR_DRIVE_SLEEP_CHG_EVENT = 0, 3452 LSM6DSR_DRIVE_SLEEP_STATUS = 1, 3453 } lsm6dsr_sleep_status_on_int_t; 3454 int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx, 3455 lsm6dsr_sleep_status_on_int_t val); 3456 int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx, 3457 lsm6dsr_sleep_status_on_int_t *val); 3458 3459 typedef enum 3460 { 3461 LSM6DSR_XL_AND_GY_NOT_AFFECTED = 0, 3462 LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED = 1, 3463 LSM6DSR_XL_12Hz5_GY_SLEEP = 2, 3464 LSM6DSR_XL_12Hz5_GY_PD = 3, 3465 } lsm6dsr_inact_en_t; 3466 int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx, 3467 lsm6dsr_inact_en_t val); 3468 int32_t lsm6dsr_act_mode_get(stmdev_ctx_t *ctx, 3469 lsm6dsr_inact_en_t *val); 3470 3471 int32_t lsm6dsr_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3472 int32_t lsm6dsr_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3473 3474 int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, 3475 uint8_t val); 3476 int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx, 3477 uint8_t *val); 3478 3479 int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, 3480 uint8_t val); 3481 int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx, 3482 uint8_t *val); 3483 3484 int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, 3485 uint8_t val); 3486 int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx, 3487 uint8_t *val); 3488 3489 int32_t lsm6dsr_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); 3490 int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); 3491 3492 typedef enum 3493 { 3494 LSM6DSR_XYZ = 0, 3495 LSM6DSR_YXZ = 1, 3496 LSM6DSR_XZY = 2, 3497 LSM6DSR_ZYX = 3, 3498 LSM6DSR_YZX = 5, 3499 LSM6DSR_ZXY = 6, 3500 } lsm6dsr_tap_priority_t; 3501 int32_t lsm6dsr_tap_axis_priority_set(stmdev_ctx_t *ctx, 3502 lsm6dsr_tap_priority_t val); 3503 int32_t lsm6dsr_tap_axis_priority_get(stmdev_ctx_t *ctx, 3504 lsm6dsr_tap_priority_t *val); 3505 3506 int32_t lsm6dsr_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); 3507 int32_t lsm6dsr_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); 3508 3509 int32_t lsm6dsr_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); 3510 int32_t lsm6dsr_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val); 3511 3512 int32_t lsm6dsr_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 3513 int32_t lsm6dsr_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 3514 3515 int32_t lsm6dsr_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 3516 int32_t lsm6dsr_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 3517 3518 int32_t lsm6dsr_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3519 int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3520 3521 typedef enum 3522 { 3523 LSM6DSR_ONLY_SINGLE = 0, 3524 LSM6DSR_BOTH_SINGLE_DOUBLE = 1, 3525 } lsm6dsr_single_double_tap_t; 3526 int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx, 3527 lsm6dsr_single_double_tap_t val); 3528 int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx, 3529 lsm6dsr_single_double_tap_t *val); 3530 3531 typedef enum 3532 { 3533 LSM6DSR_DEG_80 = 0, 3534 LSM6DSR_DEG_70 = 1, 3535 LSM6DSR_DEG_60 = 2, 3536 LSM6DSR_DEG_50 = 3, 3537 } lsm6dsr_sixd_ths_t; 3538 int32_t lsm6dsr_6d_threshold_set(stmdev_ctx_t *ctx, 3539 lsm6dsr_sixd_ths_t val); 3540 int32_t lsm6dsr_6d_threshold_get(stmdev_ctx_t *ctx, 3541 lsm6dsr_sixd_ths_t *val); 3542 3543 int32_t lsm6dsr_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3544 int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3545 3546 typedef enum 3547 { 3548 LSM6DSR_FF_TSH_156mg = 0, 3549 LSM6DSR_FF_TSH_219mg = 1, 3550 LSM6DSR_FF_TSH_250mg = 2, 3551 LSM6DSR_FF_TSH_312mg = 3, 3552 LSM6DSR_FF_TSH_344mg = 4, 3553 LSM6DSR_FF_TSH_406mg = 5, 3554 LSM6DSR_FF_TSH_469mg = 6, 3555 LSM6DSR_FF_TSH_500mg = 7, 3556 } lsm6dsr_ff_ths_t; 3557 int32_t lsm6dsr_ff_threshold_set(stmdev_ctx_t *ctx, 3558 lsm6dsr_ff_ths_t val); 3559 int32_t lsm6dsr_ff_threshold_get(stmdev_ctx_t *ctx, 3560 lsm6dsr_ff_ths_t *val); 3561 3562 int32_t lsm6dsr_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3563 int32_t lsm6dsr_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3564 3565 int32_t lsm6dsr_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 3566 int32_t lsm6dsr_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); 3567 3568 int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx, 3569 uint8_t val); 3570 int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx, 3571 uint8_t *val); 3572 3573 typedef enum 3574 { 3575 LSM6DSR_CMP_DISABLE = 0x00, 3576 LSM6DSR_CMP_ALWAYS = 0x04, 3577 LSM6DSR_CMP_8_TO_1 = 0x05, 3578 LSM6DSR_CMP_16_TO_1 = 0x06, 3579 LSM6DSR_CMP_32_TO_1 = 0x07, 3580 } lsm6dsr_uncoptr_rate_t; 3581 int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx, 3582 lsm6dsr_uncoptr_rate_t val); 3583 int32_t lsm6dsr_compression_algo_get(stmdev_ctx_t *ctx, 3584 lsm6dsr_uncoptr_rate_t *val); 3585 3586 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 3587 uint8_t val); 3588 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 3589 uint8_t *val); 3590 3591 int32_t lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t *ctx, 3592 uint8_t val); 3593 int32_t lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t *ctx, 3594 uint8_t *val); 3595 3596 int32_t lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 3597 int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 3598 3599 typedef enum 3600 { 3601 LSM6DSR_XL_NOT_BATCHED = 0, 3602 LSM6DSR_XL_BATCHED_AT_12Hz5 = 1, 3603 LSM6DSR_XL_BATCHED_AT_26Hz = 2, 3604 LSM6DSR_XL_BATCHED_AT_52Hz = 3, 3605 LSM6DSR_XL_BATCHED_AT_104Hz = 4, 3606 LSM6DSR_XL_BATCHED_AT_208Hz = 5, 3607 LSM6DSR_XL_BATCHED_AT_417Hz = 6, 3608 LSM6DSR_XL_BATCHED_AT_833Hz = 7, 3609 LSM6DSR_XL_BATCHED_AT_1667Hz = 8, 3610 LSM6DSR_XL_BATCHED_AT_3333Hz = 9, 3611 LSM6DSR_XL_BATCHED_AT_6667Hz = 10, 3612 LSM6DSR_XL_BATCHED_AT_6Hz5 = 11, 3613 } lsm6dsr_bdr_xl_t; 3614 int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx, 3615 lsm6dsr_bdr_xl_t val); 3616 int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx, 3617 lsm6dsr_bdr_xl_t *val); 3618 3619 typedef enum 3620 { 3621 LSM6DSR_GY_NOT_BATCHED = 0, 3622 LSM6DSR_GY_BATCHED_AT_12Hz5 = 1, 3623 LSM6DSR_GY_BATCHED_AT_26Hz = 2, 3624 LSM6DSR_GY_BATCHED_AT_52Hz = 3, 3625 LSM6DSR_GY_BATCHED_AT_104Hz = 4, 3626 LSM6DSR_GY_BATCHED_AT_208Hz = 5, 3627 LSM6DSR_GY_BATCHED_AT_417Hz = 6, 3628 LSM6DSR_GY_BATCHED_AT_833Hz = 7, 3629 LSM6DSR_GY_BATCHED_AT_1667Hz = 8, 3630 LSM6DSR_GY_BATCHED_AT_3333Hz = 9, 3631 LSM6DSR_GY_BATCHED_AT_6667Hz = 10, 3632 LSM6DSR_GY_BATCHED_6Hz5 = 11, 3633 } lsm6dsr_bdr_gy_t; 3634 int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx, 3635 lsm6dsr_bdr_gy_t val); 3636 int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx, 3637 lsm6dsr_bdr_gy_t *val); 3638 3639 typedef enum 3640 { 3641 LSM6DSR_BYPASS_MODE = 0, 3642 LSM6DSR_FIFO_MODE = 1, 3643 LSM6DSR_STREAM_TO_FIFO_MODE = 3, 3644 LSM6DSR_BYPASS_TO_STREAM_MODE = 4, 3645 LSM6DSR_STREAM_MODE = 6, 3646 LSM6DSR_BYPASS_TO_FIFO_MODE = 7, 3647 } lsm6dsr_fifo_mode_t; 3648 int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx, 3649 lsm6dsr_fifo_mode_t val); 3650 int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx, 3651 lsm6dsr_fifo_mode_t *val); 3652 3653 typedef enum 3654 { 3655 LSM6DSR_TEMP_NOT_BATCHED = 0, 3656 LSM6DSR_TEMP_BATCHED_AT_52Hz = 1, 3657 LSM6DSR_TEMP_BATCHED_AT_12Hz5 = 2, 3658 LSM6DSR_TEMP_BATCHED_AT_1Hz6 = 3, 3659 } lsm6dsr_odr_t_batch_t; 3660 int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx, 3661 lsm6dsr_odr_t_batch_t val); 3662 int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx, 3663 lsm6dsr_odr_t_batch_t *val); 3664 3665 typedef enum 3666 { 3667 LSM6DSR_NO_DECIMATION = 0, 3668 LSM6DSR_DEC_1 = 1, 3669 LSM6DSR_DEC_8 = 2, 3670 LSM6DSR_DEC_32 = 3, 3671 } lsm6dsr_odr_ts_batch_t; 3672 int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, 3673 lsm6dsr_odr_ts_batch_t val); 3674 int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, 3675 lsm6dsr_odr_ts_batch_t *val); 3676 3677 typedef enum 3678 { 3679 LSM6DSR_XL_BATCH_EVENT = 0, 3680 LSM6DSR_GYRO_BATCH_EVENT = 1, 3681 } lsm6dsr_trig_counter_bdr_t; 3682 int32_t lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, 3683 lsm6dsr_trig_counter_bdr_t val); 3684 int32_t lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, 3685 lsm6dsr_trig_counter_bdr_t *val); 3686 3687 int32_t lsm6dsr_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val); 3688 int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, 3689 uint8_t *val); 3690 3691 int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx, 3692 uint16_t val); 3693 int32_t lsm6dsr_batch_counter_threshold_get(stmdev_ctx_t *ctx, 3694 uint16_t *val); 3695 3696 int32_t lsm6dsr_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); 3697 3698 int32_t lsm6dsr_fifo_status_get(stmdev_ctx_t *ctx, 3699 lsm6dsr_fifo_status2_t *val); 3700 3701 int32_t lsm6dsr_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3702 3703 int32_t lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3704 3705 int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3706 3707 typedef enum 3708 { 3709 LSM6DSR_GYRO_NC_TAG = 1, 3710 LSM6DSR_XL_NC_TAG, 3711 LSM6DSR_TEMPERATURE_TAG, 3712 LSM6DSR_TIMESTAMP_TAG, 3713 LSM6DSR_CFG_CHANGE_TAG, 3714 LSM6DSR_XL_NC_T_2_TAG, 3715 LSM6DSR_XL_NC_T_1_TAG, 3716 LSM6DSR_XL_2XC_TAG, 3717 LSM6DSR_XL_3XC_TAG, 3718 LSM6DSR_GYRO_NC_T_2_TAG, 3719 LSM6DSR_GYRO_NC_T_1_TAG, 3720 LSM6DSR_GYRO_2XC_TAG, 3721 LSM6DSR_GYRO_3XC_TAG, 3722 LSM6DSR_SENSORHUB_SLAVE0_TAG, 3723 LSM6DSR_SENSORHUB_SLAVE1_TAG, 3724 LSM6DSR_SENSORHUB_SLAVE2_TAG, 3725 LSM6DSR_SENSORHUB_SLAVE3_TAG, 3726 LSM6DSR_STEP_CPUNTER_TAG, 3727 LSM6DSR_GAME_ROTATION_TAG, 3728 LSM6DSR_GEOMAG_ROTATION_TAG, 3729 LSM6DSR_ROTATION_TAG, 3730 LSM6DSR_SENSORHUB_NACK_TAG = 0x19, 3731 } lsm6dsr_fifo_tag_t; 3732 int32_t lsm6dsr_fifo_sensor_tag_get(stmdev_ctx_t *ctx, 3733 lsm6dsr_fifo_tag_t *val); 3734 3735 int32_t lsm6dsr_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3736 int32_t lsm6dsr_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 3737 3738 int32_t lsm6dsr_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); 3739 int32_t lsm6dsr_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val); 3740 3741 int32_t lsm6dsr_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); 3742 int32_t lsm6dsr_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val); 3743 3744 int32_t lsm6dsr_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); 3745 int32_t lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val); 3746 3747 int32_t lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); 3748 int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val); 3749 3750 typedef enum 3751 { 3752 LSM6DSR_DEN_DISABLE = 0, 3753 LSM6DSR_LEVEL_FIFO = 6, 3754 LSM6DSR_LEVEL_LETCHED = 3, 3755 LSM6DSR_LEVEL_TRIGGER = 2, 3756 LSM6DSR_EDGE_TRIGGER = 4, 3757 } lsm6dsr_den_mode_t; 3758 int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx, 3759 lsm6dsr_den_mode_t val); 3760 int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx, 3761 lsm6dsr_den_mode_t *val); 3762 3763 typedef enum 3764 { 3765 LSM6DSR_DEN_ACT_LOW = 0, 3766 LSM6DSR_DEN_ACT_HIGH = 1, 3767 } lsm6dsr_den_lh_t; 3768 int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx, 3769 lsm6dsr_den_lh_t val); 3770 int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx, 3771 lsm6dsr_den_lh_t *val); 3772 3773 typedef enum 3774 { 3775 LSM6DSR_STAMP_IN_GY_DATA = 0, 3776 LSM6DSR_STAMP_IN_XL_DATA = 1, 3777 LSM6DSR_STAMP_IN_GY_XL_DATA = 2, 3778 } lsm6dsr_den_xl_g_t; 3779 int32_t lsm6dsr_den_enable_set(stmdev_ctx_t *ctx, 3780 lsm6dsr_den_xl_g_t val); 3781 int32_t lsm6dsr_den_enable_get(stmdev_ctx_t *ctx, 3782 lsm6dsr_den_xl_g_t *val); 3783 3784 int32_t lsm6dsr_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 3785 int32_t lsm6dsr_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); 3786 3787 int32_t lsm6dsr_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 3788 int32_t lsm6dsr_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); 3789 3790 int32_t lsm6dsr_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); 3791 int32_t lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); 3792 3793 int32_t lsm6dsr_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); 3794 int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 3795 3796 typedef enum 3797 { 3798 LSM6DSR_PEDO_BASE = 0x00, 3799 LSM6DSR_PEDO_BASE_FALSE_STEP_REJ = 0x01, 3800 LSM6DSR_PEDO_ADV_FALSE_STEP_REJ = 0x03, 3801 } lsm6dsr_pedo_mode_t; 3802 int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx, 3803 lsm6dsr_pedo_mode_t val); 3804 int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx, 3805 lsm6dsr_pedo_mode_t *val); 3806 3807 int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val); 3808 3809 int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 3810 uint8_t *buff); 3811 int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 3812 uint8_t *buff); 3813 3814 int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, 3815 uint16_t val); 3816 int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx, 3817 uint16_t *val); 3818 3819 int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, 3820 uint8_t val); 3821 int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx, 3822 uint8_t *val); 3823 3824 int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx, 3825 uint8_t val); 3826 int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx, 3827 uint8_t *val); 3828 3829 typedef enum 3830 { 3831 LSM6DSR_EVERY_STEP = 0, 3832 LSM6DSR_COUNT_OVERFLOW = 1, 3833 } lsm6dsr_carry_count_en_t; 3834 int32_t lsm6dsr_pedo_int_mode_set(stmdev_ctx_t *ctx, 3835 lsm6dsr_carry_count_en_t val); 3836 int32_t lsm6dsr_pedo_int_mode_get(stmdev_ctx_t *ctx, 3837 lsm6dsr_carry_count_en_t *val); 3838 3839 int32_t lsm6dsr_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); 3840 int32_t lsm6dsr_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 3841 3842 int32_t lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t *ctx, 3843 uint8_t *val); 3844 3845 int32_t lsm6dsr_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); 3846 int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 3847 3848 int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, 3849 uint8_t *val); 3850 3851 int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val); 3852 int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val); 3853 3854 int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 3855 int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 3856 3857 int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val); 3858 int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val); 3859 3860 typedef enum 3861 { 3862 LSM6DSR_Z_EQ_Y = 0, 3863 LSM6DSR_Z_EQ_MIN_Y = 1, 3864 LSM6DSR_Z_EQ_X = 2, 3865 LSM6DSR_Z_EQ_MIN_X = 3, 3866 LSM6DSR_Z_EQ_MIN_Z = 4, 3867 LSM6DSR_Z_EQ_Z = 5, 3868 } lsm6dsr_mag_z_axis_t; 3869 int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx, 3870 lsm6dsr_mag_z_axis_t val); 3871 int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx, 3872 lsm6dsr_mag_z_axis_t *val); 3873 3874 typedef enum 3875 { 3876 LSM6DSR_Y_EQ_Y = 0, 3877 LSM6DSR_Y_EQ_MIN_Y = 1, 3878 LSM6DSR_Y_EQ_X = 2, 3879 LSM6DSR_Y_EQ_MIN_X = 3, 3880 LSM6DSR_Y_EQ_MIN_Z = 4, 3881 LSM6DSR_Y_EQ_Z = 5, 3882 } lsm6dsr_mag_y_axis_t; 3883 int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx, 3884 lsm6dsr_mag_y_axis_t val); 3885 int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx, 3886 lsm6dsr_mag_y_axis_t *val); 3887 3888 typedef enum 3889 { 3890 LSM6DSR_X_EQ_Y = 0, 3891 LSM6DSR_X_EQ_MIN_Y = 1, 3892 LSM6DSR_X_EQ_X = 2, 3893 LSM6DSR_X_EQ_MIN_X = 3, 3894 LSM6DSR_X_EQ_MIN_Z = 4, 3895 LSM6DSR_X_EQ_Z = 5, 3896 } lsm6dsr_mag_x_axis_t; 3897 int32_t lsm6dsr_mag_x_orient_set(stmdev_ctx_t *ctx, 3898 lsm6dsr_mag_x_axis_t val); 3899 int32_t lsm6dsr_mag_x_orient_get(stmdev_ctx_t *ctx, 3900 lsm6dsr_mag_x_axis_t *val); 3901 3902 int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, 3903 uint8_t *val); 3904 3905 int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); 3906 int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); 3907 3908 typedef struct 3909 { 3910 lsm6dsr_fsm_enable_a_t fsm_enable_a; 3911 lsm6dsr_fsm_enable_b_t fsm_enable_b; 3912 } lsm6dsr_emb_fsm_enable_t; 3913 int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx, 3914 lsm6dsr_emb_fsm_enable_t *val); 3915 int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx, 3916 lsm6dsr_emb_fsm_enable_t *val); 3917 3918 int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 3919 int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 3920 3921 typedef enum 3922 { 3923 LSM6DSR_LC_NORMAL = 0, 3924 LSM6DSR_LC_CLEAR = 1, 3925 LSM6DSR_LC_CLEAR_DONE = 2, 3926 } lsm6dsr_fsm_lc_clr_t; 3927 int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx, 3928 lsm6dsr_fsm_lc_clr_t val); 3929 int32_t lsm6dsr_long_clr_get(stmdev_ctx_t *ctx, 3930 lsm6dsr_fsm_lc_clr_t *val); 3931 3932 typedef struct 3933 { 3934 lsm6dsr_fsm_outs1_t fsm_outs1; 3935 lsm6dsr_fsm_outs2_t fsm_outs2; 3936 lsm6dsr_fsm_outs3_t fsm_outs3; 3937 lsm6dsr_fsm_outs4_t fsm_outs4; 3938 lsm6dsr_fsm_outs5_t fsm_outs5; 3939 lsm6dsr_fsm_outs6_t fsm_outs6; 3940 lsm6dsr_fsm_outs7_t fsm_outs7; 3941 lsm6dsr_fsm_outs8_t fsm_outs8; 3942 lsm6dsr_fsm_outs9_t fsm_outs9; 3943 lsm6dsr_fsm_outs10_t fsm_outs10; 3944 lsm6dsr_fsm_outs11_t fsm_outs11; 3945 lsm6dsr_fsm_outs12_t fsm_outs12; 3946 lsm6dsr_fsm_outs13_t fsm_outs13; 3947 lsm6dsr_fsm_outs14_t fsm_outs14; 3948 lsm6dsr_fsm_outs15_t fsm_outs15; 3949 lsm6dsr_fsm_outs16_t fsm_outs16; 3950 } lsm6dsr_fsm_out_t; 3951 int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, 3952 lsm6dsr_fsm_out_t *val); 3953 3954 typedef enum 3955 { 3956 LSM6DSR_ODR_FSM_12Hz5 = 0, 3957 LSM6DSR_ODR_FSM_26Hz = 1, 3958 LSM6DSR_ODR_FSM_52Hz = 2, 3959 LSM6DSR_ODR_FSM_104Hz = 3, 3960 } lsm6dsr_fsm_odr_t; 3961 int32_t lsm6dsr_fsm_data_rate_set(stmdev_ctx_t *ctx, 3962 lsm6dsr_fsm_odr_t val); 3963 int32_t lsm6dsr_fsm_data_rate_get(stmdev_ctx_t *ctx, 3964 lsm6dsr_fsm_odr_t *val); 3965 3966 int32_t lsm6dsr_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); 3967 int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); 3968 3969 int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx, 3970 uint16_t val); 3971 int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx, 3972 uint16_t *val); 3973 3974 int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx, 3975 uint8_t *buff); 3976 int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx, 3977 uint8_t *buff); 3978 3979 int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, 3980 uint16_t val); 3981 int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx, 3982 uint16_t *val); 3983 3984 typedef struct 3985 { 3986 lsm6dsr_sensor_hub_1_t sh_byte_1; 3987 lsm6dsr_sensor_hub_2_t sh_byte_2; 3988 lsm6dsr_sensor_hub_3_t sh_byte_3; 3989 lsm6dsr_sensor_hub_4_t sh_byte_4; 3990 lsm6dsr_sensor_hub_5_t sh_byte_5; 3991 lsm6dsr_sensor_hub_6_t sh_byte_6; 3992 lsm6dsr_sensor_hub_7_t sh_byte_7; 3993 lsm6dsr_sensor_hub_8_t sh_byte_8; 3994 lsm6dsr_sensor_hub_9_t sh_byte_9; 3995 lsm6dsr_sensor_hub_10_t sh_byte_10; 3996 lsm6dsr_sensor_hub_11_t sh_byte_11; 3997 lsm6dsr_sensor_hub_12_t sh_byte_12; 3998 lsm6dsr_sensor_hub_13_t sh_byte_13; 3999 lsm6dsr_sensor_hub_14_t sh_byte_14; 4000 lsm6dsr_sensor_hub_15_t sh_byte_15; 4001 lsm6dsr_sensor_hub_16_t sh_byte_16; 4002 lsm6dsr_sensor_hub_17_t sh_byte_17; 4003 lsm6dsr_sensor_hub_18_t sh_byte_18; 4004 } lsm6dsr_emb_sh_read_t; 4005 int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx, 4006 lsm6dsr_emb_sh_read_t *val); 4007 4008 typedef enum 4009 { 4010 LSM6DSR_SLV_0 = 0, 4011 LSM6DSR_SLV_0_1 = 1, 4012 LSM6DSR_SLV_0_1_2 = 2, 4013 LSM6DSR_SLV_0_1_2_3 = 3, 4014 } lsm6dsr_aux_sens_on_t; 4015 int32_t lsm6dsr_sh_slave_connected_set(stmdev_ctx_t *ctx, 4016 lsm6dsr_aux_sens_on_t val); 4017 int32_t lsm6dsr_sh_slave_connected_get(stmdev_ctx_t *ctx, 4018 lsm6dsr_aux_sens_on_t *val); 4019 4020 int32_t lsm6dsr_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 4021 int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 4022 4023 typedef enum 4024 { 4025 LSM6DSR_EXT_PULL_UP = 0, 4026 LSM6DSR_INTERNAL_PULL_UP = 1, 4027 } lsm6dsr_shub_pu_en_t; 4028 int32_t lsm6dsr_sh_pin_mode_set(stmdev_ctx_t *ctx, 4029 lsm6dsr_shub_pu_en_t val); 4030 int32_t lsm6dsr_sh_pin_mode_get(stmdev_ctx_t *ctx, 4031 lsm6dsr_shub_pu_en_t *val); 4032 4033 int32_t lsm6dsr_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 4034 int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 4035 4036 typedef enum 4037 { 4038 LSM6DSR_EXT_ON_INT2_PIN = 1, 4039 LSM6DSR_XL_GY_DRDY = 0, 4040 } lsm6dsr_start_config_t; 4041 int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx, 4042 lsm6dsr_start_config_t val); 4043 int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx, 4044 lsm6dsr_start_config_t *val); 4045 4046 typedef enum 4047 { 4048 LSM6DSR_EACH_SH_CYCLE = 0, 4049 LSM6DSR_ONLY_FIRST_CYCLE = 1, 4050 } lsm6dsr_write_once_t; 4051 int32_t lsm6dsr_sh_write_mode_set(stmdev_ctx_t *ctx, 4052 lsm6dsr_write_once_t val); 4053 int32_t lsm6dsr_sh_write_mode_get(stmdev_ctx_t *ctx, 4054 lsm6dsr_write_once_t *val); 4055 4056 int32_t lsm6dsr_sh_reset_set(stmdev_ctx_t *ctx); 4057 int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 4058 4059 typedef enum 4060 { 4061 LSM6DSR_SH_ODR_104Hz = 0, 4062 LSM6DSR_SH_ODR_52Hz = 1, 4063 LSM6DSR_SH_ODR_26Hz = 2, 4064 LSM6DSR_SH_ODR_13Hz = 3, 4065 } lsm6dsr_shub_odr_t; 4066 int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx, 4067 lsm6dsr_shub_odr_t val); 4068 int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx, 4069 lsm6dsr_shub_odr_t *val); 4070 4071 typedef struct 4072 { 4073 uint8_t slv0_add; 4074 uint8_t slv0_subadd; 4075 uint8_t slv0_data; 4076 } lsm6dsr_sh_cfg_write_t; 4077 int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx, 4078 lsm6dsr_sh_cfg_write_t *val); 4079 4080 typedef struct 4081 { 4082 uint8_t slv_add; 4083 uint8_t slv_subadd; 4084 uint8_t slv_len; 4085 } lsm6dsr_sh_cfg_read_t; 4086 int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 4087 lsm6dsr_sh_cfg_read_t *val); 4088 int32_t lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 4089 lsm6dsr_sh_cfg_read_t *val); 4090 int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 4091 lsm6dsr_sh_cfg_read_t *val); 4092 int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 4093 lsm6dsr_sh_cfg_read_t *val); 4094 4095 int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx, 4096 lsm6dsr_status_master_t *val); 4097 4098 typedef enum 4099 { 4100 LSM6DSR_S4S_TPH_7bit = 0, 4101 LSM6DSR_S4S_TPH_15bit = 1, 4102 } lsm6dsr_s4s_tph_res_t; 4103 int32_t lsm6dsr_s4s_tph_res_set(stmdev_ctx_t *ctx, 4104 lsm6dsr_s4s_tph_res_t val); 4105 int32_t lsm6dsr_s4s_tph_res_get(stmdev_ctx_t *ctx, 4106 lsm6dsr_s4s_tph_res_t *val); 4107 4108 int32_t lsm6dsr_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val); 4109 int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val); 4110 4111 typedef enum 4112 { 4113 LSM6DSR_S4S_DT_RES_11 = 0, 4114 LSM6DSR_S4S_DT_RES_12 = 1, 4115 LSM6DSR_S4S_DT_RES_13 = 2, 4116 LSM6DSR_S4S_DT_RES_14 = 3, 4117 } lsm6dsr_s4s_res_ratio_t; 4118 int32_t lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t *ctx, 4119 lsm6dsr_s4s_res_ratio_t val); 4120 int32_t lsm6dsr_s4s_res_ratio_get(stmdev_ctx_t *ctx, 4121 lsm6dsr_s4s_res_ratio_t *val); 4122 4123 int32_t lsm6dsr_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val); 4124 int32_t lsm6dsr_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val); 4125 4126 int32_t lsm6dsr_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val); 4127 int32_t lsm6dsr_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val); 4128 4129 /** 4130 *@} 4131 * 4132 */ 4133 4134 #ifdef __cplusplus 4135 } 4136 #endif 4137 4138 #endif /* LSM6DSR_REGS_H */ 4139 4140 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4141
