1 /** 2 ****************************************************************************** 3 * @file lsm6dsox_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsox_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSOX_REGS_H 23 #define LSM6DSOX_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSOX 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSOX_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSOX_I2C_ADD_L 0xD5U 173 #define LSM6DSOX_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSOX_ID 0x6CU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSOX_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t ois_ctrl_from_ui : 1; 188 uint8_t not_used_01 : 5; 189 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 192 uint8_t not_used_01 : 5; 193 uint8_t ois_ctrl_from_ui : 1; 194 #endif /* DRV_BYTE_ORDER */ 195 } lsm6dsox_func_cfg_access_t; 196 197 #define LSM6DSOX_PIN_CTRL 0x02U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t not_used_01 : 6; 202 uint8_t sdo_pu_en : 1; 203 uint8_t ois_pu_dis : 1; 204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 205 uint8_t ois_pu_dis : 1; 206 uint8_t sdo_pu_en : 1; 207 uint8_t not_used_01 : 6; 208 #endif /* DRV_BYTE_ORDER */ 209 } lsm6dsox_pin_ctrl_t; 210 211 #define LSM6DSOX_S4S_TPH_L 0x04U 212 typedef struct 213 { 214 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 215 uint8_t tph_l : 7; 216 uint8_t tph_h_sel : 1; 217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 218 uint8_t tph_h_sel : 1; 219 uint8_t tph_l : 7; 220 #endif /* DRV_BYTE_ORDER */ 221 } lsm6dsox_s4s_tph_l_t; 222 223 #define LSM6DSOX_S4S_TPH_H 0x05U 224 typedef struct 225 { 226 uint8_t tph_h : 8; 227 } lsm6dsox_s4s_tph_h_t; 228 229 #define LSM6DSOX_S4S_RR 0x06U 230 typedef struct 231 { 232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 233 uint8_t rr : 2; 234 uint8_t not_used_01 : 6; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t not_used_01 : 6; 237 uint8_t rr : 2; 238 #endif /* DRV_BYTE_ORDER */ 239 } lsm6dsox_s4s_rr_t; 240 241 #define LSM6DSOX_FIFO_CTRL1 0x07U 242 typedef struct 243 { 244 uint8_t wtm : 8; 245 } lsm6dsox_fifo_ctrl1_t; 246 247 #define LSM6DSOX_FIFO_CTRL2 0x08U 248 typedef struct 249 { 250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 251 uint8_t wtm : 1; 252 uint8_t uncoptr_rate : 2; 253 uint8_t not_used_01 : 1; 254 uint8_t odrchg_en : 1; 255 uint8_t not_used_02 : 1; 256 uint8_t fifo_compr_rt_en : 1; 257 uint8_t stop_on_wtm : 1; 258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 259 uint8_t stop_on_wtm : 1; 260 uint8_t fifo_compr_rt_en : 1; 261 uint8_t not_used_02 : 1; 262 uint8_t odrchg_en : 1; 263 uint8_t not_used_01 : 1; 264 uint8_t uncoptr_rate : 2; 265 uint8_t wtm : 1; 266 #endif /* DRV_BYTE_ORDER */ 267 } lsm6dsox_fifo_ctrl2_t; 268 269 #define LSM6DSOX_FIFO_CTRL3 0x09U 270 typedef struct 271 { 272 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 273 uint8_t bdr_xl : 4; 274 uint8_t bdr_gy : 4; 275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 276 uint8_t bdr_gy : 4; 277 uint8_t bdr_xl : 4; 278 #endif /* DRV_BYTE_ORDER */ 279 } lsm6dsox_fifo_ctrl3_t; 280 281 #define LSM6DSOX_FIFO_CTRL4 0x0AU 282 typedef struct 283 { 284 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 285 uint8_t fifo_mode : 3; 286 uint8_t not_used_01 : 1; 287 uint8_t odr_t_batch : 2; 288 uint8_t odr_ts_batch : 2; 289 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 290 uint8_t odr_ts_batch : 2; 291 uint8_t odr_t_batch : 2; 292 uint8_t not_used_01 : 1; 293 uint8_t fifo_mode : 3; 294 #endif /* DRV_BYTE_ORDER */ 295 } lsm6dsox_fifo_ctrl4_t; 296 297 #define LSM6DSOX_COUNTER_BDR_REG1 0x0BU 298 typedef struct 299 { 300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 301 uint8_t cnt_bdr_th : 3; 302 uint8_t not_used_01 : 2; 303 uint8_t trig_counter_bdr : 1; 304 uint8_t rst_counter_bdr : 1; 305 uint8_t dataready_pulsed : 1; 306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 307 uint8_t dataready_pulsed : 1; 308 uint8_t rst_counter_bdr : 1; 309 uint8_t trig_counter_bdr : 1; 310 uint8_t not_used_01 : 2; 311 uint8_t cnt_bdr_th : 3; 312 #endif /* DRV_BYTE_ORDER */ 313 } lsm6dsox_counter_bdr_reg1_t; 314 315 #define LSM6DSOX_COUNTER_BDR_REG2 0x0CU 316 typedef struct 317 { 318 uint8_t cnt_bdr_th : 8; 319 } lsm6dsox_counter_bdr_reg2_t; 320 321 #define LSM6DSOX_INT1_CTRL 0x0D 322 typedef struct 323 { 324 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 325 uint8_t int1_drdy_xl : 1; 326 uint8_t int1_drdy_g : 1; 327 uint8_t int1_boot : 1; 328 uint8_t int1_fifo_th : 1; 329 uint8_t int1_fifo_ovr : 1; 330 uint8_t int1_fifo_full : 1; 331 uint8_t int1_cnt_bdr : 1; 332 uint8_t den_drdy_flag : 1; 333 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 334 uint8_t den_drdy_flag : 1; 335 uint8_t int1_cnt_bdr : 1; 336 uint8_t int1_fifo_full : 1; 337 uint8_t int1_fifo_ovr : 1; 338 uint8_t int1_fifo_th : 1; 339 uint8_t int1_boot : 1; 340 uint8_t int1_drdy_g : 1; 341 uint8_t int1_drdy_xl : 1; 342 #endif /* DRV_BYTE_ORDER */ 343 } lsm6dsox_int1_ctrl_t; 344 345 #define LSM6DSOX_INT2_CTRL 0x0EU 346 typedef struct 347 { 348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 349 uint8_t int2_drdy_xl : 1; 350 uint8_t int2_drdy_g : 1; 351 uint8_t int2_drdy_temp : 1; 352 uint8_t int2_fifo_th : 1; 353 uint8_t int2_fifo_ovr : 1; 354 uint8_t int2_fifo_full : 1; 355 uint8_t int2_cnt_bdr : 1; 356 uint8_t not_used_01 : 1; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t not_used_01 : 1; 359 uint8_t int2_cnt_bdr : 1; 360 uint8_t int2_fifo_full : 1; 361 uint8_t int2_fifo_ovr : 1; 362 uint8_t int2_fifo_th : 1; 363 uint8_t int2_drdy_temp : 1; 364 uint8_t int2_drdy_g : 1; 365 uint8_t int2_drdy_xl : 1; 366 #endif /* DRV_BYTE_ORDER */ 367 } lsm6dsox_int2_ctrl_t; 368 369 #define LSM6DSOX_WHO_AM_I 0x0FU 370 #define LSM6DSOX_CTRL1_XL 0x10U 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t not_used_01 : 1; 375 uint8_t lpf2_xl_en : 1; 376 uint8_t fs_xl : 2; 377 uint8_t odr_xl : 4; 378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 379 uint8_t odr_xl : 4; 380 uint8_t fs_xl : 2; 381 uint8_t lpf2_xl_en : 1; 382 uint8_t not_used_01 : 1; 383 #endif /* DRV_BYTE_ORDER */ 384 } lsm6dsox_ctrl1_xl_t; 385 386 #define LSM6DSOX_CTRL2_G 0x11U 387 typedef struct 388 { 389 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 390 uint8_t not_used_01 : 1; 391 uint8_t fs_g : 3; /* fs_125 + fs_g */ 392 uint8_t odr_g : 4; 393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 394 uint8_t odr_g : 4; 395 uint8_t fs_g : 3; /* fs_125 + fs_g */ 396 uint8_t not_used_01 : 1; 397 #endif /* DRV_BYTE_ORDER */ 398 } lsm6dsox_ctrl2_g_t; 399 400 #define LSM6DSOX_CTRL3_C 0x12U 401 typedef struct 402 { 403 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 404 uint8_t sw_reset : 1; 405 uint8_t not_used_01 : 1; 406 uint8_t if_inc : 1; 407 uint8_t sim : 1; 408 uint8_t pp_od : 1; 409 uint8_t h_lactive : 1; 410 uint8_t bdu : 1; 411 uint8_t boot : 1; 412 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 413 uint8_t boot : 1; 414 uint8_t bdu : 1; 415 uint8_t h_lactive : 1; 416 uint8_t pp_od : 1; 417 uint8_t sim : 1; 418 uint8_t if_inc : 1; 419 uint8_t not_used_01 : 1; 420 uint8_t sw_reset : 1; 421 #endif /* DRV_BYTE_ORDER */ 422 } lsm6dsox_ctrl3_c_t; 423 424 #define LSM6DSOX_CTRL4_C 0x13U 425 typedef struct 426 { 427 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 428 uint8_t not_used_01 : 1; 429 uint8_t lpf1_sel_g : 1; 430 uint8_t i2c_disable : 1; 431 uint8_t drdy_mask : 1; 432 uint8_t not_used_02 : 1; 433 uint8_t int2_on_int1 : 1; 434 uint8_t sleep_g : 1; 435 uint8_t not_used_03 : 1; 436 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 437 uint8_t not_used_03 : 1; 438 uint8_t sleep_g : 1; 439 uint8_t int2_on_int1 : 1; 440 uint8_t not_used_02 : 1; 441 uint8_t drdy_mask : 1; 442 uint8_t i2c_disable : 1; 443 uint8_t lpf1_sel_g : 1; 444 uint8_t not_used_01 : 1; 445 #endif /* DRV_BYTE_ORDER */ 446 } lsm6dsox_ctrl4_c_t; 447 448 #define LSM6DSOX_CTRL5_C 0x14U 449 typedef struct 450 { 451 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 452 uint8_t st_xl : 2; 453 uint8_t st_g : 2; 454 uint8_t rounding_status : 1; 455 uint8_t rounding : 2; 456 uint8_t xl_ulp_en : 1; 457 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 458 uint8_t xl_ulp_en : 1; 459 uint8_t rounding : 2; 460 uint8_t rounding_status : 1; 461 uint8_t st_g : 2; 462 uint8_t st_xl : 2; 463 #endif /* DRV_BYTE_ORDER */ 464 } lsm6dsox_ctrl5_c_t; 465 466 #define LSM6DSOX_CTRL6_C 0x15U 467 typedef struct 468 { 469 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 470 uint8_t ftype : 3; 471 uint8_t usr_off_w : 1; 472 uint8_t xl_hm_mode : 1; 473 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 474 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 475 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 476 uint8_t xl_hm_mode : 1; 477 uint8_t usr_off_w : 1; 478 uint8_t ftype : 3; 479 #endif /* DRV_BYTE_ORDER */ 480 } lsm6dsox_ctrl6_c_t; 481 482 #define LSM6DSOX_CTRL7_G 0x16U 483 typedef struct 484 { 485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 486 uint8_t ois_on : 1; 487 uint8_t usr_off_on_out : 1; 488 uint8_t ois_on_en : 1; 489 uint8_t not_used_01 : 1; 490 uint8_t hpm_g : 2; 491 uint8_t hp_en_g : 1; 492 uint8_t g_hm_mode : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t g_hm_mode : 1; 495 uint8_t hp_en_g : 1; 496 uint8_t hpm_g : 2; 497 uint8_t not_used_01 : 1; 498 uint8_t ois_on_en : 1; 499 uint8_t usr_off_on_out : 1; 500 uint8_t ois_on : 1; 501 #endif /* DRV_BYTE_ORDER */ 502 } lsm6dsox_ctrl7_g_t; 503 504 #define LSM6DSOX_CTRL8_XL 0x17U 505 typedef struct 506 { 507 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 508 uint8_t low_pass_on_6d : 1; 509 uint8_t xl_fs_mode : 1; 510 uint8_t hp_slope_xl_en : 1; 511 uint8_t fastsettl_mode_xl : 1; 512 uint8_t hp_ref_mode_xl : 1; 513 uint8_t hpcf_xl : 3; 514 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 515 uint8_t hpcf_xl : 3; 516 uint8_t hp_ref_mode_xl : 1; 517 uint8_t fastsettl_mode_xl : 1; 518 uint8_t hp_slope_xl_en : 1; 519 uint8_t xl_fs_mode : 1; 520 uint8_t low_pass_on_6d : 1; 521 #endif /* DRV_BYTE_ORDER */ 522 } lsm6dsox_ctrl8_xl_t; 523 524 #define LSM6DSOX_CTRL9_XL 0x18U 525 typedef struct 526 { 527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 528 uint8_t not_used_01 : 1; 529 uint8_t i3c_disable : 1; 530 uint8_t den_lh : 1; 531 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 532 uint8_t den_z : 1; 533 uint8_t den_y : 1; 534 uint8_t den_x : 1; 535 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 536 uint8_t den_x : 1; 537 uint8_t den_y : 1; 538 uint8_t den_z : 1; 539 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 540 uint8_t den_lh : 1; 541 uint8_t i3c_disable : 1; 542 uint8_t not_used_01 : 1; 543 #endif /* DRV_BYTE_ORDER */ 544 } lsm6dsox_ctrl9_xl_t; 545 546 #define LSM6DSOX_CTRL10_C 0x19U 547 typedef struct 548 { 549 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 550 uint8_t not_used_01 : 5; 551 uint8_t timestamp_en : 1; 552 uint8_t not_used_02 : 2; 553 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 554 uint8_t not_used_02 : 2; 555 uint8_t timestamp_en : 1; 556 uint8_t not_used_01 : 5; 557 #endif /* DRV_BYTE_ORDER */ 558 } lsm6dsox_ctrl10_c_t; 559 560 #define LSM6DSOX_ALL_INT_SRC 0x1AU 561 typedef struct 562 { 563 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 564 uint8_t ff_ia : 1; 565 uint8_t wu_ia : 1; 566 uint8_t single_tap : 1; 567 uint8_t double_tap : 1; 568 uint8_t d6d_ia : 1; 569 uint8_t sleep_change_ia : 1; 570 uint8_t not_used_01 : 1; 571 uint8_t timestamp_endcount : 1; 572 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 573 uint8_t timestamp_endcount : 1; 574 uint8_t not_used_01 : 1; 575 uint8_t sleep_change_ia : 1; 576 uint8_t d6d_ia : 1; 577 uint8_t double_tap : 1; 578 uint8_t single_tap : 1; 579 uint8_t wu_ia : 1; 580 uint8_t ff_ia : 1; 581 #endif /* DRV_BYTE_ORDER */ 582 } lsm6dsox_all_int_src_t; 583 584 #define LSM6DSOX_WAKE_UP_SRC 0x1BU 585 typedef struct 586 { 587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 588 uint8_t z_wu : 1; 589 uint8_t y_wu : 1; 590 uint8_t x_wu : 1; 591 uint8_t wu_ia : 1; 592 uint8_t sleep_state : 1; 593 uint8_t ff_ia : 1; 594 uint8_t sleep_change_ia : 2; 595 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 596 uint8_t sleep_change_ia : 2; 597 uint8_t ff_ia : 1; 598 uint8_t sleep_state : 1; 599 uint8_t wu_ia : 1; 600 uint8_t x_wu : 1; 601 uint8_t y_wu : 1; 602 uint8_t z_wu : 1; 603 #endif /* DRV_BYTE_ORDER */ 604 } lsm6dsox_wake_up_src_t; 605 606 #define LSM6DSOX_TAP_SRC 0x1CU 607 typedef struct 608 { 609 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 610 uint8_t z_tap : 1; 611 uint8_t y_tap : 1; 612 uint8_t x_tap : 1; 613 uint8_t tap_sign : 1; 614 uint8_t double_tap : 1; 615 uint8_t single_tap : 1; 616 uint8_t tap_ia : 1; 617 uint8_t not_used_02 : 1; 618 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 619 uint8_t not_used_02 : 1; 620 uint8_t tap_ia : 1; 621 uint8_t single_tap : 1; 622 uint8_t double_tap : 1; 623 uint8_t tap_sign : 1; 624 uint8_t x_tap : 1; 625 uint8_t y_tap : 1; 626 uint8_t z_tap : 1; 627 #endif /* DRV_BYTE_ORDER */ 628 } lsm6dsox_tap_src_t; 629 630 #define LSM6DSOX_D6D_SRC 0x1DU 631 typedef struct 632 { 633 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 634 uint8_t xl : 1; 635 uint8_t xh : 1; 636 uint8_t yl : 1; 637 uint8_t yh : 1; 638 uint8_t zl : 1; 639 uint8_t zh : 1; 640 uint8_t d6d_ia : 1; 641 uint8_t den_drdy : 1; 642 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 643 uint8_t den_drdy : 1; 644 uint8_t d6d_ia : 1; 645 uint8_t zh : 1; 646 uint8_t zl : 1; 647 uint8_t yh : 1; 648 uint8_t yl : 1; 649 uint8_t xh : 1; 650 uint8_t xl : 1; 651 #endif /* DRV_BYTE_ORDER */ 652 } lsm6dsox_d6d_src_t; 653 654 #define LSM6DSOX_STATUS_REG 0x1EU 655 typedef struct 656 { 657 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 658 uint8_t xlda : 1; 659 uint8_t gda : 1; 660 uint8_t tda : 1; 661 uint8_t not_used_01 : 5; 662 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 663 uint8_t not_used_01 : 5; 664 uint8_t tda : 1; 665 uint8_t gda : 1; 666 uint8_t xlda : 1; 667 #endif /* DRV_BYTE_ORDER */ 668 } lsm6dsox_status_reg_t; 669 670 #define LSM6DSOX_OUT_TEMP_L 0x20U 671 #define LSM6DSOX_OUT_TEMP_H 0x21U 672 #define LSM6DSOX_OUTX_L_G 0x22U 673 #define LSM6DSOX_OUTX_H_G 0x23U 674 #define LSM6DSOX_OUTY_L_G 0x24U 675 #define LSM6DSOX_OUTY_H_G 0x25U 676 #define LSM6DSOX_OUTZ_L_G 0x26U 677 #define LSM6DSOX_OUTZ_H_G 0x27U 678 #define LSM6DSOX_OUTX_L_A 0x28U 679 #define LSM6DSOX_OUTX_H_A 0x29U 680 #define LSM6DSOX_OUTY_L_A 0x2AU 681 #define LSM6DSOX_OUTY_H_A 0x2BU 682 #define LSM6DSOX_OUTZ_L_A 0x2CU 683 #define LSM6DSOX_OUTZ_H_A 0x2DU 684 #define LSM6DSOX_EMB_FUNC_STATUS_MAINPAGE 0x35U 685 typedef struct 686 { 687 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 688 uint8_t not_used_01 : 3; 689 uint8_t is_step_det : 1; 690 uint8_t is_tilt : 1; 691 uint8_t is_sigmot : 1; 692 uint8_t not_used_02 : 1; 693 uint8_t is_fsm_lc : 1; 694 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 695 uint8_t is_fsm_lc : 1; 696 uint8_t not_used_02 : 1; 697 uint8_t is_sigmot : 1; 698 uint8_t is_tilt : 1; 699 uint8_t is_step_det : 1; 700 uint8_t not_used_01 : 3; 701 #endif /* DRV_BYTE_ORDER */ 702 } lsm6dsox_emb_func_status_mainpage_t; 703 704 #define LSM6DSOX_FSM_STATUS_A_MAINPAGE 0x36U 705 typedef struct 706 { 707 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 708 uint8_t is_fsm1 : 1; 709 uint8_t is_fsm2 : 1; 710 uint8_t is_fsm3 : 1; 711 uint8_t is_fsm4 : 1; 712 uint8_t is_fsm5 : 1; 713 uint8_t is_fsm6 : 1; 714 uint8_t is_fsm7 : 1; 715 uint8_t is_fsm8 : 1; 716 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 717 uint8_t is_fsm8 : 1; 718 uint8_t is_fsm7 : 1; 719 uint8_t is_fsm6 : 1; 720 uint8_t is_fsm5 : 1; 721 uint8_t is_fsm4 : 1; 722 uint8_t is_fsm3 : 1; 723 uint8_t is_fsm2 : 1; 724 uint8_t is_fsm1 : 1; 725 #endif /* DRV_BYTE_ORDER */ 726 } lsm6dsox_fsm_status_a_mainpage_t; 727 728 #define LSM6DSOX_FSM_STATUS_B_MAINPAGE 0x37U 729 typedef struct 730 { 731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 732 uint8_t is_fsm9 : 1; 733 uint8_t is_fsm10 : 1; 734 uint8_t is_fsm11 : 1; 735 uint8_t is_fsm12 : 1; 736 uint8_t is_fsm13 : 1; 737 uint8_t is_fsm14 : 1; 738 uint8_t is_fsm15 : 1; 739 uint8_t is_fsm16 : 1; 740 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 741 uint8_t is_fsm16 : 1; 742 uint8_t is_fsm15 : 1; 743 uint8_t is_fsm14 : 1; 744 uint8_t is_fsm13 : 1; 745 uint8_t is_fsm12 : 1; 746 uint8_t is_fsm11 : 1; 747 uint8_t is_fsm10 : 1; 748 uint8_t is_fsm9 : 1; 749 #endif /* DRV_BYTE_ORDER */ 750 } lsm6dsox_fsm_status_b_mainpage_t; 751 752 #define LSM6DSOX_MLC_STATUS_MAINPAGE 0x38U 753 typedef struct 754 { 755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 756 uint8_t is_mlc1 : 1; 757 uint8_t is_mlc2 : 1; 758 uint8_t is_mlc3 : 1; 759 uint8_t is_mlc4 : 1; 760 uint8_t is_mlc5 : 1; 761 uint8_t is_mlc6 : 1; 762 uint8_t is_mlc7 : 1; 763 uint8_t is_mlc8 : 1; 764 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 765 uint8_t is_mlc8 : 1; 766 uint8_t is_mlc7 : 1; 767 uint8_t is_mlc6 : 1; 768 uint8_t is_mlc5 : 1; 769 uint8_t is_mlc4 : 1; 770 uint8_t is_mlc3 : 1; 771 uint8_t is_mlc2 : 1; 772 uint8_t is_mlc1 : 1; 773 #endif /* DRV_BYTE_ORDER */ 774 } lsm6dsox_mlc_status_mainpage_t; 775 776 #define LSM6DSOX_STATUS_MASTER_MAINPAGE 0x39U 777 typedef struct 778 { 779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 780 uint8_t sens_hub_endop : 1; 781 uint8_t not_used_01 : 2; 782 uint8_t slave0_nack : 1; 783 uint8_t slave1_nack : 1; 784 uint8_t slave2_nack : 1; 785 uint8_t slave3_nack : 1; 786 uint8_t wr_once_done : 1; 787 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 788 uint8_t wr_once_done : 1; 789 uint8_t slave3_nack : 1; 790 uint8_t slave2_nack : 1; 791 uint8_t slave1_nack : 1; 792 uint8_t slave0_nack : 1; 793 uint8_t not_used_01 : 2; 794 uint8_t sens_hub_endop : 1; 795 #endif /* DRV_BYTE_ORDER */ 796 } lsm6dsox_status_master_mainpage_t; 797 798 #define LSM6DSOX_FIFO_STATUS1 0x3AU 799 typedef struct 800 { 801 uint8_t diff_fifo : 8; 802 } lsm6dsox_fifo_status1_t; 803 804 #define LSM6DSOX_FIFO_STATUS2 0x3B 805 typedef struct 806 { 807 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 808 uint8_t diff_fifo : 2; 809 uint8_t not_used_01 : 1; 810 uint8_t over_run_latched : 1; 811 uint8_t counter_bdr_ia : 1; 812 uint8_t fifo_full_ia : 1; 813 uint8_t fifo_ovr_ia : 1; 814 uint8_t fifo_wtm_ia : 1; 815 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 816 uint8_t fifo_wtm_ia : 1; 817 uint8_t fifo_ovr_ia : 1; 818 uint8_t fifo_full_ia : 1; 819 uint8_t counter_bdr_ia : 1; 820 uint8_t over_run_latched : 1; 821 uint8_t not_used_01 : 1; 822 uint8_t diff_fifo : 2; 823 #endif /* DRV_BYTE_ORDER */ 824 } lsm6dsox_fifo_status2_t; 825 826 #define LSM6DSOX_TIMESTAMP0 0x40U 827 #define LSM6DSOX_TIMESTAMP1 0x41U 828 #define LSM6DSOX_TIMESTAMP2 0x42U 829 #define LSM6DSOX_TIMESTAMP3 0x43U 830 #define LSM6DSOX_UI_STATUS_REG_OIS 0x49U 831 typedef struct 832 { 833 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 834 uint8_t xlda : 1; 835 uint8_t gda : 1; 836 uint8_t gyro_settling : 1; 837 uint8_t not_used_01 : 5; 838 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 839 uint8_t not_used_01 : 5; 840 uint8_t gyro_settling : 1; 841 uint8_t gda : 1; 842 uint8_t xlda : 1; 843 #endif /* DRV_BYTE_ORDER */ 844 } lsm6dsox_ui_status_reg_ois_t; 845 846 #define LSM6DSOX_UI_OUTX_L_G_OIS 0x4AU 847 #define LSM6DSOX_UI_OUTX_H_G_OIS 0x4BU 848 #define LSM6DSOX_UI_OUTY_L_G_OIS 0x4CU 849 #define LSM6DSOX_UI_OUTY_H_G_OIS 0x4DU 850 #define LSM6DSOX_UI_OUTZ_L_G_OIS 0x4EU 851 #define LSM6DSOX_UI_OUTZ_H_G_OIS 0x4FU 852 #define LSM6DSOX_UI_OUTX_L_A_OIS 0x50U 853 #define LSM6DSOX_UI_OUTX_H_A_OIS 0x51U 854 #define LSM6DSOX_UI_OUTY_L_A_OIS 0x52U 855 #define LSM6DSOX_UI_OUTY_H_A_OIS 0x53U 856 #define LSM6DSOX_UI_OUTZ_L_A_OIS 0x54U 857 #define LSM6DSOX_UI_OUTZ_H_A_OIS 0x55U 858 859 #define LSM6DSOX_TAP_CFG0 0x56U 860 typedef struct 861 { 862 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 863 uint8_t lir : 1; 864 uint8_t tap_z_en : 1; 865 uint8_t tap_y_en : 1; 866 uint8_t tap_x_en : 1; 867 uint8_t slope_fds : 1; 868 uint8_t sleep_status_on_int : 1; 869 uint8_t int_clr_on_read : 1; 870 uint8_t not_used_01 : 1; 871 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 872 uint8_t not_used_01 : 1; 873 uint8_t int_clr_on_read : 1; 874 uint8_t sleep_status_on_int : 1; 875 uint8_t slope_fds : 1; 876 uint8_t tap_x_en : 1; 877 uint8_t tap_y_en : 1; 878 uint8_t tap_z_en : 1; 879 uint8_t lir : 1; 880 #endif /* DRV_BYTE_ORDER */ 881 } lsm6dsox_tap_cfg0_t; 882 883 #define LSM6DSOX_TAP_CFG1 0x57U 884 typedef struct 885 { 886 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 887 uint8_t tap_ths_x : 5; 888 uint8_t tap_priority : 3; 889 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 890 uint8_t tap_priority : 3; 891 uint8_t tap_ths_x : 5; 892 #endif /* DRV_BYTE_ORDER */ 893 } lsm6dsox_tap_cfg1_t; 894 895 #define LSM6DSOX_TAP_CFG2 0x58U 896 typedef struct 897 { 898 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 899 uint8_t tap_ths_y : 5; 900 uint8_t inact_en : 2; 901 uint8_t interrupts_enable : 1; 902 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 903 uint8_t interrupts_enable : 1; 904 uint8_t inact_en : 2; 905 uint8_t tap_ths_y : 5; 906 #endif /* DRV_BYTE_ORDER */ 907 } lsm6dsox_tap_cfg2_t; 908 909 #define LSM6DSOX_TAP_THS_6D 0x59U 910 typedef struct 911 { 912 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 913 uint8_t tap_ths_z : 5; 914 uint8_t sixd_ths : 2; 915 uint8_t d4d_en : 1; 916 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 917 uint8_t d4d_en : 1; 918 uint8_t sixd_ths : 2; 919 uint8_t tap_ths_z : 5; 920 #endif /* DRV_BYTE_ORDER */ 921 } lsm6dsox_tap_ths_6d_t; 922 923 #define LSM6DSOX_INT_DUR2 0x5AU 924 typedef struct 925 { 926 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 927 uint8_t shock : 2; 928 uint8_t quiet : 2; 929 uint8_t dur : 4; 930 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 931 uint8_t dur : 4; 932 uint8_t quiet : 2; 933 uint8_t shock : 2; 934 #endif /* DRV_BYTE_ORDER */ 935 } lsm6dsox_int_dur2_t; 936 937 #define LSM6DSOX_WAKE_UP_THS 0x5BU 938 typedef struct 939 { 940 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 941 uint8_t wk_ths : 6; 942 uint8_t usr_off_on_wu : 1; 943 uint8_t single_double_tap : 1; 944 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 945 uint8_t single_double_tap : 1; 946 uint8_t usr_off_on_wu : 1; 947 uint8_t wk_ths : 6; 948 #endif /* DRV_BYTE_ORDER */ 949 } lsm6dsox_wake_up_ths_t; 950 951 #define LSM6DSOX_WAKE_UP_DUR 0x5CU 952 typedef struct 953 { 954 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 955 uint8_t sleep_dur : 4; 956 uint8_t wake_ths_w : 1; 957 uint8_t wake_dur : 2; 958 uint8_t ff_dur : 1; 959 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 960 uint8_t ff_dur : 1; 961 uint8_t wake_dur : 2; 962 uint8_t wake_ths_w : 1; 963 uint8_t sleep_dur : 4; 964 #endif /* DRV_BYTE_ORDER */ 965 } lsm6dsox_wake_up_dur_t; 966 967 #define LSM6DSOX_FREE_FALL 0x5DU 968 typedef struct 969 { 970 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 971 uint8_t ff_ths : 3; 972 uint8_t ff_dur : 5; 973 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 974 uint8_t ff_dur : 5; 975 uint8_t ff_ths : 3; 976 #endif /* DRV_BYTE_ORDER */ 977 } lsm6dsox_free_fall_t; 978 979 #define LSM6DSOX_MD1_CFG 0x5EU 980 typedef struct 981 { 982 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 983 uint8_t int1_shub : 1; 984 uint8_t int1_emb_func : 1; 985 uint8_t int1_6d : 1; 986 uint8_t int1_double_tap : 1; 987 uint8_t int1_ff : 1; 988 uint8_t int1_wu : 1; 989 uint8_t int1_single_tap : 1; 990 uint8_t int1_sleep_change : 1; 991 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 992 uint8_t int1_sleep_change : 1; 993 uint8_t int1_single_tap : 1; 994 uint8_t int1_wu : 1; 995 uint8_t int1_ff : 1; 996 uint8_t int1_double_tap : 1; 997 uint8_t int1_6d : 1; 998 uint8_t int1_emb_func : 1; 999 uint8_t int1_shub : 1; 1000 #endif /* DRV_BYTE_ORDER */ 1001 } lsm6dsox_md1_cfg_t; 1002 1003 #define LSM6DSOX_MD2_CFG 0x5FU 1004 typedef struct 1005 { 1006 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1007 uint8_t int2_timestamp : 1; 1008 uint8_t int2_emb_func : 1; 1009 uint8_t int2_6d : 1; 1010 uint8_t int2_double_tap : 1; 1011 uint8_t int2_ff : 1; 1012 uint8_t int2_wu : 1; 1013 uint8_t int2_single_tap : 1; 1014 uint8_t int2_sleep_change : 1; 1015 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1016 uint8_t int2_sleep_change : 1; 1017 uint8_t int2_single_tap : 1; 1018 uint8_t int2_wu : 1; 1019 uint8_t int2_ff : 1; 1020 uint8_t int2_double_tap : 1; 1021 uint8_t int2_6d : 1; 1022 uint8_t int2_emb_func : 1; 1023 uint8_t int2_timestamp : 1; 1024 #endif /* DRV_BYTE_ORDER */ 1025 } lsm6dsox_md2_cfg_t; 1026 1027 #define LSM6DSOX_S4S_ST_CMD_CODE 0x60U 1028 typedef struct 1029 { 1030 uint8_t s4s_st_cmd_code : 8; 1031 } lsm6dsox_s4s_st_cmd_code_t; 1032 1033 #define LSM6DSOX_S4S_DT_REG 0x61U 1034 typedef struct 1035 { 1036 uint8_t dt : 8; 1037 } lsm6dsox_s4s_dt_reg_t; 1038 1039 #define LSM6DSOX_I3C_BUS_AVB 0x62U 1040 typedef struct 1041 { 1042 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1043 uint8_t pd_dis_int1 : 1; 1044 uint8_t not_used_01 : 2; 1045 uint8_t i3c_bus_avb_sel : 2; 1046 uint8_t not_used_02 : 3; 1047 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1048 uint8_t not_used_02 : 3; 1049 uint8_t i3c_bus_avb_sel : 2; 1050 uint8_t not_used_01 : 2; 1051 uint8_t pd_dis_int1 : 1; 1052 #endif /* DRV_BYTE_ORDER */ 1053 } lsm6dsox_i3c_bus_avb_t; 1054 1055 #define LSM6DSOX_INTERNAL_FREQ_FINE 0x63U 1056 typedef struct 1057 { 1058 uint8_t freq_fine : 8; 1059 } lsm6dsox_internal_freq_fine_t; 1060 1061 #define LSM6DSOX_UI_INT_OIS 0x6F 1062 typedef struct 1063 { 1064 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1065 uint8_t not_used_01 : 3; 1066 uint8_t spi2_read_en : 1; 1067 uint8_t not_used_02 : 1; 1068 uint8_t den_lh_ois : 1; 1069 uint8_t lvl2_ois : 1; 1070 uint8_t int2_drdy_ois : 1; 1071 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1072 uint8_t int2_drdy_ois : 1; 1073 uint8_t lvl2_ois : 1; 1074 uint8_t den_lh_ois : 1; 1075 uint8_t not_used_02 : 1; 1076 uint8_t spi2_read_en : 1; 1077 uint8_t not_used_01 : 3; 1078 #endif /* DRV_BYTE_ORDER */ 1079 } lsm6dsox_ui_int_ois_t; 1080 1081 #define LSM6DSOX_UI_CTRL1_OIS 0x70U 1082 typedef struct 1083 { 1084 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1085 uint8_t ois_en_spi2 : 1; 1086 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1087 uint8_t mode4_en : 1; 1088 uint8_t sim_ois : 1; 1089 uint8_t lvl1_ois : 1; 1090 uint8_t not_used_01 : 1; 1091 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1092 uint8_t not_used_01 : 1; 1093 uint8_t lvl1_ois : 1; 1094 uint8_t sim_ois : 1; 1095 uint8_t mode4_en : 1; 1096 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1097 uint8_t ois_en_spi2 : 1; 1098 #endif /* DRV_BYTE_ORDER */ 1099 } lsm6dsox_ui_ctrl1_ois_t; 1100 1101 #define LSM6DSOX_UI_CTRL2_OIS 0x71U 1102 typedef struct 1103 { 1104 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1105 uint8_t hp_en_ois : 1; 1106 uint8_t ftype_ois : 2; 1107 uint8_t not_used_01 : 1; 1108 uint8_t hpm_ois : 2; 1109 uint8_t not_used_02 : 2; 1110 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1111 uint8_t not_used_02 : 2; 1112 uint8_t hpm_ois : 2; 1113 uint8_t not_used_01 : 1; 1114 uint8_t ftype_ois : 2; 1115 uint8_t hp_en_ois : 1; 1116 #endif /* DRV_BYTE_ORDER */ 1117 } lsm6dsox_ui_ctrl2_ois_t; 1118 1119 #define LSM6DSOX_UI_CTRL3_OIS 0x72U 1120 typedef struct 1121 { 1122 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1123 uint8_t st_ois_clampdis : 1; 1124 uint8_t not_used_01 : 2; 1125 uint8_t filter_xl_conf_ois : 3; 1126 uint8_t fs_xl_ois : 2; 1127 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1128 uint8_t fs_xl_ois : 2; 1129 uint8_t filter_xl_conf_ois : 3; 1130 uint8_t not_used_01 : 2; 1131 uint8_t st_ois_clampdis : 1; 1132 #endif /* DRV_BYTE_ORDER */ 1133 } lsm6dsox_ui_ctrl3_ois_t; 1134 1135 #define LSM6DSOX_X_OFS_USR 0x73U 1136 #define LSM6DSOX_Y_OFS_USR 0x74U 1137 #define LSM6DSOX_Z_OFS_USR 0x75U 1138 #define LSM6DSOX_FIFO_DATA_OUT_TAG 0x78U 1139 typedef struct 1140 { 1141 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1142 uint8_t tag_parity : 1; 1143 uint8_t tag_cnt : 2; 1144 uint8_t tag_sensor : 5; 1145 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1146 uint8_t tag_sensor : 5; 1147 uint8_t tag_cnt : 2; 1148 uint8_t tag_parity : 1; 1149 #endif /* DRV_BYTE_ORDER */ 1150 } lsm6dsox_fifo_data_out_tag_t; 1151 1152 #define LSM6DSOX_FIFO_DATA_OUT_X_L 0x79 1153 #define LSM6DSOX_FIFO_DATA_OUT_X_H 0x7A 1154 #define LSM6DSOX_FIFO_DATA_OUT_Y_L 0x7B 1155 #define LSM6DSOX_FIFO_DATA_OUT_Y_H 0x7C 1156 #define LSM6DSOX_FIFO_DATA_OUT_Z_L 0x7D 1157 #define LSM6DSOX_FIFO_DATA_OUT_Z_H 0x7E 1158 1159 #define LSM6DSOX_SPI2_WHO_AM_I 0x0F 1160 #define LSM6DSOX_SPI2_STATUS_REG_OIS 0x1E 1161 typedef struct 1162 { 1163 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1164 uint8_t xlda : 1; 1165 uint8_t gda : 1; 1166 uint8_t gyro_settling : 1; 1167 uint8_t not_used_01 : 5; 1168 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1169 uint8_t not_used_01 : 5; 1170 uint8_t gyro_settling : 1; 1171 uint8_t gda : 1; 1172 uint8_t xlda : 1; 1173 #endif /* DRV_BYTE_ORDER */ 1174 } lsm6dsox_spi2_status_reg_ois_t; 1175 1176 #define LSM6DSOX_SPI2_OUT_TEMP_L 0x20 1177 #define LSM6DSOX_SPI2_OUT_TEMP_H 0x21 1178 #define LSM6DSOX_SPI2_OUTX_L_G_OIS 0x22 1179 #define LSM6DSOX_SPI2_OUTX_H_G_OIS 0x23 1180 #define LSM6DSOX_SPI2_OUTY_L_G_OIS 0x24 1181 #define LSM6DSOX_SPI2_OUTY_H_G_OIS 0x25 1182 #define LSM6DSOX_SPI2_OUTZ_L_G_OIS 0x26 1183 #define LSM6DSOX_SPI2_OUTZ_H_G_OIS 0x27 1184 #define LSM6DSOX_SPI2_OUTX_L_A_OIS 0x28 1185 #define LSM6DSOX_SPI2_OUTX_H_A_OIS 0x29 1186 #define LSM6DSOX_SPI2_OUTY_L_A_OIS 0x2A 1187 #define LSM6DSOX_SPI2_OUTY_H_A_OIS 0x2B 1188 #define LSM6DSOX_SPI2_OUTZ_L_A_OIS 0x2C 1189 #define LSM6DSOX_SPI2_OUTZ_H_A_OIS 0x2D 1190 #define LSM6DSOX_SPI2_INT_OIS 0x6F 1191 typedef struct 1192 { 1193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1194 uint8_t st_xl_ois : 2; 1195 uint8_t not_used_01 : 3; 1196 uint8_t den_lh_ois : 1; 1197 uint8_t lvl2_ois : 1; 1198 uint8_t int2_drdy_ois : 1; 1199 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1200 uint8_t int2_drdy_ois : 1; 1201 uint8_t lvl2_ois : 1; 1202 uint8_t den_lh_ois : 1; 1203 uint8_t not_used_01 : 3; 1204 uint8_t st_xl_ois : 2; 1205 #endif /* DRV_BYTE_ORDER */ 1206 } lsm6dsox_spi2_int_ois_t; 1207 1208 #define LSM6DSOX_SPI2_CTRL1_OIS 0x70U 1209 typedef struct 1210 { 1211 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1212 uint8_t ois_en_spi2 : 1; 1213 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1214 uint8_t mode4_en : 1; 1215 uint8_t sim_ois : 1; 1216 uint8_t lvl1_ois : 1; 1217 uint8_t not_used_01 : 1; 1218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1219 uint8_t not_used_01 : 1; 1220 uint8_t lvl1_ois : 1; 1221 uint8_t sim_ois : 1; 1222 uint8_t mode4_en : 1; 1223 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 1224 uint8_t ois_en_spi2 : 1; 1225 #endif /* DRV_BYTE_ORDER */ 1226 } lsm6dsox_spi2_ctrl1_ois_t; 1227 1228 #define LSM6DSOX_SPI2_CTRL2_OIS 0x71U 1229 typedef struct 1230 { 1231 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1232 uint8_t hp_en_ois : 1; 1233 uint8_t ftype_ois : 2; 1234 uint8_t not_used_01 : 1; 1235 uint8_t hpm_ois : 2; 1236 uint8_t not_used_02 : 2; 1237 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1238 uint8_t not_used_02 : 2; 1239 uint8_t hpm_ois : 2; 1240 uint8_t not_used_01 : 1; 1241 uint8_t ftype_ois : 2; 1242 uint8_t hp_en_ois : 1; 1243 #endif /* DRV_BYTE_ORDER */ 1244 } lsm6dsox_spi2_ctrl2_ois_t; 1245 1246 #define LSM6DSOX_SPI2_CTRL3_OIS 0x72U 1247 typedef struct 1248 { 1249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1250 uint8_t st_ois_clampdis : 1; 1251 uint8_t st_ois : 2; 1252 uint8_t filter_xl_conf_ois : 3; 1253 uint8_t fs_xl_ois : 2; 1254 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1255 uint8_t fs_xl_ois : 2; 1256 uint8_t filter_xl_conf_ois : 3; 1257 uint8_t st_ois : 2; 1258 uint8_t st_ois_clampdis : 1; 1259 #endif /* DRV_BYTE_ORDER */ 1260 } lsm6dsox_spi2_ctrl3_ois_t; 1261 1262 #define LSM6DSOX_PAGE_SEL 0x02U 1263 typedef struct 1264 { 1265 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1266 uint8_t not_used_01 : 4; 1267 uint8_t page_sel : 4; 1268 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1269 uint8_t page_sel : 4; 1270 uint8_t not_used_01 : 4; 1271 #endif /* DRV_BYTE_ORDER */ 1272 } lsm6dsox_page_sel_t; 1273 1274 #define LSM6DSOX_EMB_FUNC_EN_A 0x04U 1275 typedef struct 1276 { 1277 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1278 uint8_t not_used_01 : 3; 1279 uint8_t pedo_en : 1; 1280 uint8_t tilt_en : 1; 1281 uint8_t sign_motion_en : 1; 1282 uint8_t not_used_02 : 2; 1283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1284 uint8_t not_used_02 : 2; 1285 uint8_t sign_motion_en : 1; 1286 uint8_t tilt_en : 1; 1287 uint8_t pedo_en : 1; 1288 uint8_t not_used_01 : 3; 1289 #endif /* DRV_BYTE_ORDER */ 1290 } lsm6dsox_emb_func_en_a_t; 1291 1292 #define LSM6DSOX_EMB_FUNC_EN_B 0x05U 1293 typedef struct 1294 { 1295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1296 uint8_t fsm_en : 1; 1297 uint8_t not_used_01 : 2; 1298 uint8_t fifo_compr_en : 1; 1299 uint8_t mlc_en : 1; 1300 uint8_t not_used_02 : 3; 1301 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1302 uint8_t not_used_02 : 3; 1303 uint8_t mlc_en : 1; 1304 uint8_t fifo_compr_en : 1; 1305 uint8_t not_used_01 : 2; 1306 uint8_t fsm_en : 1; 1307 #endif /* DRV_BYTE_ORDER */ 1308 } lsm6dsox_emb_func_en_b_t; 1309 1310 #define LSM6DSOX_PAGE_ADDRESS 0x08U 1311 typedef struct 1312 { 1313 uint8_t page_addr : 8; 1314 } lsm6dsox_page_address_t; 1315 1316 #define LSM6DSOX_PAGE_VALUE 0x09U 1317 typedef struct 1318 { 1319 uint8_t page_value : 8; 1320 } lsm6dsox_page_value_t; 1321 1322 #define LSM6DSOX_EMB_FUNC_INT1 0x0AU 1323 typedef struct 1324 { 1325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1326 uint8_t not_used_01 : 3; 1327 uint8_t int1_step_detector : 1; 1328 uint8_t int1_tilt : 1; 1329 uint8_t int1_sig_mot : 1; 1330 uint8_t not_used_02 : 1; 1331 uint8_t int1_fsm_lc : 1; 1332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1333 uint8_t int1_fsm_lc : 1; 1334 uint8_t not_used_02 : 1; 1335 uint8_t int1_sig_mot : 1; 1336 uint8_t int1_tilt : 1; 1337 uint8_t int1_step_detector : 1; 1338 uint8_t not_used_01 : 3; 1339 #endif /* DRV_BYTE_ORDER */ 1340 } lsm6dsox_emb_func_int1_t; 1341 1342 #define LSM6DSOX_FSM_INT1_A 0x0BU 1343 typedef struct 1344 { 1345 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1346 uint8_t int1_fsm1 : 1; 1347 uint8_t int1_fsm2 : 1; 1348 uint8_t int1_fsm3 : 1; 1349 uint8_t int1_fsm4 : 1; 1350 uint8_t int1_fsm5 : 1; 1351 uint8_t int1_fsm6 : 1; 1352 uint8_t int1_fsm7 : 1; 1353 uint8_t int1_fsm8 : 1; 1354 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1355 uint8_t int1_fsm8 : 1; 1356 uint8_t int1_fsm7 : 1; 1357 uint8_t int1_fsm6 : 1; 1358 uint8_t int1_fsm5 : 1; 1359 uint8_t int1_fsm4 : 1; 1360 uint8_t int1_fsm3 : 1; 1361 uint8_t int1_fsm2 : 1; 1362 uint8_t int1_fsm1 : 1; 1363 #endif /* DRV_BYTE_ORDER */ 1364 } lsm6dsox_fsm_int1_a_t; 1365 1366 #define LSM6DSOX_FSM_INT1_B 0x0CU 1367 typedef struct 1368 { 1369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1370 uint8_t int1_fsm16 : 1; 1371 uint8_t int1_fsm15 : 1; 1372 uint8_t int1_fsm14 : 1; 1373 uint8_t int1_fsm13 : 1; 1374 uint8_t int1_fsm12 : 1; 1375 uint8_t int1_fsm11 : 1; 1376 uint8_t int1_fsm10 : 1; 1377 uint8_t int1_fsm9 : 1; 1378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1379 #endif /* DRV_BYTE_ORDER */ 1380 } lsm6dsox_fsm_int1_b_t; 1381 1382 #define LSM6DSOX_MLC_INT1 0x0DU 1383 typedef struct 1384 { 1385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1386 uint8_t int1_mlc1 : 1; 1387 uint8_t int1_mlc2 : 1; 1388 uint8_t int1_mlc3 : 1; 1389 uint8_t int1_mlc4 : 1; 1390 uint8_t int1_mlc5 : 1; 1391 uint8_t int1_mlc6 : 1; 1392 uint8_t int1_mlc7 : 1; 1393 uint8_t int1_mlc8 : 1; 1394 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1395 uint8_t int1_mlc8 : 1; 1396 uint8_t int1_mlc7 : 1; 1397 uint8_t int1_mlc6 : 1; 1398 uint8_t int1_mlc5 : 1; 1399 uint8_t int1_mlc4 : 1; 1400 uint8_t int1_mlc3 : 1; 1401 uint8_t int1_mlc2 : 1; 1402 uint8_t int1_mlc1 : 1; 1403 #endif /* DRV_BYTE_ORDER */ 1404 } lsm6dsox_mlc_int1_t; 1405 1406 #define LSM6DSOX_EMB_FUNC_INT2 0x0EU 1407 typedef struct 1408 { 1409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1410 uint8_t not_used_01 : 3; 1411 uint8_t int2_step_detector : 1; 1412 uint8_t int2_tilt : 1; 1413 uint8_t int2_sig_mot : 1; 1414 uint8_t not_used_02 : 1; 1415 uint8_t int2_fsm_lc : 1; 1416 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1417 uint8_t int2_fsm_lc : 1; 1418 uint8_t not_used_02 : 1; 1419 uint8_t int2_sig_mot : 1; 1420 uint8_t int2_tilt : 1; 1421 uint8_t int2_step_detector : 1; 1422 uint8_t not_used_01 : 3; 1423 #endif /* DRV_BYTE_ORDER */ 1424 } lsm6dsox_emb_func_int2_t; 1425 1426 #define LSM6DSOX_FSM_INT2_A 0x0FU 1427 typedef struct 1428 { 1429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1430 uint8_t int2_fsm1 : 1; 1431 uint8_t int2_fsm2 : 1; 1432 uint8_t int2_fsm3 : 1; 1433 uint8_t int2_fsm4 : 1; 1434 uint8_t int2_fsm5 : 1; 1435 uint8_t int2_fsm6 : 1; 1436 uint8_t int2_fsm7 : 1; 1437 uint8_t int2_fsm8 : 1; 1438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1439 uint8_t int2_fsm8 : 1; 1440 uint8_t int2_fsm7 : 1; 1441 uint8_t int2_fsm6 : 1; 1442 uint8_t int2_fsm5 : 1; 1443 uint8_t int2_fsm4 : 1; 1444 uint8_t int2_fsm3 : 1; 1445 uint8_t int2_fsm2 : 1; 1446 uint8_t int2_fsm1 : 1; 1447 #endif /* DRV_BYTE_ORDER */ 1448 } lsm6dsox_fsm_int2_a_t; 1449 1450 #define LSM6DSOX_FSM_INT2_B 0x10U 1451 typedef struct 1452 { 1453 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1454 uint8_t int2_fsm9 : 1; 1455 uint8_t int2_fsm10 : 1; 1456 uint8_t int2_fsm11 : 1; 1457 uint8_t int2_fsm12 : 1; 1458 uint8_t int2_fsm13 : 1; 1459 uint8_t int2_fsm14 : 1; 1460 uint8_t int2_fsm15 : 1; 1461 uint8_t int2_fsm16 : 1; 1462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1463 uint8_t int2_fsm16 : 1; 1464 uint8_t int2_fsm15 : 1; 1465 uint8_t int2_fsm14 : 1; 1466 uint8_t int2_fsm13 : 1; 1467 uint8_t int2_fsm12 : 1; 1468 uint8_t int2_fsm11 : 1; 1469 uint8_t int2_fsm10 : 1; 1470 uint8_t int2_fsm9 : 1; 1471 #endif /* DRV_BYTE_ORDER */ 1472 } lsm6dsox_fsm_int2_b_t; 1473 1474 #define LSM6DSOX_MLC_INT2 0x11U 1475 typedef struct 1476 { 1477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1478 uint8_t int2_mlc1 : 1; 1479 uint8_t int2_mlc2 : 1; 1480 uint8_t int2_mlc3 : 1; 1481 uint8_t int2_mlc4 : 1; 1482 uint8_t int2_mlc5 : 1; 1483 uint8_t int2_mlc6 : 1; 1484 uint8_t int2_mlc7 : 1; 1485 uint8_t int2_mlc8 : 1; 1486 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1487 uint8_t int2_mlc8 : 1; 1488 uint8_t int2_mlc7 : 1; 1489 uint8_t int2_mlc6 : 1; 1490 uint8_t int2_mlc5 : 1; 1491 uint8_t int2_mlc4 : 1; 1492 uint8_t int2_mlc3 : 1; 1493 uint8_t int2_mlc2 : 1; 1494 uint8_t int2_mlc1 : 1; 1495 #endif /* DRV_BYTE_ORDER */ 1496 } lsm6dsox_mlc_int2_t; 1497 1498 #define LSM6DSOX_EMB_FUNC_STATUS 0x12U 1499 typedef struct 1500 { 1501 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1502 uint8_t not_used_01 : 3; 1503 uint8_t is_step_det : 1; 1504 uint8_t is_tilt : 1; 1505 uint8_t is_sigmot : 1; 1506 uint8_t not_used_02 : 1; 1507 uint8_t is_fsm_lc : 1; 1508 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1509 uint8_t is_fsm_lc : 1; 1510 uint8_t not_used_02 : 1; 1511 uint8_t is_sigmot : 1; 1512 uint8_t is_tilt : 1; 1513 uint8_t is_step_det : 1; 1514 uint8_t not_used_01 : 3; 1515 #endif /* DRV_BYTE_ORDER */ 1516 } lsm6dsox_emb_func_status_t; 1517 1518 #define LSM6DSOX_FSM_STATUS_A 0x13U 1519 typedef struct 1520 { 1521 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1522 uint8_t is_fsm1 : 1; 1523 uint8_t is_fsm2 : 1; 1524 uint8_t is_fsm3 : 1; 1525 uint8_t is_fsm4 : 1; 1526 uint8_t is_fsm5 : 1; 1527 uint8_t is_fsm6 : 1; 1528 uint8_t is_fsm7 : 1; 1529 uint8_t is_fsm8 : 1; 1530 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1531 uint8_t is_fsm8 : 1; 1532 uint8_t is_fsm7 : 1; 1533 uint8_t is_fsm6 : 1; 1534 uint8_t is_fsm5 : 1; 1535 uint8_t is_fsm4 : 1; 1536 uint8_t is_fsm3 : 1; 1537 uint8_t is_fsm2 : 1; 1538 uint8_t is_fsm1 : 1; 1539 #endif /* DRV_BYTE_ORDER */ 1540 } lsm6dsox_fsm_status_a_t; 1541 1542 #define LSM6DSOX_FSM_STATUS_B 0x14U 1543 typedef struct 1544 { 1545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1546 uint8_t is_fsm9 : 1; 1547 uint8_t is_fsm10 : 1; 1548 uint8_t is_fsm11 : 1; 1549 uint8_t is_fsm12 : 1; 1550 uint8_t is_fsm13 : 1; 1551 uint8_t is_fsm14 : 1; 1552 uint8_t is_fsm15 : 1; 1553 uint8_t is_fsm16 : 1; 1554 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1555 uint8_t is_fsm16 : 1; 1556 uint8_t is_fsm15 : 1; 1557 uint8_t is_fsm14 : 1; 1558 uint8_t is_fsm13 : 1; 1559 uint8_t is_fsm12 : 1; 1560 uint8_t is_fsm11 : 1; 1561 uint8_t is_fsm10 : 1; 1562 uint8_t is_fsm9 : 1; 1563 #endif /* DRV_BYTE_ORDER */ 1564 } lsm6dsox_fsm_status_b_t; 1565 1566 #define LSM6DSOX_MLC_STATUS 0x15U 1567 typedef struct 1568 { 1569 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1570 uint8_t is_mlc1 : 1; 1571 uint8_t is_mlc2 : 1; 1572 uint8_t is_mlc3 : 1; 1573 uint8_t is_mlc4 : 1; 1574 uint8_t is_mlc5 : 1; 1575 uint8_t is_mlc6 : 1; 1576 uint8_t is_mlc7 : 1; 1577 uint8_t is_mlc8 : 1; 1578 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1579 uint8_t is_mlc8 : 1; 1580 uint8_t is_mlc7 : 1; 1581 uint8_t is_mlc6 : 1; 1582 uint8_t is_mlc5 : 1; 1583 uint8_t is_mlc4 : 1; 1584 uint8_t is_mlc3 : 1; 1585 uint8_t is_mlc2 : 1; 1586 uint8_t is_mlc1 : 1; 1587 #endif /* DRV_BYTE_ORDER */ 1588 } lsm6dsox_mlc_status_t; 1589 1590 #define LSM6DSOX_PAGE_RW 0x17U 1591 typedef struct 1592 { 1593 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1594 uint8_t not_used_01 : 5; 1595 uint8_t page_rw : 2; /* page_write + page_read */ 1596 uint8_t emb_func_lir : 1; 1597 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1598 uint8_t emb_func_lir : 1; 1599 uint8_t page_rw : 2; /* page_write + page_read */ 1600 uint8_t not_used_01 : 5; 1601 #endif /* DRV_BYTE_ORDER */ 1602 } lsm6dsox_page_rw_t; 1603 1604 #define LSM6DSOX_EMB_FUNC_FIFO_CFG 0x44U 1605 typedef struct 1606 { 1607 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1608 uint8_t not_used_00 : 6; 1609 uint8_t pedo_fifo_en : 1; 1610 uint8_t not_used_01 : 1; 1611 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1612 uint8_t not_used_01 : 1; 1613 uint8_t pedo_fifo_en : 1; 1614 uint8_t not_used_00 : 6; 1615 #endif /* DRV_BYTE_ORDER */ 1616 } lsm6dsox_emb_func_fifo_cfg_t; 1617 1618 #define LSM6DSOX_FSM_ENABLE_A 0x46U 1619 typedef struct 1620 { 1621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1622 uint8_t fsm1_en : 1; 1623 uint8_t fsm2_en : 1; 1624 uint8_t fsm3_en : 1; 1625 uint8_t fsm4_en : 1; 1626 uint8_t fsm5_en : 1; 1627 uint8_t fsm6_en : 1; 1628 uint8_t fsm7_en : 1; 1629 uint8_t fsm8_en : 1; 1630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1631 uint8_t fsm8_en : 1; 1632 uint8_t fsm7_en : 1; 1633 uint8_t fsm6_en : 1; 1634 uint8_t fsm5_en : 1; 1635 uint8_t fsm4_en : 1; 1636 uint8_t fsm3_en : 1; 1637 uint8_t fsm2_en : 1; 1638 uint8_t fsm1_en : 1; 1639 #endif /* DRV_BYTE_ORDER */ 1640 } lsm6dsox_fsm_enable_a_t; 1641 1642 #define LSM6DSOX_FSM_ENABLE_B 0x47U 1643 typedef struct 1644 { 1645 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1646 uint8_t fsm9_en : 1; 1647 uint8_t fsm10_en : 1; 1648 uint8_t fsm11_en : 1; 1649 uint8_t fsm12_en : 1; 1650 uint8_t fsm13_en : 1; 1651 uint8_t fsm14_en : 1; 1652 uint8_t fsm15_en : 1; 1653 uint8_t fsm16_en : 1; 1654 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1655 uint8_t fsm16_en : 1; 1656 uint8_t fsm15_en : 1; 1657 uint8_t fsm14_en : 1; 1658 uint8_t fsm13_en : 1; 1659 uint8_t fsm12_en : 1; 1660 uint8_t fsm11_en : 1; 1661 uint8_t fsm10_en : 1; 1662 uint8_t fsm9_en : 1; 1663 #endif /* DRV_BYTE_ORDER */ 1664 } lsm6dsox_fsm_enable_b_t; 1665 1666 #define LSM6DSOX_FSM_LONG_COUNTER_L 0x48U 1667 #define LSM6DSOX_FSM_LONG_COUNTER_H 0x49U 1668 #define LSM6DSOX_FSM_LONG_COUNTER_CLEAR 0x4AU 1669 typedef struct 1670 { 1671 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1672 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1673 uint8_t not_used_01 : 6; 1674 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1675 uint8_t not_used_01 : 6; 1676 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1677 #endif /* DRV_BYTE_ORDER */ 1678 } lsm6dsox_fsm_long_counter_clear_t; 1679 1680 #define LSM6DSOX_FSM_OUTS1 0x4CU 1681 typedef struct 1682 { 1683 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1684 uint8_t n_v : 1; 1685 uint8_t p_v : 1; 1686 uint8_t n_z : 1; 1687 uint8_t p_z : 1; 1688 uint8_t n_y : 1; 1689 uint8_t p_y : 1; 1690 uint8_t n_x : 1; 1691 uint8_t p_x : 1; 1692 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1693 uint8_t p_x : 1; 1694 uint8_t n_x : 1; 1695 uint8_t p_y : 1; 1696 uint8_t n_y : 1; 1697 uint8_t p_z : 1; 1698 uint8_t n_z : 1; 1699 uint8_t p_v : 1; 1700 uint8_t n_v : 1; 1701 #endif /* DRV_BYTE_ORDER */ 1702 } lsm6dsox_fsm_outs1_t; 1703 1704 #define LSM6DSOX_FSM_OUTS2 0x4DU 1705 typedef struct 1706 { 1707 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1708 uint8_t n_v : 1; 1709 uint8_t p_v : 1; 1710 uint8_t n_z : 1; 1711 uint8_t p_z : 1; 1712 uint8_t n_y : 1; 1713 uint8_t p_y : 1; 1714 uint8_t n_x : 1; 1715 uint8_t p_x : 1; 1716 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1717 uint8_t p_x : 1; 1718 uint8_t n_x : 1; 1719 uint8_t p_y : 1; 1720 uint8_t n_y : 1; 1721 uint8_t p_z : 1; 1722 uint8_t n_z : 1; 1723 uint8_t p_v : 1; 1724 uint8_t n_v : 1; 1725 #endif /* DRV_BYTE_ORDER */ 1726 } lsm6dsox_fsm_outs2_t; 1727 1728 #define LSM6DSOX_FSM_OUTS3 0x4EU 1729 typedef struct 1730 { 1731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1732 uint8_t n_v : 1; 1733 uint8_t p_v : 1; 1734 uint8_t n_z : 1; 1735 uint8_t p_z : 1; 1736 uint8_t n_y : 1; 1737 uint8_t p_y : 1; 1738 uint8_t n_x : 1; 1739 uint8_t p_x : 1; 1740 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1741 uint8_t p_x : 1; 1742 uint8_t n_x : 1; 1743 uint8_t p_y : 1; 1744 uint8_t n_y : 1; 1745 uint8_t p_z : 1; 1746 uint8_t n_z : 1; 1747 uint8_t p_v : 1; 1748 uint8_t n_v : 1; 1749 #endif /* DRV_BYTE_ORDER */ 1750 } lsm6dsox_fsm_outs3_t; 1751 1752 #define LSM6DSOX_FSM_OUTS4 0x4FU 1753 typedef struct 1754 { 1755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1756 uint8_t n_v : 1; 1757 uint8_t p_v : 1; 1758 uint8_t n_z : 1; 1759 uint8_t p_z : 1; 1760 uint8_t n_y : 1; 1761 uint8_t p_y : 1; 1762 uint8_t n_x : 1; 1763 uint8_t p_x : 1; 1764 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1765 uint8_t p_x : 1; 1766 uint8_t n_x : 1; 1767 uint8_t p_y : 1; 1768 uint8_t n_y : 1; 1769 uint8_t p_z : 1; 1770 uint8_t n_z : 1; 1771 uint8_t p_v : 1; 1772 uint8_t n_v : 1; 1773 #endif /* DRV_BYTE_ORDER */ 1774 } lsm6dsox_fsm_outs4_t; 1775 1776 #define LSM6DSOX_FSM_OUTS5 0x50U 1777 typedef struct 1778 { 1779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1780 uint8_t n_v : 1; 1781 uint8_t p_v : 1; 1782 uint8_t n_z : 1; 1783 uint8_t p_z : 1; 1784 uint8_t n_y : 1; 1785 uint8_t p_y : 1; 1786 uint8_t n_x : 1; 1787 uint8_t p_x : 1; 1788 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1789 uint8_t p_x : 1; 1790 uint8_t n_x : 1; 1791 uint8_t p_y : 1; 1792 uint8_t n_y : 1; 1793 uint8_t p_z : 1; 1794 uint8_t n_z : 1; 1795 uint8_t p_v : 1; 1796 uint8_t n_v : 1; 1797 #endif /* DRV_BYTE_ORDER */ 1798 } lsm6dsox_fsm_outs5_t; 1799 1800 #define LSM6DSOX_FSM_OUTS6 0x51U 1801 typedef struct 1802 { 1803 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1804 uint8_t n_v : 1; 1805 uint8_t p_v : 1; 1806 uint8_t n_z : 1; 1807 uint8_t p_z : 1; 1808 uint8_t n_y : 1; 1809 uint8_t p_y : 1; 1810 uint8_t n_x : 1; 1811 uint8_t p_x : 1; 1812 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1813 uint8_t p_x : 1; 1814 uint8_t n_x : 1; 1815 uint8_t p_y : 1; 1816 uint8_t n_y : 1; 1817 uint8_t p_z : 1; 1818 uint8_t n_z : 1; 1819 uint8_t p_v : 1; 1820 uint8_t n_v : 1; 1821 #endif /* DRV_BYTE_ORDER */ 1822 } lsm6dsox_fsm_outs6_t; 1823 1824 #define LSM6DSOX_FSM_OUTS7 0x52U 1825 typedef struct 1826 { 1827 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1828 uint8_t n_v : 1; 1829 uint8_t p_v : 1; 1830 uint8_t n_z : 1; 1831 uint8_t p_z : 1; 1832 uint8_t n_y : 1; 1833 uint8_t p_y : 1; 1834 uint8_t n_x : 1; 1835 uint8_t p_x : 1; 1836 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1837 uint8_t p_x : 1; 1838 uint8_t n_x : 1; 1839 uint8_t p_y : 1; 1840 uint8_t n_y : 1; 1841 uint8_t p_z : 1; 1842 uint8_t n_z : 1; 1843 uint8_t p_v : 1; 1844 uint8_t n_v : 1; 1845 #endif /* DRV_BYTE_ORDER */ 1846 } lsm6dsox_fsm_outs7_t; 1847 1848 #define LSM6DSOX_FSM_OUTS8 0x53U 1849 typedef struct 1850 { 1851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1852 uint8_t n_v : 1; 1853 uint8_t p_v : 1; 1854 uint8_t n_z : 1; 1855 uint8_t p_z : 1; 1856 uint8_t n_y : 1; 1857 uint8_t p_y : 1; 1858 uint8_t n_x : 1; 1859 uint8_t p_x : 1; 1860 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1861 uint8_t p_x : 1; 1862 uint8_t n_x : 1; 1863 uint8_t p_y : 1; 1864 uint8_t n_y : 1; 1865 uint8_t p_z : 1; 1866 uint8_t n_z : 1; 1867 uint8_t p_v : 1; 1868 uint8_t n_v : 1; 1869 #endif /* DRV_BYTE_ORDER */ 1870 } lsm6dsox_fsm_outs8_t; 1871 1872 #define LSM6DSOX_FSM_OUTS9 0x54U 1873 typedef struct 1874 { 1875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1876 uint8_t n_v : 1; 1877 uint8_t p_v : 1; 1878 uint8_t n_z : 1; 1879 uint8_t p_z : 1; 1880 uint8_t n_y : 1; 1881 uint8_t p_y : 1; 1882 uint8_t n_x : 1; 1883 uint8_t p_x : 1; 1884 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1885 uint8_t p_x : 1; 1886 uint8_t n_x : 1; 1887 uint8_t p_y : 1; 1888 uint8_t n_y : 1; 1889 uint8_t p_z : 1; 1890 uint8_t n_z : 1; 1891 uint8_t p_v : 1; 1892 uint8_t n_v : 1; 1893 #endif /* DRV_BYTE_ORDER */ 1894 } lsm6dsox_fsm_outs9_t; 1895 1896 #define LSM6DSOX_FSM_OUTS10 0x55U 1897 typedef struct 1898 { 1899 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1900 uint8_t n_v : 1; 1901 uint8_t p_v : 1; 1902 uint8_t n_z : 1; 1903 uint8_t p_z : 1; 1904 uint8_t n_y : 1; 1905 uint8_t p_y : 1; 1906 uint8_t n_x : 1; 1907 uint8_t p_x : 1; 1908 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1909 uint8_t p_x : 1; 1910 uint8_t n_x : 1; 1911 uint8_t p_y : 1; 1912 uint8_t n_y : 1; 1913 uint8_t p_z : 1; 1914 uint8_t n_z : 1; 1915 uint8_t p_v : 1; 1916 uint8_t n_v : 1; 1917 #endif /* DRV_BYTE_ORDER */ 1918 } lsm6dsox_fsm_outs10_t; 1919 1920 #define LSM6DSOX_FSM_OUTS11 0x56U 1921 typedef struct 1922 { 1923 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1924 uint8_t n_v : 1; 1925 uint8_t p_v : 1; 1926 uint8_t n_z : 1; 1927 uint8_t p_z : 1; 1928 uint8_t n_y : 1; 1929 uint8_t p_y : 1; 1930 uint8_t n_x : 1; 1931 uint8_t p_x : 1; 1932 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1933 uint8_t p_x : 1; 1934 uint8_t n_x : 1; 1935 uint8_t p_y : 1; 1936 uint8_t n_y : 1; 1937 uint8_t p_z : 1; 1938 uint8_t n_z : 1; 1939 uint8_t p_v : 1; 1940 uint8_t n_v : 1; 1941 #endif /* DRV_BYTE_ORDER */ 1942 } lsm6dsox_fsm_outs11_t; 1943 1944 #define LSM6DSOX_FSM_OUTS12 0x57U 1945 typedef struct 1946 { 1947 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1948 uint8_t n_v : 1; 1949 uint8_t p_v : 1; 1950 uint8_t n_z : 1; 1951 uint8_t p_z : 1; 1952 uint8_t n_y : 1; 1953 uint8_t p_y : 1; 1954 uint8_t n_x : 1; 1955 uint8_t p_x : 1; 1956 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1957 uint8_t p_x : 1; 1958 uint8_t n_x : 1; 1959 uint8_t p_y : 1; 1960 uint8_t n_y : 1; 1961 uint8_t p_z : 1; 1962 uint8_t n_z : 1; 1963 uint8_t p_v : 1; 1964 uint8_t n_v : 1; 1965 #endif /* DRV_BYTE_ORDER */ 1966 } lsm6dsox_fsm_outs12_t; 1967 1968 #define LSM6DSOX_FSM_OUTS13 0x58U 1969 typedef struct 1970 { 1971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1972 uint8_t n_v : 1; 1973 uint8_t p_v : 1; 1974 uint8_t n_z : 1; 1975 uint8_t p_z : 1; 1976 uint8_t n_y : 1; 1977 uint8_t p_y : 1; 1978 uint8_t n_x : 1; 1979 uint8_t p_x : 1; 1980 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1981 uint8_t p_x : 1; 1982 uint8_t n_x : 1; 1983 uint8_t p_y : 1; 1984 uint8_t n_y : 1; 1985 uint8_t p_z : 1; 1986 uint8_t n_z : 1; 1987 uint8_t p_v : 1; 1988 uint8_t n_v : 1; 1989 #endif /* DRV_BYTE_ORDER */ 1990 } lsm6dsox_fsm_outs13_t; 1991 1992 #define LSM6DSOX_FSM_OUTS14 0x59U 1993 typedef struct 1994 { 1995 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1996 uint8_t n_v : 1; 1997 uint8_t p_v : 1; 1998 uint8_t n_z : 1; 1999 uint8_t p_z : 1; 2000 uint8_t n_y : 1; 2001 uint8_t p_y : 1; 2002 uint8_t n_x : 1; 2003 uint8_t p_x : 1; 2004 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2005 uint8_t p_x : 1; 2006 uint8_t n_x : 1; 2007 uint8_t p_y : 1; 2008 uint8_t n_y : 1; 2009 uint8_t p_z : 1; 2010 uint8_t n_z : 1; 2011 uint8_t p_v : 1; 2012 uint8_t n_v : 1; 2013 #endif /* DRV_BYTE_ORDER */ 2014 } lsm6dsox_fsm_outs14_t; 2015 2016 #define LSM6DSOX_FSM_OUTS15 0x5AU 2017 typedef struct 2018 { 2019 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2020 uint8_t n_v : 1; 2021 uint8_t p_v : 1; 2022 uint8_t n_z : 1; 2023 uint8_t p_z : 1; 2024 uint8_t n_y : 1; 2025 uint8_t p_y : 1; 2026 uint8_t n_x : 1; 2027 uint8_t p_x : 1; 2028 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2029 uint8_t p_x : 1; 2030 uint8_t n_x : 1; 2031 uint8_t p_y : 1; 2032 uint8_t n_y : 1; 2033 uint8_t p_z : 1; 2034 uint8_t n_z : 1; 2035 uint8_t p_v : 1; 2036 uint8_t n_v : 1; 2037 #endif /* DRV_BYTE_ORDER */ 2038 } lsm6dsox_fsm_outs15_t; 2039 2040 #define LSM6DSOX_FSM_OUTS16 0x5BU 2041 typedef struct 2042 { 2043 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2044 uint8_t n_v : 1; 2045 uint8_t p_v : 1; 2046 uint8_t n_z : 1; 2047 uint8_t p_z : 1; 2048 uint8_t n_y : 1; 2049 uint8_t p_y : 1; 2050 uint8_t n_x : 1; 2051 uint8_t p_x : 1; 2052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2053 uint8_t p_x : 1; 2054 uint8_t n_x : 1; 2055 uint8_t p_y : 1; 2056 uint8_t n_y : 1; 2057 uint8_t p_z : 1; 2058 uint8_t n_z : 1; 2059 uint8_t p_v : 1; 2060 uint8_t n_v : 1; 2061 #endif /* DRV_BYTE_ORDER */ 2062 } lsm6dsox_fsm_outs16_t; 2063 2064 #define LSM6DSOX_EMB_FUNC_ODR_CFG_B 0x5FU 2065 typedef struct 2066 { 2067 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2068 uint8_t not_used_01 : 3; 2069 uint8_t fsm_odr : 2; 2070 uint8_t not_used_02 : 3; 2071 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2072 uint8_t not_used_02 : 3; 2073 uint8_t fsm_odr : 2; 2074 uint8_t not_used_01 : 3; 2075 #endif /* DRV_BYTE_ORDER */ 2076 } lsm6dsox_emb_func_odr_cfg_b_t; 2077 2078 #define LSM6DSOX_EMB_FUNC_ODR_CFG_C 0x60U 2079 typedef struct 2080 { 2081 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2082 uint8_t not_used_01 : 4; 2083 uint8_t mlc_odr : 2; 2084 uint8_t not_used_02 : 2; 2085 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2086 uint8_t not_used_02 : 2; 2087 uint8_t mlc_odr : 2; 2088 uint8_t not_used_01 : 4; 2089 #endif /* DRV_BYTE_ORDER */ 2090 } lsm6dsox_emb_func_odr_cfg_c_t; 2091 2092 #define LSM6DSOX_STEP_COUNTER_L 0x62U 2093 #define LSM6DSOX_STEP_COUNTER_H 0x63U 2094 #define LSM6DSOX_EMB_FUNC_SRC 0x64U 2095 typedef struct 2096 { 2097 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2098 uint8_t not_used_01 : 2; 2099 uint8_t stepcounter_bit_set : 1; 2100 uint8_t step_overflow : 1; 2101 uint8_t step_count_delta_ia : 1; 2102 uint8_t step_detected : 1; 2103 uint8_t not_used_02 : 1; 2104 uint8_t pedo_rst_step : 1; 2105 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2106 uint8_t pedo_rst_step : 1; 2107 uint8_t not_used_02 : 1; 2108 uint8_t step_detected : 1; 2109 uint8_t step_count_delta_ia : 1; 2110 uint8_t step_overflow : 1; 2111 uint8_t stepcounter_bit_set : 1; 2112 uint8_t not_used_01 : 2; 2113 #endif /* DRV_BYTE_ORDER */ 2114 } lsm6dsox_emb_func_src_t; 2115 2116 #define LSM6DSOX_EMB_FUNC_INIT_A 0x66U 2117 typedef struct 2118 { 2119 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2120 uint8_t not_used_01 : 3; 2121 uint8_t step_det_init : 1; 2122 uint8_t tilt_init : 1; 2123 uint8_t sig_mot_init : 1; 2124 uint8_t not_used_02 : 2; 2125 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2126 uint8_t not_used_02 : 2; 2127 uint8_t sig_mot_init : 1; 2128 uint8_t tilt_init : 1; 2129 uint8_t step_det_init : 1; 2130 uint8_t not_used_01 : 3; 2131 #endif /* DRV_BYTE_ORDER */ 2132 } lsm6dsox_emb_func_init_a_t; 2133 2134 #define LSM6DSOX_EMB_FUNC_INIT_B 0x67U 2135 typedef struct 2136 { 2137 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2138 uint8_t fsm_init : 1; 2139 uint8_t not_used_01 : 2; 2140 uint8_t fifo_compr_init : 1; 2141 uint8_t mlc_init : 1; 2142 uint8_t not_used_02 : 3; 2143 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2144 uint8_t not_used_02 : 3; 2145 uint8_t mlc_init : 1; 2146 uint8_t fifo_compr_init : 1; 2147 uint8_t not_used_01 : 2; 2148 uint8_t fsm_init : 1; 2149 #endif /* DRV_BYTE_ORDER */ 2150 } lsm6dsox_emb_func_init_b_t; 2151 2152 #define LSM6DSOX_MLC0_SRC 0x70U 2153 #define LSM6DSOX_MLC1_SRC 0x71U 2154 #define LSM6DSOX_MLC2_SRC 0x72U 2155 #define LSM6DSOX_MLC3_SRC 0x73U 2156 #define LSM6DSOX_MLC4_SRC 0x74U 2157 #define LSM6DSOX_MLC5_SRC 0x75U 2158 #define LSM6DSOX_MLC6_SRC 0x76U 2159 #define LSM6DSOX_MLC7_SRC 0x77U 2160 #define LSM6DSOX_MAG_SENSITIVITY_L 0xBAU 2161 #define LSM6DSOX_MAG_SENSITIVITY_H 0xBBU 2162 #define LSM6DSOX_MAG_OFFX_L 0xC0U 2163 #define LSM6DSOX_MAG_OFFX_H 0xC1U 2164 #define LSM6DSOX_MAG_OFFY_L 0xC2U 2165 #define LSM6DSOX_MAG_OFFY_H 0xC3U 2166 #define LSM6DSOX_MAG_OFFZ_L 0xC4U 2167 #define LSM6DSOX_MAG_OFFZ_H 0xC5U 2168 #define LSM6DSOX_MAG_SI_XX_L 0xC6U 2169 #define LSM6DSOX_MAG_SI_XX_H 0xC7U 2170 #define LSM6DSOX_MAG_SI_XY_L 0xC8U 2171 #define LSM6DSOX_MAG_SI_XY_H 0xC9U 2172 #define LSM6DSOX_MAG_SI_XZ_L 0xCAU 2173 #define LSM6DSOX_MAG_SI_XZ_H 0xCBU 2174 #define LSM6DSOX_MAG_SI_YY_L 0xCCU 2175 #define LSM6DSOX_MAG_SI_YY_H 0xCDU 2176 #define LSM6DSOX_MAG_SI_YZ_L 0xCEU 2177 #define LSM6DSOX_MAG_SI_YZ_H 0xCFU 2178 #define LSM6DSOX_MAG_SI_ZZ_L 0xD0U 2179 #define LSM6DSOX_MAG_SI_ZZ_H 0xD1U 2180 #define LSM6DSOX_MAG_CFG_A 0xD4U 2181 typedef struct 2182 { 2183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2184 uint8_t mag_z_axis : 3; 2185 uint8_t not_used_01 : 1; 2186 uint8_t mag_y_axis : 3; 2187 uint8_t not_used_02 : 1; 2188 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2189 uint8_t not_used_02 : 1; 2190 uint8_t mag_y_axis : 3; 2191 uint8_t not_used_01 : 1; 2192 uint8_t mag_z_axis : 3; 2193 #endif /* DRV_BYTE_ORDER */ 2194 } lsm6dsox_mag_cfg_a_t; 2195 2196 #define LSM6DSOX_MAG_CFG_B 0xD5U 2197 typedef struct 2198 { 2199 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2200 uint8_t mag_x_axis : 3; 2201 uint8_t not_used_01 : 5; 2202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2203 uint8_t not_used_01 : 5; 2204 uint8_t mag_x_axis : 3; 2205 #endif /* DRV_BYTE_ORDER */ 2206 } lsm6dsox_mag_cfg_b_t; 2207 2208 #define LSM6DSOX_FSM_LC_TIMEOUT_L 0x17AU 2209 #define LSM6DSOX_FSM_LC_TIMEOUT_H 0x17BU 2210 #define LSM6DSOX_FSM_PROGRAMS 0x17CU 2211 #define LSM6DSOX_FSM_START_ADD_L 0x17EU 2212 #define LSM6DSOX_FSM_START_ADD_H 0x17FU 2213 #define LSM6DSOX_PEDO_CMD_REG 0x183U 2214 typedef struct 2215 { 2216 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2217 uint8_t ad_det_en : 1; 2218 uint8_t not_used_01 : 1; 2219 uint8_t fp_rejection_en : 1; 2220 uint8_t carry_count_en : 1; 2221 uint8_t not_used_02 : 4; 2222 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2223 uint8_t not_used_02 : 4; 2224 uint8_t carry_count_en : 1; 2225 uint8_t fp_rejection_en : 1; 2226 uint8_t not_used_01 : 1; 2227 uint8_t ad_det_en : 1; 2228 #endif /* DRV_BYTE_ORDER */ 2229 } lsm6dsox_pedo_cmd_reg_t; 2230 2231 #define LSM6DSOX_PEDO_DEB_STEPS_CONF 0x184U 2232 #define LSM6DSOX_PEDO_SC_DELTAT_L 0x1D0U 2233 #define LSM6DSOX_PEDO_SC_DELTAT_H 0x1D1U 2234 2235 #define LSM6DSOX_MLC_MAG_SENSITIVITY_L 0x1E8U 2236 #define LSM6DSOX_MLC_MAG_SENSITIVITY_H 0x1E9U 2237 2238 #define LSM6DSOX_SENSOR_HUB_1 0x02U 2239 typedef struct 2240 { 2241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2242 uint8_t bit0 : 1; 2243 uint8_t bit1 : 1; 2244 uint8_t bit2 : 1; 2245 uint8_t bit3 : 1; 2246 uint8_t bit4 : 1; 2247 uint8_t bit5 : 1; 2248 uint8_t bit6 : 1; 2249 uint8_t bit7 : 1; 2250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2251 uint8_t bit7 : 1; 2252 uint8_t bit6 : 1; 2253 uint8_t bit5 : 1; 2254 uint8_t bit4 : 1; 2255 uint8_t bit3 : 1; 2256 uint8_t bit2 : 1; 2257 uint8_t bit1 : 1; 2258 uint8_t bit0 : 1; 2259 #endif /* DRV_BYTE_ORDER */ 2260 } lsm6dsox_sensor_hub_1_t; 2261 2262 #define LSM6DSOX_SENSOR_HUB_2 0x03U 2263 typedef struct 2264 { 2265 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2266 uint8_t bit0 : 1; 2267 uint8_t bit1 : 1; 2268 uint8_t bit2 : 1; 2269 uint8_t bit3 : 1; 2270 uint8_t bit4 : 1; 2271 uint8_t bit5 : 1; 2272 uint8_t bit6 : 1; 2273 uint8_t bit7 : 1; 2274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2275 uint8_t bit7 : 1; 2276 uint8_t bit6 : 1; 2277 uint8_t bit5 : 1; 2278 uint8_t bit4 : 1; 2279 uint8_t bit3 : 1; 2280 uint8_t bit2 : 1; 2281 uint8_t bit1 : 1; 2282 uint8_t bit0 : 1; 2283 #endif /* DRV_BYTE_ORDER */ 2284 } lsm6dsox_sensor_hub_2_t; 2285 2286 #define LSM6DSOX_SENSOR_HUB_3 0x04U 2287 typedef struct 2288 { 2289 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2290 uint8_t bit0 : 1; 2291 uint8_t bit1 : 1; 2292 uint8_t bit2 : 1; 2293 uint8_t bit3 : 1; 2294 uint8_t bit4 : 1; 2295 uint8_t bit5 : 1; 2296 uint8_t bit6 : 1; 2297 uint8_t bit7 : 1; 2298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2299 uint8_t bit7 : 1; 2300 uint8_t bit6 : 1; 2301 uint8_t bit5 : 1; 2302 uint8_t bit4 : 1; 2303 uint8_t bit3 : 1; 2304 uint8_t bit2 : 1; 2305 uint8_t bit1 : 1; 2306 uint8_t bit0 : 1; 2307 #endif /* DRV_BYTE_ORDER */ 2308 } lsm6dsox_sensor_hub_3_t; 2309 2310 #define LSM6DSOX_SENSOR_HUB_4 0x05U 2311 typedef struct 2312 { 2313 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2314 uint8_t bit0 : 1; 2315 uint8_t bit1 : 1; 2316 uint8_t bit2 : 1; 2317 uint8_t bit3 : 1; 2318 uint8_t bit4 : 1; 2319 uint8_t bit5 : 1; 2320 uint8_t bit6 : 1; 2321 uint8_t bit7 : 1; 2322 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2323 uint8_t bit7 : 1; 2324 uint8_t bit6 : 1; 2325 uint8_t bit5 : 1; 2326 uint8_t bit4 : 1; 2327 uint8_t bit3 : 1; 2328 uint8_t bit2 : 1; 2329 uint8_t bit1 : 1; 2330 uint8_t bit0 : 1; 2331 #endif /* DRV_BYTE_ORDER */ 2332 } lsm6dsox_sensor_hub_4_t; 2333 2334 #define LSM6DSOX_SENSOR_HUB_5 0x06U 2335 typedef struct 2336 { 2337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2338 uint8_t bit0 : 1; 2339 uint8_t bit1 : 1; 2340 uint8_t bit2 : 1; 2341 uint8_t bit3 : 1; 2342 uint8_t bit4 : 1; 2343 uint8_t bit5 : 1; 2344 uint8_t bit6 : 1; 2345 uint8_t bit7 : 1; 2346 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2347 uint8_t bit7 : 1; 2348 uint8_t bit6 : 1; 2349 uint8_t bit5 : 1; 2350 uint8_t bit4 : 1; 2351 uint8_t bit3 : 1; 2352 uint8_t bit2 : 1; 2353 uint8_t bit1 : 1; 2354 uint8_t bit0 : 1; 2355 #endif /* DRV_BYTE_ORDER */ 2356 } lsm6dsox_sensor_hub_5_t; 2357 2358 #define LSM6DSOX_SENSOR_HUB_6 0x07U 2359 typedef struct 2360 { 2361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2362 uint8_t bit0 : 1; 2363 uint8_t bit1 : 1; 2364 uint8_t bit2 : 1; 2365 uint8_t bit3 : 1; 2366 uint8_t bit4 : 1; 2367 uint8_t bit5 : 1; 2368 uint8_t bit6 : 1; 2369 uint8_t bit7 : 1; 2370 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2371 uint8_t bit7 : 1; 2372 uint8_t bit6 : 1; 2373 uint8_t bit5 : 1; 2374 uint8_t bit4 : 1; 2375 uint8_t bit3 : 1; 2376 uint8_t bit2 : 1; 2377 uint8_t bit1 : 1; 2378 uint8_t bit0 : 1; 2379 #endif /* DRV_BYTE_ORDER */ 2380 } lsm6dsox_sensor_hub_6_t; 2381 2382 #define LSM6DSOX_SENSOR_HUB_7 0x08U 2383 typedef struct 2384 { 2385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2386 uint8_t bit0 : 1; 2387 uint8_t bit1 : 1; 2388 uint8_t bit2 : 1; 2389 uint8_t bit3 : 1; 2390 uint8_t bit4 : 1; 2391 uint8_t bit5 : 1; 2392 uint8_t bit6 : 1; 2393 uint8_t bit7 : 1; 2394 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2395 uint8_t bit7 : 1; 2396 uint8_t bit6 : 1; 2397 uint8_t bit5 : 1; 2398 uint8_t bit4 : 1; 2399 uint8_t bit3 : 1; 2400 uint8_t bit2 : 1; 2401 uint8_t bit1 : 1; 2402 uint8_t bit0 : 1; 2403 #endif /* DRV_BYTE_ORDER */ 2404 } lsm6dsox_sensor_hub_7_t; 2405 2406 #define LSM6DSOX_SENSOR_HUB_8 0x09U 2407 typedef struct 2408 { 2409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2410 uint8_t bit0 : 1; 2411 uint8_t bit1 : 1; 2412 uint8_t bit2 : 1; 2413 uint8_t bit3 : 1; 2414 uint8_t bit4 : 1; 2415 uint8_t bit5 : 1; 2416 uint8_t bit6 : 1; 2417 uint8_t bit7 : 1; 2418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2419 uint8_t bit7 : 1; 2420 uint8_t bit6 : 1; 2421 uint8_t bit5 : 1; 2422 uint8_t bit4 : 1; 2423 uint8_t bit3 : 1; 2424 uint8_t bit2 : 1; 2425 uint8_t bit1 : 1; 2426 uint8_t bit0 : 1; 2427 #endif /* DRV_BYTE_ORDER */ 2428 } lsm6dsox_sensor_hub_8_t; 2429 2430 #define LSM6DSOX_SENSOR_HUB_9 0x0AU 2431 typedef struct 2432 { 2433 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2434 uint8_t bit0 : 1; 2435 uint8_t bit1 : 1; 2436 uint8_t bit2 : 1; 2437 uint8_t bit3 : 1; 2438 uint8_t bit4 : 1; 2439 uint8_t bit5 : 1; 2440 uint8_t bit6 : 1; 2441 uint8_t bit7 : 1; 2442 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2443 uint8_t bit7 : 1; 2444 uint8_t bit6 : 1; 2445 uint8_t bit5 : 1; 2446 uint8_t bit4 : 1; 2447 uint8_t bit3 : 1; 2448 uint8_t bit2 : 1; 2449 uint8_t bit1 : 1; 2450 uint8_t bit0 : 1; 2451 #endif /* DRV_BYTE_ORDER */ 2452 } lsm6dsox_sensor_hub_9_t; 2453 2454 #define LSM6DSOX_SENSOR_HUB_10 0x0BU 2455 typedef struct 2456 { 2457 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2458 uint8_t bit0 : 1; 2459 uint8_t bit1 : 1; 2460 uint8_t bit2 : 1; 2461 uint8_t bit3 : 1; 2462 uint8_t bit4 : 1; 2463 uint8_t bit5 : 1; 2464 uint8_t bit6 : 1; 2465 uint8_t bit7 : 1; 2466 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2467 uint8_t bit7 : 1; 2468 uint8_t bit6 : 1; 2469 uint8_t bit5 : 1; 2470 uint8_t bit4 : 1; 2471 uint8_t bit3 : 1; 2472 uint8_t bit2 : 1; 2473 uint8_t bit1 : 1; 2474 uint8_t bit0 : 1; 2475 #endif /* DRV_BYTE_ORDER */ 2476 } lsm6dsox_sensor_hub_10_t; 2477 2478 #define LSM6DSOX_SENSOR_HUB_11 0x0CU 2479 typedef struct 2480 { 2481 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2482 uint8_t bit0 : 1; 2483 uint8_t bit1 : 1; 2484 uint8_t bit2 : 1; 2485 uint8_t bit3 : 1; 2486 uint8_t bit4 : 1; 2487 uint8_t bit5 : 1; 2488 uint8_t bit6 : 1; 2489 uint8_t bit7 : 1; 2490 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2491 uint8_t bit7 : 1; 2492 uint8_t bit6 : 1; 2493 uint8_t bit5 : 1; 2494 uint8_t bit4 : 1; 2495 uint8_t bit3 : 1; 2496 uint8_t bit2 : 1; 2497 uint8_t bit1 : 1; 2498 uint8_t bit0 : 1; 2499 #endif /* DRV_BYTE_ORDER */ 2500 } lsm6dsox_sensor_hub_11_t; 2501 2502 #define LSM6DSOX_SENSOR_HUB_12 0x0DU 2503 typedef struct 2504 { 2505 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2506 uint8_t bit0 : 1; 2507 uint8_t bit1 : 1; 2508 uint8_t bit2 : 1; 2509 uint8_t bit3 : 1; 2510 uint8_t bit4 : 1; 2511 uint8_t bit5 : 1; 2512 uint8_t bit6 : 1; 2513 uint8_t bit7 : 1; 2514 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2515 uint8_t bit7 : 1; 2516 uint8_t bit6 : 1; 2517 uint8_t bit5 : 1; 2518 uint8_t bit4 : 1; 2519 uint8_t bit3 : 1; 2520 uint8_t bit2 : 1; 2521 uint8_t bit1 : 1; 2522 uint8_t bit0 : 1; 2523 #endif /* DRV_BYTE_ORDER */ 2524 } lsm6dsox_sensor_hub_12_t; 2525 2526 #define LSM6DSOX_SENSOR_HUB_13 0x0EU 2527 typedef struct 2528 { 2529 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2530 uint8_t bit0 : 1; 2531 uint8_t bit1 : 1; 2532 uint8_t bit2 : 1; 2533 uint8_t bit3 : 1; 2534 uint8_t bit4 : 1; 2535 uint8_t bit5 : 1; 2536 uint8_t bit6 : 1; 2537 uint8_t bit7 : 1; 2538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2539 uint8_t bit7 : 1; 2540 uint8_t bit6 : 1; 2541 uint8_t bit5 : 1; 2542 uint8_t bit4 : 1; 2543 uint8_t bit3 : 1; 2544 uint8_t bit2 : 1; 2545 uint8_t bit1 : 1; 2546 uint8_t bit0 : 1; 2547 #endif /* DRV_BYTE_ORDER */ 2548 } lsm6dsox_sensor_hub_13_t; 2549 2550 #define LSM6DSOX_SENSOR_HUB_14 0x0FU 2551 typedef struct 2552 { 2553 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2554 uint8_t bit0 : 1; 2555 uint8_t bit1 : 1; 2556 uint8_t bit2 : 1; 2557 uint8_t bit3 : 1; 2558 uint8_t bit4 : 1; 2559 uint8_t bit5 : 1; 2560 uint8_t bit6 : 1; 2561 uint8_t bit7 : 1; 2562 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2563 uint8_t bit7 : 1; 2564 uint8_t bit6 : 1; 2565 uint8_t bit5 : 1; 2566 uint8_t bit4 : 1; 2567 uint8_t bit3 : 1; 2568 uint8_t bit2 : 1; 2569 uint8_t bit1 : 1; 2570 uint8_t bit0 : 1; 2571 #endif /* DRV_BYTE_ORDER */ 2572 } lsm6dsox_sensor_hub_14_t; 2573 2574 #define LSM6DSOX_SENSOR_HUB_15 0x10U 2575 typedef struct 2576 { 2577 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2578 uint8_t bit0 : 1; 2579 uint8_t bit1 : 1; 2580 uint8_t bit2 : 1; 2581 uint8_t bit3 : 1; 2582 uint8_t bit4 : 1; 2583 uint8_t bit5 : 1; 2584 uint8_t bit6 : 1; 2585 uint8_t bit7 : 1; 2586 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2587 uint8_t bit7 : 1; 2588 uint8_t bit6 : 1; 2589 uint8_t bit5 : 1; 2590 uint8_t bit4 : 1; 2591 uint8_t bit3 : 1; 2592 uint8_t bit2 : 1; 2593 uint8_t bit1 : 1; 2594 uint8_t bit0 : 1; 2595 #endif /* DRV_BYTE_ORDER */ 2596 } lsm6dsox_sensor_hub_15_t; 2597 2598 #define LSM6DSOX_SENSOR_HUB_16 0x11U 2599 typedef struct 2600 { 2601 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2602 uint8_t bit0 : 1; 2603 uint8_t bit1 : 1; 2604 uint8_t bit2 : 1; 2605 uint8_t bit3 : 1; 2606 uint8_t bit4 : 1; 2607 uint8_t bit5 : 1; 2608 uint8_t bit6 : 1; 2609 uint8_t bit7 : 1; 2610 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2611 uint8_t bit7 : 1; 2612 uint8_t bit6 : 1; 2613 uint8_t bit5 : 1; 2614 uint8_t bit4 : 1; 2615 uint8_t bit3 : 1; 2616 uint8_t bit2 : 1; 2617 uint8_t bit1 : 1; 2618 uint8_t bit0 : 1; 2619 #endif /* DRV_BYTE_ORDER */ 2620 } lsm6dsox_sensor_hub_16_t; 2621 2622 #define LSM6DSOX_SENSOR_HUB_17 0x12U 2623 typedef struct 2624 { 2625 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2626 uint8_t bit0 : 1; 2627 uint8_t bit1 : 1; 2628 uint8_t bit2 : 1; 2629 uint8_t bit3 : 1; 2630 uint8_t bit4 : 1; 2631 uint8_t bit5 : 1; 2632 uint8_t bit6 : 1; 2633 uint8_t bit7 : 1; 2634 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2635 uint8_t bit7 : 1; 2636 uint8_t bit6 : 1; 2637 uint8_t bit5 : 1; 2638 uint8_t bit4 : 1; 2639 uint8_t bit3 : 1; 2640 uint8_t bit2 : 1; 2641 uint8_t bit1 : 1; 2642 uint8_t bit0 : 1; 2643 #endif /* DRV_BYTE_ORDER */ 2644 } lsm6dsox_sensor_hub_17_t; 2645 2646 #define LSM6DSOX_SENSOR_HUB_18 0x13U 2647 typedef struct 2648 { 2649 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2650 uint8_t bit0 : 1; 2651 uint8_t bit1 : 1; 2652 uint8_t bit2 : 1; 2653 uint8_t bit3 : 1; 2654 uint8_t bit4 : 1; 2655 uint8_t bit5 : 1; 2656 uint8_t bit6 : 1; 2657 uint8_t bit7 : 1; 2658 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2659 uint8_t bit7 : 1; 2660 uint8_t bit6 : 1; 2661 uint8_t bit5 : 1; 2662 uint8_t bit4 : 1; 2663 uint8_t bit3 : 1; 2664 uint8_t bit2 : 1; 2665 uint8_t bit1 : 1; 2666 uint8_t bit0 : 1; 2667 #endif /* DRV_BYTE_ORDER */ 2668 } lsm6dsox_sensor_hub_18_t; 2669 2670 #define LSM6DSOX_MASTER_CONFIG 0x14U 2671 typedef struct 2672 { 2673 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2674 uint8_t aux_sens_on : 2; 2675 uint8_t master_on : 1; 2676 uint8_t shub_pu_en : 1; 2677 uint8_t pass_through_mode : 1; 2678 uint8_t start_config : 1; 2679 uint8_t write_once : 1; 2680 uint8_t rst_master_regs : 1; 2681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2682 uint8_t rst_master_regs : 1; 2683 uint8_t write_once : 1; 2684 uint8_t start_config : 1; 2685 uint8_t pass_through_mode : 1; 2686 uint8_t shub_pu_en : 1; 2687 uint8_t master_on : 1; 2688 uint8_t aux_sens_on : 2; 2689 #endif /* DRV_BYTE_ORDER */ 2690 } lsm6dsox_master_config_t; 2691 2692 #define LSM6DSOX_SLV0_ADD 0x15U 2693 typedef struct 2694 { 2695 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2696 uint8_t rw_0 : 1; 2697 uint8_t slave0 : 7; 2698 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2699 uint8_t slave0 : 7; 2700 uint8_t rw_0 : 1; 2701 #endif /* DRV_BYTE_ORDER */ 2702 } lsm6dsox_slv0_add_t; 2703 2704 #define LSM6DSOX_SLV0_SUBADD 0x16U 2705 typedef struct 2706 { 2707 uint8_t slave0_reg : 8; 2708 } lsm6dsox_slv0_subadd_t; 2709 2710 #define LSM6DSOX_SLV0_CONFIG 0x17U 2711 typedef struct 2712 { 2713 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2714 uint8_t slave0_numop : 3; 2715 uint8_t batch_ext_sens_0_en : 1; 2716 uint8_t not_used_01 : 2; 2717 uint8_t shub_odr : 2; 2718 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2719 uint8_t shub_odr : 2; 2720 uint8_t not_used_01 : 2; 2721 uint8_t batch_ext_sens_0_en : 1; 2722 uint8_t slave0_numop : 3; 2723 #endif /* DRV_BYTE_ORDER */ 2724 } lsm6dsox_slv0_config_t; 2725 2726 #define LSM6DSOX_SLV1_ADD 0x18U 2727 typedef struct 2728 { 2729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2730 uint8_t r_1 : 1; 2731 uint8_t slave1_add : 7; 2732 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2733 uint8_t slave1_add : 7; 2734 uint8_t r_1 : 1; 2735 #endif /* DRV_BYTE_ORDER */ 2736 } lsm6dsox_slv1_add_t; 2737 2738 #define LSM6DSOX_SLV1_SUBADD 0x19U 2739 typedef struct 2740 { 2741 uint8_t slave1_reg : 8; 2742 } lsm6dsox_slv1_subadd_t; 2743 2744 #define LSM6DSOX_SLV1_CONFIG 0x1AU 2745 typedef struct 2746 { 2747 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2748 uint8_t slave1_numop : 3; 2749 uint8_t batch_ext_sens_1_en : 1; 2750 uint8_t not_used_01 : 4; 2751 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2752 uint8_t not_used_01 : 4; 2753 uint8_t batch_ext_sens_1_en : 1; 2754 uint8_t slave1_numop : 3; 2755 #endif /* DRV_BYTE_ORDER */ 2756 } lsm6dsox_slv1_config_t; 2757 2758 #define LSM6DSOX_SLV2_ADD 0x1BU 2759 typedef struct 2760 { 2761 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2762 uint8_t r_2 : 1; 2763 uint8_t slave2_add : 7; 2764 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2765 uint8_t slave2_add : 7; 2766 uint8_t r_2 : 1; 2767 #endif /* DRV_BYTE_ORDER */ 2768 } lsm6dsox_slv2_add_t; 2769 2770 #define LSM6DSOX_SLV2_SUBADD 0x1CU 2771 typedef struct 2772 { 2773 uint8_t slave2_reg : 8; 2774 } lsm6dsox_slv2_subadd_t; 2775 2776 #define LSM6DSOX_SLV2_CONFIG 0x1DU 2777 typedef struct 2778 { 2779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2780 uint8_t slave2_numop : 3; 2781 uint8_t batch_ext_sens_2_en : 1; 2782 uint8_t not_used_01 : 4; 2783 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2784 uint8_t not_used_01 : 4; 2785 uint8_t batch_ext_sens_2_en : 1; 2786 uint8_t slave2_numop : 3; 2787 #endif /* DRV_BYTE_ORDER */ 2788 } lsm6dsox_slv2_config_t; 2789 2790 #define LSM6DSOX_SLV3_ADD 0x1EU 2791 typedef struct 2792 { 2793 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2794 uint8_t r_3 : 1; 2795 uint8_t slave3_add : 7; 2796 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2797 uint8_t slave3_add : 7; 2798 uint8_t r_3 : 1; 2799 #endif /* DRV_BYTE_ORDER */ 2800 } lsm6dsox_slv3_add_t; 2801 2802 #define LSM6DSOX_SLV3_SUBADD 0x1FU 2803 typedef struct 2804 { 2805 uint8_t slave3_reg : 8; 2806 } lsm6dsox_slv3_subadd_t; 2807 2808 #define LSM6DSOX_SLV3_CONFIG 0x20U 2809 typedef struct 2810 { 2811 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2812 uint8_t slave3_numop : 3; 2813 uint8_t batch_ext_sens_3_en : 1; 2814 uint8_t not_used_01 : 4; 2815 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2816 uint8_t not_used_01 : 4; 2817 uint8_t batch_ext_sens_3_en : 1; 2818 uint8_t slave3_numop : 3; 2819 #endif /* DRV_BYTE_ORDER */ 2820 } lsm6dsox_slv3_config_t; 2821 2822 #define LSM6DSOX_DATAWRITE_SLV0 0x21U 2823 typedef struct 2824 { 2825 uint8_t slave0_dataw : 8; 2826 } lsm6dsox_datawrite_slv0_t; 2827 2828 #define LSM6DSOX_STATUS_MASTER 0x22U 2829 typedef struct 2830 { 2831 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2832 uint8_t sens_hub_endop : 1; 2833 uint8_t not_used_01 : 2; 2834 uint8_t slave0_nack : 1; 2835 uint8_t slave1_nack : 1; 2836 uint8_t slave2_nack : 1; 2837 uint8_t slave3_nack : 1; 2838 uint8_t wr_once_done : 1; 2839 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2840 uint8_t wr_once_done : 1; 2841 uint8_t slave3_nack : 1; 2842 uint8_t slave2_nack : 1; 2843 uint8_t slave1_nack : 1; 2844 uint8_t slave0_nack : 1; 2845 uint8_t not_used_01 : 2; 2846 uint8_t sens_hub_endop : 1; 2847 #endif /* DRV_BYTE_ORDER */ 2848 } lsm6dsox_status_master_t; 2849 2850 #define LSM6DSOX_START_FSM_ADD 0x0400U 2851 2852 /** 2853 * @defgroup LSM6DSOX_Register_Union 2854 * @brief This union group all the registers having a bit-field 2855 * description. 2856 * This union is useful but it's not needed by the driver. 2857 * 2858 * REMOVING this union you are compliant with: 2859 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2860 * 2861 * @{ 2862 * 2863 */ 2864 typedef union 2865 { 2866 lsm6dsox_func_cfg_access_t func_cfg_access; 2867 lsm6dsox_pin_ctrl_t pin_ctrl; 2868 lsm6dsox_s4s_tph_l_t s4s_tph_l; 2869 lsm6dsox_s4s_tph_h_t s4s_tph_h; 2870 lsm6dsox_s4s_rr_t s4s_rr; 2871 lsm6dsox_fifo_ctrl1_t fifo_ctrl1; 2872 lsm6dsox_fifo_ctrl2_t fifo_ctrl2; 2873 lsm6dsox_fifo_ctrl3_t fifo_ctrl3; 2874 lsm6dsox_fifo_ctrl4_t fifo_ctrl4; 2875 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1; 2876 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2; 2877 lsm6dsox_int1_ctrl_t int1_ctrl; 2878 lsm6dsox_int2_ctrl_t int2_ctrl; 2879 lsm6dsox_ctrl1_xl_t ctrl1_xl; 2880 lsm6dsox_ctrl2_g_t ctrl2_g; 2881 lsm6dsox_ctrl3_c_t ctrl3_c; 2882 lsm6dsox_ctrl4_c_t ctrl4_c; 2883 lsm6dsox_ctrl5_c_t ctrl5_c; 2884 lsm6dsox_ctrl6_c_t ctrl6_c; 2885 lsm6dsox_ctrl7_g_t ctrl7_g; 2886 lsm6dsox_ctrl8_xl_t ctrl8_xl; 2887 lsm6dsox_ctrl9_xl_t ctrl9_xl; 2888 lsm6dsox_ctrl10_c_t ctrl10_c; 2889 lsm6dsox_all_int_src_t all_int_src; 2890 lsm6dsox_wake_up_src_t wake_up_src; 2891 lsm6dsox_tap_src_t tap_src; 2892 lsm6dsox_d6d_src_t d6d_src; 2893 lsm6dsox_status_reg_t status_reg; 2894 lsm6dsox_fifo_status1_t fifo_status1; 2895 lsm6dsox_fifo_status2_t fifo_status2; 2896 lsm6dsox_ui_status_reg_ois_t ui_status_reg_ois; 2897 lsm6dsox_tap_cfg0_t tap_cfg0; 2898 lsm6dsox_tap_cfg1_t tap_cfg1; 2899 lsm6dsox_tap_cfg2_t tap_cfg2; 2900 lsm6dsox_tap_ths_6d_t tap_ths_6d; 2901 lsm6dsox_int_dur2_t int_dur2; 2902 lsm6dsox_wake_up_ths_t wake_up_ths; 2903 lsm6dsox_wake_up_dur_t wake_up_dur; 2904 lsm6dsox_free_fall_t free_fall; 2905 lsm6dsox_md1_cfg_t md1_cfg; 2906 lsm6dsox_md2_cfg_t md2_cfg; 2907 lsm6dsox_s4s_st_cmd_code_t s4s_st_cmd_code; 2908 lsm6dsox_s4s_dt_reg_t s4s_dt_reg; 2909 lsm6dsox_i3c_bus_avb_t i3c_bus_avb; 2910 lsm6dsox_internal_freq_fine_t internal_freq_fine; 2911 lsm6dsox_ui_int_ois_t ui_int_ois; 2912 lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois; 2913 lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois; 2914 lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois; 2915 lsm6dsox_fifo_data_out_tag_t fifo_data_out_tag; 2916 lsm6dsox_spi2_status_reg_ois_t spi2_status_reg_ois; 2917 lsm6dsox_spi2_int_ois_t spi2_int_ois; 2918 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois; 2919 lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois; 2920 lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois; 2921 lsm6dsox_page_sel_t page_sel; 2922 lsm6dsox_emb_func_en_a_t emb_func_en_a; 2923 lsm6dsox_emb_func_en_b_t emb_func_en_b; 2924 lsm6dsox_page_address_t page_address; 2925 lsm6dsox_page_value_t page_value; 2926 lsm6dsox_emb_func_int1_t emb_func_int1; 2927 lsm6dsox_fsm_int1_a_t fsm_int1_a; 2928 lsm6dsox_fsm_int1_b_t fsm_int1_b; 2929 lsm6dsox_emb_func_int2_t emb_func_int2; 2930 lsm6dsox_fsm_int2_a_t fsm_int2_a; 2931 lsm6dsox_fsm_int2_b_t fsm_int2_b; 2932 lsm6dsox_emb_func_status_t emb_func_status; 2933 lsm6dsox_fsm_status_a_t fsm_status_a; 2934 lsm6dsox_fsm_status_b_t fsm_status_b; 2935 lsm6dsox_page_rw_t page_rw; 2936 lsm6dsox_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2937 lsm6dsox_fsm_enable_a_t fsm_enable_a; 2938 lsm6dsox_fsm_enable_b_t fsm_enable_b; 2939 lsm6dsox_fsm_long_counter_clear_t fsm_long_counter_clear; 2940 lsm6dsox_fsm_outs1_t fsm_outs1; 2941 lsm6dsox_fsm_outs2_t fsm_outs2; 2942 lsm6dsox_fsm_outs3_t fsm_outs3; 2943 lsm6dsox_fsm_outs4_t fsm_outs4; 2944 lsm6dsox_fsm_outs5_t fsm_outs5; 2945 lsm6dsox_fsm_outs6_t fsm_outs6; 2946 lsm6dsox_fsm_outs7_t fsm_outs7; 2947 lsm6dsox_fsm_outs8_t fsm_outs8; 2948 lsm6dsox_fsm_outs9_t fsm_outs9; 2949 lsm6dsox_fsm_outs10_t fsm_outs10; 2950 lsm6dsox_fsm_outs11_t fsm_outs11; 2951 lsm6dsox_fsm_outs12_t fsm_outs12; 2952 lsm6dsox_fsm_outs13_t fsm_outs13; 2953 lsm6dsox_fsm_outs14_t fsm_outs14; 2954 lsm6dsox_fsm_outs15_t fsm_outs15; 2955 lsm6dsox_fsm_outs16_t fsm_outs16; 2956 lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2957 lsm6dsox_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 2958 lsm6dsox_emb_func_src_t emb_func_src; 2959 lsm6dsox_emb_func_init_a_t emb_func_init_a; 2960 lsm6dsox_emb_func_init_b_t emb_func_init_b; 2961 lsm6dsox_mag_cfg_a_t mag_cfg_a; 2962 lsm6dsox_mag_cfg_b_t mag_cfg_b; 2963 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg; 2964 lsm6dsox_sensor_hub_1_t sensor_hub_1; 2965 lsm6dsox_sensor_hub_2_t sensor_hub_2; 2966 lsm6dsox_sensor_hub_3_t sensor_hub_3; 2967 lsm6dsox_sensor_hub_4_t sensor_hub_4; 2968 lsm6dsox_sensor_hub_5_t sensor_hub_5; 2969 lsm6dsox_sensor_hub_6_t sensor_hub_6; 2970 lsm6dsox_sensor_hub_7_t sensor_hub_7; 2971 lsm6dsox_sensor_hub_8_t sensor_hub_8; 2972 lsm6dsox_sensor_hub_9_t sensor_hub_9; 2973 lsm6dsox_sensor_hub_10_t sensor_hub_10; 2974 lsm6dsox_sensor_hub_11_t sensor_hub_11; 2975 lsm6dsox_sensor_hub_12_t sensor_hub_12; 2976 lsm6dsox_sensor_hub_13_t sensor_hub_13; 2977 lsm6dsox_sensor_hub_14_t sensor_hub_14; 2978 lsm6dsox_sensor_hub_15_t sensor_hub_15; 2979 lsm6dsox_sensor_hub_16_t sensor_hub_16; 2980 lsm6dsox_sensor_hub_17_t sensor_hub_17; 2981 lsm6dsox_sensor_hub_18_t sensor_hub_18; 2982 lsm6dsox_master_config_t master_config; 2983 lsm6dsox_slv0_add_t slv0_add; 2984 lsm6dsox_slv0_subadd_t slv0_subadd; 2985 lsm6dsox_slv0_config_t slv0_config; 2986 lsm6dsox_slv1_add_t slv1_add; 2987 lsm6dsox_slv1_subadd_t slv1_subadd; 2988 lsm6dsox_slv1_config_t slv1_config; 2989 lsm6dsox_slv2_add_t slv2_add; 2990 lsm6dsox_slv2_subadd_t slv2_subadd; 2991 lsm6dsox_slv2_config_t slv2_config; 2992 lsm6dsox_slv3_add_t slv3_add; 2993 lsm6dsox_slv3_subadd_t slv3_subadd; 2994 lsm6dsox_slv3_config_t slv3_config; 2995 lsm6dsox_datawrite_slv0_t datawrite_slv0; 2996 lsm6dsox_status_master_t status_master; 2997 bitwise_t bitwise; 2998 uint8_t byte; 2999 } lsm6dsox_reg_t; 3000 3001 /** 3002 * @} 3003 * 3004 */ 3005 3006 #ifndef __weak 3007 #define __weak __attribute__((weak)) 3008 #endif /* __weak */ 3009 3010 /* 3011 * These are the basic platform dependent I/O routines to read 3012 * and write device registers connected on a standard bus. 3013 * The driver keeps offering a default implementation based on function 3014 * pointers to read/write routines for backward compatibility. 3015 * The __weak directive allows the final application to overwrite 3016 * them with a custom implementation. 3017 */ 3018 3019 int32_t lsm6dsox_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 3020 uint8_t *data, 3021 uint16_t len); 3022 int32_t lsm6dsox_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 3023 uint8_t *data, 3024 uint16_t len); 3025 3026 float_t lsm6dsox_from_fs2_to_mg(int16_t lsb); 3027 float_t lsm6dsox_from_fs4_to_mg(int16_t lsb); 3028 float_t lsm6dsox_from_fs8_to_mg(int16_t lsb); 3029 float_t lsm6dsox_from_fs16_to_mg(int16_t lsb); 3030 3031 float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb); 3032 float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb); 3033 float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb); 3034 float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb); 3035 float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb); 3036 3037 float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb); 3038 3039 float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb); 3040 3041 typedef enum 3042 { 3043 LSM6DSOX_2g = 0, 3044 LSM6DSOX_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSOX_2g */ 3045 LSM6DSOX_4g = 2, 3046 LSM6DSOX_8g = 3, 3047 } lsm6dsox_fs_xl_t; 3048 int32_t lsm6dsox_xl_full_scale_set(const stmdev_ctx_t *ctx, 3049 lsm6dsox_fs_xl_t val); 3050 int32_t lsm6dsox_xl_full_scale_get(const stmdev_ctx_t *ctx, 3051 lsm6dsox_fs_xl_t *val); 3052 3053 typedef enum 3054 { 3055 LSM6DSOX_XL_ODR_OFF = 0, 3056 LSM6DSOX_XL_ODR_12Hz5 = 1, 3057 LSM6DSOX_XL_ODR_26Hz = 2, 3058 LSM6DSOX_XL_ODR_52Hz = 3, 3059 LSM6DSOX_XL_ODR_104Hz = 4, 3060 LSM6DSOX_XL_ODR_208Hz = 5, 3061 LSM6DSOX_XL_ODR_417Hz = 6, 3062 LSM6DSOX_XL_ODR_833Hz = 7, 3063 LSM6DSOX_XL_ODR_1667Hz = 8, 3064 LSM6DSOX_XL_ODR_3333Hz = 9, 3065 LSM6DSOX_XL_ODR_6667Hz = 10, 3066 LSM6DSOX_XL_ODR_1Hz6 = 11, /* (low power only) */ 3067 } lsm6dsox_odr_xl_t; 3068 int32_t lsm6dsox_xl_data_rate_set(const stmdev_ctx_t *ctx, 3069 lsm6dsox_odr_xl_t val); 3070 int32_t lsm6dsox_xl_data_rate_get(const stmdev_ctx_t *ctx, 3071 lsm6dsox_odr_xl_t *val); 3072 3073 typedef enum 3074 { 3075 LSM6DSOX_250dps = 0, 3076 LSM6DSOX_125dps = 1, 3077 LSM6DSOX_500dps = 2, 3078 LSM6DSOX_1000dps = 4, 3079 LSM6DSOX_2000dps = 6, 3080 } lsm6dsox_fs_g_t; 3081 int32_t lsm6dsox_gy_full_scale_set(const stmdev_ctx_t *ctx, 3082 lsm6dsox_fs_g_t val); 3083 int32_t lsm6dsox_gy_full_scale_get(const stmdev_ctx_t *ctx, 3084 lsm6dsox_fs_g_t *val); 3085 3086 typedef enum 3087 { 3088 LSM6DSOX_GY_ODR_OFF = 0, 3089 LSM6DSOX_GY_ODR_12Hz5 = 1, 3090 LSM6DSOX_GY_ODR_26Hz = 2, 3091 LSM6DSOX_GY_ODR_52Hz = 3, 3092 LSM6DSOX_GY_ODR_104Hz = 4, 3093 LSM6DSOX_GY_ODR_208Hz = 5, 3094 LSM6DSOX_GY_ODR_417Hz = 6, 3095 LSM6DSOX_GY_ODR_833Hz = 7, 3096 LSM6DSOX_GY_ODR_1667Hz = 8, 3097 LSM6DSOX_GY_ODR_3333Hz = 9, 3098 LSM6DSOX_GY_ODR_6667Hz = 10, 3099 } lsm6dsox_odr_g_t; 3100 int32_t lsm6dsox_gy_data_rate_set(const stmdev_ctx_t *ctx, 3101 lsm6dsox_odr_g_t val); 3102 int32_t lsm6dsox_gy_data_rate_get(const stmdev_ctx_t *ctx, 3103 lsm6dsox_odr_g_t *val); 3104 3105 int32_t lsm6dsox_block_data_update_set(const stmdev_ctx_t *ctx, 3106 uint8_t val); 3107 int32_t lsm6dsox_block_data_update_get(const stmdev_ctx_t *ctx, 3108 uint8_t *val); 3109 3110 typedef enum 3111 { 3112 LSM6DSOX_LSb_1mg = 0, 3113 LSM6DSOX_LSb_16mg = 1, 3114 } lsm6dsox_usr_off_w_t; 3115 int32_t lsm6dsox_xl_offset_weight_set(const stmdev_ctx_t *ctx, 3116 lsm6dsox_usr_off_w_t val); 3117 int32_t lsm6dsox_xl_offset_weight_get(const stmdev_ctx_t *ctx, 3118 lsm6dsox_usr_off_w_t *val); 3119 3120 typedef enum 3121 { 3122 LSM6DSOX_HIGH_PERFORMANCE_MD = 0, 3123 LSM6DSOX_LOW_NORMAL_POWER_MD = 1, 3124 LSM6DSOX_ULTRA_LOW_POWER_MD = 2, 3125 } lsm6dsox_xl_hm_mode_t; 3126 int32_t lsm6dsox_xl_power_mode_set(const stmdev_ctx_t *ctx, 3127 lsm6dsox_xl_hm_mode_t val); 3128 int32_t lsm6dsox_xl_power_mode_get(const stmdev_ctx_t *ctx, 3129 lsm6dsox_xl_hm_mode_t *val); 3130 3131 typedef enum 3132 { 3133 LSM6DSOX_GY_HIGH_PERFORMANCE = 0, 3134 LSM6DSOX_GY_NORMAL = 1, 3135 } lsm6dsox_g_hm_mode_t; 3136 int32_t lsm6dsox_gy_power_mode_set(const stmdev_ctx_t *ctx, 3137 lsm6dsox_g_hm_mode_t val); 3138 int32_t lsm6dsox_gy_power_mode_get(const stmdev_ctx_t *ctx, 3139 lsm6dsox_g_hm_mode_t *val); 3140 3141 int32_t lsm6dsox_status_reg_get(const stmdev_ctx_t *ctx, 3142 lsm6dsox_status_reg_t *val); 3143 3144 int32_t lsm6dsox_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 3145 uint8_t *val); 3146 3147 int32_t lsm6dsox_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 3148 uint8_t *val); 3149 3150 int32_t lsm6dsox_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 3151 uint8_t *val); 3152 3153 int32_t lsm6dsox_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, 3154 uint8_t *buff); 3155 int32_t lsm6dsox_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, 3156 uint8_t *buff); 3157 3158 int32_t lsm6dsox_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, 3159 uint8_t *buff); 3160 int32_t lsm6dsox_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, 3161 uint8_t *buff); 3162 3163 int32_t lsm6dsox_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, 3164 uint8_t *buff); 3165 int32_t lsm6dsox_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, 3166 uint8_t *buff); 3167 3168 int32_t lsm6dsox_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 3169 int32_t lsm6dsox_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3170 3171 int32_t lsm6dsox_timestamp_rst(const stmdev_ctx_t *ctx); 3172 3173 int32_t lsm6dsox_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 3174 int32_t lsm6dsox_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 3175 3176 int32_t lsm6dsox_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 3177 3178 typedef enum 3179 { 3180 LSM6DSOX_NO_ROUND = 0, 3181 LSM6DSOX_ROUND_XL = 1, 3182 LSM6DSOX_ROUND_GY = 2, 3183 LSM6DSOX_ROUND_GY_XL = 3, 3184 } lsm6dsox_rounding_t; 3185 int32_t lsm6dsox_rounding_mode_set(const stmdev_ctx_t *ctx, 3186 lsm6dsox_rounding_t val); 3187 int32_t lsm6dsox_rounding_mode_get(const stmdev_ctx_t *ctx, 3188 lsm6dsox_rounding_t *val); 3189 3190 typedef enum 3191 { 3192 LSM6DSOX_STAT_RND_DISABLE = 0, 3193 LSM6DSOX_STAT_RND_ENABLE = 1, 3194 } lsm6dsox_rounding_status_t; 3195 int32_t lsm6dsox_rounding_on_status_set(const stmdev_ctx_t *ctx, 3196 lsm6dsox_rounding_status_t val); 3197 int32_t lsm6dsox_rounding_on_status_get(const stmdev_ctx_t *ctx, 3198 lsm6dsox_rounding_status_t *val); 3199 3200 int32_t lsm6dsox_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 3201 3202 int32_t lsm6dsox_angular_rate_raw_get(const stmdev_ctx_t *ctx, 3203 int16_t *val); 3204 3205 int32_t lsm6dsox_acceleration_raw_get(const stmdev_ctx_t *ctx, 3206 int16_t *val); 3207 3208 int32_t lsm6dsox_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 3209 3210 int32_t lsm6dsox_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, 3211 int16_t *val); 3212 3213 int32_t lsm6dsox_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, 3214 int16_t *val); 3215 3216 int32_t lsm6dsox_aux_temperature_raw_get(const stmdev_ctx_t *ctx, 3217 int16_t *val); 3218 3219 int32_t lsm6dsox_aux_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, 3220 int16_t *val); 3221 3222 int32_t lsm6dsox_aux_ois_acceleration_raw_get(const stmdev_ctx_t *ctx, 3223 int16_t *val); 3224 3225 int32_t lsm6dsox_number_of_steps_get(const stmdev_ctx_t *ctx, 3226 uint16_t *val); 3227 3228 int32_t lsm6dsox_steps_reset(const stmdev_ctx_t *ctx); 3229 3230 int32_t lsm6dsox_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 3231 3232 int32_t lsm6dsox_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 3233 int32_t lsm6dsox_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 3234 3235 typedef enum 3236 { 3237 LSM6DSOX_USER_BANK = 0, 3238 LSM6DSOX_SENSOR_HUB_BANK = 1, 3239 LSM6DSOX_EMBEDDED_FUNC_BANK = 2, 3240 } lsm6dsox_reg_access_t; 3241 int32_t lsm6dsox_mem_bank_set(const stmdev_ctx_t *ctx, 3242 lsm6dsox_reg_access_t val); 3243 int32_t lsm6dsox_mem_bank_get(const stmdev_ctx_t *ctx, 3244 lsm6dsox_reg_access_t *val); 3245 3246 int32_t lsm6dsox_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, 3247 uint8_t *val); 3248 int32_t lsm6dsox_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, 3249 uint8_t *val); 3250 3251 int32_t lsm6dsox_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 3252 uint8_t *buf, uint8_t len); 3253 int32_t lsm6dsox_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 3254 uint8_t *val); 3255 3256 typedef enum 3257 { 3258 LSM6DSOX_DRDY_LATCHED = 0, 3259 LSM6DSOX_DRDY_PULSED = 1, 3260 } lsm6dsox_dataready_pulsed_t; 3261 int32_t lsm6dsox_data_ready_mode_set(const stmdev_ctx_t *ctx, 3262 lsm6dsox_dataready_pulsed_t val); 3263 int32_t lsm6dsox_data_ready_mode_get(const stmdev_ctx_t *ctx, 3264 lsm6dsox_dataready_pulsed_t *val); 3265 3266 int32_t lsm6dsox_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 3267 3268 int32_t lsm6dsox_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 3269 int32_t lsm6dsox_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 3270 3271 int32_t lsm6dsox_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 3272 int32_t lsm6dsox_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 3273 3274 int32_t lsm6dsox_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 3275 int32_t lsm6dsox_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 3276 3277 typedef enum 3278 { 3279 LSM6DSOX_XL_ST_DISABLE = 0, 3280 LSM6DSOX_XL_ST_POSITIVE = 1, 3281 LSM6DSOX_XL_ST_NEGATIVE = 2, 3282 } lsm6dsox_st_xl_t; 3283 int32_t lsm6dsox_xl_self_test_set(const stmdev_ctx_t *ctx, 3284 lsm6dsox_st_xl_t val); 3285 int32_t lsm6dsox_xl_self_test_get(const stmdev_ctx_t *ctx, 3286 lsm6dsox_st_xl_t *val); 3287 3288 typedef enum 3289 { 3290 LSM6DSOX_GY_ST_DISABLE = 0, 3291 LSM6DSOX_GY_ST_POSITIVE = 1, 3292 LSM6DSOX_GY_ST_NEGATIVE = 3, 3293 } lsm6dsox_st_g_t; 3294 int32_t lsm6dsox_gy_self_test_set(const stmdev_ctx_t *ctx, 3295 lsm6dsox_st_g_t val); 3296 int32_t lsm6dsox_gy_self_test_get(const stmdev_ctx_t *ctx, 3297 lsm6dsox_st_g_t *val); 3298 3299 int32_t lsm6dsox_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 3300 int32_t lsm6dsox_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 3301 3302 int32_t lsm6dsox_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 3303 int32_t lsm6dsox_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3304 3305 int32_t lsm6dsox_filter_settling_mask_set(const stmdev_ctx_t *ctx, 3306 uint8_t val); 3307 int32_t lsm6dsox_filter_settling_mask_get(const stmdev_ctx_t *ctx, 3308 uint8_t *val); 3309 3310 typedef enum 3311 { 3312 LSM6DSOX_ULTRA_LIGHT = 0, 3313 LSM6DSOX_VERY_LIGHT = 1, 3314 LSM6DSOX_LIGHT = 2, 3315 LSM6DSOX_MEDIUM = 3, 3316 LSM6DSOX_STRONG = 4, 3317 LSM6DSOX_VERY_STRONG = 5, 3318 LSM6DSOX_AGGRESSIVE = 6, 3319 LSM6DSOX_XTREME = 7, 3320 } lsm6dsox_ftype_t; 3321 int32_t lsm6dsox_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3322 lsm6dsox_ftype_t val); 3323 int32_t lsm6dsox_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3324 lsm6dsox_ftype_t *val); 3325 3326 int32_t lsm6dsox_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 3327 int32_t lsm6dsox_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 3328 3329 typedef enum 3330 { 3331 LSM6DSOX_HP_PATH_DISABLE_ON_OUT = 0x00, 3332 LSM6DSOX_SLOPE_ODR_DIV_4 = 0x10, 3333 LSM6DSOX_HP_ODR_DIV_10 = 0x11, 3334 LSM6DSOX_HP_ODR_DIV_20 = 0x12, 3335 LSM6DSOX_HP_ODR_DIV_45 = 0x13, 3336 LSM6DSOX_HP_ODR_DIV_100 = 0x14, 3337 LSM6DSOX_HP_ODR_DIV_200 = 0x15, 3338 LSM6DSOX_HP_ODR_DIV_400 = 0x16, 3339 LSM6DSOX_HP_ODR_DIV_800 = 0x17, 3340 LSM6DSOX_HP_REF_MD_ODR_DIV_10 = 0x31, 3341 LSM6DSOX_HP_REF_MD_ODR_DIV_20 = 0x32, 3342 LSM6DSOX_HP_REF_MD_ODR_DIV_45 = 0x33, 3343 LSM6DSOX_HP_REF_MD_ODR_DIV_100 = 0x34, 3344 LSM6DSOX_HP_REF_MD_ODR_DIV_200 = 0x35, 3345 LSM6DSOX_HP_REF_MD_ODR_DIV_400 = 0x36, 3346 LSM6DSOX_HP_REF_MD_ODR_DIV_800 = 0x37, 3347 LSM6DSOX_LP_ODR_DIV_10 = 0x01, 3348 LSM6DSOX_LP_ODR_DIV_20 = 0x02, 3349 LSM6DSOX_LP_ODR_DIV_45 = 0x03, 3350 LSM6DSOX_LP_ODR_DIV_100 = 0x04, 3351 LSM6DSOX_LP_ODR_DIV_200 = 0x05, 3352 LSM6DSOX_LP_ODR_DIV_400 = 0x06, 3353 LSM6DSOX_LP_ODR_DIV_800 = 0x07, 3354 } lsm6dsox_hp_slope_xl_en_t; 3355 int32_t lsm6dsox_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 3356 lsm6dsox_hp_slope_xl_en_t val); 3357 int32_t lsm6dsox_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 3358 lsm6dsox_hp_slope_xl_en_t *val); 3359 3360 int32_t lsm6dsox_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 3361 int32_t lsm6dsox_xl_fast_settling_get(const stmdev_ctx_t *ctx, 3362 uint8_t *val); 3363 3364 typedef enum 3365 { 3366 LSM6DSOX_USE_SLOPE = 0, 3367 LSM6DSOX_USE_HPF = 1, 3368 } lsm6dsox_slope_fds_t; 3369 int32_t lsm6dsox_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 3370 lsm6dsox_slope_fds_t val); 3371 int32_t lsm6dsox_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 3372 lsm6dsox_slope_fds_t *val); 3373 3374 typedef enum 3375 { 3376 LSM6DSOX_HP_FILTER_NONE = 0x00, 3377 LSM6DSOX_HP_FILTER_16mHz = 0x80, 3378 LSM6DSOX_HP_FILTER_65mHz = 0x81, 3379 LSM6DSOX_HP_FILTER_260mHz = 0x82, 3380 LSM6DSOX_HP_FILTER_1Hz04 = 0x83, 3381 } lsm6dsox_hpm_g_t; 3382 int32_t lsm6dsox_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 3383 lsm6dsox_hpm_g_t val); 3384 int32_t lsm6dsox_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 3385 lsm6dsox_hpm_g_t *val); 3386 3387 typedef enum 3388 { 3389 LSM6DSOX_OIS_CTRL_AUX_DATA_UI = 0x00, 3390 LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX = 0x01, 3391 LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI = 0x02, 3392 LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX = 0x03, 3393 } lsm6dsox_spi2_read_en_t; 3394 int32_t lsm6dsox_ois_mode_set(const stmdev_ctx_t *ctx, 3395 lsm6dsox_spi2_read_en_t val); 3396 int32_t lsm6dsox_ois_mode_get(const stmdev_ctx_t *ctx, 3397 lsm6dsox_spi2_read_en_t *val); 3398 3399 typedef enum 3400 { 3401 LSM6DSOX_AUX_PULL_UP_DISC = 0, 3402 LSM6DSOX_AUX_PULL_UP_CONNECT = 1, 3403 } lsm6dsox_ois_pu_dis_t; 3404 int32_t lsm6dsox_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx, 3405 lsm6dsox_ois_pu_dis_t val); 3406 int32_t lsm6dsox_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx, 3407 lsm6dsox_ois_pu_dis_t *val); 3408 3409 typedef enum 3410 { 3411 LSM6DSOX_AUX_ON = 1, 3412 LSM6DSOX_AUX_ON_BY_AUX_INTERFACE = 0, 3413 } lsm6dsox_ois_on_t; 3414 int32_t lsm6dsox_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx, 3415 lsm6dsox_ois_on_t val); 3416 int32_t lsm6dsox_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx, 3417 lsm6dsox_ois_on_t *val); 3418 3419 typedef enum 3420 { 3421 LSM6DSOX_USE_SAME_XL_FS = 0, 3422 LSM6DSOX_USE_DIFFERENT_XL_FS = 1, 3423 } lsm6dsox_xl_fs_mode_t; 3424 int32_t lsm6dsox_aux_xl_fs_mode_set(const stmdev_ctx_t *ctx, 3425 lsm6dsox_xl_fs_mode_t val); 3426 int32_t lsm6dsox_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx, 3427 lsm6dsox_xl_fs_mode_t *val); 3428 3429 int32_t lsm6dsox_aux_status_reg_get(const stmdev_ctx_t *ctx, 3430 lsm6dsox_spi2_status_reg_ois_t *val); 3431 3432 int32_t lsm6dsox_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 3433 uint8_t *val); 3434 3435 int32_t lsm6dsox_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 3436 uint8_t *val); 3437 3438 int32_t lsm6dsox_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, 3439 uint8_t *val); 3440 3441 typedef enum 3442 { 3443 LSM6DSOX_AUX_DEN_ACTIVE_LOW = 0, 3444 LSM6DSOX_AUX_DEN_ACTIVE_HIGH = 1, 3445 } lsm6dsox_den_lh_ois_t; 3446 int32_t lsm6dsox_aux_den_polarity_set(const stmdev_ctx_t *ctx, 3447 lsm6dsox_den_lh_ois_t val); 3448 int32_t lsm6dsox_aux_den_polarity_get(const stmdev_ctx_t *ctx, 3449 lsm6dsox_den_lh_ois_t *val); 3450 3451 typedef enum 3452 { 3453 LSM6DSOX_AUX_DEN_DISABLE = 0, 3454 LSM6DSOX_AUX_DEN_LEVEL_LATCH = 3, 3455 LSM6DSOX_AUX_DEN_LEVEL_TRIG = 2, 3456 } lsm6dsox_lvl2_ois_t; 3457 int32_t lsm6dsox_aux_den_mode_set(const stmdev_ctx_t *ctx, 3458 lsm6dsox_lvl2_ois_t val); 3459 int32_t lsm6dsox_aux_den_mode_get(const stmdev_ctx_t *ctx, 3460 lsm6dsox_lvl2_ois_t *val); 3461 3462 int32_t lsm6dsox_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 3463 int32_t lsm6dsox_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, 3464 uint8_t *val); 3465 3466 typedef enum 3467 { 3468 LSM6DSOX_AUX_DISABLE = 0, 3469 LSM6DSOX_MODE_3_GY = 1, 3470 LSM6DSOX_MODE_4_GY_XL = 3, 3471 } lsm6dsox_ois_en_spi2_t; 3472 int32_t lsm6dsox_aux_mode_set(const stmdev_ctx_t *ctx, 3473 lsm6dsox_ois_en_spi2_t val); 3474 int32_t lsm6dsox_aux_mode_get(const stmdev_ctx_t *ctx, 3475 lsm6dsox_ois_en_spi2_t *val); 3476 3477 typedef enum 3478 { 3479 LSM6DSOX_250dps_AUX = 0, 3480 LSM6DSOX_125dps_AUX = 1, 3481 LSM6DSOX_500dps_AUX = 2, 3482 LSM6DSOX_1000dps_AUX = 4, 3483 LSM6DSOX_2000dps_AUX = 6, 3484 } lsm6dsox_fs_g_ois_t; 3485 int32_t lsm6dsox_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, 3486 lsm6dsox_fs_g_ois_t val); 3487 int32_t lsm6dsox_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, 3488 lsm6dsox_fs_g_ois_t *val); 3489 3490 typedef enum 3491 { 3492 LSM6DSOX_AUX_SPI_4_WIRE = 0, 3493 LSM6DSOX_AUX_SPI_3_WIRE = 1, 3494 } lsm6dsox_sim_ois_t; 3495 int32_t lsm6dsox_aux_spi_mode_set(const stmdev_ctx_t *ctx, 3496 lsm6dsox_sim_ois_t val); 3497 int32_t lsm6dsox_aux_spi_mode_get(const stmdev_ctx_t *ctx, 3498 lsm6dsox_sim_ois_t *val); 3499 3500 typedef enum 3501 { 3502 LSM6DSOX_351Hz39 = 0, 3503 LSM6DSOX_236Hz63 = 1, 3504 LSM6DSOX_172Hz70 = 2, 3505 LSM6DSOX_937Hz91 = 3, 3506 } lsm6dsox_ftype_ois_t; 3507 int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 3508 lsm6dsox_ftype_ois_t val); 3509 int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 3510 lsm6dsox_ftype_ois_t *val); 3511 3512 typedef enum 3513 { 3514 LSM6DSOX_AUX_HP_DISABLE = 0x00, 3515 LSM6DSOX_AUX_HP_Hz016 = 0x10, 3516 LSM6DSOX_AUX_HP_Hz065 = 0x11, 3517 LSM6DSOX_AUX_HP_Hz260 = 0x12, 3518 LSM6DSOX_AUX_HP_1Hz040 = 0x13, 3519 } lsm6dsox_hpm_ois_t; 3520 int32_t lsm6dsox_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx, 3521 lsm6dsox_hpm_ois_t val); 3522 int32_t lsm6dsox_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx, 3523 lsm6dsox_hpm_ois_t *val); 3524 3525 typedef enum 3526 { 3527 LSM6DSOX_ENABLE_CLAMP = 0, 3528 LSM6DSOX_DISABLE_CLAMP = 1, 3529 } lsm6dsox_st_ois_clampdis_t; 3530 int32_t lsm6dsox_aux_gy_clamp_set(const stmdev_ctx_t *ctx, 3531 lsm6dsox_st_ois_clampdis_t val); 3532 int32_t lsm6dsox_aux_gy_clamp_get(const stmdev_ctx_t *ctx, 3533 lsm6dsox_st_ois_clampdis_t *val); 3534 3535 typedef enum 3536 { 3537 LSM6DSOX_289Hz = 0, 3538 LSM6DSOX_258Hz = 1, 3539 LSM6DSOX_120Hz = 2, 3540 LSM6DSOX_65Hz2 = 3, 3541 LSM6DSOX_33Hz2 = 4, 3542 LSM6DSOX_16Hz6 = 5, 3543 LSM6DSOX_8Hz30 = 6, 3544 LSM6DSOX_4Hz15 = 7, 3545 } lsm6dsox_filter_xl_conf_ois_t; 3546 int32_t lsm6dsox_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx, 3547 lsm6dsox_filter_xl_conf_ois_t val); 3548 int32_t lsm6dsox_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx, 3549 lsm6dsox_filter_xl_conf_ois_t *val); 3550 3551 typedef enum 3552 { 3553 LSM6DSOX_AUX_2g = 0, 3554 LSM6DSOX_AUX_16g = 1, 3555 LSM6DSOX_AUX_4g = 2, 3556 LSM6DSOX_AUX_8g = 3, 3557 } lsm6dsox_fs_xl_ois_t; 3558 int32_t lsm6dsox_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, 3559 lsm6dsox_fs_xl_ois_t val); 3560 int32_t lsm6dsox_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, 3561 lsm6dsox_fs_xl_ois_t *val); 3562 3563 typedef enum 3564 { 3565 LSM6DSOX_PULL_UP_DISC = 0, 3566 LSM6DSOX_PULL_UP_CONNECT = 1, 3567 } lsm6dsox_sdo_pu_en_t; 3568 int32_t lsm6dsox_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 3569 lsm6dsox_sdo_pu_en_t val); 3570 int32_t lsm6dsox_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 3571 lsm6dsox_sdo_pu_en_t *val); 3572 3573 typedef enum 3574 { 3575 LSM6DSOX_SPI_4_WIRE = 0, 3576 LSM6DSOX_SPI_3_WIRE = 1, 3577 } lsm6dsox_sim_t; 3578 int32_t lsm6dsox_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sim_t val); 3579 int32_t lsm6dsox_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sim_t *val); 3580 3581 typedef enum 3582 { 3583 LSM6DSOX_I2C_ENABLE = 0, 3584 LSM6DSOX_I2C_DISABLE = 1, 3585 } lsm6dsox_i2c_disable_t; 3586 int32_t lsm6dsox_i2c_interface_set(const stmdev_ctx_t *ctx, 3587 lsm6dsox_i2c_disable_t val); 3588 int32_t lsm6dsox_i2c_interface_get(const stmdev_ctx_t *ctx, 3589 lsm6dsox_i2c_disable_t *val); 3590 3591 typedef enum 3592 { 3593 LSM6DSOX_I3C_DISABLE = 0x80, 3594 LSM6DSOX_I3C_ENABLE_T_50us = 0x00, 3595 LSM6DSOX_I3C_ENABLE_T_2us = 0x01, 3596 LSM6DSOX_I3C_ENABLE_T_1ms = 0x02, 3597 LSM6DSOX_I3C_ENABLE_T_25ms = 0x03, 3598 } lsm6dsox_i3c_disable_t; 3599 int32_t lsm6dsox_i3c_disable_set(const stmdev_ctx_t *ctx, 3600 lsm6dsox_i3c_disable_t val); 3601 int32_t lsm6dsox_i3c_disable_get(const stmdev_ctx_t *ctx, 3602 lsm6dsox_i3c_disable_t *val); 3603 3604 typedef enum 3605 { 3606 LSM6DSOX_PUSH_PULL = 0x00, 3607 LSM6DSOX_OPEN_DRAIN = 0x01, 3608 LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL = 0x02, 3609 LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN = 0x03, 3610 } lsm6dsox_pp_od_t; 3611 int32_t lsm6dsox_pin_mode_set(const stmdev_ctx_t *ctx, 3612 lsm6dsox_pp_od_t val); 3613 int32_t lsm6dsox_pin_mode_get(const stmdev_ctx_t *ctx, 3614 lsm6dsox_pp_od_t *val); 3615 3616 typedef enum 3617 { 3618 LSM6DSOX_ACTIVE_HIGH = 0, 3619 LSM6DSOX_ACTIVE_LOW = 1, 3620 } lsm6dsox_h_lactive_t; 3621 int32_t lsm6dsox_pin_polarity_set(const stmdev_ctx_t *ctx, 3622 lsm6dsox_h_lactive_t val); 3623 int32_t lsm6dsox_pin_polarity_get(const stmdev_ctx_t *ctx, 3624 lsm6dsox_h_lactive_t *val); 3625 3626 int32_t lsm6dsox_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 3627 int32_t lsm6dsox_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 3628 3629 typedef enum 3630 { 3631 LSM6DSOX_ALL_INT_PULSED = 0, 3632 LSM6DSOX_BASE_LATCHED_EMB_PULSED = 1, 3633 LSM6DSOX_BASE_PULSED_EMB_LATCHED = 2, 3634 LSM6DSOX_ALL_INT_LATCHED = 3, 3635 } lsm6dsox_lir_t; 3636 int32_t lsm6dsox_int_notification_set(const stmdev_ctx_t *ctx, 3637 lsm6dsox_lir_t val); 3638 int32_t lsm6dsox_int_notification_get(const stmdev_ctx_t *ctx, 3639 lsm6dsox_lir_t *val); 3640 3641 typedef enum 3642 { 3643 LSM6DSOX_LSb_FS_DIV_64 = 0, 3644 LSM6DSOX_LSb_FS_DIV_256 = 1, 3645 } lsm6dsox_wake_ths_w_t; 3646 int32_t lsm6dsox_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 3647 lsm6dsox_wake_ths_w_t val); 3648 int32_t lsm6dsox_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 3649 lsm6dsox_wake_ths_w_t *val); 3650 3651 int32_t lsm6dsox_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 3652 int32_t lsm6dsox_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 3653 3654 int32_t lsm6dsox_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 3655 uint8_t val); 3656 int32_t lsm6dsox_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 3657 uint8_t *val); 3658 3659 int32_t lsm6dsox_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3660 int32_t lsm6dsox_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3661 3662 int32_t lsm6dsox_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3663 int32_t lsm6dsox_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3664 3665 typedef enum 3666 { 3667 LSM6DSOX_DRIVE_SLEEP_CHG_EVENT = 0, 3668 LSM6DSOX_DRIVE_SLEEP_STATUS = 1, 3669 } lsm6dsox_sleep_status_on_int_t; 3670 int32_t lsm6dsox_act_pin_notification_set(const stmdev_ctx_t *ctx, 3671 lsm6dsox_sleep_status_on_int_t val); 3672 int32_t lsm6dsox_act_pin_notification_get(const stmdev_ctx_t *ctx, 3673 lsm6dsox_sleep_status_on_int_t *val); 3674 3675 typedef enum 3676 { 3677 LSM6DSOX_XL_AND_GY_NOT_AFFECTED = 0, 3678 LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED = 1, 3679 LSM6DSOX_XL_12Hz5_GY_SLEEP = 2, 3680 LSM6DSOX_XL_12Hz5_GY_PD = 3, 3681 } lsm6dsox_inact_en_t; 3682 int32_t lsm6dsox_act_mode_set(const stmdev_ctx_t *ctx, 3683 lsm6dsox_inact_en_t val); 3684 int32_t lsm6dsox_act_mode_get(const stmdev_ctx_t *ctx, 3685 lsm6dsox_inact_en_t *val); 3686 3687 int32_t lsm6dsox_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3688 int32_t lsm6dsox_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3689 3690 int32_t lsm6dsox_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 3691 uint8_t val); 3692 int32_t lsm6dsox_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 3693 uint8_t *val); 3694 3695 int32_t lsm6dsox_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 3696 uint8_t val); 3697 int32_t lsm6dsox_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 3698 uint8_t *val); 3699 3700 int32_t lsm6dsox_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 3701 uint8_t val); 3702 int32_t lsm6dsox_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 3703 uint8_t *val); 3704 3705 int32_t lsm6dsox_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); 3706 int32_t lsm6dsox_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 3707 3708 typedef enum 3709 { 3710 LSM6DSOX_XYZ = 0, 3711 LSM6DSOX_YXZ = 1, 3712 LSM6DSOX_XZY = 2, 3713 LSM6DSOX_ZYX = 3, 3714 LSM6DSOX_YZX = 5, 3715 LSM6DSOX_ZXY = 6, 3716 } lsm6dsox_tap_priority_t; 3717 int32_t lsm6dsox_tap_axis_priority_set(const stmdev_ctx_t *ctx, 3718 lsm6dsox_tap_priority_t val); 3719 int32_t lsm6dsox_tap_axis_priority_get(const stmdev_ctx_t *ctx, 3720 lsm6dsox_tap_priority_t *val); 3721 3722 int32_t lsm6dsox_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val); 3723 int32_t lsm6dsox_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val); 3724 3725 int32_t lsm6dsox_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val); 3726 int32_t lsm6dsox_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val); 3727 3728 int32_t lsm6dsox_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 3729 int32_t lsm6dsox_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 3730 3731 int32_t lsm6dsox_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 3732 int32_t lsm6dsox_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 3733 3734 int32_t lsm6dsox_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3735 int32_t lsm6dsox_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3736 3737 typedef enum 3738 { 3739 LSM6DSOX_ONLY_SINGLE = 0, 3740 LSM6DSOX_BOTH_SINGLE_DOUBLE = 1, 3741 } lsm6dsox_single_double_tap_t; 3742 int32_t lsm6dsox_tap_mode_set(const stmdev_ctx_t *ctx, 3743 lsm6dsox_single_double_tap_t val); 3744 int32_t lsm6dsox_tap_mode_get(const stmdev_ctx_t *ctx, 3745 lsm6dsox_single_double_tap_t *val); 3746 3747 typedef enum 3748 { 3749 LSM6DSOX_DEG_80 = 0, 3750 LSM6DSOX_DEG_70 = 1, 3751 LSM6DSOX_DEG_60 = 2, 3752 LSM6DSOX_DEG_50 = 3, 3753 } lsm6dsox_sixd_ths_t; 3754 int32_t lsm6dsox_6d_threshold_set(const stmdev_ctx_t *ctx, 3755 lsm6dsox_sixd_ths_t val); 3756 int32_t lsm6dsox_6d_threshold_get(const stmdev_ctx_t *ctx, 3757 lsm6dsox_sixd_ths_t *val); 3758 3759 int32_t lsm6dsox_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3760 int32_t lsm6dsox_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3761 3762 typedef enum 3763 { 3764 LSM6DSOX_FF_TSH_156mg = 0, 3765 LSM6DSOX_FF_TSH_219mg = 1, 3766 LSM6DSOX_FF_TSH_250mg = 2, 3767 LSM6DSOX_FF_TSH_312mg = 3, 3768 LSM6DSOX_FF_TSH_344mg = 4, 3769 LSM6DSOX_FF_TSH_406mg = 5, 3770 LSM6DSOX_FF_TSH_469mg = 6, 3771 LSM6DSOX_FF_TSH_500mg = 7, 3772 } lsm6dsox_ff_ths_t; 3773 int32_t lsm6dsox_ff_threshold_set(const stmdev_ctx_t *ctx, 3774 lsm6dsox_ff_ths_t val); 3775 int32_t lsm6dsox_ff_threshold_get(const stmdev_ctx_t *ctx, 3776 lsm6dsox_ff_ths_t *val); 3777 3778 int32_t lsm6dsox_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 3779 int32_t lsm6dsox_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 3780 3781 int32_t lsm6dsox_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); 3782 int32_t lsm6dsox_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); 3783 3784 int32_t lsm6dsox_compression_algo_init_set(const stmdev_ctx_t *ctx, 3785 uint8_t val); 3786 int32_t lsm6dsox_compression_algo_init_get(const stmdev_ctx_t *ctx, 3787 uint8_t *val); 3788 3789 typedef enum 3790 { 3791 LSM6DSOX_CMP_DISABLE = 0x00, 3792 LSM6DSOX_CMP_ALWAYS = 0x04, 3793 LSM6DSOX_CMP_8_TO_1 = 0x05, 3794 LSM6DSOX_CMP_16_TO_1 = 0x06, 3795 LSM6DSOX_CMP_32_TO_1 = 0x07, 3796 } lsm6dsox_uncoptr_rate_t; 3797 int32_t lsm6dsox_compression_algo_set(const stmdev_ctx_t *ctx, 3798 lsm6dsox_uncoptr_rate_t val); 3799 int32_t lsm6dsox_compression_algo_get(const stmdev_ctx_t *ctx, 3800 lsm6dsox_uncoptr_rate_t *val); 3801 3802 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3803 uint8_t val); 3804 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3805 uint8_t *val); 3806 3807 int32_t lsm6dsox_compression_algo_real_time_set(const stmdev_ctx_t *ctx, 3808 uint8_t val); 3809 int32_t lsm6dsox_compression_algo_real_time_get(const stmdev_ctx_t *ctx, 3810 uint8_t *val); 3811 3812 int32_t lsm6dsox_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 3813 int32_t lsm6dsox_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 3814 uint8_t *val); 3815 3816 typedef enum 3817 { 3818 LSM6DSOX_XL_NOT_BATCHED = 0, 3819 LSM6DSOX_XL_BATCHED_AT_12Hz5 = 1, 3820 LSM6DSOX_XL_BATCHED_AT_26Hz = 2, 3821 LSM6DSOX_XL_BATCHED_AT_52Hz = 3, 3822 LSM6DSOX_XL_BATCHED_AT_104Hz = 4, 3823 LSM6DSOX_XL_BATCHED_AT_208Hz = 5, 3824 LSM6DSOX_XL_BATCHED_AT_417Hz = 6, 3825 LSM6DSOX_XL_BATCHED_AT_833Hz = 7, 3826 LSM6DSOX_XL_BATCHED_AT_1667Hz = 8, 3827 LSM6DSOX_XL_BATCHED_AT_3333Hz = 9, 3828 LSM6DSOX_XL_BATCHED_AT_6667Hz = 10, 3829 LSM6DSOX_XL_BATCHED_AT_6Hz5 = 11, 3830 } lsm6dsox_bdr_xl_t; 3831 int32_t lsm6dsox_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3832 lsm6dsox_bdr_xl_t val); 3833 int32_t lsm6dsox_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3834 lsm6dsox_bdr_xl_t *val); 3835 3836 typedef enum 3837 { 3838 LSM6DSOX_GY_NOT_BATCHED = 0, 3839 LSM6DSOX_GY_BATCHED_AT_12Hz5 = 1, 3840 LSM6DSOX_GY_BATCHED_AT_26Hz = 2, 3841 LSM6DSOX_GY_BATCHED_AT_52Hz = 3, 3842 LSM6DSOX_GY_BATCHED_AT_104Hz = 4, 3843 LSM6DSOX_GY_BATCHED_AT_208Hz = 5, 3844 LSM6DSOX_GY_BATCHED_AT_417Hz = 6, 3845 LSM6DSOX_GY_BATCHED_AT_833Hz = 7, 3846 LSM6DSOX_GY_BATCHED_AT_1667Hz = 8, 3847 LSM6DSOX_GY_BATCHED_AT_3333Hz = 9, 3848 LSM6DSOX_GY_BATCHED_AT_6667Hz = 10, 3849 LSM6DSOX_GY_BATCHED_AT_6Hz5 = 11, 3850 } lsm6dsox_bdr_gy_t; 3851 int32_t lsm6dsox_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3852 lsm6dsox_bdr_gy_t val); 3853 int32_t lsm6dsox_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3854 lsm6dsox_bdr_gy_t *val); 3855 3856 typedef enum 3857 { 3858 LSM6DSOX_BYPASS_MODE = 0, 3859 LSM6DSOX_FIFO_MODE = 1, 3860 LSM6DSOX_STREAM_TO_FIFO_MODE = 3, 3861 LSM6DSOX_BYPASS_TO_STREAM_MODE = 4, 3862 LSM6DSOX_STREAM_MODE = 6, 3863 LSM6DSOX_BYPASS_TO_FIFO_MODE = 7, 3864 } lsm6dsox_fifo_mode_t; 3865 int32_t lsm6dsox_fifo_mode_set(const stmdev_ctx_t *ctx, 3866 lsm6dsox_fifo_mode_t val); 3867 int32_t lsm6dsox_fifo_mode_get(const stmdev_ctx_t *ctx, 3868 lsm6dsox_fifo_mode_t *val); 3869 3870 typedef enum 3871 { 3872 LSM6DSOX_TEMP_NOT_BATCHED = 0, 3873 LSM6DSOX_TEMP_BATCHED_AT_1Hz6 = 1, 3874 LSM6DSOX_TEMP_BATCHED_AT_12Hz5 = 2, 3875 LSM6DSOX_TEMP_BATCHED_AT_52Hz = 3, 3876 } lsm6dsox_odr_t_batch_t; 3877 int32_t lsm6dsox_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3878 lsm6dsox_odr_t_batch_t val); 3879 int32_t lsm6dsox_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3880 lsm6dsox_odr_t_batch_t *val); 3881 3882 typedef enum 3883 { 3884 LSM6DSOX_NO_DECIMATION = 0, 3885 LSM6DSOX_DEC_1 = 1, 3886 LSM6DSOX_DEC_8 = 2, 3887 LSM6DSOX_DEC_32 = 3, 3888 } lsm6dsox_odr_ts_batch_t; 3889 int32_t lsm6dsox_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 3890 lsm6dsox_odr_ts_batch_t val); 3891 int32_t lsm6dsox_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 3892 lsm6dsox_odr_ts_batch_t *val); 3893 3894 typedef enum 3895 { 3896 LSM6DSOX_XL_BATCH_EVENT = 0, 3897 LSM6DSOX_GYRO_BATCH_EVENT = 1, 3898 } lsm6dsox_trig_counter_bdr_t; 3899 3900 typedef enum 3901 { 3902 LSM6DSOX_GYRO_NC_TAG = 1, 3903 LSM6DSOX_XL_NC_TAG, 3904 LSM6DSOX_TEMPERATURE_TAG, 3905 LSM6DSOX_TIMESTAMP_TAG, 3906 LSM6DSOX_CFG_CHANGE_TAG, 3907 LSM6DSOX_XL_NC_T_2_TAG, 3908 LSM6DSOX_XL_NC_T_1_TAG, 3909 LSM6DSOX_XL_2XC_TAG, 3910 LSM6DSOX_XL_3XC_TAG, 3911 LSM6DSOX_GYRO_NC_T_2_TAG, 3912 LSM6DSOX_GYRO_NC_T_1_TAG, 3913 LSM6DSOX_GYRO_2XC_TAG, 3914 LSM6DSOX_GYRO_3XC_TAG, 3915 LSM6DSOX_SENSORHUB_SLAVE0_TAG, 3916 LSM6DSOX_SENSORHUB_SLAVE1_TAG, 3917 LSM6DSOX_SENSORHUB_SLAVE2_TAG, 3918 LSM6DSOX_SENSORHUB_SLAVE3_TAG, 3919 LSM6DSOX_STEP_CPUNTER_TAG, 3920 LSM6DSOX_GAME_ROTATION_TAG, 3921 LSM6DSOX_GEOMAG_ROTATION_TAG, 3922 LSM6DSOX_ROTATION_TAG, 3923 LSM6DSOX_SENSORHUB_NACK_TAG = 0x19, 3924 } lsm6dsox_fifo_tag_t; 3925 int32_t lsm6dsox_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 3926 lsm6dsox_trig_counter_bdr_t val); 3927 int32_t lsm6dsox_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 3928 lsm6dsox_trig_counter_bdr_t *val); 3929 3930 int32_t lsm6dsox_rst_batch_counter_set(const stmdev_ctx_t *ctx, 3931 uint8_t val); 3932 int32_t lsm6dsox_rst_batch_counter_get(const stmdev_ctx_t *ctx, 3933 uint8_t *val); 3934 3935 int32_t lsm6dsox_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3936 uint16_t val); 3937 int32_t lsm6dsox_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3938 uint16_t *val); 3939 3940 int32_t lsm6dsox_fifo_data_level_get(const stmdev_ctx_t *ctx, 3941 uint16_t *val); 3942 3943 int32_t lsm6dsox_fifo_status_get(const stmdev_ctx_t *ctx, 3944 lsm6dsox_fifo_status2_t *val); 3945 3946 int32_t lsm6dsox_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3947 3948 int32_t lsm6dsox_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3949 3950 int32_t lsm6dsox_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 3951 3952 int32_t lsm6dsox_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 3953 lsm6dsox_fifo_tag_t *val); 3954 3955 int32_t lsm6dsox_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 3956 int32_t lsm6dsox_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 3957 3958 int32_t lsm6dsox_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val); 3959 int32_t lsm6dsox_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, 3960 uint8_t *val); 3961 3962 int32_t lsm6dsox_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val); 3963 int32_t lsm6dsox_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, 3964 uint8_t *val); 3965 3966 int32_t lsm6dsox_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val); 3967 int32_t lsm6dsox_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, 3968 uint8_t *val); 3969 3970 int32_t lsm6dsox_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val); 3971 int32_t lsm6dsox_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, 3972 uint8_t *val); 3973 3974 typedef enum 3975 { 3976 LSM6DSOX_DEN_DISABLE = 0, 3977 LSM6DSOX_LEVEL_FIFO = 6, 3978 LSM6DSOX_LEVEL_LETCHED = 3, 3979 LSM6DSOX_LEVEL_TRIGGER = 2, 3980 LSM6DSOX_EDGE_TRIGGER = 4, 3981 } lsm6dsox_den_mode_t; 3982 int32_t lsm6dsox_den_mode_set(const stmdev_ctx_t *ctx, 3983 lsm6dsox_den_mode_t val); 3984 int32_t lsm6dsox_den_mode_get(const stmdev_ctx_t *ctx, 3985 lsm6dsox_den_mode_t *val); 3986 3987 typedef enum 3988 { 3989 LSM6DSOX_DEN_ACT_LOW = 0, 3990 LSM6DSOX_DEN_ACT_HIGH = 1, 3991 } lsm6dsox_den_lh_t; 3992 int32_t lsm6dsox_den_polarity_set(const stmdev_ctx_t *ctx, 3993 lsm6dsox_den_lh_t val); 3994 int32_t lsm6dsox_den_polarity_get(const stmdev_ctx_t *ctx, 3995 lsm6dsox_den_lh_t *val); 3996 3997 typedef enum 3998 { 3999 LSM6DSOX_STAMP_IN_GY_DATA = 0, 4000 LSM6DSOX_STAMP_IN_XL_DATA = 1, 4001 LSM6DSOX_STAMP_IN_GY_XL_DATA = 2, 4002 } lsm6dsox_den_xl_g_t; 4003 int32_t lsm6dsox_den_enable_set(const stmdev_ctx_t *ctx, 4004 lsm6dsox_den_xl_g_t val); 4005 int32_t lsm6dsox_den_enable_get(const stmdev_ctx_t *ctx, 4006 lsm6dsox_den_xl_g_t *val); 4007 4008 int32_t lsm6dsox_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); 4009 int32_t lsm6dsox_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 4010 4011 int32_t lsm6dsox_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); 4012 int32_t lsm6dsox_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); 4013 4014 int32_t lsm6dsox_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); 4015 int32_t lsm6dsox_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); 4016 4017 typedef enum 4018 { 4019 LSM6DSOX_PEDO_BASE_MODE = 0x00, 4020 LSM6DSOX_FALSE_STEP_REJ = 0x10, 4021 LSM6DSOX_FALSE_STEP_REJ_ADV_MODE = 0x30, 4022 } lsm6dsox_pedo_md_t; 4023 int32_t lsm6dsox_pedo_sens_set(const stmdev_ctx_t *ctx, 4024 lsm6dsox_pedo_md_t val); 4025 int32_t lsm6dsox_pedo_sens_get(const stmdev_ctx_t *ctx, 4026 lsm6dsox_pedo_md_t *val); 4027 4028 int32_t lsm6dsox_pedo_step_detect_get(const stmdev_ctx_t *ctx, 4029 uint8_t *val); 4030 4031 int32_t lsm6dsox_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 4032 uint8_t *buff); 4033 int32_t lsm6dsox_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 4034 uint8_t *buff); 4035 4036 int32_t lsm6dsox_pedo_steps_period_set(const stmdev_ctx_t *ctx, 4037 uint16_t val); 4038 int32_t lsm6dsox_pedo_steps_period_get(const stmdev_ctx_t *ctx, 4039 uint16_t *val); 4040 4041 int32_t lsm6dsox_pedo_adv_detection_set(const stmdev_ctx_t *ctx, 4042 uint8_t val); 4043 int32_t lsm6dsox_pedo_adv_detection_get(const stmdev_ctx_t *ctx, 4044 uint8_t *val); 4045 4046 int32_t lsm6dsox_pedo_false_step_rejection_set(const stmdev_ctx_t *ctx, 4047 uint8_t val); 4048 int32_t lsm6dsox_pedo_false_step_rejection_get(const stmdev_ctx_t *ctx, 4049 uint8_t *val); 4050 4051 typedef enum 4052 { 4053 LSM6DSOX_EVERY_STEP = 0, 4054 LSM6DSOX_COUNT_OVERFLOW = 1, 4055 } lsm6dsox_carry_count_en_t; 4056 int32_t lsm6dsox_pedo_int_mode_set(const stmdev_ctx_t *ctx, 4057 lsm6dsox_carry_count_en_t val); 4058 int32_t lsm6dsox_pedo_int_mode_get(const stmdev_ctx_t *ctx, 4059 lsm6dsox_carry_count_en_t *val); 4060 4061 int32_t lsm6dsox_motion_flag_data_ready_get(const stmdev_ctx_t *ctx, 4062 uint8_t *val); 4063 4064 int32_t lsm6dsox_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx, 4065 uint8_t *val); 4066 4067 int32_t lsm6dsox_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx, 4068 uint16_t val); 4069 int32_t lsm6dsox_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx, 4070 uint16_t *val); 4071 4072 int32_t lsm6dsox_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, 4073 uint16_t val); 4074 int32_t lsm6dsox_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, 4075 uint16_t *val); 4076 4077 int32_t lsm6dsox_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 4078 int32_t lsm6dsox_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 4079 4080 int32_t lsm6dsox_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); 4081 int32_t lsm6dsox_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); 4082 4083 typedef enum 4084 { 4085 LSM6DSOX_Z_EQ_Y = 0, 4086 LSM6DSOX_Z_EQ_MIN_Y = 1, 4087 LSM6DSOX_Z_EQ_X = 2, 4088 LSM6DSOX_Z_EQ_MIN_X = 3, 4089 LSM6DSOX_Z_EQ_MIN_Z = 4, 4090 LSM6DSOX_Z_EQ_Z = 5, 4091 } lsm6dsox_mag_z_axis_t; 4092 int32_t lsm6dsox_mag_z_orient_set(const stmdev_ctx_t *ctx, 4093 lsm6dsox_mag_z_axis_t val); 4094 int32_t lsm6dsox_mag_z_orient_get(const stmdev_ctx_t *ctx, 4095 lsm6dsox_mag_z_axis_t *val); 4096 4097 typedef enum 4098 { 4099 LSM6DSOX_Y_EQ_Y = 0, 4100 LSM6DSOX_Y_EQ_MIN_Y = 1, 4101 LSM6DSOX_Y_EQ_X = 2, 4102 LSM6DSOX_Y_EQ_MIN_X = 3, 4103 LSM6DSOX_Y_EQ_MIN_Z = 4, 4104 LSM6DSOX_Y_EQ_Z = 5, 4105 } lsm6dsox_mag_y_axis_t; 4106 int32_t lsm6dsox_mag_y_orient_set(const stmdev_ctx_t *ctx, 4107 lsm6dsox_mag_y_axis_t val); 4108 int32_t lsm6dsox_mag_y_orient_get(const stmdev_ctx_t *ctx, 4109 lsm6dsox_mag_y_axis_t *val); 4110 4111 typedef enum 4112 { 4113 LSM6DSOX_X_EQ_Y = 0, 4114 LSM6DSOX_X_EQ_MIN_Y = 1, 4115 LSM6DSOX_X_EQ_X = 2, 4116 LSM6DSOX_X_EQ_MIN_X = 3, 4117 LSM6DSOX_X_EQ_MIN_Z = 4, 4118 LSM6DSOX_X_EQ_Z = 5, 4119 } lsm6dsox_mag_x_axis_t; 4120 int32_t lsm6dsox_mag_x_orient_set(const stmdev_ctx_t *ctx, 4121 lsm6dsox_mag_x_axis_t val); 4122 int32_t lsm6dsox_mag_x_orient_get(const stmdev_ctx_t *ctx, 4123 lsm6dsox_mag_x_axis_t *val); 4124 4125 int32_t lsm6dsox_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 4126 uint8_t *val); 4127 4128 typedef struct 4129 { 4130 lsm6dsox_fsm_enable_a_t fsm_enable_a; 4131 lsm6dsox_fsm_enable_b_t fsm_enable_b; 4132 } lsm6dsox_emb_fsm_enable_t; 4133 int32_t lsm6dsox_fsm_enable_set(const stmdev_ctx_t *ctx, 4134 lsm6dsox_emb_fsm_enable_t *val); 4135 int32_t lsm6dsox_fsm_enable_get(const stmdev_ctx_t *ctx, 4136 lsm6dsox_emb_fsm_enable_t *val); 4137 4138 int32_t lsm6dsox_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 4139 int32_t lsm6dsox_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 4140 4141 typedef enum 4142 { 4143 LSM6DSOX_LC_NORMAL = 0, 4144 LSM6DSOX_LC_CLEAR = 1, 4145 LSM6DSOX_LC_CLEAR_DONE = 2, 4146 } lsm6dsox_fsm_lc_clr_t; 4147 int32_t lsm6dsox_long_clr_set(const stmdev_ctx_t *ctx, 4148 lsm6dsox_fsm_lc_clr_t val); 4149 int32_t lsm6dsox_long_clr_get(const stmdev_ctx_t *ctx, 4150 lsm6dsox_fsm_lc_clr_t *val); 4151 4152 typedef struct 4153 { 4154 lsm6dsox_fsm_outs1_t fsm_outs1; 4155 lsm6dsox_fsm_outs2_t fsm_outs2; 4156 lsm6dsox_fsm_outs3_t fsm_outs3; 4157 lsm6dsox_fsm_outs4_t fsm_outs4; 4158 lsm6dsox_fsm_outs5_t fsm_outs5; 4159 lsm6dsox_fsm_outs6_t fsm_outs6; 4160 lsm6dsox_fsm_outs7_t fsm_outs7; 4161 lsm6dsox_fsm_outs8_t fsm_outs8; 4162 lsm6dsox_fsm_outs1_t fsm_outs9; 4163 lsm6dsox_fsm_outs2_t fsm_outs10; 4164 lsm6dsox_fsm_outs3_t fsm_outs11; 4165 lsm6dsox_fsm_outs4_t fsm_outs12; 4166 lsm6dsox_fsm_outs5_t fsm_outs13; 4167 lsm6dsox_fsm_outs6_t fsm_outs14; 4168 lsm6dsox_fsm_outs7_t fsm_outs15; 4169 lsm6dsox_fsm_outs8_t fsm_outs16; 4170 } lsm6dsox_fsm_out_t; 4171 int32_t lsm6dsox_fsm_out_get(const stmdev_ctx_t *ctx, 4172 lsm6dsox_fsm_out_t *val); 4173 4174 typedef enum 4175 { 4176 LSM6DSOX_ODR_FSM_12Hz5 = 0, 4177 LSM6DSOX_ODR_FSM_26Hz = 1, 4178 LSM6DSOX_ODR_FSM_52Hz = 2, 4179 LSM6DSOX_ODR_FSM_104Hz = 3, 4180 } lsm6dsox_fsm_odr_t; 4181 int32_t lsm6dsox_fsm_data_rate_set(const stmdev_ctx_t *ctx, 4182 lsm6dsox_fsm_odr_t val); 4183 int32_t lsm6dsox_fsm_data_rate_get(const stmdev_ctx_t *ctx, 4184 lsm6dsox_fsm_odr_t *val); 4185 4186 int32_t lsm6dsox_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 4187 int32_t lsm6dsox_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 4188 4189 int32_t lsm6dsox_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 4190 uint16_t val); 4191 int32_t lsm6dsox_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 4192 uint16_t *val); 4193 4194 int32_t lsm6dsox_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, 4195 uint8_t val); 4196 int32_t lsm6dsox_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, 4197 uint8_t *val); 4198 4199 int32_t lsm6dsox_fsm_start_address_set(const stmdev_ctx_t *ctx, 4200 uint16_t val); 4201 int32_t lsm6dsox_fsm_start_address_get(const stmdev_ctx_t *ctx, 4202 uint16_t *val); 4203 4204 int32_t lsm6dsox_mlc_status_get(const stmdev_ctx_t *ctx, 4205 lsm6dsox_mlc_status_mainpage_t *val); 4206 4207 typedef enum 4208 { 4209 LSM6DSOX_ODR_PRGS_12Hz5 = 0, 4210 LSM6DSOX_ODR_PRGS_26Hz = 1, 4211 LSM6DSOX_ODR_PRGS_52Hz = 2, 4212 LSM6DSOX_ODR_PRGS_104Hz = 3, 4213 } lsm6dsox_mlc_odr_t; 4214 int32_t lsm6dsox_mlc_data_rate_set(const stmdev_ctx_t *ctx, 4215 lsm6dsox_mlc_odr_t val); 4216 int32_t lsm6dsox_mlc_data_rate_get(const stmdev_ctx_t *ctx, 4217 lsm6dsox_mlc_odr_t *val); 4218 4219 typedef struct 4220 { 4221 lsm6dsox_sensor_hub_1_t sh_byte_1; 4222 lsm6dsox_sensor_hub_2_t sh_byte_2; 4223 lsm6dsox_sensor_hub_3_t sh_byte_3; 4224 lsm6dsox_sensor_hub_4_t sh_byte_4; 4225 lsm6dsox_sensor_hub_5_t sh_byte_5; 4226 lsm6dsox_sensor_hub_6_t sh_byte_6; 4227 lsm6dsox_sensor_hub_7_t sh_byte_7; 4228 lsm6dsox_sensor_hub_8_t sh_byte_8; 4229 lsm6dsox_sensor_hub_9_t sh_byte_9; 4230 lsm6dsox_sensor_hub_10_t sh_byte_10; 4231 lsm6dsox_sensor_hub_11_t sh_byte_11; 4232 lsm6dsox_sensor_hub_12_t sh_byte_12; 4233 lsm6dsox_sensor_hub_13_t sh_byte_13; 4234 lsm6dsox_sensor_hub_14_t sh_byte_14; 4235 lsm6dsox_sensor_hub_15_t sh_byte_15; 4236 lsm6dsox_sensor_hub_16_t sh_byte_16; 4237 lsm6dsox_sensor_hub_17_t sh_byte_17; 4238 lsm6dsox_sensor_hub_18_t sh_byte_18; 4239 } lsm6dsox_emb_sh_read_t; 4240 int32_t lsm6dsox_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 4241 lsm6dsox_emb_sh_read_t *val, 4242 uint8_t len); 4243 4244 typedef enum 4245 { 4246 LSM6DSOX_SLV_0 = 0, 4247 LSM6DSOX_SLV_0_1 = 1, 4248 LSM6DSOX_SLV_0_1_2 = 2, 4249 LSM6DSOX_SLV_0_1_2_3 = 3, 4250 } lsm6dsox_aux_sens_on_t; 4251 int32_t lsm6dsox_sh_slave_connected_set(const stmdev_ctx_t *ctx, 4252 lsm6dsox_aux_sens_on_t val); 4253 int32_t lsm6dsox_sh_slave_connected_get(const stmdev_ctx_t *ctx, 4254 lsm6dsox_aux_sens_on_t *val); 4255 4256 int32_t lsm6dsox_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 4257 int32_t lsm6dsox_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 4258 4259 typedef enum 4260 { 4261 LSM6DSOX_EXT_PULL_UP = 0, 4262 LSM6DSOX_INTERNAL_PULL_UP = 1, 4263 } lsm6dsox_shub_pu_en_t; 4264 int32_t lsm6dsox_sh_pin_mode_set(const stmdev_ctx_t *ctx, 4265 lsm6dsox_shub_pu_en_t val); 4266 int32_t lsm6dsox_sh_pin_mode_get(const stmdev_ctx_t *ctx, 4267 lsm6dsox_shub_pu_en_t *val); 4268 4269 int32_t lsm6dsox_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); 4270 int32_t lsm6dsox_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); 4271 4272 typedef enum 4273 { 4274 LSM6DSOX_EXT_ON_INT2_PIN = 1, 4275 LSM6DSOX_XL_GY_DRDY = 0, 4276 } lsm6dsox_start_config_t; 4277 int32_t lsm6dsox_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 4278 lsm6dsox_start_config_t val); 4279 int32_t lsm6dsox_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 4280 lsm6dsox_start_config_t *val); 4281 4282 typedef enum 4283 { 4284 LSM6DSOX_EACH_SH_CYCLE = 0, 4285 LSM6DSOX_ONLY_FIRST_CYCLE = 1, 4286 } lsm6dsox_write_once_t; 4287 int32_t lsm6dsox_sh_write_mode_set(const stmdev_ctx_t *ctx, 4288 lsm6dsox_write_once_t val); 4289 int32_t lsm6dsox_sh_write_mode_get(const stmdev_ctx_t *ctx, 4290 lsm6dsox_write_once_t *val); 4291 4292 int32_t lsm6dsox_sh_reset_set(const stmdev_ctx_t *ctx); 4293 int32_t lsm6dsox_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 4294 4295 typedef enum 4296 { 4297 LSM6DSOX_SH_ODR_104Hz = 0, 4298 LSM6DSOX_SH_ODR_52Hz = 1, 4299 LSM6DSOX_SH_ODR_26Hz = 2, 4300 LSM6DSOX_SH_ODR_13Hz = 3, 4301 } lsm6dsox_shub_odr_t; 4302 int32_t lsm6dsox_sh_data_rate_set(const stmdev_ctx_t *ctx, 4303 lsm6dsox_shub_odr_t val); 4304 int32_t lsm6dsox_sh_data_rate_get(const stmdev_ctx_t *ctx, 4305 lsm6dsox_shub_odr_t *val); 4306 4307 typedef struct 4308 { 4309 uint8_t slv0_add; 4310 uint8_t slv0_subadd; 4311 uint8_t slv0_data; 4312 } lsm6dsox_sh_cfg_write_t; 4313 int32_t lsm6dsox_sh_cfg_write(const stmdev_ctx_t *ctx, 4314 lsm6dsox_sh_cfg_write_t *val); 4315 4316 typedef struct 4317 { 4318 uint8_t slv_add; 4319 uint8_t slv_subadd; 4320 uint8_t slv_len; 4321 } lsm6dsox_sh_cfg_read_t; 4322 int32_t lsm6dsox_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 4323 lsm6dsox_sh_cfg_read_t *val); 4324 int32_t lsm6dsox_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 4325 lsm6dsox_sh_cfg_read_t *val); 4326 int32_t lsm6dsox_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 4327 lsm6dsox_sh_cfg_read_t *val); 4328 int32_t lsm6dsox_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 4329 lsm6dsox_sh_cfg_read_t *val); 4330 4331 int32_t lsm6dsox_sh_status_get(const stmdev_ctx_t *ctx, 4332 lsm6dsox_status_master_t *val); 4333 typedef enum 4334 { 4335 LSM6DSOX_S4S_TPH_7bit = 0, 4336 LSM6DSOX_S4S_TPH_15bit = 1, 4337 } lsm6dsox_s4s_tph_res_t; 4338 int32_t lsm6dsox_s4s_tph_res_set(const stmdev_ctx_t *ctx, 4339 lsm6dsox_s4s_tph_res_t val); 4340 int32_t lsm6dsox_s4s_tph_res_get(const stmdev_ctx_t *ctx, 4341 lsm6dsox_s4s_tph_res_t *val); 4342 4343 int32_t lsm6dsox_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val); 4344 int32_t lsm6dsox_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val); 4345 4346 typedef enum 4347 { 4348 LSM6DSOX_S4S_DT_RES_11 = 0, 4349 LSM6DSOX_S4S_DT_RES_12 = 1, 4350 LSM6DSOX_S4S_DT_RES_13 = 2, 4351 LSM6DSOX_S4S_DT_RES_14 = 3, 4352 } lsm6dsox_s4s_res_ratio_t; 4353 int32_t lsm6dsox_s4s_res_ratio_set(const stmdev_ctx_t *ctx, 4354 lsm6dsox_s4s_res_ratio_t val); 4355 int32_t lsm6dsox_s4s_res_ratio_get(const stmdev_ctx_t *ctx, 4356 lsm6dsox_s4s_res_ratio_t *val); 4357 4358 int32_t lsm6dsox_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val); 4359 int32_t lsm6dsox_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val); 4360 4361 int32_t lsm6dsox_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val); 4362 int32_t lsm6dsox_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val); 4363 4364 typedef struct 4365 { 4366 uint8_t ui; 4367 uint8_t aux; 4368 } lsm6dsox_id_t; 4369 int32_t lsm6dsox_id_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4370 lsm6dsox_id_t *val); 4371 4372 typedef enum 4373 { 4374 LSM6DSOX_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 4375 LSM6DSOX_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ 4376 LSM6DSOX_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 4377 LSM6DSOX_I2C = 0x04, /* Only I2C */ 4378 LSM6DSOX_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ 4379 LSM6DSOX_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ 4380 LSM6DSOX_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ 4381 LSM6DSOX_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ 4382 } lsm6dsox_ui_bus_md_t; 4383 4384 typedef enum 4385 { 4386 LSM6DSOX_SPI_4W_AUX = 0x00, 4387 LSM6DSOX_SPI_3W_AUX = 0x01, 4388 } lsm6dsox_aux_bus_md_t; 4389 4390 typedef struct 4391 { 4392 lsm6dsox_ui_bus_md_t ui_bus_md; 4393 lsm6dsox_aux_bus_md_t aux_bus_md; 4394 } lsm6dsox_bus_mode_t; 4395 int32_t lsm6dsox_bus_mode_set(const stmdev_ctx_t *ctx, 4396 stmdev_ctx_t *aux_ctx, 4397 lsm6dsox_bus_mode_t val); 4398 int32_t lsm6dsox_bus_mode_get(const stmdev_ctx_t *ctx, 4399 stmdev_ctx_t *aux_ctx, 4400 lsm6dsox_bus_mode_t *val); 4401 4402 typedef enum 4403 { 4404 LSM6DSOX_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 4405 LSM6DSOX_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 4406 LSM6DSOX_RESET = 0x02, /* Reset configuration registers */ 4407 LSM6DSOX_FIFO_COMP = 0x04, /* FIFO compression initialization request. */ 4408 LSM6DSOX_FSM = 0x08, /* Finite State Machine initialization request */ 4409 LSM6DSOX_MLC = 0x10, /* Machine Learning Core initialization request */ 4410 LSM6DSOX_PEDO = 0x20, /* Pedometer algo initialization request. */ 4411 LSM6DSOX_TILT = 0x40, /* Tilt algo initialization request */ 4412 LSM6DSOX_SMOTION = 0x80, /* Significant Motion initialization request */ 4413 } lsm6dsox_init_t; 4414 int32_t lsm6dsox_init_set(const stmdev_ctx_t *ctx, lsm6dsox_init_t val); 4415 4416 typedef struct 4417 { 4418 uint8_t sw_reset : 1; /* Restoring configuration registers */ 4419 uint8_t boot : 1; /* Restoring calibration parameters */ 4420 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4421 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4422 uint8_t drdy_temp : 1; /* Temperature data ready */ 4423 uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */ 4424 uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */ 4425 uint8_t ois_gyro_settling : 1; /* Gyroscope is in the settling phase */ 4426 } lsm6dsox_status_t; 4427 int32_t lsm6dsox_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4428 lsm6dsox_status_t *val); 4429 4430 typedef struct 4431 { 4432 uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ 4433 uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ 4434 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 4435 uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 4436 } lsm6dsox_pin_conf_t; 4437 int32_t lsm6dsox_pin_conf_set(const stmdev_ctx_t *ctx, 4438 lsm6dsox_pin_conf_t val); 4439 int32_t lsm6dsox_pin_conf_get(const stmdev_ctx_t *ctx, 4440 lsm6dsox_pin_conf_t *val); 4441 4442 typedef struct 4443 { 4444 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 4445 uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ 4446 uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ 4447 } lsm6dsox_int_mode_t; 4448 int32_t lsm6dsox_interrupt_mode_set(const stmdev_ctx_t *ctx, 4449 lsm6dsox_int_mode_t val); 4450 int32_t lsm6dsox_interrupt_mode_get(const stmdev_ctx_t *ctx, 4451 lsm6dsox_int_mode_t *val); 4452 4453 typedef struct 4454 { 4455 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4456 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4457 uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */ 4458 uint8_t boot : 1; /* Restoring calibration parameters */ 4459 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4460 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4461 uint8_t fifo_full : 1; /* FIFO full */ 4462 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4463 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 4464 uint8_t sh_endop : 1; /* sensor hub end operation */ 4465 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 4466 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4467 uint8_t double_tap : 1; /* double-tap event */ 4468 uint8_t free_fall : 1; /* free fall event */ 4469 uint8_t wake_up : 1; /* wake up event */ 4470 uint8_t single_tap : 1; /* single-tap event */ 4471 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 4472 uint8_t step_detector : 1; /* Step detected */ 4473 uint8_t tilt : 1; /* Relative tilt event detected */ 4474 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4475 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 4476 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4477 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4478 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4479 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4480 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4481 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4482 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4483 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4484 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4485 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4486 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4487 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4488 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4489 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4490 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4491 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4492 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4493 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4494 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4495 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4496 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4497 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4498 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4499 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4500 } lsm6dsox_pin_int1_route_t; 4501 4502 int32_t lsm6dsox_pin_int1_route_set(const stmdev_ctx_t *ctx, 4503 lsm6dsox_pin_int1_route_t val); 4504 int32_t lsm6dsox_pin_int1_route_get(const stmdev_ctx_t *ctx, 4505 lsm6dsox_pin_int1_route_t *val); 4506 4507 typedef struct 4508 { 4509 uint8_t drdy_ois : 1; /* OIS chain data ready */ 4510 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4511 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4512 uint8_t drdy_temp : 1; /* Temperature data ready */ 4513 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4514 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4515 uint8_t fifo_full : 1; /* FIFO full */ 4516 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4517 uint8_t timestamp : 1; /* timestamp overflow */ 4518 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4519 uint8_t double_tap : 1; /* double-tap event */ 4520 uint8_t free_fall : 1; /* free fall event */ 4521 uint8_t wake_up : 1; /* wake up event */ 4522 uint8_t single_tap : 1; /* single-tap event */ 4523 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 4524 uint8_t step_detector : 1; /* Step detected */ 4525 uint8_t tilt : 1; /* Relative tilt event detected */ 4526 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4527 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 4528 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4529 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4530 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4531 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4532 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4533 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4534 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4535 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4536 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4537 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4538 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4539 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4540 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4541 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4542 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4543 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4544 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4545 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4546 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4547 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4548 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4549 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4550 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4551 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4552 } lsm6dsox_pin_int2_route_t; 4553 4554 int32_t lsm6dsox_pin_int2_route_set(const stmdev_ctx_t *ctx, 4555 stmdev_ctx_t *aux_ctx, 4556 lsm6dsox_pin_int2_route_t val); 4557 int32_t lsm6dsox_pin_int2_route_get(const stmdev_ctx_t *ctx, 4558 stmdev_ctx_t *aux_ctx, 4559 lsm6dsox_pin_int2_route_t *val); 4560 4561 typedef struct 4562 { 4563 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 4564 uint8_t drdy_g : 1; /* Gyroscope data ready */ 4565 uint8_t drdy_temp : 1; /* Temperature data ready */ 4566 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 4567 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 4568 uint8_t free_fall : 1; /* free fall event */ 4569 uint8_t wake_up : 1; /* wake up event */ 4570 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 4571 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 4572 uint8_t wake_up_x : 1; /* wake up on X axis event */ 4573 uint8_t single_tap : 1; /* single-tap event */ 4574 uint8_t double_tap : 1; /* double-tap event */ 4575 uint8_t tap_z : 1; /* single-tap on Z axis event */ 4576 uint8_t tap_y : 1; /* single-tap on Y axis event */ 4577 uint8_t tap_x : 1; /* single-tap on X axis event */ 4578 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 4579 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 4580 uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ 4581 uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ 4582 uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ 4583 uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ 4584 uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ 4585 uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ 4586 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 4587 uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 4588 uint8_t step_detector : 1; /* Step detected */ 4589 uint8_t tilt : 1; /* Relative tilt event detected */ 4590 uint8_t sig_mot : 1; /* "significant motion" event detected */ 4591 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 4592 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 4593 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 4594 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 4595 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 4596 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 4597 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 4598 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 4599 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 4600 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 4601 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 4602 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 4603 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 4604 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 4605 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 4606 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 4607 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 4608 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 4609 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 4610 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 4611 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 4612 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 4613 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 4614 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 4615 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 4616 uint8_t sh_endop : 1; /* sensor hub end operation */ 4617 uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */ 4618 uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */ 4619 uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */ 4620 uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */ 4621 uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ 4622 uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/ 4623 uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ 4624 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 4625 uint8_t fifo_full : 1; /* FIFO full */ 4626 uint8_t fifo_ovr : 1; /* FIFO overrun */ 4627 uint8_t fifo_th : 1; /* FIFO threshold reached */ 4628 } lsm6dsox_all_sources_t; 4629 int32_t lsm6dsox_all_sources_get(const stmdev_ctx_t *ctx, 4630 lsm6dsox_all_sources_t *val); 4631 4632 typedef struct 4633 { 4634 uint8_t odr_fine_tune; 4635 } lsm6dsox_dev_cal_t; 4636 int32_t lsm6dsox_calibration_get(const stmdev_ctx_t *ctx, 4637 lsm6dsox_dev_cal_t *val); 4638 4639 typedef enum 4640 { 4641 LSM6DSOX_XL_UI_OFF = 0x00, /* in power down */ 4642 LSM6DSOX_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ 4643 LSM6DSOX_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */ 4644 LSM6DSOX_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ 4645 LSM6DSOX_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ 4646 LSM6DSOX_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */ 4647 LSM6DSOX_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ 4648 LSM6DSOX_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ 4649 LSM6DSOX_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy, OIS imu off) */ 4650 LSM6DSOX_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ 4651 LSM6DSOX_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ 4652 LSM6DSOX_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy, OIS imu off) */ 4653 LSM6DSOX_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ 4654 LSM6DSOX_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ 4655 LSM6DSOX_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */ 4656 LSM6DSOX_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ 4657 LSM6DSOX_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ 4658 LSM6DSOX_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */ 4659 LSM6DSOX_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ 4660 LSM6DSOX_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ 4661 LSM6DSOX_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ 4662 LSM6DSOX_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ 4663 LSM6DSOX_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ 4664 } lsm6dsox_ui_xl_odr_t; 4665 4666 typedef enum 4667 { 4668 LSM6DSOX_XL_UI_2g = 0, 4669 LSM6DSOX_XL_UI_4g = 2, 4670 LSM6DSOX_XL_UI_8g = 3, 4671 LSM6DSOX_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */ 4672 } lsm6dsox_ui_xl_fs_t; 4673 4674 typedef enum 4675 { 4676 LSM6DSOX_GY_UI_OFF = 0x00, /* gy in power down */ 4677 LSM6DSOX_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ 4678 LSM6DSOX_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ 4679 LSM6DSOX_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ 4680 LSM6DSOX_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ 4681 LSM6DSOX_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ 4682 LSM6DSOX_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ 4683 LSM6DSOX_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ 4684 LSM6DSOX_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ 4685 LSM6DSOX_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ 4686 LSM6DSOX_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ 4687 LSM6DSOX_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ 4688 LSM6DSOX_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ 4689 LSM6DSOX_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ 4690 LSM6DSOX_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ 4691 LSM6DSOX_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ 4692 } lsm6dsox_ui_gy_odr_t; 4693 4694 typedef enum 4695 { 4696 LSM6DSOX_GY_UI_250dps = 0, 4697 LSM6DSOX_GY_UI_125dps = 1, 4698 LSM6DSOX_GY_UI_500dps = 2, 4699 LSM6DSOX_GY_UI_1000dps = 4, 4700 LSM6DSOX_GY_UI_2000dps = 6, 4701 } lsm6dsox_ui_gy_fs_t; 4702 4703 typedef enum 4704 { 4705 LSM6DSOX_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */ 4706 LSM6DSOX_OIS_ONLY_UI = 0x02, /* Primary interface full control */ 4707 LSM6DSOX_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */ 4708 } lsm6dsox_ois_ctrl_md_t; 4709 4710 typedef enum 4711 { 4712 LSM6DSOX_XL_OIS_OFF = 0x00, /* in power down */ 4713 LSM6DSOX_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */ 4714 } lsm6dsox_ois_xl_odr_t; 4715 4716 typedef enum 4717 { 4718 LSM6DSOX_XL_OIS_2g = 0, 4719 LSM6DSOX_XL_OIS_4g = 2, 4720 LSM6DSOX_XL_OIS_8g = 3, 4721 LSM6DSOX_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */ 4722 } lsm6dsox_ois_xl_fs_t; 4723 4724 typedef enum 4725 { 4726 LSM6DSOX_GY_OIS_OFF = 0x00, /* in power down */ 4727 LSM6DSOX_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/ 4728 } lsm6dsox_ois_gy_odr_t; 4729 4730 typedef enum 4731 { 4732 LSM6DSOX_GY_OIS_250dps = 0, 4733 LSM6DSOX_GY_OIS_125dps = 1, 4734 LSM6DSOX_GY_OIS_500dps = 2, 4735 LSM6DSOX_GY_OIS_1000dps = 4, 4736 LSM6DSOX_GY_OIS_2000dps = 6, 4737 } lsm6dsox_ois_gy_fs_t; 4738 4739 typedef enum 4740 { 4741 LSM6DSOX_FSM_DISABLE = 0x00, 4742 LSM6DSOX_FSM_XL = 0x01, 4743 LSM6DSOX_FSM_GY = 0x02, 4744 LSM6DSOX_FSM_XL_GY = 0x03, 4745 } lsm6dsox_fsm_sens_t; 4746 4747 typedef enum 4748 { 4749 LSM6DSOX_MLC_DISABLE = 0x00, 4750 LSM6DSOX_MLC_XL = 0x01, 4751 LSM6DSOX_MLC_XL_GY = 0x03, 4752 } lsm6dsox_mlc_sens_t; 4753 4754 typedef struct 4755 { 4756 struct 4757 { 4758 struct 4759 { 4760 lsm6dsox_ui_xl_odr_t odr; 4761 lsm6dsox_ui_xl_fs_t fs; 4762 } xl; 4763 struct 4764 { 4765 lsm6dsox_ui_gy_odr_t odr; 4766 lsm6dsox_ui_gy_fs_t fs; 4767 } gy; 4768 } ui; 4769 struct 4770 { 4771 lsm6dsox_ois_ctrl_md_t ctrl_md; 4772 struct 4773 { 4774 lsm6dsox_ois_xl_odr_t odr; 4775 lsm6dsox_ois_xl_fs_t fs; 4776 } xl; 4777 struct 4778 { 4779 lsm6dsox_ois_gy_odr_t odr; 4780 lsm6dsox_ois_gy_fs_t fs; 4781 } gy; 4782 } ois; 4783 struct 4784 { 4785 lsm6dsox_fsm_sens_t sens; 4786 lsm6dsox_fsm_odr_t odr; 4787 } fsm; 4788 struct 4789 { 4790 lsm6dsox_mlc_sens_t sens; 4791 lsm6dsox_mlc_odr_t odr; 4792 } mlc; 4793 } lsm6dsox_md_t; 4794 int32_t lsm6dsox_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4795 lsm6dsox_md_t *val); 4796 int32_t lsm6dsox_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4797 lsm6dsox_md_t *val); 4798 4799 typedef struct 4800 { 4801 struct 4802 { 4803 struct 4804 { 4805 float_t mg[3]; 4806 int16_t raw[3]; 4807 } xl; 4808 struct 4809 { 4810 float_t mdps[3]; 4811 int16_t raw[3]; 4812 } gy; 4813 struct 4814 { 4815 float_t deg_c; 4816 int16_t raw; 4817 } heat; 4818 } ui; 4819 struct 4820 { 4821 struct 4822 { 4823 float_t mg[3]; 4824 int16_t raw[3]; 4825 } xl; 4826 struct 4827 { 4828 float_t mdps[3]; 4829 int16_t raw[3]; 4830 } gy; 4831 } ois; 4832 } lsm6dsox_data_t; 4833 int32_t lsm6dsox_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx, 4834 lsm6dsox_md_t *md, lsm6dsox_data_t *data); 4835 4836 typedef struct 4837 { 4838 uint8_t sig_mot : 1; /* significant motion */ 4839 uint8_t tilt : 1; /* tilt detection */ 4840 uint8_t step : 1; /* step counter/detector */ 4841 uint8_t mlc : 1; /* machine learning core */ 4842 uint8_t fsm : 1; /* finite state machine */ 4843 uint8_t fifo_compr : 1; /* mlc 8 interrupt event */ 4844 } lsm6dsox_emb_sens_t; 4845 int32_t lsm6dsox_embedded_sens_set(const stmdev_ctx_t *ctx, 4846 lsm6dsox_emb_sens_t *emb_sens); 4847 int32_t lsm6dsox_embedded_sens_get(const stmdev_ctx_t *ctx, 4848 lsm6dsox_emb_sens_t *emb_sens); 4849 int32_t lsm6dsox_embedded_sens_off(const stmdev_ctx_t *ctx); 4850 4851 /** 4852 * @} 4853 * 4854 */ 4855 4856 #ifdef __cplusplus 4857 } 4858 #endif 4859 4860 #endif /*LSM6DSOX_DRIVER_H */ 4861 4862 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 4863
