1 /** 2 ****************************************************************************** 3 * @file lsm6dso32_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dso32_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSO32_REGS_H 23 #define LSM6DSO32_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSO32 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSO32_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSO32_I2C_ADD_L 0xD5 173 #define LSM6DSO32_I2C_ADD_H 0xD7 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSO32_ID 0x6C 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSO32_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_00 : 6; 188 uint8_t reg_access : 189 2; /* shub_reg_access + func_cfg_access */ 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t reg_access : 192 2; /* shub_reg_access + func_cfg_access */ 193 uint8_t not_used_00 : 6; 194 #endif /* DRV_BYTE_ORDER */ 195 } lsm6dso32_func_cfg_access_t; 196 197 #define LSM6DSO32_PIN_CTRL 0x02U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t not_used_01 : 6; 202 uint8_t sdo_pu_en : 1; 203 uint8_t not_used_02 : 1; 204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 205 uint8_t not_used_02 : 1; 206 uint8_t sdo_pu_en : 1; 207 uint8_t not_used_01 : 6; 208 #endif /* DRV_BYTE_ORDER */ 209 } lsm6dso32_pin_ctrl_t; 210 211 #define LSM6DSO32_FIFO_CTRL1 0x07U 212 typedef struct 213 { 214 uint8_t wtm : 8; 215 } lsm6dso32_fifo_ctrl1_t; 216 217 #define LSM6DSO32_FIFO_CTRL2 0x08U 218 typedef struct 219 { 220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 221 uint8_t wtm : 1; 222 uint8_t uncoptr_rate : 2; 223 uint8_t not_used_01 : 1; 224 uint8_t odrchg_en : 1; 225 uint8_t not_used_02 : 1; 226 uint8_t fifo_compr_rt_en : 1; 227 uint8_t stop_on_wtm : 1; 228 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 229 uint8_t stop_on_wtm : 1; 230 uint8_t fifo_compr_rt_en : 1; 231 uint8_t not_used_02 : 1; 232 uint8_t odrchg_en : 1; 233 uint8_t not_used_01 : 1; 234 uint8_t uncoptr_rate : 2; 235 uint8_t wtm : 1; 236 #endif /* DRV_BYTE_ORDER */ 237 } lsm6dso32_fifo_ctrl2_t; 238 239 #define LSM6DSO32_FIFO_CTRL3 0x09U 240 typedef struct 241 { 242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 243 uint8_t bdr_xl : 4; 244 uint8_t bdr_gy : 4; 245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 246 uint8_t bdr_gy : 4; 247 uint8_t bdr_xl : 4; 248 #endif /* DRV_BYTE_ORDER */ 249 } lsm6dso32_fifo_ctrl3_t; 250 251 #define LSM6DSO32_FIFO_CTRL4 0x0AU 252 typedef struct 253 { 254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 255 uint8_t fifo_mode : 3; 256 uint8_t not_used_01 : 1; 257 uint8_t odr_t_batch : 2; 258 uint8_t odr_ts_batch : 2; 259 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 260 uint8_t odr_ts_batch : 2; 261 uint8_t odr_t_batch : 2; 262 uint8_t not_used_01 : 1; 263 uint8_t fifo_mode : 3; 264 #endif /* DRV_BYTE_ORDER */ 265 } lsm6dso32_fifo_ctrl4_t; 266 267 #define LSM6DSO32_COUNTER_BDR_REG1 0x0BU 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t cnt_bdr_th : 3; 272 uint8_t not_used_01 : 2; 273 uint8_t trig_counter_bdr : 1; 274 uint8_t rst_counter_bdr : 1; 275 uint8_t dataready_pulsed : 1; 276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 277 uint8_t dataready_pulsed : 1; 278 uint8_t rst_counter_bdr : 1; 279 uint8_t trig_counter_bdr : 1; 280 uint8_t not_used_01 : 2; 281 uint8_t cnt_bdr_th : 3; 282 #endif /* DRV_BYTE_ORDER */ 283 } lsm6dso32_counter_bdr_reg1_t; 284 285 #define LSM6DSO32_COUNTER_BDR_REG2 0x0CU 286 typedef struct 287 { 288 uint8_t cnt_bdr_th : 8; 289 } lsm6dso32_counter_bdr_reg2_t; 290 291 #define LSM6DSO32_INT1_CTRL 0x0DU 292 typedef struct 293 { 294 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 295 uint8_t int1_drdy_xl : 1; 296 uint8_t int1_drdy_g : 1; 297 uint8_t int1_boot : 1; 298 uint8_t int1_fifo_th : 1; 299 uint8_t int1_fifo_ovr : 1; 300 uint8_t int1_fifo_full : 1; 301 uint8_t int1_cnt_bdr : 1; 302 uint8_t den_drdy_flag : 1; 303 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 304 uint8_t den_drdy_flag : 1; 305 uint8_t int1_cnt_bdr : 1; 306 uint8_t int1_fifo_full : 1; 307 uint8_t int1_fifo_ovr : 1; 308 uint8_t int1_fifo_th : 1; 309 uint8_t int1_boot : 1; 310 uint8_t int1_drdy_g : 1; 311 uint8_t int1_drdy_xl : 1; 312 #endif /* DRV_BYTE_ORDER */ 313 } lsm6dso32_int1_ctrl_t; 314 315 #define LSM6DSO32_INT2_CTRL 0x0EU 316 typedef struct 317 { 318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 319 uint8_t int2_drdy_xl : 1; 320 uint8_t int2_drdy_g : 1; 321 uint8_t int2_drdy_temp : 1; 322 uint8_t int2_fifo_th : 1; 323 uint8_t int2_fifo_ovr : 1; 324 uint8_t int2_fifo_full : 1; 325 uint8_t int2_cnt_bdr : 1; 326 uint8_t not_used_01 : 1; 327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 328 uint8_t not_used_01 : 1; 329 uint8_t int2_cnt_bdr : 1; 330 uint8_t int2_fifo_full : 1; 331 uint8_t int2_fifo_ovr : 1; 332 uint8_t int2_fifo_th : 1; 333 uint8_t int2_drdy_temp : 1; 334 uint8_t int2_drdy_g : 1; 335 uint8_t int2_drdy_xl : 1; 336 #endif /* DRV_BYTE_ORDER */ 337 } lsm6dso32_int2_ctrl_t; 338 339 #define LSM6DSO32_WHO_AM_I 0x0FU 340 #define LSM6DSO32_CTRL1_XL 0x10U 341 typedef struct 342 { 343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 344 uint8_t not_used_01 : 1; 345 uint8_t lpf2_xl_en : 1; 346 uint8_t fs_xl : 2; 347 uint8_t odr_xl : 4; 348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 349 uint8_t odr_xl : 4; 350 uint8_t fs_xl : 2; 351 uint8_t lpf2_xl_en : 1; 352 uint8_t not_used_01 : 1; 353 #endif /* DRV_BYTE_ORDER */ 354 } lsm6dso32_ctrl1_xl_t; 355 356 #define LSM6DSO32_CTRL2_G 0x11U 357 typedef struct 358 { 359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 360 uint8_t not_used_01 : 1; 361 uint8_t fs_g : 3; /* fs_125 + fs_g */ 362 uint8_t odr_g : 4; 363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 364 uint8_t odr_g : 4; 365 uint8_t fs_g : 3; /* fs_125 + fs_g */ 366 uint8_t not_used_01 : 1; 367 #endif /* DRV_BYTE_ORDER */ 368 } lsm6dso32_ctrl2_g_t; 369 370 #define LSM6DSO32_CTRL3_C 0x12U 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t sw_reset : 1; 375 uint8_t not_used_01 : 1; 376 uint8_t if_inc : 1; 377 uint8_t sim : 1; 378 uint8_t pp_od : 1; 379 uint8_t h_lactive : 1; 380 uint8_t bdu : 1; 381 uint8_t boot : 1; 382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 383 uint8_t boot : 1; 384 uint8_t bdu : 1; 385 uint8_t h_lactive : 1; 386 uint8_t pp_od : 1; 387 uint8_t sim : 1; 388 uint8_t if_inc : 1; 389 uint8_t not_used_01 : 1; 390 uint8_t sw_reset : 1; 391 #endif /* DRV_BYTE_ORDER */ 392 } lsm6dso32_ctrl3_c_t; 393 394 #define LSM6DSO32_CTRL4_C 0x13U 395 typedef struct 396 { 397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 398 uint8_t not_used_01 : 1; 399 uint8_t lpf1_sel_g : 1; 400 uint8_t i2c_disable : 1; 401 uint8_t drdy_mask : 1; 402 uint8_t not_used_02 : 1; 403 uint8_t int2_on_int1 : 1; 404 uint8_t sleep_g : 1; 405 uint8_t not_used_03 : 1; 406 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 407 uint8_t not_used_03 : 1; 408 uint8_t sleep_g : 1; 409 uint8_t int2_on_int1 : 1; 410 uint8_t not_used_02 : 1; 411 uint8_t drdy_mask : 1; 412 uint8_t i2c_disable : 1; 413 uint8_t lpf1_sel_g : 1; 414 uint8_t not_used_01 : 1; 415 #endif /* DRV_BYTE_ORDER */ 416 } lsm6dso32_ctrl4_c_t; 417 418 #define LSM6DSO32_CTRL5_C 0x14U 419 typedef struct 420 { 421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 422 uint8_t st_xl : 2; 423 uint8_t st_g : 2; 424 uint8_t not_used_01 : 1; 425 uint8_t rounding : 2; 426 uint8_t xl_ulp_en : 1; 427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 428 uint8_t xl_ulp_en : 1; 429 uint8_t rounding : 2; 430 uint8_t not_used_01 : 1; 431 uint8_t st_g : 2; 432 uint8_t st_xl : 2; 433 #endif /* DRV_BYTE_ORDER */ 434 } lsm6dso32_ctrl5_c_t; 435 436 #define LSM6DSO32_CTRL6_C 0x15U 437 typedef struct 438 { 439 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 440 uint8_t ftype : 3; 441 uint8_t usr_off_w : 1; 442 uint8_t xl_hm_mode : 1; 443 uint8_t den_mode : 444 3; /* trig_en + lvl1_en + lvl2_en */ 445 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 446 uint8_t den_mode : 447 3; /* trig_en + lvl1_en + lvl2_en */ 448 uint8_t xl_hm_mode : 1; 449 uint8_t usr_off_w : 1; 450 uint8_t ftype : 3; 451 #endif /* DRV_BYTE_ORDER */ 452 } lsm6dso32_ctrl6_c_t; 453 454 #define LSM6DSO32_CTRL7_G 0x16U 455 typedef struct 456 { 457 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 458 uint8_t not_used_01 : 1; 459 uint8_t usr_off_on_out : 1; 460 uint8_t not_used_02 : 2; 461 uint8_t hpm_g : 2; 462 uint8_t hp_en_g : 1; 463 uint8_t g_hm_mode : 1; 464 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 465 uint8_t g_hm_mode : 1; 466 uint8_t hp_en_g : 1; 467 uint8_t hpm_g : 2; 468 uint8_t not_used_02 : 2; 469 uint8_t usr_off_on_out : 1; 470 uint8_t not_used_01 : 1; 471 #endif /* DRV_BYTE_ORDER */ 472 } lsm6dso32_ctrl7_g_t; 473 474 #define LSM6DSO32_CTRL8_XL 0x17U 475 typedef struct 476 { 477 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 478 uint8_t low_pass_on_6d : 1; 479 uint8_t not_used_01 : 1; 480 uint8_t hp_slope_xl_en : 1; 481 uint8_t fastsettl_mode_xl : 1; 482 uint8_t hp_ref_mode_xl : 1; 483 uint8_t hpcf_xl : 3; 484 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 485 uint8_t hpcf_xl : 3; 486 uint8_t hp_ref_mode_xl : 1; 487 uint8_t fastsettl_mode_xl : 1; 488 uint8_t hp_slope_xl_en : 1; 489 uint8_t not_used_01 : 1; 490 uint8_t low_pass_on_6d : 1; 491 #endif /* DRV_BYTE_ORDER */ 492 } lsm6dso32_ctrl8_xl_t; 493 494 #define LSM6DSO32_CTRL9_XL 0x18U 495 typedef struct 496 { 497 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 498 uint8_t not_used_01 : 1; 499 uint8_t i3c_disable : 1; 500 uint8_t den_lh : 1; 501 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 502 uint8_t den_z : 1; 503 uint8_t den_y : 1; 504 uint8_t den_x : 1; 505 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 506 uint8_t den_x : 1; 507 uint8_t den_y : 1; 508 uint8_t den_z : 1; 509 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 510 uint8_t den_lh : 1; 511 uint8_t i3c_disable : 1; 512 uint8_t not_used_01 : 1; 513 #endif /* DRV_BYTE_ORDER */ 514 } lsm6dso32_ctrl9_xl_t; 515 516 #define LSM6DSO32_CTRL10_C 0x19U 517 typedef struct 518 { 519 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 520 uint8_t not_used_01 : 5; 521 uint8_t timestamp_en : 1; 522 uint8_t not_used_02 : 2; 523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 524 uint8_t not_used_02 : 2; 525 uint8_t timestamp_en : 1; 526 uint8_t not_used_01 : 5; 527 #endif /* DRV_BYTE_ORDER */ 528 } lsm6dso32_ctrl10_c_t; 529 530 #define LSM6DSO32_ALL_INT_SRC 0x1AU 531 typedef struct 532 { 533 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 534 uint8_t ff_ia : 1; 535 uint8_t wu_ia : 1; 536 uint8_t single_tap : 1; 537 uint8_t double_tap : 1; 538 uint8_t d6d_ia : 1; 539 uint8_t sleep_change_ia : 1; 540 uint8_t not_used_01 : 1; 541 uint8_t timestamp_endcount : 1; 542 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 543 uint8_t timestamp_endcount : 1; 544 uint8_t not_used_01 : 1; 545 uint8_t sleep_change_ia : 1; 546 uint8_t d6d_ia : 1; 547 uint8_t double_tap : 1; 548 uint8_t single_tap : 1; 549 uint8_t wu_ia : 1; 550 uint8_t ff_ia : 1; 551 #endif /* DRV_BYTE_ORDER */ 552 } lsm6dso32_all_int_src_t; 553 554 #define LSM6DSO32_WAKE_UP_SRC 0x1BU 555 typedef struct 556 { 557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 558 uint8_t z_wu : 1; 559 uint8_t y_wu : 1; 560 uint8_t x_wu : 1; 561 uint8_t wu_ia : 1; 562 uint8_t sleep_state : 1; 563 uint8_t ff_ia : 1; 564 uint8_t sleep_change_ia : 1; 565 uint8_t not_used_01 : 1; 566 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 567 uint8_t not_used_01 : 1; 568 uint8_t sleep_change_ia : 1; 569 uint8_t ff_ia : 1; 570 uint8_t sleep_state : 1; 571 uint8_t wu_ia : 1; 572 uint8_t x_wu : 1; 573 uint8_t y_wu : 1; 574 uint8_t z_wu : 1; 575 #endif /* DRV_BYTE_ORDER */ 576 } lsm6dso32_wake_up_src_t; 577 578 #define LSM6DSO32_TAP_SRC 0x1CU 579 typedef struct 580 { 581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 582 uint8_t z_tap : 1; 583 uint8_t y_tap : 1; 584 uint8_t x_tap : 1; 585 uint8_t tap_sign : 1; 586 uint8_t double_tap : 1; 587 uint8_t single_tap : 1; 588 uint8_t tap_ia : 1; 589 uint8_t not_used_02 : 1; 590 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 591 uint8_t not_used_02 : 1; 592 uint8_t tap_ia : 1; 593 uint8_t single_tap : 1; 594 uint8_t double_tap : 1; 595 uint8_t tap_sign : 1; 596 uint8_t x_tap : 1; 597 uint8_t y_tap : 1; 598 uint8_t z_tap : 1; 599 #endif /* DRV_BYTE_ORDER */ 600 } lsm6dso32_tap_src_t; 601 602 #define LSM6DSO32_D6D_SRC 0x1DU 603 typedef struct 604 { 605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 606 uint8_t xl : 1; 607 uint8_t xh : 1; 608 uint8_t yl : 1; 609 uint8_t yh : 1; 610 uint8_t zl : 1; 611 uint8_t zh : 1; 612 uint8_t d6d_ia : 1; 613 uint8_t den_drdy : 1; 614 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 615 uint8_t den_drdy : 1; 616 uint8_t d6d_ia : 1; 617 uint8_t zh : 1; 618 uint8_t zl : 1; 619 uint8_t yh : 1; 620 uint8_t yl : 1; 621 uint8_t xh : 1; 622 uint8_t xl : 1; 623 #endif /* DRV_BYTE_ORDER */ 624 } lsm6dso32_d6d_src_t; 625 626 #define LSM6DSO32_STATUS_REG 0x1EU 627 typedef struct 628 { 629 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 630 uint8_t xlda : 1; 631 uint8_t gda : 1; 632 uint8_t tda : 1; 633 uint8_t not_used_01 : 5; 634 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 635 uint8_t not_used_01 : 5; 636 uint8_t tda : 1; 637 uint8_t gda : 1; 638 uint8_t xlda : 1; 639 #endif /* DRV_BYTE_ORDER */ 640 } lsm6dso32_status_reg_t; 641 642 #define LSM6DSO32_OUT_TEMP_L 0x20U 643 #define LSM6DSO32_OUT_TEMP_H 0x21U 644 #define LSM6DSO32_OUTX_L_G 0x22U 645 #define LSM6DSO32_OUTX_H_G 0x23U 646 #define LSM6DSO32_OUTY_L_G 0x24U 647 #define LSM6DSO32_OUTY_H_G 0x25U 648 #define LSM6DSO32_OUTZ_L_G 0x26U 649 #define LSM6DSO32_OUTZ_H_G 0x27U 650 #define LSM6DSO32_OUTX_L_A 0x28U 651 #define LSM6DSO32_OUTX_H_A 0x29U 652 #define LSM6DSO32_OUTY_L_A 0x2AU 653 #define LSM6DSO32_OUTY_H_A 0x2BU 654 #define LSM6DSO32_OUTZ_L_A 0x2CU 655 #define LSM6DSO32_OUTZ_H_A 0x2DU 656 #define LSM6DSO32_EMB_FUNC_STATUS_MAINPAGE 0x35U 657 typedef struct 658 { 659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 660 uint8_t not_used_01 : 3; 661 uint8_t is_step_det : 1; 662 uint8_t is_tilt : 1; 663 uint8_t is_sigmot : 1; 664 uint8_t not_used_02 : 1; 665 uint8_t is_fsm_lc : 1; 666 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 667 uint8_t is_fsm_lc : 1; 668 uint8_t not_used_02 : 1; 669 uint8_t is_sigmot : 1; 670 uint8_t is_tilt : 1; 671 uint8_t is_step_det : 1; 672 uint8_t not_used_01 : 3; 673 #endif /* DRV_BYTE_ORDER */ 674 } lsm6dso32_emb_func_status_mainpage_t; 675 676 #define LSM6DSO32_FSM_STATUS_A_MAINPAGE 0x36U 677 typedef struct 678 { 679 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 680 uint8_t is_fsm1 : 1; 681 uint8_t is_fsm2 : 1; 682 uint8_t is_fsm3 : 1; 683 uint8_t is_fsm4 : 1; 684 uint8_t is_fsm5 : 1; 685 uint8_t is_fsm6 : 1; 686 uint8_t is_fsm7 : 1; 687 uint8_t is_fsm8 : 1; 688 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 689 uint8_t is_fsm8 : 1; 690 uint8_t is_fsm7 : 1; 691 uint8_t is_fsm6 : 1; 692 uint8_t is_fsm5 : 1; 693 uint8_t is_fsm4 : 1; 694 uint8_t is_fsm3 : 1; 695 uint8_t is_fsm2 : 1; 696 uint8_t is_fsm1 : 1; 697 #endif /* DRV_BYTE_ORDER */ 698 } lsm6dso32_fsm_status_a_mainpage_t; 699 700 #define LSM6DSO32_FSM_STATUS_B_MAINPAGE 0x37U 701 typedef struct 702 { 703 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 704 uint8_t is_fsm9 : 1; 705 uint8_t is_fsm10 : 1; 706 uint8_t is_fsm11 : 1; 707 uint8_t is_fsm12 : 1; 708 uint8_t is_fsm13 : 1; 709 uint8_t is_fsm14 : 1; 710 uint8_t is_fsm15 : 1; 711 uint8_t is_fsm16 : 1; 712 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 713 uint8_t is_fsm16 : 1; 714 uint8_t is_fsm15 : 1; 715 uint8_t is_fsm14 : 1; 716 uint8_t is_fsm13 : 1; 717 uint8_t is_fsm12 : 1; 718 uint8_t is_fsm11 : 1; 719 uint8_t is_fsm10 : 1; 720 uint8_t is_fsm9 : 1; 721 #endif /* DRV_BYTE_ORDER */ 722 } lsm6dso32_fsm_status_b_mainpage_t; 723 724 #define LSM6DSO32_STATUS_MASTER_MAINPAGE 0x39U 725 typedef struct 726 { 727 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 728 uint8_t sens_hub_endop : 1; 729 uint8_t not_used_01 : 2; 730 uint8_t slave0_nack : 1; 731 uint8_t slave1_nack : 1; 732 uint8_t slave2_nack : 1; 733 uint8_t slave3_nack : 1; 734 uint8_t wr_once_done : 1; 735 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 736 uint8_t wr_once_done : 1; 737 uint8_t slave3_nack : 1; 738 uint8_t slave2_nack : 1; 739 uint8_t slave1_nack : 1; 740 uint8_t slave0_nack : 1; 741 uint8_t not_used_01 : 2; 742 uint8_t sens_hub_endop : 1; 743 #endif /* DRV_BYTE_ORDER */ 744 } lsm6dso32_status_master_mainpage_t; 745 746 #define LSM6DSO32_FIFO_STATUS1 0x3AU 747 typedef struct 748 { 749 uint8_t diff_fifo : 8; 750 } lsm6dso32_fifo_status1_t; 751 752 #define LSM6DSO32_FIFO_STATUS2 0x3B 753 typedef struct 754 { 755 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 756 uint8_t diff_fifo : 2; 757 uint8_t not_used_01 : 1; 758 uint8_t over_run_latched : 1; 759 uint8_t counter_bdr_ia : 1; 760 uint8_t fifo_full_ia : 1; 761 uint8_t fifo_ovr_ia : 1; 762 uint8_t fifo_wtm_ia : 1; 763 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 764 uint8_t fifo_wtm_ia : 1; 765 uint8_t fifo_ovr_ia : 1; 766 uint8_t fifo_full_ia : 1; 767 uint8_t counter_bdr_ia : 1; 768 uint8_t over_run_latched : 1; 769 uint8_t not_used_01 : 1; 770 uint8_t diff_fifo : 2; 771 #endif /* DRV_BYTE_ORDER */ 772 } lsm6dso32_fifo_status2_t; 773 774 #define LSM6DSO32_TIMESTAMP0 0x40U 775 #define LSM6DSO32_TIMESTAMP1 0x41U 776 #define LSM6DSO32_TIMESTAMP2 0x42U 777 #define LSM6DSO32_TIMESTAMP3 0x43U 778 779 #define LSM6DSO32_TAP_CFG0 0x56U 780 typedef struct 781 { 782 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 783 uint8_t lir : 1; 784 uint8_t tap_z_en : 1; 785 uint8_t tap_y_en : 1; 786 uint8_t tap_x_en : 1; 787 uint8_t slope_fds : 1; 788 uint8_t sleep_status_on_int : 1; 789 uint8_t int_clr_on_read : 1; 790 uint8_t not_used_01 : 1; 791 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 792 uint8_t not_used_01 : 1; 793 uint8_t int_clr_on_read : 1; 794 uint8_t sleep_status_on_int : 1; 795 uint8_t slope_fds : 1; 796 uint8_t tap_x_en : 1; 797 uint8_t tap_y_en : 1; 798 uint8_t tap_z_en : 1; 799 uint8_t lir : 1; 800 #endif /* DRV_BYTE_ORDER */ 801 } lsm6dso32_tap_cfg0_t; 802 803 #define LSM6DSO32_TAP_CFG1 0x57U 804 typedef struct 805 { 806 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 807 uint8_t tap_ths_x : 5; 808 uint8_t tap_priority : 3; 809 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 810 uint8_t tap_priority : 3; 811 uint8_t tap_ths_x : 5; 812 #endif /* DRV_BYTE_ORDER */ 813 } lsm6dso32_tap_cfg1_t; 814 815 #define LSM6DSO32_TAP_CFG2 0x58U 816 typedef struct 817 { 818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 819 uint8_t tap_ths_y : 5; 820 uint8_t inact_en : 2; 821 uint8_t interrupts_enable : 1; 822 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 823 uint8_t interrupts_enable : 1; 824 uint8_t inact_en : 2; 825 uint8_t tap_ths_y : 5; 826 #endif /* DRV_BYTE_ORDER */ 827 } lsm6dso32_tap_cfg2_t; 828 829 #define LSM6DSO32_TAP_THS_6D 0x59U 830 typedef struct 831 { 832 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 833 uint8_t tap_ths_z : 5; 834 uint8_t sixd_ths : 2; 835 uint8_t d4d_en : 1; 836 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 837 uint8_t d4d_en : 1; 838 uint8_t sixd_ths : 2; 839 uint8_t tap_ths_z : 5; 840 #endif /* DRV_BYTE_ORDER */ 841 } lsm6dso32_tap_ths_6d_t; 842 843 #define LSM6DSO32_INT_DUR2 0x5AU 844 typedef struct 845 { 846 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 847 uint8_t shock : 2; 848 uint8_t quiet : 2; 849 uint8_t dur : 4; 850 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 851 uint8_t dur : 4; 852 uint8_t quiet : 2; 853 uint8_t shock : 2; 854 #endif /* DRV_BYTE_ORDER */ 855 } lsm6dso32_int_dur2_t; 856 857 #define LSM6DSO32_WAKE_UP_THS 0x5BU 858 typedef struct 859 { 860 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 861 uint8_t wk_ths : 6; 862 uint8_t usr_off_on_wu : 1; 863 uint8_t single_double_tap : 1; 864 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 865 uint8_t single_double_tap : 1; 866 uint8_t usr_off_on_wu : 1; 867 uint8_t wk_ths : 6; 868 #endif /* DRV_BYTE_ORDER */ 869 } lsm6dso32_wake_up_ths_t; 870 871 #define LSM6DSO32_WAKE_UP_DUR 0x5CU 872 typedef struct 873 { 874 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 875 uint8_t sleep_dur : 4; 876 uint8_t wake_ths_w : 1; 877 uint8_t wake_dur : 2; 878 uint8_t ff_dur : 1; 879 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 880 uint8_t ff_dur : 1; 881 uint8_t wake_dur : 2; 882 uint8_t wake_ths_w : 1; 883 uint8_t sleep_dur : 4; 884 #endif /* DRV_BYTE_ORDER */ 885 } lsm6dso32_wake_up_dur_t; 886 887 #define LSM6DSO32_FREE_FALL 0x5DU 888 typedef struct 889 { 890 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 891 uint8_t ff_ths : 3; 892 uint8_t ff_dur : 5; 893 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 894 uint8_t ff_dur : 5; 895 uint8_t ff_ths : 3; 896 #endif /* DRV_BYTE_ORDER */ 897 } lsm6dso32_free_fall_t; 898 899 #define LSM6DSO32_MD1_CFG 0x5EU 900 typedef struct 901 { 902 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 903 uint8_t int1_shub : 1; 904 uint8_t int1_emb_func : 1; 905 uint8_t int1_6d : 1; 906 uint8_t int1_double_tap : 1; 907 uint8_t int1_ff : 1; 908 uint8_t int1_wu : 1; 909 uint8_t int1_single_tap : 1; 910 uint8_t int1_sleep_change : 1; 911 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 912 uint8_t int1_sleep_change : 1; 913 uint8_t int1_single_tap : 1; 914 uint8_t int1_wu : 1; 915 uint8_t int1_ff : 1; 916 uint8_t int1_double_tap : 1; 917 uint8_t int1_6d : 1; 918 uint8_t int1_emb_func : 1; 919 uint8_t int1_shub : 1; 920 #endif /* DRV_BYTE_ORDER */ 921 } lsm6dso32_md1_cfg_t; 922 923 #define LSM6DSO32_MD2_CFG 0x5FU 924 typedef struct 925 { 926 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 927 uint8_t int2_timestamp : 1; 928 uint8_t int2_emb_func : 1; 929 uint8_t int2_6d : 1; 930 uint8_t int2_double_tap : 1; 931 uint8_t int2_ff : 1; 932 uint8_t int2_wu : 1; 933 uint8_t int2_single_tap : 1; 934 uint8_t int2_sleep_change : 1; 935 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 936 uint8_t int2_sleep_change : 1; 937 uint8_t int2_single_tap : 1; 938 uint8_t int2_wu : 1; 939 uint8_t int2_ff : 1; 940 uint8_t int2_double_tap : 1; 941 uint8_t int2_6d : 1; 942 uint8_t int2_emb_func : 1; 943 uint8_t int2_timestamp : 1; 944 #endif /* DRV_BYTE_ORDER */ 945 } lsm6dso32_md2_cfg_t; 946 947 #define LSM6DSO32_I3C_BUS_AVB 0x62U 948 typedef struct 949 { 950 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 951 uint8_t pd_dis_int1 : 1; 952 uint8_t not_used_01 : 2; 953 uint8_t i3c_bus_avb_sel : 2; 954 uint8_t not_used_02 : 3; 955 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 956 uint8_t not_used_02 : 3; 957 uint8_t i3c_bus_avb_sel : 2; 958 uint8_t not_used_01 : 2; 959 uint8_t pd_dis_int1 : 1; 960 #endif /* DRV_BYTE_ORDER */ 961 } lsm6dso32_i3c_bus_avb_t; 962 963 #define LSM6DSO32_INTERNAL_FREQ_FINE 0x63U 964 typedef struct 965 { 966 uint8_t freq_fine : 8; 967 } lsm6dso32_internal_freq_fine_t; 968 969 #define LSM6DSO32_X_OFS_USR 0x73U 970 #define LSM6DSO32_Y_OFS_USR 0x74U 971 #define LSM6DSO32_Z_OFS_USR 0x75U 972 #define LSM6DSO32_FIFO_DATA_OUT_TAG 0x78U 973 typedef struct 974 { 975 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 976 uint8_t tag_parity : 1; 977 uint8_t tag_cnt : 2; 978 uint8_t tag_sensor : 5; 979 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 980 uint8_t tag_sensor : 5; 981 uint8_t tag_cnt : 2; 982 uint8_t tag_parity : 1; 983 #endif /* DRV_BYTE_ORDER */ 984 } lsm6dso32_fifo_data_out_tag_t; 985 986 #define LSM6DSO32_FIFO_DATA_OUT_X_L 0x79U 987 #define LSM6DSO32_FIFO_DATA_OUT_X_H 0x7AU 988 #define LSM6DSO32_FIFO_DATA_OUT_Y_L 0x7BU 989 #define LSM6DSO32_FIFO_DATA_OUT_Y_H 0x7CU 990 #define LSM6DSO32_FIFO_DATA_OUT_Z_L 0x7DU 991 #define LSM6DSO32_FIFO_DATA_OUT_Z_H 0x7EU 992 #define LSM6DSO32_PAGE_SEL 0x02U 993 typedef struct 994 { 995 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 996 uint8_t not_used_01 : 4; 997 uint8_t page_sel : 4; 998 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 999 uint8_t page_sel : 4; 1000 uint8_t not_used_01 : 4; 1001 #endif /* DRV_BYTE_ORDER */ 1002 } lsm6dso32_page_sel_t; 1003 1004 #define LSM6DSO32_EMB_FUNC_EN_A 0x04U 1005 typedef struct 1006 { 1007 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1008 uint8_t not_used_01 : 3; 1009 uint8_t pedo_en : 1; 1010 uint8_t tilt_en : 1; 1011 uint8_t sign_motion_en : 1; 1012 uint8_t not_used_02 : 2; 1013 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1014 uint8_t not_used_02 : 2; 1015 uint8_t sign_motion_en : 1; 1016 uint8_t tilt_en : 1; 1017 uint8_t pedo_en : 1; 1018 uint8_t not_used_01 : 3; 1019 #endif /* DRV_BYTE_ORDER */ 1020 } lsm6dso32_emb_func_en_a_t; 1021 1022 #define LSM6DSO32_EMB_FUNC_EN_B 0x05U 1023 typedef struct 1024 { 1025 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1026 uint8_t fsm_en : 1; 1027 uint8_t not_used_01 : 2; 1028 uint8_t fifo_compr_en : 1; 1029 uint8_t pedo_adv_en : 1; 1030 uint8_t not_used_02 : 3; 1031 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1032 uint8_t not_used_02 : 3; 1033 uint8_t pedo_adv_en : 1; 1034 uint8_t fifo_compr_en : 1; 1035 uint8_t not_used_01 : 2; 1036 uint8_t fsm_en : 1; 1037 #endif /* DRV_BYTE_ORDER */ 1038 } lsm6dso32_emb_func_en_b_t; 1039 1040 #define LSM6DSO32_PAGE_ADDRESS 0x08U 1041 typedef struct 1042 { 1043 uint8_t page_addr : 8; 1044 } lsm6dso32_page_address_t; 1045 1046 #define LSM6DSO32_PAGE_VALUE 0x09U 1047 typedef struct 1048 { 1049 uint8_t page_value : 8; 1050 } lsm6dso32_page_value_t; 1051 1052 #define LSM6DSO32_EMB_FUNC_INT1 0x0AU 1053 typedef struct 1054 { 1055 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1056 uint8_t not_used_01 : 3; 1057 uint8_t int1_step_detector : 1; 1058 uint8_t int1_tilt : 1; 1059 uint8_t int1_sig_mot : 1; 1060 uint8_t not_used_02 : 1; 1061 uint8_t int1_fsm_lc : 1; 1062 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1063 uint8_t int1_fsm_lc : 1; 1064 uint8_t not_used_02 : 1; 1065 uint8_t int1_sig_mot : 1; 1066 uint8_t int1_tilt : 1; 1067 uint8_t int1_step_detector : 1; 1068 uint8_t not_used_01 : 3; 1069 #endif /* DRV_BYTE_ORDER */ 1070 } lsm6dso32_emb_func_int1_t; 1071 1072 #define LSM6DSO32_FSM_INT1_A 0x0BU 1073 typedef struct 1074 { 1075 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1076 uint8_t int1_fsm1 : 1; 1077 uint8_t int1_fsm2 : 1; 1078 uint8_t int1_fsm3 : 1; 1079 uint8_t int1_fsm4 : 1; 1080 uint8_t int1_fsm5 : 1; 1081 uint8_t int1_fsm6 : 1; 1082 uint8_t int1_fsm7 : 1; 1083 uint8_t int1_fsm8 : 1; 1084 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1085 uint8_t int1_fsm8 : 1; 1086 uint8_t int1_fsm7 : 1; 1087 uint8_t int1_fsm6 : 1; 1088 uint8_t int1_fsm5 : 1; 1089 uint8_t int1_fsm4 : 1; 1090 uint8_t int1_fsm3 : 1; 1091 uint8_t int1_fsm2 : 1; 1092 uint8_t int1_fsm1 : 1; 1093 #endif /* DRV_BYTE_ORDER */ 1094 } lsm6dso32_fsm_int1_a_t; 1095 1096 #define LSM6DSO32_FSM_INT1_B 0x0CU 1097 typedef struct 1098 { 1099 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1100 uint8_t int1_fsm9 : 1; 1101 uint8_t int1_fsm10 : 1; 1102 uint8_t int1_fsm11 : 1; 1103 uint8_t int1_fsm12 : 1; 1104 uint8_t int1_fsm13 : 1; 1105 uint8_t int1_fsm14 : 1; 1106 uint8_t int1_fsm15 : 1; 1107 uint8_t int1_fsm16 : 1; 1108 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1109 uint8_t int1_fsm16 : 1; 1110 uint8_t int1_fsm15 : 1; 1111 uint8_t int1_fsm14 : 1; 1112 uint8_t int1_fsm13 : 1; 1113 uint8_t int1_fsm12 : 1; 1114 uint8_t int1_fsm11 : 1; 1115 uint8_t int1_fsm10 : 1; 1116 uint8_t int1_fsm9 : 1; 1117 #endif /* DRV_BYTE_ORDER */ 1118 } lsm6dso32_fsm_int1_b_t; 1119 1120 #define LSM6DSO32_EMB_FUNC_INT2 0x0EU 1121 typedef struct 1122 { 1123 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1124 uint8_t not_used_01 : 3; 1125 uint8_t int2_step_detector : 1; 1126 uint8_t int2_tilt : 1; 1127 uint8_t int2_sig_mot : 1; 1128 uint8_t not_used_02 : 1; 1129 uint8_t int2_fsm_lc : 1; 1130 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1131 uint8_t int2_fsm_lc : 1; 1132 uint8_t not_used_02 : 1; 1133 uint8_t int2_sig_mot : 1; 1134 uint8_t int2_tilt : 1; 1135 uint8_t int2_step_detector : 1; 1136 uint8_t not_used_01 : 3; 1137 #endif /* DRV_BYTE_ORDER */ 1138 } lsm6dso32_emb_func_int2_t; 1139 1140 #define LSM6DSO32_FSM_INT2_A 0x0FU 1141 typedef struct 1142 { 1143 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1144 uint8_t int2_fsm1 : 1; 1145 uint8_t int2_fsm2 : 1; 1146 uint8_t int2_fsm3 : 1; 1147 uint8_t int2_fsm4 : 1; 1148 uint8_t int2_fsm5 : 1; 1149 uint8_t int2_fsm6 : 1; 1150 uint8_t int2_fsm7 : 1; 1151 uint8_t int2_fsm8 : 1; 1152 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1153 uint8_t int2_fsm8 : 1; 1154 uint8_t int2_fsm7 : 1; 1155 uint8_t int2_fsm6 : 1; 1156 uint8_t int2_fsm5 : 1; 1157 uint8_t int2_fsm4 : 1; 1158 uint8_t int2_fsm3 : 1; 1159 uint8_t int2_fsm2 : 1; 1160 uint8_t int2_fsm1 : 1; 1161 #endif /* DRV_BYTE_ORDER */ 1162 } lsm6dso32_fsm_int2_a_t; 1163 1164 #define LSM6DSO32_FSM_INT2_B 0x10U 1165 typedef struct 1166 { 1167 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1168 uint8_t int2_fsm9 : 1; 1169 uint8_t int2_fsm10 : 1; 1170 uint8_t int2_fsm11 : 1; 1171 uint8_t int2_fsm12 : 1; 1172 uint8_t int2_fsm13 : 1; 1173 uint8_t int2_fsm14 : 1; 1174 uint8_t int2_fsm15 : 1; 1175 uint8_t int2_fsm16 : 1; 1176 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1177 uint8_t int2_fsm16 : 1; 1178 uint8_t int2_fsm15 : 1; 1179 uint8_t int2_fsm14 : 1; 1180 uint8_t int2_fsm13 : 1; 1181 uint8_t int2_fsm12 : 1; 1182 uint8_t int2_fsm11 : 1; 1183 uint8_t int2_fsm10 : 1; 1184 uint8_t int2_fsm9 : 1; 1185 #endif /* DRV_BYTE_ORDER */ 1186 } lsm6dso32_fsm_int2_b_t; 1187 1188 #define LSM6DSO32_EMB_FUNC_STATUS 0x12U 1189 typedef struct 1190 { 1191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1192 uint8_t not_used_01 : 3; 1193 uint8_t is_step_det : 1; 1194 uint8_t is_tilt : 1; 1195 uint8_t is_sigmot : 1; 1196 uint8_t not_used_02 : 1; 1197 uint8_t is_fsm_lc : 1; 1198 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1199 uint8_t is_fsm_lc : 1; 1200 uint8_t not_used_02 : 1; 1201 uint8_t is_sigmot : 1; 1202 uint8_t is_tilt : 1; 1203 uint8_t is_step_det : 1; 1204 uint8_t not_used_01 : 3; 1205 #endif /* DRV_BYTE_ORDER */ 1206 } lsm6dso32_emb_func_status_t; 1207 1208 #define LSM6DSO32_FSM_STATUS_A 0x13U 1209 typedef struct 1210 { 1211 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1212 uint8_t is_fsm1 : 1; 1213 uint8_t is_fsm2 : 1; 1214 uint8_t is_fsm3 : 1; 1215 uint8_t is_fsm4 : 1; 1216 uint8_t is_fsm5 : 1; 1217 uint8_t is_fsm6 : 1; 1218 uint8_t is_fsm7 : 1; 1219 uint8_t is_fsm8 : 1; 1220 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1221 uint8_t is_fsm8 : 1; 1222 uint8_t is_fsm7 : 1; 1223 uint8_t is_fsm6 : 1; 1224 uint8_t is_fsm5 : 1; 1225 uint8_t is_fsm4 : 1; 1226 uint8_t is_fsm3 : 1; 1227 uint8_t is_fsm2 : 1; 1228 uint8_t is_fsm1 : 1; 1229 #endif /* DRV_BYTE_ORDER */ 1230 } lsm6dso32_fsm_status_a_t; 1231 1232 #define LSM6DSO32_FSM_STATUS_B 0x14U 1233 typedef struct 1234 { 1235 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1236 uint8_t is_fsm9 : 1; 1237 uint8_t is_fsm10 : 1; 1238 uint8_t is_fsm11 : 1; 1239 uint8_t is_fsm12 : 1; 1240 uint8_t is_fsm13 : 1; 1241 uint8_t is_fsm14 : 1; 1242 uint8_t is_fsm15 : 1; 1243 uint8_t is_fsm16 : 1; 1244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1245 uint8_t is_fsm16 : 1; 1246 uint8_t is_fsm15 : 1; 1247 uint8_t is_fsm14 : 1; 1248 uint8_t is_fsm13 : 1; 1249 uint8_t is_fsm12 : 1; 1250 uint8_t is_fsm11 : 1; 1251 uint8_t is_fsm10 : 1; 1252 uint8_t is_fsm9 : 1; 1253 #endif /* DRV_BYTE_ORDER */ 1254 } lsm6dso32_fsm_status_b_t; 1255 1256 #define LSM6DSO32_PAGE_RW 0x17U 1257 typedef struct 1258 { 1259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1260 uint8_t not_used_01 : 5; 1261 uint8_t page_rw : 2; /* page_write + page_read */ 1262 uint8_t emb_func_lir : 1; 1263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1264 uint8_t emb_func_lir : 1; 1265 uint8_t page_rw : 2; /* page_write + page_read */ 1266 uint8_t not_used_01 : 5; 1267 #endif /* DRV_BYTE_ORDER */ 1268 } lsm6dso32_page_rw_t; 1269 1270 #define LSM6DSO32_EMB_FUNC_FIFO_CFG 0x44U 1271 typedef struct 1272 { 1273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1274 uint8_t not_used_00 : 6; 1275 uint8_t pedo_fifo_en : 1; 1276 uint8_t not_used_01 : 1; 1277 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1278 uint8_t not_used_01 : 1; 1279 uint8_t pedo_fifo_en : 1; 1280 uint8_t not_used_00 : 6; 1281 #endif /* DRV_BYTE_ORDER */ 1282 } lsm6dso32_emb_func_fifo_cfg_t; 1283 1284 #define LSM6DSO32_FSM_ENABLE_A 0x46U 1285 typedef struct 1286 { 1287 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1288 uint8_t fsm1_en : 1; 1289 uint8_t fsm2_en : 1; 1290 uint8_t fsm3_en : 1; 1291 uint8_t fsm4_en : 1; 1292 uint8_t fsm5_en : 1; 1293 uint8_t fsm6_en : 1; 1294 uint8_t fsm7_en : 1; 1295 uint8_t fsm8_en : 1; 1296 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1297 uint8_t fsm8_en : 1; 1298 uint8_t fsm7_en : 1; 1299 uint8_t fsm6_en : 1; 1300 uint8_t fsm5_en : 1; 1301 uint8_t fsm4_en : 1; 1302 uint8_t fsm3_en : 1; 1303 uint8_t fsm2_en : 1; 1304 uint8_t fsm1_en : 1; 1305 #endif /* DRV_BYTE_ORDER */ 1306 } lsm6dso32_fsm_enable_a_t; 1307 1308 #define LSM6DSO32_FSM_ENABLE_B 0x47U 1309 typedef struct 1310 { 1311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1312 uint8_t fsm9_en : 1; 1313 uint8_t fsm10_en : 1; 1314 uint8_t fsm11_en : 1; 1315 uint8_t fsm12_en : 1; 1316 uint8_t fsm13_en : 1; 1317 uint8_t fsm14_en : 1; 1318 uint8_t fsm15_en : 1; 1319 uint8_t fsm16_en : 1; 1320 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1321 uint8_t fsm16_en : 1; 1322 uint8_t fsm15_en : 1; 1323 uint8_t fsm14_en : 1; 1324 uint8_t fsm13_en : 1; 1325 uint8_t fsm12_en : 1; 1326 uint8_t fsm11_en : 1; 1327 uint8_t fsm10_en : 1; 1328 uint8_t fsm9_en : 1; 1329 #endif /* DRV_BYTE_ORDER */ 1330 } lsm6dso32_fsm_enable_b_t; 1331 1332 #define LSM6DSO32_FSM_LONG_COUNTER_L 0x48U 1333 #define LSM6DSO32_FSM_LONG_COUNTER_H 0x49U 1334 #define LSM6DSO32_FSM_LONG_COUNTER_CLEAR 0x4AU 1335 typedef struct 1336 { 1337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1338 uint8_t fsm_lc_clr : 1339 2; /* fsm_lc_cleared + fsm_lc_clear */ 1340 uint8_t not_used_01 : 6; 1341 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1342 uint8_t not_used_01 : 6; 1343 uint8_t fsm_lc_clr : 1344 2; /* fsm_lc_cleared + fsm_lc_clear */ 1345 #endif /* DRV_BYTE_ORDER */ 1346 } lsm6dso32_fsm_long_counter_clear_t; 1347 1348 #define LSM6DSO32_FSM_OUTS1 0x4CU 1349 typedef struct 1350 { 1351 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1352 uint8_t n_v : 1; 1353 uint8_t p_v : 1; 1354 uint8_t n_z : 1; 1355 uint8_t p_z : 1; 1356 uint8_t n_y : 1; 1357 uint8_t p_y : 1; 1358 uint8_t n_x : 1; 1359 uint8_t p_x : 1; 1360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1361 uint8_t p_x : 1; 1362 uint8_t n_x : 1; 1363 uint8_t p_y : 1; 1364 uint8_t n_y : 1; 1365 uint8_t p_z : 1; 1366 uint8_t n_z : 1; 1367 uint8_t p_v : 1; 1368 uint8_t n_v : 1; 1369 #endif /* DRV_BYTE_ORDER */ 1370 } lsm6dso32_fsm_outs1_t; 1371 1372 #define LSM6DSO32_FSM_OUTS2 0x4DU 1373 typedef struct 1374 { 1375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1376 uint8_t n_v : 1; 1377 uint8_t p_v : 1; 1378 uint8_t n_z : 1; 1379 uint8_t p_z : 1; 1380 uint8_t n_y : 1; 1381 uint8_t p_y : 1; 1382 uint8_t n_x : 1; 1383 uint8_t p_x : 1; 1384 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1385 uint8_t p_x : 1; 1386 uint8_t n_x : 1; 1387 uint8_t p_y : 1; 1388 uint8_t n_y : 1; 1389 uint8_t p_z : 1; 1390 uint8_t n_z : 1; 1391 uint8_t p_v : 1; 1392 uint8_t n_v : 1; 1393 #endif /* DRV_BYTE_ORDER */ 1394 } lsm6dso32_fsm_outs2_t; 1395 1396 #define LSM6DSO32_FSM_OUTS3 0x4EU 1397 typedef struct 1398 { 1399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1400 uint8_t n_v : 1; 1401 uint8_t p_v : 1; 1402 uint8_t n_z : 1; 1403 uint8_t p_z : 1; 1404 uint8_t n_y : 1; 1405 uint8_t p_y : 1; 1406 uint8_t n_x : 1; 1407 uint8_t p_x : 1; 1408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1409 uint8_t p_x : 1; 1410 uint8_t n_x : 1; 1411 uint8_t p_y : 1; 1412 uint8_t n_y : 1; 1413 uint8_t p_z : 1; 1414 uint8_t n_z : 1; 1415 uint8_t p_v : 1; 1416 uint8_t n_v : 1; 1417 #endif /* DRV_BYTE_ORDER */ 1418 } lsm6dso32_fsm_outs3_t; 1419 1420 #define LSM6DSO32_FSM_OUTS4 0x4FU 1421 typedef struct 1422 { 1423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1424 uint8_t n_v : 1; 1425 uint8_t p_v : 1; 1426 uint8_t n_z : 1; 1427 uint8_t p_z : 1; 1428 uint8_t n_y : 1; 1429 uint8_t p_y : 1; 1430 uint8_t n_x : 1; 1431 uint8_t p_x : 1; 1432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1433 uint8_t p_x : 1; 1434 uint8_t n_x : 1; 1435 uint8_t p_y : 1; 1436 uint8_t n_y : 1; 1437 uint8_t p_z : 1; 1438 uint8_t n_z : 1; 1439 uint8_t p_v : 1; 1440 uint8_t n_v : 1; 1441 #endif /* DRV_BYTE_ORDER */ 1442 } lsm6dso32_fsm_outs4_t; 1443 1444 #define LSM6DSO32_FSM_OUTS5 0x50U 1445 typedef struct 1446 { 1447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1448 uint8_t n_v : 1; 1449 uint8_t p_v : 1; 1450 uint8_t n_z : 1; 1451 uint8_t p_z : 1; 1452 uint8_t n_y : 1; 1453 uint8_t p_y : 1; 1454 uint8_t n_x : 1; 1455 uint8_t p_x : 1; 1456 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1457 uint8_t p_x : 1; 1458 uint8_t n_x : 1; 1459 uint8_t p_y : 1; 1460 uint8_t n_y : 1; 1461 uint8_t p_z : 1; 1462 uint8_t n_z : 1; 1463 uint8_t p_v : 1; 1464 uint8_t n_v : 1; 1465 #endif /* DRV_BYTE_ORDER */ 1466 } lsm6dso32_fsm_outs5_t; 1467 1468 #define LSM6DSO32_FSM_OUTS6 0x51U 1469 typedef struct 1470 { 1471 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1472 uint8_t n_v : 1; 1473 uint8_t p_v : 1; 1474 uint8_t n_z : 1; 1475 uint8_t p_z : 1; 1476 uint8_t n_y : 1; 1477 uint8_t p_y : 1; 1478 uint8_t n_x : 1; 1479 uint8_t p_x : 1; 1480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1481 uint8_t p_x : 1; 1482 uint8_t n_x : 1; 1483 uint8_t p_y : 1; 1484 uint8_t n_y : 1; 1485 uint8_t p_z : 1; 1486 uint8_t n_z : 1; 1487 uint8_t p_v : 1; 1488 uint8_t n_v : 1; 1489 #endif /* DRV_BYTE_ORDER */ 1490 } lsm6dso32_fsm_outs6_t; 1491 1492 #define LSM6DSO32_FSM_OUTS7 0x52U 1493 typedef struct 1494 { 1495 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1496 uint8_t n_v : 1; 1497 uint8_t p_v : 1; 1498 uint8_t n_z : 1; 1499 uint8_t p_z : 1; 1500 uint8_t n_y : 1; 1501 uint8_t p_y : 1; 1502 uint8_t n_x : 1; 1503 uint8_t p_x : 1; 1504 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1505 uint8_t p_x : 1; 1506 uint8_t n_x : 1; 1507 uint8_t p_y : 1; 1508 uint8_t n_y : 1; 1509 uint8_t p_z : 1; 1510 uint8_t n_z : 1; 1511 uint8_t p_v : 1; 1512 uint8_t n_v : 1; 1513 #endif /* DRV_BYTE_ORDER */ 1514 } lsm6dso32_fsm_outs7_t; 1515 1516 #define LSM6DSO32_FSM_OUTS8 0x53U 1517 typedef struct 1518 { 1519 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1520 uint8_t n_v : 1; 1521 uint8_t p_v : 1; 1522 uint8_t n_z : 1; 1523 uint8_t p_z : 1; 1524 uint8_t n_y : 1; 1525 uint8_t p_y : 1; 1526 uint8_t n_x : 1; 1527 uint8_t p_x : 1; 1528 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1529 uint8_t p_x : 1; 1530 uint8_t n_x : 1; 1531 uint8_t p_y : 1; 1532 uint8_t n_y : 1; 1533 uint8_t p_z : 1; 1534 uint8_t n_z : 1; 1535 uint8_t p_v : 1; 1536 uint8_t n_v : 1; 1537 #endif /* DRV_BYTE_ORDER */ 1538 } lsm6dso32_fsm_outs8_t; 1539 1540 #define LSM6DSO32_FSM_OUTS9 0x54U 1541 typedef struct 1542 { 1543 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1544 uint8_t n_v : 1; 1545 uint8_t p_v : 1; 1546 uint8_t n_z : 1; 1547 uint8_t p_z : 1; 1548 uint8_t n_y : 1; 1549 uint8_t p_y : 1; 1550 uint8_t n_x : 1; 1551 uint8_t p_x : 1; 1552 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1553 uint8_t p_x : 1; 1554 uint8_t n_x : 1; 1555 uint8_t p_y : 1; 1556 uint8_t n_y : 1; 1557 uint8_t p_z : 1; 1558 uint8_t n_z : 1; 1559 uint8_t p_v : 1; 1560 uint8_t n_v : 1; 1561 #endif /* DRV_BYTE_ORDER */ 1562 } lsm6dso32_fsm_outs9_t; 1563 1564 #define LSM6DSO32_FSM_OUTS10 0x55U 1565 typedef struct 1566 { 1567 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1568 uint8_t n_v : 1; 1569 uint8_t p_v : 1; 1570 uint8_t n_z : 1; 1571 uint8_t p_z : 1; 1572 uint8_t n_y : 1; 1573 uint8_t p_y : 1; 1574 uint8_t n_x : 1; 1575 uint8_t p_x : 1; 1576 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1577 uint8_t p_x : 1; 1578 uint8_t n_x : 1; 1579 uint8_t p_y : 1; 1580 uint8_t n_y : 1; 1581 uint8_t p_z : 1; 1582 uint8_t n_z : 1; 1583 uint8_t p_v : 1; 1584 uint8_t n_v : 1; 1585 #endif /* DRV_BYTE_ORDER */ 1586 } lsm6dso32_fsm_outs10_t; 1587 1588 #define LSM6DSO32_FSM_OUTS11 0x56U 1589 typedef struct 1590 { 1591 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1592 uint8_t n_v : 1; 1593 uint8_t p_v : 1; 1594 uint8_t n_z : 1; 1595 uint8_t p_z : 1; 1596 uint8_t n_y : 1; 1597 uint8_t p_y : 1; 1598 uint8_t n_x : 1; 1599 uint8_t p_x : 1; 1600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1601 uint8_t p_x : 1; 1602 uint8_t n_x : 1; 1603 uint8_t p_y : 1; 1604 uint8_t n_y : 1; 1605 uint8_t p_z : 1; 1606 uint8_t n_z : 1; 1607 uint8_t p_v : 1; 1608 uint8_t n_v : 1; 1609 #endif /* DRV_BYTE_ORDER */ 1610 } lsm6dso32_fsm_outs11_t; 1611 1612 #define LSM6DSO32_FSM_OUTS12 0x57U 1613 typedef struct 1614 { 1615 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1616 uint8_t n_v : 1; 1617 uint8_t p_v : 1; 1618 uint8_t n_z : 1; 1619 uint8_t p_z : 1; 1620 uint8_t n_y : 1; 1621 uint8_t p_y : 1; 1622 uint8_t n_x : 1; 1623 uint8_t p_x : 1; 1624 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1625 uint8_t p_x : 1; 1626 uint8_t n_x : 1; 1627 uint8_t p_y : 1; 1628 uint8_t n_y : 1; 1629 uint8_t p_z : 1; 1630 uint8_t n_z : 1; 1631 uint8_t p_v : 1; 1632 uint8_t n_v : 1; 1633 #endif /* DRV_BYTE_ORDER */ 1634 } lsm6dso32_fsm_outs12_t; 1635 1636 #define LSM6DSO32_FSM_OUTS13 0x58U 1637 typedef struct 1638 { 1639 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1640 uint8_t n_v : 1; 1641 uint8_t p_v : 1; 1642 uint8_t n_z : 1; 1643 uint8_t p_z : 1; 1644 uint8_t n_y : 1; 1645 uint8_t p_y : 1; 1646 uint8_t n_x : 1; 1647 uint8_t p_x : 1; 1648 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1649 uint8_t p_x : 1; 1650 uint8_t n_x : 1; 1651 uint8_t p_y : 1; 1652 uint8_t n_y : 1; 1653 uint8_t p_z : 1; 1654 uint8_t n_z : 1; 1655 uint8_t p_v : 1; 1656 uint8_t n_v : 1; 1657 #endif /* DRV_BYTE_ORDER */ 1658 } lsm6dso32_fsm_outs13_t; 1659 1660 #define LSM6DSO32_FSM_OUTS14 0x59U 1661 typedef struct 1662 { 1663 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1664 uint8_t n_v : 1; 1665 uint8_t p_v : 1; 1666 uint8_t n_z : 1; 1667 uint8_t p_z : 1; 1668 uint8_t n_y : 1; 1669 uint8_t p_y : 1; 1670 uint8_t n_x : 1; 1671 uint8_t p_x : 1; 1672 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1673 uint8_t p_x : 1; 1674 uint8_t n_x : 1; 1675 uint8_t p_y : 1; 1676 uint8_t n_y : 1; 1677 uint8_t p_z : 1; 1678 uint8_t n_z : 1; 1679 uint8_t p_v : 1; 1680 uint8_t n_v : 1; 1681 #endif /* DRV_BYTE_ORDER */ 1682 } lsm6dso32_fsm_outs14_t; 1683 1684 #define LSM6DSO32_FSM_OUTS15 0x5AU 1685 typedef struct 1686 { 1687 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1688 uint8_t n_v : 1; 1689 uint8_t p_v : 1; 1690 uint8_t n_z : 1; 1691 uint8_t p_z : 1; 1692 uint8_t n_y : 1; 1693 uint8_t p_y : 1; 1694 uint8_t n_x : 1; 1695 uint8_t p_x : 1; 1696 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1697 uint8_t p_x : 1; 1698 uint8_t n_x : 1; 1699 uint8_t p_y : 1; 1700 uint8_t n_y : 1; 1701 uint8_t p_z : 1; 1702 uint8_t n_z : 1; 1703 uint8_t p_v : 1; 1704 uint8_t n_v : 1; 1705 #endif /* DRV_BYTE_ORDER */ 1706 } lsm6dso32_fsm_outs15_t; 1707 1708 #define LSM6DSO32_FSM_OUTS16 0x5BU 1709 typedef struct 1710 { 1711 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1712 uint8_t n_v : 1; 1713 uint8_t p_v : 1; 1714 uint8_t n_z : 1; 1715 uint8_t p_z : 1; 1716 uint8_t n_y : 1; 1717 uint8_t p_y : 1; 1718 uint8_t n_x : 1; 1719 uint8_t p_x : 1; 1720 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1721 uint8_t p_x : 1; 1722 uint8_t n_x : 1; 1723 uint8_t p_y : 1; 1724 uint8_t n_y : 1; 1725 uint8_t p_z : 1; 1726 uint8_t n_z : 1; 1727 uint8_t p_v : 1; 1728 uint8_t n_v : 1; 1729 #endif /* DRV_BYTE_ORDER */ 1730 } lsm6dso32_fsm_outs16_t; 1731 1732 #define LSM6DSO32_EMB_FUNC_ODR_CFG_B 0x5FU 1733 typedef struct 1734 { 1735 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1736 uint8_t not_used_01 : 3; 1737 uint8_t fsm_odr : 2; 1738 uint8_t not_used_02 : 3; 1739 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1740 uint8_t not_used_02 : 3; 1741 uint8_t fsm_odr : 2; 1742 uint8_t not_used_01 : 3; 1743 #endif /* DRV_BYTE_ORDER */ 1744 } lsm6dso32_emb_func_odr_cfg_b_t; 1745 1746 #define LSM6DSO32_STEP_COUNTER_L 0x62U 1747 #define LSM6DSO32_STEP_COUNTER_H 0x63U 1748 #define LSM6DSO32_EMB_FUNC_SRC 0x64U 1749 typedef struct 1750 { 1751 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1752 uint8_t not_used_01 : 2; 1753 uint8_t stepcounter_bit_set : 1; 1754 uint8_t step_overflow : 1; 1755 uint8_t step_count_delta_ia : 1; 1756 uint8_t step_detected : 1; 1757 uint8_t not_used_02 : 1; 1758 uint8_t pedo_rst_step : 1; 1759 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1760 uint8_t pedo_rst_step : 1; 1761 uint8_t not_used_02 : 1; 1762 uint8_t step_detected : 1; 1763 uint8_t step_count_delta_ia : 1; 1764 uint8_t step_overflow : 1; 1765 uint8_t stepcounter_bit_set : 1; 1766 uint8_t not_used_01 : 2; 1767 #endif /* DRV_BYTE_ORDER */ 1768 } lsm6dso32_emb_func_src_t; 1769 1770 #define LSM6DSO32_EMB_FUNC_INIT_A 0x66U 1771 typedef struct 1772 { 1773 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1774 uint8_t not_used_01 : 3; 1775 uint8_t step_det_init : 1; 1776 uint8_t tilt_init : 1; 1777 uint8_t sig_mot_init : 1; 1778 uint8_t not_used_02 : 2; 1779 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1780 uint8_t not_used_02 : 2; 1781 uint8_t sig_mot_init : 1; 1782 uint8_t tilt_init : 1; 1783 uint8_t step_det_init : 1; 1784 uint8_t not_used_01 : 3; 1785 #endif /* DRV_BYTE_ORDER */ 1786 } lsm6dso32_emb_func_init_a_t; 1787 1788 #define LSM6DSO32_EMB_FUNC_INIT_B 0x67U 1789 typedef struct 1790 { 1791 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1792 uint8_t fsm_init : 1; 1793 uint8_t not_used_01 : 2; 1794 uint8_t fifo_compr_init : 1; 1795 uint8_t not_used_02 : 4; 1796 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1797 uint8_t not_used_02 : 4; 1798 uint8_t fifo_compr_init : 1; 1799 uint8_t not_used_01 : 2; 1800 uint8_t fsm_init : 1; 1801 #endif /* DRV_BYTE_ORDER */ 1802 } lsm6dso32_emb_func_init_b_t; 1803 1804 #define LSM6DSO32_MAG_SENSITIVITY_L 0xBAU 1805 #define LSM6DSO32_MAG_SENSITIVITY_H 0xBBU 1806 #define LSM6DSO32_MAG_OFFX_L 0xC0U 1807 #define LSM6DSO32_MAG_OFFX_H 0xC1U 1808 #define LSM6DSO32_MAG_OFFY_L 0xC2U 1809 #define LSM6DSO32_MAG_OFFY_H 0xC3U 1810 #define LSM6DSO32_MAG_OFFZ_L 0xC4U 1811 #define LSM6DSO32_MAG_OFFZ_H 0xC5U 1812 #define LSM6DSO32_MAG_SI_XX_L 0xC6U 1813 #define LSM6DSO32_MAG_SI_XX_H 0xC7U 1814 #define LSM6DSO32_MAG_SI_XY_L 0xC8U 1815 #define LSM6DSO32_MAG_SI_XY_H 0xC9U 1816 #define LSM6DSO32_MAG_SI_XZ_L 0xCAU 1817 #define LSM6DSO32_MAG_SI_XZ_H 0xCBU 1818 #define LSM6DSO32_MAG_SI_YY_L 0xCCU 1819 #define LSM6DSO32_MAG_SI_YY_H 0xCDU 1820 #define LSM6DSO32_MAG_SI_YZ_L 0xCEU 1821 #define LSM6DSO32_MAG_SI_YZ_H 0xCFU 1822 #define LSM6DSO32_MAG_SI_ZZ_L 0xD0U 1823 #define LSM6DSO32_MAG_SI_ZZ_H 0xD1U 1824 #define LSM6DSO32_MAG_CFG_A 0xD4U 1825 typedef struct 1826 { 1827 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1828 uint8_t mag_z_axis : 3; 1829 uint8_t not_used_01 : 1; 1830 uint8_t mag_y_axis : 3; 1831 uint8_t not_used_02 : 1; 1832 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1833 uint8_t not_used_02 : 1; 1834 uint8_t mag_y_axis : 3; 1835 uint8_t not_used_01 : 1; 1836 uint8_t mag_z_axis : 3; 1837 #endif /* DRV_BYTE_ORDER */ 1838 } lsm6dso32_mag_cfg_a_t; 1839 1840 #define LSM6DSO32_MAG_CFG_B 0xD5U 1841 typedef struct 1842 { 1843 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1844 uint8_t mag_x_axis : 3; 1845 uint8_t not_used_01 : 5; 1846 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1847 uint8_t not_used_01 : 5; 1848 uint8_t mag_x_axis : 3; 1849 #endif /* DRV_BYTE_ORDER */ 1850 } lsm6dso32_mag_cfg_b_t; 1851 1852 #define LSM6DSO32_FSM_LC_TIMEOUT_L 0x17AU 1853 #define LSM6DSO32_FSM_LC_TIMEOUT_H 0x17BU 1854 #define LSM6DSO32_FSM_PROGRAMS 0x17CU 1855 #define LSM6DSO32_FSM_START_ADD_L 0x17EU 1856 #define LSM6DSO32_FSM_START_ADD_H 0x17FU 1857 #define LSM6DSO32_PEDO_CMD_REG 0x183U 1858 typedef struct 1859 { 1860 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1861 uint8_t ad_det_en : 1; 1862 uint8_t not_used_01 : 1; 1863 uint8_t fp_rejection_en : 1; 1864 uint8_t carry_count_en : 1; 1865 uint8_t not_used_02 : 4; 1866 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1867 uint8_t not_used_02 : 4; 1868 uint8_t carry_count_en : 1; 1869 uint8_t fp_rejection_en : 1; 1870 uint8_t not_used_01 : 1; 1871 uint8_t ad_det_en : 1; 1872 #endif /* DRV_BYTE_ORDER */ 1873 } lsm6dso32_pedo_cmd_reg_t; 1874 1875 #define LSM6DSO32_PEDO_DEB_STEPS_CONF 0x184U 1876 #define LSM6DSO32_PEDO_SC_DELTAT_L 0x1D0U 1877 #define LSM6DSO32_PEDO_SC_DELTAT_H 0x1D1U 1878 #define LSM6DSO32_SENSOR_HUB_1 0x02U 1879 typedef struct 1880 { 1881 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1882 uint8_t bit0 : 1; 1883 uint8_t bit1 : 1; 1884 uint8_t bit2 : 1; 1885 uint8_t bit3 : 1; 1886 uint8_t bit4 : 1; 1887 uint8_t bit5 : 1; 1888 uint8_t bit6 : 1; 1889 uint8_t bit7 : 1; 1890 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1891 uint8_t bit7 : 1; 1892 uint8_t bit6 : 1; 1893 uint8_t bit5 : 1; 1894 uint8_t bit4 : 1; 1895 uint8_t bit3 : 1; 1896 uint8_t bit2 : 1; 1897 uint8_t bit1 : 1; 1898 uint8_t bit0 : 1; 1899 #endif /* DRV_BYTE_ORDER */ 1900 } lsm6dso32_sensor_hub_1_t; 1901 1902 #define LSM6DSO32_SENSOR_HUB_2 0x03U 1903 typedef struct 1904 { 1905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1906 uint8_t bit0 : 1; 1907 uint8_t bit1 : 1; 1908 uint8_t bit2 : 1; 1909 uint8_t bit3 : 1; 1910 uint8_t bit4 : 1; 1911 uint8_t bit5 : 1; 1912 uint8_t bit6 : 1; 1913 uint8_t bit7 : 1; 1914 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1915 uint8_t bit7 : 1; 1916 uint8_t bit6 : 1; 1917 uint8_t bit5 : 1; 1918 uint8_t bit4 : 1; 1919 uint8_t bit3 : 1; 1920 uint8_t bit2 : 1; 1921 uint8_t bit1 : 1; 1922 uint8_t bit0 : 1; 1923 #endif /* DRV_BYTE_ORDER */ 1924 } lsm6dso32_sensor_hub_2_t; 1925 1926 #define LSM6DSO32_SENSOR_HUB_3 0x04U 1927 typedef struct 1928 { 1929 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1930 uint8_t bit0 : 1; 1931 uint8_t bit1 : 1; 1932 uint8_t bit2 : 1; 1933 uint8_t bit3 : 1; 1934 uint8_t bit4 : 1; 1935 uint8_t bit5 : 1; 1936 uint8_t bit6 : 1; 1937 uint8_t bit7 : 1; 1938 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1939 uint8_t bit7 : 1; 1940 uint8_t bit6 : 1; 1941 uint8_t bit5 : 1; 1942 uint8_t bit4 : 1; 1943 uint8_t bit3 : 1; 1944 uint8_t bit2 : 1; 1945 uint8_t bit1 : 1; 1946 uint8_t bit0 : 1; 1947 #endif /* DRV_BYTE_ORDER */ 1948 } lsm6dso32_sensor_hub_3_t; 1949 1950 #define LSM6DSO32_SENSOR_HUB_4 0x05U 1951 typedef struct 1952 { 1953 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1954 uint8_t bit0 : 1; 1955 uint8_t bit1 : 1; 1956 uint8_t bit2 : 1; 1957 uint8_t bit3 : 1; 1958 uint8_t bit4 : 1; 1959 uint8_t bit5 : 1; 1960 uint8_t bit6 : 1; 1961 uint8_t bit7 : 1; 1962 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1963 uint8_t bit7 : 1; 1964 uint8_t bit6 : 1; 1965 uint8_t bit5 : 1; 1966 uint8_t bit4 : 1; 1967 uint8_t bit3 : 1; 1968 uint8_t bit2 : 1; 1969 uint8_t bit1 : 1; 1970 uint8_t bit0 : 1; 1971 #endif /* DRV_BYTE_ORDER */ 1972 } lsm6dso32_sensor_hub_4_t; 1973 1974 #define LSM6DSO32_SENSOR_HUB_5 0x06U 1975 typedef struct 1976 { 1977 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1978 uint8_t bit0 : 1; 1979 uint8_t bit1 : 1; 1980 uint8_t bit2 : 1; 1981 uint8_t bit3 : 1; 1982 uint8_t bit4 : 1; 1983 uint8_t bit5 : 1; 1984 uint8_t bit6 : 1; 1985 uint8_t bit7 : 1; 1986 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1987 uint8_t bit7 : 1; 1988 uint8_t bit6 : 1; 1989 uint8_t bit5 : 1; 1990 uint8_t bit4 : 1; 1991 uint8_t bit3 : 1; 1992 uint8_t bit2 : 1; 1993 uint8_t bit1 : 1; 1994 uint8_t bit0 : 1; 1995 #endif /* DRV_BYTE_ORDER */ 1996 } lsm6dso32_sensor_hub_5_t; 1997 1998 #define LSM6DSO32_SENSOR_HUB_6 0x07U 1999 typedef struct 2000 { 2001 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2002 uint8_t bit0 : 1; 2003 uint8_t bit1 : 1; 2004 uint8_t bit2 : 1; 2005 uint8_t bit3 : 1; 2006 uint8_t bit4 : 1; 2007 uint8_t bit5 : 1; 2008 uint8_t bit6 : 1; 2009 uint8_t bit7 : 1; 2010 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2011 uint8_t bit7 : 1; 2012 uint8_t bit6 : 1; 2013 uint8_t bit5 : 1; 2014 uint8_t bit4 : 1; 2015 uint8_t bit3 : 1; 2016 uint8_t bit2 : 1; 2017 uint8_t bit1 : 1; 2018 uint8_t bit0 : 1; 2019 #endif /* DRV_BYTE_ORDER */ 2020 } lsm6dso32_sensor_hub_6_t; 2021 2022 #define LSM6DSO32_SENSOR_HUB_7 0x08U 2023 typedef struct 2024 { 2025 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2026 uint8_t bit0 : 1; 2027 uint8_t bit1 : 1; 2028 uint8_t bit2 : 1; 2029 uint8_t bit3 : 1; 2030 uint8_t bit4 : 1; 2031 uint8_t bit5 : 1; 2032 uint8_t bit6 : 1; 2033 uint8_t bit7 : 1; 2034 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2035 uint8_t bit7 : 1; 2036 uint8_t bit6 : 1; 2037 uint8_t bit5 : 1; 2038 uint8_t bit4 : 1; 2039 uint8_t bit3 : 1; 2040 uint8_t bit2 : 1; 2041 uint8_t bit1 : 1; 2042 uint8_t bit0 : 1; 2043 #endif /* DRV_BYTE_ORDER */ 2044 } lsm6dso32_sensor_hub_7_t; 2045 2046 #define LSM6DSO32_SENSOR_HUB_8 0x09U 2047 typedef struct 2048 { 2049 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2050 uint8_t bit0 : 1; 2051 uint8_t bit1 : 1; 2052 uint8_t bit2 : 1; 2053 uint8_t bit3 : 1; 2054 uint8_t bit4 : 1; 2055 uint8_t bit5 : 1; 2056 uint8_t bit6 : 1; 2057 uint8_t bit7 : 1; 2058 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2059 uint8_t bit7 : 1; 2060 uint8_t bit6 : 1; 2061 uint8_t bit5 : 1; 2062 uint8_t bit4 : 1; 2063 uint8_t bit3 : 1; 2064 uint8_t bit2 : 1; 2065 uint8_t bit1 : 1; 2066 uint8_t bit0 : 1; 2067 #endif /* DRV_BYTE_ORDER */ 2068 } lsm6dso32_sensor_hub_8_t; 2069 2070 #define LSM6DSO32_SENSOR_HUB_9 0x0AU 2071 typedef struct 2072 { 2073 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2074 uint8_t bit0 : 1; 2075 uint8_t bit1 : 1; 2076 uint8_t bit2 : 1; 2077 uint8_t bit3 : 1; 2078 uint8_t bit4 : 1; 2079 uint8_t bit5 : 1; 2080 uint8_t bit6 : 1; 2081 uint8_t bit7 : 1; 2082 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2083 uint8_t bit7 : 1; 2084 uint8_t bit6 : 1; 2085 uint8_t bit5 : 1; 2086 uint8_t bit4 : 1; 2087 uint8_t bit3 : 1; 2088 uint8_t bit2 : 1; 2089 uint8_t bit1 : 1; 2090 uint8_t bit0 : 1; 2091 #endif /* DRV_BYTE_ORDER */ 2092 } lsm6dso32_sensor_hub_9_t; 2093 2094 #define LSM6DSO32_SENSOR_HUB_10 0x0BU 2095 typedef struct 2096 { 2097 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2098 uint8_t bit0 : 1; 2099 uint8_t bit1 : 1; 2100 uint8_t bit2 : 1; 2101 uint8_t bit3 : 1; 2102 uint8_t bit4 : 1; 2103 uint8_t bit5 : 1; 2104 uint8_t bit6 : 1; 2105 uint8_t bit7 : 1; 2106 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2107 uint8_t bit7 : 1; 2108 uint8_t bit6 : 1; 2109 uint8_t bit5 : 1; 2110 uint8_t bit4 : 1; 2111 uint8_t bit3 : 1; 2112 uint8_t bit2 : 1; 2113 uint8_t bit1 : 1; 2114 uint8_t bit0 : 1; 2115 #endif /* DRV_BYTE_ORDER */ 2116 } lsm6dso32_sensor_hub_10_t; 2117 2118 #define LSM6DSO32_SENSOR_HUB_11 0x0CU 2119 typedef struct 2120 { 2121 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2122 uint8_t bit0 : 1; 2123 uint8_t bit1 : 1; 2124 uint8_t bit2 : 1; 2125 uint8_t bit3 : 1; 2126 uint8_t bit4 : 1; 2127 uint8_t bit5 : 1; 2128 uint8_t bit6 : 1; 2129 uint8_t bit7 : 1; 2130 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2131 uint8_t bit7 : 1; 2132 uint8_t bit6 : 1; 2133 uint8_t bit5 : 1; 2134 uint8_t bit4 : 1; 2135 uint8_t bit3 : 1; 2136 uint8_t bit2 : 1; 2137 uint8_t bit1 : 1; 2138 uint8_t bit0 : 1; 2139 #endif /* DRV_BYTE_ORDER */ 2140 } lsm6dso32_sensor_hub_11_t; 2141 2142 #define LSM6DSO32_SENSOR_HUB_12 0x0DU 2143 typedef struct 2144 { 2145 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2146 uint8_t bit0 : 1; 2147 uint8_t bit1 : 1; 2148 uint8_t bit2 : 1; 2149 uint8_t bit3 : 1; 2150 uint8_t bit4 : 1; 2151 uint8_t bit5 : 1; 2152 uint8_t bit6 : 1; 2153 uint8_t bit7 : 1; 2154 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2155 uint8_t bit7 : 1; 2156 uint8_t bit6 : 1; 2157 uint8_t bit5 : 1; 2158 uint8_t bit4 : 1; 2159 uint8_t bit3 : 1; 2160 uint8_t bit2 : 1; 2161 uint8_t bit1 : 1; 2162 uint8_t bit0 : 1; 2163 #endif /* DRV_BYTE_ORDER */ 2164 } lsm6dso32_sensor_hub_12_t; 2165 2166 #define LSM6DSO32_SENSOR_HUB_13 0x0EU 2167 typedef struct 2168 { 2169 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2170 uint8_t bit0 : 1; 2171 uint8_t bit1 : 1; 2172 uint8_t bit2 : 1; 2173 uint8_t bit3 : 1; 2174 uint8_t bit4 : 1; 2175 uint8_t bit5 : 1; 2176 uint8_t bit6 : 1; 2177 uint8_t bit7 : 1; 2178 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2179 uint8_t bit7 : 1; 2180 uint8_t bit6 : 1; 2181 uint8_t bit5 : 1; 2182 uint8_t bit4 : 1; 2183 uint8_t bit3 : 1; 2184 uint8_t bit2 : 1; 2185 uint8_t bit1 : 1; 2186 uint8_t bit0 : 1; 2187 #endif /* DRV_BYTE_ORDER */ 2188 } lsm6dso32_sensor_hub_13_t; 2189 2190 #define LSM6DSO32_SENSOR_HUB_14 0x0FU 2191 typedef struct 2192 { 2193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2194 uint8_t bit0 : 1; 2195 uint8_t bit1 : 1; 2196 uint8_t bit2 : 1; 2197 uint8_t bit3 : 1; 2198 uint8_t bit4 : 1; 2199 uint8_t bit5 : 1; 2200 uint8_t bit6 : 1; 2201 uint8_t bit7 : 1; 2202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2203 uint8_t bit7 : 1; 2204 uint8_t bit6 : 1; 2205 uint8_t bit5 : 1; 2206 uint8_t bit4 : 1; 2207 uint8_t bit3 : 1; 2208 uint8_t bit2 : 1; 2209 uint8_t bit1 : 1; 2210 uint8_t bit0 : 1; 2211 #endif /* DRV_BYTE_ORDER */ 2212 } lsm6dso32_sensor_hub_14_t; 2213 2214 #define LSM6DSO32_SENSOR_HUB_15 0x10U 2215 typedef struct 2216 { 2217 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2218 uint8_t bit0 : 1; 2219 uint8_t bit1 : 1; 2220 uint8_t bit2 : 1; 2221 uint8_t bit3 : 1; 2222 uint8_t bit4 : 1; 2223 uint8_t bit5 : 1; 2224 uint8_t bit6 : 1; 2225 uint8_t bit7 : 1; 2226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2227 uint8_t bit7 : 1; 2228 uint8_t bit6 : 1; 2229 uint8_t bit5 : 1; 2230 uint8_t bit4 : 1; 2231 uint8_t bit3 : 1; 2232 uint8_t bit2 : 1; 2233 uint8_t bit1 : 1; 2234 uint8_t bit0 : 1; 2235 #endif /* DRV_BYTE_ORDER */ 2236 } lsm6dso32_sensor_hub_15_t; 2237 2238 #define LSM6DSO32_SENSOR_HUB_16 0x11U 2239 typedef struct 2240 { 2241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2242 uint8_t bit0 : 1; 2243 uint8_t bit1 : 1; 2244 uint8_t bit2 : 1; 2245 uint8_t bit3 : 1; 2246 uint8_t bit4 : 1; 2247 uint8_t bit5 : 1; 2248 uint8_t bit6 : 1; 2249 uint8_t bit7 : 1; 2250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2251 uint8_t bit7 : 1; 2252 uint8_t bit6 : 1; 2253 uint8_t bit5 : 1; 2254 uint8_t bit4 : 1; 2255 uint8_t bit3 : 1; 2256 uint8_t bit2 : 1; 2257 uint8_t bit1 : 1; 2258 uint8_t bit0 : 1; 2259 #endif /* DRV_BYTE_ORDER */ 2260 } lsm6dso32_sensor_hub_16_t; 2261 2262 #define LSM6DSO32_SENSOR_HUB_17 0x12U 2263 typedef struct 2264 { 2265 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2266 uint8_t bit0 : 1; 2267 uint8_t bit1 : 1; 2268 uint8_t bit2 : 1; 2269 uint8_t bit3 : 1; 2270 uint8_t bit4 : 1; 2271 uint8_t bit5 : 1; 2272 uint8_t bit6 : 1; 2273 uint8_t bit7 : 1; 2274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2275 uint8_t bit7 : 1; 2276 uint8_t bit6 : 1; 2277 uint8_t bit5 : 1; 2278 uint8_t bit4 : 1; 2279 uint8_t bit3 : 1; 2280 uint8_t bit2 : 1; 2281 uint8_t bit1 : 1; 2282 uint8_t bit0 : 1; 2283 #endif /* DRV_BYTE_ORDER */ 2284 } lsm6dso32_sensor_hub_17_t; 2285 2286 #define LSM6DSO32_SENSOR_HUB_18 0x13U 2287 typedef struct 2288 { 2289 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2290 uint8_t bit0 : 1; 2291 uint8_t bit1 : 1; 2292 uint8_t bit2 : 1; 2293 uint8_t bit3 : 1; 2294 uint8_t bit4 : 1; 2295 uint8_t bit5 : 1; 2296 uint8_t bit6 : 1; 2297 uint8_t bit7 : 1; 2298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2299 uint8_t bit7 : 1; 2300 uint8_t bit6 : 1; 2301 uint8_t bit5 : 1; 2302 uint8_t bit4 : 1; 2303 uint8_t bit3 : 1; 2304 uint8_t bit2 : 1; 2305 uint8_t bit1 : 1; 2306 uint8_t bit0 : 1; 2307 #endif /* DRV_BYTE_ORDER */ 2308 } lsm6dso32_sensor_hub_18_t; 2309 2310 #define LSM6DSO32_MASTER_CONFIG 0x14U 2311 typedef struct 2312 { 2313 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2314 uint8_t aux_sens_on : 2; 2315 uint8_t master_on : 1; 2316 uint8_t shub_pu_en : 1; 2317 uint8_t pass_through_mode : 1; 2318 uint8_t start_config : 1; 2319 uint8_t write_once : 1; 2320 uint8_t rst_master_regs : 1; 2321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2322 uint8_t rst_master_regs : 1; 2323 uint8_t write_once : 1; 2324 uint8_t start_config : 1; 2325 uint8_t pass_through_mode : 1; 2326 uint8_t shub_pu_en : 1; 2327 uint8_t master_on : 1; 2328 uint8_t aux_sens_on : 2; 2329 #endif /* DRV_BYTE_ORDER */ 2330 } lsm6dso32_master_config_t; 2331 2332 #define LSM6DSO32_SLV0_ADD 0x15U 2333 typedef struct 2334 { 2335 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2336 uint8_t rw_0 : 1; 2337 uint8_t slave0 : 7; 2338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2339 uint8_t slave0 : 7; 2340 uint8_t rw_0 : 1; 2341 #endif /* DRV_BYTE_ORDER */ 2342 } lsm6dso32_slv0_add_t; 2343 2344 #define LSM6DSO32_SLV0_SUBADD 0x16U 2345 typedef struct 2346 { 2347 uint8_t slave0_reg : 8; 2348 } lsm6dso32_slv0_subadd_t; 2349 2350 #define LSM6DSO32_SLV0_CONFIG 0x17U 2351 typedef struct 2352 { 2353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2354 uint8_t slave0_numop : 3; 2355 uint8_t batch_ext_sens_0_en : 1; 2356 uint8_t not_used_01 : 2; 2357 uint8_t shub_odr : 2; 2358 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2359 uint8_t shub_odr : 2; 2360 uint8_t not_used_01 : 2; 2361 uint8_t batch_ext_sens_0_en : 1; 2362 uint8_t slave0_numop : 3; 2363 #endif /* DRV_BYTE_ORDER */ 2364 } lsm6dso32_slv0_config_t; 2365 2366 #define LSM6DSO32_SLV1_ADD 0x18U 2367 typedef struct 2368 { 2369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2370 uint8_t r_1 : 1; 2371 uint8_t slave1_add : 7; 2372 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2373 uint8_t slave1_add : 7; 2374 uint8_t r_1 : 1; 2375 #endif /* DRV_BYTE_ORDER */ 2376 } lsm6dso32_slv1_add_t; 2377 2378 #define LSM6DSO32_SLV1_SUBADD 0x19U 2379 typedef struct 2380 { 2381 uint8_t slave1_reg : 8; 2382 } lsm6dso32_slv1_subadd_t; 2383 2384 #define LSM6DSO32_SLV1_CONFIG 0x1AU 2385 typedef struct 2386 { 2387 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2388 uint8_t slave1_numop : 3; 2389 uint8_t batch_ext_sens_1_en : 1; 2390 uint8_t not_used_01 : 4; 2391 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2392 uint8_t not_used_01 : 4; 2393 uint8_t batch_ext_sens_1_en : 1; 2394 uint8_t slave1_numop : 3; 2395 #endif /* DRV_BYTE_ORDER */ 2396 } lsm6dso32_slv1_config_t; 2397 2398 #define LSM6DSO32_SLV2_ADD 0x1BU 2399 typedef struct 2400 { 2401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2402 uint8_t r_2 : 1; 2403 uint8_t slave2_add : 7; 2404 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2405 uint8_t slave2_add : 7; 2406 uint8_t r_2 : 1; 2407 #endif /* DRV_BYTE_ORDER */ 2408 } lsm6dso32_slv2_add_t; 2409 2410 #define LSM6DSO32_SLV2_SUBADD 0x1CU 2411 typedef struct 2412 { 2413 uint8_t slave2_reg : 8; 2414 } lsm6dso32_slv2_subadd_t; 2415 2416 #define LSM6DSO32_SLV2_CONFIG 0x1DU 2417 typedef struct 2418 { 2419 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2420 uint8_t slave2_numop : 3; 2421 uint8_t batch_ext_sens_2_en : 1; 2422 uint8_t not_used_01 : 4; 2423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2424 uint8_t not_used_01 : 4; 2425 uint8_t batch_ext_sens_2_en : 1; 2426 uint8_t slave2_numop : 3; 2427 #endif /* DRV_BYTE_ORDER */ 2428 } lsm6dso32_slv2_config_t; 2429 2430 #define LSM6DSO32_SLV3_ADD 0x1EU 2431 typedef struct 2432 { 2433 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2434 uint8_t r_3 : 1; 2435 uint8_t slave3_add : 7; 2436 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2437 uint8_t slave3_add : 7; 2438 uint8_t r_3 : 1; 2439 #endif /* DRV_BYTE_ORDER */ 2440 } lsm6dso32_slv3_add_t; 2441 2442 #define LSM6DSO32_SLV3_SUBADD 0x1FU 2443 typedef struct 2444 { 2445 uint8_t slave3_reg : 8; 2446 } lsm6dso32_slv3_subadd_t; 2447 2448 #define LSM6DSO32_SLV3_CONFIG 0x20U 2449 typedef struct 2450 { 2451 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2452 uint8_t slave3_numop : 3; 2453 uint8_t batch_ext_sens_3_en : 1; 2454 uint8_t not_used_01 : 4; 2455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2456 uint8_t not_used_01 : 4; 2457 uint8_t batch_ext_sens_3_en : 1; 2458 uint8_t slave3_numop : 3; 2459 #endif /* DRV_BYTE_ORDER */ 2460 } lsm6dso32_slv3_config_t; 2461 2462 #define LSM6DSO32_DATAWRITE_SLV0 0x21U 2463 typedef struct 2464 { 2465 uint8_t slave0_dataw : 8; 2466 } lsm6dso32_datawrite_src_mode_sub_slv0_t; 2467 2468 #define LSM6DSO32_STATUS_MASTER 0x22U 2469 typedef struct 2470 { 2471 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2472 uint8_t sens_hub_endop : 1; 2473 uint8_t not_used_01 : 2; 2474 uint8_t slave0_nack : 1; 2475 uint8_t slave1_nack : 1; 2476 uint8_t slave2_nack : 1; 2477 uint8_t slave3_nack : 1; 2478 uint8_t wr_once_done : 1; 2479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2480 uint8_t wr_once_done : 1; 2481 uint8_t slave3_nack : 1; 2482 uint8_t slave2_nack : 1; 2483 uint8_t slave1_nack : 1; 2484 uint8_t slave0_nack : 1; 2485 uint8_t not_used_01 : 2; 2486 uint8_t sens_hub_endop : 1; 2487 #endif /* DRV_BYTE_ORDER */ 2488 } lsm6dso32_status_master_t; 2489 2490 /** 2491 * @defgroup LSM6DSO32_Register_Union 2492 * @brief This union group all the registers having a bit-field 2493 * description. 2494 * This union is useful but it's not needed by the driver. 2495 * 2496 * REMOVING this union you are compliant with: 2497 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2498 * 2499 * @{ 2500 * 2501 */ 2502 typedef union 2503 { 2504 lsm6dso32_func_cfg_access_t func_cfg_access; 2505 lsm6dso32_pin_ctrl_t pin_ctrl; 2506 lsm6dso32_fifo_ctrl1_t fifo_ctrl1; 2507 lsm6dso32_fifo_ctrl2_t fifo_ctrl2; 2508 lsm6dso32_fifo_ctrl3_t fifo_ctrl3; 2509 lsm6dso32_fifo_ctrl4_t fifo_ctrl4; 2510 lsm6dso32_counter_bdr_reg1_t counter_bdr_reg1; 2511 lsm6dso32_counter_bdr_reg2_t counter_bdr_reg2; 2512 lsm6dso32_int1_ctrl_t int1_ctrl; 2513 lsm6dso32_int2_ctrl_t int2_ctrl; 2514 lsm6dso32_ctrl1_xl_t ctrl1_xl; 2515 lsm6dso32_ctrl2_g_t ctrl2_g; 2516 lsm6dso32_ctrl3_c_t ctrl3_c; 2517 lsm6dso32_ctrl4_c_t ctrl4_c; 2518 lsm6dso32_ctrl5_c_t ctrl5_c; 2519 lsm6dso32_ctrl6_c_t ctrl6_c; 2520 lsm6dso32_ctrl7_g_t ctrl7_g; 2521 lsm6dso32_ctrl8_xl_t ctrl8_xl; 2522 lsm6dso32_ctrl9_xl_t ctrl9_xl; 2523 lsm6dso32_ctrl10_c_t ctrl10_c; 2524 lsm6dso32_all_int_src_t all_int_src; 2525 lsm6dso32_wake_up_src_t wake_up_src; 2526 lsm6dso32_tap_src_t tap_src; 2527 lsm6dso32_d6d_src_t d6d_src; 2528 lsm6dso32_status_reg_t status_reg; 2529 lsm6dso32_fifo_status1_t fifo_status1; 2530 lsm6dso32_fifo_status2_t fifo_status2; 2531 lsm6dso32_tap_cfg0_t tap_cfg0; 2532 lsm6dso32_tap_cfg1_t tap_cfg1; 2533 lsm6dso32_tap_cfg2_t tap_cfg2; 2534 lsm6dso32_tap_ths_6d_t tap_ths_6d; 2535 lsm6dso32_int_dur2_t int_dur2; 2536 lsm6dso32_wake_up_ths_t wake_up_ths; 2537 lsm6dso32_wake_up_dur_t wake_up_dur; 2538 lsm6dso32_free_fall_t free_fall; 2539 lsm6dso32_md1_cfg_t md1_cfg; 2540 lsm6dso32_md2_cfg_t md2_cfg; 2541 lsm6dso32_i3c_bus_avb_t i3c_bus_avb; 2542 lsm6dso32_internal_freq_fine_t internal_freq_fine; 2543 lsm6dso32_fifo_data_out_tag_t fifo_data_out_tag; 2544 lsm6dso32_page_sel_t page_sel; 2545 lsm6dso32_emb_func_en_a_t emb_func_en_a; 2546 lsm6dso32_emb_func_en_b_t emb_func_en_b; 2547 lsm6dso32_page_address_t page_address; 2548 lsm6dso32_page_value_t page_value; 2549 lsm6dso32_emb_func_int1_t emb_func_int1; 2550 lsm6dso32_fsm_int1_a_t fsm_int1_a; 2551 lsm6dso32_fsm_int1_b_t fsm_int1_b; 2552 lsm6dso32_emb_func_int2_t emb_func_int2; 2553 lsm6dso32_fsm_int2_a_t fsm_int2_a; 2554 lsm6dso32_fsm_int2_b_t fsm_int2_b; 2555 lsm6dso32_emb_func_status_t emb_func_status; 2556 lsm6dso32_fsm_status_a_t fsm_status_a; 2557 lsm6dso32_fsm_status_b_t fsm_status_b; 2558 lsm6dso32_page_rw_t page_rw; 2559 lsm6dso32_emb_func_fifo_cfg_t emb_func_fifo_cfg; 2560 lsm6dso32_fsm_enable_a_t fsm_enable_a; 2561 lsm6dso32_fsm_enable_b_t fsm_enable_b; 2562 lsm6dso32_fsm_long_counter_clear_t fsm_long_counter_clear; 2563 lsm6dso32_fsm_outs1_t fsm_outs1; 2564 lsm6dso32_fsm_outs2_t fsm_outs2; 2565 lsm6dso32_fsm_outs3_t fsm_outs3; 2566 lsm6dso32_fsm_outs4_t fsm_outs4; 2567 lsm6dso32_fsm_outs5_t fsm_outs5; 2568 lsm6dso32_fsm_outs6_t fsm_outs6; 2569 lsm6dso32_fsm_outs7_t fsm_outs7; 2570 lsm6dso32_fsm_outs8_t fsm_outs8; 2571 lsm6dso32_fsm_outs9_t fsm_outs9; 2572 lsm6dso32_fsm_outs10_t fsm_outs10; 2573 lsm6dso32_fsm_outs11_t fsm_outs11; 2574 lsm6dso32_fsm_outs12_t fsm_outs12; 2575 lsm6dso32_fsm_outs13_t fsm_outs13; 2576 lsm6dso32_fsm_outs14_t fsm_outs14; 2577 lsm6dso32_fsm_outs15_t fsm_outs15; 2578 lsm6dso32_fsm_outs16_t fsm_outs16; 2579 lsm6dso32_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2580 lsm6dso32_emb_func_src_t emb_func_src; 2581 lsm6dso32_emb_func_init_a_t emb_func_init_a; 2582 lsm6dso32_emb_func_init_b_t emb_func_init_b; 2583 lsm6dso32_mag_cfg_a_t mag_cfg_a; 2584 lsm6dso32_mag_cfg_b_t mag_cfg_b; 2585 lsm6dso32_pedo_cmd_reg_t pedo_cmd_reg; 2586 lsm6dso32_sensor_hub_1_t sensor_hub_1; 2587 lsm6dso32_sensor_hub_2_t sensor_hub_2; 2588 lsm6dso32_sensor_hub_3_t sensor_hub_3; 2589 lsm6dso32_sensor_hub_4_t sensor_hub_4; 2590 lsm6dso32_sensor_hub_5_t sensor_hub_5; 2591 lsm6dso32_sensor_hub_6_t sensor_hub_6; 2592 lsm6dso32_sensor_hub_7_t sensor_hub_7; 2593 lsm6dso32_sensor_hub_8_t sensor_hub_8; 2594 lsm6dso32_sensor_hub_9_t sensor_hub_9; 2595 lsm6dso32_sensor_hub_10_t sensor_hub_10; 2596 lsm6dso32_sensor_hub_11_t sensor_hub_11; 2597 lsm6dso32_sensor_hub_12_t sensor_hub_12; 2598 lsm6dso32_sensor_hub_13_t sensor_hub_13; 2599 lsm6dso32_sensor_hub_14_t sensor_hub_14; 2600 lsm6dso32_sensor_hub_15_t sensor_hub_15; 2601 lsm6dso32_sensor_hub_16_t sensor_hub_16; 2602 lsm6dso32_sensor_hub_17_t sensor_hub_17; 2603 lsm6dso32_sensor_hub_18_t sensor_hub_18; 2604 lsm6dso32_master_config_t master_config; 2605 lsm6dso32_slv0_add_t slv0_add; 2606 lsm6dso32_slv0_subadd_t slv0_subadd; 2607 lsm6dso32_slv0_config_t slv0_config; 2608 lsm6dso32_slv1_add_t slv1_add; 2609 lsm6dso32_slv1_subadd_t slv1_subadd; 2610 lsm6dso32_slv1_config_t slv1_config; 2611 lsm6dso32_slv2_add_t slv2_add; 2612 lsm6dso32_slv2_subadd_t slv2_subadd; 2613 lsm6dso32_slv2_config_t slv2_config; 2614 lsm6dso32_slv3_add_t slv3_add; 2615 lsm6dso32_slv3_subadd_t slv3_subadd; 2616 lsm6dso32_slv3_config_t slv3_config; 2617 lsm6dso32_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0; 2618 lsm6dso32_status_master_t status_master; 2619 bitwise_t bitwise; 2620 uint8_t byte; 2621 } lsm6dso32_reg_t; 2622 2623 /** 2624 * @} 2625 * 2626 */ 2627 2628 #ifndef __weak 2629 #define __weak __attribute__((weak)) 2630 #endif /* __weak */ 2631 2632 /* 2633 * These are the basic platform dependent I/O routines to read 2634 * and write device registers connected on a standard bus. 2635 * The driver keeps offering a default implementation based on function 2636 * pointers to read/write routines for backward compatibility. 2637 * The __weak directive allows the final application to overwrite 2638 * them with a custom implementation. 2639 */ 2640 2641 int32_t lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 2642 uint8_t *data, 2643 uint16_t len); 2644 int32_t lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 2645 uint8_t *data, 2646 uint16_t len); 2647 2648 float_t lsm6dso32_from_fs4_to_mg(int16_t lsb); 2649 float_t lsm6dso32_from_fs8_to_mg(int16_t lsb); 2650 float_t lsm6dso32_from_fs16_to_mg(int16_t lsb); 2651 float_t lsm6dso32_from_fs32_to_mg(int16_t lsb); 2652 2653 float_t lsm6dso32_from_fs125_to_mdps(int16_t lsb); 2654 float_t lsm6dso32_from_fs250_to_mdps(int16_t lsb); 2655 float_t lsm6dso32_from_fs500_to_mdps(int16_t lsb); 2656 float_t lsm6dso32_from_fs1000_to_mdps(int16_t lsb); 2657 float_t lsm6dso32_from_fs2000_to_mdps(int16_t lsb); 2658 2659 float_t lsm6dso32_from_lsb_to_celsius(int16_t lsb); 2660 2661 float_t lsm6dso32_from_lsb_to_nsec(int16_t lsb); 2662 2663 typedef enum 2664 { 2665 LSM6DSO32_4g = 0x00, 2666 LSM6DSO32_8g = 0x02, 2667 LSM6DSO32_16g = 0x03, 2668 LSM6DSO32_32g = 0x01, 2669 } lsm6dso32_fs_xl_t; 2670 int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx, 2671 lsm6dso32_fs_xl_t val); 2672 int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx, 2673 lsm6dso32_fs_xl_t *val); 2674 2675 typedef enum 2676 { 2677 /* Accelerometer power off */ 2678 LSM6DSO32_XL_ODR_OFF = 0x00, 2679 /* Accelerometer low power mode */ 2680 LSM6DSO32_XL_ODR_6Hz5_LOW_PW = 0x1B, 2681 LSM6DSO32_XL_ODR_12Hz5_LOW_PW = 0x11, 2682 LSM6DSO32_XL_ODR_26Hz_LOW_PW = 0x12, 2683 LSM6DSO32_XL_ODR_52Hz_LOW_PW = 0x13, 2684 /* Accelerometer normal mode */ 2685 LSM6DSO32_XL_ODR_104Hz_NORMAL_MD = 0x14, 2686 LSM6DSO32_XL_ODR_208Hz_NORMAL_MD = 0x15, 2687 /* Accelerometer high performance */ 2688 LSM6DSO32_XL_ODR_12Hz5_HIGH_PERF = 0x01, 2689 LSM6DSO32_XL_ODR_26Hz_HIGH_PERF = 0x02, 2690 LSM6DSO32_XL_ODR_52Hz_HIGH_PERF = 0x03, 2691 LSM6DSO32_XL_ODR_104Hz_HIGH_PERF = 0x04, 2692 LSM6DSO32_XL_ODR_208Hz_HIGH_PERF = 0x05, 2693 LSM6DSO32_XL_ODR_417Hz_HIGH_PERF = 0x06, 2694 LSM6DSO32_XL_ODR_833Hz_HIGH_PERF = 0x07, 2695 LSM6DSO32_XL_ODR_1667Hz_HIGH_PERF = 0x08, 2696 LSM6DSO32_XL_ODR_3333Hz_HIGH_PERF = 0x09, 2697 LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF = 0x0A, 2698 /* Accelerometer ultra low power. 2699 * WARNING: Gyroscope must be in Power-Down mode when 2700 * accelerometer is in ultra low power mode. 2701 */ 2702 LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW = 0x2B, 2703 LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW = 0x21, 2704 LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW = 0x22, 2705 LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW = 0x23, 2706 LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW = 0x24, 2707 LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW = 0x25, 2708 } lsm6dso32_odr_xl_t; 2709 int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx, 2710 lsm6dso32_odr_xl_t val); 2711 int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx, 2712 lsm6dso32_odr_xl_t *val); 2713 2714 typedef enum 2715 { 2716 LSM6DSO32_250dps = 0, 2717 LSM6DSO32_125dps = 1, 2718 LSM6DSO32_500dps = 2, 2719 LSM6DSO32_1000dps = 4, 2720 LSM6DSO32_2000dps = 6, 2721 } lsm6dso32_fs_g_t; 2722 int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx, 2723 lsm6dso32_fs_g_t val); 2724 int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx, 2725 lsm6dso32_fs_g_t *val); 2726 2727 typedef enum 2728 { 2729 /* Gyroscope power off */ 2730 LSM6DSO32_GY_ODR_OFF = 0x00, 2731 /* Gyroscope high performance mode */ 2732 LSM6DSO32_GY_ODR_12Hz5_HIGH_PERF = 0x01, 2733 LSM6DSO32_GY_ODR_26Hz_HIGH_PERF = 0x02, 2734 LSM6DSO32_GY_ODR_52Hz_HIGH_PERF = 0x03, 2735 LSM6DSO32_GY_ODR_104Hz_HIGH_PERF = 0x04, 2736 LSM6DSO32_GY_ODR_208Hz_HIGH_PERF = 0x05, 2737 LSM6DSO32_GY_ODR_417Hz_HIGH_PERF = 0x06, 2738 LSM6DSO32_GY_ODR_833Hz_HIGH_PERF = 0x07, 2739 LSM6DSO32_GY_ODR_1667Hz_HIGH_PERF = 0x08, 2740 LSM6DSO32_GY_ODR_3333Hz_HIGH_PERF = 0x09, 2741 LSM6DSO32_GY_ODR_6667Hz_HIGH_PERF = 0x0A, 2742 /* Gyroscope normal mode */ 2743 LSM6DSO32_GY_ODR_104Hz_NORMAL_MD = 0x14, 2744 LSM6DSO32_GY_ODR_208Hz_NORMAL_MD = 0x15, 2745 /* Gyroscope low power mode */ 2746 LSM6DSO32_GY_ODR_12Hz5_LOW_PW = 0x11, 2747 LSM6DSO32_GY_ODR_26Hz_LOW_PW = 0x12, 2748 LSM6DSO32_GY_ODR_52Hz_LOW_PW = 0x13, 2749 } lsm6dso32_odr_g_t; 2750 int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx, 2751 lsm6dso32_odr_g_t val); 2752 int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx, 2753 lsm6dso32_odr_g_t *val); 2754 2755 int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx, 2756 uint8_t val); 2757 int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx, 2758 uint8_t *val); 2759 2760 typedef enum 2761 { 2762 LSM6DSO32_LSb_1mg = 0, 2763 LSM6DSO32_LSb_16mg = 1, 2764 } lsm6dso32_usr_off_w_t; 2765 int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx, 2766 lsm6dso32_usr_off_w_t val); 2767 int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx, 2768 lsm6dso32_usr_off_w_t *val); 2769 2770 typedef struct 2771 { 2772 lsm6dso32_all_int_src_t all_int_src; 2773 lsm6dso32_wake_up_src_t wake_up_src; 2774 lsm6dso32_tap_src_t tap_src; 2775 lsm6dso32_d6d_src_t d6d_src; 2776 lsm6dso32_status_reg_t status_reg; 2777 lsm6dso32_emb_func_status_t emb_func_status; 2778 lsm6dso32_fsm_status_a_t fsm_status_a; 2779 lsm6dso32_fsm_status_b_t fsm_status_b; 2780 } lsm6dso32_all_sources_t; 2781 int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx, 2782 lsm6dso32_all_sources_t *val); 2783 2784 int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx, 2785 lsm6dso32_status_reg_t *val); 2786 2787 int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2788 uint8_t *val); 2789 2790 int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 2791 uint8_t *val); 2792 2793 int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 2794 uint8_t *val); 2795 2796 int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx, 2797 uint8_t *buff); 2798 int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx, 2799 uint8_t *buff); 2800 2801 int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx, 2802 uint8_t *buff); 2803 int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx, 2804 uint8_t *buff); 2805 2806 int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx, 2807 uint8_t *buff); 2808 int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx, 2809 uint8_t *buff); 2810 2811 int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); 2812 int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); 2813 2814 int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2815 int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2816 2817 int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val); 2818 2819 typedef enum 2820 { 2821 LSM6DSO32_NO_ROUND = 0, 2822 LSM6DSO32_ROUND_XL = 1, 2823 LSM6DSO32_ROUND_GY = 2, 2824 LSM6DSO32_ROUND_GY_XL = 3, 2825 } lsm6dso32_rounding_t; 2826 int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx, 2827 lsm6dso32_rounding_t val); 2828 int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx, 2829 lsm6dso32_rounding_t *val); 2830 2831 int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, 2832 int16_t *val); 2833 2834 int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx, 2835 int16_t *val); 2836 2837 int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx, 2838 int16_t *val); 2839 2840 int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); 2841 2842 int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx, 2843 uint16_t *val); 2844 2845 int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx); 2846 2847 int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2848 int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2849 2850 typedef enum 2851 { 2852 LSM6DSO32_USER_BANK = 0, 2853 LSM6DSO32_SENSOR_HUB_BANK = 1, 2854 LSM6DSO32_EMBEDDED_FUNC_BANK = 2, 2855 } lsm6dso32_reg_access_t; 2856 int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx, 2857 lsm6dso32_reg_access_t val); 2858 int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx, 2859 lsm6dso32_reg_access_t *val); 2860 2861 int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx, 2862 uint16_t address, 2863 uint8_t *val); 2864 int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address, 2865 uint8_t *val); 2866 int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 2867 uint8_t *buf, uint8_t len); 2868 int32_t lsm6dso32_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 2869 uint8_t *val); 2870 2871 typedef enum 2872 { 2873 LSM6DSO32_DRDY_LATCHED = 0, 2874 LSM6DSO32_DRDY_PULSED = 1, 2875 } lsm6dso32_dataready_pulsed_t; 2876 int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx, 2877 lsm6dso32_dataready_pulsed_t val); 2878 int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx, 2879 lsm6dso32_dataready_pulsed_t *val); 2880 2881 int32_t lsm6dso32_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 2882 2883 int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2884 int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2885 2886 int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2887 int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2888 2889 int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2890 int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2891 2892 typedef enum 2893 { 2894 LSM6DSO32_XL_ST_DISABLE = 0, 2895 LSM6DSO32_XL_ST_POSITIVE = 1, 2896 LSM6DSO32_XL_ST_NEGATIVE = 2, 2897 } lsm6dso32_st_xl_t; 2898 int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx, 2899 lsm6dso32_st_xl_t val); 2900 int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx, 2901 lsm6dso32_st_xl_t *val); 2902 2903 typedef enum 2904 { 2905 LSM6DSO32_GY_ST_DISABLE = 0, 2906 LSM6DSO32_GY_ST_POSITIVE = 1, 2907 LSM6DSO32_GY_ST_NEGATIVE = 3, 2908 } lsm6dso32_st_g_t; 2909 int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx, 2910 lsm6dso32_st_g_t val); 2911 int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx, 2912 lsm6dso32_st_g_t *val); 2913 2914 int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 2915 int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 2916 2917 int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val); 2918 int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val); 2919 2920 int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx, 2921 uint8_t val); 2922 int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx, 2923 uint8_t *val); 2924 2925 typedef enum 2926 { 2927 LSM6DSO32_ULTRA_LIGHT = 0, 2928 LSM6DSO32_VERY_LIGHT = 1, 2929 LSM6DSO32_LIGHT = 2, 2930 LSM6DSO32_MEDIUM = 3, 2931 LSM6DSO32_STRONG = 4, /* not available for data rate > 1k670Hz */ 2932 LSM6DSO32_VERY_STRONG = 5, /* not available for data rate > 1k670Hz */ 2933 LSM6DSO32_AGGRESSIVE = 6, /* not available for data rate > 1k670Hz */ 2934 LSM6DSO32_XTREME = 7, /* not available for data rate > 1k670Hz */ 2935 } lsm6dso32_ftype_t; 2936 int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx, 2937 lsm6dso32_ftype_t val); 2938 int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx, 2939 lsm6dso32_ftype_t *val); 2940 2941 int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val); 2942 int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val); 2943 2944 typedef enum 2945 { 2946 LSM6DSO32_HP_PATH_DISABLE_ON_OUT = 0x00, 2947 LSM6DSO32_SLOPE_ODR_DIV_4 = 0x10, 2948 LSM6DSO32_HP_ODR_DIV_10 = 0x11, 2949 LSM6DSO32_HP_ODR_DIV_20 = 0x12, 2950 LSM6DSO32_HP_ODR_DIV_45 = 0x13, 2951 LSM6DSO32_HP_ODR_DIV_100 = 0x14, 2952 LSM6DSO32_HP_ODR_DIV_200 = 0x15, 2953 LSM6DSO32_HP_ODR_DIV_400 = 0x16, 2954 LSM6DSO32_HP_ODR_DIV_800 = 0x17, 2955 LSM6DSO32_HP_REF_MD_ODR_DIV_10 = 0x31, 2956 LSM6DSO32_HP_REF_MD_ODR_DIV_20 = 0x32, 2957 LSM6DSO32_HP_REF_MD_ODR_DIV_45 = 0x33, 2958 LSM6DSO32_HP_REF_MD_ODR_DIV_100 = 0x34, 2959 LSM6DSO32_HP_REF_MD_ODR_DIV_200 = 0x35, 2960 LSM6DSO32_HP_REF_MD_ODR_DIV_400 = 0x36, 2961 LSM6DSO32_HP_REF_MD_ODR_DIV_800 = 0x37, 2962 LSM6DSO32_LP_ODR_DIV_10 = 0x01, 2963 LSM6DSO32_LP_ODR_DIV_20 = 0x02, 2964 LSM6DSO32_LP_ODR_DIV_45 = 0x03, 2965 LSM6DSO32_LP_ODR_DIV_100 = 0x04, 2966 LSM6DSO32_LP_ODR_DIV_200 = 0x05, 2967 LSM6DSO32_LP_ODR_DIV_400 = 0x06, 2968 LSM6DSO32_LP_ODR_DIV_800 = 0x07, 2969 } lsm6dso32_hp_slope_xl_en_t; 2970 int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, 2971 lsm6dso32_hp_slope_xl_en_t val); 2972 int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, 2973 lsm6dso32_hp_slope_xl_en_t *val); 2974 2975 int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, 2976 uint8_t val); 2977 int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx, 2978 uint8_t *val); 2979 2980 typedef enum 2981 { 2982 LSM6DSO32_USE_SLOPE = 0, 2983 LSM6DSO32_USE_HPF = 1, 2984 } lsm6dso32_slope_fds_t; 2985 int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 2986 lsm6dso32_slope_fds_t val); 2987 int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 2988 lsm6dso32_slope_fds_t *val); 2989 2990 typedef enum 2991 { 2992 LSM6DSO32_HP_FILTER_NONE = 0x00, 2993 LSM6DSO32_HP_FILTER_16mHz = 0x80, 2994 LSM6DSO32_HP_FILTER_65mHz = 0x81, 2995 LSM6DSO32_HP_FILTER_260mHz = 0x82, 2996 LSM6DSO32_HP_FILTER_1Hz04 = 0x83, 2997 } lsm6dso32_hpm_g_t; 2998 int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx, 2999 lsm6dso32_hpm_g_t val); 3000 int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx, 3001 lsm6dso32_hpm_g_t *val); 3002 3003 typedef enum 3004 { 3005 LSM6DSO32_PULL_UP_DISC = 0, 3006 LSM6DSO32_PULL_UP_CONNECT = 1, 3007 } lsm6dso32_sdo_pu_en_t; 3008 int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 3009 lsm6dso32_sdo_pu_en_t val); 3010 int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 3011 lsm6dso32_sdo_pu_en_t *val); 3012 3013 typedef enum 3014 { 3015 LSM6DSO32_SPI_4_WIRE = 0, 3016 LSM6DSO32_SPI_3_WIRE = 1, 3017 } lsm6dso32_sim_t; 3018 int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, 3019 lsm6dso32_sim_t val); 3020 int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx, 3021 lsm6dso32_sim_t *val); 3022 3023 typedef enum 3024 { 3025 LSM6DSO32_I2C_ENABLE = 0, 3026 LSM6DSO32_I2C_DISABLE = 1, 3027 } lsm6dso32_i2c_disable_t; 3028 int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx, 3029 lsm6dso32_i2c_disable_t val); 3030 int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx, 3031 lsm6dso32_i2c_disable_t *val); 3032 3033 typedef enum 3034 { 3035 LSM6DSO32_I3C_DISABLE = 0x80, 3036 LSM6DSO32_I3C_ENABLE_T_50us = 0x00, 3037 LSM6DSO32_I3C_ENABLE_T_2us = 0x01, 3038 LSM6DSO32_I3C_ENABLE_T_1ms = 0x02, 3039 LSM6DSO32_I3C_ENABLE_T_25ms = 0x03, 3040 } lsm6dso32_i3c_disable_t; 3041 int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx, 3042 lsm6dso32_i3c_disable_t val); 3043 int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx, 3044 lsm6dso32_i3c_disable_t *val); 3045 3046 typedef enum 3047 { 3048 LSM6DSO32_PULL_DOWN_DISC = 0, 3049 LSM6DSO32_PULL_DOWN_CONNECT = 1, 3050 } lsm6dso32_int1_pd_en_t; 3051 int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx, 3052 lsm6dso32_int1_pd_en_t val); 3053 int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx, 3054 lsm6dso32_int1_pd_en_t *val); 3055 3056 typedef struct 3057 { 3058 lsm6dso32_int1_ctrl_t int1_ctrl; 3059 lsm6dso32_md1_cfg_t md1_cfg; 3060 lsm6dso32_emb_func_int1_t emb_func_int1; 3061 lsm6dso32_fsm_int1_a_t fsm_int1_a; 3062 lsm6dso32_fsm_int1_b_t fsm_int1_b; 3063 } lsm6dso32_pin_int1_route_t; 3064 int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx, 3065 lsm6dso32_pin_int1_route_t *val); 3066 int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx, 3067 lsm6dso32_pin_int1_route_t *val); 3068 3069 typedef struct 3070 { 3071 lsm6dso32_int2_ctrl_t int2_ctrl; 3072 lsm6dso32_md2_cfg_t md2_cfg; 3073 lsm6dso32_emb_func_int2_t emb_func_int2; 3074 lsm6dso32_fsm_int2_a_t fsm_int2_a; 3075 lsm6dso32_fsm_int2_b_t fsm_int2_b; 3076 } lsm6dso32_pin_int2_route_t; 3077 int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx, 3078 lsm6dso32_pin_int2_route_t *val); 3079 int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx, 3080 lsm6dso32_pin_int2_route_t *val); 3081 3082 typedef enum 3083 { 3084 LSM6DSO32_PUSH_PULL = 0, 3085 LSM6DSO32_OPEN_DRAIN = 1, 3086 } lsm6dso32_pp_od_t; 3087 int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx, 3088 lsm6dso32_pp_od_t val); 3089 int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx, 3090 lsm6dso32_pp_od_t *val); 3091 3092 typedef enum 3093 { 3094 LSM6DSO32_ACTIVE_HIGH = 0, 3095 LSM6DSO32_ACTIVE_LOW = 1, 3096 } lsm6dso32_h_lactive_t; 3097 int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx, 3098 lsm6dso32_h_lactive_t val); 3099 int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx, 3100 lsm6dso32_h_lactive_t *val); 3101 3102 int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 3103 int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 3104 3105 typedef enum 3106 { 3107 LSM6DSO32_ALL_INT_PULSED = 0, 3108 LSM6DSO32_BASE_LATCHED_EMB_PULSED = 1, 3109 LSM6DSO32_BASE_PULSED_EMB_LATCHED = 2, 3110 LSM6DSO32_ALL_INT_LATCHED = 3, 3111 } lsm6dso32_lir_t; 3112 int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx, 3113 lsm6dso32_lir_t val); 3114 int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx, 3115 lsm6dso32_lir_t *val); 3116 3117 typedef enum 3118 { 3119 LSM6DSO32_LSb_FS_DIV_64 = 0, 3120 LSM6DSO32_LSb_FS_DIV_256 = 1, 3121 } lsm6dso32_wake_ths_w_t; 3122 int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx, 3123 lsm6dso32_wake_ths_w_t val); 3124 int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx, 3125 lsm6dso32_wake_ths_w_t *val); 3126 3127 int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 3128 int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 3129 3130 int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, 3131 uint8_t val); 3132 int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, 3133 uint8_t *val); 3134 3135 int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3136 int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3137 3138 int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3139 int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3140 3141 typedef enum 3142 { 3143 LSM6DSO32_DRIVE_SLEEP_CHG_EVENT = 0, 3144 LSM6DSO32_DRIVE_SLEEP_STATUS = 1, 3145 } lsm6dso32_sleep_status_on_int_t; 3146 int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx, 3147 lsm6dso32_sleep_status_on_int_t val); 3148 int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx, 3149 lsm6dso32_sleep_status_on_int_t *val); 3150 3151 typedef enum 3152 { 3153 LSM6DSO32_XL_AND_GY_NOT_AFFECTED = 0, 3154 LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED = 1, 3155 LSM6DSO32_XL_12Hz5_GY_SLEEP = 2, 3156 LSM6DSO32_XL_12Hz5_GY_PD = 3, 3157 } lsm6dso32_inact_en_t; 3158 int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx, 3159 lsm6dso32_inact_en_t val); 3160 int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx, 3161 lsm6dso32_inact_en_t *val); 3162 3163 int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3164 int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3165 3166 int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx, 3167 uint8_t val); 3168 int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx, 3169 uint8_t *val); 3170 3171 int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx, 3172 uint8_t val); 3173 int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx, 3174 uint8_t *val); 3175 3176 int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx, 3177 uint8_t val); 3178 int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx, 3179 uint8_t *val); 3180 3181 int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); 3182 int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, 3183 uint8_t *val); 3184 3185 typedef enum 3186 { 3187 LSM6DSO32_XYZ = 0, 3188 LSM6DSO32_YXZ = 1, 3189 LSM6DSO32_XZY = 2, 3190 LSM6DSO32_ZYX = 3, 3191 LSM6DSO32_YZX = 5, 3192 LSM6DSO32_ZXY = 6, 3193 } lsm6dso32_tap_priority_t; 3194 int32_t lsm6dso32_tap_axis_priority_set(stmdev_ctx_t *ctx, 3195 lsm6dso32_tap_priority_t val); 3196 int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx, 3197 lsm6dso32_tap_priority_t *val); 3198 3199 int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); 3200 int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, 3201 uint8_t *val); 3202 3203 int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val); 3204 int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, 3205 uint8_t *val); 3206 3207 int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 3208 int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 3209 3210 int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 3211 int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 3212 3213 int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3214 int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3215 3216 typedef enum 3217 { 3218 LSM6DSO32_ONLY_SINGLE = 0, 3219 LSM6DSO32_BOTH_SINGLE_DOUBLE = 1, 3220 } lsm6dso32_single_double_tap_t; 3221 int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx, 3222 lsm6dso32_single_double_tap_t val); 3223 int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx, 3224 lsm6dso32_single_double_tap_t *val); 3225 3226 typedef enum 3227 { 3228 LSM6DSO32_DEG_68 = 0, 3229 LSM6DSO32_DEG_47 = 1, 3230 } lsm6dso32_sixd_ths_t; 3231 int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx, 3232 lsm6dso32_sixd_ths_t val); 3233 int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx, 3234 lsm6dso32_sixd_ths_t *val); 3235 3236 int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 3237 int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 3238 3239 typedef enum 3240 { 3241 LSM6DSO32_FF_TSH_312mg = 0, 3242 LSM6DSO32_FF_TSH_438mg = 1, 3243 LSM6DSO32_FF_TSH_500mg = 2, 3244 } lsm6dso32_ff_ths_t; 3245 int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx, 3246 lsm6dso32_ff_ths_t val); 3247 int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx, 3248 lsm6dso32_ff_ths_t *val); 3249 3250 int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 3251 int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 3252 3253 int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 3254 int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, 3255 uint16_t *val); 3256 3257 int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx, 3258 uint8_t val); 3259 int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx, 3260 uint8_t *val); 3261 3262 typedef enum 3263 { 3264 LSM6DSO32_CMP_DISABLE = 0x00, 3265 LSM6DSO32_CMP_ALWAYS = 0x04, 3266 LSM6DSO32_CMP_8_TO_1 = 0x05, 3267 LSM6DSO32_CMP_16_TO_1 = 0x06, 3268 LSM6DSO32_CMP_32_TO_1 = 0x07, 3269 } lsm6dso32_uncoptr_rate_t; 3270 int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx, 3271 lsm6dso32_uncoptr_rate_t val); 3272 int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx, 3273 lsm6dso32_uncoptr_rate_t *val); 3274 3275 int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 3276 uint8_t val); 3277 int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 3278 uint8_t *val); 3279 3280 int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx, 3281 uint8_t val); 3282 int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx, 3283 uint8_t *val); 3284 3285 int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, 3286 uint8_t val); 3287 int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, 3288 uint8_t *val); 3289 3290 typedef enum 3291 { 3292 LSM6DSO32_XL_NOT_BATCHED = 0, 3293 LSM6DSO32_XL_BATCHED_AT_12Hz5 = 1, 3294 LSM6DSO32_XL_BATCHED_AT_26Hz = 2, 3295 LSM6DSO32_XL_BATCHED_AT_52Hz = 3, 3296 LSM6DSO32_XL_BATCHED_AT_104Hz = 4, 3297 LSM6DSO32_XL_BATCHED_AT_208Hz = 5, 3298 LSM6DSO32_XL_BATCHED_AT_417Hz = 6, 3299 LSM6DSO32_XL_BATCHED_AT_833Hz = 7, 3300 LSM6DSO32_XL_BATCHED_AT_1667Hz = 8, 3301 LSM6DSO32_XL_BATCHED_AT_3333Hz = 9, 3302 LSM6DSO32_XL_BATCHED_AT_6667Hz = 10, 3303 LSM6DSO32_XL_BATCHED_AT_6Hz5 = 11, 3304 } lsm6dso32_bdr_xl_t; 3305 int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx, 3306 lsm6dso32_bdr_xl_t val); 3307 int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx, 3308 lsm6dso32_bdr_xl_t *val); 3309 3310 typedef enum 3311 { 3312 LSM6DSO32_GY_NOT_BATCHED = 0, 3313 LSM6DSO32_GY_BATCHED_AT_12Hz5 = 1, 3314 LSM6DSO32_GY_BATCHED_AT_26Hz = 2, 3315 LSM6DSO32_GY_BATCHED_AT_52Hz = 3, 3316 LSM6DSO32_GY_BATCHED_AT_104Hz = 4, 3317 LSM6DSO32_GY_BATCHED_AT_208Hz = 5, 3318 LSM6DSO32_GY_BATCHED_AT_417Hz = 6, 3319 LSM6DSO32_GY_BATCHED_AT_833Hz = 7, 3320 LSM6DSO32_GY_BATCHED_AT_1667Hz = 8, 3321 LSM6DSO32_GY_BATCHED_AT_3333Hz = 9, 3322 LSM6DSO32_GY_BATCHED_AT_6667Hz = 10, 3323 LSM6DSO32_GY_BATCHED_AT_6Hz5 = 11, 3324 } lsm6dso32_bdr_gy_t; 3325 int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx, 3326 lsm6dso32_bdr_gy_t val); 3327 int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx, 3328 lsm6dso32_bdr_gy_t *val); 3329 3330 typedef enum 3331 { 3332 LSM6DSO32_BYPASS_MODE = 0, 3333 LSM6DSO32_FIFO_MODE = 1, 3334 LSM6DSO32_STREAM_TO_FIFO_MODE = 3, 3335 LSM6DSO32_BYPASS_TO_STREAM_MODE = 4, 3336 LSM6DSO32_STREAM_MODE = 6, 3337 LSM6DSO32_BYPASS_TO_FIFO_MODE = 7, 3338 } lsm6dso32_fifo_mode_t; 3339 int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx, 3340 lsm6dso32_fifo_mode_t val); 3341 int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx, 3342 lsm6dso32_fifo_mode_t *val); 3343 3344 typedef enum 3345 { 3346 LSM6DSO32_TEMP_NOT_BATCHED = 0, 3347 LSM6DSO32_TEMP_BATCHED_AT_1Hz6 = 1, 3348 LSM6DSO32_TEMP_BATCHED_AT_12Hz5 = 2, 3349 LSM6DSO32_TEMP_BATCHED_AT_52Hz = 3, 3350 } lsm6dso32_odr_t_batch_t; 3351 int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx, 3352 lsm6dso32_odr_t_batch_t val); 3353 int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx, 3354 lsm6dso32_odr_t_batch_t *val); 3355 3356 typedef enum 3357 { 3358 LSM6DSO32_NO_DECIMATION = 0, 3359 LSM6DSO32_DEC_1 = 1, 3360 LSM6DSO32_DEC_8 = 2, 3361 LSM6DSO32_DEC_32 = 3, 3362 } lsm6dso32_odr_ts_batch_t; 3363 int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, 3364 lsm6dso32_odr_ts_batch_t val); 3365 int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, 3366 lsm6dso32_odr_ts_batch_t *val); 3367 3368 typedef enum 3369 { 3370 LSM6DSO32_XL_BATCH_EVENT = 0, 3371 LSM6DSO32_GYRO_BATCH_EVENT = 1, 3372 } lsm6dso32_trig_counter_bdr_t; 3373 3374 typedef enum 3375 { 3376 LSM6DSO32_GYRO_NC_TAG = 1, 3377 LSM6DSO32_XL_NC_TAG, 3378 LSM6DSO32_TEMPERATURE_TAG, 3379 LSM6DSO32_TIMESTAMP_TAG, 3380 LSM6DSO32_CFG_CHANGE_TAG, 3381 LSM6DSO32_XL_NC_T_2_TAG, 3382 LSM6DSO32_XL_NC_T_1_TAG, 3383 LSM6DSO32_XL_2XC_TAG, 3384 LSM6DSO32_XL_3XC_TAG, 3385 LSM6DSO32_GYRO_NC_T_2_TAG, 3386 LSM6DSO32_GYRO_NC_T_1_TAG, 3387 LSM6DSO32_GYRO_2XC_TAG, 3388 LSM6DSO32_GYRO_3XC_TAG, 3389 LSM6DSO32_SENSORHUB_SLAVE0_TAG, 3390 LSM6DSO32_SENSORHUB_SLAVE1_TAG, 3391 LSM6DSO32_SENSORHUB_SLAVE2_TAG, 3392 LSM6DSO32_SENSORHUB_SLAVE3_TAG, 3393 LSM6DSO32_STEP_COUNTER_TAG, 3394 LSM6DSO32_SENSORHUB_NACK_TAG = 0x19, 3395 } lsm6dso32_fifo_tag_t; 3396 int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx, 3397 lsm6dso32_trig_counter_bdr_t val); 3398 int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx, 3399 lsm6dso32_trig_counter_bdr_t *val); 3400 3401 int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx, 3402 uint8_t val); 3403 int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx, 3404 uint8_t *val); 3405 3406 int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx, 3407 uint16_t val); 3408 int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx, 3409 uint16_t *val); 3410 3411 int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx, 3412 uint16_t *val); 3413 3414 int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx, 3415 lsm6dso32_fifo_status2_t *val); 3416 3417 int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3418 3419 int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3420 3421 int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 3422 3423 int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx, 3424 lsm6dso32_fifo_tag_t *val); 3425 3426 int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); 3427 int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, 3428 uint8_t *val); 3429 3430 int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, 3431 uint8_t val); 3432 int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx, 3433 uint8_t *val); 3434 3435 int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, 3436 uint8_t val); 3437 int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx, 3438 uint8_t *val); 3439 3440 int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, 3441 uint8_t val); 3442 int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx, 3443 uint8_t *val); 3444 3445 int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, 3446 uint8_t val); 3447 int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx, 3448 uint8_t *val); 3449 3450 typedef enum 3451 { 3452 LSM6DSO32_DEN_DISABLE = 0, 3453 LSM6DSO32_LEVEL_FIFO = 6, 3454 LSM6DSO32_LEVEL_LETCHED = 3, 3455 LSM6DSO32_LEVEL_TRIGGER = 2, 3456 LSM6DSO32_EDGE_TRIGGER = 4, 3457 } lsm6dso32_den_mode_t; 3458 int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx, 3459 lsm6dso32_den_mode_t val); 3460 int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx, 3461 lsm6dso32_den_mode_t *val); 3462 3463 typedef enum 3464 { 3465 LSM6DSO32_DEN_ACT_LOW = 0, 3466 LSM6DSO32_DEN_ACT_HIGH = 1, 3467 } lsm6dso32_den_lh_t; 3468 int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx, 3469 lsm6dso32_den_lh_t val); 3470 int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx, 3471 lsm6dso32_den_lh_t *val); 3472 3473 typedef enum 3474 { 3475 LSM6DSO32_STAMP_IN_GY_DATA = 0, 3476 LSM6DSO32_STAMP_IN_XL_DATA = 1, 3477 LSM6DSO32_STAMP_IN_GY_XL_DATA = 2, 3478 } lsm6dso32_den_xl_g_t; 3479 int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx, 3480 lsm6dso32_den_xl_g_t val); 3481 int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx, 3482 lsm6dso32_den_xl_g_t *val); 3483 3484 int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 3485 int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, 3486 uint8_t *val); 3487 3488 int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 3489 int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, 3490 uint8_t *val); 3491 3492 int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); 3493 int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, 3494 uint8_t *val); 3495 3496 typedef enum 3497 { 3498 LSM6DSO32_PEDO_DISABLE = 0x00, 3499 LSM6DSO32_PEDO_BASE_MODE = 0x01, 3500 LSM6DSO32_PEDO_ADV_MODE = 0x03, 3501 LSM6DSO32_FALSE_STEP_REJ = 0x13, 3502 LSM6DSO32_FALSE_STEP_REJ_ADV_MODE = 0x33, 3503 } lsm6dso32_pedo_md_t; 3504 int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx, 3505 lsm6dso32_pedo_md_t val); 3506 int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx, 3507 lsm6dso32_pedo_md_t *val); 3508 3509 int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx, 3510 uint8_t *val); 3511 3512 int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 3513 uint8_t *buff); 3514 int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 3515 uint8_t *buff); 3516 3517 int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx, 3518 uint16_t val); 3519 int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx, 3520 uint16_t *val); 3521 3522 typedef enum 3523 { 3524 LSM6DSO32_EVERY_STEP = 0, 3525 LSM6DSO32_COUNT_OVERFLOW = 1, 3526 } lsm6dso32_carry_count_en_t; 3527 int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx, 3528 lsm6dso32_carry_count_en_t val); 3529 int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx, 3530 lsm6dso32_carry_count_en_t *val); 3531 3532 int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); 3533 int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 3534 3535 int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx, 3536 uint8_t *val); 3537 3538 int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); 3539 int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 3540 3541 int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx, 3542 uint8_t *val); 3543 3544 int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, 3545 uint16_t val); 3546 int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx, 3547 uint16_t *val); 3548 3549 int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 3550 int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 3551 3552 int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val); 3553 int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val); 3554 3555 typedef enum 3556 { 3557 LSM6DSO32_Z_EQ_Y = 0, 3558 LSM6DSO32_Z_EQ_MIN_Y = 1, 3559 LSM6DSO32_Z_EQ_X = 2, 3560 LSM6DSO32_Z_EQ_MIN_X = 3, 3561 LSM6DSO32_Z_EQ_MIN_Z = 4, 3562 LSM6DSO32_Z_EQ_Z = 5, 3563 } lsm6dso32_mag_z_axis_t; 3564 int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx, 3565 lsm6dso32_mag_z_axis_t val); 3566 int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx, 3567 lsm6dso32_mag_z_axis_t *val); 3568 3569 typedef enum 3570 { 3571 LSM6DSO32_Y_EQ_Y = 0, 3572 LSM6DSO32_Y_EQ_MIN_Y = 1, 3573 LSM6DSO32_Y_EQ_X = 2, 3574 LSM6DSO32_Y_EQ_MIN_X = 3, 3575 LSM6DSO32_Y_EQ_MIN_Z = 4, 3576 LSM6DSO32_Y_EQ_Z = 5, 3577 } lsm6dso32_mag_y_axis_t; 3578 int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx, 3579 lsm6dso32_mag_y_axis_t val); 3580 int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx, 3581 lsm6dso32_mag_y_axis_t *val); 3582 3583 typedef enum 3584 { 3585 LSM6DSO32_X_EQ_Y = 0, 3586 LSM6DSO32_X_EQ_MIN_Y = 1, 3587 LSM6DSO32_X_EQ_X = 2, 3588 LSM6DSO32_X_EQ_MIN_X = 3, 3589 LSM6DSO32_X_EQ_MIN_Z = 4, 3590 LSM6DSO32_X_EQ_Z = 5, 3591 } lsm6dso32_mag_x_axis_t; 3592 int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx, 3593 lsm6dso32_mag_x_axis_t val); 3594 int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx, 3595 lsm6dso32_mag_x_axis_t *val); 3596 3597 int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, 3598 uint8_t *val); 3599 3600 int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); 3601 int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); 3602 3603 typedef struct 3604 { 3605 lsm6dso32_fsm_enable_a_t fsm_enable_a; 3606 lsm6dso32_fsm_enable_b_t fsm_enable_b; 3607 } lsm6dso32_emb_fsm_enable_t; 3608 int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx, 3609 lsm6dso32_emb_fsm_enable_t *val); 3610 int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx, 3611 lsm6dso32_emb_fsm_enable_t *val); 3612 3613 int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 3614 int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 3615 3616 typedef enum 3617 { 3618 LSM6DSO32_LC_NORMAL = 0, 3619 LSM6DSO32_LC_CLEAR = 1, 3620 LSM6DSO32_LC_CLEAR_DONE = 2, 3621 } lsm6dso32_fsm_lc_clr_t; 3622 int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx, 3623 lsm6dso32_fsm_lc_clr_t val); 3624 int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx, 3625 lsm6dso32_fsm_lc_clr_t *val); 3626 3627 typedef struct 3628 { 3629 lsm6dso32_fsm_outs1_t fsm_outs1; 3630 lsm6dso32_fsm_outs2_t fsm_outs2; 3631 lsm6dso32_fsm_outs3_t fsm_outs3; 3632 lsm6dso32_fsm_outs4_t fsm_outs4; 3633 lsm6dso32_fsm_outs5_t fsm_outs5; 3634 lsm6dso32_fsm_outs6_t fsm_outs6; 3635 lsm6dso32_fsm_outs7_t fsm_outs7; 3636 lsm6dso32_fsm_outs8_t fsm_outs8; 3637 lsm6dso32_fsm_outs1_t fsm_outs9; 3638 lsm6dso32_fsm_outs2_t fsm_outs10; 3639 lsm6dso32_fsm_outs3_t fsm_outs11; 3640 lsm6dso32_fsm_outs4_t fsm_outs12; 3641 lsm6dso32_fsm_outs5_t fsm_outs13; 3642 lsm6dso32_fsm_outs6_t fsm_outs14; 3643 lsm6dso32_fsm_outs7_t fsm_outs15; 3644 lsm6dso32_fsm_outs8_t fsm_outs16; 3645 } lsm6dso32_fsm_out_t; 3646 int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx, 3647 lsm6dso32_fsm_out_t *val); 3648 3649 typedef enum 3650 { 3651 LSM6DSO32_ODR_FSM_12Hz5 = 0, 3652 LSM6DSO32_ODR_FSM_26Hz = 1, 3653 LSM6DSO32_ODR_FSM_52Hz = 2, 3654 LSM6DSO32_ODR_FSM_104Hz = 3, 3655 } lsm6dso32_fsm_odr_t; 3656 int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx, 3657 lsm6dso32_fsm_odr_t val); 3658 int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx, 3659 lsm6dso32_fsm_odr_t *val); 3660 3661 int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); 3662 int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); 3663 3664 int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx, 3665 uint16_t val); 3666 int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx, 3667 uint16_t *val); 3668 3669 int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx, 3670 uint8_t *buff); 3671 int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx, 3672 uint8_t *buff); 3673 3674 int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx, 3675 uint16_t val); 3676 int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx, 3677 uint16_t *val); 3678 3679 typedef struct 3680 { 3681 lsm6dso32_sensor_hub_1_t sh_byte_1; 3682 lsm6dso32_sensor_hub_2_t sh_byte_2; 3683 lsm6dso32_sensor_hub_3_t sh_byte_3; 3684 lsm6dso32_sensor_hub_4_t sh_byte_4; 3685 lsm6dso32_sensor_hub_5_t sh_byte_5; 3686 lsm6dso32_sensor_hub_6_t sh_byte_6; 3687 lsm6dso32_sensor_hub_7_t sh_byte_7; 3688 lsm6dso32_sensor_hub_8_t sh_byte_8; 3689 lsm6dso32_sensor_hub_9_t sh_byte_9; 3690 lsm6dso32_sensor_hub_10_t sh_byte_10; 3691 lsm6dso32_sensor_hub_11_t sh_byte_11; 3692 lsm6dso32_sensor_hub_12_t sh_byte_12; 3693 lsm6dso32_sensor_hub_13_t sh_byte_13; 3694 lsm6dso32_sensor_hub_14_t sh_byte_14; 3695 lsm6dso32_sensor_hub_15_t sh_byte_15; 3696 lsm6dso32_sensor_hub_16_t sh_byte_16; 3697 lsm6dso32_sensor_hub_17_t sh_byte_17; 3698 lsm6dso32_sensor_hub_18_t sh_byte_18; 3699 } lsm6dso32_emb_sh_read_t; 3700 int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx, 3701 lsm6dso32_emb_sh_read_t *val); 3702 3703 typedef enum 3704 { 3705 LSM6DSO32_SLV_0 = 0, 3706 LSM6DSO32_SLV_0_1 = 1, 3707 LSM6DSO32_SLV_0_1_2 = 2, 3708 LSM6DSO32_SLV_0_1_2_3 = 3, 3709 } lsm6dso32_aux_sens_on_t; 3710 int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx, 3711 lsm6dso32_aux_sens_on_t val); 3712 int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx, 3713 lsm6dso32_aux_sens_on_t *val); 3714 3715 int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 3716 int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 3717 3718 typedef enum 3719 { 3720 LSM6DSO32_EXT_PULL_UP = 0, 3721 LSM6DSO32_INTERNAL_PULL_UP = 1, 3722 } lsm6dso32_shub_pu_en_t; 3723 int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx, 3724 lsm6dso32_shub_pu_en_t val); 3725 int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx, 3726 lsm6dso32_shub_pu_en_t *val); 3727 3728 int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 3729 int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, 3730 uint8_t *val); 3731 3732 typedef enum 3733 { 3734 LSM6DSO32_EXT_ON_INT2_PIN = 1, 3735 LSM6DSO32_XL_GY_DRDY = 0, 3736 } lsm6dso32_start_config_t; 3737 int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx, 3738 lsm6dso32_start_config_t val); 3739 int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx, 3740 lsm6dso32_start_config_t *val); 3741 3742 typedef enum 3743 { 3744 LSM6DSO32_EACH_SH_CYCLE = 0, 3745 LSM6DSO32_ONLY_FIRST_CYCLE = 1, 3746 } lsm6dso32_write_once_t; 3747 int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx, 3748 lsm6dso32_write_once_t val); 3749 int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx, 3750 lsm6dso32_write_once_t *val); 3751 3752 int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx); 3753 int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 3754 3755 typedef enum 3756 { 3757 LSM6DSO32_SH_ODR_104Hz = 0, 3758 LSM6DSO32_SH_ODR_52Hz = 1, 3759 LSM6DSO32_SH_ODR_26Hz = 2, 3760 LSM6DSO32_SH_ODR_13Hz = 3, 3761 } lsm6dso32_shub_odr_t; 3762 int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx, 3763 lsm6dso32_shub_odr_t val); 3764 int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx, 3765 lsm6dso32_shub_odr_t *val); 3766 3767 typedef struct 3768 { 3769 uint8_t slv0_add; 3770 uint8_t slv0_subadd; 3771 uint8_t slv0_data; 3772 } lsm6dso32_sh_cfg_write_t; 3773 int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx, 3774 lsm6dso32_sh_cfg_write_t *val); 3775 3776 typedef struct 3777 { 3778 uint8_t slv_add; 3779 uint8_t slv_subadd; 3780 uint8_t slv_len; 3781 } lsm6dso32_sh_cfg_read_t; 3782 int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 3783 lsm6dso32_sh_cfg_read_t *val); 3784 int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 3785 lsm6dso32_sh_cfg_read_t *val); 3786 int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 3787 lsm6dso32_sh_cfg_read_t *val); 3788 int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 3789 lsm6dso32_sh_cfg_read_t *val); 3790 3791 int32_t lsm6dso32_sh_status_get(stmdev_ctx_t *ctx, 3792 lsm6dso32_status_master_t *val); 3793 3794 /** 3795 * @} 3796 * 3797 */ 3798 3799 #ifdef __cplusplus 3800 } 3801 #endif 3802 3803 #endif /*LSM6DSO32_DRIVER_H */ 3804 3805 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3806
