1 /** 2 ****************************************************************************** 3 * @file lsm6dsm_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsm_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSM_REGS_H 23 #define LSM6DSM_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSM 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 71 /** @defgroup STMicroelectronics sensors common types 72 * @{ 73 * 74 */ 75 76 #ifndef MEMS_SHARED_TYPES 77 #define MEMS_SHARED_TYPES 78 79 typedef struct 80 { 81 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 82 uint8_t bit0 : 1; 83 uint8_t bit1 : 1; 84 uint8_t bit2 : 1; 85 uint8_t bit3 : 1; 86 uint8_t bit4 : 1; 87 uint8_t bit5 : 1; 88 uint8_t bit6 : 1; 89 uint8_t bit7 : 1; 90 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 91 uint8_t bit7 : 1; 92 uint8_t bit6 : 1; 93 uint8_t bit5 : 1; 94 uint8_t bit4 : 1; 95 uint8_t bit3 : 1; 96 uint8_t bit2 : 1; 97 uint8_t bit1 : 1; 98 uint8_t bit0 : 1; 99 #endif /* DRV_BYTE_ORDER */ 100 } bitwise_t; 101 102 #define PROPERTY_DISABLE (0U) 103 #define PROPERTY_ENABLE (1U) 104 105 /** @addtogroup Interfaces_Functions 106 * @brief This section provide a set of functions used to read and 107 * write a generic register of the device. 108 * MANDATORY: return 0 -> no Error. 109 * @{ 110 * 111 */ 112 113 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 114 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 115 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 116 117 typedef struct 118 { 119 /** Component mandatory fields **/ 120 stmdev_write_ptr write_reg; 121 stmdev_read_ptr read_reg; 122 /** Component optional fields **/ 123 stmdev_mdelay_ptr mdelay; 124 /** Customizable optional pointer **/ 125 void *handle; 126 } stmdev_ctx_t; 127 128 /** 129 * @} 130 * 131 */ 132 133 #endif /* MEMS_SHARED_TYPES */ 134 135 #ifndef MEMS_UCF_SHARED_TYPES 136 #define MEMS_UCF_SHARED_TYPES 137 138 /** @defgroup Generic address-data structure definition 139 * @brief This structure is useful to load a predefined configuration 140 * of a sensor. 141 * You can create a sensor configuration by your own or using 142 * Unico / Unicleo tools available on STMicroelectronics 143 * web site. 144 * 145 * @{ 146 * 147 */ 148 149 typedef struct 150 { 151 uint8_t address; 152 uint8_t data; 153 } ucf_line_t; 154 155 /** 156 * @} 157 * 158 */ 159 160 #endif /* MEMS_UCF_SHARED_TYPES */ 161 162 /** 163 * @} 164 * 165 */ 166 167 /** @defgroup LSM6DSM_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 173 #define LSM6DSM_I2C_ADD_L 0xD5U 174 #define LSM6DSM_I2C_ADD_H 0xD7U 175 176 /** Device Identification (Who am I) **/ 177 #define LSM6DSM_ID 0x6AU 178 179 /** 180 * @} 181 * 182 */ 183 184 #define LSM6DSM_FUNC_CFG_ACCESS 0x01U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t not_used_01 : 5; 189 uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ 192 uint8_t not_used_01 : 5; 193 #endif /* DRV_BYTE_ORDER */ 194 } lsm6dsm_func_cfg_access_t; 195 196 #define LSM6DSM_SENSOR_SYNC_TIME_FRAME 0x04U 197 typedef struct 198 { 199 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 200 uint8_t tph : 4; 201 uint8_t not_used_01 : 4; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t not_used_01 : 4; 204 uint8_t tph : 4; 205 #endif /* DRV_BYTE_ORDER */ 206 } lsm6dsm_sensor_sync_time_frame_t; 207 208 #define LSM6DSM_SENSOR_SYNC_RES_RATIO 0x05U 209 typedef struct 210 { 211 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 212 uint8_t rr : 2; 213 uint8_t not_used_01 : 6; 214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 215 uint8_t not_used_01 : 6; 216 uint8_t rr : 2; 217 #endif /* DRV_BYTE_ORDER */ 218 } lsm6dsm_sensor_sync_res_ratio_t; 219 220 #define LSM6DSM_FIFO_CTRL1 0x06U 221 typedef struct 222 { 223 uint8_t fth : 8; /* + FIFO_CTRL2(fth) */ 224 } lsm6dsm_fifo_ctrl1_t; 225 226 #define LSM6DSM_FIFO_CTRL2 0x07U 227 typedef struct 228 { 229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 230 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 231 uint8_t fifo_temp_en : 1; 232 uint8_t not_used_01 : 2; 233 uint8_t timer_pedo_fifo_drdy : 1; 234 uint8_t timer_pedo_fifo_en : 1; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t timer_pedo_fifo_en : 1; 237 uint8_t timer_pedo_fifo_drdy : 1; 238 uint8_t not_used_01 : 2; 239 uint8_t fifo_temp_en : 1; 240 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 241 #endif /* DRV_BYTE_ORDER */ 242 } lsm6dsm_fifo_ctrl2_t; 243 244 #define LSM6DSM_FIFO_CTRL3 0x08U 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t dec_fifo_xl : 3; 249 uint8_t dec_fifo_gyro : 3; 250 uint8_t not_used_01 : 2; 251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 252 uint8_t not_used_01 : 2; 253 uint8_t dec_fifo_gyro : 3; 254 uint8_t dec_fifo_xl : 3; 255 #endif /* DRV_BYTE_ORDER */ 256 } lsm6dsm_fifo_ctrl3_t; 257 258 #define LSM6DSM_FIFO_CTRL4 0x09U 259 typedef struct 260 { 261 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 262 uint8_t dec_ds3_fifo : 3; 263 uint8_t dec_ds4_fifo : 3; 264 uint8_t only_high_data : 1; 265 uint8_t stop_on_fth : 1; 266 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 267 uint8_t stop_on_fth : 1; 268 uint8_t only_high_data : 1; 269 uint8_t dec_ds4_fifo : 3; 270 uint8_t dec_ds3_fifo : 3; 271 #endif /* DRV_BYTE_ORDER */ 272 } lsm6dsm_fifo_ctrl4_t; 273 274 #define LSM6DSM_FIFO_CTRL5 0x0AU 275 typedef struct 276 { 277 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 278 uint8_t fifo_mode : 3; 279 uint8_t odr_fifo : 4; 280 uint8_t not_used_01 : 1; 281 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 282 uint8_t not_used_01 : 1; 283 uint8_t odr_fifo : 4; 284 uint8_t fifo_mode : 3; 285 #endif /* DRV_BYTE_ORDER */ 286 } lsm6dsm_fifo_ctrl5_t; 287 288 #define LSM6DSM_DRDY_PULSE_CFG 0x0BU 289 typedef struct 290 { 291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 292 uint8_t int2_wrist_tilt : 1; 293 uint8_t not_used_01 : 6; 294 uint8_t drdy_pulsed : 1; 295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 296 uint8_t drdy_pulsed : 1; 297 uint8_t not_used_01 : 6; 298 uint8_t int2_wrist_tilt : 1; 299 #endif /* DRV_BYTE_ORDER */ 300 } lsm6dsm_drdy_pulse_cfg_t; 301 302 #define LSM6DSM_INT1_CTRL 0x0DU 303 typedef struct 304 { 305 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 306 uint8_t int1_drdy_xl : 1; 307 uint8_t int1_drdy_g : 1; 308 uint8_t int1_boot : 1; 309 uint8_t int1_fth : 1; 310 uint8_t int1_fifo_ovr : 1; 311 uint8_t int1_full_flag : 1; 312 uint8_t int1_sign_mot : 1; 313 uint8_t int1_step_detector : 1; 314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 315 uint8_t int1_step_detector : 1; 316 uint8_t int1_sign_mot : 1; 317 uint8_t int1_full_flag : 1; 318 uint8_t int1_fifo_ovr : 1; 319 uint8_t int1_fth : 1; 320 uint8_t int1_boot : 1; 321 uint8_t int1_drdy_g : 1; 322 uint8_t int1_drdy_xl : 1; 323 #endif /* DRV_BYTE_ORDER */ 324 } lsm6dsm_int1_ctrl_t; 325 326 #define LSM6DSM_INT2_CTRL 0x0EU 327 typedef struct 328 { 329 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 330 uint8_t int2_drdy_xl : 1; 331 uint8_t int2_drdy_g : 1; 332 uint8_t int2_drdy_temp : 1; 333 uint8_t int2_fth : 1; 334 uint8_t int2_fifo_ovr : 1; 335 uint8_t int2_full_flag : 1; 336 uint8_t int2_step_count_ov : 1; 337 uint8_t int2_step_delta : 1; 338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 339 uint8_t int2_step_delta : 1; 340 uint8_t int2_step_count_ov : 1; 341 uint8_t int2_full_flag : 1; 342 uint8_t int2_fifo_ovr : 1; 343 uint8_t int2_fth : 1; 344 uint8_t int2_drdy_temp : 1; 345 uint8_t int2_drdy_g : 1; 346 uint8_t int2_drdy_xl : 1; 347 #endif /* DRV_BYTE_ORDER */ 348 } lsm6dsm_int2_ctrl_t; 349 350 #define LSM6DSM_WHO_AM_I 0x0FU 351 #define LSM6DSM_CTRL1_XL 0x10U 352 typedef struct 353 { 354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 355 uint8_t bw0_xl : 1; 356 uint8_t lpf1_bw_sel : 1; 357 uint8_t fs_xl : 2; 358 uint8_t odr_xl : 4; 359 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 360 uint8_t odr_xl : 4; 361 uint8_t fs_xl : 2; 362 uint8_t lpf1_bw_sel : 1; 363 uint8_t bw0_xl : 1; 364 #endif /* DRV_BYTE_ORDER */ 365 } lsm6dsm_ctrl1_xl_t; 366 367 #define LSM6DSM_CTRL2_G 0x11U 368 typedef struct 369 { 370 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 371 uint8_t not_used_01 : 1; 372 uint8_t fs_g : 3; /* fs_g + fs_125 */ 373 uint8_t odr_g : 4; 374 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 375 uint8_t odr_g : 4; 376 uint8_t fs_g : 3; /* fs_g + fs_125 */ 377 uint8_t not_used_01 : 1; 378 #endif /* DRV_BYTE_ORDER */ 379 } lsm6dsm_ctrl2_g_t; 380 381 #define LSM6DSM_CTRL3_C 0x12U 382 typedef struct 383 { 384 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 385 uint8_t sw_reset : 1; 386 uint8_t ble : 1; 387 uint8_t if_inc : 1; 388 uint8_t sim : 1; 389 uint8_t pp_od : 1; 390 uint8_t h_lactive : 1; 391 uint8_t bdu : 1; 392 uint8_t boot : 1; 393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 394 uint8_t boot : 1; 395 uint8_t bdu : 1; 396 uint8_t h_lactive : 1; 397 uint8_t pp_od : 1; 398 uint8_t sim : 1; 399 uint8_t if_inc : 1; 400 uint8_t ble : 1; 401 uint8_t sw_reset : 1; 402 #endif /* DRV_BYTE_ORDER */ 403 } lsm6dsm_ctrl3_c_t; 404 405 #define LSM6DSM_CTRL4_C 0x13U 406 typedef struct 407 { 408 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 409 uint8_t not_used_01 : 1; 410 uint8_t lpf1_sel_g : 1; 411 uint8_t i2c_disable : 1; 412 uint8_t drdy_mask : 1; 413 uint8_t den_drdy_int1 : 1; 414 uint8_t int2_on_int1 : 1; 415 uint8_t sleep : 1; 416 uint8_t den_xl_en : 1; 417 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 418 uint8_t den_xl_en : 1; 419 uint8_t sleep : 1; 420 uint8_t int2_on_int1 : 1; 421 uint8_t den_drdy_int1 : 1; 422 uint8_t drdy_mask : 1; 423 uint8_t i2c_disable : 1; 424 uint8_t lpf1_sel_g : 1; 425 uint8_t not_used_01 : 1; 426 #endif /* DRV_BYTE_ORDER */ 427 } lsm6dsm_ctrl4_c_t; 428 429 #define LSM6DSM_CTRL5_C 0x14U 430 typedef struct 431 { 432 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 433 uint8_t st_xl : 2; 434 uint8_t st_g : 2; 435 uint8_t den_lh : 1; 436 uint8_t rounding : 3; 437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 438 uint8_t rounding : 3; 439 uint8_t den_lh : 1; 440 uint8_t st_g : 2; 441 uint8_t st_xl : 2; 442 #endif /* DRV_BYTE_ORDER */ 443 } lsm6dsm_ctrl5_c_t; 444 445 #define LSM6DSM_CTRL6_C 0x15U 446 typedef struct 447 { 448 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 449 uint8_t ftype : 2; 450 uint8_t not_used_01 : 1; 451 uint8_t usr_off_w : 1; 452 uint8_t xl_hm_mode : 1; 453 uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ 454 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 455 uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ 456 uint8_t xl_hm_mode : 1; 457 uint8_t usr_off_w : 1; 458 uint8_t not_used_01 : 1; 459 uint8_t ftype : 2; 460 #endif /* DRV_BYTE_ORDER */ 461 } lsm6dsm_ctrl6_c_t; 462 463 #define LSM6DSM_CTRL7_G 0x16U 464 typedef struct 465 { 466 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 467 uint8_t not_used_01 : 2; 468 uint8_t rounding_status : 1; 469 uint8_t not_used_02 : 1; 470 uint8_t hpm_g : 2; 471 uint8_t hp_en_g : 1; 472 uint8_t g_hm_mode : 1; 473 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 474 uint8_t g_hm_mode : 1; 475 uint8_t hp_en_g : 1; 476 uint8_t hpm_g : 2; 477 uint8_t not_used_02 : 1; 478 uint8_t rounding_status : 1; 479 uint8_t not_used_01 : 2; 480 #endif /* DRV_BYTE_ORDER */ 481 } lsm6dsm_ctrl7_g_t; 482 483 #define LSM6DSM_CTRL8_XL 0x17U 484 typedef struct 485 { 486 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 487 uint8_t low_pass_on_6d : 1; 488 uint8_t not_used_01 : 1; 489 uint8_t hp_slope_xl_en : 1; 490 uint8_t input_composite : 1; 491 uint8_t hp_ref_mode : 1; 492 uint8_t hpcf_xl : 2; 493 uint8_t lpf2_xl_en : 1; 494 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 495 uint8_t lpf2_xl_en : 1; 496 uint8_t hpcf_xl : 2; 497 uint8_t hp_ref_mode : 1; 498 uint8_t input_composite : 1; 499 uint8_t hp_slope_xl_en : 1; 500 uint8_t not_used_01 : 1; 501 uint8_t low_pass_on_6d : 1; 502 #endif /* DRV_BYTE_ORDER */ 503 } lsm6dsm_ctrl8_xl_t; 504 505 #define LSM6DSM_CTRL9_XL 0x18U 506 typedef struct 507 { 508 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 509 uint8_t not_used_01 : 2; 510 uint8_t soft_en : 1; 511 uint8_t not_used_02 : 1; 512 uint8_t den_xl_g : 1; 513 uint8_t den_z : 1; 514 uint8_t den_y : 1; 515 uint8_t den_x : 1; 516 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 517 uint8_t den_x : 1; 518 uint8_t den_y : 1; 519 uint8_t den_z : 1; 520 uint8_t den_xl_g : 1; 521 uint8_t not_used_02 : 1; 522 uint8_t soft_en : 1; 523 uint8_t not_used_01 : 2; 524 #endif /* DRV_BYTE_ORDER */ 525 } lsm6dsm_ctrl9_xl_t; 526 527 #define LSM6DSM_CTRL10_C 0x19U 528 typedef struct 529 { 530 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 531 uint8_t sign_motion_en : 1; 532 uint8_t pedo_rst_step : 1; 533 uint8_t func_en : 1; 534 uint8_t tilt_en : 1; 535 uint8_t pedo_en : 1; 536 uint8_t timer_en : 1; 537 uint8_t not_used_01 : 1; 538 uint8_t wrist_tilt_en : 1; 539 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 540 uint8_t wrist_tilt_en : 1; 541 uint8_t not_used_01 : 1; 542 uint8_t timer_en : 1; 543 uint8_t pedo_en : 1; 544 uint8_t tilt_en : 1; 545 uint8_t func_en : 1; 546 uint8_t pedo_rst_step : 1; 547 uint8_t sign_motion_en : 1; 548 #endif /* DRV_BYTE_ORDER */ 549 } lsm6dsm_ctrl10_c_t; 550 551 #define LSM6DSM_MASTER_CONFIG 0x1AU 552 typedef struct 553 { 554 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 555 uint8_t master_on : 1; 556 uint8_t iron_en : 1; 557 uint8_t pass_through_mode : 1; 558 uint8_t pull_up_en : 1; 559 uint8_t start_config : 1; 560 uint8_t not_used_01 : 1; 561 uint8_t data_valid_sel_fifo : 1; 562 uint8_t drdy_on_int1 : 1; 563 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 564 uint8_t drdy_on_int1 : 1; 565 uint8_t data_valid_sel_fifo : 1; 566 uint8_t not_used_01 : 1; 567 uint8_t start_config : 1; 568 uint8_t pull_up_en : 1; 569 uint8_t pass_through_mode : 1; 570 uint8_t iron_en : 1; 571 uint8_t master_on : 1; 572 #endif /* DRV_BYTE_ORDER */ 573 } lsm6dsm_master_config_t; 574 575 #define LSM6DSM_WAKE_UP_SRC 0x1BU 576 typedef struct 577 { 578 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 579 uint8_t z_wu : 1; 580 uint8_t y_wu : 1; 581 uint8_t x_wu : 1; 582 uint8_t wu_ia : 1; 583 uint8_t sleep_state_ia : 1; 584 uint8_t ff_ia : 1; 585 uint8_t not_used_01 : 2; 586 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 587 uint8_t not_used_01 : 2; 588 uint8_t ff_ia : 1; 589 uint8_t sleep_state_ia : 1; 590 uint8_t wu_ia : 1; 591 uint8_t x_wu : 1; 592 uint8_t y_wu : 1; 593 uint8_t z_wu : 1; 594 #endif /* DRV_BYTE_ORDER */ 595 } lsm6dsm_wake_up_src_t; 596 597 #define LSM6DSM_TAP_SRC 0x1CU 598 typedef struct 599 { 600 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 601 uint8_t z_tap : 1; 602 uint8_t y_tap : 1; 603 uint8_t x_tap : 1; 604 uint8_t tap_sign : 1; 605 uint8_t double_tap : 1; 606 uint8_t single_tap : 1; 607 uint8_t tap_ia : 1; 608 uint8_t not_used_01 : 1; 609 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 610 uint8_t not_used_01 : 1; 611 uint8_t tap_ia : 1; 612 uint8_t single_tap : 1; 613 uint8_t double_tap : 1; 614 uint8_t tap_sign : 1; 615 uint8_t x_tap : 1; 616 uint8_t y_tap : 1; 617 uint8_t z_tap : 1; 618 #endif /* DRV_BYTE_ORDER */ 619 } lsm6dsm_tap_src_t; 620 621 #define LSM6DSM_D6D_SRC 0x1DU 622 typedef struct 623 { 624 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 625 uint8_t xl : 1; 626 uint8_t xh : 1; 627 uint8_t yl : 1; 628 uint8_t yh : 1; 629 uint8_t zl : 1; 630 uint8_t zh : 1; 631 uint8_t d6d_ia : 1; 632 uint8_t den_drdy : 1; 633 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 634 uint8_t den_drdy : 1; 635 uint8_t d6d_ia : 1; 636 uint8_t zh : 1; 637 uint8_t zl : 1; 638 uint8_t yh : 1; 639 uint8_t yl : 1; 640 uint8_t xh : 1; 641 uint8_t xl : 1; 642 #endif /* DRV_BYTE_ORDER */ 643 } lsm6dsm_d6d_src_t; 644 645 #define LSM6DSM_STATUS_REG 0x1EU 646 typedef struct 647 { 648 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 649 uint8_t xlda : 1; 650 uint8_t gda : 1; 651 uint8_t tda : 1; 652 uint8_t not_used_01 : 5; 653 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 654 uint8_t not_used_01 : 5; 655 uint8_t tda : 1; 656 uint8_t gda : 1; 657 uint8_t xlda : 1; 658 #endif /* DRV_BYTE_ORDER */ 659 } lsm6dsm_status_reg_t; 660 661 #define LSM6DSM_STATUS_SPIAUX 0x1EU 662 typedef struct 663 { 664 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 665 uint8_t xlda : 1; 666 uint8_t gda : 1; 667 uint8_t gyro_settling : 1; 668 uint8_t not_used_01 : 5; 669 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 670 uint8_t not_used_01 : 5; 671 uint8_t gyro_settling : 1; 672 uint8_t gda : 1; 673 uint8_t xlda : 1; 674 #endif /* DRV_BYTE_ORDER */ 675 } lsm6dsm_status_spiaux_t; 676 677 #define LSM6DSM_OUT_TEMP_L 0x20U 678 #define LSM6DSM_OUT_TEMP_H 0x21U 679 #define LSM6DSM_OUTX_L_G 0x22U 680 #define LSM6DSM_OUTX_H_G 0x23U 681 #define LSM6DSM_OUTY_L_G 0x24U 682 #define LSM6DSM_OUTY_H_G 0x25U 683 #define LSM6DSM_OUTZ_L_G 0x26U 684 #define LSM6DSM_OUTZ_H_G 0x27U 685 #define LSM6DSM_OUTX_L_XL 0x28U 686 #define LSM6DSM_OUTX_H_XL 0x29U 687 #define LSM6DSM_OUTY_L_XL 0x2AU 688 #define LSM6DSM_OUTY_H_XL 0x2BU 689 #define LSM6DSM_OUTZ_L_XL 0x2CU 690 #define LSM6DSM_OUTZ_H_XL 0x2DU 691 #define LSM6DSM_SENSORHUB1_REG 0x2EU 692 typedef struct 693 { 694 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 695 uint8_t bit0 : 1; 696 uint8_t bit1 : 1; 697 uint8_t bit2 : 1; 698 uint8_t bit3 : 1; 699 uint8_t bit4 : 1; 700 uint8_t bit5 : 1; 701 uint8_t bit6 : 1; 702 uint8_t bit7 : 1; 703 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 704 uint8_t bit7 : 1; 705 uint8_t bit6 : 1; 706 uint8_t bit5 : 1; 707 uint8_t bit4 : 1; 708 uint8_t bit3 : 1; 709 uint8_t bit2 : 1; 710 uint8_t bit1 : 1; 711 uint8_t bit0 : 1; 712 #endif /* DRV_BYTE_ORDER */ 713 } lsm6dsm_sensorhub1_reg_t; 714 715 #define LSM6DSM_SENSORHUB2_REG 0x2FU 716 typedef struct 717 { 718 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 719 uint8_t bit0 : 1; 720 uint8_t bit1 : 1; 721 uint8_t bit2 : 1; 722 uint8_t bit3 : 1; 723 uint8_t bit4 : 1; 724 uint8_t bit5 : 1; 725 uint8_t bit6 : 1; 726 uint8_t bit7 : 1; 727 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 728 uint8_t bit7 : 1; 729 uint8_t bit6 : 1; 730 uint8_t bit5 : 1; 731 uint8_t bit4 : 1; 732 uint8_t bit3 : 1; 733 uint8_t bit2 : 1; 734 uint8_t bit1 : 1; 735 uint8_t bit0 : 1; 736 #endif /* DRV_BYTE_ORDER */ 737 } lsm6dsm_sensorhub2_reg_t; 738 739 #define LSM6DSM_SENSORHUB3_REG 0x30U 740 typedef struct 741 { 742 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 743 uint8_t bit0 : 1; 744 uint8_t bit1 : 1; 745 uint8_t bit2 : 1; 746 uint8_t bit3 : 1; 747 uint8_t bit4 : 1; 748 uint8_t bit5 : 1; 749 uint8_t bit6 : 1; 750 uint8_t bit7 : 1; 751 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 752 uint8_t bit7 : 1; 753 uint8_t bit6 : 1; 754 uint8_t bit5 : 1; 755 uint8_t bit4 : 1; 756 uint8_t bit3 : 1; 757 uint8_t bit2 : 1; 758 uint8_t bit1 : 1; 759 uint8_t bit0 : 1; 760 #endif /* DRV_BYTE_ORDER */ 761 } lsm6dsm_sensorhub3_reg_t; 762 763 #define LSM6DSM_SENSORHUB4_REG 0x31U 764 typedef struct 765 { 766 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 767 uint8_t bit0 : 1; 768 uint8_t bit1 : 1; 769 uint8_t bit2 : 1; 770 uint8_t bit3 : 1; 771 uint8_t bit4 : 1; 772 uint8_t bit5 : 1; 773 uint8_t bit6 : 1; 774 uint8_t bit7 : 1; 775 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 776 uint8_t bit7 : 1; 777 uint8_t bit6 : 1; 778 uint8_t bit5 : 1; 779 uint8_t bit4 : 1; 780 uint8_t bit3 : 1; 781 uint8_t bit2 : 1; 782 uint8_t bit1 : 1; 783 uint8_t bit0 : 1; 784 #endif /* DRV_BYTE_ORDER */ 785 } lsm6dsm_sensorhub4_reg_t; 786 787 #define LSM6DSM_SENSORHUB5_REG 0x32U 788 typedef struct 789 { 790 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 791 uint8_t bit0 : 1; 792 uint8_t bit1 : 1; 793 uint8_t bit2 : 1; 794 uint8_t bit3 : 1; 795 uint8_t bit4 : 1; 796 uint8_t bit5 : 1; 797 uint8_t bit6 : 1; 798 uint8_t bit7 : 1; 799 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 800 uint8_t bit7 : 1; 801 uint8_t bit6 : 1; 802 uint8_t bit5 : 1; 803 uint8_t bit4 : 1; 804 uint8_t bit3 : 1; 805 uint8_t bit2 : 1; 806 uint8_t bit1 : 1; 807 uint8_t bit0 : 1; 808 #endif /* DRV_BYTE_ORDER */ 809 } lsm6dsm_sensorhub5_reg_t; 810 811 #define LSM6DSM_SENSORHUB6_REG 0x33U 812 typedef struct 813 { 814 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 815 uint8_t bit0 : 1; 816 uint8_t bit1 : 1; 817 uint8_t bit2 : 1; 818 uint8_t bit3 : 1; 819 uint8_t bit4 : 1; 820 uint8_t bit5 : 1; 821 uint8_t bit6 : 1; 822 uint8_t bit7 : 1; 823 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 824 uint8_t bit7 : 1; 825 uint8_t bit6 : 1; 826 uint8_t bit5 : 1; 827 uint8_t bit4 : 1; 828 uint8_t bit3 : 1; 829 uint8_t bit2 : 1; 830 uint8_t bit1 : 1; 831 uint8_t bit0 : 1; 832 #endif /* DRV_BYTE_ORDER */ 833 } lsm6dsm_sensorhub6_reg_t; 834 835 #define LSM6DSM_SENSORHUB7_REG 0x34U 836 typedef struct 837 { 838 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 839 uint8_t bit0 : 1; 840 uint8_t bit1 : 1; 841 uint8_t bit2 : 1; 842 uint8_t bit3 : 1; 843 uint8_t bit4 : 1; 844 uint8_t bit5 : 1; 845 uint8_t bit6 : 1; 846 uint8_t bit7 : 1; 847 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 848 uint8_t bit7 : 1; 849 uint8_t bit6 : 1; 850 uint8_t bit5 : 1; 851 uint8_t bit4 : 1; 852 uint8_t bit3 : 1; 853 uint8_t bit2 : 1; 854 uint8_t bit1 : 1; 855 uint8_t bit0 : 1; 856 #endif /* DRV_BYTE_ORDER */ 857 } lsm6dsm_sensorhub7_reg_t; 858 859 #define LSM6DSM_SENSORHUB8_REG 0x35U 860 typedef struct 861 { 862 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 863 uint8_t bit0 : 1; 864 uint8_t bit1 : 1; 865 uint8_t bit2 : 1; 866 uint8_t bit3 : 1; 867 uint8_t bit4 : 1; 868 uint8_t bit5 : 1; 869 uint8_t bit6 : 1; 870 uint8_t bit7 : 1; 871 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 872 uint8_t bit7 : 1; 873 uint8_t bit6 : 1; 874 uint8_t bit5 : 1; 875 uint8_t bit4 : 1; 876 uint8_t bit3 : 1; 877 uint8_t bit2 : 1; 878 uint8_t bit1 : 1; 879 uint8_t bit0 : 1; 880 #endif /* DRV_BYTE_ORDER */ 881 } lsm6dsm_sensorhub8_reg_t; 882 883 #define LSM6DSM_SENSORHUB9_REG 0x36U 884 typedef struct 885 { 886 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 887 uint8_t bit0 : 1; 888 uint8_t bit1 : 1; 889 uint8_t bit2 : 1; 890 uint8_t bit3 : 1; 891 uint8_t bit4 : 1; 892 uint8_t bit5 : 1; 893 uint8_t bit6 : 1; 894 uint8_t bit7 : 1; 895 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 896 uint8_t bit7 : 1; 897 uint8_t bit6 : 1; 898 uint8_t bit5 : 1; 899 uint8_t bit4 : 1; 900 uint8_t bit3 : 1; 901 uint8_t bit2 : 1; 902 uint8_t bit1 : 1; 903 uint8_t bit0 : 1; 904 #endif /* DRV_BYTE_ORDER */ 905 } lsm6dsm_sensorhub9_reg_t; 906 907 #define LSM6DSM_SENSORHUB10_REG 0x37U 908 typedef struct 909 { 910 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 911 uint8_t bit0 : 1; 912 uint8_t bit1 : 1; 913 uint8_t bit2 : 1; 914 uint8_t bit3 : 1; 915 uint8_t bit4 : 1; 916 uint8_t bit5 : 1; 917 uint8_t bit6 : 1; 918 uint8_t bit7 : 1; 919 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 920 uint8_t bit7 : 1; 921 uint8_t bit6 : 1; 922 uint8_t bit5 : 1; 923 uint8_t bit4 : 1; 924 uint8_t bit3 : 1; 925 uint8_t bit2 : 1; 926 uint8_t bit1 : 1; 927 uint8_t bit0 : 1; 928 #endif /* DRV_BYTE_ORDER */ 929 } lsm6dsm_sensorhub10_reg_t; 930 931 #define LSM6DSM_SENSORHUB11_REG 0x38U 932 typedef struct 933 { 934 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 935 uint8_t bit0 : 1; 936 uint8_t bit1 : 1; 937 uint8_t bit2 : 1; 938 uint8_t bit3 : 1; 939 uint8_t bit4 : 1; 940 uint8_t bit5 : 1; 941 uint8_t bit6 : 1; 942 uint8_t bit7 : 1; 943 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 944 uint8_t bit7 : 1; 945 uint8_t bit6 : 1; 946 uint8_t bit5 : 1; 947 uint8_t bit4 : 1; 948 uint8_t bit3 : 1; 949 uint8_t bit2 : 1; 950 uint8_t bit1 : 1; 951 uint8_t bit0 : 1; 952 #endif /* DRV_BYTE_ORDER */ 953 } lsm6dsm_sensorhub11_reg_t; 954 955 #define LSM6DSM_SENSORHUB12_REG 0x39U 956 typedef struct 957 { 958 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 959 uint8_t bit0 : 1; 960 uint8_t bit1 : 1; 961 uint8_t bit2 : 1; 962 uint8_t bit3 : 1; 963 uint8_t bit4 : 1; 964 uint8_t bit5 : 1; 965 uint8_t bit6 : 1; 966 uint8_t bit7 : 1; 967 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 968 uint8_t bit7 : 1; 969 uint8_t bit6 : 1; 970 uint8_t bit5 : 1; 971 uint8_t bit4 : 1; 972 uint8_t bit3 : 1; 973 uint8_t bit2 : 1; 974 uint8_t bit1 : 1; 975 uint8_t bit0 : 1; 976 #endif /* DRV_BYTE_ORDER */ 977 } lsm6dsm_sensorhub12_reg_t; 978 979 #define LSM6DSM_FIFO_STATUS1 0x3AU 980 typedef struct 981 { 982 uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */ 983 } lsm6dsm_fifo_status1_t; 984 985 #define LSM6DSM_FIFO_STATUS2 0x3BU 986 typedef struct 987 { 988 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 989 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 990 uint8_t not_used_01 : 1; 991 uint8_t fifo_empty : 1; 992 uint8_t fifo_full_smart : 1; 993 uint8_t over_run : 1; 994 uint8_t waterm : 1; 995 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 996 uint8_t waterm : 1; 997 uint8_t over_run : 1; 998 uint8_t fifo_full_smart : 1; 999 uint8_t fifo_empty : 1; 1000 uint8_t not_used_01 : 1; 1001 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 1002 #endif /* DRV_BYTE_ORDER */ 1003 } lsm6dsm_fifo_status2_t; 1004 1005 #define LSM6DSM_FIFO_STATUS3 0x3CU 1006 typedef struct 1007 { 1008 uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ 1009 } lsm6dsm_fifo_status3_t; 1010 1011 #define LSM6DSM_FIFO_STATUS4 0x3DU 1012 typedef struct 1013 { 1014 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1015 uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ 1016 uint8_t not_used_01 : 6; 1017 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1018 uint8_t not_used_01 : 6; 1019 uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ 1020 #endif /* DRV_BYTE_ORDER */ 1021 } lsm6dsm_fifo_status4_t; 1022 1023 #define LSM6DSM_FIFO_DATA_OUT_L 0x3EU 1024 #define LSM6DSM_FIFO_DATA_OUT_H 0x3FU 1025 #define LSM6DSM_TIMESTAMP0_REG 0x40U 1026 #define LSM6DSM_TIMESTAMP1_REG 0x41U 1027 #define LSM6DSM_TIMESTAMP2_REG 0x42U 1028 #define LSM6DSM_STEP_TIMESTAMP_L 0x49U 1029 #define LSM6DSM_STEP_TIMESTAMP_H 0x4AU 1030 #define LSM6DSM_STEP_COUNTER_L 0x4BU 1031 #define LSM6DSM_STEP_COUNTER_H 0x4CU 1032 1033 #define LSM6DSM_SENSORHUB13_REG 0x4DU 1034 typedef struct 1035 { 1036 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1037 uint8_t bit0 : 1; 1038 uint8_t bit1 : 1; 1039 uint8_t bit2 : 1; 1040 uint8_t bit3 : 1; 1041 uint8_t bit4 : 1; 1042 uint8_t bit5 : 1; 1043 uint8_t bit6 : 1; 1044 uint8_t bit7 : 1; 1045 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1046 uint8_t bit7 : 1; 1047 uint8_t bit6 : 1; 1048 uint8_t bit5 : 1; 1049 uint8_t bit4 : 1; 1050 uint8_t bit3 : 1; 1051 uint8_t bit2 : 1; 1052 uint8_t bit1 : 1; 1053 uint8_t bit0 : 1; 1054 #endif /* DRV_BYTE_ORDER */ 1055 } lsm6dsm_sensorhub13_reg_t; 1056 1057 #define LSM6DSM_SENSORHUB14_REG 0x4EU 1058 typedef struct 1059 { 1060 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1061 uint8_t bit0 : 1; 1062 uint8_t bit1 : 1; 1063 uint8_t bit2 : 1; 1064 uint8_t bit3 : 1; 1065 uint8_t bit4 : 1; 1066 uint8_t bit5 : 1; 1067 uint8_t bit6 : 1; 1068 uint8_t bit7 : 1; 1069 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1070 uint8_t bit7 : 1; 1071 uint8_t bit6 : 1; 1072 uint8_t bit5 : 1; 1073 uint8_t bit4 : 1; 1074 uint8_t bit3 : 1; 1075 uint8_t bit2 : 1; 1076 uint8_t bit1 : 1; 1077 uint8_t bit0 : 1; 1078 #endif /* DRV_BYTE_ORDER */ 1079 } lsm6dsm_sensorhub14_reg_t; 1080 1081 #define LSM6DSM_SENSORHUB15_REG 0x4FU 1082 typedef struct 1083 { 1084 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1085 uint8_t bit0 : 1; 1086 uint8_t bit1 : 1; 1087 uint8_t bit2 : 1; 1088 uint8_t bit3 : 1; 1089 uint8_t bit4 : 1; 1090 uint8_t bit5 : 1; 1091 uint8_t bit6 : 1; 1092 uint8_t bit7 : 1; 1093 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1094 uint8_t bit7 : 1; 1095 uint8_t bit6 : 1; 1096 uint8_t bit5 : 1; 1097 uint8_t bit4 : 1; 1098 uint8_t bit3 : 1; 1099 uint8_t bit2 : 1; 1100 uint8_t bit1 : 1; 1101 uint8_t bit0 : 1; 1102 #endif /* DRV_BYTE_ORDER */ 1103 } lsm6dsm_sensorhub15_reg_t; 1104 1105 #define LSM6DSM_SENSORHUB16_REG 0x50U 1106 typedef struct 1107 { 1108 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1109 uint8_t bit0 : 1; 1110 uint8_t bit1 : 1; 1111 uint8_t bit2 : 1; 1112 uint8_t bit3 : 1; 1113 uint8_t bit4 : 1; 1114 uint8_t bit5 : 1; 1115 uint8_t bit6 : 1; 1116 uint8_t bit7 : 1; 1117 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1118 uint8_t bit7 : 1; 1119 uint8_t bit6 : 1; 1120 uint8_t bit5 : 1; 1121 uint8_t bit4 : 1; 1122 uint8_t bit3 : 1; 1123 uint8_t bit2 : 1; 1124 uint8_t bit1 : 1; 1125 uint8_t bit0 : 1; 1126 #endif /* DRV_BYTE_ORDER */ 1127 } lsm6dsm_sensorhub16_reg_t; 1128 1129 #define LSM6DSM_SENSORHUB17_REG 0x51U 1130 typedef struct 1131 { 1132 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1133 uint8_t bit0 : 1; 1134 uint8_t bit1 : 1; 1135 uint8_t bit2 : 1; 1136 uint8_t bit3 : 1; 1137 uint8_t bit4 : 1; 1138 uint8_t bit5 : 1; 1139 uint8_t bit6 : 1; 1140 uint8_t bit7 : 1; 1141 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1142 uint8_t bit7 : 1; 1143 uint8_t bit6 : 1; 1144 uint8_t bit5 : 1; 1145 uint8_t bit4 : 1; 1146 uint8_t bit3 : 1; 1147 uint8_t bit2 : 1; 1148 uint8_t bit1 : 1; 1149 uint8_t bit0 : 1; 1150 #endif /* DRV_BYTE_ORDER */ 1151 } lsm6dsm_sensorhub17_reg_t; 1152 1153 #define LSM6DSM_SENSORHUB18_REG 0x52U 1154 typedef struct 1155 { 1156 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1157 uint8_t bit0 : 1; 1158 uint8_t bit1 : 1; 1159 uint8_t bit2 : 1; 1160 uint8_t bit3 : 1; 1161 uint8_t bit4 : 1; 1162 uint8_t bit5 : 1; 1163 uint8_t bit6 : 1; 1164 uint8_t bit7 : 1; 1165 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1166 uint8_t bit7 : 1; 1167 uint8_t bit6 : 1; 1168 uint8_t bit5 : 1; 1169 uint8_t bit4 : 1; 1170 uint8_t bit3 : 1; 1171 uint8_t bit2 : 1; 1172 uint8_t bit1 : 1; 1173 uint8_t bit0 : 1; 1174 #endif /* DRV_BYTE_ORDER */ 1175 } lsm6dsm_sensorhub18_reg_t; 1176 1177 #define LSM6DSM_FUNC_SRC1 0x53U 1178 typedef struct 1179 { 1180 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1181 uint8_t sensorhub_end_op : 1; 1182 uint8_t si_end_op : 1; 1183 uint8_t hi_fail : 1; 1184 uint8_t step_overflow : 1; 1185 uint8_t step_detected : 1; 1186 uint8_t tilt_ia : 1; 1187 uint8_t sign_motion_ia : 1; 1188 uint8_t step_count_delta_ia : 1; 1189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1190 uint8_t step_count_delta_ia : 1; 1191 uint8_t sign_motion_ia : 1; 1192 uint8_t tilt_ia : 1; 1193 uint8_t step_detected : 1; 1194 uint8_t step_overflow : 1; 1195 uint8_t hi_fail : 1; 1196 uint8_t si_end_op : 1; 1197 uint8_t sensorhub_end_op : 1; 1198 #endif /* DRV_BYTE_ORDER */ 1199 } lsm6dsm_func_src1_t; 1200 1201 #define LSM6DSM_FUNC_SRC2 0x54U 1202 typedef struct 1203 { 1204 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1205 uint8_t wrist_tilt_ia : 1; 1206 uint8_t not_used_01 : 2; 1207 uint8_t slave0_nack : 1; 1208 uint8_t slave1_nack : 1; 1209 uint8_t slave2_nack : 1; 1210 uint8_t slave3_nack : 1; 1211 uint8_t not_used_02 : 1; 1212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1213 uint8_t not_used_02 : 1; 1214 uint8_t slave3_nack : 1; 1215 uint8_t slave2_nack : 1; 1216 uint8_t slave1_nack : 1; 1217 uint8_t slave0_nack : 1; 1218 uint8_t not_used_01 : 2; 1219 uint8_t wrist_tilt_ia : 1; 1220 #endif /* DRV_BYTE_ORDER */ 1221 } lsm6dsm_func_src2_t; 1222 1223 #define LSM6DSM_WRIST_TILT_IA 0x55U 1224 typedef struct 1225 { 1226 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1227 uint8_t not_used_01 : 2; 1228 uint8_t wrist_tilt_ia_zneg : 1; 1229 uint8_t wrist_tilt_ia_zpos : 1; 1230 uint8_t wrist_tilt_ia_yneg : 1; 1231 uint8_t wrist_tilt_ia_ypos : 1; 1232 uint8_t wrist_tilt_ia_xneg : 1; 1233 uint8_t wrist_tilt_ia_xpos : 1; 1234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1235 uint8_t wrist_tilt_ia_xpos : 1; 1236 uint8_t wrist_tilt_ia_xneg : 1; 1237 uint8_t wrist_tilt_ia_ypos : 1; 1238 uint8_t wrist_tilt_ia_yneg : 1; 1239 uint8_t wrist_tilt_ia_zpos : 1; 1240 uint8_t wrist_tilt_ia_zneg : 1; 1241 uint8_t not_used_01 : 2; 1242 #endif /* DRV_BYTE_ORDER */ 1243 } lsm6dsm_wrist_tilt_ia_t; 1244 1245 #define LSM6DSM_TAP_CFG 0x58U 1246 typedef struct 1247 { 1248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1249 uint8_t lir : 1; 1250 uint8_t tap_z_en : 1; 1251 uint8_t tap_y_en : 1; 1252 uint8_t tap_x_en : 1; 1253 uint8_t slope_fds : 1; 1254 uint8_t inact_en : 2; 1255 uint8_t interrupts_enable : 1; 1256 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1257 uint8_t interrupts_enable : 1; 1258 uint8_t inact_en : 2; 1259 uint8_t slope_fds : 1; 1260 uint8_t tap_x_en : 1; 1261 uint8_t tap_y_en : 1; 1262 uint8_t tap_z_en : 1; 1263 uint8_t lir : 1; 1264 #endif /* DRV_BYTE_ORDER */ 1265 } lsm6dsm_tap_cfg_t; 1266 1267 #define LSM6DSM_TAP_THS_6D 0x59U 1268 typedef struct 1269 { 1270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1271 uint8_t tap_ths : 5; 1272 uint8_t sixd_ths : 2; 1273 uint8_t d4d_en : 1; 1274 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1275 uint8_t d4d_en : 1; 1276 uint8_t sixd_ths : 2; 1277 uint8_t tap_ths : 5; 1278 #endif /* DRV_BYTE_ORDER */ 1279 } lsm6dsm_tap_ths_6d_t; 1280 1281 #define LSM6DSM_INT_DUR2 0x5AU 1282 typedef struct 1283 { 1284 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1285 uint8_t shock : 2; 1286 uint8_t quiet : 2; 1287 uint8_t dur : 4; 1288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1289 uint8_t dur : 4; 1290 uint8_t quiet : 2; 1291 uint8_t shock : 2; 1292 #endif /* DRV_BYTE_ORDER */ 1293 } lsm6dsm_int_dur2_t; 1294 1295 #define LSM6DSM_WAKE_UP_THS 0x5BU 1296 typedef struct 1297 { 1298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1299 uint8_t wk_ths : 6; 1300 uint8_t not_used_01 : 1; 1301 uint8_t single_double_tap : 1; 1302 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1303 uint8_t single_double_tap : 1; 1304 uint8_t not_used_01 : 1; 1305 uint8_t wk_ths : 6; 1306 #endif /* DRV_BYTE_ORDER */ 1307 } lsm6dsm_wake_up_ths_t; 1308 1309 #define LSM6DSM_WAKE_UP_DUR 0x5CU 1310 typedef struct 1311 { 1312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1313 uint8_t sleep_dur : 4; 1314 uint8_t timer_hr : 1; 1315 uint8_t wake_dur : 2; 1316 uint8_t ff_dur : 1; 1317 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1318 uint8_t ff_dur : 1; 1319 uint8_t wake_dur : 2; 1320 uint8_t timer_hr : 1; 1321 uint8_t sleep_dur : 4; 1322 #endif /* DRV_BYTE_ORDER */ 1323 } lsm6dsm_wake_up_dur_t; 1324 1325 #define LSM6DSM_FREE_FALL 0x5DU 1326 typedef struct 1327 { 1328 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1329 uint8_t ff_ths : 3; 1330 uint8_t ff_dur : 5; 1331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1332 uint8_t ff_dur : 5; 1333 uint8_t ff_ths : 3; 1334 #endif /* DRV_BYTE_ORDER */ 1335 } lsm6dsm_free_fall_t; 1336 1337 #define LSM6DSM_MD1_CFG 0x5EU 1338 typedef struct 1339 { 1340 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1341 uint8_t int1_timer : 1; 1342 uint8_t int1_tilt : 1; 1343 uint8_t int1_6d : 1; 1344 uint8_t int1_double_tap : 1; 1345 uint8_t int1_ff : 1; 1346 uint8_t int1_wu : 1; 1347 uint8_t int1_single_tap : 1; 1348 uint8_t int1_inact_state : 1; 1349 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1350 uint8_t int1_inact_state : 1; 1351 uint8_t int1_single_tap : 1; 1352 uint8_t int1_wu : 1; 1353 uint8_t int1_ff : 1; 1354 uint8_t int1_double_tap : 1; 1355 uint8_t int1_6d : 1; 1356 uint8_t int1_tilt : 1; 1357 uint8_t int1_timer : 1; 1358 #endif /* DRV_BYTE_ORDER */ 1359 } lsm6dsm_md1_cfg_t; 1360 1361 #define LSM6DSM_MD2_CFG 0x5FU 1362 typedef struct 1363 { 1364 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1365 uint8_t int2_iron : 1; 1366 uint8_t int2_tilt : 1; 1367 uint8_t int2_6d : 1; 1368 uint8_t int2_double_tap : 1; 1369 uint8_t int2_ff : 1; 1370 uint8_t int2_wu : 1; 1371 uint8_t int2_single_tap : 1; 1372 uint8_t int2_inact_state : 1; 1373 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1374 uint8_t int2_inact_state : 1; 1375 uint8_t int2_single_tap : 1; 1376 uint8_t int2_wu : 1; 1377 uint8_t int2_ff : 1; 1378 uint8_t int2_double_tap : 1; 1379 uint8_t int2_6d : 1; 1380 uint8_t int2_tilt : 1; 1381 uint8_t int2_iron : 1; 1382 #endif /* DRV_BYTE_ORDER */ 1383 } lsm6dsm_md2_cfg_t; 1384 1385 #define LSM6DSM_MASTER_CMD_CODE 0x60U 1386 typedef struct 1387 { 1388 uint8_t master_cmd_code : 8; 1389 } lsm6dsm_master_cmd_code_t; 1390 1391 #define LSM6DSM_SENS_SYNC_SPI_ERROR_CODE 0x61U 1392 typedef struct 1393 { 1394 uint8_t error_code : 8; 1395 } lsm6dsm_sens_sync_spi_error_code_t; 1396 1397 #define LSM6DSM_OUT_MAG_RAW_X_L 0x66U 1398 #define LSM6DSM_OUT_MAG_RAW_X_H 0x67U 1399 #define LSM6DSM_OUT_MAG_RAW_Y_L 0x68U 1400 #define LSM6DSM_OUT_MAG_RAW_Y_H 0x69U 1401 #define LSM6DSM_OUT_MAG_RAW_Z_L 0x6AU 1402 #define LSM6DSM_OUT_MAG_RAW_Z_H 0x6BU 1403 #define LSM6DSM_INT_OIS 0x6FU 1404 typedef struct 1405 { 1406 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1407 uint8_t not_used_01 : 6; 1408 uint8_t lvl2_ois : 1; 1409 uint8_t int2_drdy_ois : 1; 1410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1411 uint8_t int2_drdy_ois : 1; 1412 uint8_t lvl2_ois : 1; 1413 uint8_t not_used_01 : 6; 1414 #endif /* DRV_BYTE_ORDER */ 1415 } lsm6dsm_int_ois_t; 1416 1417 #define LSM6DSM_CTRL1_OIS 0x70U 1418 typedef struct 1419 { 1420 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1421 uint8_t ois_en_spi2 : 1; 1422 uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */ 1423 uint8_t mode4_en : 1; 1424 uint8_t sim_ois : 1; 1425 uint8_t lvl1_ois : 1; 1426 uint8_t ble_ois : 1; 1427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1428 uint8_t ble_ois : 1; 1429 uint8_t lvl1_ois : 1; 1430 uint8_t sim_ois : 1; 1431 uint8_t mode4_en : 1; 1432 uint8_t fs_g_ois : 3; /* fs_g_ois + fs_125_ois */ 1433 uint8_t ois_en_spi2 : 1; 1434 #endif /* DRV_BYTE_ORDER */ 1435 } lsm6dsm_ctrl1_ois_t; 1436 1437 #define LSM6DSM_CTRL2_OIS 0x71U 1438 typedef struct 1439 { 1440 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1441 uint8_t hp_en_ois : 1; 1442 uint8_t ftype_ois : 2; 1443 uint8_t not_used_01 : 1; 1444 uint8_t hpm_ois : 2; 1445 uint8_t not_used_02 : 2; 1446 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1447 uint8_t not_used_02 : 2; 1448 uint8_t hpm_ois : 2; 1449 uint8_t not_used_01 : 1; 1450 uint8_t ftype_ois : 2; 1451 uint8_t hp_en_ois : 1; 1452 #endif /* DRV_BYTE_ORDER */ 1453 } lsm6dsm_ctrl2_ois_t; 1454 1455 #define LSM6DSM_CTRL3_OIS 0x72U 1456 typedef struct 1457 { 1458 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1459 uint8_t st_ois_clampdis : 1; 1460 uint8_t st_ois : 2; 1461 uint8_t filter_xl_conf_ois : 2; 1462 uint8_t fs_xl_ois : 2; 1463 uint8_t den_lh_ois : 1; 1464 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1465 uint8_t den_lh_ois : 1; 1466 uint8_t fs_xl_ois : 2; 1467 uint8_t filter_xl_conf_ois : 2; 1468 uint8_t st_ois : 2; 1469 uint8_t st_ois_clampdis : 1; 1470 #endif /* DRV_BYTE_ORDER */ 1471 } lsm6dsm_ctrl3_ois_t; 1472 1473 #define LSM6DSM_X_OFS_USR 0x73U 1474 #define LSM6DSM_Y_OFS_USR 0x74U 1475 #define LSM6DSM_Z_OFS_USR 0x75U 1476 #define LSM6DSM_SLV0_ADD 0x02U 1477 typedef struct 1478 { 1479 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1480 uint8_t rw_0 : 1; 1481 uint8_t slave0_add : 7; 1482 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1483 uint8_t slave0_add : 7; 1484 uint8_t rw_0 : 1; 1485 #endif /* DRV_BYTE_ORDER */ 1486 } lsm6dsm_slv0_add_t; 1487 1488 #define LSM6DSM_SLV0_SUBADD 0x03U 1489 typedef struct 1490 { 1491 uint8_t slave0_reg : 8; 1492 } lsm6dsm_slv0_subadd_t; 1493 1494 #define LSM6DSM_SLAVE0_CONFIG 0x04U 1495 typedef struct 1496 { 1497 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1498 uint8_t slave0_numop : 3; 1499 uint8_t src_mode : 1; 1500 uint8_t aux_sens_on : 2; 1501 uint8_t slave0_rate : 2; 1502 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1503 uint8_t slave0_rate : 2; 1504 uint8_t aux_sens_on : 2; 1505 uint8_t src_mode : 1; 1506 uint8_t slave0_numop : 3; 1507 #endif /* DRV_BYTE_ORDER */ 1508 } lsm6dsm_slave0_config_t; 1509 1510 #define LSM6DSM_SLV1_ADD 0x05U 1511 typedef struct 1512 { 1513 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1514 uint8_t r_1 : 1; 1515 uint8_t slave1_add : 7; 1516 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1517 uint8_t slave1_add : 7; 1518 uint8_t r_1 : 1; 1519 #endif /* DRV_BYTE_ORDER */ 1520 } lsm6dsm_slv1_add_t; 1521 1522 #define LSM6DSM_SLV1_SUBADD 0x06U 1523 typedef struct 1524 { 1525 uint8_t slave1_reg : 8; 1526 } lsm6dsm_slv1_subadd_t; 1527 1528 #define LSM6DSM_SLAVE1_CONFIG 0x07U 1529 typedef struct 1530 { 1531 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1532 uint8_t slave1_numop : 3; 1533 uint8_t not_used_01 : 2; 1534 uint8_t write_once : 1; 1535 uint8_t slave1_rate : 2; 1536 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1537 uint8_t slave1_rate : 2; 1538 uint8_t write_once : 1; 1539 uint8_t not_used_01 : 2; 1540 uint8_t slave1_numop : 3; 1541 #endif /* DRV_BYTE_ORDER */ 1542 } lsm6dsm_slave1_config_t; 1543 1544 #define LSM6DSM_SLV2_ADD 0x08U 1545 typedef struct 1546 { 1547 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1548 uint8_t r_2 : 1; 1549 uint8_t slave2_add : 7; 1550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1551 uint8_t slave2_add : 7; 1552 uint8_t r_2 : 1; 1553 #endif /* DRV_BYTE_ORDER */ 1554 } lsm6dsm_slv2_add_t; 1555 1556 #define LSM6DSM_SLV2_SUBADD 0x09U 1557 typedef struct 1558 { 1559 uint8_t slave2_reg : 8; 1560 } lsm6dsm_slv2_subadd_t; 1561 1562 #define LSM6DSM_SLAVE2_CONFIG 0x0AU 1563 typedef struct 1564 { 1565 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1566 uint8_t slave2_numop : 3; 1567 uint8_t not_used_01 : 3; 1568 uint8_t slave2_rate : 2; 1569 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1570 uint8_t slave2_rate : 2; 1571 uint8_t not_used_01 : 3; 1572 uint8_t slave2_numop : 3; 1573 #endif /* DRV_BYTE_ORDER */ 1574 } lsm6dsm_slave2_config_t; 1575 1576 #define LSM6DSM_SLV3_ADD 0x0BU 1577 typedef struct 1578 { 1579 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1580 uint8_t r_3 : 1; 1581 uint8_t slave3_add : 7; 1582 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1583 uint8_t slave3_add : 7; 1584 uint8_t r_3 : 1; 1585 #endif /* DRV_BYTE_ORDER */ 1586 } lsm6dsm_slv3_add_t; 1587 1588 #define LSM6DSM_SLV3_SUBADD 0x0CU 1589 typedef struct 1590 { 1591 uint8_t slave3_reg : 8; 1592 } lsm6dsm_slv3_subadd_t; 1593 1594 #define LSM6DSM_SLAVE3_CONFIG 0x0DU 1595 typedef struct 1596 { 1597 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1598 uint8_t slave3_numop : 3; 1599 uint8_t not_used_01 : 3; 1600 uint8_t slave3_rate : 2; 1601 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1602 uint8_t slave3_rate : 2; 1603 uint8_t not_used_01 : 3; 1604 uint8_t slave3_numop : 3; 1605 #endif /* DRV_BYTE_ORDER */ 1606 } lsm6dsm_slave3_config_t; 1607 1608 #define LSM6DSM_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU 1609 typedef struct 1610 { 1611 uint8_t slave_dataw : 8; 1612 } lsm6dsm_datawrite_src_mode_sub_slv0_t; 1613 1614 #define LSM6DSM_CONFIG_PEDO_THS_MIN 0x0FU 1615 typedef struct 1616 { 1617 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1618 uint8_t ths_min : 5; 1619 uint8_t not_used_01 : 2; 1620 uint8_t pedo_fs : 1; 1621 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1622 uint8_t pedo_fs : 1; 1623 uint8_t not_used_01 : 2; 1624 uint8_t ths_min : 5; 1625 #endif /* DRV_BYTE_ORDER */ 1626 } lsm6dsm_config_pedo_ths_min_t; 1627 1628 #define LSM6DSM_SM_THS 0x13U 1629 #define LSM6DSM_PEDO_DEB_REG 0x14U 1630 typedef struct 1631 { 1632 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1633 uint8_t deb_step : 3; 1634 uint8_t deb_time : 5; 1635 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1636 uint8_t deb_time : 5; 1637 uint8_t deb_step : 3; 1638 #endif /* DRV_BYTE_ORDER */ 1639 } lsm6dsm_pedo_deb_reg_t; 1640 1641 #define LSM6DSM_STEP_COUNT_DELTA 0x15U 1642 #define LSM6DSM_MAG_SI_XX 0x24U 1643 #define LSM6DSM_MAG_SI_XY 0x25U 1644 #define LSM6DSM_MAG_SI_XZ 0x26U 1645 #define LSM6DSM_MAG_SI_YX 0x27U 1646 #define LSM6DSM_MAG_SI_YY 0x28U 1647 #define LSM6DSM_MAG_SI_YZ 0x29U 1648 #define LSM6DSM_MAG_SI_ZX 0x2AU 1649 #define LSM6DSM_MAG_SI_ZY 0x2BU 1650 #define LSM6DSM_MAG_SI_ZZ 0x2CU 1651 #define LSM6DSM_MAG_OFFX_L 0x2DU 1652 #define LSM6DSM_MAG_OFFX_H 0x2EU 1653 #define LSM6DSM_MAG_OFFY_L 0x2FU 1654 #define LSM6DSM_MAG_OFFY_H 0x30U 1655 #define LSM6DSM_MAG_OFFZ_L 0x31U 1656 #define LSM6DSM_MAG_OFFZ_H 0x32U 1657 #define LSM6DSM_A_WRIST_TILT_LAT 0x50U 1658 #define LSM6DSM_A_WRIST_TILT_THS 0x54U 1659 #define LSM6DSM_A_WRIST_TILT_MASK 0x59U 1660 typedef struct 1661 { 1662 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1663 uint8_t not_used_01 : 2; 1664 uint8_t wrist_tilt_mask_zneg : 1; 1665 uint8_t wrist_tilt_mask_zpos : 1; 1666 uint8_t wrist_tilt_mask_yneg : 1; 1667 uint8_t wrist_tilt_mask_ypos : 1; 1668 uint8_t wrist_tilt_mask_xneg : 1; 1669 uint8_t wrist_tilt_mask_xpos : 1; 1670 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1671 uint8_t wrist_tilt_mask_xpos : 1; 1672 uint8_t wrist_tilt_mask_xneg : 1; 1673 uint8_t wrist_tilt_mask_ypos : 1; 1674 uint8_t wrist_tilt_mask_yneg : 1; 1675 uint8_t wrist_tilt_mask_zpos : 1; 1676 uint8_t wrist_tilt_mask_zneg : 1; 1677 uint8_t not_used_01 : 2; 1678 #endif /* DRV_BYTE_ORDER */ 1679 } lsm6dsm_a_wrist_tilt_mask_t; 1680 1681 /** 1682 * @defgroup LSM6DSM_Register_Union 1683 * @brief This union group all the registers having a bit-field 1684 * description. 1685 * This union is useful but it's not needed by the driver. 1686 * 1687 * REMOVING this union you are compliant with: 1688 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 1689 * 1690 * @{ 1691 * 1692 */ 1693 typedef union 1694 { 1695 lsm6dsm_func_cfg_access_t func_cfg_access; 1696 lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame; 1697 lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio; 1698 lsm6dsm_fifo_ctrl1_t fifo_ctrl1; 1699 lsm6dsm_fifo_ctrl2_t fifo_ctrl2; 1700 lsm6dsm_fifo_ctrl3_t fifo_ctrl3; 1701 lsm6dsm_fifo_ctrl4_t fifo_ctrl4; 1702 lsm6dsm_fifo_ctrl5_t fifo_ctrl5; 1703 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg; 1704 lsm6dsm_int1_ctrl_t int1_ctrl; 1705 lsm6dsm_int2_ctrl_t int2_ctrl; 1706 lsm6dsm_ctrl1_xl_t ctrl1_xl; 1707 lsm6dsm_ctrl2_g_t ctrl2_g; 1708 lsm6dsm_ctrl3_c_t ctrl3_c; 1709 lsm6dsm_ctrl4_c_t ctrl4_c; 1710 lsm6dsm_ctrl5_c_t ctrl5_c; 1711 lsm6dsm_ctrl6_c_t ctrl6_c; 1712 lsm6dsm_ctrl7_g_t ctrl7_g; 1713 lsm6dsm_ctrl8_xl_t ctrl8_xl; 1714 lsm6dsm_ctrl9_xl_t ctrl9_xl; 1715 lsm6dsm_ctrl10_c_t ctrl10_c; 1716 lsm6dsm_master_config_t master_config; 1717 lsm6dsm_wake_up_src_t wake_up_src; 1718 lsm6dsm_tap_src_t tap_src; 1719 lsm6dsm_d6d_src_t d6d_src; 1720 lsm6dsm_status_reg_t status_reg; 1721 lsm6dsm_status_spiaux_t status_spiaux; 1722 lsm6dsm_sensorhub1_reg_t sensorhub1_reg; 1723 lsm6dsm_sensorhub2_reg_t sensorhub2_reg; 1724 lsm6dsm_sensorhub3_reg_t sensorhub3_reg; 1725 lsm6dsm_sensorhub4_reg_t sensorhub4_reg; 1726 lsm6dsm_sensorhub5_reg_t sensorhub5_reg; 1727 lsm6dsm_sensorhub6_reg_t sensorhub6_reg; 1728 lsm6dsm_sensorhub7_reg_t sensorhub7_reg; 1729 lsm6dsm_sensorhub8_reg_t sensorhub8_reg; 1730 lsm6dsm_sensorhub9_reg_t sensorhub9_reg; 1731 lsm6dsm_sensorhub10_reg_t sensorhub10_reg; 1732 lsm6dsm_sensorhub11_reg_t sensorhub11_reg; 1733 lsm6dsm_sensorhub12_reg_t sensorhub12_reg; 1734 lsm6dsm_fifo_status1_t fifo_status1; 1735 lsm6dsm_fifo_status2_t fifo_status2; 1736 lsm6dsm_fifo_status3_t fifo_status3; 1737 lsm6dsm_fifo_status4_t fifo_status4; 1738 lsm6dsm_sensorhub13_reg_t sensorhub13_reg; 1739 lsm6dsm_sensorhub14_reg_t sensorhub14_reg; 1740 lsm6dsm_sensorhub15_reg_t sensorhub15_reg; 1741 lsm6dsm_sensorhub16_reg_t sensorhub16_reg; 1742 lsm6dsm_sensorhub17_reg_t sensorhub17_reg; 1743 lsm6dsm_sensorhub18_reg_t sensorhub18_reg; 1744 lsm6dsm_func_src1_t func_src1; 1745 lsm6dsm_func_src2_t func_src2; 1746 lsm6dsm_wrist_tilt_ia_t wrist_tilt_ia; 1747 lsm6dsm_tap_cfg_t tap_cfg; 1748 lsm6dsm_tap_ths_6d_t tap_ths_6d; 1749 lsm6dsm_int_dur2_t int_dur2; 1750 lsm6dsm_wake_up_ths_t wake_up_ths; 1751 lsm6dsm_wake_up_dur_t wake_up_dur; 1752 lsm6dsm_free_fall_t free_fall; 1753 lsm6dsm_md1_cfg_t md1_cfg; 1754 lsm6dsm_md2_cfg_t md2_cfg; 1755 lsm6dsm_master_cmd_code_t master_cmd_code; 1756 lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code; 1757 lsm6dsm_int_ois_t int_ois; 1758 lsm6dsm_ctrl1_ois_t ctrl1_ois; 1759 lsm6dsm_ctrl2_ois_t ctrl2_ois; 1760 lsm6dsm_ctrl3_ois_t ctrl3_ois; 1761 lsm6dsm_slv0_add_t slv0_add; 1762 lsm6dsm_slv0_subadd_t slv0_subadd; 1763 lsm6dsm_slave0_config_t slave0_config; 1764 lsm6dsm_slv1_add_t slv1_add; 1765 lsm6dsm_slv1_subadd_t slv1_subadd; 1766 lsm6dsm_slave1_config_t slave1_config; 1767 lsm6dsm_slv2_add_t slv2_add; 1768 lsm6dsm_slv2_subadd_t slv2_subadd; 1769 lsm6dsm_slave2_config_t slave2_config; 1770 lsm6dsm_slv3_add_t slv3_add; 1771 lsm6dsm_slv3_subadd_t slv3_subadd; 1772 lsm6dsm_slave3_config_t slave3_config; 1773 lsm6dsm_datawrite_src_mode_sub_slv0_t 1774 datawrite_src_mode_sub_slv0; 1775 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min; 1776 lsm6dsm_pedo_deb_reg_t pedo_deb_reg; 1777 lsm6dsm_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1778 bitwise_t bitwise; 1779 uint8_t byte; 1780 } lsm6dsm_reg_t; 1781 1782 /** 1783 * @} 1784 * 1785 */ 1786 1787 #ifndef __weak 1788 #define __weak __attribute__((weak)) 1789 #endif /* __weak */ 1790 1791 /* 1792 * These are the basic platform dependent I/O routines to read 1793 * and write device registers connected on a standard bus. 1794 * The driver keeps offering a default implementation based on function 1795 * pointers to read/write routines for backward compatibility. 1796 * The __weak directive allows the final application to overwrite 1797 * them with a custom implementation. 1798 */ 1799 1800 int32_t lsm6dsm_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1801 uint8_t *data, 1802 uint16_t len); 1803 int32_t lsm6dsm_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1804 uint8_t *data, 1805 uint16_t len); 1806 1807 float_t lsm6dsm_from_fs2g_to_mg(int16_t lsb); 1808 float_t lsm6dsm_from_fs4g_to_mg(int16_t lsb); 1809 float_t lsm6dsm_from_fs8g_to_mg(int16_t lsb); 1810 float_t lsm6dsm_from_fs16g_to_mg(int16_t lsb); 1811 1812 float_t lsm6dsm_from_fs125dps_to_mdps(int16_t lsb); 1813 float_t lsm6dsm_from_fs250dps_to_mdps(int16_t lsb); 1814 float_t lsm6dsm_from_fs500dps_to_mdps(int16_t lsb); 1815 float_t lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb); 1816 float_t lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb); 1817 1818 float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb); 1819 1820 typedef enum 1821 { 1822 LSM6DSM_2g = 0, 1823 LSM6DSM_16g = 1, 1824 LSM6DSM_4g = 2, 1825 LSM6DSM_8g = 3, 1826 } lsm6dsm_fs_xl_t; 1827 int32_t lsm6dsm_xl_full_scale_set(const stmdev_ctx_t *ctx, 1828 lsm6dsm_fs_xl_t val); 1829 int32_t lsm6dsm_xl_full_scale_get(const stmdev_ctx_t *ctx, 1830 lsm6dsm_fs_xl_t *val); 1831 1832 typedef enum 1833 { 1834 LSM6DSM_XL_ODR_OFF = 0, 1835 LSM6DSM_XL_ODR_12Hz5 = 1, 1836 LSM6DSM_XL_ODR_26Hz = 2, 1837 LSM6DSM_XL_ODR_52Hz = 3, 1838 LSM6DSM_XL_ODR_104Hz = 4, 1839 LSM6DSM_XL_ODR_208Hz = 5, 1840 LSM6DSM_XL_ODR_416Hz = 6, 1841 LSM6DSM_XL_ODR_833Hz = 7, 1842 LSM6DSM_XL_ODR_1k66Hz = 8, 1843 LSM6DSM_XL_ODR_3k33Hz = 9, 1844 LSM6DSM_XL_ODR_6k66Hz = 10, 1845 LSM6DSM_XL_ODR_1Hz6 = 11, 1846 } lsm6dsm_odr_xl_t; 1847 int32_t lsm6dsm_xl_data_rate_set(const stmdev_ctx_t *ctx, 1848 lsm6dsm_odr_xl_t val); 1849 int32_t lsm6dsm_xl_data_rate_get(const stmdev_ctx_t *ctx, 1850 lsm6dsm_odr_xl_t *val); 1851 1852 typedef enum 1853 { 1854 LSM6DSM_250dps = 0, 1855 LSM6DSM_125dps = 1, 1856 LSM6DSM_500dps = 2, 1857 LSM6DSM_1000dps = 4, 1858 LSM6DSM_2000dps = 6, 1859 } lsm6dsm_fs_g_t; 1860 int32_t lsm6dsm_gy_full_scale_set(const stmdev_ctx_t *ctx, 1861 lsm6dsm_fs_g_t val); 1862 int32_t lsm6dsm_gy_full_scale_get(const stmdev_ctx_t *ctx, 1863 lsm6dsm_fs_g_t *val); 1864 1865 typedef enum 1866 { 1867 LSM6DSM_GY_ODR_OFF = 0, 1868 LSM6DSM_GY_ODR_12Hz5 = 1, 1869 LSM6DSM_GY_ODR_26Hz = 2, 1870 LSM6DSM_GY_ODR_52Hz = 3, 1871 LSM6DSM_GY_ODR_104Hz = 4, 1872 LSM6DSM_GY_ODR_208Hz = 5, 1873 LSM6DSM_GY_ODR_416Hz = 6, 1874 LSM6DSM_GY_ODR_833Hz = 7, 1875 LSM6DSM_GY_ODR_1k66Hz = 8, 1876 LSM6DSM_GY_ODR_3k33Hz = 9, 1877 LSM6DSM_GY_ODR_6k66Hz = 10, 1878 } lsm6dsm_odr_g_t; 1879 int32_t lsm6dsm_gy_data_rate_set(const stmdev_ctx_t *ctx, 1880 lsm6dsm_odr_g_t val); 1881 int32_t lsm6dsm_gy_data_rate_get(const stmdev_ctx_t *ctx, 1882 lsm6dsm_odr_g_t *val); 1883 1884 int32_t lsm6dsm_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 1885 int32_t lsm6dsm_block_data_update_get(const stmdev_ctx_t *ctx, 1886 uint8_t *val); 1887 1888 typedef enum 1889 { 1890 LSM6DSM_LSb_1mg = 0, 1891 LSM6DSM_LSb_16mg = 1, 1892 } lsm6dsm_usr_off_w_t; 1893 int32_t lsm6dsm_xl_offset_weight_set(const stmdev_ctx_t *ctx, 1894 lsm6dsm_usr_off_w_t val); 1895 int32_t lsm6dsm_xl_offset_weight_get(const stmdev_ctx_t *ctx, 1896 lsm6dsm_usr_off_w_t *val); 1897 1898 typedef enum 1899 { 1900 LSM6DSM_XL_HIGH_PERFORMANCE = 0, 1901 LSM6DSM_XL_NORMAL = 1, 1902 } lsm6dsm_xl_hm_mode_t; 1903 int32_t lsm6dsm_xl_power_mode_set(const stmdev_ctx_t *ctx, 1904 lsm6dsm_xl_hm_mode_t val); 1905 int32_t lsm6dsm_xl_power_mode_get(const stmdev_ctx_t *ctx, 1906 lsm6dsm_xl_hm_mode_t *val); 1907 1908 typedef enum 1909 { 1910 LSM6DSM_STAT_RND_DISABLE = 0, 1911 LSM6DSM_STAT_RND_ENABLE = 1, 1912 } lsm6dsm_rounding_status_t; 1913 int32_t lsm6dsm_rounding_on_status_set(const stmdev_ctx_t *ctx, 1914 lsm6dsm_rounding_status_t val); 1915 int32_t lsm6dsm_rounding_on_status_get(const stmdev_ctx_t *ctx, 1916 lsm6dsm_rounding_status_t *val); 1917 1918 typedef enum 1919 { 1920 LSM6DSM_GY_HIGH_PERFORMANCE = 0, 1921 LSM6DSM_GY_NORMAL = 1, 1922 } lsm6dsm_g_hm_mode_t; 1923 int32_t lsm6dsm_gy_power_mode_set(const stmdev_ctx_t *ctx, 1924 lsm6dsm_g_hm_mode_t val); 1925 int32_t lsm6dsm_gy_power_mode_get(const stmdev_ctx_t *ctx, 1926 lsm6dsm_g_hm_mode_t *val); 1927 1928 typedef struct 1929 { 1930 lsm6dsm_wake_up_src_t wake_up_src; 1931 lsm6dsm_tap_src_t tap_src; 1932 lsm6dsm_d6d_src_t d6d_src; 1933 lsm6dsm_status_reg_t status_reg; 1934 lsm6dsm_func_src1_t func_src1; 1935 lsm6dsm_func_src2_t func_src2; 1936 lsm6dsm_wrist_tilt_ia_t wrist_tilt_ia; 1937 lsm6dsm_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1938 } lsm6dsm_all_sources_t; 1939 int32_t lsm6dsm_all_sources_get(const stmdev_ctx_t *ctx, 1940 lsm6dsm_all_sources_t *val); 1941 1942 int32_t lsm6dsm_status_reg_get(const stmdev_ctx_t *ctx, 1943 lsm6dsm_status_reg_t *val); 1944 1945 int32_t lsm6dsm_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 1946 uint8_t *val); 1947 1948 int32_t lsm6dsm_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 1949 uint8_t *val); 1950 1951 int32_t lsm6dsm_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 1952 uint8_t *val); 1953 1954 int32_t lsm6dsm_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1955 int32_t lsm6dsm_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1956 int32_t lsm6dsm_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 1957 int32_t lsm6dsm_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 1958 1959 typedef enum 1960 { 1961 LSM6DSM_LSB_6ms4 = 0, 1962 LSM6DSM_LSB_25us = 1, 1963 } lsm6dsm_timer_hr_t; 1964 int32_t lsm6dsm_timestamp_res_set(const stmdev_ctx_t *ctx, 1965 lsm6dsm_timer_hr_t val); 1966 int32_t lsm6dsm_timestamp_res_get(const stmdev_ctx_t *ctx, 1967 lsm6dsm_timer_hr_t *val); 1968 1969 typedef enum 1970 { 1971 LSM6DSM_ROUND_DISABLE = 0, 1972 LSM6DSM_ROUND_XL = 1, 1973 LSM6DSM_ROUND_GY = 2, 1974 LSM6DSM_ROUND_GY_XL = 3, 1975 LSM6DSM_ROUND_SH1_TO_SH6 = 4, 1976 LSM6DSM_ROUND_XL_SH1_TO_SH6 = 5, 1977 LSM6DSM_ROUND_GY_XL_SH1_TO_SH12 = 6, 1978 LSM6DSM_ROUND_GY_XL_SH1_TO_SH6 = 7, 1979 } lsm6dsm_rounding_t; 1980 int32_t lsm6dsm_rounding_mode_set(const stmdev_ctx_t *ctx, 1981 lsm6dsm_rounding_t val); 1982 int32_t lsm6dsm_rounding_mode_get(const stmdev_ctx_t *ctx, 1983 lsm6dsm_rounding_t *val); 1984 1985 int32_t lsm6dsm_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1986 int32_t lsm6dsm_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1987 int32_t lsm6dsm_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1988 1989 int32_t lsm6dsm_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, 1990 int16_t *val); 1991 1992 int32_t lsm6dsm_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer, 1993 uint8_t len); 1994 1995 typedef enum 1996 { 1997 LSM6DSM_USER_BANK = 0, 1998 LSM6DSM_BANK_A = 4, 1999 LSM6DSM_BANK_B = 5, 2000 } lsm6dsm_func_cfg_en_t; 2001 int32_t lsm6dsm_mem_bank_set(const stmdev_ctx_t *ctx, 2002 lsm6dsm_func_cfg_en_t val); 2003 int32_t lsm6dsm_mem_bank_get(const stmdev_ctx_t *ctx, 2004 lsm6dsm_func_cfg_en_t *val); 2005 2006 typedef enum 2007 { 2008 LSM6DSM_DRDY_LATCHED = 0, 2009 LSM6DSM_DRDY_PULSED = 1, 2010 } lsm6dsm_drdy_pulsed_g_t; 2011 int32_t lsm6dsm_data_ready_mode_set(const stmdev_ctx_t *ctx, 2012 lsm6dsm_drdy_pulsed_g_t val); 2013 int32_t lsm6dsm_data_ready_mode_get(const stmdev_ctx_t *ctx, 2014 lsm6dsm_drdy_pulsed_g_t *val); 2015 2016 int32_t lsm6dsm_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2017 int32_t lsm6dsm_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 2018 int32_t lsm6dsm_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2019 2020 typedef enum 2021 { 2022 LSM6DSM_LSB_AT_LOW_ADD = 0, 2023 LSM6DSM_MSB_AT_LOW_ADD = 1, 2024 } lsm6dsm_ble_t; 2025 int32_t lsm6dsm_data_format_set(const stmdev_ctx_t *ctx, lsm6dsm_ble_t val); 2026 int32_t lsm6dsm_data_format_get(const stmdev_ctx_t *ctx, 2027 lsm6dsm_ble_t *val); 2028 2029 int32_t lsm6dsm_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 2030 int32_t lsm6dsm_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 2031 2032 int32_t lsm6dsm_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 2033 int32_t lsm6dsm_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 2034 2035 typedef enum 2036 { 2037 LSM6DSM_XL_ST_DISABLE = 0, 2038 LSM6DSM_XL_ST_POSITIVE = 1, 2039 LSM6DSM_XL_ST_NEGATIVE = 2, 2040 } lsm6dsm_st_xl_t; 2041 int32_t lsm6dsm_xl_self_test_set(const stmdev_ctx_t *ctx, 2042 lsm6dsm_st_xl_t val); 2043 int32_t lsm6dsm_xl_self_test_get(const stmdev_ctx_t *ctx, 2044 lsm6dsm_st_xl_t *val); 2045 2046 typedef enum 2047 { 2048 LSM6DSM_GY_ST_DISABLE = 0, 2049 LSM6DSM_GY_ST_POSITIVE = 1, 2050 LSM6DSM_GY_ST_NEGATIVE = 3, 2051 } lsm6dsm_st_g_t; 2052 int32_t lsm6dsm_gy_self_test_set(const stmdev_ctx_t *ctx, 2053 lsm6dsm_st_g_t val); 2054 int32_t lsm6dsm_gy_self_test_get(const stmdev_ctx_t *ctx, 2055 lsm6dsm_st_g_t *val); 2056 2057 int32_t lsm6dsm_filter_settling_mask_set(const stmdev_ctx_t *ctx, 2058 uint8_t val); 2059 int32_t lsm6dsm_filter_settling_mask_get(const stmdev_ctx_t *ctx, 2060 uint8_t *val); 2061 2062 typedef enum 2063 { 2064 LSM6DSM_USE_SLOPE = 0, 2065 LSM6DSM_USE_HPF = 1, 2066 } lsm6dsm_slope_fds_t; 2067 int32_t lsm6dsm_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 2068 lsm6dsm_slope_fds_t val); 2069 int32_t lsm6dsm_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 2070 lsm6dsm_slope_fds_t *val); 2071 2072 typedef enum 2073 { 2074 LSM6DSM_XL_ANA_BW_1k5Hz = 0, 2075 LSM6DSM_XL_ANA_BW_400Hz = 1, 2076 } lsm6dsm_bw0_xl_t; 2077 int32_t lsm6dsm_xl_filter_analog_set(const stmdev_ctx_t *ctx, 2078 lsm6dsm_bw0_xl_t val); 2079 int32_t lsm6dsm_xl_filter_analog_get(const stmdev_ctx_t *ctx, 2080 lsm6dsm_bw0_xl_t *val); 2081 2082 typedef enum 2083 { 2084 LSM6DSM_XL_LP1_ODR_DIV_2 = 0, 2085 LSM6DSM_XL_LP1_ODR_DIV_4 = 1, 2086 LSM6DSM_XL_LP1_NA = 2, /* ERROR CODE */ 2087 } lsm6dsm_lpf1_bw_sel_t; 2088 int32_t lsm6dsm_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2089 lsm6dsm_lpf1_bw_sel_t val); 2090 int32_t lsm6dsm_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2091 lsm6dsm_lpf1_bw_sel_t *val); 2092 2093 typedef enum 2094 { 2095 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00, 2096 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01, 2097 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02, 2098 LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400 = 0x03, 2099 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50 = 0x10, 2100 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100 = 0x11, 2101 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9 = 0x12, 2102 LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, 2103 LSM6DSM_XL_LP_NA = 0x20, /* ERROR CODE */ 2104 } lsm6dsm_input_composite_t; 2105 int32_t lsm6dsm_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, 2106 lsm6dsm_input_composite_t val); 2107 int32_t lsm6dsm_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, 2108 lsm6dsm_input_composite_t *val); 2109 2110 int32_t lsm6dsm_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2111 int32_t lsm6dsm_xl_reference_mode_get(const stmdev_ctx_t *ctx, 2112 uint8_t *val); 2113 2114 typedef enum 2115 { 2116 LSM6DSM_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */ 2117 LSM6DSM_XL_HP_ODR_DIV_100 = 0x01, 2118 LSM6DSM_XL_HP_ODR_DIV_9 = 0x02, 2119 LSM6DSM_XL_HP_ODR_DIV_400 = 0x03, 2120 LSM6DSM_XL_HP_NA = 0x10, /* ERROR CODE */ 2121 } lsm6dsm_hpcf_xl_t; 2122 int32_t lsm6dsm_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, 2123 lsm6dsm_hpcf_xl_t val); 2124 int32_t lsm6dsm_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, 2125 lsm6dsm_hpcf_xl_t *val); 2126 2127 typedef enum 2128 { 2129 LSM6DSM_XL_UI_LP1_ODR_DIV_2 = 0, 2130 LSM6DSM_XL_UI_LP1_ODR_DIV_4 = 1, 2131 LSM6DSM_XL_UI_LP1_NA = 2, 2132 } lsm6dsm_ui_lpf1_bw_sel_t; 2133 int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2134 lsm6dsm_ui_lpf1_bw_sel_t val); 2135 int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2136 lsm6dsm_ui_lpf1_bw_sel_t *val); 2137 2138 int32_t lsm6dsm_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val); 2139 int32_t lsm6dsm_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val); 2140 2141 typedef enum 2142 { 2143 LSM6DSM_AUX_LP_LIGHT = 2, 2144 LSM6DSM_AUX_LP_NORMAL = 3, 2145 LSM6DSM_AUX_LP_STRONG = 0, 2146 LSM6DSM_AUX_LP_AGGRESSIVE = 1, 2147 } lsm6dsm_filter_xl_conf_ois_t; 2148 int32_t lsm6dsm_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx, 2149 lsm6dsm_filter_xl_conf_ois_t val); 2150 int32_t lsm6dsm_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx, 2151 lsm6dsm_filter_xl_conf_ois_t *val); 2152 2153 typedef enum 2154 { 2155 LSM6DSM_LP2_ONLY = 0x00, 2156 2157 LSM6DSM_HP_16mHz_LP2 = 0x80, 2158 LSM6DSM_HP_65mHz_LP2 = 0x90, 2159 LSM6DSM_HP_260mHz_LP2 = 0xA0, 2160 LSM6DSM_HP_1Hz04_LP2 = 0xB0, 2161 2162 LSM6DSM_HP_DISABLE_LP1_LIGHT = 0x0A, 2163 LSM6DSM_HP_DISABLE_LP1_NORMAL = 0x09, 2164 LSM6DSM_HP_DISABLE_LP_STRONG = 0x08, 2165 LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, 2166 2167 LSM6DSM_HP_16mHz_LP1_LIGHT = 0x8A, 2168 LSM6DSM_HP_65mHz_LP1_NORMAL = 0x99, 2169 LSM6DSM_HP_260mHz_LP1_STRONG = 0xA8, 2170 LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, 2171 } lsm6dsm_lpf1_sel_g_t; 2172 int32_t lsm6dsm_gy_band_pass_set(const stmdev_ctx_t *ctx, 2173 lsm6dsm_lpf1_sel_g_t val); 2174 int32_t lsm6dsm_gy_band_pass_get(const stmdev_ctx_t *ctx, 2175 lsm6dsm_lpf1_sel_g_t *val); 2176 2177 int32_t lsm6dsm_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val); 2178 int32_t lsm6dsm_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val); 2179 2180 typedef enum 2181 { 2182 LSM6DSM_HP_DISABLE_LP_173Hz = 0x02, 2183 LSM6DSM_HP_DISABLE_LP_237Hz = 0x01, 2184 LSM6DSM_HP_DISABLE_LP_351Hz = 0x00, 2185 LSM6DSM_HP_DISABLE_LP_937Hz = 0x03, 2186 2187 LSM6DSM_HP_16mHz_LP_173Hz = 0x82, 2188 LSM6DSM_HP_65mHz_LP_237Hz = 0x91, 2189 LSM6DSM_HP_260mHz_LP_351Hz = 0xA0, 2190 LSM6DSM_HP_1Hz04_LP_937Hz = 0xB3, 2191 } lsm6dsm_hp_en_ois_t; 2192 int32_t lsm6dsm_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx, 2193 lsm6dsm_hp_en_ois_t val); 2194 int32_t lsm6dsm_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx, 2195 lsm6dsm_hp_en_ois_t *val); 2196 2197 int32_t lsm6dsm_aux_status_reg_get(const stmdev_ctx_t *ctx, 2198 lsm6dsm_status_spiaux_t *val); 2199 2200 int32_t lsm6dsm_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 2201 uint8_t *val); 2202 2203 int32_t lsm6dsm_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 2204 uint8_t *val); 2205 2206 int32_t lsm6dsm_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx, 2207 uint8_t *val); 2208 2209 typedef enum 2210 { 2211 LSM6DSM_AUX_DEN_DISABLE = 0, 2212 LSM6DSM_AUX_DEN_LEVEL_LATCH = 3, 2213 LSM6DSM_AUX_DEN_LEVEL_TRIG = 2, 2214 } lsm6dsm_lvl_ois_t; 2215 int32_t lsm6dsm_aux_den_mode_set(const stmdev_ctx_t *ctx, 2216 lsm6dsm_lvl_ois_t val); 2217 int32_t lsm6dsm_aux_den_mode_get(const stmdev_ctx_t *ctx, 2218 lsm6dsm_lvl_ois_t *val); 2219 2220 int32_t lsm6dsm_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val); 2221 int32_t lsm6dsm_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val); 2222 2223 typedef enum 2224 { 2225 LSM6DSM_AUX_DISABLE = 0, 2226 LSM6DSM_MODE_3_GY = 1, 2227 LSM6DSM_MODE_4_GY_XL = 3, 2228 } lsm6dsm_ois_en_spi2_t; 2229 int32_t lsm6dsm_aux_mode_set(const stmdev_ctx_t *ctx, 2230 lsm6dsm_ois_en_spi2_t val); 2231 int32_t lsm6dsm_aux_mode_get(const stmdev_ctx_t *ctx, 2232 lsm6dsm_ois_en_spi2_t *val); 2233 2234 typedef enum 2235 { 2236 LSM6DSM_250dps_AUX = 0, 2237 LSM6DSM_125dps_AUX = 1, 2238 LSM6DSM_500dps_AUX = 2, 2239 LSM6DSM_1000dps_AUX = 4, 2240 LSM6DSM_2000dps_AUX = 6, 2241 } lsm6dsm_fs_g_ois_t; 2242 int32_t lsm6dsm_aux_gy_full_scale_set(const stmdev_ctx_t *ctx, 2243 lsm6dsm_fs_g_ois_t val); 2244 int32_t lsm6dsm_aux_gy_full_scale_get(const stmdev_ctx_t *ctx, 2245 lsm6dsm_fs_g_ois_t *val); 2246 2247 typedef enum 2248 { 2249 LSM6DSM_AUX_SPI_4_WIRE = 0, 2250 LSM6DSM_AUX_SPI_3_WIRE = 1, 2251 } lsm6dsm_sim_ois_t; 2252 int32_t lsm6dsm_aux_spi_mode_set(const stmdev_ctx_t *ctx, 2253 lsm6dsm_sim_ois_t val); 2254 int32_t lsm6dsm_aux_spi_mode_get(const stmdev_ctx_t *ctx, 2255 lsm6dsm_sim_ois_t *val); 2256 2257 typedef enum 2258 { 2259 LSM6DSM_AUX_LSB_AT_LOW_ADD = 0, 2260 LSM6DSM_AUX_MSB_AT_LOW_ADD = 1, 2261 } lsm6dsm_ble_ois_t; 2262 int32_t lsm6dsm_aux_data_format_set(const stmdev_ctx_t *ctx, 2263 lsm6dsm_ble_ois_t val); 2264 int32_t lsm6dsm_aux_data_format_get(const stmdev_ctx_t *ctx, 2265 lsm6dsm_ble_ois_t *val); 2266 2267 typedef enum 2268 { 2269 LSM6DSM_ENABLE_CLAMP = 0, 2270 LSM6DSM_DISABLE_CLAMP = 1, 2271 } lsm6dsm_st_ois_clampdis_t; 2272 int32_t lsm6dsm_aux_gy_clamp_set(const stmdev_ctx_t *ctx, 2273 lsm6dsm_st_ois_clampdis_t val); 2274 int32_t lsm6dsm_aux_gy_clamp_get(const stmdev_ctx_t *ctx, 2275 lsm6dsm_st_ois_clampdis_t *val); 2276 2277 typedef enum 2278 { 2279 LSM6DSM_AUX_GY_DISABLE = 0, 2280 LSM6DSM_AUX_GY_POS = 1, 2281 LSM6DSM_AUX_GY_NEG = 3, 2282 } lsm6dsm_st_ois_t; 2283 int32_t lsm6dsm_aux_gy_self_test_set(const stmdev_ctx_t *ctx, 2284 lsm6dsm_st_ois_t val); 2285 int32_t lsm6dsm_aux_gy_self_test_get(const stmdev_ctx_t *ctx, 2286 lsm6dsm_st_ois_t *val); 2287 2288 typedef enum 2289 { 2290 LSM6DSM_AUX_2g = 0, 2291 LSM6DSM_AUX_16g = 1, 2292 LSM6DSM_AUX_4g = 2, 2293 LSM6DSM_AUX_8g = 3, 2294 } lsm6dsm_fs_xl_ois_t; 2295 int32_t lsm6dsm_aux_xl_full_scale_set(const stmdev_ctx_t *ctx, 2296 lsm6dsm_fs_xl_ois_t val); 2297 int32_t lsm6dsm_aux_xl_full_scale_get(const stmdev_ctx_t *ctx, 2298 lsm6dsm_fs_xl_ois_t *val); 2299 2300 typedef enum 2301 { 2302 LSM6DSM_AUX_DEN_ACTIVE_LOW = 0, 2303 LSM6DSM_AUX_DEN_ACTIVE_HIGH = 1, 2304 } lsm6dsm_den_lh_ois_t; 2305 int32_t lsm6dsm_aux_den_polarity_set(const stmdev_ctx_t *ctx, 2306 lsm6dsm_den_lh_ois_t val); 2307 int32_t lsm6dsm_aux_den_polarity_get(const stmdev_ctx_t *ctx, 2308 lsm6dsm_den_lh_ois_t *val); 2309 2310 typedef enum 2311 { 2312 LSM6DSM_SPI_4_WIRE = 0, 2313 LSM6DSM_SPI_3_WIRE = 1, 2314 } lsm6dsm_sim_t; 2315 int32_t lsm6dsm_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_sim_t val); 2316 int32_t lsm6dsm_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_sim_t *val); 2317 2318 typedef enum 2319 { 2320 LSM6DSM_I2C_ENABLE = 0, 2321 LSM6DSM_I2C_DISABLE = 1, 2322 } lsm6dsm_i2c_disable_t; 2323 int32_t lsm6dsm_i2c_interface_set(const stmdev_ctx_t *ctx, 2324 lsm6dsm_i2c_disable_t val); 2325 int32_t lsm6dsm_i2c_interface_get(const stmdev_ctx_t *ctx, 2326 lsm6dsm_i2c_disable_t *val); 2327 2328 typedef struct 2329 { 2330 uint8_t int1_drdy_xl : 1; 2331 uint8_t int1_drdy_g : 1; 2332 uint8_t int1_boot : 1; 2333 uint8_t int1_fth : 1; 2334 uint8_t int1_fifo_ovr : 1; 2335 uint8_t int1_full_flag : 1; 2336 uint8_t int1_sign_mot : 1; 2337 uint8_t int1_step_detector : 1; 2338 uint8_t int1_timer : 1; 2339 uint8_t int1_tilt : 1; 2340 uint8_t int1_6d : 1; 2341 uint8_t int1_double_tap : 1; 2342 uint8_t int1_ff : 1; 2343 uint8_t int1_wu : 1; 2344 uint8_t int1_single_tap : 1; 2345 uint8_t int1_inact_state : 1; 2346 uint8_t den_drdy_int1 : 1; 2347 uint8_t drdy_on_int1 : 1; 2348 } lsm6dsm_int1_route_t; 2349 int32_t lsm6dsm_pin_int1_route_set(const stmdev_ctx_t *ctx, 2350 lsm6dsm_int1_route_t val); 2351 int32_t lsm6dsm_pin_int1_route_get(const stmdev_ctx_t *ctx, 2352 lsm6dsm_int1_route_t *val); 2353 2354 typedef struct 2355 { 2356 uint8_t int2_drdy_xl : 1; 2357 uint8_t int2_drdy_g : 1; 2358 uint8_t int2_drdy_temp : 1; 2359 uint8_t int2_fth : 1; 2360 uint8_t int2_fifo_ovr : 1; 2361 uint8_t int2_full_flag : 1; 2362 uint8_t int2_step_count_ov : 1; 2363 uint8_t int2_step_delta : 1; 2364 uint8_t int2_iron : 1; 2365 uint8_t int2_tilt : 1; 2366 uint8_t int2_6d : 1; 2367 uint8_t int2_double_tap : 1; 2368 uint8_t int2_ff : 1; 2369 uint8_t int2_wu : 1; 2370 uint8_t int2_single_tap : 1; 2371 uint8_t int2_inact_state : 1; 2372 uint8_t int2_wrist_tilt : 1; 2373 } lsm6dsm_int2_route_t; 2374 int32_t lsm6dsm_pin_int2_route_set(const stmdev_ctx_t *ctx, 2375 lsm6dsm_int2_route_t val); 2376 int32_t lsm6dsm_pin_int2_route_get(const stmdev_ctx_t *ctx, 2377 lsm6dsm_int2_route_t *val); 2378 2379 typedef enum 2380 { 2381 LSM6DSM_PUSH_PULL = 0, 2382 LSM6DSM_OPEN_DRAIN = 1, 2383 } lsm6dsm_pp_od_t; 2384 int32_t lsm6dsm_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val); 2385 int32_t lsm6dsm_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val); 2386 2387 typedef enum 2388 { 2389 LSM6DSM_ACTIVE_HIGH = 0, 2390 LSM6DSM_ACTIVE_LOW = 1, 2391 } lsm6dsm_h_lactive_t; 2392 int32_t lsm6dsm_pin_polarity_set(const stmdev_ctx_t *ctx, 2393 lsm6dsm_h_lactive_t val); 2394 int32_t lsm6dsm_pin_polarity_get(const stmdev_ctx_t *ctx, 2395 lsm6dsm_h_lactive_t *val); 2396 2397 int32_t lsm6dsm_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 2398 int32_t lsm6dsm_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2399 2400 typedef enum 2401 { 2402 LSM6DSM_INT_PULSED = 0, 2403 LSM6DSM_INT_LATCHED = 1, 2404 } lsm6dsm_lir_t; 2405 int32_t lsm6dsm_int_notification_set(const stmdev_ctx_t *ctx, 2406 lsm6dsm_lir_t val); 2407 int32_t lsm6dsm_int_notification_get(const stmdev_ctx_t *ctx, 2408 lsm6dsm_lir_t *val); 2409 2410 int32_t lsm6dsm_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 2411 int32_t lsm6dsm_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 2412 2413 int32_t lsm6dsm_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2414 int32_t lsm6dsm_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2415 2416 int32_t lsm6dsm_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2417 int32_t lsm6dsm_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2418 2419 typedef enum 2420 { 2421 LSM6DSM_PROPERTY_DISABLE = 0, 2422 LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED = 1, 2423 LSM6DSM_XL_12Hz5_GY_SLEEP = 2, 2424 LSM6DSM_XL_12Hz5_GY_PD = 3, 2425 } lsm6dsm_inact_en_t; 2426 int32_t lsm6dsm_act_mode_set(const stmdev_ctx_t *ctx, 2427 lsm6dsm_inact_en_t val); 2428 int32_t lsm6dsm_act_mode_get(const stmdev_ctx_t *ctx, 2429 lsm6dsm_inact_en_t *val); 2430 2431 int32_t lsm6dsm_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2432 int32_t lsm6dsm_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2433 2434 int32_t lsm6dsm_tap_src_get(const stmdev_ctx_t *ctx, 2435 lsm6dsm_tap_src_t *val); 2436 2437 int32_t lsm6dsm_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 2438 uint8_t val); 2439 int32_t lsm6dsm_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 2440 uint8_t *val); 2441 2442 int32_t lsm6dsm_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 2443 uint8_t val); 2444 int32_t lsm6dsm_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 2445 uint8_t *val); 2446 2447 int32_t lsm6dsm_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 2448 uint8_t val); 2449 int32_t lsm6dsm_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 2450 uint8_t *val); 2451 2452 int32_t lsm6dsm_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val); 2453 int32_t lsm6dsm_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 2454 2455 int32_t lsm6dsm_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 2456 int32_t lsm6dsm_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 2457 2458 int32_t lsm6dsm_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 2459 int32_t lsm6dsm_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 2460 2461 int32_t lsm6dsm_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2462 int32_t lsm6dsm_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2463 2464 typedef enum 2465 { 2466 LSM6DSM_ONLY_SINGLE = 0, 2467 LSM6DSM_BOTH_SINGLE_DOUBLE = 1, 2468 } lsm6dsm_single_double_tap_t; 2469 int32_t lsm6dsm_tap_mode_set(const stmdev_ctx_t *ctx, 2470 lsm6dsm_single_double_tap_t val); 2471 int32_t lsm6dsm_tap_mode_get(const stmdev_ctx_t *ctx, 2472 lsm6dsm_single_double_tap_t *val); 2473 2474 typedef enum 2475 { 2476 LSM6DSM_ODR_DIV_2_FEED = 0, 2477 LSM6DSM_LPF2_FEED = 1, 2478 } lsm6dsm_low_pass_on_6d_t; 2479 int32_t lsm6dsm_6d_feed_data_set(const stmdev_ctx_t *ctx, 2480 lsm6dsm_low_pass_on_6d_t val); 2481 int32_t lsm6dsm_6d_feed_data_get(const stmdev_ctx_t *ctx, 2482 lsm6dsm_low_pass_on_6d_t *val); 2483 2484 typedef enum 2485 { 2486 LSM6DSM_DEG_80 = 0, 2487 LSM6DSM_DEG_70 = 1, 2488 LSM6DSM_DEG_60 = 2, 2489 LSM6DSM_DEG_50 = 3, 2490 } lsm6dsm_sixd_ths_t; 2491 int32_t lsm6dsm_6d_threshold_set(const stmdev_ctx_t *ctx, 2492 lsm6dsm_sixd_ths_t val); 2493 int32_t lsm6dsm_6d_threshold_get(const stmdev_ctx_t *ctx, 2494 lsm6dsm_sixd_ths_t *val); 2495 2496 int32_t lsm6dsm_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2497 int32_t lsm6dsm_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2498 2499 int32_t lsm6dsm_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2500 int32_t lsm6dsm_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2501 2502 typedef enum 2503 { 2504 LSM6DSM_FF_TSH_156mg = 0, 2505 LSM6DSM_FF_TSH_219mg = 1, 2506 LSM6DSM_FF_TSH_250mg = 2, 2507 LSM6DSM_FF_TSH_312mg = 3, 2508 LSM6DSM_FF_TSH_344mg = 4, 2509 LSM6DSM_FF_TSH_406mg = 5, 2510 LSM6DSM_FF_TSH_469mg = 6, 2511 LSM6DSM_FF_TSH_500mg = 7, 2512 } lsm6dsm_ff_ths_t; 2513 int32_t lsm6dsm_ff_threshold_set(const stmdev_ctx_t *ctx, 2514 lsm6dsm_ff_ths_t val); 2515 int32_t lsm6dsm_ff_threshold_get(const stmdev_ctx_t *ctx, 2516 lsm6dsm_ff_ths_t *val); 2517 2518 int32_t lsm6dsm_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); 2519 int32_t lsm6dsm_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); 2520 2521 int32_t lsm6dsm_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 2522 2523 int32_t lsm6dsm_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2524 int32_t lsm6dsm_fifo_over_run_get(const stmdev_ctx_t *ctx, uint8_t *val); 2525 2526 int32_t lsm6dsm_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val); 2527 2528 int32_t lsm6dsm_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 2529 int32_t lsm6dsm_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 2530 2531 typedef enum 2532 { 2533 LSM6DSM_TRG_XL_GY_DRDY = 0, 2534 LSM6DSM_TRG_STEP_DETECT = 1, 2535 LSM6DSM_TRG_SH_DRDY = 2, 2536 } lsm6dsm_trigger_fifo_t; 2537 int32_t lsm6dsm_fifo_write_trigger_set(const stmdev_ctx_t *ctx, 2538 lsm6dsm_trigger_fifo_t val); 2539 int32_t lsm6dsm_fifo_write_trigger_get(const stmdev_ctx_t *ctx, 2540 lsm6dsm_trigger_fifo_t *val); 2541 2542 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(const stmdev_ctx_t *ctx, 2543 uint8_t val); 2544 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx, 2545 uint8_t *val); 2546 2547 typedef enum 2548 { 2549 LSM6DSM_FIFO_XL_DISABLE = 0, 2550 LSM6DSM_FIFO_XL_NO_DEC = 1, 2551 LSM6DSM_FIFO_XL_DEC_2 = 2, 2552 LSM6DSM_FIFO_XL_DEC_3 = 3, 2553 LSM6DSM_FIFO_XL_DEC_4 = 4, 2554 LSM6DSM_FIFO_XL_DEC_8 = 5, 2555 LSM6DSM_FIFO_XL_DEC_16 = 6, 2556 LSM6DSM_FIFO_XL_DEC_32 = 7, 2557 } lsm6dsm_dec_fifo_xl_t; 2558 int32_t lsm6dsm_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 2559 lsm6dsm_dec_fifo_xl_t val); 2560 int32_t lsm6dsm_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 2561 lsm6dsm_dec_fifo_xl_t *val); 2562 2563 typedef enum 2564 { 2565 LSM6DSM_FIFO_GY_DISABLE = 0, 2566 LSM6DSM_FIFO_GY_NO_DEC = 1, 2567 LSM6DSM_FIFO_GY_DEC_2 = 2, 2568 LSM6DSM_FIFO_GY_DEC_3 = 3, 2569 LSM6DSM_FIFO_GY_DEC_4 = 4, 2570 LSM6DSM_FIFO_GY_DEC_8 = 5, 2571 LSM6DSM_FIFO_GY_DEC_16 = 6, 2572 LSM6DSM_FIFO_GY_DEC_32 = 7, 2573 } lsm6dsm_dec_fifo_gyro_t; 2574 int32_t lsm6dsm_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 2575 lsm6dsm_dec_fifo_gyro_t val); 2576 int32_t lsm6dsm_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 2577 lsm6dsm_dec_fifo_gyro_t *val); 2578 2579 typedef enum 2580 { 2581 LSM6DSM_FIFO_DS3_DISABLE = 0, 2582 LSM6DSM_FIFO_DS3_NO_DEC = 1, 2583 LSM6DSM_FIFO_DS3_DEC_2 = 2, 2584 LSM6DSM_FIFO_DS3_DEC_3 = 3, 2585 LSM6DSM_FIFO_DS3_DEC_4 = 4, 2586 LSM6DSM_FIFO_DS3_DEC_8 = 5, 2587 LSM6DSM_FIFO_DS3_DEC_16 = 6, 2588 LSM6DSM_FIFO_DS3_DEC_32 = 7, 2589 } lsm6dsm_dec_ds3_fifo_t; 2590 int32_t lsm6dsm_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, 2591 lsm6dsm_dec_ds3_fifo_t val); 2592 int32_t lsm6dsm_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, 2593 lsm6dsm_dec_ds3_fifo_t *val); 2594 2595 typedef enum 2596 { 2597 LSM6DSM_FIFO_DS4_DISABLE = 0, 2598 LSM6DSM_FIFO_DS4_NO_DEC = 1, 2599 LSM6DSM_FIFO_DS4_DEC_2 = 2, 2600 LSM6DSM_FIFO_DS4_DEC_3 = 3, 2601 LSM6DSM_FIFO_DS4_DEC_4 = 4, 2602 LSM6DSM_FIFO_DS4_DEC_8 = 5, 2603 LSM6DSM_FIFO_DS4_DEC_16 = 6, 2604 LSM6DSM_FIFO_DS4_DEC_32 = 7, 2605 } lsm6dsm_dec_ds4_fifo_t; 2606 int32_t lsm6dsm_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, 2607 lsm6dsm_dec_ds4_fifo_t val); 2608 int32_t lsm6dsm_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, 2609 lsm6dsm_dec_ds4_fifo_t *val); 2610 2611 int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, 2612 uint8_t val); 2613 int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, 2614 uint8_t *val); 2615 2616 int32_t lsm6dsm_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 2617 int32_t lsm6dsm_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 2618 2619 typedef enum 2620 { 2621 LSM6DSM_BYPASS_MODE = 0, 2622 LSM6DSM_FIFO_MODE = 1, 2623 LSM6DSM_STREAM_TO_FIFO_MODE = 3, 2624 LSM6DSM_BYPASS_TO_STREAM_MODE = 4, 2625 LSM6DSM_STREAM_MODE = 6, 2626 } lsm6dsm_fifo_mode_t; 2627 int32_t lsm6dsm_fifo_mode_set(const stmdev_ctx_t *ctx, 2628 lsm6dsm_fifo_mode_t val); 2629 int32_t lsm6dsm_fifo_mode_get(const stmdev_ctx_t *ctx, 2630 lsm6dsm_fifo_mode_t *val); 2631 2632 typedef enum 2633 { 2634 LSM6DSM_FIFO_DISABLE = 0, 2635 LSM6DSM_FIFO_12Hz5 = 1, 2636 LSM6DSM_FIFO_26Hz = 2, 2637 LSM6DSM_FIFO_52Hz = 3, 2638 LSM6DSM_FIFO_104Hz = 4, 2639 LSM6DSM_FIFO_208Hz = 5, 2640 LSM6DSM_FIFO_416Hz = 6, 2641 LSM6DSM_FIFO_833Hz = 7, 2642 LSM6DSM_FIFO_1k66Hz = 8, 2643 LSM6DSM_FIFO_3k33Hz = 9, 2644 LSM6DSM_FIFO_6k66Hz = 10, 2645 } lsm6dsm_odr_fifo_t; 2646 int32_t lsm6dsm_fifo_data_rate_set(const stmdev_ctx_t *ctx, 2647 lsm6dsm_odr_fifo_t val); 2648 int32_t lsm6dsm_fifo_data_rate_get(const stmdev_ctx_t *ctx, 2649 lsm6dsm_odr_fifo_t *val); 2650 2651 typedef enum 2652 { 2653 LSM6DSM_DEN_ACT_LOW = 0, 2654 LSM6DSM_DEN_ACT_HIGH = 1, 2655 } lsm6dsm_den_lh_t; 2656 int32_t lsm6dsm_den_polarity_set(const stmdev_ctx_t *ctx, 2657 lsm6dsm_den_lh_t val); 2658 int32_t lsm6dsm_den_polarity_get(const stmdev_ctx_t *ctx, 2659 lsm6dsm_den_lh_t *val); 2660 2661 typedef enum 2662 { 2663 LSM6DSM_DEN_DISABLE = 0, 2664 LSM6DSM_LEVEL_FIFO = 6, 2665 LSM6DSM_LEVEL_LETCHED = 3, 2666 LSM6DSM_LEVEL_TRIGGER = 2, 2667 LSM6DSM_EDGE_TRIGGER = 4, 2668 } lsm6dsm_den_mode_t; 2669 int32_t lsm6dsm_den_mode_set(const stmdev_ctx_t *ctx, 2670 lsm6dsm_den_mode_t val); 2671 int32_t lsm6dsm_den_mode_get(const stmdev_ctx_t *ctx, 2672 lsm6dsm_den_mode_t *val); 2673 2674 typedef enum 2675 { 2676 LSM6DSM_STAMP_IN_GY_DATA = 0, 2677 LSM6DSM_STAMP_IN_XL_DATA = 1, 2678 LSM6DSM_STAMP_IN_GY_XL_DATA = 2, 2679 } lsm6dsm_den_xl_en_t; 2680 int32_t lsm6dsm_den_enable_set(const stmdev_ctx_t *ctx, 2681 lsm6dsm_den_xl_en_t val); 2682 int32_t lsm6dsm_den_enable_get(const stmdev_ctx_t *ctx, 2683 lsm6dsm_den_xl_en_t *val); 2684 2685 int32_t lsm6dsm_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); 2686 int32_t lsm6dsm_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); 2687 2688 int32_t lsm6dsm_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); 2689 int32_t lsm6dsm_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); 2690 2691 int32_t lsm6dsm_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); 2692 int32_t lsm6dsm_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 2693 2694 int32_t lsm6dsm_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 2695 int32_t lsm6dsm_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2696 2697 int32_t lsm6dsm_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 2698 int32_t lsm6dsm_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 2699 2700 int32_t lsm6dsm_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 2701 int32_t lsm6dsm_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 2702 2703 typedef enum 2704 { 2705 LSM6DSM_PEDO_AT_2g = 0, 2706 LSM6DSM_PEDO_AT_4g = 1, 2707 } lsm6dsm_pedo_fs_t; 2708 int32_t lsm6dsm_pedo_full_scale_set(const stmdev_ctx_t *ctx, 2709 lsm6dsm_pedo_fs_t val); 2710 int32_t lsm6dsm_pedo_full_scale_get(const stmdev_ctx_t *ctx, 2711 lsm6dsm_pedo_fs_t *val); 2712 2713 int32_t lsm6dsm_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 2714 uint8_t val); 2715 int32_t lsm6dsm_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 2716 uint8_t *val); 2717 2718 int32_t lsm6dsm_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 2719 int32_t lsm6dsm_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); 2720 2721 int32_t lsm6dsm_pedo_steps_period_set(const stmdev_ctx_t *ctx, 2722 uint8_t *buff); 2723 int32_t lsm6dsm_pedo_steps_period_get(const stmdev_ctx_t *ctx, 2724 uint8_t *buff); 2725 2726 int32_t lsm6dsm_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 2727 int32_t lsm6dsm_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 2728 2729 int32_t lsm6dsm_motion_threshold_set(const stmdev_ctx_t *ctx, 2730 uint8_t *buff); 2731 int32_t lsm6dsm_motion_threshold_get(const stmdev_ctx_t *ctx, 2732 uint8_t *buff); 2733 2734 int32_t lsm6dsm_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 2735 int32_t lsm6dsm_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 2736 2737 int32_t lsm6dsm_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 2738 int32_t lsm6dsm_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 2739 2740 int32_t lsm6dsm_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff); 2741 int32_t lsm6dsm_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2742 2743 int32_t lsm6dsm_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff); 2744 int32_t lsm6dsm_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2745 2746 int32_t lsm6dsm_tilt_src_set(const stmdev_ctx_t *ctx, 2747 lsm6dsm_a_wrist_tilt_mask_t *val); 2748 int32_t lsm6dsm_tilt_src_get(const stmdev_ctx_t *ctx, 2749 lsm6dsm_a_wrist_tilt_mask_t *val); 2750 2751 int32_t lsm6dsm_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val); 2752 int32_t lsm6dsm_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); 2753 2754 int32_t lsm6dsm_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val); 2755 int32_t lsm6dsm_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val); 2756 2757 int32_t lsm6dsm_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, 2758 uint8_t *buff); 2759 int32_t lsm6dsm_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, 2760 uint8_t *buff); 2761 2762 int32_t lsm6dsm_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 2763 int32_t lsm6dsm_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 2764 2765 int32_t lsm6dsm_func_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2766 2767 int32_t lsm6dsm_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, 2768 uint8_t val); 2769 int32_t lsm6dsm_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, 2770 uint8_t *val); 2771 2772 typedef enum 2773 { 2774 LSM6DSM_RES_RATIO_2_11 = 0, 2775 LSM6DSM_RES_RATIO_2_12 = 1, 2776 LSM6DSM_RES_RATIO_2_13 = 2, 2777 LSM6DSM_RES_RATIO_2_14 = 3, 2778 } lsm6dsm_rr_t; 2779 int32_t lsm6dsm_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, 2780 lsm6dsm_rr_t val); 2781 int32_t lsm6dsm_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, 2782 lsm6dsm_rr_t *val); 2783 2784 int32_t lsm6dsm_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 2785 int32_t lsm6dsm_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 2786 2787 int32_t lsm6dsm_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); 2788 int32_t lsm6dsm_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); 2789 2790 typedef enum 2791 { 2792 LSM6DSM_EXT_PULL_UP = 0, 2793 LSM6DSM_INTERNAL_PULL_UP = 1, 2794 LSM6DSM_SH_PIN_MODE = 2, 2795 } lsm6dsm_pull_up_en_t; 2796 int32_t lsm6dsm_sh_pin_mode_set(const stmdev_ctx_t *ctx, 2797 lsm6dsm_pull_up_en_t val); 2798 int32_t lsm6dsm_sh_pin_mode_get(const stmdev_ctx_t *ctx, 2799 lsm6dsm_pull_up_en_t *val); 2800 2801 typedef enum 2802 { 2803 LSM6DSM_XL_GY_DRDY = 0, 2804 LSM6DSM_EXT_ON_INT2_PIN = 1, 2805 } lsm6dsm_start_config_t; 2806 int32_t lsm6dsm_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 2807 lsm6dsm_start_config_t val); 2808 int32_t lsm6dsm_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 2809 lsm6dsm_start_config_t *val); 2810 2811 int32_t lsm6dsm_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 2812 int32_t lsm6dsm_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2813 2814 typedef struct 2815 { 2816 lsm6dsm_sensorhub1_reg_t sh_byte_1; 2817 lsm6dsm_sensorhub2_reg_t sh_byte_2; 2818 lsm6dsm_sensorhub3_reg_t sh_byte_3; 2819 lsm6dsm_sensorhub4_reg_t sh_byte_4; 2820 lsm6dsm_sensorhub5_reg_t sh_byte_5; 2821 lsm6dsm_sensorhub6_reg_t sh_byte_6; 2822 lsm6dsm_sensorhub7_reg_t sh_byte_7; 2823 lsm6dsm_sensorhub8_reg_t sh_byte_8; 2824 lsm6dsm_sensorhub9_reg_t sh_byte_9; 2825 lsm6dsm_sensorhub10_reg_t sh_byte_10; 2826 lsm6dsm_sensorhub11_reg_t sh_byte_11; 2827 lsm6dsm_sensorhub12_reg_t sh_byte_12; 2828 lsm6dsm_sensorhub13_reg_t sh_byte_13; 2829 lsm6dsm_sensorhub14_reg_t sh_byte_14; 2830 lsm6dsm_sensorhub15_reg_t sh_byte_15; 2831 lsm6dsm_sensorhub16_reg_t sh_byte_16; 2832 lsm6dsm_sensorhub17_reg_t sh_byte_17; 2833 lsm6dsm_sensorhub18_reg_t sh_byte_18; 2834 } lsm6dsm_emb_sh_read_t; 2835 int32_t lsm6dsm_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 2836 lsm6dsm_emb_sh_read_t *val); 2837 2838 int32_t lsm6dsm_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val); 2839 int32_t lsm6dsm_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val); 2840 2841 int32_t lsm6dsm_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val); 2842 int32_t lsm6dsm_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, 2843 uint8_t *val); 2844 2845 typedef enum 2846 { 2847 LSM6DSM_NORMAL_MODE_READ = 0, 2848 LSM6DSM_SRC_MODE_READ = 1, 2849 } lsm6dsm_src_mode_t; 2850 int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_set(const stmdev_ctx_t *ctx, 2851 lsm6dsm_src_mode_t val); 2852 int32_t lsm6dsm_sh_cfg_slave_0_rd_mode_get(const stmdev_ctx_t *ctx, 2853 lsm6dsm_src_mode_t *val); 2854 2855 typedef enum 2856 { 2857 LSM6DSM_SLV_0 = 0, 2858 LSM6DSM_SLV_0_1 = 1, 2859 LSM6DSM_SLV_0_1_2 = 2, 2860 LSM6DSM_SLV_0_1_2_3 = 3, 2861 } lsm6dsm_aux_sens_on_t; 2862 int32_t lsm6dsm_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, 2863 lsm6dsm_aux_sens_on_t val); 2864 int32_t lsm6dsm_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, 2865 lsm6dsm_aux_sens_on_t *val); 2866 2867 typedef struct 2868 { 2869 uint8_t slv0_add; 2870 uint8_t slv0_subadd; 2871 uint8_t slv0_data; 2872 } lsm6dsm_sh_cfg_write_t; 2873 int32_t lsm6dsm_sh_cfg_write(const stmdev_ctx_t *ctx, 2874 lsm6dsm_sh_cfg_write_t *val); 2875 2876 typedef struct 2877 { 2878 uint8_t slv_add; 2879 uint8_t slv_subadd; 2880 uint8_t slv_len; 2881 } lsm6dsm_sh_cfg_read_t; 2882 int32_t lsm6dsm_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 2883 lsm6dsm_sh_cfg_read_t *val); 2884 int32_t lsm6dsm_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 2885 lsm6dsm_sh_cfg_read_t *val); 2886 int32_t lsm6dsm_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 2887 lsm6dsm_sh_cfg_read_t *val); 2888 int32_t lsm6dsm_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 2889 lsm6dsm_sh_cfg_read_t *val); 2890 2891 typedef enum 2892 { 2893 LSM6DSM_SL0_NO_DEC = 0, 2894 LSM6DSM_SL0_DEC_2 = 1, 2895 LSM6DSM_SL0_DEC_4 = 2, 2896 LSM6DSM_SL0_DEC_8 = 3, 2897 } lsm6dsm_slave0_rate_t; 2898 int32_t lsm6dsm_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, 2899 lsm6dsm_slave0_rate_t val); 2900 int32_t lsm6dsm_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, 2901 lsm6dsm_slave0_rate_t *val); 2902 2903 typedef enum 2904 { 2905 LSM6DSM_EACH_SH_CYCLE = 0, 2906 LSM6DSM_ONLY_FIRST_CYCLE = 1, 2907 } lsm6dsm_write_once_t; 2908 int32_t lsm6dsm_sh_write_mode_set(const stmdev_ctx_t *ctx, 2909 lsm6dsm_write_once_t val); 2910 int32_t lsm6dsm_sh_write_mode_get(const stmdev_ctx_t *ctx, 2911 lsm6dsm_write_once_t *val); 2912 2913 typedef enum 2914 { 2915 LSM6DSM_SL1_NO_DEC = 0, 2916 LSM6DSM_SL1_DEC_2 = 1, 2917 LSM6DSM_SL1_DEC_4 = 2, 2918 LSM6DSM_SL1_DEC_8 = 3, 2919 } lsm6dsm_slave1_rate_t; 2920 int32_t lsm6dsm_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, 2921 lsm6dsm_slave1_rate_t val); 2922 int32_t lsm6dsm_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, 2923 lsm6dsm_slave1_rate_t *val); 2924 2925 typedef enum 2926 { 2927 LSM6DSM_SL2_NO_DEC = 0, 2928 LSM6DSM_SL2_DEC_2 = 1, 2929 LSM6DSM_SL2_DEC_4 = 2, 2930 LSM6DSM_SL2_DEC_8 = 3, 2931 } lsm6dsm_slave2_rate_t; 2932 int32_t lsm6dsm_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, 2933 lsm6dsm_slave2_rate_t val); 2934 int32_t lsm6dsm_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, 2935 lsm6dsm_slave2_rate_t *val); 2936 2937 typedef enum 2938 { 2939 LSM6DSM_SL3_NO_DEC = 0, 2940 LSM6DSM_SL3_DEC_2 = 1, 2941 LSM6DSM_SL3_DEC_4 = 2, 2942 LSM6DSM_SL3_DEC_8 = 3, 2943 } lsm6dsm_slave3_rate_t; 2944 int32_t lsm6dsm_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, 2945 lsm6dsm_slave3_rate_t val); 2946 int32_t lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, 2947 lsm6dsm_slave3_rate_t *val); 2948 2949 /** 2950 * @} 2951 * 2952 */ 2953 2954 #ifdef __cplusplus 2955 } 2956 #endif 2957 2958 #endif /* LSM6DSM_DRIVER_H */ 2959 2960 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2961
