1 /** 2 ****************************************************************************** 3 * @file lsm6dsl_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsl_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSL_REGS_H 23 #define LSM6DSL_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSL 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSL_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSL_I2C_ADD_L 0xD5U 173 #define LSM6DSL_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSL_ID 0x6AU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DSL_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 5; 188 uint8_t func_cfg_en : 189 3; /* func_cfg_en + func_cfg_en_b */ 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t func_cfg_en : 192 3; /* func_cfg_en + func_cfg_en_b */ 193 uint8_t not_used_01 : 5; 194 #endif /* DRV_BYTE_ORDER */ 195 } lsm6dsl_func_cfg_access_t; 196 197 #define LSM6DSL_SENSOR_SYNC_TIME_FRAME 0x04U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t tph : 4; 202 uint8_t not_used_01 : 4; 203 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 204 uint8_t not_used_01 : 4; 205 uint8_t tph : 4; 206 #endif /* DRV_BYTE_ORDER */ 207 } lsm6dsl_sensor_sync_time_frame_t; 208 209 #define LSM6DSL_SENSOR_SYNC_RES_RATIO 0x05U 210 typedef struct 211 { 212 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 213 uint8_t rr : 2; 214 uint8_t not_used_01 : 6; 215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 216 uint8_t not_used_01 : 6; 217 uint8_t rr : 2; 218 #endif /* DRV_BYTE_ORDER */ 219 } lsm6dsl_sensor_sync_res_ratio_t; 220 221 #define LSM6DSL_FIFO_CTRL1 0x06U 222 typedef struct 223 { 224 uint8_t fth : 8; /* + FIFO_CTRL2(fth) */ 225 } lsm6dsl_fifo_ctrl1_t; 226 227 #define LSM6DSL_FIFO_CTRL2 0x07U 228 typedef struct 229 { 230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 231 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 232 uint8_t fifo_temp_en : 1; 233 uint8_t not_used_01 : 2; 234 uint8_t timer_pedo_fifo_drdy : 1; 235 uint8_t timer_pedo_fifo_en : 1; 236 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 237 uint8_t timer_pedo_fifo_en : 1; 238 uint8_t timer_pedo_fifo_drdy : 1; 239 uint8_t not_used_01 : 2; 240 uint8_t fifo_temp_en : 1; 241 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 242 #endif /* DRV_BYTE_ORDER */ 243 } lsm6dsl_fifo_ctrl2_t; 244 245 #define LSM6DSL_FIFO_CTRL3 0x08U 246 typedef struct 247 { 248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 249 uint8_t dec_fifo_xl : 3; 250 uint8_t dec_fifo_gyro : 3; 251 uint8_t not_used_01 : 2; 252 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 253 uint8_t not_used_01 : 2; 254 uint8_t dec_fifo_gyro : 3; 255 uint8_t dec_fifo_xl : 3; 256 #endif /* DRV_BYTE_ORDER */ 257 } lsm6dsl_fifo_ctrl3_t; 258 259 #define LSM6DSL_FIFO_CTRL4 0x09U 260 typedef struct 261 { 262 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 263 uint8_t dec_ds3_fifo : 3; 264 uint8_t dec_ds4_fifo : 3; 265 uint8_t only_high_data : 1; 266 uint8_t stop_on_fth : 1; 267 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 268 uint8_t stop_on_fth : 1; 269 uint8_t only_high_data : 1; 270 uint8_t dec_ds4_fifo : 3; 271 uint8_t dec_ds3_fifo : 3; 272 #endif /* DRV_BYTE_ORDER */ 273 } lsm6dsl_fifo_ctrl4_t; 274 275 #define LSM6DSL_FIFO_CTRL5 0x0AU 276 typedef struct 277 { 278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 279 uint8_t fifo_mode : 3; 280 uint8_t odr_fifo : 4; 281 uint8_t not_used_01 : 1; 282 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 283 uint8_t not_used_01 : 1; 284 uint8_t odr_fifo : 4; 285 uint8_t fifo_mode : 3; 286 #endif /* DRV_BYTE_ORDER */ 287 } lsm6dsl_fifo_ctrl5_t; 288 289 #define LSM6DSL_DRDY_PULSE_CFG_G 0x0BU 290 typedef struct 291 { 292 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 293 uint8_t int2_wrist_tilt : 1; 294 uint8_t not_used_01 : 6; 295 uint8_t drdy_pulsed : 1; 296 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 297 uint8_t drdy_pulsed : 1; 298 uint8_t not_used_01 : 6; 299 uint8_t int2_wrist_tilt : 1; 300 #endif /* DRV_BYTE_ORDER */ 301 } lsm6dsl_drdy_pulse_cfg_g_t; 302 303 #define LSM6DSL_INT1_CTRL 0x0DU 304 typedef struct 305 { 306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 307 uint8_t int1_drdy_xl : 1; 308 uint8_t int1_drdy_g : 1; 309 uint8_t int1_boot : 1; 310 uint8_t int1_fth : 1; 311 uint8_t int1_fifo_ovr : 1; 312 uint8_t int1_full_flag : 1; 313 uint8_t int1_sign_mot : 1; 314 uint8_t int1_step_detector : 1; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t int1_step_detector : 1; 317 uint8_t int1_sign_mot : 1; 318 uint8_t int1_full_flag : 1; 319 uint8_t int1_fifo_ovr : 1; 320 uint8_t int1_fth : 1; 321 uint8_t int1_boot : 1; 322 uint8_t int1_drdy_g : 1; 323 uint8_t int1_drdy_xl : 1; 324 #endif /* DRV_BYTE_ORDER */ 325 } lsm6dsl_int1_ctrl_t; 326 327 #define LSM6DSL_INT2_CTRL 0x0EU 328 typedef struct 329 { 330 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 331 uint8_t int2_drdy_xl : 1; 332 uint8_t int2_drdy_g : 1; 333 uint8_t int2_drdy_temp : 1; 334 uint8_t int2_fth : 1; 335 uint8_t int2_fifo_ovr : 1; 336 uint8_t int2_full_flag : 1; 337 uint8_t int2_step_count_ov : 1; 338 uint8_t int2_step_delta : 1; 339 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 340 uint8_t int2_step_delta : 1; 341 uint8_t int2_step_count_ov : 1; 342 uint8_t int2_full_flag : 1; 343 uint8_t int2_fifo_ovr : 1; 344 uint8_t int2_fth : 1; 345 uint8_t int2_drdy_temp : 1; 346 uint8_t int2_drdy_g : 1; 347 uint8_t int2_drdy_xl : 1; 348 #endif /* DRV_BYTE_ORDER */ 349 } lsm6dsl_int2_ctrl_t; 350 351 #define LSM6DSL_WHO_AM_I 0x0FU 352 #define LSM6DSL_CTRL1_XL 0x10U 353 typedef struct 354 { 355 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 356 uint8_t bw0_xl : 1; 357 uint8_t lpf1_bw_sel : 1; 358 uint8_t fs_xl : 2; 359 uint8_t odr_xl : 4; 360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 361 uint8_t odr_xl : 4; 362 uint8_t fs_xl : 2; 363 uint8_t lpf1_bw_sel : 1; 364 uint8_t bw0_xl : 1; 365 #endif /* DRV_BYTE_ORDER */ 366 } lsm6dsl_ctrl1_xl_t; 367 368 #define LSM6DSL_CTRL2_G 0x11U 369 typedef struct 370 { 371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 372 uint8_t not_used_01 : 1; 373 uint8_t fs_g : 3; /* fs_g + fs_125 */ 374 uint8_t odr_g : 4; 375 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 376 uint8_t odr_g : 4; 377 uint8_t fs_g : 3; /* fs_g + fs_125 */ 378 uint8_t not_used_01 : 1; 379 #endif /* DRV_BYTE_ORDER */ 380 } lsm6dsl_ctrl2_g_t; 381 382 #define LSM6DSL_CTRL3_C 0x12U 383 typedef struct 384 { 385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 386 uint8_t sw_reset : 1; 387 uint8_t ble : 1; 388 uint8_t if_inc : 1; 389 uint8_t sim : 1; 390 uint8_t pp_od : 1; 391 uint8_t h_lactive : 1; 392 uint8_t bdu : 1; 393 uint8_t boot : 1; 394 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 395 uint8_t boot : 1; 396 uint8_t bdu : 1; 397 uint8_t h_lactive : 1; 398 uint8_t pp_od : 1; 399 uint8_t sim : 1; 400 uint8_t if_inc : 1; 401 uint8_t ble : 1; 402 uint8_t sw_reset : 1; 403 #endif /* DRV_BYTE_ORDER */ 404 } lsm6dsl_ctrl3_c_t; 405 406 #define LSM6DSL_CTRL4_C 0x13U 407 typedef struct 408 { 409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 410 uint8_t not_used_01 : 1; 411 uint8_t lpf1_sel_g : 1; 412 uint8_t i2c_disable : 1; 413 uint8_t drdy_mask : 1; 414 uint8_t den_drdy_int1 : 1; 415 uint8_t int2_on_int1 : 1; 416 uint8_t sleep : 1; 417 uint8_t den_xl_en : 1; 418 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 419 uint8_t den_xl_en : 1; 420 uint8_t sleep : 1; 421 uint8_t int2_on_int1 : 1; 422 uint8_t den_drdy_int1 : 1; 423 uint8_t drdy_mask : 1; 424 uint8_t i2c_disable : 1; 425 uint8_t lpf1_sel_g : 1; 426 uint8_t not_used_01 : 1; 427 #endif /* DRV_BYTE_ORDER */ 428 } lsm6dsl_ctrl4_c_t; 429 430 #define LSM6DSL_CTRL5_C 0x14U 431 typedef struct 432 { 433 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 434 uint8_t st_xl : 2; 435 uint8_t st_g : 2; 436 uint8_t den_lh : 1; 437 uint8_t rounding : 3; 438 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 439 uint8_t rounding : 3; 440 uint8_t den_lh : 1; 441 uint8_t st_g : 2; 442 uint8_t st_xl : 2; 443 #endif /* DRV_BYTE_ORDER */ 444 } lsm6dsl_ctrl5_c_t; 445 446 #define LSM6DSL_CTRL6_C 0x15U 447 typedef struct 448 { 449 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 450 uint8_t ftype : 2; 451 uint8_t not_used_01 : 1; 452 uint8_t usr_off_w : 1; 453 uint8_t xl_hm_mode : 1; 454 uint8_t den_mode : 455 3; /* trig_en + lvl_en + lvl2_en */ 456 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 457 uint8_t den_mode : 458 3; /* trig_en + lvl_en + lvl2_en */ 459 uint8_t xl_hm_mode : 1; 460 uint8_t usr_off_w : 1; 461 uint8_t not_used_01 : 1; 462 uint8_t ftype : 2; 463 #endif /* DRV_BYTE_ORDER */ 464 } lsm6dsl_ctrl6_c_t; 465 466 #define LSM6DSL_CTRL7_G 0x16U 467 typedef struct 468 { 469 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 470 uint8_t not_used_01 : 2; 471 uint8_t rounding_status : 1; 472 uint8_t not_used_02 : 1; 473 uint8_t hpm_g : 2; 474 uint8_t hp_en_g : 1; 475 uint8_t g_hm_mode : 1; 476 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 477 uint8_t g_hm_mode : 1; 478 uint8_t hp_en_g : 1; 479 uint8_t hpm_g : 2; 480 uint8_t not_used_02 : 1; 481 uint8_t rounding_status : 1; 482 uint8_t not_used_01 : 2; 483 #endif /* DRV_BYTE_ORDER */ 484 } lsm6dsl_ctrl7_g_t; 485 486 #define LSM6DSL_CTRL8_XL 0x17U 487 typedef struct 488 { 489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 490 uint8_t low_pass_on_6d : 1; 491 uint8_t not_used_01 : 1; 492 uint8_t hp_slope_xl_en : 1; 493 uint8_t input_composite : 1; 494 uint8_t hp_ref_mode : 1; 495 uint8_t hpcf_xl : 2; 496 uint8_t lpf2_xl_en : 1; 497 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 498 uint8_t lpf2_xl_en : 1; 499 uint8_t hpcf_xl : 2; 500 uint8_t hp_ref_mode : 1; 501 uint8_t input_composite : 1; 502 uint8_t hp_slope_xl_en : 1; 503 uint8_t not_used_01 : 1; 504 uint8_t low_pass_on_6d : 1; 505 #endif /* DRV_BYTE_ORDER */ 506 } lsm6dsl_ctrl8_xl_t; 507 508 #define LSM6DSL_CTRL9_XL 0x18U 509 typedef struct 510 { 511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 512 uint8_t not_used_01 : 2; 513 uint8_t soft_en : 1; 514 uint8_t not_used_02 : 1; 515 uint8_t den_xl_g : 1; 516 uint8_t den_z : 1; 517 uint8_t den_y : 1; 518 uint8_t den_x : 1; 519 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 520 uint8_t den_x : 1; 521 uint8_t den_y : 1; 522 uint8_t den_z : 1; 523 uint8_t den_xl_g : 1; 524 uint8_t not_used_02 : 1; 525 uint8_t soft_en : 1; 526 uint8_t not_used_01 : 2; 527 #endif /* DRV_BYTE_ORDER */ 528 } lsm6dsl_ctrl9_xl_t; 529 530 #define LSM6DSL_CTRL10_C 0x19U 531 typedef struct 532 { 533 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 534 uint8_t sign_motion_en : 1; 535 uint8_t pedo_rst_step : 1; 536 uint8_t func_en : 1; 537 uint8_t tilt_en : 1; 538 uint8_t pedo_en : 1; 539 uint8_t timer_en : 1; 540 uint8_t not_used_01 : 1; 541 uint8_t wrist_tilt_en : 1; 542 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 543 uint8_t wrist_tilt_en : 1; 544 uint8_t not_used_01 : 1; 545 uint8_t timer_en : 1; 546 uint8_t pedo_en : 1; 547 uint8_t tilt_en : 1; 548 uint8_t func_en : 1; 549 uint8_t pedo_rst_step : 1; 550 uint8_t sign_motion_en : 1; 551 #endif /* DRV_BYTE_ORDER */ 552 } lsm6dsl_ctrl10_c_t; 553 554 #define LSM6DSL_MASTER_CONFIG 0x1AU 555 typedef struct 556 { 557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 558 uint8_t master_on : 1; 559 uint8_t iron_en : 1; 560 uint8_t pass_through_mode : 1; 561 uint8_t pull_up_en : 1; 562 uint8_t start_config : 1; 563 uint8_t not_used_01 : 1; 564 uint8_t data_valid_sel_fifo : 1; 565 uint8_t drdy_on_int1 : 1; 566 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 567 uint8_t drdy_on_int1 : 1; 568 uint8_t data_valid_sel_fifo : 1; 569 uint8_t not_used_01 : 1; 570 uint8_t start_config : 1; 571 uint8_t pull_up_en : 1; 572 uint8_t pass_through_mode : 1; 573 uint8_t iron_en : 1; 574 uint8_t master_on : 1; 575 #endif /* DRV_BYTE_ORDER */ 576 } lsm6dsl_master_config_t; 577 578 #define LSM6DSL_WAKE_UP_SRC 0x1BU 579 typedef struct 580 { 581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 582 uint8_t z_wu : 1; 583 uint8_t y_wu : 1; 584 uint8_t x_wu : 1; 585 uint8_t wu_ia : 1; 586 uint8_t sleep_state_ia : 1; 587 uint8_t ff_ia : 1; 588 uint8_t not_used_01 : 2; 589 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 590 uint8_t not_used_01 : 2; 591 uint8_t ff_ia : 1; 592 uint8_t sleep_state_ia : 1; 593 uint8_t wu_ia : 1; 594 uint8_t x_wu : 1; 595 uint8_t y_wu : 1; 596 uint8_t z_wu : 1; 597 #endif /* DRV_BYTE_ORDER */ 598 } lsm6dsl_wake_up_src_t; 599 600 #define LSM6DSL_TAP_SRC 0x1CU 601 typedef struct 602 { 603 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 604 uint8_t z_tap : 1; 605 uint8_t y_tap : 1; 606 uint8_t x_tap : 1; 607 uint8_t tap_sign : 1; 608 uint8_t double_tap : 1; 609 uint8_t single_tap : 1; 610 uint8_t tap_ia : 1; 611 uint8_t not_used_01 : 1; 612 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 613 uint8_t not_used_01 : 1; 614 uint8_t tap_ia : 1; 615 uint8_t single_tap : 1; 616 uint8_t double_tap : 1; 617 uint8_t tap_sign : 1; 618 uint8_t x_tap : 1; 619 uint8_t y_tap : 1; 620 uint8_t z_tap : 1; 621 #endif /* DRV_BYTE_ORDER */ 622 } lsm6dsl_tap_src_t; 623 624 #define LSM6DSL_D6D_SRC 0x1DU 625 typedef struct 626 { 627 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 628 uint8_t xl : 1; 629 uint8_t xh : 1; 630 uint8_t yl : 1; 631 uint8_t yh : 1; 632 uint8_t zl : 1; 633 uint8_t zh : 1; 634 uint8_t d6d_ia : 1; 635 uint8_t den_drdy : 1; 636 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 637 uint8_t den_drdy : 1; 638 uint8_t d6d_ia : 1; 639 uint8_t zh : 1; 640 uint8_t zl : 1; 641 uint8_t yh : 1; 642 uint8_t yl : 1; 643 uint8_t xh : 1; 644 uint8_t xl : 1; 645 #endif /* DRV_BYTE_ORDER */ 646 } lsm6dsl_d6d_src_t; 647 648 #define LSM6DSL_STATUS_REG 0x1EU 649 typedef struct 650 { 651 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 652 uint8_t xlda : 1; 653 uint8_t gda : 1; 654 uint8_t tda : 1; 655 uint8_t not_used_01 : 5; 656 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 657 uint8_t not_used_01 : 5; 658 uint8_t tda : 1; 659 uint8_t gda : 1; 660 uint8_t xlda : 1; 661 #endif /* DRV_BYTE_ORDER */ 662 } lsm6dsl_status_reg_t; 663 664 #define LSM6DSL_OUT_TEMP_L 0x20U 665 #define LSM6DSL_OUT_TEMP_H 0x21U 666 #define LSM6DSL_OUTX_L_G 0x22U 667 #define LSM6DSL_OUTX_H_G 0x23U 668 #define LSM6DSL_OUTY_L_G 0x24U 669 #define LSM6DSL_OUTY_H_G 0x25U 670 #define LSM6DSL_OUTZ_L_G 0x26U 671 #define LSM6DSL_OUTZ_H_G 0x27U 672 #define LSM6DSL_OUTX_L_XL 0x28U 673 #define LSM6DSL_OUTX_H_XL 0x29U 674 #define LSM6DSL_OUTY_L_XL 0x2AU 675 #define LSM6DSL_OUTY_H_XL 0x2BU 676 #define LSM6DSL_OUTZ_L_XL 0x2CU 677 #define LSM6DSL_OUTZ_H_XL 0x2DU 678 #define LSM6DSL_SENSORHUB1_REG 0x2EU 679 typedef struct 680 { 681 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 682 uint8_t bit0 : 1; 683 uint8_t bit1 : 1; 684 uint8_t bit2 : 1; 685 uint8_t bit3 : 1; 686 uint8_t bit4 : 1; 687 uint8_t bit5 : 1; 688 uint8_t bit6 : 1; 689 uint8_t bit7 : 1; 690 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 691 uint8_t bit7 : 1; 692 uint8_t bit6 : 1; 693 uint8_t bit5 : 1; 694 uint8_t bit4 : 1; 695 uint8_t bit3 : 1; 696 uint8_t bit2 : 1; 697 uint8_t bit1 : 1; 698 uint8_t bit0 : 1; 699 #endif /* DRV_BYTE_ORDER */ 700 } lsm6dsl_sensorhub1_reg_t; 701 702 #define LSM6DSL_SENSORHUB2_REG 0x2FU 703 typedef struct 704 { 705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 706 uint8_t bit0 : 1; 707 uint8_t bit1 : 1; 708 uint8_t bit2 : 1; 709 uint8_t bit3 : 1; 710 uint8_t bit4 : 1; 711 uint8_t bit5 : 1; 712 uint8_t bit6 : 1; 713 uint8_t bit7 : 1; 714 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 715 uint8_t bit7 : 1; 716 uint8_t bit6 : 1; 717 uint8_t bit5 : 1; 718 uint8_t bit4 : 1; 719 uint8_t bit3 : 1; 720 uint8_t bit2 : 1; 721 uint8_t bit1 : 1; 722 uint8_t bit0 : 1; 723 #endif /* DRV_BYTE_ORDER */ 724 } lsm6dsl_sensorhub2_reg_t; 725 726 #define LSM6DSL_SENSORHUB3_REG 0x30U 727 typedef struct 728 { 729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 730 uint8_t bit0 : 1; 731 uint8_t bit1 : 1; 732 uint8_t bit2 : 1; 733 uint8_t bit3 : 1; 734 uint8_t bit4 : 1; 735 uint8_t bit5 : 1; 736 uint8_t bit6 : 1; 737 uint8_t bit7 : 1; 738 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 739 uint8_t bit7 : 1; 740 uint8_t bit6 : 1; 741 uint8_t bit5 : 1; 742 uint8_t bit4 : 1; 743 uint8_t bit3 : 1; 744 uint8_t bit2 : 1; 745 uint8_t bit1 : 1; 746 uint8_t bit0 : 1; 747 #endif /* DRV_BYTE_ORDER */ 748 } lsm6dsl_sensorhub3_reg_t; 749 750 #define LSM6DSL_SENSORHUB4_REG 0x31U 751 typedef struct 752 { 753 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 754 uint8_t bit0 : 1; 755 uint8_t bit1 : 1; 756 uint8_t bit2 : 1; 757 uint8_t bit3 : 1; 758 uint8_t bit4 : 1; 759 uint8_t bit5 : 1; 760 uint8_t bit6 : 1; 761 uint8_t bit7 : 1; 762 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 763 uint8_t bit7 : 1; 764 uint8_t bit6 : 1; 765 uint8_t bit5 : 1; 766 uint8_t bit4 : 1; 767 uint8_t bit3 : 1; 768 uint8_t bit2 : 1; 769 uint8_t bit1 : 1; 770 uint8_t bit0 : 1; 771 #endif /* DRV_BYTE_ORDER */ 772 } lsm6dsl_sensorhub4_reg_t; 773 774 #define LSM6DSL_SENSORHUB5_REG 0x32U 775 typedef struct 776 { 777 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 778 uint8_t bit0 : 1; 779 uint8_t bit1 : 1; 780 uint8_t bit2 : 1; 781 uint8_t bit3 : 1; 782 uint8_t bit4 : 1; 783 uint8_t bit5 : 1; 784 uint8_t bit6 : 1; 785 uint8_t bit7 : 1; 786 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 787 uint8_t bit7 : 1; 788 uint8_t bit6 : 1; 789 uint8_t bit5 : 1; 790 uint8_t bit4 : 1; 791 uint8_t bit3 : 1; 792 uint8_t bit2 : 1; 793 uint8_t bit1 : 1; 794 uint8_t bit0 : 1; 795 #endif /* DRV_BYTE_ORDER */ 796 } lsm6dsl_sensorhub5_reg_t; 797 798 #define LSM6DSL_SENSORHUB6_REG 0x33U 799 typedef struct 800 { 801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 802 uint8_t bit0 : 1; 803 uint8_t bit1 : 1; 804 uint8_t bit2 : 1; 805 uint8_t bit3 : 1; 806 uint8_t bit4 : 1; 807 uint8_t bit5 : 1; 808 uint8_t bit6 : 1; 809 uint8_t bit7 : 1; 810 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 811 uint8_t bit7 : 1; 812 uint8_t bit6 : 1; 813 uint8_t bit5 : 1; 814 uint8_t bit4 : 1; 815 uint8_t bit3 : 1; 816 uint8_t bit2 : 1; 817 uint8_t bit1 : 1; 818 uint8_t bit0 : 1; 819 #endif /* DRV_BYTE_ORDER */ 820 } lsm6dsl_sensorhub6_reg_t; 821 822 #define LSM6DSL_SENSORHUB7_REG 0x34U 823 typedef struct 824 { 825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 826 uint8_t bit0 : 1; 827 uint8_t bit1 : 1; 828 uint8_t bit2 : 1; 829 uint8_t bit3 : 1; 830 uint8_t bit4 : 1; 831 uint8_t bit5 : 1; 832 uint8_t bit6 : 1; 833 uint8_t bit7 : 1; 834 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 835 uint8_t bit7 : 1; 836 uint8_t bit6 : 1; 837 uint8_t bit5 : 1; 838 uint8_t bit4 : 1; 839 uint8_t bit3 : 1; 840 uint8_t bit2 : 1; 841 uint8_t bit1 : 1; 842 uint8_t bit0 : 1; 843 #endif /* DRV_BYTE_ORDER */ 844 } lsm6dsl_sensorhub7_reg_t; 845 846 #define LSM6DSL_SENSORHUB8_REG 0x35U 847 typedef struct 848 { 849 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 850 uint8_t bit0 : 1; 851 uint8_t bit1 : 1; 852 uint8_t bit2 : 1; 853 uint8_t bit3 : 1; 854 uint8_t bit4 : 1; 855 uint8_t bit5 : 1; 856 uint8_t bit6 : 1; 857 uint8_t bit7 : 1; 858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 859 uint8_t bit7 : 1; 860 uint8_t bit6 : 1; 861 uint8_t bit5 : 1; 862 uint8_t bit4 : 1; 863 uint8_t bit3 : 1; 864 uint8_t bit2 : 1; 865 uint8_t bit1 : 1; 866 uint8_t bit0 : 1; 867 #endif /* DRV_BYTE_ORDER */ 868 } lsm6dsl_sensorhub8_reg_t; 869 870 #define LSM6DSL_SENSORHUB9_REG 0x36U 871 typedef struct 872 { 873 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 874 uint8_t bit0 : 1; 875 uint8_t bit1 : 1; 876 uint8_t bit2 : 1; 877 uint8_t bit3 : 1; 878 uint8_t bit4 : 1; 879 uint8_t bit5 : 1; 880 uint8_t bit6 : 1; 881 uint8_t bit7 : 1; 882 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 883 uint8_t bit7 : 1; 884 uint8_t bit6 : 1; 885 uint8_t bit5 : 1; 886 uint8_t bit4 : 1; 887 uint8_t bit3 : 1; 888 uint8_t bit2 : 1; 889 uint8_t bit1 : 1; 890 uint8_t bit0 : 1; 891 #endif /* DRV_BYTE_ORDER */ 892 } lsm6dsl_sensorhub9_reg_t; 893 894 #define LSM6DSL_SENSORHUB10_REG 0x37U 895 typedef struct 896 { 897 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 898 uint8_t bit0 : 1; 899 uint8_t bit1 : 1; 900 uint8_t bit2 : 1; 901 uint8_t bit3 : 1; 902 uint8_t bit4 : 1; 903 uint8_t bit5 : 1; 904 uint8_t bit6 : 1; 905 uint8_t bit7 : 1; 906 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 907 uint8_t bit7 : 1; 908 uint8_t bit6 : 1; 909 uint8_t bit5 : 1; 910 uint8_t bit4 : 1; 911 uint8_t bit3 : 1; 912 uint8_t bit2 : 1; 913 uint8_t bit1 : 1; 914 uint8_t bit0 : 1; 915 #endif /* DRV_BYTE_ORDER */ 916 } lsm6dsl_sensorhub10_reg_t; 917 918 #define LSM6DSL_SENSORHUB11_REG 0x38U 919 typedef struct 920 { 921 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 922 uint8_t bit0 : 1; 923 uint8_t bit1 : 1; 924 uint8_t bit2 : 1; 925 uint8_t bit3 : 1; 926 uint8_t bit4 : 1; 927 uint8_t bit5 : 1; 928 uint8_t bit6 : 1; 929 uint8_t bit7 : 1; 930 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 931 uint8_t bit7 : 1; 932 uint8_t bit6 : 1; 933 uint8_t bit5 : 1; 934 uint8_t bit4 : 1; 935 uint8_t bit3 : 1; 936 uint8_t bit2 : 1; 937 uint8_t bit1 : 1; 938 uint8_t bit0 : 1; 939 #endif /* DRV_BYTE_ORDER */ 940 } lsm6dsl_sensorhub11_reg_t; 941 942 #define LSM6DSL_SENSORHUB12_REG 0x39U 943 typedef struct 944 { 945 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 946 uint8_t bit0 : 1; 947 uint8_t bit1 : 1; 948 uint8_t bit2 : 1; 949 uint8_t bit3 : 1; 950 uint8_t bit4 : 1; 951 uint8_t bit5 : 1; 952 uint8_t bit6 : 1; 953 uint8_t bit7 : 1; 954 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 955 uint8_t bit7 : 1; 956 uint8_t bit6 : 1; 957 uint8_t bit5 : 1; 958 uint8_t bit4 : 1; 959 uint8_t bit3 : 1; 960 uint8_t bit2 : 1; 961 uint8_t bit1 : 1; 962 uint8_t bit0 : 1; 963 #endif /* DRV_BYTE_ORDER */ 964 } lsm6dsl_sensorhub12_reg_t; 965 966 #define LSM6DSL_FIFO_STATUS1 0x3AU 967 typedef struct 968 { 969 uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */ 970 } lsm6dsl_fifo_status1_t; 971 972 #define LSM6DSL_FIFO_STATUS2 0x3BU 973 typedef struct 974 { 975 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 976 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 977 uint8_t not_used_01 : 1; 978 uint8_t fifo_empty : 1; 979 uint8_t fifo_full_smart : 1; 980 uint8_t over_run : 1; 981 uint8_t waterm : 1; 982 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 983 uint8_t waterm : 1; 984 uint8_t over_run : 1; 985 uint8_t fifo_full_smart : 1; 986 uint8_t fifo_empty : 1; 987 uint8_t not_used_01 : 1; 988 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 989 #endif /* DRV_BYTE_ORDER */ 990 } lsm6dsl_fifo_status2_t; 991 992 #define LSM6DSL_FIFO_STATUS3 0x3CU 993 typedef struct 994 { 995 uint8_t fifo_pattern : 996 8; /* + FIFO_STATUS4(fifo_pattern) */ 997 } lsm6dsl_fifo_status3_t; 998 999 #define LSM6DSL_FIFO_STATUS4 0x3DU 1000 typedef struct 1001 { 1002 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1003 uint8_t fifo_pattern : 1004 2; /* + FIFO_STATUS3(fifo_pattern) */ 1005 uint8_t not_used_01 : 6; 1006 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1007 uint8_t not_used_01 : 6; 1008 uint8_t fifo_pattern : 1009 2; /* + FIFO_STATUS3(fifo_pattern) */ 1010 #endif /* DRV_BYTE_ORDER */ 1011 } lsm6dsl_fifo_status4_t; 1012 1013 #define LSM6DSL_FIFO_DATA_OUT_L 0x3EU 1014 #define LSM6DSL_FIFO_DATA_OUT_H 0x3FU 1015 #define LSM6DSL_TIMESTAMP0_REG 0x40U 1016 #define LSM6DSL_TIMESTAMP1_REG 0x41U 1017 #define LSM6DSL_TIMESTAMP2_REG 0x42U 1018 #define LSM6DSL_STEP_TIMESTAMP_L 0x49U 1019 #define LSM6DSL_STEP_TIMESTAMP_H 0x4AU 1020 #define LSM6DSL_STEP_COUNTER_L 0x4BU 1021 #define LSM6DSL_STEP_COUNTER_H 0x4CU 1022 1023 #define LSM6DSL_SENSORHUB13_REG 0x4DU 1024 typedef struct 1025 { 1026 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1027 uint8_t bit0 : 1; 1028 uint8_t bit1 : 1; 1029 uint8_t bit2 : 1; 1030 uint8_t bit3 : 1; 1031 uint8_t bit4 : 1; 1032 uint8_t bit5 : 1; 1033 uint8_t bit6 : 1; 1034 uint8_t bit7 : 1; 1035 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1036 uint8_t bit7 : 1; 1037 uint8_t bit6 : 1; 1038 uint8_t bit5 : 1; 1039 uint8_t bit4 : 1; 1040 uint8_t bit3 : 1; 1041 uint8_t bit2 : 1; 1042 uint8_t bit1 : 1; 1043 uint8_t bit0 : 1; 1044 #endif /* DRV_BYTE_ORDER */ 1045 } lsm6dsl_sensorhub13_reg_t; 1046 1047 #define LSM6DSL_SENSORHUB14_REG 0x4EU 1048 typedef struct 1049 { 1050 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1051 uint8_t bit0 : 1; 1052 uint8_t bit1 : 1; 1053 uint8_t bit2 : 1; 1054 uint8_t bit3 : 1; 1055 uint8_t bit4 : 1; 1056 uint8_t bit5 : 1; 1057 uint8_t bit6 : 1; 1058 uint8_t bit7 : 1; 1059 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1060 uint8_t bit7 : 1; 1061 uint8_t bit6 : 1; 1062 uint8_t bit5 : 1; 1063 uint8_t bit4 : 1; 1064 uint8_t bit3 : 1; 1065 uint8_t bit2 : 1; 1066 uint8_t bit1 : 1; 1067 uint8_t bit0 : 1; 1068 #endif /* DRV_BYTE_ORDER */ 1069 } lsm6dsl_sensorhub14_reg_t; 1070 1071 #define LSM6DSL_SENSORHUB15_REG 0x4FU 1072 typedef struct 1073 { 1074 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1075 uint8_t bit0 : 1; 1076 uint8_t bit1 : 1; 1077 uint8_t bit2 : 1; 1078 uint8_t bit3 : 1; 1079 uint8_t bit4 : 1; 1080 uint8_t bit5 : 1; 1081 uint8_t bit6 : 1; 1082 uint8_t bit7 : 1; 1083 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1084 uint8_t bit7 : 1; 1085 uint8_t bit6 : 1; 1086 uint8_t bit5 : 1; 1087 uint8_t bit4 : 1; 1088 uint8_t bit3 : 1; 1089 uint8_t bit2 : 1; 1090 uint8_t bit1 : 1; 1091 uint8_t bit0 : 1; 1092 #endif /* DRV_BYTE_ORDER */ 1093 } lsm6dsl_sensorhub15_reg_t; 1094 1095 #define LSM6DSL_SENSORHUB16_REG 0x50U 1096 typedef struct 1097 { 1098 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1099 uint8_t bit0 : 1; 1100 uint8_t bit1 : 1; 1101 uint8_t bit2 : 1; 1102 uint8_t bit3 : 1; 1103 uint8_t bit4 : 1; 1104 uint8_t bit5 : 1; 1105 uint8_t bit6 : 1; 1106 uint8_t bit7 : 1; 1107 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1108 uint8_t bit7 : 1; 1109 uint8_t bit6 : 1; 1110 uint8_t bit5 : 1; 1111 uint8_t bit4 : 1; 1112 uint8_t bit3 : 1; 1113 uint8_t bit2 : 1; 1114 uint8_t bit1 : 1; 1115 uint8_t bit0 : 1; 1116 #endif /* DRV_BYTE_ORDER */ 1117 } lsm6dsl_sensorhub16_reg_t; 1118 1119 #define LSM6DSL_SENSORHUB17_REG 0x51U 1120 typedef struct 1121 { 1122 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1123 uint8_t bit0 : 1; 1124 uint8_t bit1 : 1; 1125 uint8_t bit2 : 1; 1126 uint8_t bit3 : 1; 1127 uint8_t bit4 : 1; 1128 uint8_t bit5 : 1; 1129 uint8_t bit6 : 1; 1130 uint8_t bit7 : 1; 1131 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1132 uint8_t bit7 : 1; 1133 uint8_t bit6 : 1; 1134 uint8_t bit5 : 1; 1135 uint8_t bit4 : 1; 1136 uint8_t bit3 : 1; 1137 uint8_t bit2 : 1; 1138 uint8_t bit1 : 1; 1139 uint8_t bit0 : 1; 1140 #endif /* DRV_BYTE_ORDER */ 1141 } lsm6dsl_sensorhub17_reg_t; 1142 1143 #define LSM6DSL_SENSORHUB18_REG 0x52U 1144 typedef struct 1145 { 1146 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1147 uint8_t bit0 : 1; 1148 uint8_t bit1 : 1; 1149 uint8_t bit2 : 1; 1150 uint8_t bit3 : 1; 1151 uint8_t bit4 : 1; 1152 uint8_t bit5 : 1; 1153 uint8_t bit6 : 1; 1154 uint8_t bit7 : 1; 1155 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1156 uint8_t bit7 : 1; 1157 uint8_t bit6 : 1; 1158 uint8_t bit5 : 1; 1159 uint8_t bit4 : 1; 1160 uint8_t bit3 : 1; 1161 uint8_t bit2 : 1; 1162 uint8_t bit1 : 1; 1163 uint8_t bit0 : 1; 1164 #endif /* DRV_BYTE_ORDER */ 1165 } lsm6dsl_sensorhub18_reg_t; 1166 1167 #define LSM6DSL_FUNC_SRC1 0x53U 1168 typedef struct 1169 { 1170 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1171 uint8_t sensorhub_end_op : 1; 1172 uint8_t si_end_op : 1; 1173 uint8_t hi_fail : 1; 1174 uint8_t step_overflow : 1; 1175 uint8_t step_detected : 1; 1176 uint8_t tilt_ia : 1; 1177 uint8_t sign_motion_ia : 1; 1178 uint8_t step_count_delta_ia : 1; 1179 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1180 uint8_t step_count_delta_ia : 1; 1181 uint8_t sign_motion_ia : 1; 1182 uint8_t tilt_ia : 1; 1183 uint8_t step_detected : 1; 1184 uint8_t step_overflow : 1; 1185 uint8_t hi_fail : 1; 1186 uint8_t si_end_op : 1; 1187 uint8_t sensorhub_end_op : 1; 1188 #endif /* DRV_BYTE_ORDER */ 1189 } lsm6dsl_func_src1_t; 1190 1191 #define LSM6DSL_FUNC_SRC2 0x54U 1192 typedef struct 1193 { 1194 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1195 uint8_t wrist_tilt_ia : 1; 1196 uint8_t not_used_01 : 2; 1197 uint8_t slave0_nack : 1; 1198 uint8_t slave1_nack : 1; 1199 uint8_t slave2_nack : 1; 1200 uint8_t slave3_nack : 1; 1201 uint8_t not_used_02 : 1; 1202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1203 uint8_t not_used_02 : 1; 1204 uint8_t slave3_nack : 1; 1205 uint8_t slave2_nack : 1; 1206 uint8_t slave1_nack : 1; 1207 uint8_t slave0_nack : 1; 1208 uint8_t not_used_01 : 2; 1209 uint8_t wrist_tilt_ia : 1; 1210 #endif /* DRV_BYTE_ORDER */ 1211 } lsm6dsl_func_src2_t; 1212 1213 #define LSM6DSL_WRIST_TILT_IA 0x55U 1214 typedef struct 1215 { 1216 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1217 uint8_t not_used_01 : 2; 1218 uint8_t wrist_tilt_ia_zneg : 1; 1219 uint8_t wrist_tilt_ia_zpos : 1; 1220 uint8_t wrist_tilt_ia_yneg : 1; 1221 uint8_t wrist_tilt_ia_ypos : 1; 1222 uint8_t wrist_tilt_ia_xneg : 1; 1223 uint8_t wrist_tilt_ia_xpos : 1; 1224 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1225 uint8_t wrist_tilt_ia_xpos : 1; 1226 uint8_t wrist_tilt_ia_xneg : 1; 1227 uint8_t wrist_tilt_ia_ypos : 1; 1228 uint8_t wrist_tilt_ia_yneg : 1; 1229 uint8_t wrist_tilt_ia_zpos : 1; 1230 uint8_t wrist_tilt_ia_zneg : 1; 1231 uint8_t not_used_01 : 2; 1232 #endif /* DRV_BYTE_ORDER */ 1233 } lsm6dsl_wrist_tilt_ia_t; 1234 1235 #define LSM6DSL_TAP_CFG 0x58U 1236 typedef struct 1237 { 1238 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1239 uint8_t lir : 1; 1240 uint8_t tap_z_en : 1; 1241 uint8_t tap_y_en : 1; 1242 uint8_t tap_x_en : 1; 1243 uint8_t slope_fds : 1; 1244 uint8_t inact_en : 2; 1245 uint8_t interrupts_enable : 1; 1246 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1247 uint8_t interrupts_enable : 1; 1248 uint8_t inact_en : 2; 1249 uint8_t slope_fds : 1; 1250 uint8_t tap_x_en : 1; 1251 uint8_t tap_y_en : 1; 1252 uint8_t tap_z_en : 1; 1253 uint8_t lir : 1; 1254 #endif /* DRV_BYTE_ORDER */ 1255 } lsm6dsl_tap_cfg_t; 1256 1257 #define LSM6DSL_TAP_THS_6D 0x59U 1258 typedef struct 1259 { 1260 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1261 uint8_t tap_ths : 5; 1262 uint8_t sixd_ths : 2; 1263 uint8_t d4d_en : 1; 1264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1265 uint8_t d4d_en : 1; 1266 uint8_t sixd_ths : 2; 1267 uint8_t tap_ths : 5; 1268 #endif /* DRV_BYTE_ORDER */ 1269 } lsm6dsl_tap_ths_6d_t; 1270 1271 #define LSM6DSL_INT_DUR2 0x5AU 1272 typedef struct 1273 { 1274 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1275 uint8_t shock : 2; 1276 uint8_t quiet : 2; 1277 uint8_t dur : 4; 1278 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1279 uint8_t dur : 4; 1280 uint8_t quiet : 2; 1281 uint8_t shock : 2; 1282 #endif /* DRV_BYTE_ORDER */ 1283 } lsm6dsl_int_dur2_t; 1284 1285 #define LSM6DSL_WAKE_UP_THS 0x5BU 1286 typedef struct 1287 { 1288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1289 uint8_t wk_ths : 6; 1290 uint8_t not_used_01 : 1; 1291 uint8_t single_double_tap : 1; 1292 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1293 uint8_t single_double_tap : 1; 1294 uint8_t not_used_01 : 1; 1295 uint8_t wk_ths : 6; 1296 #endif /* DRV_BYTE_ORDER */ 1297 } lsm6dsl_wake_up_ths_t; 1298 1299 #define LSM6DSL_WAKE_UP_DUR 0x5CU 1300 typedef struct 1301 { 1302 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1303 uint8_t sleep_dur : 4; 1304 uint8_t timer_hr : 1; 1305 uint8_t wake_dur : 2; 1306 uint8_t ff_dur : 1; 1307 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1308 uint8_t ff_dur : 1; 1309 uint8_t wake_dur : 2; 1310 uint8_t timer_hr : 1; 1311 uint8_t sleep_dur : 4; 1312 #endif /* DRV_BYTE_ORDER */ 1313 } lsm6dsl_wake_up_dur_t; 1314 1315 #define LSM6DSL_FREE_FALL 0x5DU 1316 typedef struct 1317 { 1318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1319 uint8_t ff_ths : 3; 1320 uint8_t ff_dur : 5; 1321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1322 uint8_t ff_dur : 5; 1323 uint8_t ff_ths : 3; 1324 #endif /* DRV_BYTE_ORDER */ 1325 } lsm6dsl_free_fall_t; 1326 1327 #define LSM6DSL_MD1_CFG 0x5EU 1328 typedef struct 1329 { 1330 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1331 uint8_t int1_timer : 1; 1332 uint8_t int1_tilt : 1; 1333 uint8_t int1_6d : 1; 1334 uint8_t int1_double_tap : 1; 1335 uint8_t int1_ff : 1; 1336 uint8_t int1_wu : 1; 1337 uint8_t int1_single_tap : 1; 1338 uint8_t int1_inact_state : 1; 1339 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1340 uint8_t int1_inact_state : 1; 1341 uint8_t int1_single_tap : 1; 1342 uint8_t int1_wu : 1; 1343 uint8_t int1_ff : 1; 1344 uint8_t int1_double_tap : 1; 1345 uint8_t int1_6d : 1; 1346 uint8_t int1_tilt : 1; 1347 uint8_t int1_timer : 1; 1348 #endif /* DRV_BYTE_ORDER */ 1349 } lsm6dsl_md1_cfg_t; 1350 1351 #define LSM6DSL_MD2_CFG 0x5FU 1352 typedef struct 1353 { 1354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1355 uint8_t int2_iron : 1; 1356 uint8_t int2_tilt : 1; 1357 uint8_t int2_6d : 1; 1358 uint8_t int2_double_tap : 1; 1359 uint8_t int2_ff : 1; 1360 uint8_t int2_wu : 1; 1361 uint8_t int2_single_tap : 1; 1362 uint8_t int2_inact_state : 1; 1363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1364 uint8_t int2_inact_state : 1; 1365 uint8_t int2_single_tap : 1; 1366 uint8_t int2_wu : 1; 1367 uint8_t int2_ff : 1; 1368 uint8_t int2_double_tap : 1; 1369 uint8_t int2_6d : 1; 1370 uint8_t int2_tilt : 1; 1371 uint8_t int2_iron : 1; 1372 #endif /* DRV_BYTE_ORDER */ 1373 } lsm6dsl_md2_cfg_t; 1374 1375 #define LSM6DSL_MASTER_CMD_CODE 0x60U 1376 typedef struct 1377 { 1378 uint8_t master_cmd_code : 8; 1379 } lsm6dsl_master_cmd_code_t; 1380 1381 #define LSM6DSL_SENS_SYNC_SPI_ERROR_CODE 0x61U 1382 typedef struct 1383 { 1384 uint8_t error_code : 8; 1385 } lsm6dsl_sens_sync_spi_error_code_t; 1386 1387 #define LSM6DSL_OUT_MAG_RAW_X_L 0x66U 1388 #define LSM6DSL_OUT_MAG_RAW_X_H 0x67U 1389 #define LSM6DSL_OUT_MAG_RAW_Y_L 0x68U 1390 #define LSM6DSL_OUT_MAG_RAW_Y_H 0x69U 1391 #define LSM6DSL_OUT_MAG_RAW_Z_L 0x6AU 1392 #define LSM6DSL_OUT_MAG_RAW_Z_H 0x6BU 1393 #define LSM6DSL_X_OFS_USR 0x73U 1394 #define LSM6DSL_Y_OFS_USR 0x74U 1395 #define LSM6DSL_Z_OFS_USR 0x75U 1396 #define LSM6DSL_SLV0_ADD 0x02U 1397 typedef struct 1398 { 1399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1400 uint8_t rw_0 : 1; 1401 uint8_t slave0_add : 7; 1402 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1403 uint8_t slave0_add : 7; 1404 uint8_t rw_0 : 1; 1405 #endif /* DRV_BYTE_ORDER */ 1406 } lsm6dsl_slv0_add_t; 1407 1408 #define LSM6DSL_SLV0_SUBADD 0x03U 1409 typedef struct 1410 { 1411 uint8_t slave0_reg : 8; 1412 } lsm6dsl_slv0_subadd_t; 1413 1414 #define LSM6DSL_SLAVE0_CONFIG 0x04U 1415 typedef struct 1416 { 1417 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1418 uint8_t slave0_numop : 3; 1419 uint8_t src_mode : 1; 1420 uint8_t aux_sens_on : 2; 1421 uint8_t slave0_rate : 2; 1422 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1423 uint8_t slave0_rate : 2; 1424 uint8_t aux_sens_on : 2; 1425 uint8_t src_mode : 1; 1426 uint8_t slave0_numop : 3; 1427 #endif /* DRV_BYTE_ORDER */ 1428 } lsm6dsl_slave0_config_t; 1429 1430 #define LSM6DSL_SLV1_ADD 0x05U 1431 typedef struct 1432 { 1433 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1434 uint8_t r_1 : 1; 1435 uint8_t slave1_add : 7; 1436 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1437 uint8_t slave1_add : 7; 1438 uint8_t r_1 : 1; 1439 #endif /* DRV_BYTE_ORDER */ 1440 } lsm6dsl_slv1_add_t; 1441 1442 #define LSM6DSL_SLV1_SUBADD 0x06U 1443 typedef struct 1444 { 1445 uint8_t slave1_reg : 8; 1446 } lsm6dsl_slv1_subadd_t; 1447 1448 #define LSM6DSL_SLAVE1_CONFIG 0x07U 1449 typedef struct 1450 { 1451 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1452 uint8_t slave1_numop : 3; 1453 uint8_t not_used_01 : 2; 1454 uint8_t write_once : 1; 1455 uint8_t slave1_rate : 2; 1456 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1457 uint8_t slave1_rate : 2; 1458 uint8_t write_once : 1; 1459 uint8_t not_used_01 : 2; 1460 uint8_t slave1_numop : 3; 1461 #endif /* DRV_BYTE_ORDER */ 1462 } lsm6dsl_slave1_config_t; 1463 1464 #define LSM6DSL_SLV2_ADD 0x08U 1465 typedef struct 1466 { 1467 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1468 uint8_t r_2 : 1; 1469 uint8_t slave2_add : 7; 1470 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1471 uint8_t slave2_add : 7; 1472 uint8_t r_2 : 1; 1473 #endif /* DRV_BYTE_ORDER */ 1474 } lsm6dsl_slv2_add_t; 1475 1476 #define LSM6DSL_SLV2_SUBADD 0x09U 1477 typedef struct 1478 { 1479 uint8_t slave2_reg : 8; 1480 } lsm6dsl_slv2_subadd_t; 1481 1482 #define LSM6DSL_SLAVE2_CONFIG 0x0AU 1483 typedef struct 1484 { 1485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1486 uint8_t slave2_numop : 3; 1487 uint8_t not_used_01 : 3; 1488 uint8_t slave2_rate : 2; 1489 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1490 uint8_t slave2_rate : 2; 1491 uint8_t not_used_01 : 3; 1492 uint8_t slave2_numop : 3; 1493 #endif /* DRV_BYTE_ORDER */ 1494 } lsm6dsl_slave2_config_t; 1495 1496 #define LSM6DSL_SLV3_ADD 0x0BU 1497 typedef struct 1498 { 1499 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1500 uint8_t r_3 : 1; 1501 uint8_t slave3_add : 7; 1502 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1503 uint8_t slave3_add : 7; 1504 uint8_t r_3 : 1; 1505 #endif /* DRV_BYTE_ORDER */ 1506 } lsm6dsl_slv3_add_t; 1507 1508 #define LSM6DSL_SLV3_SUBADD 0x0CU 1509 typedef struct 1510 { 1511 uint8_t slave3_reg : 8; 1512 } lsm6dsl_slv3_subadd_t; 1513 1514 #define LSM6DSL_SLAVE3_CONFIG 0x0DU 1515 typedef struct 1516 { 1517 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1518 uint8_t slave3_numop : 3; 1519 uint8_t not_used_01 : 3; 1520 uint8_t slave3_rate : 2; 1521 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1522 uint8_t slave3_rate : 2; 1523 uint8_t not_used_01 : 3; 1524 uint8_t slave3_numop : 3; 1525 #endif /* DRV_BYTE_ORDER */ 1526 } lsm6dsl_slave3_config_t; 1527 1528 #define LSM6DSL_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU 1529 typedef struct 1530 { 1531 uint8_t slave_dataw : 8; 1532 } lsm6dsl_datawrite_src_mode_sub_slv0_t; 1533 1534 #define LSM6DSL_CONFIG_PEDO_THS_MIN 0x0FU 1535 typedef struct 1536 { 1537 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1538 uint8_t ths_min : 5; 1539 uint8_t not_used_01 : 2; 1540 uint8_t pedo_fs : 1; 1541 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1542 uint8_t pedo_fs : 1; 1543 uint8_t not_used_01 : 2; 1544 uint8_t ths_min : 5; 1545 #endif /* DRV_BYTE_ORDER */ 1546 } lsm6dsl_config_pedo_ths_min_t; 1547 1548 #define LSM6DSL_SM_THS 0x13U 1549 #define LSM6DSL_PEDO_DEB_REG 0x14U 1550 typedef struct 1551 { 1552 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1553 uint8_t deb_step : 3; 1554 uint8_t deb_time : 5; 1555 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1556 uint8_t deb_time : 5; 1557 uint8_t deb_step : 3; 1558 #endif /* DRV_BYTE_ORDER */ 1559 } lsm6dsl_pedo_deb_reg_t; 1560 1561 #define LSM6DSL_STEP_COUNT_DELTA 0x15U 1562 #define LSM6DSL_MAG_SI_XX 0x24U 1563 #define LSM6DSL_MAG_SI_XY 0x25U 1564 #define LSM6DSL_MAG_SI_XZ 0x26U 1565 #define LSM6DSL_MAG_SI_YX 0x27U 1566 #define LSM6DSL_MAG_SI_YY 0x28U 1567 #define LSM6DSL_MAG_SI_YZ 0x29U 1568 #define LSM6DSL_MAG_SI_ZX 0x2AU 1569 #define LSM6DSL_MAG_SI_ZY 0x2BU 1570 #define LSM6DSL_MAG_SI_ZZ 0x2CU 1571 #define LSM6DSL_MAG_OFFX_L 0x2DU 1572 #define LSM6DSL_MAG_OFFX_H 0x2EU 1573 #define LSM6DSL_MAG_OFFY_L 0x2FU 1574 #define LSM6DSL_MAG_OFFY_H 0x30U 1575 #define LSM6DSL_MAG_OFFZ_L 0x31U 1576 #define LSM6DSL_MAG_OFFZ_H 0x32U 1577 #define LSM6DSL_A_WRIST_TILT_LAT 0x50U 1578 #define LSM6DSL_A_WRIST_TILT_THS 0x54U 1579 #define LSM6DSL_A_WRIST_TILT_MASK 0x59U 1580 typedef struct 1581 { 1582 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1583 uint8_t not_used_01 : 2; 1584 uint8_t wrist_tilt_mask_zneg : 1; 1585 uint8_t wrist_tilt_mask_zpos : 1; 1586 uint8_t wrist_tilt_mask_yneg : 1; 1587 uint8_t wrist_tilt_mask_ypos : 1; 1588 uint8_t wrist_tilt_mask_xneg : 1; 1589 uint8_t wrist_tilt_mask_xpos : 1; 1590 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1591 uint8_t wrist_tilt_mask_xpos : 1; 1592 uint8_t wrist_tilt_mask_xneg : 1; 1593 uint8_t wrist_tilt_mask_ypos : 1; 1594 uint8_t wrist_tilt_mask_yneg : 1; 1595 uint8_t wrist_tilt_mask_zpos : 1; 1596 uint8_t wrist_tilt_mask_zneg : 1; 1597 uint8_t not_used_01 : 2; 1598 #endif /* DRV_BYTE_ORDER */ 1599 } lsm6dsl_a_wrist_tilt_mask_t; 1600 1601 /** 1602 * @defgroup LSM6DSL_Register_Union 1603 * @brief This union group all the registers having a bit-field 1604 * description. 1605 * This union is useful but it's not needed by the driver. 1606 * 1607 * REMOVING this union you are compliant with: 1608 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 1609 * 1610 * @{ 1611 * 1612 */ 1613 typedef union 1614 { 1615 lsm6dsl_func_cfg_access_t func_cfg_access; 1616 lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame; 1617 lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio; 1618 lsm6dsl_fifo_ctrl1_t fifo_ctrl1; 1619 lsm6dsl_fifo_ctrl2_t fifo_ctrl2; 1620 lsm6dsl_fifo_ctrl3_t fifo_ctrl3; 1621 lsm6dsl_fifo_ctrl4_t fifo_ctrl4; 1622 lsm6dsl_fifo_ctrl5_t fifo_ctrl5; 1623 lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; 1624 lsm6dsl_int1_ctrl_t int1_ctrl; 1625 lsm6dsl_int2_ctrl_t int2_ctrl; 1626 lsm6dsl_ctrl1_xl_t ctrl1_xl; 1627 lsm6dsl_ctrl2_g_t ctrl2_g; 1628 lsm6dsl_ctrl3_c_t ctrl3_c; 1629 lsm6dsl_ctrl4_c_t ctrl4_c; 1630 lsm6dsl_ctrl5_c_t ctrl5_c; 1631 lsm6dsl_ctrl6_c_t ctrl6_c; 1632 lsm6dsl_ctrl7_g_t ctrl7_g; 1633 lsm6dsl_ctrl8_xl_t ctrl8_xl; 1634 lsm6dsl_ctrl9_xl_t ctrl9_xl; 1635 lsm6dsl_ctrl10_c_t ctrl10_c; 1636 lsm6dsl_master_config_t master_config; 1637 lsm6dsl_wake_up_src_t wake_up_src; 1638 lsm6dsl_tap_src_t tap_src; 1639 lsm6dsl_d6d_src_t d6d_src; 1640 lsm6dsl_status_reg_t status_reg; 1641 lsm6dsl_sensorhub1_reg_t sensorhub1_reg; 1642 lsm6dsl_sensorhub2_reg_t sensorhub2_reg; 1643 lsm6dsl_sensorhub3_reg_t sensorhub3_reg; 1644 lsm6dsl_sensorhub4_reg_t sensorhub4_reg; 1645 lsm6dsl_sensorhub5_reg_t sensorhub5_reg; 1646 lsm6dsl_sensorhub6_reg_t sensorhub6_reg; 1647 lsm6dsl_sensorhub7_reg_t sensorhub7_reg; 1648 lsm6dsl_sensorhub8_reg_t sensorhub8_reg; 1649 lsm6dsl_sensorhub9_reg_t sensorhub9_reg; 1650 lsm6dsl_sensorhub10_reg_t sensorhub10_reg; 1651 lsm6dsl_sensorhub11_reg_t sensorhub11_reg; 1652 lsm6dsl_sensorhub12_reg_t sensorhub12_reg; 1653 lsm6dsl_fifo_status1_t fifo_status1; 1654 lsm6dsl_fifo_status2_t fifo_status2; 1655 lsm6dsl_fifo_status3_t fifo_status3; 1656 lsm6dsl_fifo_status4_t fifo_status4; 1657 lsm6dsl_sensorhub13_reg_t sensorhub13_reg; 1658 lsm6dsl_sensorhub14_reg_t sensorhub14_reg; 1659 lsm6dsl_sensorhub15_reg_t sensorhub15_reg; 1660 lsm6dsl_sensorhub16_reg_t sensorhub16_reg; 1661 lsm6dsl_sensorhub17_reg_t sensorhub17_reg; 1662 lsm6dsl_sensorhub18_reg_t sensorhub18_reg; 1663 lsm6dsl_func_src1_t func_src1; 1664 lsm6dsl_func_src2_t func_src2; 1665 lsm6dsl_wrist_tilt_ia_t wrist_tilt_ia; 1666 lsm6dsl_tap_cfg_t tap_cfg; 1667 lsm6dsl_tap_ths_6d_t tap_ths_6d; 1668 lsm6dsl_int_dur2_t int_dur2; 1669 lsm6dsl_wake_up_ths_t wake_up_ths; 1670 lsm6dsl_wake_up_dur_t wake_up_dur; 1671 lsm6dsl_free_fall_t free_fall; 1672 lsm6dsl_md1_cfg_t md1_cfg; 1673 lsm6dsl_md2_cfg_t md2_cfg; 1674 lsm6dsl_master_cmd_code_t master_cmd_code; 1675 lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code; 1676 lsm6dsl_slv0_add_t slv0_add; 1677 lsm6dsl_slv0_subadd_t slv0_subadd; 1678 lsm6dsl_slave0_config_t slave0_config; 1679 lsm6dsl_slv1_add_t slv1_add; 1680 lsm6dsl_slv1_subadd_t slv1_subadd; 1681 lsm6dsl_slave1_config_t slave1_config; 1682 lsm6dsl_slv2_add_t slv2_add; 1683 lsm6dsl_slv2_subadd_t slv2_subadd; 1684 lsm6dsl_slave2_config_t slave2_config; 1685 lsm6dsl_slv3_add_t slv3_add; 1686 lsm6dsl_slv3_subadd_t slv3_subadd; 1687 lsm6dsl_slave3_config_t slave3_config; 1688 lsm6dsl_datawrite_src_mode_sub_slv0_t 1689 datawrite_src_mode_sub_slv0; 1690 lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min; 1691 lsm6dsl_pedo_deb_reg_t pedo_deb_reg; 1692 lsm6dsl_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1693 bitwise_t bitwise; 1694 uint8_t byte; 1695 } lsm6dsl_reg_t; 1696 1697 /** 1698 * @} 1699 * 1700 */ 1701 1702 #ifndef __weak 1703 #define __weak __attribute__((weak)) 1704 #endif /* __weak */ 1705 1706 /* 1707 * These are the basic platform dependent I/O routines to read 1708 * and write device registers connected on a standard bus. 1709 * The driver keeps offering a default implementation based on function 1710 * pointers to read/write routines for backward compatibility. 1711 * The __weak directive allows the final application to overwrite 1712 * them with a custom implementation. 1713 */ 1714 1715 int32_t lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 1716 uint8_t *data, 1717 uint16_t len); 1718 int32_t lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 1719 uint8_t *data, 1720 uint16_t len); 1721 1722 float_t lsm6dsl_from_fs2g_to_mg(int16_t lsb); 1723 float_t lsm6dsl_from_fs4g_to_mg(int16_t lsb); 1724 float_t lsm6dsl_from_fs8g_to_mg(int16_t lsb); 1725 float_t lsm6dsl_from_fs16g_to_mg(int16_t lsb); 1726 1727 float_t lsm6dsl_from_fs125dps_to_mdps(int16_t lsb); 1728 float_t lsm6dsl_from_fs250dps_to_mdps(int16_t lsb); 1729 float_t lsm6dsl_from_fs500dps_to_mdps(int16_t lsb); 1730 float_t lsm6dsl_from_fs1000dps_to_mdps(int16_t lsb); 1731 float_t lsm6dsl_from_fs2000dps_to_mdps(int16_t lsb); 1732 1733 float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb); 1734 1735 typedef enum 1736 { 1737 LSM6DSL_2g = 0, 1738 LSM6DSL_16g = 1, 1739 LSM6DSL_4g = 2, 1740 LSM6DSL_8g = 3, 1741 LSM6DSL_XL_FS_ND = 4, /* ERROR CODE */ 1742 } lsm6dsl_fs_xl_t; 1743 int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx, 1744 lsm6dsl_fs_xl_t val); 1745 int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx, 1746 lsm6dsl_fs_xl_t *val); 1747 1748 typedef enum 1749 { 1750 LSM6DSL_XL_ODR_OFF = 0, 1751 LSM6DSL_XL_ODR_12Hz5 = 1, 1752 LSM6DSL_XL_ODR_26Hz = 2, 1753 LSM6DSL_XL_ODR_52Hz = 3, 1754 LSM6DSL_XL_ODR_104Hz = 4, 1755 LSM6DSL_XL_ODR_208Hz = 5, 1756 LSM6DSL_XL_ODR_416Hz = 6, 1757 LSM6DSL_XL_ODR_833Hz = 7, 1758 LSM6DSL_XL_ODR_1k66Hz = 8, 1759 LSM6DSL_XL_ODR_3k33Hz = 9, 1760 LSM6DSL_XL_ODR_6k66Hz = 10, 1761 LSM6DSL_XL_ODR_1Hz6 = 11, 1762 LSM6DSL_XL_ODR_ND = 12, /* ERROR CODE */ 1763 } lsm6dsl_odr_xl_t; 1764 int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx, 1765 lsm6dsl_odr_xl_t val); 1766 int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx, 1767 lsm6dsl_odr_xl_t *val); 1768 1769 typedef enum 1770 { 1771 LSM6DSL_250dps = 0, 1772 LSM6DSL_125dps = 1, 1773 LSM6DSL_500dps = 2, 1774 LSM6DSL_1000dps = 4, 1775 LSM6DSL_2000dps = 6, 1776 LSM6DSL_GY_FS_ND = 7, /* ERROR CODE */ 1777 } lsm6dsl_fs_g_t; 1778 int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx, 1779 lsm6dsl_fs_g_t val); 1780 int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx, 1781 lsm6dsl_fs_g_t *val); 1782 1783 typedef enum 1784 { 1785 LSM6DSL_GY_ODR_OFF = 0, 1786 LSM6DSL_GY_ODR_12Hz5 = 1, 1787 LSM6DSL_GY_ODR_26Hz = 2, 1788 LSM6DSL_GY_ODR_52Hz = 3, 1789 LSM6DSL_GY_ODR_104Hz = 4, 1790 LSM6DSL_GY_ODR_208Hz = 5, 1791 LSM6DSL_GY_ODR_416Hz = 6, 1792 LSM6DSL_GY_ODR_833Hz = 7, 1793 LSM6DSL_GY_ODR_1k66Hz = 8, 1794 LSM6DSL_GY_ODR_3k33Hz = 9, 1795 LSM6DSL_GY_ODR_6k66Hz = 10, 1796 LSM6DSL_GY_ODR_ND = 11, /* ERROR CODE */ 1797 } lsm6dsl_odr_g_t; 1798 int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx, 1799 lsm6dsl_odr_g_t val); 1800 int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx, 1801 lsm6dsl_odr_g_t *val); 1802 1803 int32_t lsm6dsl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 1804 int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx, 1805 uint8_t *val); 1806 1807 typedef enum 1808 { 1809 LSM6DSL_LSb_1mg = 0, 1810 LSM6DSL_LSb_16mg = 1, 1811 LSM6DSL_WEIGHT_ND = 2, 1812 } lsm6dsl_usr_off_w_t; 1813 int32_t lsm6dsl_xl_offset_weight_set(stmdev_ctx_t *ctx, 1814 lsm6dsl_usr_off_w_t val); 1815 int32_t lsm6dsl_xl_offset_weight_get(stmdev_ctx_t *ctx, 1816 lsm6dsl_usr_off_w_t *val); 1817 1818 typedef enum 1819 { 1820 LSM6DSL_XL_HIGH_PERFORMANCE = 0, 1821 LSM6DSL_XL_NORMAL = 1, 1822 LSM6DSL_XL_PW_MODE_ND = 2, /* ERROR CODE */ 1823 } lsm6dsl_xl_hm_mode_t; 1824 int32_t lsm6dsl_xl_power_mode_set(stmdev_ctx_t *ctx, 1825 lsm6dsl_xl_hm_mode_t val); 1826 int32_t lsm6dsl_xl_power_mode_get(stmdev_ctx_t *ctx, 1827 lsm6dsl_xl_hm_mode_t *val); 1828 1829 typedef enum 1830 { 1831 LSM6DSL_STAT_RND_DISABLE = 0, 1832 LSM6DSL_STAT_RND_ENABLE = 1, 1833 LSM6DSL_STAT_RND_ND = 2, /* ERROR CODE */ 1834 } lsm6dsl_rounding_status_t; 1835 int32_t lsm6dsl_rounding_on_status_set(stmdev_ctx_t *ctx, 1836 lsm6dsl_rounding_status_t val); 1837 int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx, 1838 lsm6dsl_rounding_status_t *val); 1839 1840 typedef enum 1841 { 1842 LSM6DSL_GY_HIGH_PERFORMANCE = 0, 1843 LSM6DSL_GY_NORMAL = 1, 1844 LSM6DSL_GY_PW_MODE_ND = 2, /* ERROR CODE */ 1845 } lsm6dsl_g_hm_mode_t; 1846 int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx, 1847 lsm6dsl_g_hm_mode_t val); 1848 int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx, 1849 lsm6dsl_g_hm_mode_t *val); 1850 1851 typedef struct 1852 { 1853 lsm6dsl_wake_up_src_t wake_up_src; 1854 lsm6dsl_tap_src_t tap_src; 1855 lsm6dsl_d6d_src_t d6d_src; 1856 lsm6dsl_status_reg_t status_reg; 1857 lsm6dsl_func_src1_t func_src1; 1858 lsm6dsl_func_src2_t func_src2; 1859 lsm6dsl_wrist_tilt_ia_t wrist_tilt_ia; 1860 lsm6dsl_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1861 } lsm6dsl_all_sources_t; 1862 int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx, 1863 lsm6dsl_all_sources_t *val); 1864 1865 int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx, 1866 lsm6dsl_status_reg_t *val); 1867 1868 int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 1869 uint8_t *val); 1870 1871 int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx, 1872 uint8_t *val); 1873 1874 int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 1875 uint8_t *val); 1876 1877 int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); 1878 int32_t lsm6dsl_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); 1879 int32_t lsm6dsl_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 1880 int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 1881 1882 typedef enum 1883 { 1884 LSM6DSL_LSB_6ms4 = 0, 1885 LSM6DSL_LSB_25us = 1, 1886 LSM6DSL_TS_RES_ND = 2, /* ERROR CODE */ 1887 } lsm6dsl_timer_hr_t; 1888 int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx, 1889 lsm6dsl_timer_hr_t val); 1890 int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx, 1891 lsm6dsl_timer_hr_t *val); 1892 1893 typedef enum 1894 { 1895 LSM6DSL_ROUND_DISABLE = 0, 1896 LSM6DSL_ROUND_XL = 1, 1897 LSM6DSL_ROUND_GY = 2, 1898 LSM6DSL_ROUND_GY_XL = 3, 1899 LSM6DSL_ROUND_SH1_TO_SH6 = 4, 1900 LSM6DSL_ROUND_XL_SH1_TO_SH6 = 5, 1901 LSM6DSL_ROUND_GY_XL_SH1_TO_SH12 = 6, 1902 LSM6DSL_ROUND_GY_XL_SH1_TO_SH6 = 7, 1903 LSM6DSL_ROUND_OUT_ND = 8, /* ERROR CODE */ 1904 } lsm6dsl_rounding_t; 1905 int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx, 1906 lsm6dsl_rounding_t val); 1907 int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx, 1908 lsm6dsl_rounding_t *val); 1909 1910 int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 1911 int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val); 1912 int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 1913 1914 int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx, 1915 int16_t *val); 1916 1917 int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, 1918 uint8_t len); 1919 1920 typedef enum 1921 { 1922 LSM6DSL_USER_BANK = 0, 1923 LSM6DSL_BANK_A = 4, 1924 LSM6DSL_BANK_B = 5, 1925 LSM6DSL_BANK_ND = 6, /* ERROR CODE */ 1926 } lsm6dsl_func_cfg_en_t; 1927 int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx, 1928 lsm6dsl_func_cfg_en_t val); 1929 int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx, 1930 lsm6dsl_func_cfg_en_t *val); 1931 1932 typedef enum 1933 { 1934 LSM6DSL_DRDY_LATCHED = 0, 1935 LSM6DSL_DRDY_PULSED = 1, 1936 LSM6DSL_DRDY_ND = 2, /* ERROR CODE */ 1937 } lsm6dsl_drdy_pulsed_g_t; 1938 int32_t lsm6dsl_data_ready_mode_set(stmdev_ctx_t *ctx, 1939 lsm6dsl_drdy_pulsed_g_t val); 1940 int32_t lsm6dsl_data_ready_mode_get(stmdev_ctx_t *ctx, 1941 lsm6dsl_drdy_pulsed_g_t *val); 1942 1943 int32_t lsm6dsl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 1944 int32_t lsm6dsl_reset_set(stmdev_ctx_t *ctx, uint8_t val); 1945 int32_t lsm6dsl_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 1946 1947 typedef enum 1948 { 1949 LSM6DSL_LSB_AT_LOW_ADD = 0, 1950 LSM6DSL_MSB_AT_LOW_ADD = 1, 1951 LSM6DSL_DATA_FMT_ND = 2, /* ERROR CODE */ 1952 } lsm6dsl_ble_t; 1953 int32_t lsm6dsl_data_format_set(stmdev_ctx_t *ctx, lsm6dsl_ble_t val); 1954 int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx, 1955 lsm6dsl_ble_t *val); 1956 1957 int32_t lsm6dsl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 1958 int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 1959 1960 int32_t lsm6dsl_boot_set(stmdev_ctx_t *ctx, uint8_t val); 1961 int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 1962 1963 typedef enum 1964 { 1965 LSM6DSL_XL_ST_DISABLE = 0, 1966 LSM6DSL_XL_ST_POSITIVE = 1, 1967 LSM6DSL_XL_ST_NEGATIVE = 2, 1968 LSM6DSL_XL_ST_ND = 3, /* ERROR CODE */ 1969 } lsm6dsl_st_xl_t; 1970 int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx, 1971 lsm6dsl_st_xl_t val); 1972 int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx, 1973 lsm6dsl_st_xl_t *val); 1974 1975 typedef enum 1976 { 1977 LSM6DSL_GY_ST_DISABLE = 0, 1978 LSM6DSL_GY_ST_POSITIVE = 1, 1979 LSM6DSL_GY_ST_NEGATIVE = 3, 1980 LSM6DSL_GY_ST_ND = 4, /* ERROR CODE */ 1981 } lsm6dsl_st_g_t; 1982 int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx, 1983 lsm6dsl_st_g_t val); 1984 int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx, 1985 lsm6dsl_st_g_t *val); 1986 1987 int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx, 1988 uint8_t val); 1989 int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx, 1990 uint8_t *val); 1991 1992 typedef enum 1993 { 1994 LSM6DSL_USE_SLOPE = 0, 1995 LSM6DSL_USE_HPF = 1, 1996 LSM6DSL_HP_PATH_ND = 2, /* ERROR CODE */ 1997 } lsm6dsl_slope_fds_t; 1998 int32_t lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 1999 lsm6dsl_slope_fds_t val); 2000 int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 2001 lsm6dsl_slope_fds_t *val); 2002 2003 typedef enum 2004 { 2005 LSM6DSL_XL_ANA_BW_1k5Hz = 0, 2006 LSM6DSL_XL_ANA_BW_400Hz = 1, 2007 LSM6DSL_XL_ANA_BW_ND = 2, /* ERROR CODE */ 2008 } lsm6dsl_bw0_xl_t; 2009 int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx, 2010 lsm6dsl_bw0_xl_t val); 2011 int32_t lsm6dsl_xl_filter_analog_get(stmdev_ctx_t *ctx, 2012 lsm6dsl_bw0_xl_t *val); 2013 2014 typedef enum 2015 { 2016 LSM6DSL_XL_LP1_ODR_DIV_2 = 0, 2017 LSM6DSL_XL_LP1_ODR_DIV_4 = 1, 2018 LSM6DSL_XL_LP1_NA = 2, /* ERROR CODE */ 2019 } lsm6dsl_lpf1_bw_sel_t; 2020 int32_t lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, 2021 lsm6dsl_lpf1_bw_sel_t val); 2022 int32_t lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, 2023 lsm6dsl_lpf1_bw_sel_t *val); 2024 2025 typedef enum 2026 { 2027 LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00, 2028 LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01, 2029 LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02, 2030 LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400 = 0x03, 2031 LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50 = 0x10, 2032 LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100 = 0x11, 2033 LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9 = 0x12, 2034 LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, 2035 LSM6DSL_XL_LP_NA = 0x20, /* ERROR CODE */ 2036 } lsm6dsl_input_composite_t; 2037 int32_t lsm6dsl_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, 2038 lsm6dsl_input_composite_t val); 2039 int32_t lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, 2040 lsm6dsl_input_composite_t *val); 2041 2042 int32_t lsm6dsl_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2043 int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, 2044 uint8_t *val); 2045 2046 typedef enum 2047 { 2048 LSM6DSL_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */ 2049 LSM6DSL_XL_HP_ODR_DIV_100 = 0x01, 2050 LSM6DSL_XL_HP_ODR_DIV_9 = 0x02, 2051 LSM6DSL_XL_HP_ODR_DIV_400 = 0x03, 2052 LSM6DSL_XL_HP_NA = 0x10, /* ERROR CODE */ 2053 } lsm6dsl_hpcf_xl_t; 2054 int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, 2055 lsm6dsl_hpcf_xl_t val); 2056 int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, 2057 lsm6dsl_hpcf_xl_t *val); 2058 2059 typedef enum 2060 { 2061 LSM6DSL_LP2_ONLY = 0x00, 2062 2063 LSM6DSL_HP_16mHz_LP2 = 0x80, 2064 LSM6DSL_HP_65mHz_LP2 = 0x90, 2065 LSM6DSL_HP_260mHz_LP2 = 0xA0, 2066 LSM6DSL_HP_1Hz04_LP2 = 0xB0, 2067 2068 LSM6DSL_HP_DISABLE_LP1_LIGHT = 0x0A, 2069 LSM6DSL_HP_DISABLE_LP1_NORMAL = 0x09, 2070 LSM6DSL_HP_DISABLE_LP_STRONG = 0x08, 2071 LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, 2072 2073 LSM6DSL_HP_16mHz_LP1_LIGHT = 0x8A, 2074 LSM6DSL_HP_65mHz_LP1_NORMAL = 0x99, 2075 LSM6DSL_HP_260mHz_LP1_STRONG = 0xA8, 2076 LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, 2077 2078 LSM6DSL_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */ 2079 } lsm6dsl_lpf1_sel_g_t; 2080 int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx, 2081 lsm6dsl_lpf1_sel_g_t val); 2082 int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx, 2083 lsm6dsl_lpf1_sel_g_t *val); 2084 2085 typedef enum 2086 { 2087 LSM6DSL_SPI_4_WIRE = 0, 2088 LSM6DSL_SPI_3_WIRE = 1, 2089 LSM6DSL_SPI_MODE_ND = 2, /* ERROR CODE */ 2090 } lsm6dsl_sim_t; 2091 int32_t lsm6dsl_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsl_sim_t val); 2092 int32_t lsm6dsl_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsl_sim_t *val); 2093 2094 typedef enum 2095 { 2096 LSM6DSL_I2C_ENABLE = 0, 2097 LSM6DSL_I2C_DISABLE = 1, 2098 LSM6DSL_I2C_MODE_ND = 2, /* ERROR CODE */ 2099 } lsm6dsl_i2c_disable_t; 2100 int32_t lsm6dsl_i2c_interface_set(stmdev_ctx_t *ctx, 2101 lsm6dsl_i2c_disable_t val); 2102 int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx, 2103 lsm6dsl_i2c_disable_t *val); 2104 2105 typedef struct 2106 { 2107 uint8_t int1_drdy_xl : 1; 2108 uint8_t int1_drdy_g : 1; 2109 uint8_t int1_boot : 1; 2110 uint8_t int1_fth : 1; 2111 uint8_t int1_fifo_ovr : 1; 2112 uint8_t int1_full_flag : 1; 2113 uint8_t int1_sign_mot : 1; 2114 uint8_t int1_step_detector : 1; 2115 uint8_t int1_timer : 1; 2116 uint8_t int1_tilt : 1; 2117 uint8_t int1_6d : 1; 2118 uint8_t int1_double_tap : 1; 2119 uint8_t int1_ff : 1; 2120 uint8_t int1_wu : 1; 2121 uint8_t int1_single_tap : 1; 2122 uint8_t int1_inact_state : 1; 2123 uint8_t den_drdy_int1 : 1; 2124 uint8_t drdy_on_int1 : 1; 2125 } lsm6dsl_int1_route_t; 2126 int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx, 2127 lsm6dsl_int1_route_t val); 2128 int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx, 2129 lsm6dsl_int1_route_t *val); 2130 2131 typedef struct 2132 { 2133 uint8_t int2_drdy_xl : 1; 2134 uint8_t int2_drdy_g : 1; 2135 uint8_t int2_drdy_temp : 1; 2136 uint8_t int2_fth : 1; 2137 uint8_t int2_fifo_ovr : 1; 2138 uint8_t int2_full_flag : 1; 2139 uint8_t int2_step_count_ov : 1; 2140 uint8_t int2_step_delta : 1; 2141 uint8_t int2_iron : 1; 2142 uint8_t int2_tilt : 1; 2143 uint8_t int2_6d : 1; 2144 uint8_t int2_double_tap : 1; 2145 uint8_t int2_ff : 1; 2146 uint8_t int2_wu : 1; 2147 uint8_t int2_single_tap : 1; 2148 uint8_t int2_inact_state : 1; 2149 uint8_t int2_wrist_tilt : 1; 2150 } lsm6dsl_int2_route_t; 2151 int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx, 2152 lsm6dsl_int2_route_t val); 2153 int32_t lsm6dsl_pin_int2_route_get(stmdev_ctx_t *ctx, 2154 lsm6dsl_int2_route_t *val); 2155 2156 typedef enum 2157 { 2158 LSM6DSL_PUSH_PULL = 0, 2159 LSM6DSL_OPEN_DRAIN = 1, 2160 LSM6DSL_PIN_MODE_ND = 2, /* ERROR CODE */ 2161 } lsm6dsl_pp_od_t; 2162 int32_t lsm6dsl_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val); 2163 int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val); 2164 2165 typedef enum 2166 { 2167 LSM6DSL_ACTIVE_HIGH = 0, 2168 LSM6DSL_ACTIVE_LOW = 1, 2169 LSM6DSL_POLARITY_ND = 2, /* ERROR CODE */ 2170 } lsm6dsl_h_lactive_t; 2171 int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx, 2172 lsm6dsl_h_lactive_t val); 2173 int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx, 2174 lsm6dsl_h_lactive_t *val); 2175 2176 int32_t lsm6dsl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 2177 int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 2178 2179 typedef enum 2180 { 2181 LSM6DSL_INT_PULSED = 0, 2182 LSM6DSL_INT_LATCHED = 1, 2183 LSM6DSL_INT_MODE = 2, /* ERROR CODE */ 2184 } lsm6dsl_lir_t; 2185 int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx, 2186 lsm6dsl_lir_t val); 2187 int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx, 2188 lsm6dsl_lir_t *val); 2189 2190 int32_t lsm6dsl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 2191 int32_t lsm6dsl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 2192 2193 int32_t lsm6dsl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2194 int32_t lsm6dsl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2195 2196 int32_t lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2197 int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 2198 2199 typedef enum 2200 { 2201 LSM6DSL_PROPERTY_DISABLE = 0, 2202 LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED = 1, 2203 LSM6DSL_XL_12Hz5_GY_SLEEP = 2, 2204 LSM6DSL_XL_12Hz5_GY_PD = 3, 2205 LSM6DSL_ACT_MODE_ND = 4, /* ERROR CODE */ 2206 } lsm6dsl_inact_en_t; 2207 int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx, 2208 lsm6dsl_inact_en_t val); 2209 int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx, 2210 lsm6dsl_inact_en_t *val); 2211 2212 int32_t lsm6dsl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2213 int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2214 2215 int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx, 2216 lsm6dsl_tap_src_t *val); 2217 2218 int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, 2219 uint8_t val); 2220 int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx, 2221 uint8_t *val); 2222 2223 int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, 2224 uint8_t val); 2225 int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx, 2226 uint8_t *val); 2227 2228 int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, 2229 uint8_t val); 2230 int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx, 2231 uint8_t *val); 2232 2233 int32_t lsm6dsl_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); 2234 int32_t lsm6dsl_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); 2235 2236 int32_t lsm6dsl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 2237 int32_t lsm6dsl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 2238 2239 int32_t lsm6dsl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 2240 int32_t lsm6dsl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 2241 2242 int32_t lsm6dsl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2243 int32_t lsm6dsl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2244 2245 typedef enum 2246 { 2247 LSM6DSL_ONLY_SINGLE = 0, 2248 LSM6DSL_BOTH_SINGLE_DOUBLE = 1, 2249 LSM6DSL_TAP_MODE_ND = 2, /* ERROR CODE */ 2250 } lsm6dsl_single_double_tap_t; 2251 int32_t lsm6dsl_tap_mode_set(stmdev_ctx_t *ctx, 2252 lsm6dsl_single_double_tap_t val); 2253 int32_t lsm6dsl_tap_mode_get(stmdev_ctx_t *ctx, 2254 lsm6dsl_single_double_tap_t *val); 2255 2256 typedef enum 2257 { 2258 LSM6DSL_ODR_DIV_2_FEED = 0, 2259 LSM6DSL_LPF2_FEED = 1, 2260 LSM6DSL_6D_FEED_ND = 2, /* ERROR CODE */ 2261 } lsm6dsl_low_pass_on_6d_t; 2262 int32_t lsm6dsl_6d_feed_data_set(stmdev_ctx_t *ctx, 2263 lsm6dsl_low_pass_on_6d_t val); 2264 int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx, 2265 lsm6dsl_low_pass_on_6d_t *val); 2266 2267 typedef enum 2268 { 2269 LSM6DSL_DEG_80 = 0, 2270 LSM6DSL_DEG_70 = 1, 2271 LSM6DSL_DEG_60 = 2, 2272 LSM6DSL_DEG_50 = 3, 2273 LSM6DSL_6D_TH_ND = 4, /* ERROR CODE */ 2274 } lsm6dsl_sixd_ths_t; 2275 int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx, 2276 lsm6dsl_sixd_ths_t val); 2277 int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx, 2278 lsm6dsl_sixd_ths_t *val); 2279 2280 int32_t lsm6dsl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); 2281 int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); 2282 2283 int32_t lsm6dsl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2284 int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2285 2286 typedef enum 2287 { 2288 LSM6DSL_FF_TSH_156mg = 0, 2289 LSM6DSL_FF_TSH_219mg = 1, 2290 LSM6DSL_FF_TSH_250mg = 2, 2291 LSM6DSL_FF_TSH_312mg = 3, 2292 LSM6DSL_FF_TSH_344mg = 4, 2293 LSM6DSL_FF_TSH_406mg = 5, 2294 LSM6DSL_FF_TSH_469mg = 6, 2295 LSM6DSL_FF_TSH_500mg = 7, 2296 LSM6DSL_FF_TSH_ND = 8, /* ERROR CODE */ 2297 } lsm6dsl_ff_ths_t; 2298 int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx, 2299 lsm6dsl_ff_ths_t val); 2300 int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx, 2301 lsm6dsl_ff_ths_t *val); 2302 2303 int32_t lsm6dsl_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 2304 int32_t lsm6dsl_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); 2305 2306 int32_t lsm6dsl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); 2307 2308 int32_t lsm6dsl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2309 2310 int32_t lsm6dsl_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); 2311 2312 int32_t lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); 2313 int32_t lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); 2314 2315 typedef enum 2316 { 2317 LSM6DSL_TRG_XL_GY_DRDY = 0, 2318 LSM6DSL_TRG_STEP_DETECT = 1, 2319 LSM6DSL_TRG_SH_DRDY = 2, 2320 LSM6DSL_TRG_SH_ND = 3, /* ERROR CODE */ 2321 } lsm6dsl_trigger_fifo_t; 2322 int32_t lsm6dsl_fifo_write_trigger_set(stmdev_ctx_t *ctx, 2323 lsm6dsl_trigger_fifo_t val); 2324 int32_t lsm6dsl_fifo_write_trigger_get(stmdev_ctx_t *ctx, 2325 lsm6dsl_trigger_fifo_t *val); 2326 2327 int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, 2328 uint8_t val); 2329 int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, 2330 uint8_t *val); 2331 2332 typedef enum 2333 { 2334 LSM6DSL_FIFO_XL_DISABLE = 0, 2335 LSM6DSL_FIFO_XL_NO_DEC = 1, 2336 LSM6DSL_FIFO_XL_DEC_2 = 2, 2337 LSM6DSL_FIFO_XL_DEC_3 = 3, 2338 LSM6DSL_FIFO_XL_DEC_4 = 4, 2339 LSM6DSL_FIFO_XL_DEC_8 = 5, 2340 LSM6DSL_FIFO_XL_DEC_16 = 6, 2341 LSM6DSL_FIFO_XL_DEC_32 = 7, 2342 LSM6DSL_FIFO_XL_DEC_ND = 8, /* ERROR CODE */ 2343 } lsm6dsl_dec_fifo_xl_t; 2344 int32_t lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t *ctx, 2345 lsm6dsl_dec_fifo_xl_t val); 2346 int32_t lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t *ctx, 2347 lsm6dsl_dec_fifo_xl_t *val); 2348 2349 typedef enum 2350 { 2351 LSM6DSL_FIFO_GY_DISABLE = 0, 2352 LSM6DSL_FIFO_GY_NO_DEC = 1, 2353 LSM6DSL_FIFO_GY_DEC_2 = 2, 2354 LSM6DSL_FIFO_GY_DEC_3 = 3, 2355 LSM6DSL_FIFO_GY_DEC_4 = 4, 2356 LSM6DSL_FIFO_GY_DEC_8 = 5, 2357 LSM6DSL_FIFO_GY_DEC_16 = 6, 2358 LSM6DSL_FIFO_GY_DEC_32 = 7, 2359 LSM6DSL_FIFO_GY_DEC_ND = 8, /* ERROR CODE */ 2360 } lsm6dsl_dec_fifo_gyro_t; 2361 int32_t lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t *ctx, 2362 lsm6dsl_dec_fifo_gyro_t val); 2363 int32_t lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t *ctx, 2364 lsm6dsl_dec_fifo_gyro_t *val); 2365 2366 typedef enum 2367 { 2368 LSM6DSL_FIFO_DS3_DISABLE = 0, 2369 LSM6DSL_FIFO_DS3_NO_DEC = 1, 2370 LSM6DSL_FIFO_DS3_DEC_2 = 2, 2371 LSM6DSL_FIFO_DS3_DEC_3 = 3, 2372 LSM6DSL_FIFO_DS3_DEC_4 = 4, 2373 LSM6DSL_FIFO_DS3_DEC_8 = 5, 2374 LSM6DSL_FIFO_DS3_DEC_16 = 6, 2375 LSM6DSL_FIFO_DS3_DEC_32 = 7, 2376 LSM6DSL_FIFO_DS3_DEC_ND = 8, /* ERROR CODE */ 2377 } lsm6dsl_dec_ds3_fifo_t; 2378 int32_t lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, 2379 lsm6dsl_dec_ds3_fifo_t val); 2380 int32_t lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, 2381 lsm6dsl_dec_ds3_fifo_t *val); 2382 2383 typedef enum 2384 { 2385 LSM6DSL_FIFO_DS4_DISABLE = 0, 2386 LSM6DSL_FIFO_DS4_NO_DEC = 1, 2387 LSM6DSL_FIFO_DS4_DEC_2 = 2, 2388 LSM6DSL_FIFO_DS4_DEC_3 = 3, 2389 LSM6DSL_FIFO_DS4_DEC_4 = 4, 2390 LSM6DSL_FIFO_DS4_DEC_8 = 5, 2391 LSM6DSL_FIFO_DS4_DEC_16 = 6, 2392 LSM6DSL_FIFO_DS4_DEC_32 = 7, 2393 LSM6DSL_FIFO_DS4_DEC_ND = 8, /* ERROR CODE */ 2394 } lsm6dsl_dec_ds4_fifo_t; 2395 int32_t lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, 2396 lsm6dsl_dec_ds4_fifo_t val); 2397 int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, 2398 lsm6dsl_dec_ds4_fifo_t *val); 2399 2400 int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, 2401 uint8_t val); 2402 int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, 2403 uint8_t *val); 2404 2405 int32_t lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 2406 int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); 2407 2408 typedef enum 2409 { 2410 LSM6DSL_BYPASS_MODE = 0, 2411 LSM6DSL_FIFO_MODE = 1, 2412 LSM6DSL_STREAM_TO_FIFO_MODE = 3, 2413 LSM6DSL_BYPASS_TO_STREAM_MODE = 4, 2414 LSM6DSL_STREAM_MODE = 6, 2415 LSM6DSL_FIFO_MODE_ND = 8, /* ERROR CODE */ 2416 } lsm6dsl_fifo_mode_t; 2417 int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx, 2418 lsm6dsl_fifo_mode_t val); 2419 int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx, 2420 lsm6dsl_fifo_mode_t *val); 2421 2422 typedef enum 2423 { 2424 LSM6DSL_FIFO_DISABLE = 0, 2425 LSM6DSL_FIFO_12Hz5 = 1, 2426 LSM6DSL_FIFO_26Hz = 2, 2427 LSM6DSL_FIFO_52Hz = 3, 2428 LSM6DSL_FIFO_104Hz = 4, 2429 LSM6DSL_FIFO_208Hz = 5, 2430 LSM6DSL_FIFO_416Hz = 6, 2431 LSM6DSL_FIFO_833Hz = 7, 2432 LSM6DSL_FIFO_1k66Hz = 8, 2433 LSM6DSL_FIFO_3k33Hz = 9, 2434 LSM6DSL_FIFO_6k66Hz = 10, 2435 LSM6DSL_FIFO_RATE_ND = 11, /* ERROR CODE */ 2436 } lsm6dsl_odr_fifo_t; 2437 int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx, 2438 lsm6dsl_odr_fifo_t val); 2439 int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx, 2440 lsm6dsl_odr_fifo_t *val); 2441 2442 typedef enum 2443 { 2444 LSM6DSL_DEN_ACT_LOW = 0, 2445 LSM6DSL_DEN_ACT_HIGH = 1, 2446 LSM6DSL_DEN_POL_ND = 2, /* ERROR CODE */ 2447 } lsm6dsl_den_lh_t; 2448 int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx, 2449 lsm6dsl_den_lh_t val); 2450 int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx, 2451 lsm6dsl_den_lh_t *val); 2452 2453 typedef enum 2454 { 2455 LSM6DSL_DEN_DISABLE = 0, 2456 LSM6DSL_LEVEL_FIFO = 6, 2457 LSM6DSL_LEVEL_LETCHED = 3, 2458 LSM6DSL_LEVEL_TRIGGER = 2, 2459 LSM6DSL_EDGE_TRIGGER = 4, 2460 LSM6DSL_DEN_MODE_ND = 5, /* ERROR CODE */ 2461 } lsm6dsl_den_mode_t; 2462 int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx, 2463 lsm6dsl_den_mode_t val); 2464 int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx, 2465 lsm6dsl_den_mode_t *val); 2466 2467 typedef enum 2468 { 2469 LSM6DSL_STAMP_IN_GY_DATA = 0, 2470 LSM6DSL_STAMP_IN_XL_DATA = 1, 2471 LSM6DSL_STAMP_IN_GY_XL_DATA = 2, 2472 LSM6DSL_DEN_STAMP_ND = 3, /* ERROR CODE */ 2473 } lsm6dsl_den_xl_en_t; 2474 int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx, 2475 lsm6dsl_den_xl_en_t val); 2476 int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx, 2477 lsm6dsl_den_xl_en_t *val); 2478 2479 int32_t lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); 2480 int32_t lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); 2481 2482 int32_t lsm6dsl_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 2483 int32_t lsm6dsl_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); 2484 2485 int32_t lsm6dsl_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 2486 int32_t lsm6dsl_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); 2487 2488 int32_t lsm6dsl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2489 int32_t lsm6dsl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2490 2491 int32_t lsm6dsl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2492 int32_t lsm6dsl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2493 2494 int32_t lsm6dsl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 2495 int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 2496 2497 typedef enum 2498 { 2499 LSM6DSL_PEDO_AT_2g = 0, 2500 LSM6DSL_PEDO_AT_4g = 1, 2501 LSM6DSL_PEDO_FS_ND = 2, /* ERROR CODE */ 2502 } lsm6dsl_pedo_fs_t; 2503 int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx, 2504 lsm6dsl_pedo_fs_t val); 2505 int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx, 2506 lsm6dsl_pedo_fs_t *val); 2507 2508 int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx, 2509 uint8_t val); 2510 int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx, 2511 uint8_t *val); 2512 2513 int32_t lsm6dsl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 2514 int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); 2515 2516 int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx, 2517 uint8_t *buff); 2518 int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx, 2519 uint8_t *buff); 2520 2521 int32_t lsm6dsl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2522 int32_t lsm6dsl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2523 2524 int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx, 2525 uint8_t *buff); 2526 int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx, 2527 uint8_t *buff); 2528 2529 int32_t lsm6dsl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2530 int32_t lsm6dsl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2531 2532 int32_t lsm6dsl_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); 2533 int32_t lsm6dsl_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); 2534 2535 int32_t lsm6dsl_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff); 2536 int32_t lsm6dsl_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff); 2537 2538 int32_t lsm6dsl_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff); 2539 int32_t lsm6dsl_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff); 2540 2541 int32_t lsm6dsl_tilt_src_set(stmdev_ctx_t *ctx, 2542 lsm6dsl_a_wrist_tilt_mask_t *val); 2543 int32_t lsm6dsl_tilt_src_get(stmdev_ctx_t *ctx, 2544 lsm6dsl_a_wrist_tilt_mask_t *val); 2545 2546 int32_t lsm6dsl_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); 2547 int32_t lsm6dsl_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); 2548 2549 int32_t lsm6dsl_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); 2550 int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); 2551 2552 int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, 2553 uint8_t *buff); 2554 int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, 2555 uint8_t *buff); 2556 2557 int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val); 2558 int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val); 2559 2560 int32_t lsm6dsl_func_en_set(stmdev_ctx_t *ctx, uint8_t val); 2561 2562 int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, 2563 uint8_t val); 2564 int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, 2565 uint8_t *val); 2566 2567 typedef enum 2568 { 2569 LSM6DSL_RES_RATIO_2_11 = 0, 2570 LSM6DSL_RES_RATIO_2_12 = 1, 2571 LSM6DSL_RES_RATIO_2_13 = 2, 2572 LSM6DSL_RES_RATIO_2_14 = 3, 2573 LSM6DSL_RES_RATIO_ND = 4, /* ERROR CODE */ 2574 } lsm6dsl_rr_t; 2575 int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, 2576 lsm6dsl_rr_t val); 2577 int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, 2578 lsm6dsl_rr_t *val); 2579 2580 int32_t lsm6dsl_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 2581 int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 2582 2583 int32_t lsm6dsl_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 2584 int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 2585 2586 typedef enum 2587 { 2588 LSM6DSL_EXT_PULL_UP = 0, 2589 LSM6DSL_INTERNAL_PULL_UP = 1, 2590 LSM6DSL_SH_PIN_MODE = 2, /* ERROR CODE */ 2591 } lsm6dsl_pull_up_en_t; 2592 int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx, 2593 lsm6dsl_pull_up_en_t val); 2594 int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx, 2595 lsm6dsl_pull_up_en_t *val); 2596 2597 typedef enum 2598 { 2599 LSM6DSL_XL_GY_DRDY = 0, 2600 LSM6DSL_EXT_ON_INT2_PIN = 1, 2601 LSM6DSL_SH_SYNCRO_ND = 2, /* ERROR CODE */ 2602 } lsm6dsl_start_config_t; 2603 int32_t lsm6dsl_sh_syncro_mode_set(stmdev_ctx_t *ctx, 2604 lsm6dsl_start_config_t val); 2605 int32_t lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t *ctx, 2606 lsm6dsl_start_config_t *val); 2607 2608 int32_t lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 2609 int32_t lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 2610 2611 typedef struct 2612 { 2613 lsm6dsl_sensorhub1_reg_t sh_byte_1; 2614 lsm6dsl_sensorhub2_reg_t sh_byte_2; 2615 lsm6dsl_sensorhub3_reg_t sh_byte_3; 2616 lsm6dsl_sensorhub4_reg_t sh_byte_4; 2617 lsm6dsl_sensorhub5_reg_t sh_byte_5; 2618 lsm6dsl_sensorhub6_reg_t sh_byte_6; 2619 lsm6dsl_sensorhub7_reg_t sh_byte_7; 2620 lsm6dsl_sensorhub8_reg_t sh_byte_8; 2621 lsm6dsl_sensorhub9_reg_t sh_byte_9; 2622 lsm6dsl_sensorhub10_reg_t sh_byte_10; 2623 lsm6dsl_sensorhub11_reg_t sh_byte_11; 2624 lsm6dsl_sensorhub12_reg_t sh_byte_12; 2625 lsm6dsl_sensorhub13_reg_t sh_byte_13; 2626 lsm6dsl_sensorhub14_reg_t sh_byte_14; 2627 lsm6dsl_sensorhub15_reg_t sh_byte_15; 2628 lsm6dsl_sensorhub16_reg_t sh_byte_16; 2629 lsm6dsl_sensorhub17_reg_t sh_byte_17; 2630 lsm6dsl_sensorhub18_reg_t sh_byte_18; 2631 } lsm6dsl_emb_sh_read_t; 2632 int32_t lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t *ctx, 2633 lsm6dsl_emb_sh_read_t *val); 2634 2635 int32_t lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val); 2636 int32_t lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val); 2637 2638 int32_t lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val); 2639 int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx, 2640 uint8_t *val); 2641 2642 typedef enum 2643 { 2644 LSM6DSL_SLV_0 = 0, 2645 LSM6DSL_SLV_0_1 = 1, 2646 LSM6DSL_SLV_0_1_2 = 2, 2647 LSM6DSL_SLV_0_1_2_3 = 3, 2648 LSM6DSL_SLV_EN_ND = 4, /* ERROR CODE */ 2649 } lsm6dsl_aux_sens_on_t; 2650 int32_t lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, 2651 lsm6dsl_aux_sens_on_t val); 2652 int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, 2653 lsm6dsl_aux_sens_on_t *val); 2654 2655 typedef struct 2656 { 2657 uint8_t slv0_add; 2658 uint8_t slv0_subadd; 2659 uint8_t slv0_data; 2660 } lsm6dsl_sh_cfg_write_t; 2661 int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx, 2662 lsm6dsl_sh_cfg_write_t *val); 2663 2664 typedef struct 2665 { 2666 uint8_t slv_add; 2667 uint8_t slv_subadd; 2668 uint8_t slv_len; 2669 } lsm6dsl_sh_cfg_read_t; 2670 int32_t lsm6dsl_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 2671 lsm6dsl_sh_cfg_read_t *val); 2672 int32_t lsm6dsl_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 2673 lsm6dsl_sh_cfg_read_t *val); 2674 int32_t lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 2675 lsm6dsl_sh_cfg_read_t *val); 2676 int32_t lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 2677 lsm6dsl_sh_cfg_read_t *val); 2678 2679 typedef enum 2680 { 2681 LSM6DSL_SL0_NO_DEC = 0, 2682 LSM6DSL_SL0_DEC_2 = 1, 2683 LSM6DSL_SL0_DEC_4 = 2, 2684 LSM6DSL_SL0_DEC_8 = 3, 2685 LSM6DSL_SL0_DEC_ND = 4, /* ERROR CODE */ 2686 } lsm6dsl_slave0_rate_t; 2687 int32_t lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t *ctx, 2688 lsm6dsl_slave0_rate_t val); 2689 int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx, 2690 lsm6dsl_slave0_rate_t *val); 2691 2692 typedef enum 2693 { 2694 LSM6DSL_EACH_SH_CYCLE = 0, 2695 LSM6DSL_ONLY_FIRST_CYCLE = 1, 2696 LSM6DSL_SH_WR_MODE_ND = 2, /* ERROR CODE */ 2697 } lsm6dsl_write_once_t; 2698 int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx, 2699 lsm6dsl_write_once_t val); 2700 int32_t lsm6dsl_sh_write_mode_get(stmdev_ctx_t *ctx, 2701 lsm6dsl_write_once_t *val); 2702 2703 typedef enum 2704 { 2705 LSM6DSL_SL1_NO_DEC = 0, 2706 LSM6DSL_SL1_DEC_2 = 1, 2707 LSM6DSL_SL1_DEC_4 = 2, 2708 LSM6DSL_SL1_DEC_8 = 3, 2709 LSM6DSL_SL1_DEC_ND = 4, /* ERROR CODE */ 2710 } lsm6dsl_slave1_rate_t; 2711 int32_t lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t *ctx, 2712 lsm6dsl_slave1_rate_t val); 2713 int32_t lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t *ctx, 2714 lsm6dsl_slave1_rate_t *val); 2715 2716 typedef enum 2717 { 2718 LSM6DSL_SL2_NO_DEC = 0, 2719 LSM6DSL_SL2_DEC_2 = 1, 2720 LSM6DSL_SL2_DEC_4 = 2, 2721 LSM6DSL_SL2_DEC_8 = 3, 2722 LSM6DSL_SL2_DEC_ND = 4, /* ERROR CODE */ 2723 } lsm6dsl_slave2_rate_t; 2724 int32_t lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t *ctx, 2725 lsm6dsl_slave2_rate_t val); 2726 int32_t lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t *ctx, 2727 lsm6dsl_slave2_rate_t *val); 2728 2729 typedef enum 2730 { 2731 LSM6DSL_SL3_NO_DEC = 0, 2732 LSM6DSL_SL3_DEC_2 = 1, 2733 LSM6DSL_SL3_DEC_4 = 2, 2734 LSM6DSL_SL3_DEC_8 = 3, 2735 LSM6DSL_SL3_DEC_ND = 4, /* ERROR CODE */ 2736 } lsm6dsl_slave3_rate_t; 2737 int32_t lsm6dsl_sh_slave_3_dec_set(stmdev_ctx_t *ctx, 2738 lsm6dsl_slave3_rate_t val); 2739 int32_t lsm6dsl_sh_slave_3_dec_get(stmdev_ctx_t *ctx, 2740 lsm6dsl_slave3_rate_t *val); 2741 2742 /** 2743 * @} 2744 * 2745 */ 2746 2747 #ifdef __cplusplus 2748 } 2749 #endif 2750 2751 #endif /* LSM6DSL_DRIVER_H */ 2752 2753 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2754
