1 /** 2 ****************************************************************************** 3 * @file lsm6ds3tr_c_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6ds3tr_c_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DS3TR_C_DRIVER_H 23 #define LSM6DS3TR_C_DRIVER_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DS3TR_C 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DS3TR_C_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DS3TR_C_I2C_ADD_L 0xD5U 173 #define LSM6DS3TR_C_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DS3TR_C_ID 0x6AU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define LSM6DS3TR_C_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 5; 188 uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ 191 uint8_t not_used_01 : 5; 192 #endif /* DRV_BYTE_ORDER */ 193 } lsm6ds3tr_c_func_cfg_access_t; 194 195 #define LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME 0x04U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t tph : 4; 200 uint8_t not_used_01 : 4; 201 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 202 uint8_t not_used_01 : 4; 203 uint8_t tph : 4; 204 #endif /* DRV_BYTE_ORDER */ 205 } lsm6ds3tr_c_sensor_sync_time_frame_t; 206 207 #define LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO 0x05U 208 typedef struct 209 { 210 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 211 uint8_t rr : 2; 212 uint8_t not_used_01 : 6; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t not_used_01 : 6; 215 uint8_t rr : 2; 216 #endif /* DRV_BYTE_ORDER */ 217 } lsm6ds3tr_c_sensor_sync_res_ratio_t; 218 219 #define LSM6DS3TR_C_FIFO_CTRL1 0x06U 220 typedef struct 221 { 222 uint8_t fth : 8; /* + FIFO_CTRL2(fth) */ 223 } lsm6ds3tr_c_fifo_ctrl1_t; 224 225 #define LSM6DS3TR_C_FIFO_CTRL2 0x07U 226 typedef struct 227 { 228 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 229 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 230 uint8_t fifo_temp_en : 1; 231 uint8_t not_used_01 : 2; 232 uint8_t timer_pedo_fifo_drdy : 1; 233 uint8_t timer_pedo_fifo_en : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t timer_pedo_fifo_en : 1; 236 uint8_t timer_pedo_fifo_drdy : 1; 237 uint8_t not_used_01 : 2; 238 uint8_t fifo_temp_en : 1; 239 uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ 240 #endif /* DRV_BYTE_ORDER */ 241 } lsm6ds3tr_c_fifo_ctrl2_t; 242 243 #define LSM6DS3TR_C_FIFO_CTRL3 0x08U 244 typedef struct 245 { 246 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 247 uint8_t dec_fifo_xl : 3; 248 uint8_t dec_fifo_gyro : 3; 249 uint8_t not_used_01 : 2; 250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 251 uint8_t not_used_01 : 2; 252 uint8_t dec_fifo_gyro : 3; 253 uint8_t dec_fifo_xl : 3; 254 #endif /* DRV_BYTE_ORDER */ 255 } lsm6ds3tr_c_fifo_ctrl3_t; 256 257 #define LSM6DS3TR_C_FIFO_CTRL4 0x09U 258 typedef struct 259 { 260 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 261 uint8_t dec_ds3_fifo : 3; 262 uint8_t dec_ds4_fifo : 3; 263 uint8_t only_high_data : 1; 264 uint8_t stop_on_fth : 1; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t stop_on_fth : 1; 267 uint8_t only_high_data : 1; 268 uint8_t dec_ds4_fifo : 3; 269 uint8_t dec_ds3_fifo : 3; 270 #endif /* DRV_BYTE_ORDER */ 271 } lsm6ds3tr_c_fifo_ctrl4_t; 272 273 #define LSM6DS3TR_C_FIFO_CTRL5 0x0AU 274 typedef struct 275 { 276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 277 uint8_t fifo_mode : 3; 278 uint8_t odr_fifo : 4; 279 uint8_t not_used_01 : 1; 280 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 281 uint8_t not_used_01 : 1; 282 uint8_t odr_fifo : 4; 283 uint8_t fifo_mode : 3; 284 #endif /* DRV_BYTE_ORDER */ 285 } lsm6ds3tr_c_fifo_ctrl5_t; 286 287 #define LSM6DS3TR_C_DRDY_PULSE_CFG_G 0x0BU 288 typedef struct 289 { 290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 291 uint8_t int2_wrist_tilt : 1; 292 uint8_t not_used_01 : 6; 293 uint8_t drdy_pulsed : 1; 294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 295 uint8_t drdy_pulsed : 1; 296 uint8_t not_used_01 : 6; 297 uint8_t int2_wrist_tilt : 1; 298 #endif /* DRV_BYTE_ORDER */ 299 } lsm6ds3tr_c_drdy_pulse_cfg_g_t; 300 301 #define LSM6DS3TR_C_INT1_CTRL 0x0DU 302 typedef struct 303 { 304 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 305 uint8_t int1_drdy_xl : 1; 306 uint8_t int1_drdy_g : 1; 307 uint8_t int1_boot : 1; 308 uint8_t int1_fth : 1; 309 uint8_t int1_fifo_ovr : 1; 310 uint8_t int1_full_flag : 1; 311 uint8_t int1_sign_mot : 1; 312 uint8_t int1_step_detector : 1; 313 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 314 uint8_t int1_step_detector : 1; 315 uint8_t int1_sign_mot : 1; 316 uint8_t int1_full_flag : 1; 317 uint8_t int1_fifo_ovr : 1; 318 uint8_t int1_fth : 1; 319 uint8_t int1_boot : 1; 320 uint8_t int1_drdy_g : 1; 321 uint8_t int1_drdy_xl : 1; 322 #endif /* DRV_BYTE_ORDER */ 323 } lsm6ds3tr_c_int1_ctrl_t; 324 325 #define LSM6DS3TR_C_INT2_CTRL 0x0EU 326 typedef struct 327 { 328 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 329 uint8_t int2_drdy_xl : 1; 330 uint8_t int2_drdy_g : 1; 331 uint8_t int2_drdy_temp : 1; 332 uint8_t int2_fth : 1; 333 uint8_t int2_fifo_ovr : 1; 334 uint8_t int2_full_flag : 1; 335 uint8_t int2_step_count_ov : 1; 336 uint8_t int2_step_delta : 1; 337 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 338 uint8_t int2_step_delta : 1; 339 uint8_t int2_step_count_ov : 1; 340 uint8_t int2_full_flag : 1; 341 uint8_t int2_fifo_ovr : 1; 342 uint8_t int2_fth : 1; 343 uint8_t int2_drdy_temp : 1; 344 uint8_t int2_drdy_g : 1; 345 uint8_t int2_drdy_xl : 1; 346 #endif /* DRV_BYTE_ORDER */ 347 } lsm6ds3tr_c_int2_ctrl_t; 348 349 #define LSM6DS3TR_C_WHO_AM_I 0x0FU 350 #define LSM6DS3TR_C_CTRL1_XL 0x10U 351 typedef struct 352 { 353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 354 uint8_t bw0_xl : 1; 355 uint8_t lpf1_bw_sel : 1; 356 uint8_t fs_xl : 2; 357 uint8_t odr_xl : 4; 358 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 359 uint8_t odr_xl : 4; 360 uint8_t fs_xl : 2; 361 uint8_t lpf1_bw_sel : 1; 362 uint8_t bw0_xl : 1; 363 #endif /* DRV_BYTE_ORDER */ 364 } lsm6ds3tr_c_ctrl1_xl_t; 365 366 #define LSM6DS3TR_C_CTRL2_G 0x11U 367 typedef struct 368 { 369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 370 uint8_t not_used_01 : 1; 371 uint8_t fs_g : 3; /* fs_g + fs_125 */ 372 uint8_t odr_g : 4; 373 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 374 uint8_t odr_g : 4; 375 uint8_t fs_g : 3; /* fs_g + fs_125 */ 376 uint8_t not_used_01 : 1; 377 #endif /* DRV_BYTE_ORDER */ 378 } lsm6ds3tr_c_ctrl2_g_t; 379 380 #define LSM6DS3TR_C_CTRL3_C 0x12U 381 typedef struct 382 { 383 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 384 uint8_t sw_reset : 1; 385 uint8_t ble : 1; 386 uint8_t if_inc : 1; 387 uint8_t sim : 1; 388 uint8_t pp_od : 1; 389 uint8_t h_lactive : 1; 390 uint8_t bdu : 1; 391 uint8_t boot : 1; 392 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 393 uint8_t boot : 1; 394 uint8_t bdu : 1; 395 uint8_t h_lactive : 1; 396 uint8_t pp_od : 1; 397 uint8_t sim : 1; 398 uint8_t if_inc : 1; 399 uint8_t ble : 1; 400 uint8_t sw_reset : 1; 401 #endif /* DRV_BYTE_ORDER */ 402 } lsm6ds3tr_c_ctrl3_c_t; 403 404 #define LSM6DS3TR_C_CTRL4_C 0x13U 405 typedef struct 406 { 407 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 408 uint8_t not_used_01 : 1; 409 uint8_t lpf1_sel_g : 1; 410 uint8_t i2c_disable : 1; 411 uint8_t drdy_mask : 1; 412 uint8_t den_drdy_int1 : 1; 413 uint8_t int2_on_int1 : 1; 414 uint8_t sleep : 1; 415 uint8_t den_xl_en : 1; 416 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 417 uint8_t den_xl_en : 1; 418 uint8_t sleep : 1; 419 uint8_t int2_on_int1 : 1; 420 uint8_t den_drdy_int1 : 1; 421 uint8_t drdy_mask : 1; 422 uint8_t i2c_disable : 1; 423 uint8_t lpf1_sel_g : 1; 424 uint8_t not_used_01 : 1; 425 #endif /* DRV_BYTE_ORDER */ 426 } lsm6ds3tr_c_ctrl4_c_t; 427 428 #define LSM6DS3TR_C_CTRL5_C 0x14U 429 typedef struct 430 { 431 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 432 uint8_t st_xl : 2; 433 uint8_t st_g : 2; 434 uint8_t den_lh : 1; 435 uint8_t rounding : 3; 436 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 437 uint8_t rounding : 3; 438 uint8_t den_lh : 1; 439 uint8_t st_g : 2; 440 uint8_t st_xl : 2; 441 #endif /* DRV_BYTE_ORDER */ 442 } lsm6ds3tr_c_ctrl5_c_t; 443 444 #define LSM6DS3TR_C_CTRL6_C 0x15U 445 typedef struct 446 { 447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 448 uint8_t ftype : 2; 449 uint8_t not_used_01 : 1; 450 uint8_t usr_off_w : 1; 451 uint8_t xl_hm_mode : 1; 452 uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ 453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 454 uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ 455 uint8_t xl_hm_mode : 1; 456 uint8_t usr_off_w : 1; 457 uint8_t not_used_01 : 1; 458 uint8_t ftype : 2; 459 #endif /* DRV_BYTE_ORDER */ 460 } lsm6ds3tr_c_ctrl6_c_t; 461 462 #define LSM6DS3TR_C_CTRL7_G 0x16U 463 typedef struct 464 { 465 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 466 uint8_t not_used_01 : 2; 467 uint8_t rounding_status : 1; 468 uint8_t not_used_02 : 1; 469 uint8_t hpm_g : 2; 470 uint8_t hp_en_g : 1; 471 uint8_t g_hm_mode : 1; 472 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 473 uint8_t g_hm_mode : 1; 474 uint8_t hp_en_g : 1; 475 uint8_t hpm_g : 2; 476 uint8_t not_used_02 : 1; 477 uint8_t rounding_status : 1; 478 uint8_t not_used_01 : 2; 479 #endif /* DRV_BYTE_ORDER */ 480 } lsm6ds3tr_c_ctrl7_g_t; 481 482 #define LSM6DS3TR_C_CTRL8_XL 0x17U 483 typedef struct 484 { 485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 486 uint8_t low_pass_on_6d : 1; 487 uint8_t not_used_01 : 1; 488 uint8_t hp_slope_xl_en : 1; 489 uint8_t input_composite : 1; 490 uint8_t hp_ref_mode : 1; 491 uint8_t hpcf_xl : 2; 492 uint8_t lpf2_xl_en : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t lpf2_xl_en : 1; 495 uint8_t hpcf_xl : 2; 496 uint8_t hp_ref_mode : 1; 497 uint8_t input_composite : 1; 498 uint8_t hp_slope_xl_en : 1; 499 uint8_t not_used_01 : 1; 500 uint8_t low_pass_on_6d : 1; 501 #endif /* DRV_BYTE_ORDER */ 502 } lsm6ds3tr_c_ctrl8_xl_t; 503 504 #define LSM6DS3TR_C_CTRL9_XL 0x18U 505 typedef struct 506 { 507 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 508 uint8_t not_used_01 : 2; 509 uint8_t soft_en : 1; 510 uint8_t not_used_02 : 1; 511 uint8_t den_xl_g : 1; 512 uint8_t den_z : 1; 513 uint8_t den_y : 1; 514 uint8_t den_x : 1; 515 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 516 uint8_t den_x : 1; 517 uint8_t den_y : 1; 518 uint8_t den_z : 1; 519 uint8_t den_xl_g : 1; 520 uint8_t not_used_02 : 1; 521 uint8_t soft_en : 1; 522 uint8_t not_used_01 : 2; 523 #endif /* DRV_BYTE_ORDER */ 524 } lsm6ds3tr_c_ctrl9_xl_t; 525 526 #define LSM6DS3TR_C_CTRL10_C 0x19U 527 typedef struct 528 { 529 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 530 uint8_t sign_motion_en : 1; 531 uint8_t pedo_rst_step : 1; 532 uint8_t func_en : 1; 533 uint8_t tilt_en : 1; 534 uint8_t pedo_en : 1; 535 uint8_t timer_en : 1; 536 uint8_t not_used_01 : 1; 537 uint8_t wrist_tilt_en : 1; 538 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 539 uint8_t wrist_tilt_en : 1; 540 uint8_t not_used_01 : 1; 541 uint8_t timer_en : 1; 542 uint8_t pedo_en : 1; 543 uint8_t tilt_en : 1; 544 uint8_t func_en : 1; 545 uint8_t pedo_rst_step : 1; 546 uint8_t sign_motion_en : 1; 547 #endif /* DRV_BYTE_ORDER */ 548 } lsm6ds3tr_c_ctrl10_c_t; 549 550 #define LSM6DS3TR_C_MASTER_CONFIG 0x1AU 551 typedef struct 552 { 553 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 554 uint8_t master_on : 1; 555 uint8_t iron_en : 1; 556 uint8_t pass_through_mode : 1; 557 uint8_t pull_up_en : 1; 558 uint8_t start_config : 1; 559 uint8_t not_used_01 : 1; 560 uint8_t data_valid_sel_fifo : 1; 561 uint8_t drdy_on_int1 : 1; 562 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 563 uint8_t drdy_on_int1 : 1; 564 uint8_t data_valid_sel_fifo : 1; 565 uint8_t not_used_01 : 1; 566 uint8_t start_config : 1; 567 uint8_t pull_up_en : 1; 568 uint8_t pass_through_mode : 1; 569 uint8_t iron_en : 1; 570 uint8_t master_on : 1; 571 #endif /* DRV_BYTE_ORDER */ 572 } lsm6ds3tr_c_master_config_t; 573 574 #define LSM6DS3TR_C_WAKE_UP_SRC 0x1BU 575 typedef struct 576 { 577 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 578 uint8_t z_wu : 1; 579 uint8_t y_wu : 1; 580 uint8_t x_wu : 1; 581 uint8_t wu_ia : 1; 582 uint8_t sleep_state_ia : 1; 583 uint8_t ff_ia : 1; 584 uint8_t not_used_01 : 2; 585 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 586 uint8_t not_used_01 : 2; 587 uint8_t ff_ia : 1; 588 uint8_t sleep_state_ia : 1; 589 uint8_t wu_ia : 1; 590 uint8_t x_wu : 1; 591 uint8_t y_wu : 1; 592 uint8_t z_wu : 1; 593 #endif /* DRV_BYTE_ORDER */ 594 } lsm6ds3tr_c_wake_up_src_t; 595 596 #define LSM6DS3TR_C_TAP_SRC 0x1CU 597 typedef struct 598 { 599 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 600 uint8_t z_tap : 1; 601 uint8_t y_tap : 1; 602 uint8_t x_tap : 1; 603 uint8_t tap_sign : 1; 604 uint8_t double_tap : 1; 605 uint8_t single_tap : 1; 606 uint8_t tap_ia : 1; 607 uint8_t not_used_01 : 1; 608 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 609 uint8_t not_used_01 : 1; 610 uint8_t tap_ia : 1; 611 uint8_t single_tap : 1; 612 uint8_t double_tap : 1; 613 uint8_t tap_sign : 1; 614 uint8_t x_tap : 1; 615 uint8_t y_tap : 1; 616 uint8_t z_tap : 1; 617 #endif /* DRV_BYTE_ORDER */ 618 } lsm6ds3tr_c_tap_src_t; 619 620 #define LSM6DS3TR_C_D6D_SRC 0x1DU 621 typedef struct 622 { 623 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 624 uint8_t xl : 1; 625 uint8_t xh : 1; 626 uint8_t yl : 1; 627 uint8_t yh : 1; 628 uint8_t zl : 1; 629 uint8_t zh : 1; 630 uint8_t d6d_ia : 1; 631 uint8_t den_drdy : 1; 632 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 633 uint8_t den_drdy : 1; 634 uint8_t d6d_ia : 1; 635 uint8_t zh : 1; 636 uint8_t zl : 1; 637 uint8_t yh : 1; 638 uint8_t yl : 1; 639 uint8_t xh : 1; 640 uint8_t xl : 1; 641 #endif /* DRV_BYTE_ORDER */ 642 } lsm6ds3tr_c_d6d_src_t; 643 644 #define LSM6DS3TR_C_STATUS_REG 0x1EU 645 typedef struct 646 { 647 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 648 uint8_t xlda : 1; 649 uint8_t gda : 1; 650 uint8_t tda : 1; 651 uint8_t not_used_01 : 5; 652 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 653 uint8_t not_used_01 : 5; 654 uint8_t tda : 1; 655 uint8_t gda : 1; 656 uint8_t xlda : 1; 657 #endif /* DRV_BYTE_ORDER */ 658 } lsm6ds3tr_c_status_reg_t; 659 660 #define LSM6DS3TR_C_OUT_TEMP_L 0x20U 661 #define LSM6DS3TR_C_OUT_TEMP_H 0x21U 662 #define LSM6DS3TR_C_OUTX_L_G 0x22U 663 #define LSM6DS3TR_C_OUTX_H_G 0x23U 664 #define LSM6DS3TR_C_OUTY_L_G 0x24U 665 #define LSM6DS3TR_C_OUTY_H_G 0x25U 666 #define LSM6DS3TR_C_OUTZ_L_G 0x26U 667 #define LSM6DS3TR_C_OUTZ_H_G 0x27U 668 #define LSM6DS3TR_C_OUTX_L_XL 0x28U 669 #define LSM6DS3TR_C_OUTX_H_XL 0x29U 670 #define LSM6DS3TR_C_OUTY_L_XL 0x2AU 671 #define LSM6DS3TR_C_OUTY_H_XL 0x2BU 672 #define LSM6DS3TR_C_OUTZ_L_XL 0x2CU 673 #define LSM6DS3TR_C_OUTZ_H_XL 0x2DU 674 #define LSM6DS3TR_C_SENSORHUB1_REG 0x2EU 675 typedef struct 676 { 677 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 678 uint8_t bit0 : 1; 679 uint8_t bit1 : 1; 680 uint8_t bit2 : 1; 681 uint8_t bit3 : 1; 682 uint8_t bit4 : 1; 683 uint8_t bit5 : 1; 684 uint8_t bit6 : 1; 685 uint8_t bit7 : 1; 686 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 687 uint8_t bit7 : 1; 688 uint8_t bit6 : 1; 689 uint8_t bit5 : 1; 690 uint8_t bit4 : 1; 691 uint8_t bit3 : 1; 692 uint8_t bit2 : 1; 693 uint8_t bit1 : 1; 694 uint8_t bit0 : 1; 695 #endif /* DRV_BYTE_ORDER */ 696 } lsm6ds3tr_c_sensorhub1_reg_t; 697 698 #define LSM6DS3TR_C_SENSORHUB2_REG 0x2FU 699 typedef struct 700 { 701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 702 uint8_t bit0 : 1; 703 uint8_t bit1 : 1; 704 uint8_t bit2 : 1; 705 uint8_t bit3 : 1; 706 uint8_t bit4 : 1; 707 uint8_t bit5 : 1; 708 uint8_t bit6 : 1; 709 uint8_t bit7 : 1; 710 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 711 uint8_t bit7 : 1; 712 uint8_t bit6 : 1; 713 uint8_t bit5 : 1; 714 uint8_t bit4 : 1; 715 uint8_t bit3 : 1; 716 uint8_t bit2 : 1; 717 uint8_t bit1 : 1; 718 uint8_t bit0 : 1; 719 #endif /* DRV_BYTE_ORDER */ 720 } lsm6ds3tr_c_sensorhub2_reg_t; 721 722 #define LSM6DS3TR_C_SENSORHUB3_REG 0x30U 723 typedef struct 724 { 725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 726 uint8_t bit0 : 1; 727 uint8_t bit1 : 1; 728 uint8_t bit2 : 1; 729 uint8_t bit3 : 1; 730 uint8_t bit4 : 1; 731 uint8_t bit5 : 1; 732 uint8_t bit6 : 1; 733 uint8_t bit7 : 1; 734 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 735 uint8_t bit7 : 1; 736 uint8_t bit6 : 1; 737 uint8_t bit5 : 1; 738 uint8_t bit4 : 1; 739 uint8_t bit3 : 1; 740 uint8_t bit2 : 1; 741 uint8_t bit1 : 1; 742 uint8_t bit0 : 1; 743 #endif /* DRV_BYTE_ORDER */ 744 } lsm6ds3tr_c_sensorhub3_reg_t; 745 746 #define LSM6DS3TR_C_SENSORHUB4_REG 0x31U 747 typedef struct 748 { 749 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 750 uint8_t bit0 : 1; 751 uint8_t bit1 : 1; 752 uint8_t bit2 : 1; 753 uint8_t bit3 : 1; 754 uint8_t bit4 : 1; 755 uint8_t bit5 : 1; 756 uint8_t bit6 : 1; 757 uint8_t bit7 : 1; 758 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 759 uint8_t bit7 : 1; 760 uint8_t bit6 : 1; 761 uint8_t bit5 : 1; 762 uint8_t bit4 : 1; 763 uint8_t bit3 : 1; 764 uint8_t bit2 : 1; 765 uint8_t bit1 : 1; 766 uint8_t bit0 : 1; 767 #endif /* DRV_BYTE_ORDER */ 768 } lsm6ds3tr_c_sensorhub4_reg_t; 769 770 #define LSM6DS3TR_C_SENSORHUB5_REG 0x32U 771 typedef struct 772 { 773 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 774 uint8_t bit0 : 1; 775 uint8_t bit1 : 1; 776 uint8_t bit2 : 1; 777 uint8_t bit3 : 1; 778 uint8_t bit4 : 1; 779 uint8_t bit5 : 1; 780 uint8_t bit6 : 1; 781 uint8_t bit7 : 1; 782 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 783 uint8_t bit7 : 1; 784 uint8_t bit6 : 1; 785 uint8_t bit5 : 1; 786 uint8_t bit4 : 1; 787 uint8_t bit3 : 1; 788 uint8_t bit2 : 1; 789 uint8_t bit1 : 1; 790 uint8_t bit0 : 1; 791 #endif /* DRV_BYTE_ORDER */ 792 } lsm6ds3tr_c_sensorhub5_reg_t; 793 794 #define LSM6DS3TR_C_SENSORHUB6_REG 0x33U 795 typedef struct 796 { 797 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 798 uint8_t bit0 : 1; 799 uint8_t bit1 : 1; 800 uint8_t bit2 : 1; 801 uint8_t bit3 : 1; 802 uint8_t bit4 : 1; 803 uint8_t bit5 : 1; 804 uint8_t bit6 : 1; 805 uint8_t bit7 : 1; 806 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 807 uint8_t bit7 : 1; 808 uint8_t bit6 : 1; 809 uint8_t bit5 : 1; 810 uint8_t bit4 : 1; 811 uint8_t bit3 : 1; 812 uint8_t bit2 : 1; 813 uint8_t bit1 : 1; 814 uint8_t bit0 : 1; 815 #endif /* DRV_BYTE_ORDER */ 816 } lsm6ds3tr_c_sensorhub6_reg_t; 817 818 #define LSM6DS3TR_C_SENSORHUB7_REG 0x34U 819 typedef struct 820 { 821 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 822 uint8_t bit0 : 1; 823 uint8_t bit1 : 1; 824 uint8_t bit2 : 1; 825 uint8_t bit3 : 1; 826 uint8_t bit4 : 1; 827 uint8_t bit5 : 1; 828 uint8_t bit6 : 1; 829 uint8_t bit7 : 1; 830 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 831 uint8_t bit7 : 1; 832 uint8_t bit6 : 1; 833 uint8_t bit5 : 1; 834 uint8_t bit4 : 1; 835 uint8_t bit3 : 1; 836 uint8_t bit2 : 1; 837 uint8_t bit1 : 1; 838 uint8_t bit0 : 1; 839 #endif /* DRV_BYTE_ORDER */ 840 } lsm6ds3tr_c_sensorhub7_reg_t; 841 842 #define LSM6DS3TR_C_SENSORHUB8_REG 0x35U 843 typedef struct 844 { 845 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 846 uint8_t bit0 : 1; 847 uint8_t bit1 : 1; 848 uint8_t bit2 : 1; 849 uint8_t bit3 : 1; 850 uint8_t bit4 : 1; 851 uint8_t bit5 : 1; 852 uint8_t bit6 : 1; 853 uint8_t bit7 : 1; 854 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 855 uint8_t bit7 : 1; 856 uint8_t bit6 : 1; 857 uint8_t bit5 : 1; 858 uint8_t bit4 : 1; 859 uint8_t bit3 : 1; 860 uint8_t bit2 : 1; 861 uint8_t bit1 : 1; 862 uint8_t bit0 : 1; 863 #endif /* DRV_BYTE_ORDER */ 864 } lsm6ds3tr_c_sensorhub8_reg_t; 865 866 #define LSM6DS3TR_C_SENSORHUB9_REG 0x36U 867 typedef struct 868 { 869 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 870 uint8_t bit0 : 1; 871 uint8_t bit1 : 1; 872 uint8_t bit2 : 1; 873 uint8_t bit3 : 1; 874 uint8_t bit4 : 1; 875 uint8_t bit5 : 1; 876 uint8_t bit6 : 1; 877 uint8_t bit7 : 1; 878 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 879 uint8_t bit7 : 1; 880 uint8_t bit6 : 1; 881 uint8_t bit5 : 1; 882 uint8_t bit4 : 1; 883 uint8_t bit3 : 1; 884 uint8_t bit2 : 1; 885 uint8_t bit1 : 1; 886 uint8_t bit0 : 1; 887 #endif /* DRV_BYTE_ORDER */ 888 } lsm6ds3tr_c_sensorhub9_reg_t; 889 890 #define LSM6DS3TR_C_SENSORHUB10_REG 0x37U 891 typedef struct 892 { 893 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 894 uint8_t bit0 : 1; 895 uint8_t bit1 : 1; 896 uint8_t bit2 : 1; 897 uint8_t bit3 : 1; 898 uint8_t bit4 : 1; 899 uint8_t bit5 : 1; 900 uint8_t bit6 : 1; 901 uint8_t bit7 : 1; 902 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 903 uint8_t bit7 : 1; 904 uint8_t bit6 : 1; 905 uint8_t bit5 : 1; 906 uint8_t bit4 : 1; 907 uint8_t bit3 : 1; 908 uint8_t bit2 : 1; 909 uint8_t bit1 : 1; 910 uint8_t bit0 : 1; 911 #endif /* DRV_BYTE_ORDER */ 912 } lsm6ds3tr_c_sensorhub10_reg_t; 913 914 #define LSM6DS3TR_C_SENSORHUB11_REG 0x38U 915 typedef struct 916 { 917 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 918 uint8_t bit0 : 1; 919 uint8_t bit1 : 1; 920 uint8_t bit2 : 1; 921 uint8_t bit3 : 1; 922 uint8_t bit4 : 1; 923 uint8_t bit5 : 1; 924 uint8_t bit6 : 1; 925 uint8_t bit7 : 1; 926 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 927 uint8_t bit7 : 1; 928 uint8_t bit6 : 1; 929 uint8_t bit5 : 1; 930 uint8_t bit4 : 1; 931 uint8_t bit3 : 1; 932 uint8_t bit2 : 1; 933 uint8_t bit1 : 1; 934 uint8_t bit0 : 1; 935 #endif /* DRV_BYTE_ORDER */ 936 } lsm6ds3tr_c_sensorhub11_reg_t; 937 938 #define LSM6DS3TR_C_SENSORHUB12_REG 0x39U 939 typedef struct 940 { 941 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 942 uint8_t bit0 : 1; 943 uint8_t bit1 : 1; 944 uint8_t bit2 : 1; 945 uint8_t bit3 : 1; 946 uint8_t bit4 : 1; 947 uint8_t bit5 : 1; 948 uint8_t bit6 : 1; 949 uint8_t bit7 : 1; 950 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 951 uint8_t bit7 : 1; 952 uint8_t bit6 : 1; 953 uint8_t bit5 : 1; 954 uint8_t bit4 : 1; 955 uint8_t bit3 : 1; 956 uint8_t bit2 : 1; 957 uint8_t bit1 : 1; 958 uint8_t bit0 : 1; 959 #endif /* DRV_BYTE_ORDER */ 960 } lsm6ds3tr_c_sensorhub12_reg_t; 961 962 #define LSM6DS3TR_C_FIFO_STATUS1 0x3AU 963 typedef struct 964 { 965 uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */ 966 } lsm6ds3tr_c_fifo_status1_t; 967 968 #define LSM6DS3TR_C_FIFO_STATUS2 0x3BU 969 typedef struct 970 { 971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 972 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 973 uint8_t not_used_01 : 1; 974 uint8_t fifo_empty : 1; 975 uint8_t fifo_full_smart : 1; 976 uint8_t over_run : 1; 977 uint8_t waterm : 1; 978 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 979 uint8_t waterm : 1; 980 uint8_t over_run : 1; 981 uint8_t fifo_full_smart : 1; 982 uint8_t fifo_empty : 1; 983 uint8_t not_used_01 : 1; 984 uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ 985 #endif /* DRV_BYTE_ORDER */ 986 } lsm6ds3tr_c_fifo_status2_t; 987 988 #define LSM6DS3TR_C_FIFO_STATUS3 0x3CU 989 typedef struct 990 { 991 uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ 992 } lsm6ds3tr_c_fifo_status3_t; 993 994 #define LSM6DS3TR_C_FIFO_STATUS4 0x3DU 995 typedef struct 996 { 997 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 998 uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ 999 uint8_t not_used_01 : 6; 1000 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1001 uint8_t not_used_01 : 6; 1002 uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ 1003 #endif /* DRV_BYTE_ORDER */ 1004 } lsm6ds3tr_c_fifo_status4_t; 1005 1006 #define LSM6DS3TR_C_FIFO_DATA_OUT_L 0x3EU 1007 #define LSM6DS3TR_C_FIFO_DATA_OUT_H 0x3FU 1008 #define LSM6DS3TR_C_TIMESTAMP0_REG 0x40U 1009 #define LSM6DS3TR_C_TIMESTAMP1_REG 0x41U 1010 #define LSM6DS3TR_C_TIMESTAMP2_REG 0x42U 1011 #define LSM6DS3TR_C_STEP_TIMESTAMP_L 0x49U 1012 #define LSM6DS3TR_C_STEP_TIMESTAMP_H 0x4AU 1013 #define LSM6DS3TR_C_STEP_COUNTER_L 0x4BU 1014 #define LSM6DS3TR_C_STEP_COUNTER_H 0x4CU 1015 1016 #define LSM6DS3TR_C_SENSORHUB13_REG 0x4DU 1017 typedef struct 1018 { 1019 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1020 uint8_t bit0 : 1; 1021 uint8_t bit1 : 1; 1022 uint8_t bit2 : 1; 1023 uint8_t bit3 : 1; 1024 uint8_t bit4 : 1; 1025 uint8_t bit5 : 1; 1026 uint8_t bit6 : 1; 1027 uint8_t bit7 : 1; 1028 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1029 uint8_t bit7 : 1; 1030 uint8_t bit6 : 1; 1031 uint8_t bit5 : 1; 1032 uint8_t bit4 : 1; 1033 uint8_t bit3 : 1; 1034 uint8_t bit2 : 1; 1035 uint8_t bit1 : 1; 1036 uint8_t bit0 : 1; 1037 #endif /* DRV_BYTE_ORDER */ 1038 } lsm6ds3tr_c_sensorhub13_reg_t; 1039 1040 #define LSM6DS3TR_C_SENSORHUB14_REG 0x4EU 1041 typedef struct 1042 { 1043 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1044 uint8_t bit0 : 1; 1045 uint8_t bit1 : 1; 1046 uint8_t bit2 : 1; 1047 uint8_t bit3 : 1; 1048 uint8_t bit4 : 1; 1049 uint8_t bit5 : 1; 1050 uint8_t bit6 : 1; 1051 uint8_t bit7 : 1; 1052 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1053 uint8_t bit7 : 1; 1054 uint8_t bit6 : 1; 1055 uint8_t bit5 : 1; 1056 uint8_t bit4 : 1; 1057 uint8_t bit3 : 1; 1058 uint8_t bit2 : 1; 1059 uint8_t bit1 : 1; 1060 uint8_t bit0 : 1; 1061 #endif /* DRV_BYTE_ORDER */ 1062 } lsm6ds3tr_c_sensorhub14_reg_t; 1063 1064 #define LSM6DS3TR_C_SENSORHUB15_REG 0x4FU 1065 typedef struct 1066 { 1067 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1068 uint8_t bit0 : 1; 1069 uint8_t bit1 : 1; 1070 uint8_t bit2 : 1; 1071 uint8_t bit3 : 1; 1072 uint8_t bit4 : 1; 1073 uint8_t bit5 : 1; 1074 uint8_t bit6 : 1; 1075 uint8_t bit7 : 1; 1076 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1077 uint8_t bit7 : 1; 1078 uint8_t bit6 : 1; 1079 uint8_t bit5 : 1; 1080 uint8_t bit4 : 1; 1081 uint8_t bit3 : 1; 1082 uint8_t bit2 : 1; 1083 uint8_t bit1 : 1; 1084 uint8_t bit0 : 1; 1085 #endif /* DRV_BYTE_ORDER */ 1086 } lsm6ds3tr_c_sensorhub15_reg_t; 1087 1088 #define LSM6DS3TR_C_SENSORHUB16_REG 0x50U 1089 typedef struct 1090 { 1091 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1092 uint8_t bit0 : 1; 1093 uint8_t bit1 : 1; 1094 uint8_t bit2 : 1; 1095 uint8_t bit3 : 1; 1096 uint8_t bit4 : 1; 1097 uint8_t bit5 : 1; 1098 uint8_t bit6 : 1; 1099 uint8_t bit7 : 1; 1100 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1101 uint8_t bit7 : 1; 1102 uint8_t bit6 : 1; 1103 uint8_t bit5 : 1; 1104 uint8_t bit4 : 1; 1105 uint8_t bit3 : 1; 1106 uint8_t bit2 : 1; 1107 uint8_t bit1 : 1; 1108 uint8_t bit0 : 1; 1109 #endif /* DRV_BYTE_ORDER */ 1110 } lsm6ds3tr_c_sensorhub16_reg_t; 1111 1112 #define LSM6DS3TR_C_SENSORHUB17_REG 0x51U 1113 typedef struct 1114 { 1115 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1116 uint8_t bit0 : 1; 1117 uint8_t bit1 : 1; 1118 uint8_t bit2 : 1; 1119 uint8_t bit3 : 1; 1120 uint8_t bit4 : 1; 1121 uint8_t bit5 : 1; 1122 uint8_t bit6 : 1; 1123 uint8_t bit7 : 1; 1124 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1125 uint8_t bit7 : 1; 1126 uint8_t bit6 : 1; 1127 uint8_t bit5 : 1; 1128 uint8_t bit4 : 1; 1129 uint8_t bit3 : 1; 1130 uint8_t bit2 : 1; 1131 uint8_t bit1 : 1; 1132 uint8_t bit0 : 1; 1133 #endif /* DRV_BYTE_ORDER */ 1134 } lsm6ds3tr_c_sensorhub17_reg_t; 1135 1136 #define LSM6DS3TR_C_SENSORHUB18_REG 0x52U 1137 typedef struct 1138 { 1139 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1140 uint8_t bit0 : 1; 1141 uint8_t bit1 : 1; 1142 uint8_t bit2 : 1; 1143 uint8_t bit3 : 1; 1144 uint8_t bit4 : 1; 1145 uint8_t bit5 : 1; 1146 uint8_t bit6 : 1; 1147 uint8_t bit7 : 1; 1148 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1149 uint8_t bit7 : 1; 1150 uint8_t bit6 : 1; 1151 uint8_t bit5 : 1; 1152 uint8_t bit4 : 1; 1153 uint8_t bit3 : 1; 1154 uint8_t bit2 : 1; 1155 uint8_t bit1 : 1; 1156 uint8_t bit0 : 1; 1157 #endif /* DRV_BYTE_ORDER */ 1158 } lsm6ds3tr_c_sensorhub18_reg_t; 1159 1160 #define LSM6DS3TR_C_FUNC_SRC1 0x53U 1161 typedef struct 1162 { 1163 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1164 uint8_t sensorhub_end_op : 1; 1165 uint8_t si_end_op : 1; 1166 uint8_t hi_fail : 1; 1167 uint8_t step_overflow : 1; 1168 uint8_t step_detected : 1; 1169 uint8_t tilt_ia : 1; 1170 uint8_t sign_motion_ia : 1; 1171 uint8_t step_count_delta_ia : 1; 1172 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1173 uint8_t step_count_delta_ia : 1; 1174 uint8_t sign_motion_ia : 1; 1175 uint8_t tilt_ia : 1; 1176 uint8_t step_detected : 1; 1177 uint8_t step_overflow : 1; 1178 uint8_t hi_fail : 1; 1179 uint8_t si_end_op : 1; 1180 uint8_t sensorhub_end_op : 1; 1181 #endif /* DRV_BYTE_ORDER */ 1182 } lsm6ds3tr_c_func_src1_t; 1183 1184 #define LSM6DS3TR_C_FUNC_SRC2 0x54U 1185 typedef struct 1186 { 1187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1188 uint8_t wrist_tilt_ia : 1; 1189 uint8_t not_used_01 : 2; 1190 uint8_t slave0_nack : 1; 1191 uint8_t slave1_nack : 1; 1192 uint8_t slave2_nack : 1; 1193 uint8_t slave3_nack : 1; 1194 uint8_t not_used_02 : 1; 1195 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1196 uint8_t not_used_02 : 1; 1197 uint8_t slave3_nack : 1; 1198 uint8_t slave2_nack : 1; 1199 uint8_t slave1_nack : 1; 1200 uint8_t slave0_nack : 1; 1201 uint8_t not_used_01 : 2; 1202 uint8_t wrist_tilt_ia : 1; 1203 #endif /* DRV_BYTE_ORDER */ 1204 } lsm6ds3tr_c_func_src2_t; 1205 1206 #define LSM6DS3TR_C_WRIST_TILT_IA 0x55U 1207 typedef struct 1208 { 1209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1210 uint8_t not_used_01 : 2; 1211 uint8_t wrist_tilt_ia_zneg : 1; 1212 uint8_t wrist_tilt_ia_zpos : 1; 1213 uint8_t wrist_tilt_ia_yneg : 1; 1214 uint8_t wrist_tilt_ia_ypos : 1; 1215 uint8_t wrist_tilt_ia_xneg : 1; 1216 uint8_t wrist_tilt_ia_xpos : 1; 1217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1218 uint8_t wrist_tilt_ia_xpos : 1; 1219 uint8_t wrist_tilt_ia_xneg : 1; 1220 uint8_t wrist_tilt_ia_ypos : 1; 1221 uint8_t wrist_tilt_ia_yneg : 1; 1222 uint8_t wrist_tilt_ia_zpos : 1; 1223 uint8_t wrist_tilt_ia_zneg : 1; 1224 uint8_t not_used_01 : 2; 1225 #endif /* DRV_BYTE_ORDER */ 1226 } lsm6ds3tr_c_wrist_tilt_ia_t; 1227 1228 #define LSM6DS3TR_C_TAP_CFG 0x58U 1229 typedef struct 1230 { 1231 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1232 uint8_t lir : 1; 1233 uint8_t tap_z_en : 1; 1234 uint8_t tap_y_en : 1; 1235 uint8_t tap_x_en : 1; 1236 uint8_t slope_fds : 1; 1237 uint8_t inact_en : 2; 1238 uint8_t interrupts_enable : 1; 1239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1240 uint8_t interrupts_enable : 1; 1241 uint8_t inact_en : 2; 1242 uint8_t slope_fds : 1; 1243 uint8_t tap_x_en : 1; 1244 uint8_t tap_y_en : 1; 1245 uint8_t tap_z_en : 1; 1246 uint8_t lir : 1; 1247 #endif /* DRV_BYTE_ORDER */ 1248 } lsm6ds3tr_c_tap_cfg_t; 1249 1250 #define LSM6DS3TR_C_TAP_THS_6D 0x59U 1251 typedef struct 1252 { 1253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1254 uint8_t tap_ths : 5; 1255 uint8_t sixd_ths : 2; 1256 uint8_t d4d_en : 1; 1257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1258 uint8_t d4d_en : 1; 1259 uint8_t sixd_ths : 2; 1260 uint8_t tap_ths : 5; 1261 #endif /* DRV_BYTE_ORDER */ 1262 } lsm6ds3tr_c_tap_ths_6d_t; 1263 1264 #define LSM6DS3TR_C_INT_DUR2 0x5AU 1265 typedef struct 1266 { 1267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1268 uint8_t shock : 2; 1269 uint8_t quiet : 2; 1270 uint8_t dur : 4; 1271 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1272 uint8_t dur : 4; 1273 uint8_t quiet : 2; 1274 uint8_t shock : 2; 1275 #endif /* DRV_BYTE_ORDER */ 1276 } lsm6ds3tr_c_int_dur2_t; 1277 1278 #define LSM6DS3TR_C_WAKE_UP_THS 0x5BU 1279 typedef struct 1280 { 1281 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1282 uint8_t wk_ths : 6; 1283 uint8_t not_used_01 : 1; 1284 uint8_t single_double_tap : 1; 1285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1286 uint8_t single_double_tap : 1; 1287 uint8_t not_used_01 : 1; 1288 uint8_t wk_ths : 6; 1289 #endif /* DRV_BYTE_ORDER */ 1290 } lsm6ds3tr_c_wake_up_ths_t; 1291 1292 #define LSM6DS3TR_C_WAKE_UP_DUR 0x5CU 1293 typedef struct 1294 { 1295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1296 uint8_t sleep_dur : 4; 1297 uint8_t timer_hr : 1; 1298 uint8_t wake_dur : 2; 1299 uint8_t ff_dur : 1; 1300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1301 uint8_t ff_dur : 1; 1302 uint8_t wake_dur : 2; 1303 uint8_t timer_hr : 1; 1304 uint8_t sleep_dur : 4; 1305 #endif /* DRV_BYTE_ORDER */ 1306 } lsm6ds3tr_c_wake_up_dur_t; 1307 1308 #define LSM6DS3TR_C_FREE_FALL 0x5DU 1309 typedef struct 1310 { 1311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1312 uint8_t ff_ths : 3; 1313 uint8_t ff_dur : 5; 1314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1315 uint8_t ff_dur : 5; 1316 uint8_t ff_ths : 3; 1317 #endif /* DRV_BYTE_ORDER */ 1318 } lsm6ds3tr_c_free_fall_t; 1319 1320 #define LSM6DS3TR_C_MD1_CFG 0x5EU 1321 typedef struct 1322 { 1323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1324 uint8_t int1_timer : 1; 1325 uint8_t int1_tilt : 1; 1326 uint8_t int1_6d : 1; 1327 uint8_t int1_double_tap : 1; 1328 uint8_t int1_ff : 1; 1329 uint8_t int1_wu : 1; 1330 uint8_t int1_single_tap : 1; 1331 uint8_t int1_inact_state : 1; 1332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1333 uint8_t int1_inact_state : 1; 1334 uint8_t int1_single_tap : 1; 1335 uint8_t int1_wu : 1; 1336 uint8_t int1_ff : 1; 1337 uint8_t int1_double_tap : 1; 1338 uint8_t int1_6d : 1; 1339 uint8_t int1_tilt : 1; 1340 uint8_t int1_timer : 1; 1341 #endif /* DRV_BYTE_ORDER */ 1342 } lsm6ds3tr_c_md1_cfg_t; 1343 1344 #define LSM6DS3TR_C_MD2_CFG 0x5FU 1345 typedef struct 1346 { 1347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1348 uint8_t int2_iron : 1; 1349 uint8_t int2_tilt : 1; 1350 uint8_t int2_6d : 1; 1351 uint8_t int2_double_tap : 1; 1352 uint8_t int2_ff : 1; 1353 uint8_t int2_wu : 1; 1354 uint8_t int2_single_tap : 1; 1355 uint8_t int2_inact_state : 1; 1356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1357 uint8_t int2_inact_state : 1; 1358 uint8_t int2_single_tap : 1; 1359 uint8_t int2_wu : 1; 1360 uint8_t int2_ff : 1; 1361 uint8_t int2_double_tap : 1; 1362 uint8_t int2_6d : 1; 1363 uint8_t int2_tilt : 1; 1364 uint8_t int2_iron : 1; 1365 #endif /* DRV_BYTE_ORDER */ 1366 } lsm6ds3tr_c_md2_cfg_t; 1367 1368 #define LSM6DS3TR_C_MASTER_CMD_CODE 0x60U 1369 typedef struct 1370 { 1371 uint8_t master_cmd_code : 8; 1372 } lsm6ds3tr_c_master_cmd_code_t; 1373 1374 #define LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE 0x61U 1375 typedef struct 1376 { 1377 uint8_t error_code : 8; 1378 } lsm6ds3tr_c_sens_sync_spi_error_code_t; 1379 1380 #define LSM6DS3TR_C_OUT_MAG_RAW_X_L 0x66U 1381 #define LSM6DS3TR_C_OUT_MAG_RAW_X_H 0x67U 1382 #define LSM6DS3TR_C_OUT_MAG_RAW_Y_L 0x68U 1383 #define LSM6DS3TR_C_OUT_MAG_RAW_Y_H 0x69U 1384 #define LSM6DS3TR_C_OUT_MAG_RAW_Z_L 0x6AU 1385 #define LSM6DS3TR_C_OUT_MAG_RAW_Z_H 0x6BU 1386 #define LSM6DS3TR_C_X_OFS_USR 0x73U 1387 #define LSM6DS3TR_C_Y_OFS_USR 0x74U 1388 #define LSM6DS3TR_C_Z_OFS_USR 0x75U 1389 #define LSM6DS3TR_C_SLV0_ADD 0x02U 1390 typedef struct 1391 { 1392 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1393 uint8_t rw_0 : 1; 1394 uint8_t slave0_add : 7; 1395 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1396 uint8_t slave0_add : 7; 1397 uint8_t rw_0 : 1; 1398 #endif /* DRV_BYTE_ORDER */ 1399 } lsm6ds3tr_c_slv0_add_t; 1400 1401 #define LSM6DS3TR_C_SLV0_SUBADD 0x03U 1402 typedef struct 1403 { 1404 uint8_t slave0_reg : 8; 1405 } lsm6ds3tr_c_slv0_subadd_t; 1406 1407 #define LSM6DS3TR_C_SLAVE0_CONFIG 0x04U 1408 typedef struct 1409 { 1410 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1411 uint8_t slave0_numop : 3; 1412 uint8_t src_mode : 1; 1413 uint8_t aux_sens_on : 2; 1414 uint8_t slave0_rate : 2; 1415 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1416 uint8_t slave0_rate : 2; 1417 uint8_t aux_sens_on : 2; 1418 uint8_t src_mode : 1; 1419 uint8_t slave0_numop : 3; 1420 #endif /* DRV_BYTE_ORDER */ 1421 } lsm6ds3tr_c_slave0_config_t; 1422 1423 #define LSM6DS3TR_C_SLV1_ADD 0x05U 1424 typedef struct 1425 { 1426 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1427 uint8_t r_1 : 1; 1428 uint8_t slave1_add : 7; 1429 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1430 uint8_t slave1_add : 7; 1431 uint8_t r_1 : 1; 1432 #endif /* DRV_BYTE_ORDER */ 1433 } lsm6ds3tr_c_slv1_add_t; 1434 1435 #define LSM6DS3TR_C_SLV1_SUBADD 0x06U 1436 typedef struct 1437 { 1438 uint8_t slave1_reg : 8; 1439 } lsm6ds3tr_c_slv1_subadd_t; 1440 1441 #define LSM6DS3TR_C_SLAVE1_CONFIG 0x07U 1442 typedef struct 1443 { 1444 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1445 uint8_t slave1_numop : 3; 1446 uint8_t not_used_01 : 2; 1447 uint8_t write_once : 1; 1448 uint8_t slave1_rate : 2; 1449 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1450 uint8_t slave1_rate : 2; 1451 uint8_t write_once : 1; 1452 uint8_t not_used_01 : 2; 1453 uint8_t slave1_numop : 3; 1454 #endif /* DRV_BYTE_ORDER */ 1455 } lsm6ds3tr_c_slave1_config_t; 1456 1457 #define LSM6DS3TR_C_SLV2_ADD 0x08U 1458 typedef struct 1459 { 1460 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1461 uint8_t r_2 : 1; 1462 uint8_t slave2_add : 7; 1463 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1464 uint8_t slave2_add : 7; 1465 uint8_t r_2 : 1; 1466 #endif /* DRV_BYTE_ORDER */ 1467 } lsm6ds3tr_c_slv2_add_t; 1468 1469 #define LSM6DS3TR_C_SLV2_SUBADD 0x09U 1470 typedef struct 1471 { 1472 uint8_t slave2_reg : 8; 1473 } lsm6ds3tr_c_slv2_subadd_t; 1474 1475 #define LSM6DS3TR_C_SLAVE2_CONFIG 0x0AU 1476 typedef struct 1477 { 1478 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1479 uint8_t slave2_numop : 3; 1480 uint8_t not_used_01 : 3; 1481 uint8_t slave2_rate : 2; 1482 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1483 uint8_t slave2_rate : 2; 1484 uint8_t not_used_01 : 3; 1485 uint8_t slave2_numop : 3; 1486 #endif /* DRV_BYTE_ORDER */ 1487 } lsm6ds3tr_c_slave2_config_t; 1488 1489 #define LSM6DS3TR_C_SLV3_ADD 0x0BU 1490 typedef struct 1491 { 1492 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1493 uint8_t r_3 : 1; 1494 uint8_t slave3_add : 7; 1495 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1496 uint8_t slave3_add : 7; 1497 uint8_t r_3 : 1; 1498 #endif /* DRV_BYTE_ORDER */ 1499 } lsm6ds3tr_c_slv3_add_t; 1500 1501 #define LSM6DS3TR_C_SLV3_SUBADD 0x0CU 1502 typedef struct 1503 { 1504 uint8_t slave3_reg : 8; 1505 } lsm6ds3tr_c_slv3_subadd_t; 1506 1507 #define LSM6DS3TR_C_SLAVE3_CONFIG 0x0DU 1508 typedef struct 1509 { 1510 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1511 uint8_t slave3_numop : 3; 1512 uint8_t not_used_01 : 3; 1513 uint8_t slave3_rate : 2; 1514 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1515 uint8_t slave3_rate : 2; 1516 uint8_t not_used_01 : 3; 1517 uint8_t slave3_numop : 3; 1518 #endif /* DRV_BYTE_ORDER */ 1519 } lsm6ds3tr_c_slave3_config_t; 1520 1521 #define LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU 1522 typedef struct 1523 { 1524 uint8_t slave_dataw : 8; 1525 } lsm6ds3tr_c_datawrite_src_mode_sub_slv0_t; 1526 1527 #define LSM6DS3TR_C_CONFIG_PEDO_THS_MIN 0x0FU 1528 typedef struct 1529 { 1530 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1531 uint8_t ths_min : 5; 1532 uint8_t not_used_01 : 2; 1533 uint8_t pedo_fs : 1; 1534 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1535 uint8_t pedo_fs : 1; 1536 uint8_t not_used_01 : 2; 1537 uint8_t ths_min : 5; 1538 #endif /* DRV_BYTE_ORDER */ 1539 } lsm6ds3tr_c_config_pedo_ths_min_t; 1540 1541 #define LSM6DS3TR_C_SM_THS 0x13U 1542 #define LSM6DS3TR_C_PEDO_DEB_REG 0x14U 1543 typedef struct 1544 { 1545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1546 uint8_t deb_step : 3; 1547 uint8_t deb_time : 5; 1548 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1549 uint8_t deb_time : 5; 1550 uint8_t deb_step : 3; 1551 #endif /* DRV_BYTE_ORDER */ 1552 } lsm6ds3tr_c_pedo_deb_reg_t; 1553 1554 #define LSM6DS3TR_C_STEP_COUNT_DELTA 0x15U 1555 #define LSM6DS3TR_C_MAG_SI_XX 0x24U 1556 #define LSM6DS3TR_C_MAG_SI_XY 0x25U 1557 #define LSM6DS3TR_C_MAG_SI_XZ 0x26U 1558 #define LSM6DS3TR_C_MAG_SI_YX 0x27U 1559 #define LSM6DS3TR_C_MAG_SI_YY 0x28U 1560 #define LSM6DS3TR_C_MAG_SI_YZ 0x29U 1561 #define LSM6DS3TR_C_MAG_SI_ZX 0x2AU 1562 #define LSM6DS3TR_C_MAG_SI_ZY 0x2BU 1563 #define LSM6DS3TR_C_MAG_SI_ZZ 0x2CU 1564 #define LSM6DS3TR_C_MAG_OFFX_L 0x2DU 1565 #define LSM6DS3TR_C_MAG_OFFX_H 0x2EU 1566 #define LSM6DS3TR_C_MAG_OFFY_L 0x2FU 1567 #define LSM6DS3TR_C_MAG_OFFY_H 0x30U 1568 #define LSM6DS3TR_C_MAG_OFFZ_L 0x31U 1569 #define LSM6DS3TR_C_MAG_OFFZ_H 0x32U 1570 #define LSM6DS3TR_C_A_WRIST_TILT_LAT 0x50U 1571 #define LSM6DS3TR_C_A_WRIST_TILT_THS 0x54U 1572 #define LSM6DS3TR_C_A_WRIST_TILT_MASK 0x59U 1573 typedef struct 1574 { 1575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1576 uint8_t not_used_01 : 2; 1577 uint8_t wrist_tilt_mask_zneg : 1; 1578 uint8_t wrist_tilt_mask_zpos : 1; 1579 uint8_t wrist_tilt_mask_yneg : 1; 1580 uint8_t wrist_tilt_mask_ypos : 1; 1581 uint8_t wrist_tilt_mask_xneg : 1; 1582 uint8_t wrist_tilt_mask_xpos : 1; 1583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1584 uint8_t wrist_tilt_mask_xpos : 1; 1585 uint8_t wrist_tilt_mask_xneg : 1; 1586 uint8_t wrist_tilt_mask_ypos : 1; 1587 uint8_t wrist_tilt_mask_yneg : 1; 1588 uint8_t wrist_tilt_mask_zpos : 1; 1589 uint8_t wrist_tilt_mask_zneg : 1; 1590 uint8_t not_used_01 : 2; 1591 #endif /* DRV_BYTE_ORDER */ 1592 } lsm6ds3tr_c_a_wrist_tilt_mask_t; 1593 1594 /** 1595 * @defgroup LSM6DS3TR_C_Register_Union 1596 * @brief This union group all the registers having a bit-field 1597 * description. 1598 * This union is useful but it's not needed by the driver. 1599 * 1600 * REMOVING this union you are compliant with: 1601 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 1602 * 1603 * @{ 1604 * 1605 */ 1606 typedef union 1607 { 1608 lsm6ds3tr_c_func_cfg_access_t func_cfg_access; 1609 lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame; 1610 lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio; 1611 lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1; 1612 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; 1613 lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; 1614 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; 1615 lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; 1616 lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; 1617 lsm6ds3tr_c_int1_ctrl_t int1_ctrl; 1618 lsm6ds3tr_c_int2_ctrl_t int2_ctrl; 1619 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; 1620 lsm6ds3tr_c_ctrl2_g_t ctrl2_g; 1621 lsm6ds3tr_c_ctrl3_c_t ctrl3_c; 1622 lsm6ds3tr_c_ctrl4_c_t ctrl4_c; 1623 lsm6ds3tr_c_ctrl5_c_t ctrl5_c; 1624 lsm6ds3tr_c_ctrl6_c_t ctrl6_c; 1625 lsm6ds3tr_c_ctrl7_g_t ctrl7_g; 1626 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; 1627 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; 1628 lsm6ds3tr_c_ctrl10_c_t ctrl10_c; 1629 lsm6ds3tr_c_master_config_t master_config; 1630 lsm6ds3tr_c_wake_up_src_t wake_up_src; 1631 lsm6ds3tr_c_tap_src_t tap_src; 1632 lsm6ds3tr_c_d6d_src_t d6d_src; 1633 lsm6ds3tr_c_status_reg_t status_reg; 1634 lsm6ds3tr_c_sensorhub1_reg_t sensorhub1_reg; 1635 lsm6ds3tr_c_sensorhub2_reg_t sensorhub2_reg; 1636 lsm6ds3tr_c_sensorhub3_reg_t sensorhub3_reg; 1637 lsm6ds3tr_c_sensorhub4_reg_t sensorhub4_reg; 1638 lsm6ds3tr_c_sensorhub5_reg_t sensorhub5_reg; 1639 lsm6ds3tr_c_sensorhub6_reg_t sensorhub6_reg; 1640 lsm6ds3tr_c_sensorhub7_reg_t sensorhub7_reg; 1641 lsm6ds3tr_c_sensorhub8_reg_t sensorhub8_reg; 1642 lsm6ds3tr_c_sensorhub9_reg_t sensorhub9_reg; 1643 lsm6ds3tr_c_sensorhub10_reg_t sensorhub10_reg; 1644 lsm6ds3tr_c_sensorhub11_reg_t sensorhub11_reg; 1645 lsm6ds3tr_c_sensorhub12_reg_t sensorhub12_reg; 1646 lsm6ds3tr_c_fifo_status1_t fifo_status1; 1647 lsm6ds3tr_c_fifo_status2_t fifo_status2; 1648 lsm6ds3tr_c_fifo_status3_t fifo_status3; 1649 lsm6ds3tr_c_fifo_status4_t fifo_status4; 1650 lsm6ds3tr_c_sensorhub13_reg_t sensorhub13_reg; 1651 lsm6ds3tr_c_sensorhub14_reg_t sensorhub14_reg; 1652 lsm6ds3tr_c_sensorhub15_reg_t sensorhub15_reg; 1653 lsm6ds3tr_c_sensorhub16_reg_t sensorhub16_reg; 1654 lsm6ds3tr_c_sensorhub17_reg_t sensorhub17_reg; 1655 lsm6ds3tr_c_sensorhub18_reg_t sensorhub18_reg; 1656 lsm6ds3tr_c_func_src1_t func_src1; 1657 lsm6ds3tr_c_func_src2_t func_src2; 1658 lsm6ds3tr_c_wrist_tilt_ia_t wrist_tilt_ia; 1659 lsm6ds3tr_c_tap_cfg_t tap_cfg; 1660 lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; 1661 lsm6ds3tr_c_int_dur2_t int_dur2; 1662 lsm6ds3tr_c_wake_up_ths_t wake_up_ths; 1663 lsm6ds3tr_c_wake_up_dur_t wake_up_dur; 1664 lsm6ds3tr_c_free_fall_t free_fall; 1665 lsm6ds3tr_c_md1_cfg_t md1_cfg; 1666 lsm6ds3tr_c_md2_cfg_t md2_cfg; 1667 lsm6ds3tr_c_master_cmd_code_t master_cmd_code; 1668 lsm6ds3tr_c_sens_sync_spi_error_code_t 1669 sens_sync_spi_error_code; 1670 lsm6ds3tr_c_slv0_add_t slv0_add; 1671 lsm6ds3tr_c_slv0_subadd_t slv0_subadd; 1672 lsm6ds3tr_c_slave0_config_t slave0_config; 1673 lsm6ds3tr_c_slv1_add_t slv1_add; 1674 lsm6ds3tr_c_slv1_subadd_t slv1_subadd; 1675 lsm6ds3tr_c_slave1_config_t slave1_config; 1676 lsm6ds3tr_c_slv2_add_t slv2_add; 1677 lsm6ds3tr_c_slv2_subadd_t slv2_subadd; 1678 lsm6ds3tr_c_slave2_config_t slave2_config; 1679 lsm6ds3tr_c_slv3_add_t slv3_add; 1680 lsm6ds3tr_c_slv3_subadd_t slv3_subadd; 1681 lsm6ds3tr_c_slave3_config_t slave3_config; 1682 lsm6ds3tr_c_datawrite_src_mode_sub_slv0_t 1683 datawrite_src_mode_sub_slv0; 1684 lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; 1685 lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; 1686 lsm6ds3tr_c_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1687 bitwise_t bitwise; 1688 uint8_t byte; 1689 } lsm6ds3tr_c_reg_t; 1690 1691 /** 1692 * @} 1693 * 1694 */ 1695 1696 #ifndef __weak 1697 #define __weak __attribute__((weak)) 1698 #endif /* __weak */ 1699 1700 /* 1701 * These are the basic platform dependent I/O routines to read 1702 * and write device registers connected on a standard bus. 1703 * The driver keeps offering a default implementation based on function 1704 * pointers to read/write routines for backward compatibility. 1705 * The __weak directive allows the final application to overwrite 1706 * them with a custom implementation. 1707 */ 1708 1709 int32_t lsm6ds3tr_c_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1710 uint8_t *data, 1711 uint16_t len); 1712 int32_t lsm6ds3tr_c_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1713 uint8_t *data, 1714 uint16_t len); 1715 1716 float_t lsm6ds3tr_c_from_fs2g_to_mg(int16_t lsb); 1717 float_t lsm6ds3tr_c_from_fs4g_to_mg(int16_t lsb); 1718 float_t lsm6ds3tr_c_from_fs8g_to_mg(int16_t lsb); 1719 float_t lsm6ds3tr_c_from_fs16g_to_mg(int16_t lsb); 1720 1721 float_t lsm6ds3tr_c_from_fs125dps_to_mdps(int16_t lsb); 1722 float_t lsm6ds3tr_c_from_fs250dps_to_mdps(int16_t lsb); 1723 float_t lsm6ds3tr_c_from_fs500dps_to_mdps(int16_t lsb); 1724 float_t lsm6ds3tr_c_from_fs1000dps_to_mdps(int16_t lsb); 1725 float_t lsm6ds3tr_c_from_fs2000dps_to_mdps(int16_t lsb); 1726 1727 float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb); 1728 1729 typedef enum 1730 { 1731 LSM6DS3TR_C_2g = 0, 1732 LSM6DS3TR_C_16g = 1, 1733 LSM6DS3TR_C_4g = 2, 1734 LSM6DS3TR_C_8g = 3, 1735 LSM6DS3TR_C_XL_FS_ND = 4, /* ERROR CODE */ 1736 } lsm6ds3tr_c_fs_xl_t; 1737 int32_t lsm6ds3tr_c_xl_full_scale_set(const stmdev_ctx_t *ctx, 1738 lsm6ds3tr_c_fs_xl_t val); 1739 int32_t lsm6ds3tr_c_xl_full_scale_get(const stmdev_ctx_t *ctx, 1740 lsm6ds3tr_c_fs_xl_t *val); 1741 1742 typedef enum 1743 { 1744 LSM6DS3TR_C_XL_ODR_OFF = 0, 1745 LSM6DS3TR_C_XL_ODR_12Hz5 = 1, 1746 LSM6DS3TR_C_XL_ODR_26Hz = 2, 1747 LSM6DS3TR_C_XL_ODR_52Hz = 3, 1748 LSM6DS3TR_C_XL_ODR_104Hz = 4, 1749 LSM6DS3TR_C_XL_ODR_208Hz = 5, 1750 LSM6DS3TR_C_XL_ODR_416Hz = 6, 1751 LSM6DS3TR_C_XL_ODR_833Hz = 7, 1752 LSM6DS3TR_C_XL_ODR_1k66Hz = 8, 1753 LSM6DS3TR_C_XL_ODR_3k33Hz = 9, 1754 LSM6DS3TR_C_XL_ODR_6k66Hz = 10, 1755 LSM6DS3TR_C_XL_ODR_1Hz6 = 11, 1756 LSM6DS3TR_C_XL_ODR_ND = 12, /* ERROR CODE */ 1757 } lsm6ds3tr_c_odr_xl_t; 1758 int32_t lsm6ds3tr_c_xl_data_rate_set(const stmdev_ctx_t *ctx, 1759 lsm6ds3tr_c_odr_xl_t val); 1760 int32_t lsm6ds3tr_c_xl_data_rate_get(const stmdev_ctx_t *ctx, 1761 lsm6ds3tr_c_odr_xl_t *val); 1762 1763 typedef enum 1764 { 1765 LSM6DS3TR_C_250dps = 0, 1766 LSM6DS3TR_C_125dps = 1, 1767 LSM6DS3TR_C_500dps = 2, 1768 LSM6DS3TR_C_1000dps = 4, 1769 LSM6DS3TR_C_2000dps = 6, 1770 LSM6DS3TR_C_GY_FS_ND = 7, /* ERROR CODE */ 1771 } lsm6ds3tr_c_fs_g_t; 1772 int32_t lsm6ds3tr_c_gy_full_scale_set(const stmdev_ctx_t *ctx, 1773 lsm6ds3tr_c_fs_g_t val); 1774 int32_t lsm6ds3tr_c_gy_full_scale_get(const stmdev_ctx_t *ctx, 1775 lsm6ds3tr_c_fs_g_t *val); 1776 1777 typedef enum 1778 { 1779 LSM6DS3TR_C_GY_ODR_OFF = 0, 1780 LSM6DS3TR_C_GY_ODR_12Hz5 = 1, 1781 LSM6DS3TR_C_GY_ODR_26Hz = 2, 1782 LSM6DS3TR_C_GY_ODR_52Hz = 3, 1783 LSM6DS3TR_C_GY_ODR_104Hz = 4, 1784 LSM6DS3TR_C_GY_ODR_208Hz = 5, 1785 LSM6DS3TR_C_GY_ODR_416Hz = 6, 1786 LSM6DS3TR_C_GY_ODR_833Hz = 7, 1787 LSM6DS3TR_C_GY_ODR_1k66Hz = 8, 1788 LSM6DS3TR_C_GY_ODR_3k33Hz = 9, 1789 LSM6DS3TR_C_GY_ODR_6k66Hz = 10, 1790 LSM6DS3TR_C_GY_ODR_ND = 11, /* ERROR CODE */ 1791 } lsm6ds3tr_c_odr_g_t; 1792 int32_t lsm6ds3tr_c_gy_data_rate_set(const stmdev_ctx_t *ctx, 1793 lsm6ds3tr_c_odr_g_t val); 1794 int32_t lsm6ds3tr_c_gy_data_rate_get(const stmdev_ctx_t *ctx, 1795 lsm6ds3tr_c_odr_g_t *val); 1796 1797 int32_t lsm6ds3tr_c_block_data_update_set(const stmdev_ctx_t *ctx, 1798 uint8_t val); 1799 int32_t lsm6ds3tr_c_block_data_update_get(const stmdev_ctx_t *ctx, 1800 uint8_t *val); 1801 1802 typedef enum 1803 { 1804 LSM6DS3TR_C_LSb_1mg = 0, 1805 LSM6DS3TR_C_LSb_16mg = 1, 1806 LSM6DS3TR_C_WEIGHT_ND = 2, 1807 } lsm6ds3tr_c_usr_off_w_t; 1808 int32_t lsm6ds3tr_c_xl_offset_weight_set(const stmdev_ctx_t *ctx, 1809 lsm6ds3tr_c_usr_off_w_t val); 1810 int32_t lsm6ds3tr_c_xl_offset_weight_get(const stmdev_ctx_t *ctx, 1811 lsm6ds3tr_c_usr_off_w_t *val); 1812 1813 typedef enum 1814 { 1815 LSM6DS3TR_C_XL_HIGH_PERFORMANCE = 0, 1816 LSM6DS3TR_C_XL_NORMAL = 1, 1817 LSM6DS3TR_C_XL_PW_MODE_ND = 2, /* ERROR CODE */ 1818 } lsm6ds3tr_c_xl_hm_mode_t; 1819 int32_t lsm6ds3tr_c_xl_power_mode_set(const stmdev_ctx_t *ctx, 1820 lsm6ds3tr_c_xl_hm_mode_t val); 1821 int32_t lsm6ds3tr_c_xl_power_mode_get(const stmdev_ctx_t *ctx, 1822 lsm6ds3tr_c_xl_hm_mode_t *val); 1823 1824 typedef enum 1825 { 1826 LSM6DS3TR_C_STAT_RND_DISABLE = 0, 1827 LSM6DS3TR_C_STAT_RND_ENABLE = 1, 1828 LSM6DS3TR_C_STAT_RND_ND = 2, /* ERROR CODE */ 1829 } lsm6ds3tr_c_rounding_status_t; 1830 int32_t lsm6ds3tr_c_rounding_on_status_set(const stmdev_ctx_t *ctx, 1831 lsm6ds3tr_c_rounding_status_t val); 1832 int32_t lsm6ds3tr_c_rounding_on_status_get(const stmdev_ctx_t *ctx, 1833 lsm6ds3tr_c_rounding_status_t *val); 1834 1835 typedef enum 1836 { 1837 LSM6DS3TR_C_GY_HIGH_PERFORMANCE = 0, 1838 LSM6DS3TR_C_GY_NORMAL = 1, 1839 LSM6DS3TR_C_GY_PW_MODE_ND = 2, /* ERROR CODE */ 1840 } lsm6ds3tr_c_g_hm_mode_t; 1841 int32_t lsm6ds3tr_c_gy_power_mode_set(const stmdev_ctx_t *ctx, 1842 lsm6ds3tr_c_g_hm_mode_t val); 1843 int32_t lsm6ds3tr_c_gy_power_mode_get(const stmdev_ctx_t *ctx, 1844 lsm6ds3tr_c_g_hm_mode_t *val); 1845 1846 typedef struct 1847 { 1848 lsm6ds3tr_c_wake_up_src_t wake_up_src; 1849 lsm6ds3tr_c_tap_src_t tap_src; 1850 lsm6ds3tr_c_d6d_src_t d6d_src; 1851 lsm6ds3tr_c_status_reg_t status_reg; 1852 lsm6ds3tr_c_func_src1_t func_src1; 1853 lsm6ds3tr_c_func_src2_t func_src2; 1854 lsm6ds3tr_c_wrist_tilt_ia_t wrist_tilt_ia; 1855 lsm6ds3tr_c_a_wrist_tilt_mask_t a_wrist_tilt_mask; 1856 } lsm6ds3tr_c_all_sources_t; 1857 int32_t lsm6ds3tr_c_all_sources_get(const stmdev_ctx_t *ctx, 1858 lsm6ds3tr_c_all_sources_t *val); 1859 1860 int32_t lsm6ds3tr_c_status_reg_get(const stmdev_ctx_t *ctx, 1861 lsm6ds3tr_c_status_reg_t *val); 1862 1863 int32_t lsm6ds3tr_c_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 1864 uint8_t *val); 1865 1866 int32_t lsm6ds3tr_c_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, 1867 uint8_t *val); 1868 1869 int32_t lsm6ds3tr_c_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 1870 uint8_t *val); 1871 1872 int32_t lsm6ds3tr_c_xl_usr_offset_set(const stmdev_ctx_t *ctx, 1873 uint8_t *buff); 1874 int32_t lsm6ds3tr_c_xl_usr_offset_get(const stmdev_ctx_t *ctx, 1875 uint8_t *buff); 1876 int32_t lsm6ds3tr_c_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 1877 int32_t lsm6ds3tr_c_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 1878 1879 typedef enum 1880 { 1881 LSM6DS3TR_C_LSB_6ms4 = 0, 1882 LSM6DS3TR_C_LSB_25us = 1, 1883 LSM6DS3TR_C_TS_RES_ND = 2, /* ERROR CODE */ 1884 } lsm6ds3tr_c_timer_hr_t; 1885 int32_t lsm6ds3tr_c_timestamp_res_set(const stmdev_ctx_t *ctx, 1886 lsm6ds3tr_c_timer_hr_t val); 1887 int32_t lsm6ds3tr_c_timestamp_res_get(const stmdev_ctx_t *ctx, 1888 lsm6ds3tr_c_timer_hr_t *val); 1889 1890 typedef enum 1891 { 1892 LSM6DS3TR_C_ROUND_DISABLE = 0, 1893 LSM6DS3TR_C_ROUND_XL = 1, 1894 LSM6DS3TR_C_ROUND_GY = 2, 1895 LSM6DS3TR_C_ROUND_GY_XL = 3, 1896 LSM6DS3TR_C_ROUND_SH1_TO_SH6 = 4, 1897 LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6 = 5, 1898 LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12 = 6, 1899 LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6 = 7, 1900 LSM6DS3TR_C_ROUND_OUT_ND = 8, /* ERROR CODE */ 1901 } lsm6ds3tr_c_rounding_t; 1902 int32_t lsm6ds3tr_c_rounding_mode_set(const stmdev_ctx_t *ctx, 1903 lsm6ds3tr_c_rounding_t val); 1904 int32_t lsm6ds3tr_c_rounding_mode_get(const stmdev_ctx_t *ctx, 1905 lsm6ds3tr_c_rounding_t *val); 1906 1907 int32_t lsm6ds3tr_c_temperature_raw_get(const stmdev_ctx_t *ctx, 1908 int16_t *val); 1909 int32_t lsm6ds3tr_c_angular_rate_raw_get(const stmdev_ctx_t *ctx, 1910 int16_t *val); 1911 int32_t lsm6ds3tr_c_acceleration_raw_get(const stmdev_ctx_t *ctx, 1912 int16_t *val); 1913 1914 int32_t lsm6ds3tr_c_mag_calibrated_raw_get(const stmdev_ctx_t *ctx, 1915 int16_t *val); 1916 1917 int32_t lsm6ds3tr_c_fifo_raw_data_get(const stmdev_ctx_t *ctx, 1918 uint8_t *buffer, 1919 uint8_t len); 1920 1921 typedef enum 1922 { 1923 LSM6DS3TR_C_USER_BANK = 0, 1924 LSM6DS3TR_C_BANK_A = 4, 1925 LSM6DS3TR_C_BANK_B = 5, 1926 LSM6DS3TR_C_BANK_ND = 6, /* ERROR CODE */ 1927 } lsm6ds3tr_c_func_cfg_en_t; 1928 int32_t lsm6ds3tr_c_mem_bank_set(const stmdev_ctx_t *ctx, 1929 lsm6ds3tr_c_func_cfg_en_t val); 1930 int32_t lsm6ds3tr_c_mem_bank_get(const stmdev_ctx_t *ctx, 1931 lsm6ds3tr_c_func_cfg_en_t *val); 1932 1933 typedef enum 1934 { 1935 LSM6DS3TR_C_DRDY_LATCHED = 0, 1936 LSM6DS3TR_C_DRDY_PULSED = 1, 1937 LSM6DS3TR_C_DRDY_ND = 2, /* ERROR CODE */ 1938 } lsm6ds3tr_c_drdy_pulsed_g_t; 1939 int32_t lsm6ds3tr_c_data_ready_mode_set(const stmdev_ctx_t *ctx, 1940 lsm6ds3tr_c_drdy_pulsed_g_t val); 1941 int32_t lsm6ds3tr_c_data_ready_mode_get(const stmdev_ctx_t *ctx, 1942 lsm6ds3tr_c_drdy_pulsed_g_t *val); 1943 1944 int32_t lsm6ds3tr_c_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1945 int32_t lsm6ds3tr_c_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 1946 int32_t lsm6ds3tr_c_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1947 1948 typedef enum 1949 { 1950 LSM6DS3TR_C_LSB_AT_LOW_ADD = 0, 1951 LSM6DS3TR_C_MSB_AT_LOW_ADD = 1, 1952 LSM6DS3TR_C_DATA_FMT_ND = 2, /* ERROR CODE */ 1953 } lsm6ds3tr_c_ble_t; 1954 int32_t lsm6ds3tr_c_data_format_set(const stmdev_ctx_t *ctx, 1955 lsm6ds3tr_c_ble_t val); 1956 int32_t lsm6ds3tr_c_data_format_get(const stmdev_ctx_t *ctx, 1957 lsm6ds3tr_c_ble_t *val); 1958 1959 int32_t lsm6ds3tr_c_auto_increment_set(const stmdev_ctx_t *ctx, 1960 uint8_t val); 1961 int32_t lsm6ds3tr_c_auto_increment_get(const stmdev_ctx_t *ctx, 1962 uint8_t *val); 1963 1964 int32_t lsm6ds3tr_c_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 1965 int32_t lsm6ds3tr_c_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 1966 1967 typedef enum 1968 { 1969 LSM6DS3TR_C_XL_ST_DISABLE = 0, 1970 LSM6DS3TR_C_XL_ST_POSITIVE = 1, 1971 LSM6DS3TR_C_XL_ST_NEGATIVE = 2, 1972 LSM6DS3TR_C_XL_ST_ND = 3, /* ERROR CODE */ 1973 } lsm6ds3tr_c_st_xl_t; 1974 int32_t lsm6ds3tr_c_xl_self_test_set(const stmdev_ctx_t *ctx, 1975 lsm6ds3tr_c_st_xl_t val); 1976 int32_t lsm6ds3tr_c_xl_self_test_get(const stmdev_ctx_t *ctx, 1977 lsm6ds3tr_c_st_xl_t *val); 1978 1979 typedef enum 1980 { 1981 LSM6DS3TR_C_GY_ST_DISABLE = 0, 1982 LSM6DS3TR_C_GY_ST_POSITIVE = 1, 1983 LSM6DS3TR_C_GY_ST_NEGATIVE = 3, 1984 LSM6DS3TR_C_GY_ST_ND = 4, /* ERROR CODE */ 1985 } lsm6ds3tr_c_st_g_t; 1986 int32_t lsm6ds3tr_c_gy_self_test_set(const stmdev_ctx_t *ctx, 1987 lsm6ds3tr_c_st_g_t val); 1988 int32_t lsm6ds3tr_c_gy_self_test_get(const stmdev_ctx_t *ctx, 1989 lsm6ds3tr_c_st_g_t *val); 1990 1991 int32_t lsm6ds3tr_c_filter_settling_mask_set(const stmdev_ctx_t *ctx, 1992 uint8_t val); 1993 int32_t lsm6ds3tr_c_filter_settling_mask_get(const stmdev_ctx_t *ctx, 1994 uint8_t *val); 1995 1996 typedef enum 1997 { 1998 LSM6DS3TR_C_USE_SLOPE = 0, 1999 LSM6DS3TR_C_USE_HPF = 1, 2000 LSM6DS3TR_C_HP_PATH_ND = 2, /* ERROR CODE */ 2001 } lsm6ds3tr_c_slope_fds_t; 2002 int32_t lsm6ds3tr_c_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 2003 lsm6ds3tr_c_slope_fds_t val); 2004 int32_t lsm6ds3tr_c_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 2005 lsm6ds3tr_c_slope_fds_t *val); 2006 2007 typedef enum 2008 { 2009 LSM6DS3TR_C_XL_ANA_BW_1k5Hz = 0, 2010 LSM6DS3TR_C_XL_ANA_BW_400Hz = 1, 2011 LSM6DS3TR_C_XL_ANA_BW_ND = 2, /* ERROR CODE */ 2012 } lsm6ds3tr_c_bw0_xl_t; 2013 int32_t lsm6ds3tr_c_xl_filter_analog_set(const stmdev_ctx_t *ctx, 2014 lsm6ds3tr_c_bw0_xl_t val); 2015 int32_t lsm6ds3tr_c_xl_filter_analog_get(const stmdev_ctx_t *ctx, 2016 lsm6ds3tr_c_bw0_xl_t *val); 2017 2018 typedef enum 2019 { 2020 LSM6DS3TR_C_XL_LP1_ODR_DIV_2 = 0, 2021 LSM6DS3TR_C_XL_LP1_ODR_DIV_4 = 1, 2022 LSM6DS3TR_C_XL_LP1_NA = 2, /* ERROR CODE */ 2023 } lsm6ds3tr_c_lpf1_bw_sel_t; 2024 int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2025 lsm6ds3tr_c_lpf1_bw_sel_t val); 2026 int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2027 lsm6ds3tr_c_lpf1_bw_sel_t *val); 2028 2029 typedef enum 2030 { 2031 LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00, 2032 LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01, 2033 LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02, 2034 LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400 = 0x03, 2035 LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50 = 0x10, 2036 LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100 = 0x11, 2037 LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9 = 0x12, 2038 LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, 2039 LSM6DS3TR_C_XL_LP_NA = 0x20, /* ERROR CODE */ 2040 } lsm6ds3tr_c_input_composite_t; 2041 int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, 2042 lsm6ds3tr_c_input_composite_t val); 2043 int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, 2044 lsm6ds3tr_c_input_composite_t *val); 2045 2046 int32_t lsm6ds3tr_c_xl_reference_mode_set(const stmdev_ctx_t *ctx, 2047 uint8_t val); 2048 int32_t lsm6ds3tr_c_xl_reference_mode_get(const stmdev_ctx_t *ctx, 2049 uint8_t *val); 2050 2051 typedef enum 2052 { 2053 LSM6DS3TR_C_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */ 2054 LSM6DS3TR_C_XL_HP_ODR_DIV_100 = 0x01, 2055 LSM6DS3TR_C_XL_HP_ODR_DIV_9 = 0x02, 2056 LSM6DS3TR_C_XL_HP_ODR_DIV_400 = 0x03, 2057 LSM6DS3TR_C_XL_HP_NA = 0x10, /* ERROR CODE */ 2058 } lsm6ds3tr_c_hpcf_xl_t; 2059 int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx, 2060 lsm6ds3tr_c_hpcf_xl_t val); 2061 int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx, 2062 lsm6ds3tr_c_hpcf_xl_t *val); 2063 2064 typedef enum 2065 { 2066 LSM6DS3TR_C_LP2_ONLY = 0x00, 2067 2068 LSM6DS3TR_C_HP_16mHz_LP2 = 0x80, 2069 LSM6DS3TR_C_HP_65mHz_LP2 = 0x90, 2070 LSM6DS3TR_C_HP_260mHz_LP2 = 0xA0, 2071 LSM6DS3TR_C_HP_1Hz04_LP2 = 0xB0, 2072 2073 LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT = 0x0A, 2074 LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL = 0x09, 2075 LSM6DS3TR_C_HP_DISABLE_LP_STRONG = 0x08, 2076 LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, 2077 2078 LSM6DS3TR_C_HP_16mHz_LP1_LIGHT = 0x8A, 2079 LSM6DS3TR_C_HP_65mHz_LP1_NORMAL = 0x99, 2080 LSM6DS3TR_C_HP_260mHz_LP1_STRONG = 0xA8, 2081 LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, 2082 2083 LSM6DS3TR_C_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */ 2084 } lsm6ds3tr_c_lpf1_sel_g_t; 2085 int32_t lsm6ds3tr_c_gy_band_pass_set(const stmdev_ctx_t *ctx, 2086 lsm6ds3tr_c_lpf1_sel_g_t val); 2087 int32_t lsm6ds3tr_c_gy_band_pass_get(const stmdev_ctx_t *ctx, 2088 lsm6ds3tr_c_lpf1_sel_g_t *val); 2089 2090 typedef enum 2091 { 2092 LSM6DS3TR_C_SPI_4_WIRE = 0, 2093 LSM6DS3TR_C_SPI_3_WIRE = 1, 2094 LSM6DS3TR_C_SPI_MODE_ND = 2, /* ERROR CODE */ 2095 } lsm6ds3tr_c_sim_t; 2096 int32_t lsm6ds3tr_c_spi_mode_set(const stmdev_ctx_t *ctx, 2097 lsm6ds3tr_c_sim_t val); 2098 int32_t lsm6ds3tr_c_spi_mode_get(const stmdev_ctx_t *ctx, 2099 lsm6ds3tr_c_sim_t *val); 2100 2101 typedef enum 2102 { 2103 LSM6DS3TR_C_I2C_ENABLE = 0, 2104 LSM6DS3TR_C_I2C_DISABLE = 1, 2105 LSM6DS3TR_C_I2C_MODE_ND = 2, /* ERROR CODE */ 2106 } lsm6ds3tr_c_i2c_disable_t; 2107 int32_t lsm6ds3tr_c_i2c_interface_set(const stmdev_ctx_t *ctx, 2108 lsm6ds3tr_c_i2c_disable_t val); 2109 int32_t lsm6ds3tr_c_i2c_interface_get(const stmdev_ctx_t *ctx, 2110 lsm6ds3tr_c_i2c_disable_t *val); 2111 2112 typedef struct 2113 { 2114 uint8_t int1_drdy_xl : 1; 2115 uint8_t int1_drdy_g : 1; 2116 uint8_t int1_boot : 1; 2117 uint8_t int1_fth : 1; 2118 uint8_t int1_fifo_ovr : 1; 2119 uint8_t int1_full_flag : 1; 2120 uint8_t int1_sign_mot : 1; 2121 uint8_t int1_step_detector : 1; 2122 uint8_t int1_timer : 1; 2123 uint8_t int1_tilt : 1; 2124 uint8_t int1_6d : 1; 2125 uint8_t int1_double_tap : 1; 2126 uint8_t int1_ff : 1; 2127 uint8_t int1_wu : 1; 2128 uint8_t int1_single_tap : 1; 2129 uint8_t int1_inact_state : 1; 2130 uint8_t den_drdy_int1 : 1; 2131 uint8_t drdy_on_int1 : 1; 2132 } lsm6ds3tr_c_int1_route_t; 2133 int32_t lsm6ds3tr_c_pin_int1_route_set(const stmdev_ctx_t *ctx, 2134 lsm6ds3tr_c_int1_route_t val); 2135 int32_t lsm6ds3tr_c_pin_int1_route_get(const stmdev_ctx_t *ctx, 2136 lsm6ds3tr_c_int1_route_t *val); 2137 2138 typedef struct 2139 { 2140 uint8_t int2_drdy_xl : 1; 2141 uint8_t int2_drdy_g : 1; 2142 uint8_t int2_drdy_temp : 1; 2143 uint8_t int2_fth : 1; 2144 uint8_t int2_fifo_ovr : 1; 2145 uint8_t int2_full_flag : 1; 2146 uint8_t int2_step_count_ov : 1; 2147 uint8_t int2_step_delta : 1; 2148 uint8_t int2_iron : 1; 2149 uint8_t int2_tilt : 1; 2150 uint8_t int2_6d : 1; 2151 uint8_t int2_double_tap : 1; 2152 uint8_t int2_ff : 1; 2153 uint8_t int2_wu : 1; 2154 uint8_t int2_single_tap : 1; 2155 uint8_t int2_inact_state : 1; 2156 uint8_t int2_wrist_tilt : 1; 2157 } lsm6ds3tr_c_int2_route_t; 2158 int32_t lsm6ds3tr_c_pin_int2_route_set(const stmdev_ctx_t *ctx, 2159 lsm6ds3tr_c_int2_route_t val); 2160 int32_t lsm6ds3tr_c_pin_int2_route_get(const stmdev_ctx_t *ctx, 2161 lsm6ds3tr_c_int2_route_t *val); 2162 2163 typedef enum 2164 { 2165 LSM6DS3TR_C_PUSH_PULL = 0, 2166 LSM6DS3TR_C_OPEN_DRAIN = 1, 2167 LSM6DS3TR_C_PIN_MODE_ND = 2, /* ERROR CODE */ 2168 } lsm6ds3tr_c_pp_od_t; 2169 int32_t lsm6ds3tr_c_pin_mode_set(const stmdev_ctx_t *ctx, 2170 lsm6ds3tr_c_pp_od_t val); 2171 int32_t lsm6ds3tr_c_pin_mode_get(const stmdev_ctx_t *ctx, 2172 lsm6ds3tr_c_pp_od_t *val); 2173 2174 typedef enum 2175 { 2176 LSM6DS3TR_C_ACTIVE_HIGH = 0, 2177 LSM6DS3TR_C_ACTIVE_LOW = 1, 2178 LSM6DS3TR_C_POLARITY_ND = 2, /* ERROR CODE */ 2179 } lsm6ds3tr_c_h_lactive_t; 2180 int32_t lsm6ds3tr_c_pin_polarity_set(const stmdev_ctx_t *ctx, 2181 lsm6ds3tr_c_h_lactive_t val); 2182 int32_t lsm6ds3tr_c_pin_polarity_get(const stmdev_ctx_t *ctx, 2183 lsm6ds3tr_c_h_lactive_t *val); 2184 2185 int32_t lsm6ds3tr_c_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 2186 int32_t lsm6ds3tr_c_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2187 2188 typedef enum 2189 { 2190 LSM6DS3TR_C_INT_PULSED = 0, 2191 LSM6DS3TR_C_INT_LATCHED = 1, 2192 LSM6DS3TR_C_INT_MODE = 2, /* ERROR CODE */ 2193 } lsm6ds3tr_c_lir_t; 2194 int32_t lsm6ds3tr_c_int_notification_set(const stmdev_ctx_t *ctx, 2195 lsm6ds3tr_c_lir_t val); 2196 int32_t lsm6ds3tr_c_int_notification_get(const stmdev_ctx_t *ctx, 2197 lsm6ds3tr_c_lir_t *val); 2198 2199 int32_t lsm6ds3tr_c_wkup_threshold_set(const stmdev_ctx_t *ctx, 2200 uint8_t val); 2201 int32_t lsm6ds3tr_c_wkup_threshold_get(const stmdev_ctx_t *ctx, 2202 uint8_t *val); 2203 2204 int32_t lsm6ds3tr_c_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2205 int32_t lsm6ds3tr_c_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2206 2207 int32_t lsm6ds3tr_c_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2208 int32_t lsm6ds3tr_c_gy_sleep_mode_get(const stmdev_ctx_t *ctx, 2209 uint8_t *val); 2210 2211 typedef enum 2212 { 2213 LSM6DS3TR_C_PROPERTY_DISABLE = 0, 2214 LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED = 1, 2215 LSM6DS3TR_C_XL_12Hz5_GY_SLEEP = 2, 2216 LSM6DS3TR_C_XL_12Hz5_GY_PD = 3, 2217 LSM6DS3TR_C_ACT_MODE_ND = 4, /* ERROR CODE */ 2218 } lsm6ds3tr_c_inact_en_t; 2219 int32_t lsm6ds3tr_c_act_mode_set(const stmdev_ctx_t *ctx, 2220 lsm6ds3tr_c_inact_en_t val); 2221 int32_t lsm6ds3tr_c_act_mode_get(const stmdev_ctx_t *ctx, 2222 lsm6ds3tr_c_inact_en_t *val); 2223 2224 int32_t lsm6ds3tr_c_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2225 int32_t lsm6ds3tr_c_act_sleep_dur_get(const stmdev_ctx_t *ctx, 2226 uint8_t *val); 2227 2228 int32_t lsm6ds3tr_c_tap_src_get(const stmdev_ctx_t *ctx, 2229 lsm6ds3tr_c_tap_src_t *val); 2230 2231 int32_t lsm6ds3tr_c_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 2232 uint8_t val); 2233 int32_t lsm6ds3tr_c_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 2234 uint8_t *val); 2235 2236 int32_t lsm6ds3tr_c_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 2237 uint8_t val); 2238 int32_t lsm6ds3tr_c_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 2239 uint8_t *val); 2240 2241 int32_t lsm6ds3tr_c_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 2242 uint8_t val); 2243 int32_t lsm6ds3tr_c_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 2244 uint8_t *val); 2245 2246 int32_t lsm6ds3tr_c_tap_threshold_x_set(const stmdev_ctx_t *ctx, 2247 uint8_t val); 2248 int32_t lsm6ds3tr_c_tap_threshold_x_get(const stmdev_ctx_t *ctx, 2249 uint8_t *val); 2250 2251 int32_t lsm6ds3tr_c_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 2252 int32_t lsm6ds3tr_c_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 2253 2254 int32_t lsm6ds3tr_c_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 2255 int32_t lsm6ds3tr_c_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 2256 2257 int32_t lsm6ds3tr_c_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2258 int32_t lsm6ds3tr_c_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2259 2260 typedef enum 2261 { 2262 LSM6DS3TR_C_ONLY_SINGLE = 0, 2263 LSM6DS3TR_C_BOTH_SINGLE_DOUBLE = 1, 2264 LSM6DS3TR_C_TAP_MODE_ND = 2, /* ERROR CODE */ 2265 } lsm6ds3tr_c_single_double_tap_t; 2266 int32_t lsm6ds3tr_c_tap_mode_set(const stmdev_ctx_t *ctx, 2267 lsm6ds3tr_c_single_double_tap_t val); 2268 int32_t lsm6ds3tr_c_tap_mode_get(const stmdev_ctx_t *ctx, 2269 lsm6ds3tr_c_single_double_tap_t *val); 2270 2271 typedef enum 2272 { 2273 LSM6DS3TR_C_ODR_DIV_2_FEED = 0, 2274 LSM6DS3TR_C_LPF2_FEED = 1, 2275 LSM6DS3TR_C_6D_FEED_ND = 2, /* ERROR CODE */ 2276 } lsm6ds3tr_c_low_pass_on_6d_t; 2277 int32_t lsm6ds3tr_c_6d_feed_data_set(const stmdev_ctx_t *ctx, 2278 lsm6ds3tr_c_low_pass_on_6d_t val); 2279 int32_t lsm6ds3tr_c_6d_feed_data_get(const stmdev_ctx_t *ctx, 2280 lsm6ds3tr_c_low_pass_on_6d_t *val); 2281 2282 typedef enum 2283 { 2284 LSM6DS3TR_C_DEG_80 = 0, 2285 LSM6DS3TR_C_DEG_70 = 1, 2286 LSM6DS3TR_C_DEG_60 = 2, 2287 LSM6DS3TR_C_DEG_50 = 3, 2288 LSM6DS3TR_C_6D_TH_ND = 4, /* ERROR CODE */ 2289 } lsm6ds3tr_c_sixd_ths_t; 2290 int32_t lsm6ds3tr_c_6d_threshold_set(const stmdev_ctx_t *ctx, 2291 lsm6ds3tr_c_sixd_ths_t val); 2292 int32_t lsm6ds3tr_c_6d_threshold_get(const stmdev_ctx_t *ctx, 2293 lsm6ds3tr_c_sixd_ths_t *val); 2294 2295 int32_t lsm6ds3tr_c_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2296 int32_t lsm6ds3tr_c_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2297 2298 int32_t lsm6ds3tr_c_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2299 int32_t lsm6ds3tr_c_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2300 2301 typedef enum 2302 { 2303 LSM6DS3TR_C_FF_TSH_156mg = 0, 2304 LSM6DS3TR_C_FF_TSH_219mg = 1, 2305 LSM6DS3TR_C_FF_TSH_250mg = 2, 2306 LSM6DS3TR_C_FF_TSH_312mg = 3, 2307 LSM6DS3TR_C_FF_TSH_344mg = 4, 2308 LSM6DS3TR_C_FF_TSH_406mg = 5, 2309 LSM6DS3TR_C_FF_TSH_469mg = 6, 2310 LSM6DS3TR_C_FF_TSH_500mg = 7, 2311 LSM6DS3TR_C_FF_TSH_ND = 8, /* ERROR CODE */ 2312 } lsm6ds3tr_c_ff_ths_t; 2313 int32_t lsm6ds3tr_c_ff_threshold_set(const stmdev_ctx_t *ctx, 2314 lsm6ds3tr_c_ff_ths_t val); 2315 int32_t lsm6ds3tr_c_ff_threshold_get(const stmdev_ctx_t *ctx, 2316 lsm6ds3tr_c_ff_ths_t *val); 2317 2318 int32_t lsm6ds3tr_c_fifo_watermark_set(const stmdev_ctx_t *ctx, 2319 uint16_t val); 2320 int32_t lsm6ds3tr_c_fifo_watermark_get(const stmdev_ctx_t *ctx, 2321 uint16_t *val); 2322 2323 int32_t lsm6ds3tr_c_fifo_data_level_get(const stmdev_ctx_t *ctx, 2324 uint16_t *val); 2325 2326 int32_t lsm6ds3tr_c_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, 2327 uint8_t *val); 2328 2329 int32_t lsm6ds3tr_c_fifo_pattern_get(const stmdev_ctx_t *ctx, 2330 uint16_t *val); 2331 2332 int32_t lsm6ds3tr_c_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 2333 uint8_t val); 2334 int32_t lsm6ds3tr_c_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 2335 uint8_t *val); 2336 2337 typedef enum 2338 { 2339 LSM6DS3TR_C_TRG_XL_GY_DRDY = 0, 2340 LSM6DS3TR_C_TRG_STEP_DETECT = 1, 2341 LSM6DS3TR_C_TRG_SH_DRDY = 2, 2342 LSM6DS3TR_C_TRG_SH_ND = 3, /* ERROR CODE */ 2343 } lsm6ds3tr_c_trigger_fifo_t; 2344 int32_t lsm6ds3tr_c_fifo_write_trigger_set(const stmdev_ctx_t *ctx, 2345 lsm6ds3tr_c_trigger_fifo_t val); 2346 int32_t lsm6ds3tr_c_fifo_write_trigger_get(const stmdev_ctx_t *ctx, 2347 lsm6ds3tr_c_trigger_fifo_t *val); 2348 2349 int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set( 2350 stmdev_ctx_t *ctx, 2351 uint8_t val); 2352 int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get( 2353 stmdev_ctx_t *ctx, 2354 uint8_t *val); 2355 2356 typedef enum 2357 { 2358 LSM6DS3TR_C_FIFO_XL_DISABLE = 0, 2359 LSM6DS3TR_C_FIFO_XL_NO_DEC = 1, 2360 LSM6DS3TR_C_FIFO_XL_DEC_2 = 2, 2361 LSM6DS3TR_C_FIFO_XL_DEC_3 = 3, 2362 LSM6DS3TR_C_FIFO_XL_DEC_4 = 4, 2363 LSM6DS3TR_C_FIFO_XL_DEC_8 = 5, 2364 LSM6DS3TR_C_FIFO_XL_DEC_16 = 6, 2365 LSM6DS3TR_C_FIFO_XL_DEC_32 = 7, 2366 LSM6DS3TR_C_FIFO_XL_DEC_ND = 8, /* ERROR CODE */ 2367 } lsm6ds3tr_c_dec_fifo_xl_t; 2368 int32_t lsm6ds3tr_c_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 2369 lsm6ds3tr_c_dec_fifo_xl_t val); 2370 int32_t lsm6ds3tr_c_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 2371 lsm6ds3tr_c_dec_fifo_xl_t *val); 2372 2373 typedef enum 2374 { 2375 LSM6DS3TR_C_FIFO_GY_DISABLE = 0, 2376 LSM6DS3TR_C_FIFO_GY_NO_DEC = 1, 2377 LSM6DS3TR_C_FIFO_GY_DEC_2 = 2, 2378 LSM6DS3TR_C_FIFO_GY_DEC_3 = 3, 2379 LSM6DS3TR_C_FIFO_GY_DEC_4 = 4, 2380 LSM6DS3TR_C_FIFO_GY_DEC_8 = 5, 2381 LSM6DS3TR_C_FIFO_GY_DEC_16 = 6, 2382 LSM6DS3TR_C_FIFO_GY_DEC_32 = 7, 2383 LSM6DS3TR_C_FIFO_GY_DEC_ND = 8, /* ERROR CODE */ 2384 } lsm6ds3tr_c_dec_fifo_gyro_t; 2385 int32_t lsm6ds3tr_c_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 2386 lsm6ds3tr_c_dec_fifo_gyro_t val); 2387 int32_t lsm6ds3tr_c_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 2388 lsm6ds3tr_c_dec_fifo_gyro_t *val); 2389 2390 typedef enum 2391 { 2392 LSM6DS3TR_C_FIFO_DS3_DISABLE = 0, 2393 LSM6DS3TR_C_FIFO_DS3_NO_DEC = 1, 2394 LSM6DS3TR_C_FIFO_DS3_DEC_2 = 2, 2395 LSM6DS3TR_C_FIFO_DS3_DEC_3 = 3, 2396 LSM6DS3TR_C_FIFO_DS3_DEC_4 = 4, 2397 LSM6DS3TR_C_FIFO_DS3_DEC_8 = 5, 2398 LSM6DS3TR_C_FIFO_DS3_DEC_16 = 6, 2399 LSM6DS3TR_C_FIFO_DS3_DEC_32 = 7, 2400 LSM6DS3TR_C_FIFO_DS3_DEC_ND = 8, /* ERROR CODE */ 2401 } lsm6ds3tr_c_dec_ds3_fifo_t; 2402 int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx, 2403 lsm6ds3tr_c_dec_ds3_fifo_t val); 2404 int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx, 2405 lsm6ds3tr_c_dec_ds3_fifo_t *val); 2406 2407 typedef enum 2408 { 2409 LSM6DS3TR_C_FIFO_DS4_DISABLE = 0, 2410 LSM6DS3TR_C_FIFO_DS4_NO_DEC = 1, 2411 LSM6DS3TR_C_FIFO_DS4_DEC_2 = 2, 2412 LSM6DS3TR_C_FIFO_DS4_DEC_3 = 3, 2413 LSM6DS3TR_C_FIFO_DS4_DEC_4 = 4, 2414 LSM6DS3TR_C_FIFO_DS4_DEC_8 = 5, 2415 LSM6DS3TR_C_FIFO_DS4_DEC_16 = 6, 2416 LSM6DS3TR_C_FIFO_DS4_DEC_32 = 7, 2417 LSM6DS3TR_C_FIFO_DS4_DEC_ND = 8, /* ERROR CODE */ 2418 } lsm6ds3tr_c_dec_ds4_fifo_t; 2419 int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx, 2420 lsm6ds3tr_c_dec_ds4_fifo_t val); 2421 int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx, 2422 lsm6ds3tr_c_dec_ds4_fifo_t *val); 2423 2424 int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx, 2425 uint8_t val); 2426 int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx, 2427 uint8_t *val); 2428 2429 int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, 2430 uint8_t val); 2431 int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, 2432 uint8_t *val); 2433 2434 typedef enum 2435 { 2436 LSM6DS3TR_C_BYPASS_MODE = 0, 2437 LSM6DS3TR_C_FIFO_MODE = 1, 2438 LSM6DS3TR_C_STREAM_TO_FIFO_MODE = 3, 2439 LSM6DS3TR_C_BYPASS_TO_STREAM_MODE = 4, 2440 LSM6DS3TR_C_STREAM_MODE = 6, 2441 LSM6DS3TR_C_FIFO_MODE_ND = 8, /* ERROR CODE */ 2442 } lsm6ds3tr_c_fifo_mode_t; 2443 int32_t lsm6ds3tr_c_fifo_mode_set(const stmdev_ctx_t *ctx, 2444 lsm6ds3tr_c_fifo_mode_t val); 2445 int32_t lsm6ds3tr_c_fifo_mode_get(const stmdev_ctx_t *ctx, 2446 lsm6ds3tr_c_fifo_mode_t *val); 2447 2448 typedef enum 2449 { 2450 LSM6DS3TR_C_FIFO_DISABLE = 0, 2451 LSM6DS3TR_C_FIFO_12Hz5 = 1, 2452 LSM6DS3TR_C_FIFO_26Hz = 2, 2453 LSM6DS3TR_C_FIFO_52Hz = 3, 2454 LSM6DS3TR_C_FIFO_104Hz = 4, 2455 LSM6DS3TR_C_FIFO_208Hz = 5, 2456 LSM6DS3TR_C_FIFO_416Hz = 6, 2457 LSM6DS3TR_C_FIFO_833Hz = 7, 2458 LSM6DS3TR_C_FIFO_1k66Hz = 8, 2459 LSM6DS3TR_C_FIFO_3k33Hz = 9, 2460 LSM6DS3TR_C_FIFO_6k66Hz = 10, 2461 LSM6DS3TR_C_FIFO_RATE_ND = 11, /* ERROR CODE */ 2462 } lsm6ds3tr_c_odr_fifo_t; 2463 int32_t lsm6ds3tr_c_fifo_data_rate_set(const stmdev_ctx_t *ctx, 2464 lsm6ds3tr_c_odr_fifo_t val); 2465 int32_t lsm6ds3tr_c_fifo_data_rate_get(const stmdev_ctx_t *ctx, 2466 lsm6ds3tr_c_odr_fifo_t *val); 2467 2468 typedef enum 2469 { 2470 LSM6DS3TR_C_DEN_ACT_LOW = 0, 2471 LSM6DS3TR_C_DEN_ACT_HIGH = 1, 2472 LSM6DS3TR_C_DEN_POL_ND = 2, /* ERROR CODE */ 2473 } lsm6ds3tr_c_den_lh_t; 2474 int32_t lsm6ds3tr_c_den_polarity_set(const stmdev_ctx_t *ctx, 2475 lsm6ds3tr_c_den_lh_t val); 2476 int32_t lsm6ds3tr_c_den_polarity_get(const stmdev_ctx_t *ctx, 2477 lsm6ds3tr_c_den_lh_t *val); 2478 2479 typedef enum 2480 { 2481 LSM6DS3TR_C_DEN_DISABLE = 0, 2482 LSM6DS3TR_C_LEVEL_FIFO = 6, 2483 LSM6DS3TR_C_LEVEL_LETCHED = 3, 2484 LSM6DS3TR_C_LEVEL_TRIGGER = 2, 2485 LSM6DS3TR_C_EDGE_TRIGGER = 4, 2486 LSM6DS3TR_C_DEN_MODE_ND = 5, /* ERROR CODE */ 2487 } lsm6ds3tr_c_den_mode_t; 2488 int32_t lsm6ds3tr_c_den_mode_set(const stmdev_ctx_t *ctx, 2489 lsm6ds3tr_c_den_mode_t val); 2490 int32_t lsm6ds3tr_c_den_mode_get(const stmdev_ctx_t *ctx, 2491 lsm6ds3tr_c_den_mode_t *val); 2492 2493 typedef enum 2494 { 2495 LSM6DS3TR_C_STAMP_IN_GY_DATA = 0, 2496 LSM6DS3TR_C_STAMP_IN_XL_DATA = 1, 2497 LSM6DS3TR_C_STAMP_IN_GY_XL_DATA = 2, 2498 LSM6DS3TR_C_DEN_STAMP_ND = 3, /* ERROR CODE */ 2499 } lsm6ds3tr_c_den_xl_en_t; 2500 int32_t lsm6ds3tr_c_den_enable_set(const stmdev_ctx_t *ctx, 2501 lsm6ds3tr_c_den_xl_en_t val); 2502 int32_t lsm6ds3tr_c_den_enable_get(const stmdev_ctx_t *ctx, 2503 lsm6ds3tr_c_den_xl_en_t *val); 2504 2505 int32_t lsm6ds3tr_c_den_mark_axis_z_set(const stmdev_ctx_t *ctx, 2506 uint8_t val); 2507 int32_t lsm6ds3tr_c_den_mark_axis_z_get(const stmdev_ctx_t *ctx, 2508 uint8_t *val); 2509 2510 int32_t lsm6ds3tr_c_den_mark_axis_y_set(const stmdev_ctx_t *ctx, 2511 uint8_t val); 2512 int32_t lsm6ds3tr_c_den_mark_axis_y_get(const stmdev_ctx_t *ctx, 2513 uint8_t *val); 2514 2515 int32_t lsm6ds3tr_c_den_mark_axis_x_set(const stmdev_ctx_t *ctx, 2516 uint8_t val); 2517 int32_t lsm6ds3tr_c_den_mark_axis_x_get(const stmdev_ctx_t *ctx, 2518 uint8_t *val); 2519 2520 int32_t lsm6ds3tr_c_pedo_step_reset_set(const stmdev_ctx_t *ctx, 2521 uint8_t val); 2522 int32_t lsm6ds3tr_c_pedo_step_reset_get(const stmdev_ctx_t *ctx, 2523 uint8_t *val); 2524 2525 int32_t lsm6ds3tr_c_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 2526 int32_t lsm6ds3tr_c_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 2527 2528 int32_t lsm6ds3tr_c_pedo_threshold_set(const stmdev_ctx_t *ctx, 2529 uint8_t val); 2530 int32_t lsm6ds3tr_c_pedo_threshold_get(const stmdev_ctx_t *ctx, 2531 uint8_t *val); 2532 2533 typedef enum 2534 { 2535 LSM6DS3TR_C_PEDO_AT_2g = 0, 2536 LSM6DS3TR_C_PEDO_AT_4g = 1, 2537 LSM6DS3TR_C_PEDO_FS_ND = 2, /* ERROR CODE */ 2538 } lsm6ds3tr_c_pedo_fs_t; 2539 int32_t lsm6ds3tr_c_pedo_full_scale_set(const stmdev_ctx_t *ctx, 2540 lsm6ds3tr_c_pedo_fs_t val); 2541 int32_t lsm6ds3tr_c_pedo_full_scale_get(const stmdev_ctx_t *ctx, 2542 lsm6ds3tr_c_pedo_fs_t *val); 2543 2544 int32_t lsm6ds3tr_c_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 2545 uint8_t val); 2546 int32_t lsm6ds3tr_c_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 2547 uint8_t *val); 2548 2549 int32_t lsm6ds3tr_c_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 2550 int32_t lsm6ds3tr_c_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); 2551 2552 int32_t lsm6ds3tr_c_pedo_steps_period_set(const stmdev_ctx_t *ctx, 2553 uint8_t *buff); 2554 int32_t lsm6ds3tr_c_pedo_steps_period_get(const stmdev_ctx_t *ctx, 2555 uint8_t *buff); 2556 2557 int32_t lsm6ds3tr_c_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 2558 int32_t lsm6ds3tr_c_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 2559 2560 int32_t lsm6ds3tr_c_motion_threshold_set(const stmdev_ctx_t *ctx, 2561 uint8_t *buff); 2562 int32_t lsm6ds3tr_c_motion_threshold_get(const stmdev_ctx_t *ctx, 2563 uint8_t *buff); 2564 2565 int32_t lsm6ds3tr_c_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 2566 int32_t lsm6ds3tr_c_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 2567 2568 int32_t lsm6ds3tr_c_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, 2569 uint8_t val); 2570 int32_t lsm6ds3tr_c_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, 2571 uint8_t *val); 2572 2573 int32_t lsm6ds3tr_c_tilt_latency_set(const stmdev_ctx_t *ctx, 2574 uint8_t *buff); 2575 int32_t lsm6ds3tr_c_tilt_latency_get(const stmdev_ctx_t *ctx, 2576 uint8_t *buff); 2577 2578 int32_t lsm6ds3tr_c_tilt_threshold_set(const stmdev_ctx_t *ctx, 2579 uint8_t *buff); 2580 int32_t lsm6ds3tr_c_tilt_threshold_get(const stmdev_ctx_t *ctx, 2581 uint8_t *buff); 2582 2583 int32_t lsm6ds3tr_c_tilt_src_set(const stmdev_ctx_t *ctx, 2584 lsm6ds3tr_c_a_wrist_tilt_mask_t *val); 2585 int32_t lsm6ds3tr_c_tilt_src_get(const stmdev_ctx_t *ctx, 2586 lsm6ds3tr_c_a_wrist_tilt_mask_t *val); 2587 2588 int32_t lsm6ds3tr_c_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val); 2589 int32_t lsm6ds3tr_c_mag_soft_iron_get(const stmdev_ctx_t *ctx, 2590 uint8_t *val); 2591 2592 int32_t lsm6ds3tr_c_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val); 2593 int32_t lsm6ds3tr_c_mag_hard_iron_get(const stmdev_ctx_t *ctx, 2594 uint8_t *val); 2595 2596 int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx, 2597 uint8_t *buff); 2598 int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx, 2599 uint8_t *buff); 2600 2601 int32_t lsm6ds3tr_c_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 2602 int32_t lsm6ds3tr_c_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 2603 2604 int32_t lsm6ds3tr_c_func_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2605 2606 int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, 2607 uint8_t val); 2608 int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx, 2609 uint8_t *val); 2610 2611 typedef enum 2612 { 2613 LSM6DS3TR_C_RES_RATIO_2_11 = 0, 2614 LSM6DS3TR_C_RES_RATIO_2_12 = 1, 2615 LSM6DS3TR_C_RES_RATIO_2_13 = 2, 2616 LSM6DS3TR_C_RES_RATIO_2_14 = 3, 2617 LSM6DS3TR_C_RES_RATIO_ND = 4, /* ERROR CODE */ 2618 } lsm6ds3tr_c_rr_t; 2619 int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx, 2620 lsm6ds3tr_c_rr_t val); 2621 int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx, 2622 lsm6ds3tr_c_rr_t *val); 2623 2624 int32_t lsm6ds3tr_c_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 2625 int32_t lsm6ds3tr_c_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 2626 2627 int32_t lsm6ds3tr_c_sh_pass_through_set(const stmdev_ctx_t *ctx, 2628 uint8_t val); 2629 int32_t lsm6ds3tr_c_sh_pass_through_get(const stmdev_ctx_t *ctx, 2630 uint8_t *val); 2631 2632 typedef enum 2633 { 2634 LSM6DS3TR_C_EXT_PULL_UP = 0, 2635 LSM6DS3TR_C_INTERNAL_PULL_UP = 1, 2636 LSM6DS3TR_C_SH_PIN_MODE = 2, /* ERROR CODE */ 2637 } lsm6ds3tr_c_pull_up_en_t; 2638 int32_t lsm6ds3tr_c_sh_pin_mode_set(const stmdev_ctx_t *ctx, 2639 lsm6ds3tr_c_pull_up_en_t val); 2640 int32_t lsm6ds3tr_c_sh_pin_mode_get(const stmdev_ctx_t *ctx, 2641 lsm6ds3tr_c_pull_up_en_t *val); 2642 2643 typedef enum 2644 { 2645 LSM6DS3TR_C_XL_GY_DRDY = 0, 2646 LSM6DS3TR_C_EXT_ON_INT2_PIN = 1, 2647 LSM6DS3TR_C_SH_SYNCRO_ND = 2, /* ERROR CODE */ 2648 } lsm6ds3tr_c_start_config_t; 2649 int32_t lsm6ds3tr_c_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 2650 lsm6ds3tr_c_start_config_t val); 2651 int32_t lsm6ds3tr_c_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 2652 lsm6ds3tr_c_start_config_t *val); 2653 2654 int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, 2655 uint8_t val); 2656 int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, 2657 uint8_t *val); 2658 2659 typedef struct 2660 { 2661 lsm6ds3tr_c_sensorhub1_reg_t sh_byte_1; 2662 lsm6ds3tr_c_sensorhub2_reg_t sh_byte_2; 2663 lsm6ds3tr_c_sensorhub3_reg_t sh_byte_3; 2664 lsm6ds3tr_c_sensorhub4_reg_t sh_byte_4; 2665 lsm6ds3tr_c_sensorhub5_reg_t sh_byte_5; 2666 lsm6ds3tr_c_sensorhub6_reg_t sh_byte_6; 2667 lsm6ds3tr_c_sensorhub7_reg_t sh_byte_7; 2668 lsm6ds3tr_c_sensorhub8_reg_t sh_byte_8; 2669 lsm6ds3tr_c_sensorhub9_reg_t sh_byte_9; 2670 lsm6ds3tr_c_sensorhub10_reg_t sh_byte_10; 2671 lsm6ds3tr_c_sensorhub11_reg_t sh_byte_11; 2672 lsm6ds3tr_c_sensorhub12_reg_t sh_byte_12; 2673 lsm6ds3tr_c_sensorhub13_reg_t sh_byte_13; 2674 lsm6ds3tr_c_sensorhub14_reg_t sh_byte_14; 2675 lsm6ds3tr_c_sensorhub15_reg_t sh_byte_15; 2676 lsm6ds3tr_c_sensorhub16_reg_t sh_byte_16; 2677 lsm6ds3tr_c_sensorhub17_reg_t sh_byte_17; 2678 lsm6ds3tr_c_sensorhub18_reg_t sh_byte_18; 2679 } lsm6ds3tr_c_emb_sh_read_t; 2680 int32_t lsm6ds3tr_c_sh_read_data_raw_get(const stmdev_ctx_t *ctx, 2681 lsm6ds3tr_c_emb_sh_read_t *val); 2682 2683 int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, 2684 uint8_t val); 2685 int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, 2686 uint8_t *val); 2687 2688 int32_t lsm6ds3tr_c_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, 2689 uint8_t val); 2690 int32_t lsm6ds3tr_c_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, 2691 uint8_t *val); 2692 2693 typedef enum 2694 { 2695 LSM6DS3TR_C_SLV_0 = 0, 2696 LSM6DS3TR_C_SLV_0_1 = 1, 2697 LSM6DS3TR_C_SLV_0_1_2 = 2, 2698 LSM6DS3TR_C_SLV_0_1_2_3 = 3, 2699 LSM6DS3TR_C_SLV_EN_ND = 4, /* ERROR CODE */ 2700 } lsm6ds3tr_c_aux_sens_on_t; 2701 int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx, 2702 lsm6ds3tr_c_aux_sens_on_t val); 2703 int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx, 2704 lsm6ds3tr_c_aux_sens_on_t *val); 2705 2706 typedef struct 2707 { 2708 uint8_t slv0_add; 2709 uint8_t slv0_subadd; 2710 uint8_t slv0_data; 2711 } lsm6ds3tr_c_sh_cfg_write_t; 2712 int32_t lsm6ds3tr_c_sh_cfg_write(const stmdev_ctx_t *ctx, 2713 lsm6ds3tr_c_sh_cfg_write_t *val); 2714 2715 typedef struct 2716 { 2717 uint8_t slv_add; 2718 uint8_t slv_subadd; 2719 uint8_t slv_len; 2720 } lsm6ds3tr_c_sh_cfg_read_t; 2721 int32_t lsm6ds3tr_c_sh_slv0_cfg_read(const stmdev_ctx_t *ctx, 2722 lsm6ds3tr_c_sh_cfg_read_t *val); 2723 int32_t lsm6ds3tr_c_sh_slv1_cfg_read(const stmdev_ctx_t *ctx, 2724 lsm6ds3tr_c_sh_cfg_read_t *val); 2725 int32_t lsm6ds3tr_c_sh_slv2_cfg_read(const stmdev_ctx_t *ctx, 2726 lsm6ds3tr_c_sh_cfg_read_t *val); 2727 int32_t lsm6ds3tr_c_sh_slv3_cfg_read(const stmdev_ctx_t *ctx, 2728 lsm6ds3tr_c_sh_cfg_read_t *val); 2729 2730 typedef enum 2731 { 2732 LSM6DS3TR_C_SL0_NO_DEC = 0, 2733 LSM6DS3TR_C_SL0_DEC_2 = 1, 2734 LSM6DS3TR_C_SL0_DEC_4 = 2, 2735 LSM6DS3TR_C_SL0_DEC_8 = 3, 2736 LSM6DS3TR_C_SL0_DEC_ND = 4, /* ERROR CODE */ 2737 } lsm6ds3tr_c_slave0_rate_t; 2738 int32_t lsm6ds3tr_c_sh_slave_0_dec_set(const stmdev_ctx_t *ctx, 2739 lsm6ds3tr_c_slave0_rate_t val); 2740 int32_t lsm6ds3tr_c_sh_slave_0_dec_get(const stmdev_ctx_t *ctx, 2741 lsm6ds3tr_c_slave0_rate_t *val); 2742 2743 typedef enum 2744 { 2745 LSM6DS3TR_C_EACH_SH_CYCLE = 0, 2746 LSM6DS3TR_C_ONLY_FIRST_CYCLE = 1, 2747 LSM6DS3TR_C_SH_WR_MODE_ND = 2, /* ERROR CODE */ 2748 } lsm6ds3tr_c_write_once_t; 2749 int32_t lsm6ds3tr_c_sh_write_mode_set(const stmdev_ctx_t *ctx, 2750 lsm6ds3tr_c_write_once_t val); 2751 int32_t lsm6ds3tr_c_sh_write_mode_get(const stmdev_ctx_t *ctx, 2752 lsm6ds3tr_c_write_once_t *val); 2753 2754 typedef enum 2755 { 2756 LSM6DS3TR_C_SL1_NO_DEC = 0, 2757 LSM6DS3TR_C_SL1_DEC_2 = 1, 2758 LSM6DS3TR_C_SL1_DEC_4 = 2, 2759 LSM6DS3TR_C_SL1_DEC_8 = 3, 2760 LSM6DS3TR_C_SL1_DEC_ND = 4, /* ERROR CODE */ 2761 } lsm6ds3tr_c_slave1_rate_t; 2762 int32_t lsm6ds3tr_c_sh_slave_1_dec_set(const stmdev_ctx_t *ctx, 2763 lsm6ds3tr_c_slave1_rate_t val); 2764 int32_t lsm6ds3tr_c_sh_slave_1_dec_get(const stmdev_ctx_t *ctx, 2765 lsm6ds3tr_c_slave1_rate_t *val); 2766 2767 typedef enum 2768 { 2769 LSM6DS3TR_C_SL2_NO_DEC = 0, 2770 LSM6DS3TR_C_SL2_DEC_2 = 1, 2771 LSM6DS3TR_C_SL2_DEC_4 = 2, 2772 LSM6DS3TR_C_SL2_DEC_8 = 3, 2773 LSM6DS3TR_C_SL2_DEC_ND = 4, /* ERROR CODE */ 2774 } lsm6ds3tr_c_slave2_rate_t; 2775 int32_t lsm6ds3tr_c_sh_slave_2_dec_set(const stmdev_ctx_t *ctx, 2776 lsm6ds3tr_c_slave2_rate_t val); 2777 int32_t lsm6ds3tr_c_sh_slave_2_dec_get(const stmdev_ctx_t *ctx, 2778 lsm6ds3tr_c_slave2_rate_t *val); 2779 2780 typedef enum 2781 { 2782 LSM6DS3TR_C_SL3_NO_DEC = 0, 2783 LSM6DS3TR_C_SL3_DEC_2 = 1, 2784 LSM6DS3TR_C_SL3_DEC_4 = 2, 2785 LSM6DS3TR_C_SL3_DEC_8 = 3, 2786 LSM6DS3TR_C_SL3_DEC_ND = 4, /* ERROR CODE */ 2787 } lsm6ds3tr_c_slave3_rate_t; 2788 int32_t lsm6ds3tr_c_sh_slave_3_dec_set(const stmdev_ctx_t *ctx, 2789 lsm6ds3tr_c_slave3_rate_t val); 2790 int32_t lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t *ctx, 2791 lsm6ds3tr_c_slave3_rate_t *val); 2792 2793 /** 2794 * @} 2795 * 2796 */ 2797 2798 #ifdef __cplusplus 2799 } 2800 #endif 2801 2802 #endif /* LSM6DS3TR_C_DRIVER_H */ 2803 2804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2805
