1 /** 2 ****************************************************************************** 3 * @file lsm303ah_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm303ah_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM303AH_REGS_H 23 #define LSM303AH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM303AH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM303AH_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define LSM303AH_I2C_ADD_XL 0x3BU 173 #define LSM303AH_I2C_ADD_MG 0x3DU 174 175 /** Device Identification (Who am I) **/ 176 #define LSM303AH_ID_XL 0x43U 177 #define LSM303AH_ID_MG 0x40U 178 179 /** 180 * @} 181 * 182 */ 183 184 #define LSM303AH_MODULE_8BIT_A 0x0CU 185 #define LSM303AH_WHO_AM_I_A 0x0FU 186 #define LSM303AH_CTRL1_A 0x20U 187 typedef struct 188 { 189 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 190 uint8_t bdu : 1; 191 uint8_t hf_odr : 1; 192 uint8_t fs : 2; 193 uint8_t odr : 4; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t odr : 4; 196 uint8_t fs : 2; 197 uint8_t hf_odr : 1; 198 uint8_t bdu : 1; 199 #endif /* DRV_BYTE_ORDER */ 200 } lsm303ah_ctrl1_a_t; 201 202 #define LSM303AH_CTRL2_A 0x21U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t sim : 1; 207 uint8_t i2c_disable : 1; 208 uint8_t if_add_inc : 1; 209 uint8_t fds_slope : 1; 210 uint8_t func_cfg_en : 1; 211 uint8_t not_used_01 : 1; 212 uint8_t soft_reset : 1; 213 uint8_t boot : 1; 214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 215 uint8_t boot : 1; 216 uint8_t soft_reset : 1; 217 uint8_t not_used_01 : 1; 218 uint8_t func_cfg_en : 1; 219 uint8_t fds_slope : 1; 220 uint8_t if_add_inc : 1; 221 uint8_t i2c_disable : 1; 222 uint8_t sim : 1; 223 #endif /* DRV_BYTE_ORDER */ 224 } lsm303ah_ctrl2_a_t; 225 226 #define LSM303AH_CTRL3_A 0x22U 227 typedef struct 228 { 229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 230 uint8_t pp_od : 1; 231 uint8_t h_lactive : 1; 232 uint8_t lir : 1; 233 uint8_t tap_z_en : 1; 234 uint8_t tap_y_en : 1; 235 uint8_t tap_x_en : 1; 236 uint8_t st : 2; 237 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 238 uint8_t st : 2; 239 uint8_t tap_x_en : 1; 240 uint8_t tap_y_en : 1; 241 uint8_t tap_z_en : 1; 242 uint8_t lir : 1; 243 uint8_t h_lactive : 1; 244 uint8_t pp_od : 1; 245 #endif /* DRV_BYTE_ORDER */ 246 } lsm303ah_ctrl3_a_t; 247 248 #define LSM303AH_CTRL4_A 0x23U 249 typedef struct 250 { 251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 252 uint8_t int1_drdy : 1; 253 uint8_t int1_fth : 1; 254 uint8_t int1_6d : 1; 255 uint8_t int1_tap : 1; 256 uint8_t int1_ff : 1; 257 uint8_t int1_wu : 1; 258 uint8_t int1_s_tap : 1; 259 uint8_t not_used_01 : 1; 260 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 261 uint8_t not_used_01 : 1; 262 uint8_t int1_s_tap : 1; 263 uint8_t int1_wu : 1; 264 uint8_t int1_ff : 1; 265 uint8_t int1_tap : 1; 266 uint8_t int1_6d : 1; 267 uint8_t int1_fth : 1; 268 uint8_t int1_drdy : 1; 269 #endif /* DRV_BYTE_ORDER */ 270 } lsm303ah_ctrl4_a_t; 271 272 #define LSM303AH_CTRL5_A 0x24U 273 typedef struct 274 { 275 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 276 uint8_t int2_drdy : 1; 277 uint8_t int2_fth : 1; 278 uint8_t int2_step : 1; 279 uint8_t int2_sig_mot : 1; 280 uint8_t int2_tilt : 1; 281 uint8_t int2_on_int1 : 1; 282 uint8_t int2_boot : 1; 283 uint8_t drdy_pulsed : 1; 284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 285 uint8_t drdy_pulsed : 1; 286 uint8_t int2_boot : 1; 287 uint8_t int2_on_int1 : 1; 288 uint8_t int2_tilt : 1; 289 uint8_t int2_sig_mot : 1; 290 uint8_t int2_step : 1; 291 uint8_t int2_fth : 1; 292 uint8_t int2_drdy : 1; 293 #endif /* DRV_BYTE_ORDER */ 294 } lsm303ah_ctrl5_a_t; 295 296 #define LSM303AH_FIFO_CTRL_A 0x25U 297 typedef struct 298 { 299 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 300 uint8_t if_cs_pu_dis : 1; 301 uint8_t not_used_01 : 2; 302 uint8_t module_to_fifo : 1; 303 uint8_t int2_step_count_ov : 1; 304 uint8_t fmode : 3; 305 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 306 uint8_t fmode : 3; 307 uint8_t int2_step_count_ov : 1; 308 uint8_t module_to_fifo : 1; 309 uint8_t not_used_01 : 2; 310 uint8_t if_cs_pu_dis : 1; 311 #endif /* DRV_BYTE_ORDER */ 312 } lsm303ah_fifo_ctrl_a_t; 313 314 #define LSM303AH_OUT_T_A 0x26U 315 #define LSM303AH_STATUS_A 0x27U 316 typedef struct 317 { 318 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 319 uint8_t drdy : 1; 320 uint8_t ff_ia : 1; 321 uint8_t _6d_ia : 1; 322 uint8_t single_tap : 1; 323 uint8_t double_tap : 1; 324 uint8_t sleep_state : 1; 325 uint8_t wu_ia : 1; 326 uint8_t fifo_ths : 1; 327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 328 uint8_t fifo_ths : 1; 329 uint8_t wu_ia : 1; 330 uint8_t sleep_state : 1; 331 uint8_t double_tap : 1; 332 uint8_t single_tap : 1; 333 uint8_t _6d_ia : 1; 334 uint8_t ff_ia : 1; 335 uint8_t drdy : 1; 336 #endif /* DRV_BYTE_ORDER */ 337 } lsm303ah_status_a_t; 338 339 #define LSM303AH_OUT_X_L_A 0x28U 340 #define LSM303AH_OUT_X_H_A 0x29U 341 #define LSM303AH_OUT_Y_L_A 0x2AU 342 #define LSM303AH_OUT_Y_H_A 0x2BU 343 #define LSM303AH_OUT_Z_L_A 0x2CU 344 #define LSM303AH_OUT_Z_H_A 0x2DU 345 #define LSM303AH_FIFO_THS_A 0x2EU 346 #define LSM303AH_FIFO_SRC_A 0x2FU 347 typedef struct 348 { 349 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 350 uint8_t not_used_01 : 5; 351 uint8_t diff : 1; 352 uint8_t fifo_ovr : 1; 353 uint8_t fth : 1; 354 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 355 uint8_t fth : 1; 356 uint8_t fifo_ovr : 1; 357 uint8_t diff : 1; 358 uint8_t not_used_01 : 5; 359 #endif /* DRV_BYTE_ORDER */ 360 } lsm303ah_fifo_src_a_t; 361 362 #define LSM303AH_FIFO_SAMPLES_A 0x30U 363 #define LSM303AH_TAP_6D_THS_A 0x31U 364 typedef struct 365 { 366 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 367 uint8_t tap_ths : 5; 368 uint8_t _6d_ths : 2; 369 uint8_t _4d_en : 1; 370 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 371 uint8_t _4d_en : 1; 372 uint8_t _6d_ths : 2; 373 uint8_t tap_ths : 5; 374 #endif /* DRV_BYTE_ORDER */ 375 } lsm303ah_tap_6d_ths_a_t; 376 377 #define LSM303AH_INT_DUR_A 0x32U 378 typedef struct 379 { 380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 381 uint8_t shock : 2; 382 uint8_t quiet : 2; 383 uint8_t lat : 4; 384 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 385 uint8_t lat : 4; 386 uint8_t quiet : 2; 387 uint8_t shock : 2; 388 #endif /* DRV_BYTE_ORDER */ 389 } lsm303ah_int_dur_a_t; 390 391 #define LSM303AH_WAKE_UP_THS_A 0x33U 392 typedef struct 393 { 394 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 395 uint8_t wu_ths : 6; 396 uint8_t sleep_on : 1; 397 uint8_t single_double_tap : 1; 398 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 399 uint8_t single_double_tap : 1; 400 uint8_t sleep_on : 1; 401 uint8_t wu_ths : 6; 402 #endif /* DRV_BYTE_ORDER */ 403 } lsm303ah_wake_up_ths_a_t; 404 405 #define LSM303AH_WAKE_UP_DUR_A 0x34U 406 typedef struct 407 { 408 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 409 uint8_t sleep_dur : 4; 410 uint8_t int1_fss7 : 1; 411 uint8_t wu_dur : 2; 412 uint8_t ff_dur : 1; 413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 414 uint8_t ff_dur : 1; 415 uint8_t wu_dur : 2; 416 uint8_t int1_fss7 : 1; 417 uint8_t sleep_dur : 4; 418 #endif /* DRV_BYTE_ORDER */ 419 } lsm303ah_wake_up_dur_a_t; 420 421 #define LSM303AH_FREE_FALL_A 0x35U 422 typedef struct 423 { 424 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 425 uint8_t ff_ths : 3; 426 uint8_t ff_dur : 5; 427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 428 uint8_t ff_dur : 5; 429 uint8_t ff_ths : 3; 430 #endif /* DRV_BYTE_ORDER */ 431 } lsm303ah_free_fall_a_t; 432 433 #define LSM303AH_STATUS_DUP_A 0x36U 434 typedef struct 435 { 436 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 437 uint8_t drdy : 1; 438 uint8_t ff_ia : 1; 439 uint8_t _6d_ia : 1; 440 uint8_t single_tap : 1; 441 uint8_t double_tap : 1; 442 uint8_t sleep_state : 1; 443 uint8_t wu_ia : 1; 444 uint8_t ovr : 1; 445 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 446 uint8_t ovr : 1; 447 uint8_t wu_ia : 1; 448 uint8_t sleep_state : 1; 449 uint8_t double_tap : 1; 450 uint8_t single_tap : 1; 451 uint8_t _6d_ia : 1; 452 uint8_t ff_ia : 1; 453 uint8_t drdy : 1; 454 #endif /* DRV_BYTE_ORDER */ 455 } lsm303ah_status_dup_a_t; 456 457 #define LSM303AH_WAKE_UP_SRC_A 0x37U 458 typedef struct 459 { 460 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 461 uint8_t z_wu : 1; 462 uint8_t y_wu : 1; 463 uint8_t x_wu : 1; 464 uint8_t wu_ia : 1; 465 uint8_t sleep_state_ia : 1; 466 uint8_t ff_ia : 1; 467 uint8_t not_used_01 : 2; 468 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 469 uint8_t not_used_01 : 2; 470 uint8_t ff_ia : 1; 471 uint8_t sleep_state_ia : 1; 472 uint8_t wu_ia : 1; 473 uint8_t x_wu : 1; 474 uint8_t y_wu : 1; 475 uint8_t z_wu : 1; 476 #endif /* DRV_BYTE_ORDER */ 477 } lsm303ah_wake_up_src_a_t; 478 479 #define LSM303AH_TAP_SRC_A 0x38U 480 typedef struct 481 { 482 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 483 uint8_t z_tap : 1; 484 uint8_t y_tap : 1; 485 uint8_t x_tap : 1; 486 uint8_t tap_sign : 1; 487 uint8_t double_tap : 1; 488 uint8_t single_tap : 1; 489 uint8_t tap_ia : 1; 490 uint8_t not_used_01 : 1; 491 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 492 uint8_t not_used_01 : 1; 493 uint8_t tap_ia : 1; 494 uint8_t single_tap : 1; 495 uint8_t double_tap : 1; 496 uint8_t tap_sign : 1; 497 uint8_t x_tap : 1; 498 uint8_t y_tap : 1; 499 uint8_t z_tap : 1; 500 #endif /* DRV_BYTE_ORDER */ 501 } lsm303ah_tap_src_a_t; 502 503 #define LSM303AH_6D_SRC_A 0x39U 504 typedef struct 505 { 506 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 507 uint8_t xl : 1; 508 uint8_t xh : 1; 509 uint8_t yl : 1; 510 uint8_t yh : 1; 511 uint8_t zl : 1; 512 uint8_t zh : 1; 513 uint8_t _6d_ia : 1; 514 uint8_t not_used_01 : 1; 515 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 516 uint8_t not_used_01 : 1; 517 uint8_t _6d_ia : 1; 518 uint8_t zh : 1; 519 uint8_t zl : 1; 520 uint8_t yh : 1; 521 uint8_t yl : 1; 522 uint8_t xh : 1; 523 uint8_t xl : 1; 524 #endif /* DRV_BYTE_ORDER */ 525 } lsm303ah_6d_src_a_t; 526 527 #define LSM303AH_STEP_COUNTER_MINTHS_A 0x3AU 528 typedef struct 529 { 530 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 531 uint8_t sc_mths : 6; 532 uint8_t pedo4g : 1; 533 uint8_t rst_nstep : 1; 534 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 535 uint8_t rst_nstep : 1; 536 uint8_t pedo4g : 1; 537 uint8_t sc_mths : 6; 538 #endif /* DRV_BYTE_ORDER */ 539 } lsm303ah_step_counter_minths_a_t; 540 541 #define LSM303AH_STEP_COUNTER_L_A 0x3BU 542 #define LSM303AH_STEP_COUNTER_H_A 0x3CU 543 #define LSM303AH_FUNC_CK_GATE_A 0x3DU 544 typedef struct 545 { 546 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 547 uint8_t ck_gate_func : 1; 548 uint8_t step_detect : 1; 549 uint8_t rst_pedo : 1; 550 uint8_t rst_sign_mot : 1; 551 uint8_t sig_mot_detect : 1; 552 uint8_t fs_src : 2; 553 uint8_t tilt_int : 1; 554 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 555 uint8_t tilt_int : 1; 556 uint8_t fs_src : 2; 557 uint8_t sig_mot_detect : 1; 558 uint8_t rst_sign_mot : 1; 559 uint8_t rst_pedo : 1; 560 uint8_t step_detect : 1; 561 uint8_t ck_gate_func : 1; 562 #endif /* DRV_BYTE_ORDER */ 563 } lsm303ah_func_ck_gate_a_t; 564 565 #define LSM303AH_FUNC_SRC_A 0x3EU 566 typedef struct 567 { 568 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 569 uint8_t not_used_01 : 1; 570 uint8_t module_ready : 1; 571 uint8_t rst_tilt : 1; 572 uint8_t not_used_02 : 5; 573 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 574 uint8_t not_used_02 : 5; 575 uint8_t rst_tilt : 1; 576 uint8_t module_ready : 1; 577 uint8_t not_used_01 : 1; 578 #endif /* DRV_BYTE_ORDER */ 579 } lsm303ah_func_src_a_t; 580 581 #define LSM303AH_FUNC_CTRL_A 0x3FU 582 typedef struct 583 { 584 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 585 uint8_t step_cnt_on : 1; 586 uint8_t sign_mot_on : 1; 587 uint8_t not_used_01 : 2; 588 uint8_t tilt_on : 1; 589 uint8_t module_on : 1; 590 uint8_t not_used_02 : 2; 591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 592 uint8_t not_used_02 : 2; 593 uint8_t module_on : 1; 594 uint8_t tilt_on : 1; 595 uint8_t not_used_01 : 2; 596 uint8_t sign_mot_on : 1; 597 uint8_t step_cnt_on : 1; 598 #endif /* DRV_BYTE_ORDER */ 599 } lsm303ah_func_ctrl_a_t; 600 601 #define LSM303AH_PEDO_DEB_REG_A 0x2BU 602 typedef struct 603 { 604 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 605 uint8_t deb_step : 3; 606 uint8_t deb_time : 5; 607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 608 uint8_t deb_time : 5; 609 uint8_t deb_step : 3; 610 #endif /* DRV_BYTE_ORDER */ 611 } lsm303ah_pedo_deb_reg_a_t; 612 613 #define LSM303AH_SM_THS_A 0x34U 614 typedef struct 615 { 616 uint8_t sm_ths : 8; 617 } lsm303ah_sm_ths_a_t; 618 619 #define LSM303AH_STEP_COUNT_DELTA_A 0x3AU 620 typedef struct 621 { 622 uint8_t step_count_d : 8; 623 } lsm303ah_step_count_delta_a_t; 624 625 #define LSM303AH_CTRL2_ADV_A 0x3FU 626 typedef struct 627 { 628 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 629 uint8_t sim : 1; 630 uint8_t i2c_disable : 1; 631 uint8_t if_add_inc : 1; 632 uint8_t fds_slope : 1; 633 uint8_t func_cfg_en : 1; 634 uint8_t not_used_01 : 1; 635 uint8_t soft_reset : 1; 636 uint8_t boot : 1; 637 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 638 uint8_t boot : 1; 639 uint8_t soft_reset : 1; 640 uint8_t not_used_01 : 1; 641 uint8_t func_cfg_en : 1; 642 uint8_t fds_slope : 1; 643 uint8_t if_add_inc : 1; 644 uint8_t i2c_disable : 1; 645 uint8_t sim : 1; 646 #endif /* DRV_BYTE_ORDER */ 647 } lsm303ah_ctrl2_adv_a_t; 648 649 #define LSM303AH_OFFSET_X_REG_L_M 0x45U 650 #define LSM303AH_OFFSET_X_REG_H_M 0x46U 651 #define LSM303AH_OFFSET_Y_REG_L_M 0x47U 652 #define LSM303AH_OFFSET_Y_REG_H_M 0x48U 653 #define LSM303AH_OFFSET_Z_REG_L_M 0x49U 654 #define LSM303AH_OFFSET_Z_REG_H_M 0x4AU 655 #define LSM303AH_WHO_AM_I_M 0x4FU 656 #define LSM303AH_CFG_REG_A_M 0x60U 657 typedef struct 658 { 659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 660 uint8_t md : 2; 661 uint8_t odr : 2; 662 uint8_t lp : 1; 663 uint8_t soft_rst : 1; 664 uint8_t reboot : 1; 665 uint8_t comp_temp_en : 1; 666 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 667 uint8_t comp_temp_en : 1; 668 uint8_t reboot : 1; 669 uint8_t soft_rst : 1; 670 uint8_t lp : 1; 671 uint8_t odr : 2; 672 uint8_t md : 2; 673 #endif /* DRV_BYTE_ORDER */ 674 } lsm303ah_cfg_reg_a_m_t; 675 676 #define LSM303AH_CFG_REG_B_M 0x61U 677 typedef struct 678 { 679 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 680 uint8_t lpf : 1; 681 uint8_t set_rst : 2; /* off_canc + set_freq */ 682 uint8_t int_on_dataoff : 1; 683 uint8_t off_canc_one_shot : 1; 684 uint8_t not_used_01 : 3; 685 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 686 uint8_t not_used_01 : 3; 687 uint8_t off_canc_one_shot : 1; 688 uint8_t int_on_dataoff : 1; 689 uint8_t set_rst : 2; /* off_canc + set_freq */ 690 uint8_t lpf : 1; 691 #endif /* DRV_BYTE_ORDER */ 692 } lsm303ah_cfg_reg_b_m_t; 693 694 #define LSM303AH_CFG_REG_C_M 0x62U 695 typedef struct 696 { 697 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 698 uint8_t int_mag : 1; 699 uint8_t self_test : 1; 700 uint8_t not_used_01 : 1; 701 uint8_t ble : 1; 702 uint8_t bdu : 1; 703 uint8_t i2c_dis : 1; 704 uint8_t int_mag_pin : 1; 705 uint8_t not_used_02 : 1; 706 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 707 uint8_t not_used_02 : 1; 708 uint8_t int_mag_pin : 1; 709 uint8_t i2c_dis : 1; 710 uint8_t bdu : 1; 711 uint8_t ble : 1; 712 uint8_t not_used_01 : 1; 713 uint8_t self_test : 1; 714 uint8_t int_mag : 1; 715 #endif /* DRV_BYTE_ORDER */ 716 } lsm303ah_cfg_reg_c_m_t; 717 718 #define LSM303AH_INT_CRTL_REG_M 0x63U 719 typedef struct 720 { 721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 722 uint8_t ien : 1; 723 uint8_t iel : 1; 724 uint8_t iea : 1; 725 uint8_t not_used_01 : 2; 726 uint8_t zien : 1; 727 uint8_t yien : 1; 728 uint8_t xien : 1; 729 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 730 uint8_t xien : 1; 731 uint8_t yien : 1; 732 uint8_t zien : 1; 733 uint8_t not_used_01 : 2; 734 uint8_t iea : 1; 735 uint8_t iel : 1; 736 uint8_t ien : 1; 737 #endif /* DRV_BYTE_ORDER */ 738 } lsm303ah_int_crtl_reg_m_t; 739 740 #define LSM303AH_INT_SOURCE_REG_M 0x64U 741 typedef struct 742 { 743 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 744 uint8_t _int : 1; 745 uint8_t mroi : 1; 746 uint8_t n_th_s_z : 1; 747 uint8_t n_th_s_y : 1; 748 uint8_t n_th_s_x : 1; 749 uint8_t p_th_s_z : 1; 750 uint8_t p_th_s_y : 1; 751 uint8_t p_th_s_x : 1; 752 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 753 uint8_t p_th_s_x : 1; 754 uint8_t p_th_s_y : 1; 755 uint8_t p_th_s_z : 1; 756 uint8_t n_th_s_x : 1; 757 uint8_t n_th_s_y : 1; 758 uint8_t n_th_s_z : 1; 759 uint8_t mroi : 1; 760 uint8_t _int : 1; 761 #endif /* DRV_BYTE_ORDER */ 762 } lsm303ah_int_source_reg_m_t; 763 764 #define LSM303AH_INT_THS_L_REG_M 0x65U 765 #define LSM303AH_INT_THS_H_REG_M 0x66U 766 #define LSM303AH_STATUS_REG_M 0x67U 767 typedef struct 768 { 769 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 770 uint8_t xda : 1; 771 uint8_t yda : 1; 772 uint8_t zda : 1; 773 uint8_t zyxda : 1; 774 uint8_t _xor : 1; 775 uint8_t yor : 1; 776 uint8_t zor : 1; 777 uint8_t zyxor : 1; 778 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 779 uint8_t zyxor : 1; 780 uint8_t zor : 1; 781 uint8_t yor : 1; 782 uint8_t _xor : 1; 783 uint8_t zyxda : 1; 784 uint8_t zda : 1; 785 uint8_t yda : 1; 786 uint8_t xda : 1; 787 #endif /* DRV_BYTE_ORDER */ 788 } lsm303ah_status_reg_m_t; 789 790 #define LSM303AH_OUTX_L_REG_M 0x68U 791 #define LSM303AH_OUTX_H_REG_M 0x69U 792 #define LSM303AH_OUTY_L_REG_M 0x6AU 793 #define LSM303AH_OUTY_H_REG_M 0x6BU 794 #define LSM303AH_OUTZ_L_REG_M 0x6CU 795 #define LSM303AH_OUTZ_H_REG_M 0x6DU 796 797 /** 798 * @defgroup LSM303AH_Register_Union 799 * @brief This union group all the registers having a bit-field 800 * description. 801 * This union is useful but it's not needed by the driver. 802 * 803 * REMOVING this union you are compliant with: 804 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 805 * 806 * @{ 807 * 808 */ 809 typedef union 810 { 811 lsm303ah_ctrl1_a_t ctrl1_a; 812 lsm303ah_ctrl2_a_t ctrl2_a; 813 lsm303ah_ctrl3_a_t ctrl3_a; 814 lsm303ah_ctrl4_a_t ctrl4_a; 815 lsm303ah_ctrl5_a_t ctrl5_a; 816 lsm303ah_fifo_ctrl_a_t fifo_ctrl_a; 817 lsm303ah_status_a_t status_a; 818 lsm303ah_fifo_src_a_t fifo_src_a; 819 lsm303ah_tap_6d_ths_a_t tap_6d_ths_a; 820 lsm303ah_int_dur_a_t int_dur_a; 821 lsm303ah_wake_up_ths_a_t wake_up_ths_a; 822 lsm303ah_wake_up_dur_a_t wake_up_dur_a; 823 lsm303ah_free_fall_a_t free_fall_a; 824 lsm303ah_status_dup_a_t status_dup_a; 825 lsm303ah_wake_up_src_a_t wake_up_src_a; 826 lsm303ah_tap_src_a_t tap_src_a; 827 lsm303ah_6d_src_a_t _6d_src_a; 828 lsm303ah_step_counter_minths_a_t step_counter_minths_a; 829 lsm303ah_func_ck_gate_a_t func_ck_gate_a; 830 lsm303ah_func_src_a_t func_src_a; 831 lsm303ah_func_ctrl_a_t func_ctrl_a; 832 lsm303ah_pedo_deb_reg_a_t pedo_deb_reg_a; 833 lsm303ah_sm_ths_a_t sm_ths_a; 834 lsm303ah_step_count_delta_a_t step_count_delta_a; 835 lsm303ah_ctrl2_adv_a_t ctrl2_adv_a; 836 lsm303ah_cfg_reg_a_m_t cfg_reg_a_m; 837 lsm303ah_cfg_reg_b_m_t cfg_reg_b_m; 838 lsm303ah_cfg_reg_c_m_t cfg_reg_c_m; 839 lsm303ah_int_crtl_reg_m_t int_crtl_reg_m; 840 lsm303ah_int_source_reg_m_t int_source_reg_m; 841 lsm303ah_status_reg_m_t status_reg_m; 842 bitwise_t bitwise; 843 uint8_t byte; 844 } lsm303ah_reg_t; 845 846 /** 847 * @} 848 * 849 */ 850 851 #ifndef __weak 852 #define __weak __attribute__((weak)) 853 #endif /* __weak */ 854 855 /* 856 * These are the basic platform dependent I/O routines to read 857 * and write device registers connected on a standard bus. 858 * The driver keeps offering a default implementation based on function 859 * pointers to read/write routines for backward compatibility. 860 * The __weak directive allows the final application to overwrite 861 * them with a custom implementation. 862 */ 863 864 int32_t lsm303ah_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 865 uint8_t *data, 866 uint16_t len); 867 int32_t lsm303ah_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 868 uint8_t *data, 869 uint16_t len); 870 871 float_t lsm303ah_from_fs2g_to_mg(int16_t lsb); 872 float_t lsm303ah_from_fs4g_to_mg(int16_t lsb); 873 float_t lsm303ah_from_fs8g_to_mg(int16_t lsb); 874 float_t lsm303ah_from_fs16g_to_mg(int16_t lsb); 875 876 float_t lsm303ah_from_lsb_to_mgauss(int16_t lsb); 877 878 float_t lsm303ah_from_lsb_to_celsius(int16_t lsb); 879 880 typedef struct 881 { 882 lsm303ah_fifo_src_a_t fifo_src_a; 883 lsm303ah_status_dup_a_t status_dup_a; 884 lsm303ah_wake_up_src_a_t wake_up_src_a; 885 lsm303ah_tap_src_a_t tap_src_a; 886 lsm303ah_6d_src_a_t _6d_src_a; 887 lsm303ah_func_ck_gate_a_t func_ck_gate_a; 888 lsm303ah_func_src_a_t func_src_a; 889 } lsm303ah_xl_all_sources_t; 890 int32_t lsm303ah_xl_all_sources_get(const stmdev_ctx_t *ctx, 891 lsm303ah_xl_all_sources_t *val); 892 893 894 int32_t lsm303ah_xl_block_data_update_set(const stmdev_ctx_t *ctx, 895 uint8_t val); 896 int32_t lsm303ah_xl_block_data_update_get(const stmdev_ctx_t *ctx, 897 uint8_t *val); 898 899 int32_t lsm303ah_mg_block_data_update_set(const stmdev_ctx_t *ctx, 900 uint8_t val); 901 int32_t lsm303ah_mg_block_data_update_get(const stmdev_ctx_t *ctx, 902 uint8_t *val); 903 904 typedef enum 905 { 906 LSM303AH_MG_LSB_AT_LOW_ADD = 0, 907 LSM303AH_MG_MSB_AT_LOW_ADD = 1, 908 } lsm303ah_mg_ble_t; 909 int32_t lsm303ah_mg_data_format_set(const stmdev_ctx_t *ctx, 910 lsm303ah_mg_ble_t val); 911 int32_t lsm303ah_mg_data_format_get(const stmdev_ctx_t *ctx, 912 lsm303ah_mg_ble_t *val); 913 914 typedef enum 915 { 916 LSM303AH_XL_2g = 0, 917 LSM303AH_XL_16g = 1, 918 LSM303AH_XL_4g = 2, 919 LSM303AH_XL_8g = 3, 920 } lsm303ah_xl_fs_t; 921 int32_t lsm303ah_xl_full_scale_set(const stmdev_ctx_t *ctx, 922 lsm303ah_xl_fs_t val); 923 int32_t lsm303ah_xl_full_scale_get(const stmdev_ctx_t *ctx, 924 lsm303ah_xl_fs_t *val); 925 926 typedef enum 927 { 928 LSM303AH_XL_ODR_OFF = 0x00, 929 LSM303AH_XL_ODR_1Hz_LP = 0x08, 930 LSM303AH_XL_ODR_12Hz5_LP = 0x09, 931 LSM303AH_XL_ODR_25Hz_LP = 0x0A, 932 LSM303AH_XL_ODR_50Hz_LP = 0x0B, 933 LSM303AH_XL_ODR_100Hz_LP = 0x0C, 934 LSM303AH_XL_ODR_200Hz_LP = 0x0D, 935 LSM303AH_XL_ODR_400Hz_LP = 0x0E, 936 LSM303AH_XL_ODR_800Hz_LP = 0x0F, 937 LSM303AH_XL_ODR_12Hz5_HR = 0x01, 938 LSM303AH_XL_ODR_25Hz_HR = 0x02, 939 LSM303AH_XL_ODR_50Hz_HR = 0x03, 940 LSM303AH_XL_ODR_100Hz_HR = 0x04, 941 LSM303AH_XL_ODR_200Hz_HR = 0x05, 942 LSM303AH_XL_ODR_400Hz_HR = 0x06, 943 LSM303AH_XL_ODR_800Hz_HR = 0x07, 944 LSM303AH_XL_ODR_1k6Hz_HF = 0x15, 945 LSM303AH_XL_ODR_3k2Hz_HF = 0x16, 946 LSM303AH_XL_ODR_6k4Hz_HF = 0x17, 947 } lsm303ah_xl_odr_t; 948 int32_t lsm303ah_xl_data_rate_set(const stmdev_ctx_t *ctx, 949 lsm303ah_xl_odr_t val); 950 int32_t lsm303ah_xl_data_rate_get(const stmdev_ctx_t *ctx, 951 lsm303ah_xl_odr_t *val); 952 953 int32_t lsm303ah_xl_status_reg_get(const stmdev_ctx_t *ctx, 954 lsm303ah_status_a_t *val); 955 956 int32_t lsm303ah_mg_status_get(const stmdev_ctx_t *ctx, 957 lsm303ah_status_reg_m_t *val); 958 959 int32_t lsm303ah_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, 960 uint8_t *val); 961 962 int32_t lsm303ah_mg_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 963 int32_t lsm303ah_mg_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 964 965 int32_t lsm303ah_mg_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 966 int32_t lsm303ah_mg_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 967 968 typedef enum 969 { 970 LSM303AH_MG_CONTINUOUS_MODE = 0, 971 LSM303AH_MG_SINGLE_TRIGGER = 1, 972 LSM303AH_MG_POWER_DOWN = 2, 973 } lsm303ah_mg_md_t; 974 int32_t lsm303ah_mg_operating_mode_set(const stmdev_ctx_t *ctx, 975 lsm303ah_mg_md_t val); 976 int32_t lsm303ah_mg_operating_mode_get(const stmdev_ctx_t *ctx, 977 lsm303ah_mg_md_t *val); 978 979 typedef enum 980 { 981 LSM303AH_MG_ODR_10Hz = 0, 982 LSM303AH_MG_ODR_20Hz = 1, 983 LSM303AH_MG_ODR_50Hz = 2, 984 LSM303AH_MG_ODR_100Hz = 3, 985 } lsm303ah_mg_odr_t; 986 int32_t lsm303ah_mg_data_rate_set(const stmdev_ctx_t *ctx, 987 lsm303ah_mg_odr_t val); 988 int32_t lsm303ah_mg_data_rate_get(const stmdev_ctx_t *ctx, 989 lsm303ah_mg_odr_t *val); 990 991 typedef enum 992 { 993 LSM303AH_MG_HIGH_RESOLUTION = 0, 994 LSM303AH_MG_LOW_POWER = 1, 995 } lsm303ah_mg_lp_t; 996 int32_t lsm303ah_mg_power_mode_set(const stmdev_ctx_t *ctx, 997 lsm303ah_mg_lp_t val); 998 int32_t lsm303ah_mg_power_mode_get(const stmdev_ctx_t *ctx, 999 lsm303ah_mg_lp_t *val); 1000 1001 int32_t lsm303ah_mg_offset_temp_comp_set(const stmdev_ctx_t *ctx, 1002 uint8_t val); 1003 int32_t lsm303ah_mg_offset_temp_comp_get(const stmdev_ctx_t *ctx, 1004 uint8_t *val); 1005 1006 typedef enum 1007 { 1008 LSM303AH_MG_SET_SENS_ODR_DIV_63 = 0, 1009 LSM303AH_MG_SENS_OFF_CANC_EVERY_ODR = 1, 1010 LSM303AH_MG_SET_SENS_ONLY_AT_POWER_ON = 2, 1011 } lsm303ah_mg_set_rst_t; 1012 int32_t lsm303ah_mg_set_rst_mode_set(const stmdev_ctx_t *ctx, 1013 lsm303ah_mg_set_rst_t val); 1014 int32_t lsm303ah_mg_set_rst_mode_get(const stmdev_ctx_t *ctx, 1015 lsm303ah_mg_set_rst_t *val); 1016 1017 int32_t lsm303ah_mg_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, 1018 uint8_t val); 1019 int32_t lsm303ah_mg_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, 1020 uint8_t *val); 1021 1022 int32_t lsm303ah_acceleration_module_raw_get(const stmdev_ctx_t *ctx, 1023 uint8_t *buff); 1024 1025 int32_t lsm303ah_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1026 1027 int32_t lsm303ah_xl_temperature_raw_get(const stmdev_ctx_t *ctx, 1028 uint8_t *buff); 1029 1030 int32_t lsm303ah_acceleration_raw_get(const stmdev_ctx_t *ctx, 1031 int16_t *val); 1032 1033 int32_t lsm303ah_number_of_steps_get(const stmdev_ctx_t *ctx, 1034 uint16_t *val); 1035 1036 int32_t lsm303ah_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1037 1038 int32_t lsm303ah_mg_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1039 1040 int32_t lsm303ah_xl_auto_increment_set(const stmdev_ctx_t *ctx, 1041 uint8_t val); 1042 int32_t lsm303ah_xl_auto_increment_get(const stmdev_ctx_t *ctx, 1043 uint8_t *val); 1044 1045 typedef enum 1046 { 1047 LSM303AH_XL_USER_BANK = 0, 1048 LSM303AH_XL_ADV_BANK = 1, 1049 } lsm303ah_xl_func_cfg_en_t; 1050 int32_t lsm303ah_xl_mem_bank_set(const stmdev_ctx_t *ctx, 1051 lsm303ah_xl_func_cfg_en_t val); 1052 1053 int32_t lsm303ah_xl_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 1054 int32_t lsm303ah_xl_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1055 1056 int32_t lsm303ah_mg_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 1057 int32_t lsm303ah_mg_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1058 1059 int32_t lsm303ah_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 1060 int32_t lsm303ah_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 1061 1062 int32_t lsm303ah_mg_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 1063 int32_t lsm303ah_mg_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 1064 1065 typedef enum 1066 { 1067 LSM303AH_XL_ST_DISABLE = 0, 1068 LSM303AH_XL_ST_POSITIVE = 1, 1069 LSM303AH_XL_ST_NEGATIVE = 2, 1070 } lsm303ah_xl_st_t; 1071 int32_t lsm303ah_xl_self_test_set(const stmdev_ctx_t *ctx, 1072 lsm303ah_xl_st_t val); 1073 int32_t lsm303ah_xl_self_test_get(const stmdev_ctx_t *ctx, 1074 lsm303ah_xl_st_t *val); 1075 1076 int32_t lsm303ah_mg_self_test_set(const stmdev_ctx_t *ctx, uint8_t val); 1077 int32_t lsm303ah_mg_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val); 1078 1079 typedef enum 1080 { 1081 LSM303AH_XL_DRDY_LATCHED = 0, 1082 LSM303AH_XL_DRDY_PULSED = 1, 1083 } lsm303ah_xl_drdy_pulsed_t; 1084 int32_t lsm303ah_xl_data_ready_mode_set(const stmdev_ctx_t *ctx, 1085 lsm303ah_xl_drdy_pulsed_t val); 1086 int32_t lsm303ah_xl_data_ready_mode_get(const stmdev_ctx_t *ctx, 1087 lsm303ah_xl_drdy_pulsed_t *val); 1088 1089 typedef enum 1090 { 1091 LSM303AH_XL_HP_INTERNAL_ONLY = 0, 1092 LSM303AH_XL_HP_ON_OUTPUTS = 1, 1093 } lsm303ah_xl_fds_slope_t; 1094 int32_t lsm303ah_xl_hp_path_set(const stmdev_ctx_t *ctx, 1095 lsm303ah_xl_fds_slope_t val); 1096 int32_t lsm303ah_xl_hp_path_get(const stmdev_ctx_t *ctx, 1097 lsm303ah_xl_fds_slope_t *val); 1098 1099 typedef enum 1100 { 1101 LSM303AH_MG_ODR_DIV_2 = 0, 1102 LSM303AH_MG_ODR_DIV_4 = 1, 1103 } lsm303ah_mg_lpf_t; 1104 int32_t lsm303ah_mg_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, 1105 lsm303ah_mg_lpf_t val); 1106 int32_t lsm303ah_mg_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, 1107 lsm303ah_mg_lpf_t *val); 1108 1109 typedef enum 1110 { 1111 LSM303AH_XL_SPI_4_WIRE = 0, 1112 LSM303AH_XL_SPI_3_WIRE = 1, 1113 } lsm303ah_xl_sim_t; 1114 int32_t lsm303ah_xl_spi_mode_set(const stmdev_ctx_t *ctx, 1115 lsm303ah_xl_sim_t val); 1116 int32_t lsm303ah_xl_spi_mode_get(const stmdev_ctx_t *ctx, 1117 lsm303ah_xl_sim_t *val); 1118 1119 typedef enum 1120 { 1121 LSM303AH_XL_I2C_ENABLE = 0, 1122 LSM303AH_XL_I2C_DISABLE = 1, 1123 } lsm303ah_xl_i2c_disable_t; 1124 int32_t lsm303ah_xl_i2c_interface_set(const stmdev_ctx_t *ctx, 1125 lsm303ah_xl_i2c_disable_t val); 1126 int32_t lsm303ah_xl_i2c_interface_get(const stmdev_ctx_t *ctx, 1127 lsm303ah_xl_i2c_disable_t *val); 1128 1129 typedef enum 1130 { 1131 LSM303AH_MG_I2C_ENABLE = 0, 1132 LSM303AH_MG_I2C_DISABLE = 1, 1133 } lsm303ah_mg_i2c_dis_t; 1134 int32_t lsm303ah_mg_i2c_interface_set(const stmdev_ctx_t *ctx, 1135 lsm303ah_mg_i2c_dis_t val); 1136 int32_t lsm303ah_mg_i2c_interface_get(const stmdev_ctx_t *ctx, 1137 lsm303ah_mg_i2c_dis_t *val); 1138 1139 typedef enum 1140 { 1141 LSM303AH_XL_PULL_UP_CONNECTED = 0, 1142 LSM303AH_XL_PULL_UP_DISCONNECTED = 1, 1143 } lsm303ah_xl_if_cs_pu_dis_t; 1144 int32_t lsm303ah_xl_cs_mode_set(const stmdev_ctx_t *ctx, 1145 lsm303ah_xl_if_cs_pu_dis_t val); 1146 int32_t lsm303ah_xl_cs_mode_get(const stmdev_ctx_t *ctx, 1147 lsm303ah_xl_if_cs_pu_dis_t *val); 1148 1149 typedef enum 1150 { 1151 LSM303AH_XL_PUSH_PULL = 0, 1152 LSM303AH_XL_OPEN_DRAIN = 1, 1153 } lsm303ah_xl_pp_od_t; 1154 int32_t lsm303ah_xl_pin_mode_set(const stmdev_ctx_t *ctx, 1155 lsm303ah_xl_pp_od_t val); 1156 int32_t lsm303ah_xl_pin_mode_get(const stmdev_ctx_t *ctx, 1157 lsm303ah_xl_pp_od_t *val); 1158 1159 typedef enum 1160 { 1161 LSM303AH_XL_ACTIVE_HIGH = 0, 1162 LSM303AH_XL_ACTIVE_LOW = 1, 1163 } lsm303ah_xl_h_lactive_t; 1164 int32_t lsm303ah_xl_pin_polarity_set(const stmdev_ctx_t *ctx, 1165 lsm303ah_xl_h_lactive_t val); 1166 int32_t lsm303ah_xl_pin_polarity_get(const stmdev_ctx_t *ctx, 1167 lsm303ah_xl_h_lactive_t *val); 1168 1169 typedef enum 1170 { 1171 LSM303AH_XL_INT_PULSED = 0, 1172 LSM303AH_XL_INT_LATCHED = 1, 1173 } lsm303ah_xl_lir_t; 1174 int32_t lsm303ah_xl_int_notification_set(const stmdev_ctx_t *ctx, 1175 lsm303ah_xl_lir_t val); 1176 int32_t lsm303ah_xl_int_notification_get(const stmdev_ctx_t *ctx, 1177 lsm303ah_xl_lir_t *val); 1178 1179 typedef struct 1180 { 1181 uint8_t int1_drdy : 1; 1182 uint8_t int1_fth : 1; 1183 uint8_t int1_6d : 1; 1184 uint8_t int1_tap : 1; 1185 uint8_t int1_ff : 1; 1186 uint8_t int1_wu : 1; 1187 uint8_t int1_s_tap : 1; 1188 uint8_t int1_fss7 : 1; 1189 } lsm303ah_xl_pin_int1_route_t; 1190 int32_t lsm303ah_xl_pin_int1_route_set(const stmdev_ctx_t *ctx, 1191 lsm303ah_xl_pin_int1_route_t val); 1192 int32_t lsm303ah_xl_pin_int1_route_get(const stmdev_ctx_t *ctx, 1193 lsm303ah_xl_pin_int1_route_t *val); 1194 1195 typedef struct 1196 { 1197 uint8_t int2_boot : 1; 1198 uint8_t int2_tilt : 1; 1199 uint8_t int2_sig_mot : 1; 1200 uint8_t int2_step : 1; 1201 uint8_t int2_fth : 1; 1202 uint8_t int2_drdy : 1; 1203 } lsm303ah_xl_pin_int2_route_t; 1204 int32_t lsm303ah_xl_pin_int2_route_set(const stmdev_ctx_t *ctx, 1205 lsm303ah_xl_pin_int2_route_t val); 1206 int32_t lsm303ah_xl_pin_int2_route_get(const stmdev_ctx_t *ctx, 1207 lsm303ah_xl_pin_int2_route_t *val); 1208 1209 int32_t lsm303ah_xl_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 1210 int32_t lsm303ah_xl_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 1211 1212 int32_t lsm303ah_mg_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 1213 int32_t lsm303ah_mg_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); 1214 1215 int32_t lsm303ah_mg_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 1216 int32_t lsm303ah_mg_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); 1217 1218 int32_t lsm303ah_mg_int_gen_conf_set(const stmdev_ctx_t *ctx, 1219 lsm303ah_int_crtl_reg_m_t *val); 1220 int32_t lsm303ah_mg_int_gen_conf_get(const stmdev_ctx_t *ctx, 1221 lsm303ah_int_crtl_reg_m_t *val); 1222 1223 int32_t lsm303ah_mg_int_gen_source_get(const stmdev_ctx_t *ctx, 1224 lsm303ah_int_source_reg_m_t *val); 1225 1226 int32_t lsm303ah_mg_int_gen_threshold_set(const stmdev_ctx_t *ctx, 1227 uint16_t val); 1228 int32_t lsm303ah_mg_int_gen_threshold_get(const stmdev_ctx_t *ctx, 1229 uint16_t *val); 1230 1231 typedef enum 1232 { 1233 LSM303AH_MG_CHECK_BEFORE = 0, 1234 LSM303AH_MG_CHECK_AFTER = 1, 1235 } lsm303ah_mg_int_on_dataoff_t; 1236 int32_t lsm303ah_mg_offset_int_conf_set(const stmdev_ctx_t *ctx, 1237 lsm303ah_mg_int_on_dataoff_t val); 1238 int32_t lsm303ah_mg_offset_int_conf_get(const stmdev_ctx_t *ctx, 1239 lsm303ah_mg_int_on_dataoff_t *val); 1240 1241 int32_t lsm303ah_xl_wkup_threshold_set(const stmdev_ctx_t *ctx, 1242 uint8_t val); 1243 int32_t lsm303ah_xl_wkup_threshold_get(const stmdev_ctx_t *ctx, 1244 uint8_t *val); 1245 1246 int32_t lsm303ah_xl_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1247 int32_t lsm303ah_xl_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1248 1249 int32_t lsm303ah_xl_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1250 int32_t lsm303ah_xl_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1251 1252 int32_t lsm303ah_xl_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1253 int32_t lsm303ah_xl_act_sleep_dur_get(const stmdev_ctx_t *ctx, 1254 uint8_t *val); 1255 1256 int32_t lsm303ah_xl_tap_detection_on_z_set(const stmdev_ctx_t *ctx, 1257 uint8_t val); 1258 int32_t lsm303ah_xl_tap_detection_on_z_get(const stmdev_ctx_t *ctx, 1259 uint8_t *val); 1260 1261 int32_t lsm303ah_xl_tap_detection_on_y_set(const stmdev_ctx_t *ctx, 1262 uint8_t val); 1263 int32_t lsm303ah_xl_tap_detection_on_y_get(const stmdev_ctx_t *ctx, 1264 uint8_t *val); 1265 1266 int32_t lsm303ah_xl_tap_detection_on_x_set(const stmdev_ctx_t *ctx, 1267 uint8_t val); 1268 int32_t lsm303ah_xl_tap_detection_on_x_get(const stmdev_ctx_t *ctx, 1269 uint8_t *val); 1270 1271 int32_t lsm303ah_xl_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1272 int32_t lsm303ah_xl_tap_threshold_get(const stmdev_ctx_t *ctx, 1273 uint8_t *val); 1274 1275 int32_t lsm303ah_xl_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val); 1276 int32_t lsm303ah_xl_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val); 1277 1278 int32_t lsm303ah_xl_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val); 1279 int32_t lsm303ah_xl_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val); 1280 1281 int32_t lsm303ah_xl_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1282 int32_t lsm303ah_xl_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1283 1284 typedef enum 1285 { 1286 LSM303AH_XL_ONLY_SINGLE = 0, 1287 LSM303AH_XL_ONLY_DOUBLE = 1, 1288 } lsm303ah_xl_single_double_tap_t; 1289 int32_t lsm303ah_xl_tap_mode_set(const stmdev_ctx_t *ctx, 1290 lsm303ah_xl_single_double_tap_t val); 1291 int32_t lsm303ah_xl_tap_mode_get(const stmdev_ctx_t *ctx, 1292 lsm303ah_xl_single_double_tap_t *val); 1293 1294 int32_t lsm303ah_xl_tap_src_get(const stmdev_ctx_t *ctx, 1295 lsm303ah_tap_src_a_t *val); 1296 1297 typedef enum 1298 { 1299 LSM303AH_XL_DEG_80 = 0, 1300 LSM303AH_XL_DEG_70 = 1, 1301 LSM303AH_XL_DEG_60 = 2, 1302 LSM303AH_XL_DEG_50 = 3, 1303 } lsm303ah_xl_6d_ths_t; 1304 int32_t lsm303ah_xl_6d_threshold_set(const stmdev_ctx_t *ctx, 1305 lsm303ah_xl_6d_ths_t val); 1306 int32_t lsm303ah_xl_6d_threshold_get(const stmdev_ctx_t *ctx, 1307 lsm303ah_xl_6d_ths_t *val); 1308 1309 int32_t lsm303ah_xl_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1310 int32_t lsm303ah_xl_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1311 1312 int32_t lsm303ah_xl_6d_src_get(const stmdev_ctx_t *ctx, 1313 lsm303ah_6d_src_a_t *val); 1314 1315 int32_t lsm303ah_xl_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1316 int32_t lsm303ah_xl_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1317 1318 int32_t lsm303ah_xl_ff_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1319 int32_t lsm303ah_xl_ff_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1320 1321 int32_t lsm303ah_xl_fifo_xl_module_batch_set(const stmdev_ctx_t *ctx, 1322 uint8_t val); 1323 int32_t lsm303ah_xl_fifo_xl_module_batch_get(const stmdev_ctx_t *ctx, 1324 uint8_t *val); 1325 1326 typedef enum 1327 { 1328 LSM303AH_XL_BYPASS_MODE = 0, 1329 LSM303AH_XL_FIFO_MODE = 1, 1330 LSM303AH_XL_STREAM_TO_FIFO_MODE = 3, 1331 LSM303AH_XL_BYPASS_TO_STREAM_MODE = 4, 1332 LSM303AH_XL_STREAM_MODE = 6, 1333 } lsm303ah_xl_fmode_t; 1334 int32_t lsm303ah_xl_fifo_mode_set(const stmdev_ctx_t *ctx, 1335 lsm303ah_xl_fmode_t val); 1336 int32_t lsm303ah_xl_fifo_mode_get(const stmdev_ctx_t *ctx, 1337 lsm303ah_xl_fmode_t *val); 1338 1339 int32_t lsm303ah_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, 1340 uint8_t val); 1341 int32_t lsm303ah_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, 1342 uint8_t *val); 1343 1344 int32_t lsm303ah_xl_fifo_full_flag_get(const stmdev_ctx_t *ctx, 1345 uint8_t *val); 1346 1347 int32_t lsm303ah_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, 1348 uint8_t *val); 1349 1350 int32_t lsm303ah_xl_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, 1351 uint8_t *val); 1352 1353 int32_t lsm303ah_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, 1354 uint16_t *val); 1355 1356 int32_t lsm303ah_xl_fifo_src_get(const stmdev_ctx_t *ctx, 1357 lsm303ah_fifo_src_a_t *val); 1358 1359 int32_t lsm303ah_xl_pedo_threshold_set(const stmdev_ctx_t *ctx, 1360 uint8_t val); 1361 int32_t lsm303ah_xl_pedo_threshold_get(const stmdev_ctx_t *ctx, 1362 uint8_t *val); 1363 1364 typedef enum 1365 { 1366 LSM303AH_XL_PEDO_AT_2g = 0, 1367 LSM303AH_XL_PEDO_AT_4g = 1, 1368 } lsm303ah_xl_pedo4g_t; 1369 int32_t lsm303ah_xl_pedo_full_scale_set(const stmdev_ctx_t *ctx, 1370 lsm303ah_xl_pedo4g_t val); 1371 int32_t lsm303ah_xl_pedo_full_scale_get(const stmdev_ctx_t *ctx, 1372 lsm303ah_xl_pedo4g_t *val); 1373 1374 int32_t lsm303ah_xl_pedo_step_reset_set(const stmdev_ctx_t *ctx, 1375 uint8_t val); 1376 int32_t lsm303ah_xl_pedo_step_reset_get(const stmdev_ctx_t *ctx, 1377 uint8_t *val); 1378 1379 int32_t lsm303ah_xl_pedo_step_detect_flag_get(const stmdev_ctx_t *ctx, 1380 uint8_t *val); 1381 1382 int32_t lsm303ah_xl_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 1383 int32_t lsm303ah_xl_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 1384 1385 int32_t lsm303ah_xl_pedo_debounce_steps_set(const stmdev_ctx_t *ctx, 1386 uint8_t val); 1387 int32_t lsm303ah_xl_pedo_debounce_steps_get(const stmdev_ctx_t *ctx, 1388 uint8_t *val); 1389 1390 int32_t lsm303ah_xl_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 1391 int32_t lsm303ah_xl_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); 1392 1393 int32_t lsm303ah_xl_pedo_steps_period_set(const stmdev_ctx_t *ctx, 1394 uint8_t *buff); 1395 int32_t lsm303ah_xl_pedo_steps_period_get(const stmdev_ctx_t *ctx, 1396 uint8_t *buff); 1397 int32_t lsm303ah_xl_motion_data_ready_flag_get(const stmdev_ctx_t *ctx, 1398 uint8_t *val); 1399 1400 int32_t lsm303ah_xl_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 1401 int32_t lsm303ah_xl_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 1402 1403 int32_t lsm303ah_xl_motion_threshold_set(const stmdev_ctx_t *ctx, 1404 uint8_t val); 1405 int32_t lsm303ah_xl_motion_threshold_get(const stmdev_ctx_t *ctx, 1406 uint8_t *val); 1407 1408 int32_t lsm303ah_xl_tilt_data_ready_flag_get(const stmdev_ctx_t *ctx, 1409 uint8_t *val); 1410 1411 int32_t lsm303ah_xl_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 1412 int32_t lsm303ah_xl_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 1413 1414 int32_t lsm303ah_xl_module_sens_set(const stmdev_ctx_t *ctx, uint8_t val); 1415 int32_t lsm303ah_xl_module_sens_get(const stmdev_ctx_t *ctx, uint8_t *val); 1416 1417 /** 1418 * @} 1419 * 1420 */ 1421 1422 #ifdef __cplusplus 1423 } 1424 #endif 1425 1426 #endif /*LSM303AH_REGS_H */ 1427 1428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1429
