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32 
33 #ifndef __HW_LRFDTXF_H__
34 #define __HW_LRFDTXF_H__
35 
36 //*****************************************************************************
37 //
38 // This section defines the register offsets of
39 // LRFDTXF component
40 //
41 //*****************************************************************************
42 // Data to from TXFIFO
43 #define LRFDTXF_O_TXD                                               0x00000000U
44 
45 //*****************************************************************************
46 //
47 // Register: LRFDTXF_O_TXD
48 //
49 //*****************************************************************************
50 // Field:  [31:0] DATA
51 //
52 // TX FIFO data. When written the register data is pushed to the TX FIFO. When
53 // read, data is popped from the TX FIFO. When writing or reading this register
54 // the access size will determine how many bytes are pushed to or popped from
55 // the FIFO. It is possible to push or pop 1,2 or 4 bytes depending on the
56 // access being done.
57 #define LRFDTXF_TXD_DATA_W                                                  32U
58 #define LRFDTXF_TXD_DATA_M                                          0xFFFFFFFFU
59 #define LRFDTXF_TXD_DATA_S                                                   0U
60 
61 
62 #endif // __LRFDTXF__
63