1 /****************************************************************************** 2 * Filename: hw_lrfdtrc_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LRFDTRC_H__ 34 #define __HW_LRFDTRC_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LRFDTRC component 40 // 41 //***************************************************************************** 42 // Tracer Configuration 43 #define LRFDTRC_O_CFG 0x00000000U 44 45 // Channel 1 Command Register 46 #define LRFDTRC_O_CH1CMD 0x00000004U 47 48 // Channel 2 Command Register 49 #define LRFDTRC_O_CH2CMD 0x00000008U 50 51 // Channel 3 Command Register 52 #define LRFDTRC_O_CH3CMD 0x0000000CU 53 54 // Channel 1 Parameter 0/1 Register 55 #define LRFDTRC_O_CH1PAR01 0x00000014U 56 57 // Channel 2 Parameter 0/1 Register 58 #define LRFDTRC_O_CH2PAR01 0x00000018U 59 60 // Channel 3 Parameter 0/1 Register 61 #define LRFDTRC_O_CH3PAR01 0x0000001CU 62 63 // Channel 1 Parameter 2/3 Register 64 #define LRFDTRC_O_CH1PAR23 0x00000024U 65 66 // Channel 2 Parameter 2/3 Register 67 #define LRFDTRC_O_CH2PAR23 0x00000028U 68 69 // Channel 3 Parameter 2/3 Register 70 #define LRFDTRC_O_CH3PAR23 0x0000002CU 71 72 //***************************************************************************** 73 // 74 // Register: LRFDTRC_O_CFG 75 // 76 //***************************************************************************** 77 // Field: [8:7] PRESCAL 78 // 79 // Data rate prescaler for bit clock of the serialized data 80 // ENUMs: 81 // DIV4 Divide clock by 4 82 // DIV3 Divide clock by 3 83 // DIV2 Divide clock by 2 84 // DIV1 Divide clock by 1 85 #define LRFDTRC_CFG_PRESCAL_W 2U 86 #define LRFDTRC_CFG_PRESCAL_M 0x00000180U 87 #define LRFDTRC_CFG_PRESCAL_S 7U 88 #define LRFDTRC_CFG_PRESCAL_DIV4 0x00000180U 89 #define LRFDTRC_CFG_PRESCAL_DIV3 0x00000100U 90 #define LRFDTRC_CFG_PRESCAL_DIV2 0x00000080U 91 #define LRFDTRC_CFG_PRESCAL_DIV1 0x00000000U 92 93 // Field: [6] TSCLR 94 // 95 // Writing 1 to this bit clears the TX timer 96 // ENUMs: 97 // ONE The bit is 1 98 // ZERO The bit is 0 99 #define LRFDTRC_CFG_TSCLR 0x00000040U 100 #define LRFDTRC_CFG_TSCLR_M 0x00000040U 101 #define LRFDTRC_CFG_TSCLR_S 6U 102 #define LRFDTRC_CFG_TSCLR_ONE 0x00000040U 103 #define LRFDTRC_CFG_TSCLR_ZERO 0x00000000U 104 105 // Field: [5] TSEN 106 // 107 // Enables the Timestamp 108 // ENUMs: 109 // ON The bit is 1 110 // OFF The bit is 0 111 #define LRFDTRC_CFG_TSEN 0x00000020U 112 #define LRFDTRC_CFG_TSEN_M 0x00000020U 113 #define LRFDTRC_CFG_TSEN_S 5U 114 #define LRFDTRC_CFG_TSEN_ON 0x00000020U 115 #define LRFDTRC_CFG_TSEN_OFF 0x00000000U 116 117 // Field: [4:3] CH3EN 118 // 119 // Enables CH3 traces 120 // ENUMs: 121 // TOPSM Enabled with MCE, MCO and CCE backdoor access 122 // access 123 // NORM Enabled in normal mode. Data from bus slave 124 // interface. 125 // OFF Disabled. No tracer transfer due to CH3 events 126 #define LRFDTRC_CFG_CH3EN_W 2U 127 #define LRFDTRC_CFG_CH3EN_M 0x00000018U 128 #define LRFDTRC_CFG_CH3EN_S 3U 129 #define LRFDTRC_CFG_CH3EN_TOPSM 0x00000010U 130 #define LRFDTRC_CFG_CH3EN_NORM 0x00000008U 131 #define LRFDTRC_CFG_CH3EN_OFF 0x00000000U 132 133 // Field: [2:1] CH2EN 134 // 135 // Enables CH2 traces 136 // ENUMs: 137 // TOPSM Enabled with PBE and RFE backdoor access access 138 // NORM Enabled in normal mode. Data from bus slave 139 // interface. 140 // OFF Disabled. No tracer transfer due to CH2 events 141 #define LRFDTRC_CFG_CH2EN_W 2U 142 #define LRFDTRC_CFG_CH2EN_M 0x00000006U 143 #define LRFDTRC_CFG_CH2EN_S 1U 144 #define LRFDTRC_CFG_CH2EN_TOPSM 0x00000004U 145 #define LRFDTRC_CFG_CH2EN_NORM 0x00000002U 146 #define LRFDTRC_CFG_CH2EN_OFF 0x00000000U 147 148 // Field: [0] CH1EN 149 // 150 // Enables CH1 traces 151 // ENUMs: 152 // NORM Enabled in normal mode. Data from bus slave 153 // interface. 154 // OFF Disabled. No tracer transfer due to CH1 events 155 #define LRFDTRC_CFG_CH1EN 0x00000001U 156 #define LRFDTRC_CFG_CH1EN_M 0x00000001U 157 #define LRFDTRC_CFG_CH1EN_S 0U 158 #define LRFDTRC_CFG_CH1EN_NORM 0x00000001U 159 #define LRFDTRC_CFG_CH1EN_OFF 0x00000000U 160 161 //***************************************************************************** 162 // 163 // Register: LRFDTRC_O_CH1CMD 164 // 165 //***************************************************************************** 166 // Field: [15:8] PKTHDR 167 // 168 // Header Byte. Reverts back to 0 when ready to transmit. A Write starts a 169 // transmission sequence. 170 // ENUMs: 171 // ALLONES All the bits are 1 172 // ALLZEROS All the bits are 0 173 #define LRFDTRC_CH1CMD_PKTHDR_W 8U 174 #define LRFDTRC_CH1CMD_PKTHDR_M 0x0000FF00U 175 #define LRFDTRC_CH1CMD_PKTHDR_S 8U 176 #define LRFDTRC_CH1CMD_PKTHDR_ALLONES 0x0000FF00U 177 #define LRFDTRC_CH1CMD_PKTHDR_ALLZEROS 0x00000000U 178 179 // Field: [2:0] PARCNT 180 // 181 // Number of parameters to transmit. Reverts back to 0 when ready to transmit. 182 // A Write starts a transmission sequence. 183 // ENUMs: 184 // ALLONES All the bits are 1 185 // ALLZEROS All the bits are 0 186 #define LRFDTRC_CH1CMD_PARCNT_W 3U 187 #define LRFDTRC_CH1CMD_PARCNT_M 0x00000007U 188 #define LRFDTRC_CH1CMD_PARCNT_S 0U 189 #define LRFDTRC_CH1CMD_PARCNT_ALLONES 0x00000007U 190 #define LRFDTRC_CH1CMD_PARCNT_ALLZEROS 0x00000000U 191 192 //***************************************************************************** 193 // 194 // Register: LRFDTRC_O_CH2CMD 195 // 196 //***************************************************************************** 197 // Field: [15:8] PKTHDR 198 // 199 // Header Byte. Reverts back to 0 when ready to transmit. A Write starts a 200 // transmission sequence. 201 // ENUMs: 202 // ALLONES All the bits are 1 203 // ALLZEROS All the bits are 0 204 #define LRFDTRC_CH2CMD_PKTHDR_W 8U 205 #define LRFDTRC_CH2CMD_PKTHDR_M 0x0000FF00U 206 #define LRFDTRC_CH2CMD_PKTHDR_S 8U 207 #define LRFDTRC_CH2CMD_PKTHDR_ALLONES 0x0000FF00U 208 #define LRFDTRC_CH2CMD_PKTHDR_ALLZEROS 0x00000000U 209 210 // Field: [2:0] PARCNT 211 // 212 // Number of parameters to transmit. Reverts back to 0 when ready to transmit. 213 // A Write starts a transmission sequence. 214 // ENUMs: 215 // ALLONES All the bits are 1 216 // ALLZEROS All the bits are 0 217 #define LRFDTRC_CH2CMD_PARCNT_W 3U 218 #define LRFDTRC_CH2CMD_PARCNT_M 0x00000007U 219 #define LRFDTRC_CH2CMD_PARCNT_S 0U 220 #define LRFDTRC_CH2CMD_PARCNT_ALLONES 0x00000007U 221 #define LRFDTRC_CH2CMD_PARCNT_ALLZEROS 0x00000000U 222 223 //***************************************************************************** 224 // 225 // Register: LRFDTRC_O_CH3CMD 226 // 227 //***************************************************************************** 228 // Field: [15:8] PKTHDR 229 // 230 // Header Byte. Reverts back to 0 when ready to transmit. A Write starts a 231 // transmission sequence. 232 // ENUMs: 233 // ALLONES All the bits are 1 234 // ALLZEROS All the bits are 0 235 #define LRFDTRC_CH3CMD_PKTHDR_W 8U 236 #define LRFDTRC_CH3CMD_PKTHDR_M 0x0000FF00U 237 #define LRFDTRC_CH3CMD_PKTHDR_S 8U 238 #define LRFDTRC_CH3CMD_PKTHDR_ALLONES 0x0000FF00U 239 #define LRFDTRC_CH3CMD_PKTHDR_ALLZEROS 0x00000000U 240 241 // Field: [2:0] PARCNT 242 // 243 // Number of parameters to transmit. Reverts back to 0 when ready to transmit. 244 // A Write starts a transmission sequence. 245 // ENUMs: 246 // ALLONES All the bits are 1 247 // ALLZEROS All the bits are 0 248 #define LRFDTRC_CH3CMD_PARCNT_W 3U 249 #define LRFDTRC_CH3CMD_PARCNT_M 0x00000007U 250 #define LRFDTRC_CH3CMD_PARCNT_S 0U 251 #define LRFDTRC_CH3CMD_PARCNT_ALLONES 0x00000007U 252 #define LRFDTRC_CH3CMD_PARCNT_ALLZEROS 0x00000000U 253 254 //***************************************************************************** 255 // 256 // Register: LRFDTRC_O_CH1PAR01 257 // 258 //***************************************************************************** 259 // Field: [31:16] PAR1 260 // 261 // Parameter 1 for Channel 1 262 // ENUMs: 263 // ALLONES All the bits are 1 264 // ALLZEROS All the bits are 0 265 #define LRFDTRC_CH1PAR01_PAR1_W 16U 266 #define LRFDTRC_CH1PAR01_PAR1_M 0xFFFF0000U 267 #define LRFDTRC_CH1PAR01_PAR1_S 16U 268 #define LRFDTRC_CH1PAR01_PAR1_ALLONES 0xFFFF0000U 269 #define LRFDTRC_CH1PAR01_PAR1_ALLZEROS 0x00000000U 270 271 // Field: [15:0] PAR0 272 // 273 // Parameter 0 for Channel 1 274 // ENUMs: 275 // ALLONES All the bits are 1 276 // ALLZEROS All the bits are 0 277 #define LRFDTRC_CH1PAR01_PAR0_W 16U 278 #define LRFDTRC_CH1PAR01_PAR0_M 0x0000FFFFU 279 #define LRFDTRC_CH1PAR01_PAR0_S 0U 280 #define LRFDTRC_CH1PAR01_PAR0_ALLONES 0x0000FFFFU 281 #define LRFDTRC_CH1PAR01_PAR0_ALLZEROS 0x00000000U 282 283 //***************************************************************************** 284 // 285 // Register: LRFDTRC_O_CH2PAR01 286 // 287 //***************************************************************************** 288 // Field: [31:16] PAR1 289 // 290 // Parameter 1 for Channel 2 291 // ENUMs: 292 // ALLONES All the bits are 1 293 // ALLZEROS All the bits are 0 294 #define LRFDTRC_CH2PAR01_PAR1_W 16U 295 #define LRFDTRC_CH2PAR01_PAR1_M 0xFFFF0000U 296 #define LRFDTRC_CH2PAR01_PAR1_S 16U 297 #define LRFDTRC_CH2PAR01_PAR1_ALLONES 0xFFFF0000U 298 #define LRFDTRC_CH2PAR01_PAR1_ALLZEROS 0x00000000U 299 300 // Field: [15:0] PAR0 301 // 302 // Parameter 0 for Channel 2 303 // ENUMs: 304 // ALLONES All the bits are 1 305 // ALLZEROS All the bits are 0 306 #define LRFDTRC_CH2PAR01_PAR0_W 16U 307 #define LRFDTRC_CH2PAR01_PAR0_M 0x0000FFFFU 308 #define LRFDTRC_CH2PAR01_PAR0_S 0U 309 #define LRFDTRC_CH2PAR01_PAR0_ALLONES 0x0000FFFFU 310 #define LRFDTRC_CH2PAR01_PAR0_ALLZEROS 0x00000000U 311 312 //***************************************************************************** 313 // 314 // Register: LRFDTRC_O_CH3PAR01 315 // 316 //***************************************************************************** 317 // Field: [31:16] PAR1 318 // 319 // Parameter 1 for Channel 3 320 // ENUMs: 321 // ALLONES All the bits are 1 322 // ALLZEROS All the bits are 0 323 #define LRFDTRC_CH3PAR01_PAR1_W 16U 324 #define LRFDTRC_CH3PAR01_PAR1_M 0xFFFF0000U 325 #define LRFDTRC_CH3PAR01_PAR1_S 16U 326 #define LRFDTRC_CH3PAR01_PAR1_ALLONES 0xFFFF0000U 327 #define LRFDTRC_CH3PAR01_PAR1_ALLZEROS 0x00000000U 328 329 // Field: [15:0] PAR0 330 // 331 // Parameter 0 for Channel 3 332 // ENUMs: 333 // ALLONES All the bits are 1 334 // ALLZEROS All the bits are 0 335 #define LRFDTRC_CH3PAR01_PAR0_W 16U 336 #define LRFDTRC_CH3PAR01_PAR0_M 0x0000FFFFU 337 #define LRFDTRC_CH3PAR01_PAR0_S 0U 338 #define LRFDTRC_CH3PAR01_PAR0_ALLONES 0x0000FFFFU 339 #define LRFDTRC_CH3PAR01_PAR0_ALLZEROS 0x00000000U 340 341 //***************************************************************************** 342 // 343 // Register: LRFDTRC_O_CH1PAR23 344 // 345 //***************************************************************************** 346 // Field: [31:16] PAR3 347 // 348 // Parameter 3 for Channel 1 349 // ENUMs: 350 // ALLONES All the bits are 1 351 // ALLZEROS All the bits are 0 352 #define LRFDTRC_CH1PAR23_PAR3_W 16U 353 #define LRFDTRC_CH1PAR23_PAR3_M 0xFFFF0000U 354 #define LRFDTRC_CH1PAR23_PAR3_S 16U 355 #define LRFDTRC_CH1PAR23_PAR3_ALLONES 0xFFFF0000U 356 #define LRFDTRC_CH1PAR23_PAR3_ALLZEROS 0x00000000U 357 358 // Field: [15:0] PAR2 359 // 360 // Parameter 2 for Channel 1 361 // ENUMs: 362 // ALLONES All the bits are 1 363 // ALLZEROS All the bits are 0 364 #define LRFDTRC_CH1PAR23_PAR2_W 16U 365 #define LRFDTRC_CH1PAR23_PAR2_M 0x0000FFFFU 366 #define LRFDTRC_CH1PAR23_PAR2_S 0U 367 #define LRFDTRC_CH1PAR23_PAR2_ALLONES 0x0000FFFFU 368 #define LRFDTRC_CH1PAR23_PAR2_ALLZEROS 0x00000000U 369 370 //***************************************************************************** 371 // 372 // Register: LRFDTRC_O_CH2PAR23 373 // 374 //***************************************************************************** 375 // Field: [31:16] PAR3 376 // 377 // Parameter 3 for Channel 2 378 // ENUMs: 379 // ALLONES All the bits are 1 380 // ALLZEROS All the bits are 0 381 #define LRFDTRC_CH2PAR23_PAR3_W 16U 382 #define LRFDTRC_CH2PAR23_PAR3_M 0xFFFF0000U 383 #define LRFDTRC_CH2PAR23_PAR3_S 16U 384 #define LRFDTRC_CH2PAR23_PAR3_ALLONES 0xFFFF0000U 385 #define LRFDTRC_CH2PAR23_PAR3_ALLZEROS 0x00000000U 386 387 // Field: [15:0] PAR2 388 // 389 // Parameter 2 for Channel 2 390 // ENUMs: 391 // ALLONES All the bits are 1 392 // ALLZEROS All the bits are 0 393 #define LRFDTRC_CH2PAR23_PAR2_W 16U 394 #define LRFDTRC_CH2PAR23_PAR2_M 0x0000FFFFU 395 #define LRFDTRC_CH2PAR23_PAR2_S 0U 396 #define LRFDTRC_CH2PAR23_PAR2_ALLONES 0x0000FFFFU 397 #define LRFDTRC_CH2PAR23_PAR2_ALLZEROS 0x00000000U 398 399 //***************************************************************************** 400 // 401 // Register: LRFDTRC_O_CH3PAR23 402 // 403 //***************************************************************************** 404 // Field: [31:16] PAR3 405 // 406 // Parameter 3 for Channel 3 407 // ENUMs: 408 // ALLONES All the bits are 1 409 // ALLZEROS All the bits are 0 410 #define LRFDTRC_CH3PAR23_PAR3_W 16U 411 #define LRFDTRC_CH3PAR23_PAR3_M 0xFFFF0000U 412 #define LRFDTRC_CH3PAR23_PAR3_S 16U 413 #define LRFDTRC_CH3PAR23_PAR3_ALLONES 0xFFFF0000U 414 #define LRFDTRC_CH3PAR23_PAR3_ALLZEROS 0x00000000U 415 416 // Field: [15:0] PAR2 417 // 418 // Parameter 2 for Channel 3 419 // ENUMs: 420 // ALLONES All the bits are 1 421 // ALLZEROS All the bits are 0 422 #define LRFDTRC_CH3PAR23_PAR2_W 16U 423 #define LRFDTRC_CH3PAR23_PAR2_M 0x0000FFFFU 424 #define LRFDTRC_CH3PAR23_PAR2_S 0U 425 #define LRFDTRC_CH3PAR23_PAR2_ALLONES 0x0000FFFFU 426 #define LRFDTRC_CH3PAR23_PAR2_ALLZEROS 0x00000000U 427 428 429 #endif // __LRFDTRC__ 430
