1 /**************************************************************************//** 2 * @file Lpuart_reg.h 3 * @version V1.00 4 * @brief LPUART register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __LPUART_REG_H__ 10 #define __LPUART_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /*---------------------- Low Power Universal Asynchronous Receiver/Transmitter Controller(LPUART) -------------------------*/ 22 /** 23 @addtogroup LPUART Low Power Universal Asynchronous Receiver/Transmitter Controller(LPUART) 24 Memory Mapped Structure for LPUART Controller 25 @{ */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var LPUART_T::DAT 33 * Offset: 0x00 LPUART Receive/Transmit Buffer Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[7:0] |DAT |Data Receive/Transmit Buffer 38 * | | |Write Operation: 39 * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO 40 * | | |The LPUART controller will send out the data stored in transmitter FIFO top location through the LPUART_TXD. 41 * | | |Read Operation: 42 * | | |By reading this register, the LPUART controller will return an 8-bit data received from receiver FIFO. 43 * |[8] |PARITY |PARITY Bit Receive/Transmit Buffer 44 * | | |Write Operation: 45 * | | |By writing to this bit, the PARITY bit will be stored in transmitter FIFO 46 * | | |If PBE (LPUART_LINE[3]) and PSS (LPUART_LINE[7]) are set, the LPUART controller will send out this bit follow the DAT (LPUART_DAT[7:0]) through the LPUART_TXD. 47 * | | |Read Operation: 48 * | | |If PBE (LPUART_LINE[3]) and PSS (LPUART_LINE[7]) are enabled, the PARITY bit can be read by this bit. 49 * | | |Note: This bit has effect only when PBE (LPUART_LINE[3]) and PSS (LPUART_LINE[7]) are set. 50 * @var LPUART_T::INTEN 51 * Offset: 0x04 LPUART Interrupt Enable Register 52 * --------------------------------------------------------------------------------------------------- 53 * |Bits |Field |Descriptions 54 * | :----: | :----: | :---- | 55 * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit 56 * | | |0 = Receive data available interrupt Disabled. 57 * | | |1 = Receive data available interrupt Enabled. 58 * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit 59 * | | |0 = Transmit holding register empty interrupt Disabled. 60 * | | |1 = Transmit holding register empty interrupt Enabled. 61 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit 62 * | | |0 = Receive Line Status interrupt Disabled. 63 * | | |1 = Receive Line Status interrupt Enabled. 64 * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit 65 * | | |0 = Modem status interrupt Disabled. 66 * | | |1 = Modem status interrupt Enabled. 67 * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit 68 * | | |0 = RX time-out interrupt Disabled. 69 * | | |1 = RX time-out interrupt Enabled. 70 * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit 71 * | | |0 = Buffer error interrupt Disabled. 72 * | | |1 = Buffer error interrupt Enabled. 73 * |[6] |WKIEN |Wake-up Interrupt Enable Bit 74 * | | |0 = Wake-up Interrupt Disabled. 75 * | | |1 = Wake-up Interrupt Enabled. 76 * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit 77 * | | |0 = Receive Buffer Time-out counter Disabled. 78 * | | |1 = Receive Buffer Time-out counter Enabled. 79 * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit 80 * | | |0 = nRTS auto-flow control Disabled. 81 * | | |1 = nRTS auto-flow control Enabled. 82 * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (LPUART_FIFO[19:16]), the LPUART will de-assert nRTS signal. 83 * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit 84 * | | |0 = nCTS auto-flow control Disabled. 85 * | | |1 = nCTS auto-flow control Enabled. 86 * | | |Note: When nCTS auto-flow is enabled, the LPUART will send data to external device if nCTS input assert (LPUART will not send data to device until nCTS is asserted). 87 * |[14] |TXPDMAEN |TX LPPDMA Enable Bit 88 * | | |0 = TX LPPDMA Disabled. 89 * | | |1 = TX LPPDMA Enabled. 90 * | | |Note: If RLSIEN (LPUART_INTEN[2]) is enabled and HWRLSINT (LPUART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused 91 * | | |If RLS interrupt is caused by Break Error Flag BIF(LPUART_FIFOSTS[6]), Frame Error Flag FEF(LPUART_FIFO[5]) or Parity Error Flag PEF(LPUART_FIFOSTS[4]), LPUART LPPDMA transmit request operation is stopped 92 * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make LPUART LPPDMA transmit request operation continue. 93 * |[15] |RXPDMAEN |RX LPPDMA Enable Bit 94 * | | |This bit can enable or disable RX LPPDMA service. 95 * | | |0 = RX LPPDMA Disabled. 96 * | | |1 = RX LPPDMA Enabled. 97 * | | |Note: If RLSIEN (LPUART_INTEN[2]) is enabled and HWRLSINT (LPUART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused 98 * | | |If RLS interrupt is caused by Break Error Flag BIF(LPUART_FIFOSTS[6]), Frame Error Flag FEF(LPUART_FIFO[5]) or Parity Error Flag PEF(LPUART_FIFOSTS[4]), LPUART LPPDMA receive request operation is stopped 99 * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing '1' to corresponding BIF, FEF and PEF to make LPUART LPPDMA receive request operation continue. 100 * |[16] |SWBEIEN |Single-wire Bit Error Detection Interrupt Enable Bit 101 * | | |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(LPUART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(LPUART_INTSTS[16]) is set. 102 * | | |0 = Single-wire Bit Error Detect Interrupt Disabled. 103 * | | |1 = Single-wire Bit Error Detect Interrupt Enabled. 104 * | | |Note: This bit is valid when FUNCSEL (LPUART_FUNCSEL[2:0]) is select LPUART Single-wire mode. 105 * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit 106 * | | |0 = Auto-baud rate interrupt Disabled. 107 * | | |1 = Auto-baud rate interrupt Enabled. 108 * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit 109 * | | |If TXENDIEN (LPUART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (LPUART_INTSTS[30]) will be generated when TXENDIF (LPUART_INTSTS[22]) is set (TX FIFO (LPUART_DAT) is empty and the STOP bit of the last byte has been transmitted). 110 * | | |0 = Transmitter empty interrupt Disabled. 111 * | | |1 = Transmitter empty interrupt Enabled. 112 * @var LPUART_T::FIFO 113 * Offset: 0x08 LPUART FIFO Control Register 114 * --------------------------------------------------------------------------------------------------- 115 * |Bits |Field |Descriptions 116 * | :----: | :----: | :---- | 117 * |[1] |RXRST |RX Field Software Reset 118 * | | |When RXRST (LPUART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. 119 * | | |0 = No effect. 120 * | | |1 = Reset the RX internal state machine and pointers. 121 * | | |Note 1: This bit will automatically clear at least 3 LPUART peripheral clock cycles. 122 * | | |Note 2: Before setting this bit, it should wait for the RXIDLE (LPUART_FIFOSTS[29]) be set. 123 * |[2] |TXRST |TX Field Software Reset 124 * | | |When TXRST (LPUART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. 125 * | | |0 = No effect. 126 * | | |1 = Reset the TX internal state machine and pointers. 127 * | | |Note 1: This bit will automatically clear at least 3 LPUART peripheral clock cycles. 128 * | | |Note 2: Before setting this bit, it should wait for the TXEMPTYF (LPUART_FIFOSTS[28]) be set. 129 * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level 130 * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (LPUART_INTSTS[0]) will be set (if RDAIEN (LPUART_INTEN[0]) enabled, and an interrupt will be generated). 131 * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. 132 * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. 133 * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. 134 * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. 135 * | | |Others = Reserved. 136 * |[8] |RXOFF |Receiver Disable Bit 137 * | | |The receiver is disabled or not (set 1 to disable receiver). 138 * | | |0 = Receiver Enabled. 139 * | | |1 = Receiver Disabled. 140 * | | |Note: This bit is used for RS-485 Normal Multi-drop mode 141 * | | |It should be programmed before RS485NMM (LPUART_ALTCTL[8]) is programmed. 142 * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control 143 * | | |0000 = nRTS Trigger Level is 1 byte. 144 * | | |0001 = nRTS Trigger Level is 4 bytes. 145 * | | |0010 = nRTS Trigger Level is 8 bytes. 146 * | | |0011 = nRTS Trigger Level is 14 bytes. 147 * | | |Others = Reserved. 148 * | | |Note: This field is used for auto nRTS flow control. 149 * @var LPUART_T::LINE 150 * Offset: 0x0C LPUART Line Control Register 151 * --------------------------------------------------------------------------------------------------- 152 * |Bits |Field |Descriptions 153 * | :----: | :----: | :---- | 154 * |[1:0] |WLS |Word Length Selection 155 * | | |This field sets LPUART word length. 156 * | | |00 = 5 bits. 157 * | | |01 = 6 bits. 158 * | | |10 = 7 bits. 159 * | | |11 = 8 bits. 160 * |[2] |NSB |Number of 'STOP Bit' 161 * | | |0 = One 'STOP bit' is generated in the transmitted data. 162 * | | |1 = When select 5-bit word length, 1.5 'STOP bit' is generated in the transmitted data 163 * | | |When select 6-, 7- and 8-bit word length, 2 'STOP bit' is generated in the transmitted data. 164 * |[3] |PBE |PARITY Bit Enable Bit 165 * | | |0 = PARITY bit generated Disabled. 166 * | | |1 = PARITY bit generated Enabled. 167 * | | |Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. 168 * |[4] |EPE |Even Parity Enable Bit 169 * | | |0 = Odd number of logic 1's is transmitted and checked in each word. 170 * | | |1 = Even number of logic 1's is transmitted and checked in each word. 171 * | | |Note: This bit has effect only when PBE (LPUART_LINE[3]) is set. 172 * |[5] |SPE |Stick Parity Enable Bit 173 * | | |0 = Stick parity Disabled. 174 * | | |1 = Stick parity Enabled. 175 * | | |Note: If PBE (LPUART_LINE[3]) and EPE (LPUART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0 176 * | | |If PBE (LPUART_LINE[3]) is 1 and EPE (LPUART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. 177 * |[6] |BCB |Break Control Bit 178 * | | |0 = Break Control Disabled. 179 * | | |1 = Break Control Enabled. 180 * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) 181 * | | |This bit acts only on TX line and has no effect on the transmitter logic. 182 * |[7] |PSS |PARITY Bit Source Selection 183 * | | |The PARITY bit can be selected to be generated and checked automatically or by software. 184 * | | |0 = PARITY bit is generated by EPE (LPUART_LINE[4]) and SPE (LPUART_LINE[5]) setting and checked automatically. 185 * | | |1 = PARITY bit generated and checked by software. 186 * | | |Note 1: This bit has effect only when PBE (LPUART_LINE[3]) is set. 187 * | | |Note 2: If PSS is 0, the PARITY bit is transmitted and checked automatically 188 * | | |If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (LPUART_DAT[8]) and the PARITY bit can be read by reading PARITY (LPUART_DAT[8]). 189 * |[8] |TXDINV |TX Data Inverted 190 * | | |0 = Transmitted data signal inverted Disabled. 191 * | | |1 = Transmitted data signal inverted Enabled. 192 * | | |Note 1: Before setting this bit, TXRXDIS (LPUART_FUNCSEL[3]) should be set then waited for TXRXACT (LPUART_FIFOSTS[31]) is cleared 193 * | | |When the configuration is done, cleared TXRXDIS (LPUART_FUNCSEL[3]) to activate LPUART controller. 194 * | | |Note 2: This bit is valid when FUNCSEL (LPUART_FUNCSEL[2:0]) is select LPUART or RS485 function. 195 * |[9] |RXDINV |RX Data Inverted 196 * | | |0 = Received data signal inverted Disabled. 197 * | | |1 = Received data signal inverted Enabled. 198 * | | |Note 1: Before setting this bit, TXRXDIS (LPUART_FUNCSEL[3]) should be set then waited for TXRXACT (LPUART_FIFOSTS[31]) is cleared 199 * | | |When the configuration is done, cleared TXRXDIS (LPUART_FUNCSEL[3]) to activate LPUART controller. 200 * | | |Note 2: This bit is valid when FUNCSEL (LPUART_FUNCSEL[2:0]) is select LPUART or RS485 function. 201 * @var LPUART_T::MODEM 202 * Offset: 0x10 LPUART Modem Control Register 203 * --------------------------------------------------------------------------------------------------- 204 * |Bits |Field |Descriptions 205 * | :----: | :----: | :---- | 206 * |[1] |RTS |nRTS Signal Control 207 * | | |This bit is direct control internal nRTS (Request-to-send) signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. 208 * | | |0 = nRTS signal is active. 209 * | | |1 = nRTS signal is inactive. 210 * | | |Note 1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in LPUART function mode. 211 * | | |Note 2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. 212 * | | |Note 3: Single-wire mode is support this feature. 213 * |[9] |RTSACTLV |nRTS Pin Active Level 214 * | | |This bit defines the active level state of nRTS pin output. 215 * | | |0 = nRTS pin output is high level active. 216 * | | |1 = nRTS pin output is low level active. (Default) 217 * | | |Note 1: Refer to Figure 6.28-13 and Figure 6.28-14 for LPUART function mode. 218 * | | |Note 2: Refer to Figure 6.28-24 and Figure 6.28-25 for RS-485 function mode. 219 * | | |Note 3: Before setting this bit, TXRXDIS (LPUART_FUNCSEL[3]) should be set then waited for TXRXACT (LPUART_FIFOSTS[31]) is cleared 220 * | | |When the configuration is done, cleared TXRXDIS (LPUART_FUNCSEL[3]) to activate LPUART controller. 221 * |[13] |RTSSTS |nRTS Pin Status (Read Only) 222 * | | |This bit mirror from nRTS pin output of voltage logic status. 223 * | | |0 = nRTS pin output is low level voltage logic state. 224 * | | |1 = nRTS pin output is high level voltage logic state. 225 * @var LPUART_T::MODEMSTS 226 * Offset: 0x14 LPUART Modem Status Register 227 * --------------------------------------------------------------------------------------------------- 228 * |Bits |Field |Descriptions 229 * | :----: | :----: | :---- | 230 * |[0] |CTSDETF |Detect nCTS State Change Flag 231 * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (LPUART_INTEN[3]) is set to 1. 232 * | | |0 = nCTS input has not change state. 233 * | | |1 = nCTS input has change state. 234 * | | |Note: This bit can be cleared by writing '1' to it. 235 * |[4] |CTSSTS |nCTS Pin Status (Read Only) 236 * | | |This bit mirror from nCTS pin input of voltage logic status. 237 * | | |0 = nCTS pin input is low level voltage logic state. 238 * | | |1 = nCTS pin input is high level voltage logic state. 239 * | | |Note: This bit echoes when LPUART controller peripheral clock is enabled, and nCTS multi-function port is selected. 240 * |[8] |CTSACTLV |nCTS Pin Active Level 241 * | | |This bit defines the active level state of nCTS pin input. 242 * | | |0 = nCTS pin input is high level active. 243 * | | |1 = nCTS pin input is low level active. (Default) 244 * | | |Note: Before setting this bit, TXRXDIS (LPUART_FUNCSEL[3]) should be set then waited for TXRXACT (LPUART_FIFOSTS[31]) is cleared 245 * | | |When the configuration is done, cleared TXRXDIS (LPUART_FUNCSEL[3]) to activate LPUART controller. 246 * @var LPUART_T::FIFOSTS 247 * Offset: 0x18 LPUART FIFO Status Register 248 * --------------------------------------------------------------------------------------------------- 249 * |Bits |Field |Descriptions 250 * | :----: | :----: | :---- | 251 * |[0] |RXOVIF |RX Overflow Error Interrupt Flag 252 * | | |This bit is set when RX FIFO overflow. 253 * | | |If the number of bytes of received data is greater than RX_FIFO (LPUART_DAT) size 16 bytes, this bit will be set. 254 * | | |0 = RX FIFO is not overflow. 255 * | | |1 = RX FIFO is overflow. 256 * | | |Note: This bit can be cleared by writing '1' to it. 257 * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag 258 * | | |This bit is set to logic '1' when auto-baud rate detect function is finished. 259 * | | |0 = Auto-baud rate detect function is not finished. 260 * | | |1 = Auto-baud rate detect function is finished. 261 * | | |Note: This bit can be cleared by writing '1' to it. 262 * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag 263 * | | |This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow. 264 * | | |0 = Auto-baud rate counter is underflow. 265 * | | |1 = Auto-baud rate counter is overflow. 266 * | | |Note: This bit can be cleared by writing '1' to it. 267 * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag 268 * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). 269 * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). 270 * | | |Note 1: This field is used for RS-485 function mode and ADDRDEN (LPUART_ALTCTL[15]) is set to 1 to enable Address detection mode. 271 * | | |Note 2: This bit can be cleared by writing '1' to it. 272 * |[4] |PEF |Parity Error Flag 273 * | | |This bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'. 274 * | | |0 = No parity error is generated. 275 * | | |1 = Parity error is generated. 276 * | | |Note: This bit can be cleared by writing '1' to it. 277 * |[5] |FEF |Framing Error Flag 278 * | | |This bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). 279 * | | |0 = No framing error is generated. 280 * | | |1 = Framing error is generated. 281 * | | |Note: This bit can be cleared by writing '1' to it. 282 * |[6] |BIF |Break Interrupt Flag 283 * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'START bit' + data bits + parity + STOP bits). 284 * | | |0 = No Break interrupt is generated. 285 * | | |1 = Break interrupt is generated. 286 * | | |Note: This bit can be cleared by writing '1' to it. 287 * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) 288 * | | |This field indicates the RX FIFO Buffer Pointer 289 * | | |When LPUART receives one byte from external device, RXPTR increases one 290 * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. 291 * | | |The Maximum value shown in RXPTR is 15 292 * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0 293 * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15 294 * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) 295 * | | |This bit initiate RX FIFO empty or not. 296 * | | |0 = RX FIFO is not empty. 297 * | | |1 = RX FIFO is empty. 298 * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high 299 * | | |It will be cleared when LPUART receives any new data. 300 * |[15] |RXFULL |Receiver FIFO Full (Read Only) 301 * | | |This bit initiates RX FIFO full or not. 302 * | | |0 = RX FIFO is not full. 303 * | | |1 = RX FIFO is full. 304 * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 305 * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) 306 * | | |This field indicates the TX FIFO Buffer Pointer 307 * | | |When CPU writes one byte into LPUART_DAT, TXPTR increases one 308 * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. 309 * | | |The Maximum value shown in TXPTR is 15 310 * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0 311 * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15 312 * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) 313 * | | |This bit indicates TX FIFO empty or not. 314 * | | |0 = TX FIFO is not empty. 315 * | | |1 = TX FIFO is empty. 316 * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high 317 * | | |It will be cleared when writing data into LPUART_DAT (TX FIFO not empty). 318 * |[23] |TXFULL |Transmitter FIFO Full (Read Only) 319 * | | |This bit indicates TX FIFO full or not. 320 * | | |0 = TX FIFO is not full. 321 * | | |1 = TX FIFO is full. 322 * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. 323 * |[24] |TXOVIF |TX Overflow Error Interrupt Flag 324 * | | |If TX FIFO (LPUART_DAT) is full, an additional write to LPUART_DAT will cause this bit to logic 1. 325 * | | |0 = TX FIFO is not overflow. 326 * | | |1 = TX FIFO is overflow. 327 * | | |Note: This bit can be cleared by writing '1' to it. 328 * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) 329 * | | |This bit is set by hardware when TX FIFO (LPUART_DAT) is empty and the STOP bit of the last byte has been transmitted. 330 * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. 331 * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. 332 * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 333 * |[29] |RXIDLE |RX Idle Status (Read Only) 334 * | | |This bit is set by hardware when RX is idle. 335 * | | |0 = RX is busy. 336 * | | |1 = RX is idle. (Default) 337 * |[31] |TXRXACT |TX and RX Active Status (Read Only) 338 * | | |This bit indicates TX and RX are active or inactive. 339 * | | |0 = TX and RX are inactive. 340 * | | |1 = TX and RX are active. (Default) 341 * | | |Note: When TXRXDIS (LPUART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared 342 * | | |The LPUART controller cannot transmit or receive data at this moment 343 * | | |Otherwise this bit is set. 344 * @var LPUART_T::INTSTS 345 * Offset: 0x1C LPUART Interrupt Status Register 346 * --------------------------------------------------------------------------------------------------- 347 * |Bits |Field |Descriptions 348 * | :----: | :----: | :---- | 349 * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only) 350 * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(LPUART_INTSTS[0]) will be set 351 * | | |If RDAIEN (LPUART_INTEN[0]) is enabled, the RDA interrupt will be generated. 352 * | | |0 = No RDA interrupt flag is generated. 353 * | | |1 = RDA interrupt flag is generated. 354 * | | |Note: This bit is read only and will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(LPUART_FIFO[7:4]). 355 * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only) 356 * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register 357 * | | |If THREIEN (LPUART_INTEN[1]) is enabled, the THRE interrupt will be generated. 358 * | | |0 = No THRE interrupt flag is generated. 359 * | | |1 = THRE interrupt flag is generated. 360 * | | |Note: This bit is read only and will be cleared when writing data into LPUART_DAT (TX FIFO is not empty). 361 * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) 362 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(LPUART_FIFOSTS[6]), FEF(LPUART_FIFOSTS[5]) and PEF(LPUART_FIFOSTS[4]), is set) 363 * | | |If RLSIEN (LPUART_INTEN[2]) is enabled, the RLS interrupt will be generated. 364 * | | |0 = No RLS interrupt flag is generated. 365 * | | |1 = RLS interrupt flag is generated. 366 * | | |Note 1: In RS-485 function mode, this field is set include 'receiver detect and received address byte character (bit9 = '1') bit" 367 * | | |At the same time, the bit of ADDRDETF (LPUART_FIFOSTS[3]) is also set. 368 * | | |Note 2: This bit is read only and reset to 0 when all bits of BIF (LPUART_FIFOSTS[6]), FEF(LPUART_FIFOSTS[5]) and PEF(LPUART_FIFOSTS[4]) are cleared. 369 * | | |Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (LPUART_FIFOSTS[6]), FEF(LPUART_FIFOSTS[5]), PEF(LPUART_FIFOSTS[4]) and ADDRDETF (LPUART_FIFOSTS[3]) are cleared. 370 * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) 371 * | | |This bit is set when the nCTS pin has state change (CTSDETF (LPUART_MODEMSTS[0]) = 1) 372 * | | |If MODEMIEN (LPUART_INTEN[3]) is enabled, the Modem interrupt will be generated. 373 * | | |0 = No Modem interrupt flag is generated. 374 * | | |1 = Modem interrupt flag is generated. 375 * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(LPUART_MODEMSTS[0]). 376 * |[4] |RXTOIF |RX Time-out Interrupt Flag 377 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (LPUART_TOUT[7:0]) 378 * | | |If RXTOIEN (LPUART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. 379 * | | |0 = No RX time-out interrupt flag is generated. 380 * | | |1 = RX time-out interrupt flag is generated. 381 * | | |Note: This bit can be cleared by writing '1' to it 382 * | | |When BITOMEN (LPUART_TOUT[31]) is reset, this bit can also be cleared by reading LPUART_DAT. 383 * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) 384 * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (LPUART_FIFOSTS[24]) or RXOVIF (LPUART_FIFOSTS[0]) is set) 385 * | | |When BUFERRIF (LPUART_INTSTS[5]) is set, the transfer is not correct 386 * | | |If BUFERRIEN (LPUART_INTEN[5]) is enabled, the buffer error interrupt will be generated. 387 * | | |0 = No buffer error interrupt flag is generated. 388 * | | |1 = Buffer error interrupt flag is generated. 389 * | | |Note: This bit is cleared if both of RXOVIF(LPUART_FIFOSTS[0]) and TXOVIF(LPUART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(LPUART_FIFOSTS[0]) and TXOVIF(LPUART_FIFOSTS[24]). 390 * |[6] |WKIF |LPUART Wake-up Interrupt Flag (Read Only) 391 * | | |This bit is set when TOUTWKF (LPUART_WKSTS[4]), RS485WKF (LPUART_WKSTS[3]), RFRTWKF (LPUART_WKSTS[2]), DATWKF (LPUART_WKSTS[1]) or CTSWKF(LPUART_WKSTS[0]) is set to 1. 392 * | | |0 = No LPUART wake-up interrupt flag is generated. 393 * | | |1 = LPUART wake-up interrupt flag is generated. 394 * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. 395 * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) 396 * | | |This bit is set if RDAIEN (LPUART_INTEN[0]) and RDAIF (LPUART_INTSTS[0]) are both set to 1. 397 * | | |0 = No RDA interrupt is generated. 398 * | | |1 = RDA interrupt is generated. 399 * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) 400 * | | |This bit is set if THREIEN (LPUART_INTEN[1]) and THREIF(LPUART_INTSTS[1]) are both set to 1. 401 * | | |0 = No THRE interrupt is generated. 402 * | | |1 = THRE interrupt is generated. 403 * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) 404 * | | |This bit is set if RLSIEN (LPUART_INTEN[2]) and RLSIF(LPUART_INTSTS[2]) are both set to 1. 405 * | | |0 = No RLS interrupt is generated. 406 * | | |1 = RLS interrupt is generated. 407 * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) 408 * | | |This bit is set if MODEMIEN(LPUART_INTEN[3]) and MODEMIF(LPUART_INTSTS[3]) are both set to 1 409 * | | |0 = No Modem interrupt is generated. 410 * | | |1 = Modem interrupt is generated.. 411 * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) 412 * | | |This bit is set if RXTOIEN (LPUART_INTEN[4]) and RXTOIF(LPUART_INTSTS[4]) are both set to 1. 413 * | | |0 = No RX time-out interrupt is generated. 414 * | | |1 = RX time-out interrupt is generated. 415 * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) 416 * | | |This bit is set if BUFERRIEN(LPUART_INTEN[5]) and BUFERRIF(LPUART_ INTSTS[5]) are both set to 1. 417 * | | |0 = No buffer error interrupt is generated. 418 * | | |1 = Buffer error interrupt is generated. 419 * |[14] |WKINT |LPUART Wake-up Interrupt Indicator (Read Only) 420 * | | |This bit is set if WKIEN (LPUART_INTEN[6]) and WKIF (LPUART_INTSTS[6]) are both set to 1. 421 * | | |0 = No LPUART wake-up interrupt is generated. 422 * | | |1 = LPUART wake-up interrupt is generated. 423 * |[16] |SWBEIF |Single-wire Bit Error Detection Interrupt Flag 424 * | | |This bit is set when the single wire bus state not equals to LPUART controller TX state in Single-wire mode. 425 * | | |0 = No single-wire bit error detection interrupt flag is generated. 426 * | | |1 = Single-wire bit error detection interrupt flag is generated. 427 * | | |Note 1: This bit is active when FUNCSEL (LPUART_FUNCSEL[2:0]) is select LPUART Single-wire mode. 428 * | | |Note 2: This bit can be cleared by writing '1' to it. 429 * |[18] |HWRLSIF |LPPDMA Mode Receive Line Status Flag (Read Only) 430 * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (LPUART_FIFOSTS[6]), FEF (LPUART_FIFOSTS[5]) and PEF (LPUART_FIFOSTS[4]) is set) 431 * | | |If RLSIEN (LPUART_INTEN[2]) is enabled, the RLS interrupt will be generated. 432 * | | |0 = No RLS interrupt flag is generated in LPPDMA mode. 433 * | | |1 = RLS interrupt flag is generated in LPPDMA mode. 434 * | | |Note 1: In RS-485 function mode, this field include 'receiver detect any address byte received address byte character (bit9 = '1') bit". 435 * | | |Note 2: In LPUART function mode, this bit is read only and reset to 0 when all bits of BIF(LPUART_FIFOSTS[6]), FEF(LPUART_FIFOSTS[5]) and PEF(LPUART_FIFOSTS[4]) are cleared. 436 * | | |Note 3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(LPUART_FIFOSTS[6]), FEF(LPUART_FIFOSTS[5]), PEF(LPUART_FIFOSTS[4]) and ADDRDETF (LPUART_FIFOSTS[3]) are cleared 437 * |[19] |HWMODIF |LPPDMA Mode MODEM Interrupt Flag (Read Only) 438 * | | |This bit is set when the nCTS pin has state change (CTSDETF (LPUART_MODEMSTS[0] =1)) 439 * | | |If MODEMIEN (LPUART_INTEN[3]) is enabled, the Modem interrupt will be generated. 440 * | | |0 = No Modem interrupt flag is generated in LPPDMA mode. 441 * | | |1 = Modem interrupt flag is generated in LPPDMA mode. 442 * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (LPUART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (LPUART_MODEMSTS[0]). 443 * |[20] |HWTOIF |LPPDMA Mode RX Time-out Interrupt Flag 444 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (LPUART_TOUT[7:0]) 445 * | | |If RXTOIEN (LPUART_INTEN[4]) is enabled, the RX time-out interrupt will be generated. 446 * | | |0 = No RX time-out interrupt flag is generated in LPPDMA mode. 447 * | | |1 = RX time-out interrupt flag is generated in LPPDMA mode. 448 * | | |Note: This bit can be cleared by writing '1' to it 449 * | | |When BITOMEN (LPUART_TOUT[31]) is reset, this bit can also be cleared by reading LPUART_DAT. 450 * |[21] |HWBUFEIF |LPPDMA Mode Buffer Error Interrupt Flag (Read Only) 451 * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (LPUART_FIFOSTS[24]) or RXOVIF (LPUART_FIFOSTS[0]) is set) 452 * | | |When BUFERRIF (LPUART_INTSTS[5]) is set, the transfer maybe is not correct 453 * | | |If BUFERRIEN (LPUART_INTEN[5]) is enabled, the buffer error interrupt will be generated. 454 * | | |0 = No buffer error interrupt flag is generated in LPPDMA mode. 455 * | | |1 = Buffer error interrupt flag is generated in LPPDMA mode. 456 * | | |Note: This bit is cleared when both TXOVIF (LPUART_FIFOSTS[24]]) and RXOVIF (LPUART_FIFOSTS[0]) are cleared. 457 * |[22] |TXENDIF |Transmitter Empty Interrupt Flag 458 * | | |This bit is set when TX FIFO (LPUART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (LPUART_FIFOSTS[28]) is set) 459 * | | |If TXENDIEN (LPUART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. 460 * | | |0 = No transmitter empty interrupt flag is generated. 461 * | | |1 = Transmitter empty interrupt flag is generated. 462 * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. 463 * |[24] |SWBEINT |Single-wire Bit Error Detect Interrupt Indicator (Read Only) 464 * | | |This bit is set if SWBEIEN (LPUART_INTEN[16]) and SWBEIF (LPUART_INTSTS[16]) are both set to 1. 465 * | | |0 = No Single-wire Bit Error Detection Interrupt generated. 466 * | | |1 = Single-wire Bit Error Detection Interrupt generated. 467 * |[26] |HWRLSINT |LPPDMA Mode Receive Line Status Interrupt Indicator (Read Only) 468 * | | |This bit is set if RLSIEN (LPUART_INTEN[2]) and HWRLSIF(LPUART_INTSTS[18]) are both set to 1. 469 * | | |0 = No RLS interrupt is generated in LPPDMA mode. 470 * | | |1 = RLS interrupt is generated in LPPDMA mode. 471 * |[27] |HWMODINT |LPPDMA Mode MODEM Status Interrupt Indicator (Read Only) 472 * | | |This bit is set if MODEMIEN (LPUART_INTEN[3]) and HWMODIF(LPUART_INTSTS[19]) are both set to 1. 473 * | | |0 = No Modem interrupt is generated in LPPDMA mode. 474 * | | |1 = Modem interrupt is generated in LPPDMA mode. 475 * |[28] |HWTOINT |LPPDMA Mode RX Time-out Interrupt Indicator (Read Only) 476 * | | |This bit is set if RXTOIEN (LPUART_INTEN[4]) and HWTOIF(LPUART_INTSTS[20]) are both set to 1. 477 * | | |0 = No RX time-out interrupt is generated in LPPDMA mode. 478 * | | |1 = RX time-out interrupt is generated in LPPDMA mode. 479 * |[29] |HWBUFEINT |LPPDMA Mode Buffer Error Interrupt Indicator (Read Only) 480 * | | |This bit is set if BUFERRIEN (LPUART_INTEN[5]) and HWBUFEIF (LPUART_INTSTS[21]) are both set to 1. 481 * | | |0 = No buffer error interrupt is generated in LPPDMA mode. 482 * | | |1 = Buffer error interrupt is generated in LPPDMA mode. 483 * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) 484 * | | |This bit is set if TXENDIEN (LPUART_INTEN[22]) and TXENDIF(LPUART_INTSTS[22]) are both set to 1. 485 * | | |0 = No Transmitter Empty interrupt is generated. 486 * | | |1 = Transmitter Empty interrupt is generated. 487 * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) 488 * | | |This bit is set if ABRIEN (LPUART_INTEN[18]) and ABRIF (LPUART_ALTCTL[17]) are both set to 1. 489 * | | |0 = No Auto-baud Rate interrupt is generated. 490 * | | |1 = The Auto-baud Rate interrupt is generated. 491 * @var LPUART_T::TOUT 492 * Offset: 0x20 LPUART Time-out Register 493 * --------------------------------------------------------------------------------------------------- 494 * |Bits |Field |Descriptions 495 * | :----: | :----: | :---- | 496 * |[7:0] |TOIC |Time-out Interrupt Comparator 497 * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (LPUART_INTEN[11]) 498 * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (LPUART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(LPUART_INTSTS[12])) is generated if RXTOIEN (LPUART_INTEN[4]) enabled 499 * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (LPUART_INTSTS[4]) 500 * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255 501 * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 STOP bit and no parity check is set for LPUART transfer. 502 * |[15:8] |DLY |TX Delay Time Value 503 * | | |This field is used to program the transfer delay time between the last STOP bit and next START bit 504 * | | |The unit is bit time. 505 * |[31] |BITOMEN |Bus Idle Time-out Mode Enable Bit 506 * | | |If BITOMEN (LPUART_TOUT[31]) is enabled, the reset conditions of the time-out counter and RXTOIF (LPUART_INTSTS[4]) will be changed to detect the bus idle. 507 * | | |When BITOMEN (LPUART_TOUT[31]) is disabled, the time-out counter and RXTOIF (LPUART_INTSTS[4]) maintain reset value whenever the RX FIFO is empty 508 * | | |In addition, a new incoming data word will also clear RXTOIF (LPUART_INTSTS[4]). 509 * | | |On the other hand, when BITOMEN (LPUART_TOUT[31]) is enabled, the RX FIFO empty state will not reset the time-out counter and RXTOIF (LPUART_INTSTS[4]), and the new incoming data word event will not clear RXTOIF (LPUART_INTSTS[4]). 510 * | | |0 = Bus idle time-out mode Disabled. 511 * | | |1 = Bus idle time-out mode Enabled. 512 * @var LPUART_T::BAUD 513 * Offset: 0x24 LPUART Baud Rate Divider Register 514 * --------------------------------------------------------------------------------------------------- 515 * |Bits |Field |Descriptions 516 * | :----: | :----: | :---- | 517 * |[15:0] |BRD |Baud Rate Divider 518 * | | |The field indicates the baud rate divider 519 * | | |This filed is used in baud rate calculation 520 * | | |The detail description is shown in Table 6.28-4. 521 * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 522 * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2 523 * | | |The detail description is shown in Table 6.28-4 524 * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 525 * | | |This bit is baud rate mode selection bit 0 526 * | | |LPUART provides three baud rate calculation modes 527 * | | |This bit combines with BAUDM1 (LPUART_BAUD[29]) to select baud rate calculation mode 528 * | | |The detail description is shown in Table 6.28-4. 529 * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 530 * | | |This bit is baud rate mode selection bit 1 531 * | | |LPUART provides three baud rate calculation modes 532 * | | |This bit combines with BAUDM0 (LPUART_BAUD[28]) to select baud rate calculation mode 533 * | | |The detail description is shown in Table 6.28-4. 534 * @var LPUART_T::ALTCTL 535 * Offset: 0x2C LPUART Alternate Control/Status Register 536 * --------------------------------------------------------------------------------------------------- 537 * |Bits |Field |Descriptions 538 * | :----: | :----: | :---- | 539 * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode 540 * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. 541 * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. 542 * | | |Note: It cannot be active with RS-485_AAD operation mode. 543 * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode 544 * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. 545 * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. 546 * | | |Note: It cannot be active with RS-485_NMM operation mode. 547 * |[10] |RS485AUD |RS-485 Auto Direction Function 548 * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. 549 * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. 550 * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. 551 * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit 552 * | | |This bit is used to enable RS-485 Address Detection mode. 553 * | | |0 = Address detection mode Disabled. 554 * | | |1 = Address detection mode Enabled. 555 * | | |Note: This bit is used for RS-485 any operation mode. 556 * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) 557 * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(LPUART_INTEN[18]) is set then the auto-baud rate interrupt will be generated. 558 * | | |0 = No auto-baud rate interrupt flag is generated. 559 * | | |1 = Auto-baud rate interrupt flag is generated. 560 * | | |Note: This bit is read only, but it can be cleared by writing '1' to ABRDTOIF (LPUART_FIFOSTS[2]) and ABRDIF(LPUART_FIFOSTS[1]) 561 * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit 562 * | | |0 = Auto-baud rate detect function Disabled. 563 * | | |1 = Auto-baud rate detect function Enabled. 564 * | | |Note : This bit is cleared automatically after auto-baud detection is finished. 565 * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length 566 * | | |00 = 1-bit time from START bit to the 1st rising edge. The input pattern shall be 0x01. 567 * | | |01 = 2-bit time from START bit to the 1st rising edge. The input pattern shall be 0x02. 568 * | | |10 = 4-bit time from START bit to the 1st rising edge. The input pattern shall be 0x08. 569 * | | |11 = 8-bit time from START bit to the 1st rising edge. The input pattern shall be 0x80. 570 * | | |Note : The calculation of bit number includes the START bit. 571 * |[31:24] |ADDRMV |Address Match Value 572 * | | |This field contains the RS-485 address match values. 573 * | | |Note: This field is used for RS-485 auto address detection mode. 574 * @var LPUART_T::FUNCSEL 575 * Offset: 0x30 LPUART Function Select Register 576 * --------------------------------------------------------------------------------------------------- 577 * |Bits |Field |Descriptions 578 * | :----: | :----: | :---- | 579 * |[2:0] |FUNCSEL |Function Select 580 * | | |000 = LPUART function. 581 * | | |011 = RS-485 function. 582 * | | |100 = LPUART Single-wire function. 583 * | | |Others = Reserved. 584 * |[3] |TXRXDIS |TX and RX Disable Bit 585 * | | |Setting this bit can disable TX and RX. 586 * | | |0 = TX and RX Enabled. 587 * | | |1 = TX and RX Disabled. 588 * | | |Note: The TX and RX will not be disabled immediately when this bit is set 589 * | | |The TX and RX complete current task before TX and RX are disabled 590 * | | |When TX and RX are disabled, the TXRXACT (LPUART_FIFOSTS[31]) is cleared. 591 * |[6] |DGE |Deglitch Enable Bit 592 * | | |0 = Deglitch Disabled. 593 * | | |1 = Deglitch Enabled. 594 * | | |Note 1: When this bit is set to logic 1, any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX) 595 * | | |This bit acts only on RX line and has no effect on the transmitter logic. 596 * | | |Note 2: It is recommended to set this bit only when operating at baud rate under 2.5 Mbps. 597 * |[7] |TXRXSWP |TX and RX Swap Enable Bit 598 * | | |Setting this bit Swaps TX pin and RX pin. 599 * | | |0 = TX and RX Swap Disabled. 600 * | | |1 = TX and RX Swap Enabled. 601 * @var LPUART_T::BRCOMP 602 * Offset: 0x3C LPUART Baud Rate Compensation Register 603 * --------------------------------------------------------------------------------------------------- 604 * |Bits |Field |Descriptions 605 * | :----: | :----: | :---- | 606 * |[8:0] |BRCOMP |Baud Rate Compensation Patten 607 * | | |These 9-bits are used to define the relative bit is compensated or not. 608 * | | |BRCOMP[7:0] is used to define the compensation of DAT (LPUART_DAT[7:0]) and BRCOM[8] is used to define PARITY (LPUART_DAT[8]). 609 * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease 610 * | | |0 = Positive (increase one module clock) compensation for each compensated bit. 611 * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. 612 * @var LPUART_T::WKCTL 613 * Offset: 0x40 LPUART Wake-up Control Register 614 * --------------------------------------------------------------------------------------------------- 615 * |Bits |Field |Descriptions 616 * | :----: | :----: | :---- | 617 * |[0] |WKCTSEN |nCTS Wake-up Enable Bit 618 * | | |0 = nCTS Wake-up system function Disabled. 619 * | | |1 = nCTS Wake-up system function Enabled. 620 * | | |Note: When the system is in Power-down mode, an external nCTS change will wake up system from Power-down mode. 621 * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit 622 * | | |0 = Incoming data wake-up system function Disabled. 623 * | | |1 = Incoming data wake-up system function Enabled. 624 * | | |Note: When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. 625 * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit 626 * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. 627 * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled. 628 * | | |Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. 629 * |[3] |WKRS485EN |RS-485 Address Match Wake-up Enable Bit 630 * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. 631 * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled. 632 * | | |Note 1: When the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. 633 * | | |Note 2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (LPUART_ALTCTL[15]) is set to 1. 634 * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit 635 * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. 636 * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled. 637 * | | |Note 1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. 638 * | | |Note 2: It is suggested the function is enabled when the WKRFRTEN (LPUART_WKCTL[2]) is set to 1. 639 * @var LPUART_T::WKSTS 640 * Offset: 0x44 LPUART Wake-up Status Register 641 * --------------------------------------------------------------------------------------------------- 642 * |Bits |Field |Descriptions 643 * | :----: | :----: | :---- | 644 * |[0] |CTSWKF |nCTS Wake-up Flag 645 * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. 646 * | | |0 = Chip stays in power-down state. 647 * | | |1 = Chip wake-up from power-down state by nCTS wake-up. 648 * | | |Note 1: If WKCTSEN (LPUART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit set to '1'. 649 * | | |Note 2: This bit can be cleared by writing '1' to it. 650 * |[1] |DATWKF |Incoming Data Wake-up Flag 651 * | | |This bit is set if chip wake-up from power-down state by data wake-up. 652 * | | |0 = Chip stays in power-down state. 653 * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. 654 * | | |Note 1: If WKDATEN (LPUART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit set to '1'. 655 * | | |Note 2: This bit can be cleared by writing '1' to it. 656 * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag 657 * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. 658 * | | |0 = Chip stays in power-down state. 659 * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. 660 * | | |Note 1: If WKRFRTEN (LPUART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit set to '1'. 661 * | | |Note 2: This bit can be cleared by writing '1' to it. 662 * |[3] |RS485WKF |RS-485 Address Match Wake-up Flag 663 * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). 664 * | | |0 = Chip stays in power-down state. 665 * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. 666 * | | |Note 1: If WKRS485EN (LPUART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit set to '1'. 667 * | | |Note 2: This bit can be cleared by writing '1' to it. 668 * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag 669 * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. 670 * | | |0 = Chip stays in power-down state. 671 * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. 672 * | | |Note 1: If WKTOUTEN (LPUART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit set to '1'. 673 * | | |Note 2: This bit can be cleared by writing '1' to it. 674 * @var LPUART_T::DWKCOMP 675 * Offset: 0x48 LPUART Incoming Data Wake-up Compensation Register 676 * --------------------------------------------------------------------------------------------------- 677 * |Bits |Field |Descriptions 678 * | :----: | :----: | :---- | 679 * |[15:0] |STCOMP |START Bit Compensation Value 680 * | | |These bits field indicate how many clock cycle selected by LPUART_CLK do the LPUART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode. 681 * | | |Note: It is valid only when WKDATEN (LPUART_WKCTL[1]) is set. 682 * @var LPUART_T::RS485DD 683 * Offset: 0x4C LPUART RS485 Transceiver Deactivate Delay Register 684 * --------------------------------------------------------------------------------------------------- 685 * |Bits |Field |Descriptions 686 * | :----: | :----: | :---- | 687 * |[15:0] |RTSDDLY |RS485 Transceiver Deactivate Delay Value 688 * | | |These bits field indicate how many clock cycles selected by LPUART_CLK do the LPUART controller delay the RS485 transceiver state trancing when the state trancing of RS485 transceiver is from TX to RX state 689 * | | |These bits field have no effect when the state trancing of RS485 transceiver is from RX to TX state. 690 * | | |Note: It is valid only when RS485AUD (LPUART_ALTCTL[10]) is set. 691 * @var LPUART_T::AUTOCTL 692 * Offset: 0x58 LPUART Automatic Operation Control Register 693 * --------------------------------------------------------------------------------------------------- 694 * |Bits |Field |Descriptions 695 * | :----: | :----: | :---- | 696 * |[3:0] |TRIGSEL |Automatic Operation Trigger Source Select 697 * | | |0000 = Low Power Auto-operation Trigger Source from LPTMR0. 698 * | | |0001 = Low Power Auto-operation Trigger Source from LPTMR1. 699 * | | |0010 = Low Power Auto-operation Trigger Source from TTMR0. 700 * | | |0011 = Low Power Auto-operation Trigger Source from TTMR1. 701 * | | |0100 = Low Power Auto-operation Trigger Source from WKIOA0. 702 * | | |0101 = Low Power Auto-operation Trigger Source from WKIOB0. 703 * | | |0110 = Low Power Auto-operation Trigger Source from WKIOC0. 704 * | | |0111 = Low Power Auto-operation Trigger Source from WKIOD0. 705 * | | |1000~1111 = Reserved. 706 * |[4] |TRIGEN |Automatic Operation Trigger Enable Bit 707 * | | |When TRIGEN (LPUART_AUTOCTL[4]) is set to '1', the automatic TX operation of LPUART will be triggered by an event sent from the trigger source selected by TRIGSEL[3:0]. 708 * | | |0 = LPUART Automatic Operation Trigger disabled. 709 * | | |1 = LPUART Automatic Operation Trigger enabled. 710 * |[5] |CKAWOEN |Automatic Operation Clock Always-on Enable Bit 711 * | | |0 = Automatic Operation Clock Always-on Disabled. 712 * | | |1 = Automatic Operation Clock Always-on Enabled. 713 * |[8] |WKAOTOEN |Bus Idle Time-out Wake-up Enable Bit 714 * | | |0 = Bus Idle Time-out Wake-up system function Disabled. 715 * | | |1 = Bus Idle Time-out Wake-up system function Enabled. 716 * | | |Note 1: When the system is in Power-down mode, Bus Idle Time-out Wake-up will wake-up system from Power-down mode if WKAOTOEN (LPUART_AUTOCTL[8]) is set to '1'. 717 * | | |Note 2: When WKAOTOEN (LPUART_AUTOCTL[8]) is reset to '0', Bus Idle Time-out Wake-up event will not wake up the system 718 * | | |Moreover, Bus Idle Time-out Wake-up event will gate the LPUART clock off if WKAOTOEN (LPUART_AUTOCTL[8]) and AOCKAWOEN (LPUART_AUTOCTL[4]) are both reset to '0'. 719 * |[9] |SWTRIG |Software Trigger (Write Only) 720 * | | |After AOEN (LPUART_AUTOCTL[31]) is set to 1, software can manually trigger the automatic TX operation by writing 1 to this bit. 721 * |[31] |AOEN |Automatic Operation Enable Bit 722 * | | |0 = Automatic Operation Disabled. 723 * | | |1 = Automatic Operation Enabled. 724 * @var LPUART_T::AUTOSTS 725 * Offset: 0x5C LPUART Automatic Operation Status Register 726 * --------------------------------------------------------------------------------------------------- 727 * |Bits |Field |Descriptions 728 * | :----: | :----: | :---- | 729 * |[0] |AOTOWKF |Bus Idle Time-out Wake-up Flag 730 * | | |This bit is set if chip wake-up from power-down state by Bus Idle Time-out Wake-up 731 * | | |0 = There is no Bus Idle Time-out Wake-up event. 732 * | | |1 = Chip wake-up from power-down state by Bus Idle Time-out Wake-up. 733 * | | |Note 1: When RXPDMAEN (LPUART_INTEN[15]) or TXPDMAEN (LPUART_INTEN[14]) is enabled, this bit is the shadow bit of HWTOIF (LPUART_INTSTS[20]); user can read/clear it by reading/resetting HWTOIF (LPUART_INTSTS[20]) or AOTOWKF (LPUART_AUTOSTS[0]). 734 * | | |Note 2: When RXPDMAEN (LPUART_INTEN[15]) and TXPDMAEN (LPUART_INTEN[14]) are both disabled, this bit is the shadow bit of RXTOIF (LPUART_INTSTS[4]); user can read/clear it by reading/resetting RXTOIF (LPUART_INTSTS[4]) or AOTOWKF (LPUART_AUTOSTS[0]). 735 * | | |Note 3: If AOEN (LPUART_AUTOCTL[31]) and WKAOTOEN (LPUART_AUTOCTL[8]) are enabled, the Bus Idle Time-out Wake-up event will set this bit. 736 * | | |Note 4: This bit can be cleared by writing '1' to it. 737 */ 738 __IO uint32_t DAT; /*!< [0x0000] LPUART Receive/Transmit Buffer Register */ 739 __IO uint32_t INTEN; /*!< [0x0004] LPUART Interrupt Enable Register */ 740 __IO uint32_t FIFO; /*!< [0x0008] LPUART FIFO Control Register */ 741 __IO uint32_t LINE; /*!< [0x000c] LPUART Line Control Register */ 742 __IO uint32_t MODEM; /*!< [0x0010] LPUART Modem Control Register */ 743 __IO uint32_t MODEMSTS; /*!< [0x0014] LPUART Modem Status Register */ 744 __IO uint32_t FIFOSTS; /*!< [0x0018] LPUART FIFO Status Register */ 745 __IO uint32_t INTSTS; /*!< [0x001c] LPUART Interrupt Status Register */ 746 __IO uint32_t TOUT; /*!< [0x0020] LPUART Time-out Register */ 747 __IO uint32_t BAUD; /*!< [0x0024] LPUART Baud Rate Divider Register */ 748 __I uint32_t RESERVE0[1]; 749 __IO uint32_t ALTCTL; /*!< [0x002c] LPUART Alternate Control/Status Register */ 750 __IO uint32_t FUNCSEL; /*!< [0x0030] LPUART Function Select Register */ 751 __I uint32_t RESERVE1[2]; 752 __IO uint32_t BRCOMP; /*!< [0x003c] LPUART Baud Rate Compensation Register */ 753 __IO uint32_t WKCTL; /*!< [0x0040] LPUART Wake-up Control Register */ 754 __IO uint32_t WKSTS; /*!< [0x0044] LPUART Wake-up Status Register */ 755 __IO uint32_t DWKCOMP; /*!< [0x0048] LPUART Incoming Data Wake-up Compensation Register */ 756 __IO uint32_t RS485DD; /*!< [0x004c] LPUART RS485 Transceiver Deactivate Delay Register */ 757 __I uint32_t RESERVE2[2]; 758 __IO uint32_t AUTOCTL; /*!< [0x0058] LPUART Automatic Operation Control Register */ 759 __IO uint32_t AUTOSTS; /*!< [0x005c] LPUART Automatic Operation Status Register */ 760 761 } LPUART_T; 762 763 /** 764 @addtogroup LPUART_CONST LPUART Bit Field Definition 765 Constant Definitions for LPUART Controller 766 @{ */ 767 768 #define LPUART_DAT_DAT_Pos (0) /*!< LPUART_T::DAT: DAT Position */ 769 #define LPUART_DAT_DAT_Msk (0xfful << LPUART_DAT_DAT_Pos) /*!< LPUART_T::DAT: DAT Mask */ 770 771 #define LPUART_DAT_PARITY_Pos (8) /*!< LPUART_T::DAT: PARITY Position */ 772 #define LPUART_DAT_PARITY_Msk (0x1ul << LPUART_DAT_PARITY_Pos) /*!< LPUART_T::DAT: PARITY Mask */ 773 774 #define LPUART_INTEN_RDAIEN_Pos (0) /*!< LPUART_T::INTEN: RDAIEN Position */ 775 #define LPUART_INTEN_RDAIEN_Msk (0x1ul << LPUART_INTEN_RDAIEN_Pos) /*!< LPUART_T::INTEN: RDAIEN Mask */ 776 777 #define LPUART_INTEN_THREIEN_Pos (1) /*!< LPUART_T::INTEN: THREIEN Position */ 778 #define LPUART_INTEN_THREIEN_Msk (0x1ul << LPUART_INTEN_THREIEN_Pos) /*!< LPUART_T::INTEN: THREIEN Mask */ 779 780 #define LPUART_INTEN_RLSIEN_Pos (2) /*!< LPUART_T::INTEN: RLSIEN Position */ 781 #define LPUART_INTEN_RLSIEN_Msk (0x1ul << LPUART_INTEN_RLSIEN_Pos) /*!< LPUART_T::INTEN: RLSIEN Mask */ 782 783 #define LPUART_INTEN_MODEMIEN_Pos (3) /*!< LPUART_T::INTEN: MODEMIEN Position */ 784 #define LPUART_INTEN_MODEMIEN_Msk (0x1ul << LPUART_INTEN_MODEMIEN_Pos) /*!< LPUART_T::INTEN: MODEMIEN Mask */ 785 786 #define LPUART_INTEN_RXTOIEN_Pos (4) /*!< LPUART_T::INTEN: RXTOIEN Position */ 787 #define LPUART_INTEN_RXTOIEN_Msk (0x1ul << LPUART_INTEN_RXTOIEN_Pos) /*!< LPUART_T::INTEN: RXTOIEN Mask */ 788 789 #define LPUART_INTEN_BUFERRIEN_Pos (5) /*!< LPUART_T::INTEN: BUFERRIEN Position */ 790 #define LPUART_INTEN_BUFERRIEN_Msk (0x1ul << LPUART_INTEN_BUFERRIEN_Pos) /*!< LPUART_T::INTEN: BUFERRIEN Mask */ 791 792 #define LPUART_INTEN_WKIEN_Pos (6) /*!< LPUART_T::INTEN: WKIEN Position */ 793 #define LPUART_INTEN_WKIEN_Msk (0x1ul << LPUART_INTEN_WKIEN_Pos) /*!< LPUART_T::INTEN: WKIEN Mask */ 794 795 #define LPUART_INTEN_TOCNTEN_Pos (11) /*!< LPUART_T::INTEN: TOCNTEN Position */ 796 #define LPUART_INTEN_TOCNTEN_Msk (0x1ul << LPUART_INTEN_TOCNTEN_Pos) /*!< LPUART_T::INTEN: TOCNTEN Mask */ 797 798 #define LPUART_INTEN_ATORTSEN_Pos (12) /*!< LPUART_T::INTEN: ATORTSEN Position */ 799 #define LPUART_INTEN_ATORTSEN_Msk (0x1ul << LPUART_INTEN_ATORTSEN_Pos) /*!< LPUART_T::INTEN: ATORTSEN Mask */ 800 801 #define LPUART_INTEN_ATOCTSEN_Pos (13) /*!< LPUART_T::INTEN: ATOCTSEN Position */ 802 #define LPUART_INTEN_ATOCTSEN_Msk (0x1ul << LPUART_INTEN_ATOCTSEN_Pos) /*!< LPUART_T::INTEN: ATOCTSEN Mask */ 803 804 #define LPUART_INTEN_TXPDMAEN_Pos (14) /*!< LPUART_T::INTEN: TXPDMAEN Position */ 805 #define LPUART_INTEN_TXPDMAEN_Msk (0x1ul << LPUART_INTEN_TXPDMAEN_Pos) /*!< LPUART_T::INTEN: TXPDMAEN Mask */ 806 807 #define LPUART_INTEN_RXPDMAEN_Pos (15) /*!< LPUART_T::INTEN: RXPDMAEN Position */ 808 #define LPUART_INTEN_RXPDMAEN_Msk (0x1ul << LPUART_INTEN_RXPDMAEN_Pos) /*!< LPUART_T::INTEN: RXPDMAEN Mask */ 809 810 #define LPUART_INTEN_SWBEIEN_Pos (16) /*!< LPUART_T::INTEN: SWBEIEN Position */ 811 #define LPUART_INTEN_SWBEIEN_Msk (0x1ul << LPUART_INTEN_SWBEIEN_Pos) /*!< LPUART_T::INTEN: SWBEIEN Mask */ 812 813 #define LPUART_INTEN_ABRIEN_Pos (18) /*!< LPUART_T::INTEN: ABRIEN Position */ 814 #define LPUART_INTEN_ABRIEN_Msk (0x1ul << LPUART_INTEN_ABRIEN_Pos) /*!< LPUART_T::INTEN: ABRIEN Mask */ 815 816 #define LPUART_INTEN_TXENDIEN_Pos (22) /*!< LPUART_T::INTEN: TXENDIEN Position */ 817 #define LPUART_INTEN_TXENDIEN_Msk (0x1ul << LPUART_INTEN_TXENDIEN_Pos) /*!< LPUART_T::INTEN: TXENDIEN Mask */ 818 819 #define LPUART_FIFO_RXRST_Pos (1) /*!< LPUART_T::FIFO: RXRST Position */ 820 #define LPUART_FIFO_RXRST_Msk (0x1ul << LPUART_FIFO_RXRST_Pos) /*!< LPUART_T::FIFO: RXRST Mask */ 821 822 #define LPUART_FIFO_TXRST_Pos (2) /*!< LPUART_T::FIFO: TXRST Position */ 823 #define LPUART_FIFO_TXRST_Msk (0x1ul << LPUART_FIFO_TXRST_Pos) /*!< LPUART_T::FIFO: TXRST Mask */ 824 825 #define LPUART_FIFO_RFITL_Pos (4) /*!< LPUART_T::FIFO: RFITL Position */ 826 #define LPUART_FIFO_RFITL_Msk (0xful << LPUART_FIFO_RFITL_Pos) /*!< LPUART_T::FIFO: RFITL Mask */ 827 828 #define LPUART_FIFO_RXOFF_Pos (8) /*!< LPUART_T::FIFO: RXOFF Position */ 829 #define LPUART_FIFO_RXOFF_Msk (0x1ul << LPUART_FIFO_RXOFF_Pos) /*!< LPUART_T::FIFO: RXOFF Mask */ 830 831 #define LPUART_FIFO_RTSTRGLV_Pos (16) /*!< LPUART_T::FIFO: RTSTRGLV Position */ 832 #define LPUART_FIFO_RTSTRGLV_Msk (0xful << LPUART_FIFO_RTSTRGLV_Pos) /*!< LPUART_T::FIFO: RTSTRGLV Mask */ 833 834 #define LPUART_LINE_WLS_Pos (0) /*!< LPUART_T::LINE: WLS Position */ 835 #define LPUART_LINE_WLS_Msk (0x3ul << LPUART_LINE_WLS_Pos) /*!< LPUART_T::LINE: WLS Mask */ 836 837 #define LPUART_LINE_NSB_Pos (2) /*!< LPUART_T::LINE: NSB Position */ 838 #define LPUART_LINE_NSB_Msk (0x1ul << LPUART_LINE_NSB_Pos) /*!< LPUART_T::LINE: NSB Mask */ 839 840 #define LPUART_LINE_PBE_Pos (3) /*!< LPUART_T::LINE: PBE Position */ 841 #define LPUART_LINE_PBE_Msk (0x1ul << LPUART_LINE_PBE_Pos) /*!< LPUART_T::LINE: PBE Mask */ 842 843 #define LPUART_LINE_EPE_Pos (4) /*!< LPUART_T::LINE: EPE Position */ 844 #define LPUART_LINE_EPE_Msk (0x1ul << LPUART_LINE_EPE_Pos) /*!< LPUART_T::LINE: EPE Mask */ 845 846 #define LPUART_LINE_SPE_Pos (5) /*!< LPUART_T::LINE: SPE Position */ 847 #define LPUART_LINE_SPE_Msk (0x1ul << LPUART_LINE_SPE_Pos) /*!< LPUART_T::LINE: SPE Mask */ 848 849 #define LPUART_LINE_BCB_Pos (6) /*!< LPUART_T::LINE: BCB Position */ 850 #define LPUART_LINE_BCB_Msk (0x1ul << LPUART_LINE_BCB_Pos) /*!< LPUART_T::LINE: BCB Mask */ 851 852 #define LPUART_LINE_PSS_Pos (7) /*!< LPUART_T::LINE: PSS Position */ 853 #define LPUART_LINE_PSS_Msk (0x1ul << LPUART_LINE_PSS_Pos) /*!< LPUART_T::LINE: PSS Mask */ 854 855 #define LPUART_LINE_TXDINV_Pos (8) /*!< LPUART_T::LINE: TXDINV Position */ 856 #define LPUART_LINE_TXDINV_Msk (0x1ul << LPUART_LINE_TXDINV_Pos) /*!< LPUART_T::LINE: TXDINV Mask */ 857 858 #define LPUART_LINE_RXDINV_Pos (9) /*!< LPUART_T::LINE: RXDINV Position */ 859 #define LPUART_LINE_RXDINV_Msk (0x1ul << LPUART_LINE_RXDINV_Pos) /*!< LPUART_T::LINE: RXDINV Mask */ 860 861 #define LPUART_MODEM_RTS_Pos (1) /*!< LPUART_T::MODEM: RTS Position */ 862 #define LPUART_MODEM_RTS_Msk (0x1ul << LPUART_MODEM_RTS_Pos) /*!< LPUART_T::MODEM: RTS Mask */ 863 864 #define LPUART_MODEM_RTSACTLV_Pos (9) /*!< LPUART_T::MODEM: RTSACTLV Position */ 865 #define LPUART_MODEM_RTSACTLV_Msk (0x1ul << LPUART_MODEM_RTSACTLV_Pos) /*!< LPUART_T::MODEM: RTSACTLV Mask */ 866 867 #define LPUART_MODEM_RTSSTS_Pos (13) /*!< LPUART_T::MODEM: RTSSTS Position */ 868 #define LPUART_MODEM_RTSSTS_Msk (0x1ul << LPUART_MODEM_RTSSTS_Pos) /*!< LPUART_T::MODEM: RTSSTS Mask */ 869 870 #define LPUART_MODEMSTS_CTSDETF_Pos (0) /*!< LPUART_T::MODEMSTS: CTSDETF Position */ 871 #define LPUART_MODEMSTS_CTSDETF_Msk (0x1ul << LPUART_MODEMSTS_CTSDETF_Pos) /*!< LPUART_T::MODEMSTS: CTSDETF Mask */ 872 873 #define LPUART_MODEMSTS_CTSSTS_Pos (4) /*!< LPUART_T::MODEMSTS: CTSSTS Position */ 874 #define LPUART_MODEMSTS_CTSSTS_Msk (0x1ul << LPUART_MODEMSTS_CTSSTS_Pos) /*!< LPUART_T::MODEMSTS: CTSSTS Mask */ 875 876 #define LPUART_MODEMSTS_CTSACTLV_Pos (8) /*!< LPUART_T::MODEMSTS: CTSACTLV Position */ 877 #define LPUART_MODEMSTS_CTSACTLV_Msk (0x1ul << LPUART_MODEMSTS_CTSACTLV_Pos) /*!< LPUART_T::MODEMSTS: CTSACTLV Mask */ 878 879 #define LPUART_FIFOSTS_RXOVIF_Pos (0) /*!< LPUART_T::FIFOSTS: RXOVIF Position */ 880 #define LPUART_FIFOSTS_RXOVIF_Msk (0x1ul << LPUART_FIFOSTS_RXOVIF_Pos) /*!< LPUART_T::FIFOSTS: RXOVIF Mask */ 881 882 #define LPUART_FIFOSTS_ABRDIF_Pos (1) /*!< LPUART_T::FIFOSTS: ABRDIF Position */ 883 #define LPUART_FIFOSTS_ABRDIF_Msk (0x1ul << LPUART_FIFOSTS_ABRDIF_Pos) /*!< LPUART_T::FIFOSTS: ABRDIF Mask */ 884 885 #define LPUART_FIFOSTS_ABRDTOIF_Pos (2) /*!< LPUART_T::FIFOSTS: ABRDTOIF Position */ 886 #define LPUART_FIFOSTS_ABRDTOIF_Msk (0x1ul << LPUART_FIFOSTS_ABRDTOIF_Pos) /*!< LPUART_T::FIFOSTS: ABRDTOIF Mask */ 887 888 #define LPUART_FIFOSTS_ADDRDETF_Pos (3) /*!< LPUART_T::FIFOSTS: ADDRDETF Position */ 889 #define LPUART_FIFOSTS_ADDRDETF_Msk (0x1ul << LPUART_FIFOSTS_ADDRDETF_Pos) /*!< LPUART_T::FIFOSTS: ADDRDETF Mask */ 890 891 #define LPUART_FIFOSTS_PEF_Pos (4) /*!< LPUART_T::FIFOSTS: PEF Position */ 892 #define LPUART_FIFOSTS_PEF_Msk (0x1ul << LPUART_FIFOSTS_PEF_Pos) /*!< LPUART_T::FIFOSTS: PEF Mask */ 893 894 #define LPUART_FIFOSTS_FEF_Pos (5) /*!< LPUART_T::FIFOSTS: FEF Position */ 895 #define LPUART_FIFOSTS_FEF_Msk (0x1ul << LPUART_FIFOSTS_FEF_Pos) /*!< LPUART_T::FIFOSTS: FEF Mask */ 896 897 #define LPUART_FIFOSTS_BIF_Pos (6) /*!< LPUART_T::FIFOSTS: BIF Position */ 898 #define LPUART_FIFOSTS_BIF_Msk (0x1ul << LPUART_FIFOSTS_BIF_Pos) /*!< LPUART_T::FIFOSTS: BIF Mask */ 899 900 #define LPUART_FIFOSTS_RXPTR_Pos (8) /*!< LPUART_T::FIFOSTS: RXPTR Position */ 901 #define LPUART_FIFOSTS_RXPTR_Msk (0x3ful << LPUART_FIFOSTS_RXPTR_Pos) /*!< LPUART_T::FIFOSTS: RXPTR Mask */ 902 903 #define LPUART_FIFOSTS_RXEMPTY_Pos (14) /*!< LPUART_T::FIFOSTS: RXEMPTY Position */ 904 #define LPUART_FIFOSTS_RXEMPTY_Msk (0x1ul << LPUART_FIFOSTS_RXEMPTY_Pos) /*!< LPUART_T::FIFOSTS: RXEMPTY Mask */ 905 906 #define LPUART_FIFOSTS_RXFULL_Pos (15) /*!< LPUART_T::FIFOSTS: RXFULL Position */ 907 #define LPUART_FIFOSTS_RXFULL_Msk (0x1ul << LPUART_FIFOSTS_RXFULL_Pos) /*!< LPUART_T::FIFOSTS: RXFULL Mask */ 908 909 #define LPUART_FIFOSTS_TXPTR_Pos (16) /*!< LPUART_T::FIFOSTS: TXPTR Position */ 910 #define LPUART_FIFOSTS_TXPTR_Msk (0x3ful << LPUART_FIFOSTS_TXPTR_Pos) /*!< LPUART_T::FIFOSTS: TXPTR Mask */ 911 912 #define LPUART_FIFOSTS_TXEMPTY_Pos (22) /*!< LPUART_T::FIFOSTS: TXEMPTY Position */ 913 #define LPUART_FIFOSTS_TXEMPTY_Msk (0x1ul << LPUART_FIFOSTS_TXEMPTY_Pos) /*!< LPUART_T::FIFOSTS: TXEMPTY Mask */ 914 915 #define LPUART_FIFOSTS_TXFULL_Pos (23) /*!< LPUART_T::FIFOSTS: TXFULL Position */ 916 #define LPUART_FIFOSTS_TXFULL_Msk (0x1ul << LPUART_FIFOSTS_TXFULL_Pos) /*!< LPUART_T::FIFOSTS: TXFULL Mask */ 917 918 #define LPUART_FIFOSTS_TXOVIF_Pos (24) /*!< LPUART_T::FIFOSTS: TXOVIF Position */ 919 #define LPUART_FIFOSTS_TXOVIF_Msk (0x1ul << LPUART_FIFOSTS_TXOVIF_Pos) /*!< LPUART_T::FIFOSTS: TXOVIF Mask */ 920 921 #define LPUART_FIFOSTS_TXEMPTYF_Pos (28) /*!< LPUART_T::FIFOSTS: TXEMPTYF Position */ 922 #define LPUART_FIFOSTS_TXEMPTYF_Msk (0x1ul << LPUART_FIFOSTS_TXEMPTYF_Pos) /*!< LPUART_T::FIFOSTS: TXEMPTYF Mask */ 923 924 #define LPUART_FIFOSTS_RXIDLE_Pos (29) /*!< LPUART_T::FIFOSTS: RXIDLE Position */ 925 #define LPUART_FIFOSTS_RXIDLE_Msk (0x1ul << LPUART_FIFOSTS_RXIDLE_Pos) /*!< LPUART_T::FIFOSTS: RXIDLE Mask */ 926 927 #define LPUART_FIFOSTS_TXRXACT_Pos (31) /*!< LPUART_T::FIFOSTS: TXRXACT Position */ 928 #define LPUART_FIFOSTS_TXRXACT_Msk (0x1ul << LPUART_FIFOSTS_TXRXACT_Pos) /*!< LPUART_T::FIFOSTS: TXRXACT Mask */ 929 930 #define LPUART_INTSTS_RDAIF_Pos (0) /*!< LPUART_T::INTSTS: RDAIF Position */ 931 #define LPUART_INTSTS_RDAIF_Msk (0x1ul << LPUART_INTSTS_RDAIF_Pos) /*!< LPUART_T::INTSTS: RDAIF Mask */ 932 933 #define LPUART_INTSTS_THREIF_Pos (1) /*!< LPUART_T::INTSTS: THREIF Position */ 934 #define LPUART_INTSTS_THREIF_Msk (0x1ul << LPUART_INTSTS_THREIF_Pos) /*!< LPUART_T::INTSTS: THREIF Mask */ 935 936 #define LPUART_INTSTS_RLSIF_Pos (2) /*!< LPUART_T::INTSTS: RLSIF Position */ 937 #define LPUART_INTSTS_RLSIF_Msk (0x1ul << LPUART_INTSTS_RLSIF_Pos) /*!< LPUART_T::INTSTS: RLSIF Mask */ 938 939 #define LPUART_INTSTS_MODEMIF_Pos (3) /*!< LPUART_T::INTSTS: MODEMIF Position */ 940 #define LPUART_INTSTS_MODEMIF_Msk (0x1ul << LPUART_INTSTS_MODEMIF_Pos) /*!< LPUART_T::INTSTS: MODEMIF Mask */ 941 942 #define LPUART_INTSTS_RXTOIF_Pos (4) /*!< LPUART_T::INTSTS: RXTOIF Position */ 943 #define LPUART_INTSTS_RXTOIF_Msk (0x1ul << LPUART_INTSTS_RXTOIF_Pos) /*!< LPUART_T::INTSTS: RXTOIF Mask */ 944 945 #define LPUART_INTSTS_BUFERRIF_Pos (5) /*!< LPUART_T::INTSTS: BUFERRIF Position */ 946 #define LPUART_INTSTS_BUFERRIF_Msk (0x1ul << LPUART_INTSTS_BUFERRIF_Pos) /*!< LPUART_T::INTSTS: BUFERRIF Mask */ 947 948 #define LPUART_INTSTS_WKIF_Pos (6) /*!< LPUART_T::INTSTS: WKIF Position */ 949 #define LPUART_INTSTS_WKIF_Msk (0x1ul << LPUART_INTSTS_WKIF_Pos) /*!< LPUART_T::INTSTS: WKIF Mask */ 950 951 #define LPUART_INTSTS_RDAINT_Pos (8) /*!< LPUART_T::INTSTS: RDAINT Position */ 952 #define LPUART_INTSTS_RDAINT_Msk (0x1ul << LPUART_INTSTS_RDAINT_Pos) /*!< LPUART_T::INTSTS: RDAINT Mask */ 953 954 #define LPUART_INTSTS_THREINT_Pos (9) /*!< LPUART_T::INTSTS: THREINT Position */ 955 #define LPUART_INTSTS_THREINT_Msk (0x1ul << LPUART_INTSTS_THREINT_Pos) /*!< LPUART_T::INTSTS: THREINT Mask */ 956 957 #define LPUART_INTSTS_RLSINT_Pos (10) /*!< LPUART_T::INTSTS: RLSINT Position */ 958 #define LPUART_INTSTS_RLSINT_Msk (0x1ul << LPUART_INTSTS_RLSINT_Pos) /*!< LPUART_T::INTSTS: RLSINT Mask */ 959 960 #define LPUART_INTSTS_MODEMINT_Pos (11) /*!< LPUART_T::INTSTS: MODEMINT Position */ 961 #define LPUART_INTSTS_MODEMINT_Msk (0x1ul << LPUART_INTSTS_MODEMINT_Pos) /*!< LPUART_T::INTSTS: MODEMINT Mask */ 962 963 #define LPUART_INTSTS_RXTOINT_Pos (12) /*!< LPUART_T::INTSTS: RXTOINT Position */ 964 #define LPUART_INTSTS_RXTOINT_Msk (0x1ul << LPUART_INTSTS_RXTOINT_Pos) /*!< LPUART_T::INTSTS: RXTOINT Mask */ 965 966 #define LPUART_INTSTS_BUFERRINT_Pos (13) /*!< LPUART_T::INTSTS: BUFERRINT Position */ 967 #define LPUART_INTSTS_BUFERRINT_Msk (0x1ul << LPUART_INTSTS_BUFERRINT_Pos) /*!< LPUART_T::INTSTS: BUFERRINT Mask */ 968 969 #define LPUART_INTSTS_WKINT_Pos (14) /*!< LPUART_T::INTSTS: WKINT Position */ 970 #define LPUART_INTSTS_WKINT_Msk (0x1ul << LPUART_INTSTS_WKINT_Pos) /*!< LPUART_T::INTSTS: WKINT Mask */ 971 972 #define LPUART_INTSTS_SWBEIF_Pos (16) /*!< LPUART_T::INTSTS: SWBEIF Position */ 973 #define LPUART_INTSTS_SWBEIF_Msk (0x1ul << LPUART_INTSTS_SWBEIF_Pos) /*!< LPUART_T::INTSTS: SWBEIF Mask */ 974 975 #define LPUART_INTSTS_HWRLSIF_Pos (18) /*!< LPUART_T::INTSTS: HWRLSIF Position */ 976 #define LPUART_INTSTS_HWRLSIF_Msk (0x1ul << LPUART_INTSTS_HWRLSIF_Pos) /*!< LPUART_T::INTSTS: HWRLSIF Mask */ 977 978 #define LPUART_INTSTS_HWMODIF_Pos (19) /*!< LPUART_T::INTSTS: HWMODIF Position */ 979 #define LPUART_INTSTS_HWMODIF_Msk (0x1ul << LPUART_INTSTS_HWMODIF_Pos) /*!< LPUART_T::INTSTS: HWMODIF Mask */ 980 981 #define LPUART_INTSTS_HWTOIF_Pos (20) /*!< LPUART_T::INTSTS: HWTOIF Position */ 982 #define LPUART_INTSTS_HWTOIF_Msk (0x1ul << LPUART_INTSTS_HWTOIF_Pos) /*!< LPUART_T::INTSTS: HWTOIF Mask */ 983 984 #define LPUART_INTSTS_HWBUFEIF_Pos (21) /*!< LPUART_T::INTSTS: HWBUFEIF Position */ 985 #define LPUART_INTSTS_HWBUFEIF_Msk (0x1ul << LPUART_INTSTS_HWBUFEIF_Pos) /*!< LPUART_T::INTSTS: HWBUFEIF Mask */ 986 987 #define LPUART_INTSTS_TXENDIF_Pos (22) /*!< LPUART_T::INTSTS: TXENDIF Position */ 988 #define LPUART_INTSTS_TXENDIF_Msk (0x1ul << LPUART_INTSTS_TXENDIF_Pos) /*!< LPUART_T::INTSTS: TXENDIF Mask */ 989 990 #define LPUART_INTSTS_SWBEINT_Pos (24) /*!< LPUART_T::INTSTS: SWBEINT Position */ 991 #define LPUART_INTSTS_SWBEINT_Msk (0x1ul << LPUART_INTSTS_SWBEINT_Pos) /*!< LPUART_T::INTSTS: SWBEINT Mask */ 992 993 #define LPUART_INTSTS_HWRLSINT_Pos (26) /*!< LPUART_T::INTSTS: HWRLSINT Position */ 994 #define LPUART_INTSTS_HWRLSINT_Msk (0x1ul << LPUART_INTSTS_HWRLSINT_Pos) /*!< LPUART_T::INTSTS: HWRLSINT Mask */ 995 996 #define LPUART_INTSTS_HWMODINT_Pos (27) /*!< LPUART_T::INTSTS: HWMODINT Position */ 997 #define LPUART_INTSTS_HWMODINT_Msk (0x1ul << LPUART_INTSTS_HWMODINT_Pos) /*!< LPUART_T::INTSTS: HWMODINT Mask */ 998 999 #define LPUART_INTSTS_HWTOINT_Pos (28) /*!< LPUART_T::INTSTS: HWTOINT Position */ 1000 #define LPUART_INTSTS_HWTOINT_Msk (0x1ul << LPUART_INTSTS_HWTOINT_Pos) /*!< LPUART_T::INTSTS: HWTOINT Mask */ 1001 1002 #define LPUART_INTSTS_HWBUFEINT_Pos (29) /*!< LPUART_T::INTSTS: HWBUFEINT Position */ 1003 #define LPUART_INTSTS_HWBUFEINT_Msk (0x1ul << LPUART_INTSTS_HWBUFEINT_Pos) /*!< LPUART_T::INTSTS: HWBUFEINT Mask */ 1004 1005 #define LPUART_INTSTS_TXENDINT_Pos (30) /*!< LPUART_T::INTSTS: TXENDINT Position */ 1006 #define LPUART_INTSTS_TXENDINT_Msk (0x1ul << LPUART_INTSTS_TXENDINT_Pos) /*!< LPUART_T::INTSTS: TXENDINT Mask */ 1007 1008 #define LPUART_INTSTS_ABRINT_Pos (31) /*!< LPUART_T::INTSTS: ABRINT Position */ 1009 #define LPUART_INTSTS_ABRINT_Msk (0x1ul << LPUART_INTSTS_ABRINT_Pos) /*!< LPUART_T::INTSTS: ABRINT Mask */ 1010 1011 #define LPUART_TOUT_TOIC_Pos (0) /*!< LPUART_T::TOUT: TOIC Position */ 1012 #define LPUART_TOUT_TOIC_Msk (0xfful << LPUART_TOUT_TOIC_Pos) /*!< LPUART_T::TOUT: TOIC Mask */ 1013 1014 #define LPUART_TOUT_DLY_Pos (8) /*!< LPUART_T::TOUT: DLY Position */ 1015 #define LPUART_TOUT_DLY_Msk (0xfful << LPUART_TOUT_DLY_Pos) /*!< LPUART_T::TOUT: DLY Mask */ 1016 1017 #define LPUART_TOUT_BITOMEN_Pos (31) /*!< LPUART_T::TOUT: BITOMEN Position */ 1018 #define LPUART_TOUT_BITOMEN_Msk (0x1ul << LPUART_TOUT_BITOMEN_Pos) /*!< LPUART_T::TOUT: BITOMEN Mask */ 1019 1020 #define LPUART_BAUD_BRD_Pos (0) /*!< LPUART_T::BAUD: BRD Position */ 1021 #define LPUART_BAUD_BRD_Msk (0xfffful << LPUART_BAUD_BRD_Pos) /*!< LPUART_T::BAUD: BRD Mask */ 1022 1023 #define LPUART_BAUD_EDIVM1_Pos (24) /*!< LPUART_T::BAUD: EDIVM1 Position */ 1024 #define LPUART_BAUD_EDIVM1_Msk (0xful << LPUART_BAUD_EDIVM1_Pos) /*!< LPUART_T::BAUD: EDIVM1 Mask */ 1025 1026 #define LPUART_BAUD_BAUDM0_Pos (28) /*!< LPUART_T::BAUD: BAUDM0 Position */ 1027 #define LPUART_BAUD_BAUDM0_Msk (0x1ul << LPUART_BAUD_BAUDM0_Pos) /*!< LPUART_T::BAUD: BAUDM0 Mask */ 1028 1029 #define LPUART_BAUD_BAUDM1_Pos (29) /*!< LPUART_T::BAUD: BAUDM1 Position */ 1030 #define LPUART_BAUD_BAUDM1_Msk (0x1ul << LPUART_BAUD_BAUDM1_Pos) /*!< LPUART_T::BAUD: BAUDM1 Mask */ 1031 1032 #define LPUART_ALTCTL_RS485NMM_Pos (8) /*!< LPUART_T::ALTCTL: RS485NMM Position */ 1033 #define LPUART_ALTCTL_RS485NMM_Msk (0x1ul << LPUART_ALTCTL_RS485NMM_Pos) /*!< LPUART_T::ALTCTL: RS485NMM Mask */ 1034 1035 #define LPUART_ALTCTL_RS485AAD_Pos (9) /*!< LPUART_T::ALTCTL: RS485AAD Position */ 1036 #define LPUART_ALTCTL_RS485AAD_Msk (0x1ul << LPUART_ALTCTL_RS485AAD_Pos) /*!< LPUART_T::ALTCTL: RS485AAD Mask */ 1037 1038 #define LPUART_ALTCTL_RS485AUD_Pos (10) /*!< LPUART_T::ALTCTL: RS485AUD Position */ 1039 #define LPUART_ALTCTL_RS485AUD_Msk (0x1ul << LPUART_ALTCTL_RS485AUD_Pos) /*!< LPUART_T::ALTCTL: RS485AUD Mask */ 1040 1041 #define LPUART_ALTCTL_ADDRDEN_Pos (15) /*!< LPUART_T::ALTCTL: ADDRDEN Position */ 1042 #define LPUART_ALTCTL_ADDRDEN_Msk (0x1ul << LPUART_ALTCTL_ADDRDEN_Pos) /*!< LPUART_T::ALTCTL: ADDRDEN Mask */ 1043 1044 #define LPUART_ALTCTL_ABRIF_Pos (17) /*!< LPUART_T::ALTCTL: ABRIF Position */ 1045 #define LPUART_ALTCTL_ABRIF_Msk (0x1ul << LPUART_ALTCTL_ABRIF_Pos) /*!< LPUART_T::ALTCTL: ABRIF Mask */ 1046 1047 #define LPUART_ALTCTL_ABRDEN_Pos (18) /*!< LPUART_T::ALTCTL: ABRDEN Position */ 1048 #define LPUART_ALTCTL_ABRDEN_Msk (0x1ul << LPUART_ALTCTL_ABRDEN_Pos) /*!< LPUART_T::ALTCTL: ABRDEN Mask */ 1049 1050 #define LPUART_ALTCTL_ABRDBITS_Pos (19) /*!< LPUART_T::ALTCTL: ABRDBITS Position */ 1051 #define LPUART_ALTCTL_ABRDBITS_Msk (0x3ul << LPUART_ALTCTL_ABRDBITS_Pos) /*!< LPUART_T::ALTCTL: ABRDBITS Mask */ 1052 1053 #define LPUART_ALTCTL_ADDRMV_Pos (24) /*!< LPUART_T::ALTCTL: ADDRMV Position */ 1054 #define LPUART_ALTCTL_ADDRMV_Msk (0xfful << LPUART_ALTCTL_ADDRMV_Pos) /*!< LPUART_T::ALTCTL: ADDRMV Mask */ 1055 1056 #define LPUART_FUNCSEL_FUNCSEL_Pos (0) /*!< LPUART_T::FUNCSEL: FUNCSEL Position */ 1057 #define LPUART_FUNCSEL_FUNCSEL_Msk (0x7ul << LPUART_FUNCSEL_FUNCSEL_Pos) /*!< LPUART_T::FUNCSEL: FUNCSEL Mask */ 1058 1059 #define LPUART_FUNCSEL_TXRXDIS_Pos (3) /*!< LPUART_T::FUNCSEL: TXRXDIS Position */ 1060 #define LPUART_FUNCSEL_TXRXDIS_Msk (0x1ul << LPUART_FUNCSEL_TXRXDIS_Pos) /*!< LPUART_T::FUNCSEL: TXRXDIS Mask */ 1061 1062 #define LPUART_FUNCSEL_DGE_Pos (6) /*!< LPUART_T::FUNCSEL: DGE Position */ 1063 #define LPUART_FUNCSEL_DGE_Msk (0x1ul << LPUART_FUNCSEL_DGE_Pos) /*!< LPUART_T::FUNCSEL: DGE Mask */ 1064 1065 #define LPUART_FUNCSEL_TXRXSWP_Pos (7) /*!< LPUART_T::FUNCSEL: TXRXSWP Position */ 1066 #define LPUART_FUNCSEL_TXRXSWP_Msk (0x1ul << LPUART_FUNCSEL_TXRXSWP_Pos) /*!< LPUART_T::FUNCSEL: TXRXSWP Mask */ 1067 1068 #define LPUART_BRCOMP_BRCOMP_Pos (0) /*!< LPUART_T::BRCOMP: BRCOMP Position */ 1069 #define LPUART_BRCOMP_BRCOMP_Msk (0x1fful << LPUART_BRCOMP_BRCOMP_Pos) /*!< LPUART_T::BRCOMP: BRCOMP Mask */ 1070 1071 #define LPUART_BRCOMP_BRCOMPDEC_Pos (31) /*!< LPUART_T::BRCOMP: BRCOMPDEC Position */ 1072 #define LPUART_BRCOMP_BRCOMPDEC_Msk (0x1ul << LPUART_BRCOMP_BRCOMPDEC_Pos) /*!< LPUART_T::BRCOMP: BRCOMPDEC Mask */ 1073 1074 #define LPUART_WKCTL_WKCTSEN_Pos (0) /*!< LPUART_T::WKCTL: WKCTSEN Position */ 1075 #define LPUART_WKCTL_WKCTSEN_Msk (0x1ul << LPUART_WKCTL_WKCTSEN_Pos) /*!< LPUART_T::WKCTL: WKCTSEN Mask */ 1076 1077 #define LPUART_WKCTL_WKDATEN_Pos (1) /*!< LPUART_T::WKCTL: WKDATEN Position */ 1078 #define LPUART_WKCTL_WKDATEN_Msk (0x1ul << LPUART_WKCTL_WKDATEN_Pos) /*!< LPUART_T::WKCTL: WKDATEN Mask */ 1079 1080 #define LPUART_WKCTL_WKRFRTEN_Pos (2) /*!< LPUART_T::WKCTL: WKRFRTEN Position */ 1081 #define LPUART_WKCTL_WKRFRTEN_Msk (0x1ul << LPUART_WKCTL_WKRFRTEN_Pos) /*!< LPUART_T::WKCTL: WKRFRTEN Mask */ 1082 1083 #define LPUART_WKCTL_WKRS485EN_Pos (3) /*!< LPUART_T::WKCTL: WKRS485EN Position */ 1084 #define LPUART_WKCTL_WKRS485EN_Msk (0x1ul << LPUART_WKCTL_WKRS485EN_Pos) /*!< LPUART_T::WKCTL: WKRS485EN Mask */ 1085 1086 #define LPUART_WKCTL_WKTOUTEN_Pos (4) /*!< LPUART_T::WKCTL: WKTOUTEN Position */ 1087 #define LPUART_WKCTL_WKTOUTEN_Msk (0x1ul << LPUART_WKCTL_WKTOUTEN_Pos) /*!< LPUART_T::WKCTL: WKTOUTEN Mask */ 1088 1089 #define LPUART_WKSTS_CTSWKF_Pos (0) /*!< LPUART_T::WKSTS: CTSWKF Position */ 1090 #define LPUART_WKSTS_CTSWKF_Msk (0x1ul << LPUART_WKSTS_CTSWKF_Pos) /*!< LPUART_T::WKSTS: CTSWKF Mask */ 1091 1092 #define LPUART_WKSTS_DATWKF_Pos (1) /*!< LPUART_T::WKSTS: DATWKF Position */ 1093 #define LPUART_WKSTS_DATWKF_Msk (0x1ul << LPUART_WKSTS_DATWKF_Pos) /*!< LPUART_T::WKSTS: DATWKF Mask */ 1094 1095 #define LPUART_WKSTS_RFRTWKF_Pos (2) /*!< LPUART_T::WKSTS: RFRTWKF Position */ 1096 #define LPUART_WKSTS_RFRTWKF_Msk (0x1ul << LPUART_WKSTS_RFRTWKF_Pos) /*!< LPUART_T::WKSTS: RFRTWKF Mask */ 1097 1098 #define LPUART_WKSTS_RS485WKF_Pos (3) /*!< LPUART_T::WKSTS: RS485WKF Position */ 1099 #define LPUART_WKSTS_RS485WKF_Msk (0x1ul << LPUART_WKSTS_RS485WKF_Pos) /*!< LPUART_T::WKSTS: RS485WKF Mask */ 1100 1101 #define LPUART_WKSTS_TOUTWKF_Pos (4) /*!< LPUART_T::WKSTS: TOUTWKF Position */ 1102 #define LPUART_WKSTS_TOUTWKF_Msk (0x1ul << LPUART_WKSTS_TOUTWKF_Pos) /*!< LPUART_T::WKSTS: TOUTWKF Mask */ 1103 1104 #define LPUART_DWKCOMP_STCOMP_Pos (0) /*!< LPUART_T::DWKCOMP: STCOMP Position */ 1105 #define LPUART_DWKCOMP_STCOMP_Msk (0xfffful << LPUART_DWKCOMP_STCOMP_Pos) /*!< LPUART_T::DWKCOMP: STCOMP Mask */ 1106 1107 #define LPUART_RS485DD_RTSDDLY_Pos (0) /*!< LPUART_T::RS485DD: RTSDDLY Position */ 1108 #define LPUART_RS485DD_RTSDDLY_Msk (0xfffful << LPUART_RS485DD_RTSDDLY_Pos) /*!< LPUART_T::RS485DD: RTSDDLY Mask */ 1109 1110 #define LPUART_AUTOCTL_TRIGSEL_Pos (0) /*!< LPUART_T::AUTOCTL: TRIGSEL Position */ 1111 #define LPUART_AUTOCTL_TRIGSEL_Msk (0xful << LPUART_AUTOCTL_TRIGSEL_Pos) /*!< LPUART_T::AUTOCTL: TRIGSEL Mask */ 1112 1113 #define LPUART_AUTOCTL_TRIGEN_Pos (4) /*!< LPUART_T::AUTOCTL: TRIGEN Position */ 1114 #define LPUART_AUTOCTL_TRIGEN_Msk (0x1ul << LPUART_AUTOCTL_TRIGEN_Pos) /*!< LPUART_T::AUTOCTL: TRIGEN Mask */ 1115 1116 #define LPUART_AUTOCTL_CKAWOEN_Pos (5) /*!< LPUART_T::AUTOCTL: CKAWOEN Position */ 1117 #define LPUART_AUTOCTL_CKAWOEN_Msk (0x1ul << LPUART_AUTOCTL_CKAWOEN_Pos) /*!< LPUART_T::AUTOCTL: CKAWOEN Mask */ 1118 1119 #define LPUART_AUTOCTL_WKAOTOEN_Pos (8) /*!< LPUART_T::AUTOCTL: WKAOTOEN Position */ 1120 #define LPUART_AUTOCTL_WKAOTOEN_Msk (0x1ul << LPUART_AUTOCTL_WKAOTOEN_Pos) /*!< LPUART_T::AUTOCTL: WKAOTOEN Mask */ 1121 1122 #define LPUART_AUTOCTL_SWTRIG_Pos (9) /*!< LPUART_T::AUTOCTL: SWTRIG Position */ 1123 #define LPUART_AUTOCTL_SWTRIG_Msk (0x1ul << LPUART_AUTOCTL_SWTRIG_Pos) /*!< LPUART_T::AUTOCTL: SWTRIG Mask */ 1124 1125 #define LPUART_AUTOCTL_AOEN_Pos (31) /*!< LPUART_T::AUTOCTL: AOEN Position */ 1126 #define LPUART_AUTOCTL_AOEN_Msk (0x1ul << LPUART_AUTOCTL_AOEN_Pos) /*!< LPUART_T::AUTOCTL: AOEN Mask */ 1127 1128 #define LPUART_AUTOSTS_AOTOWKF_Pos (0) /*!< LPUART_T::AUTOSTS: AOTOWKF Position */ 1129 #define LPUART_AUTOSTS_AOTOWKF_Msk (0x1ul << LPUART_AUTOSTS_AOTOWKF_Pos) /*!< LPUART_T::AUTOSTS: AOTOWKF Mask */ 1130 1131 /**@}*/ /* LPUART_CONST */ 1132 /**@}*/ /* end of LPUART register group */ 1133 /**@}*/ /* end of REGISTER group */ 1134 1135 #if defined ( __CC_ARM ) 1136 #pragma no_anon_unions 1137 #endif 1138 1139 #endif /* __LPUART_REG_H__ */ 1140
