1 /*! 2 \file gd32l23x.h 3 \brief general definitions for GD32L23x 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_H 36 #define GD32L23X_H 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /* define GD32L23x */ 43 #if !defined (GD32L23x) 44 #define GD32L23x 45 #endif /* define GD32L23x */ 46 #if !defined (GD32L23x) 47 #error "Please select the target GD32L23x device used in your application (in gd32l23x.h file)" 48 #endif /* undefine GD32L23x tip */ 49 50 /* define value of high speed crystal oscillator (HXTAL) in Hz */ 51 #if !defined (HXTAL_VALUE) 52 #define HXTAL_VALUE ((uint32_t)8000000) 53 #endif /* high speed crystal oscillator value */ 54 55 /* define startup timeout value of high speed crystal oscillator (HXTAL) */ 56 #if !defined (HXTAL_STARTUP_TIMEOUT) 57 #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF) 58 #endif /* high speed crystal oscillator startup timeout */ 59 60 /* define value of internal 16MHz RC oscillator (IRC16M) in Hz */ 61 #if !defined (IRC16M_VALUE) 62 #define IRC16M_VALUE ((uint32_t)16000000) 63 #endif /* internal 16MHz RC oscillator value */ 64 65 /* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */ 66 #if !defined (IRC16M_STARTUP_TIMEOUT) 67 #define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500) 68 #endif /* internal 16MHz RC oscillator startup timeout */ 69 70 #if !defined (IRC48M_VALUE) 71 #define IRC48M_VALUE ((uint32_t)48000000) 72 #endif /* IRC48M_VALUE */ 73 74 /* define value of internal 32KHz RC oscillator(IRC32K) in Hz */ 75 #if !defined (IRC32K_VALUE) 76 #define IRC32K_VALUE ((uint32_t)32000) 77 #endif /* internal 32KHz RC oscillator value */ 78 79 /* define value of low speed crystal oscillator (LXTAL)in Hz */ 80 #if !defined (LXTAL_VALUE) 81 #define LXTAL_VALUE ((uint32_t)32768) 82 #endif /* low speed crystal oscillator value */ 83 84 /* GD32L23x firmware library version number V1.0 */ 85 #define __GD32L23X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ 86 #define __GD32L23X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ 87 #define __GD32L23X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ 88 #define __GD32L23X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 89 #define __GD32L23X_STDPERIPH_VERSION ((__GD32L23X_STDPERIPH_VERSION_MAIN << 24)\ 90 |(__GD32L23X_STDPERIPH_VERSION_SUB1 << 16)\ 91 |(__GD32L23X_STDPERIPH_VERSION_SUB2 << 8)\ 92 |(__GD32L23X_STDPERIPH_VERSION_RC)) 93 94 /* configuration of the Cortex-M23 processor and core peripherals */ 95 #define __CM23_REV 0x0100U /*!< Core revision r1p0 */ 96 #define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */ 97 #define __MPU_PRESENT 0U /*!< MPU is present */ 98 #define __VTOR_PRESENT 1U /*!< VTOR is present */ 99 #define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ 100 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 101 102 /* define interrupt number */ 103 typedef enum IRQn { 104 /* Cortex-M23 processor exceptions numbers */ 105 NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */ 106 HardFault_IRQn = -13, /*!< hardfault interrupt */ 107 108 SVCall_IRQn = -5, /*!< sv call interrupt */ 109 110 PendSV_IRQn = -2, /*!< pend sv interrupt */ 111 SysTick_IRQn = -1, /*!< system tick interrupt */ 112 /* interruput numbers */ 113 WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ 114 LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ 115 TAMPER_STAMP_IRQn = 2, /*!< RTC Tamper and TimeStamp interrupt */ 116 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt */ 117 FMC_IRQn = 4, /*!< FMC interrupt */ 118 RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ 119 EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */ 120 EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */ 121 EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */ 122 EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */ 123 EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */ 124 DMA_Channel0_IRQn = 11, /*!< DMA channel 0 interrupt */ 125 DMA_Channel1_IRQn = 12, /*!< DMA channel 1 interrupt */ 126 DMA_Channel2_IRQn = 13, /*!< DMA channel 2 interrupt */ 127 DMA_Channel3_IRQn = 14, /*!< DMA channel 3 interrupt */ 128 DMA_Channel4_IRQn = 15, /*!< DMA channel 4 interrupt */ 129 DMA_Channel5_IRQn = 16, /*!< DMA channel 5 interrupt */ 130 DMA_Channel6_IRQn = 17, /*!< DMA channel 6 interrupt */ 131 ADC_IRQn = 18, /*!< ADC interrupts */ 132 USBD_HP_IRQn = 19, /*!< USBD High Priority */ 133 USBD_LP_IRQn = 20, /*!< USBD Low Priority */ 134 TIMER1_IRQn = 21, /*!< TIMER1 interrupt */ 135 TIMER2_IRQn = 22, /*!< TIMER2 interrupt */ 136 TIMER8_IRQn = 23, /*!< TIMER8 interrupt */ 137 TIMER11_IRQn = 24, /*!< TIMER11 interrupt */ 138 TIMER5_IRQn = 25, /*!< TIMER5 interrupt */ 139 TIMER6_IRQn = 26, /*!< TIMER6 interrupt */ 140 USART0_IRQn = 27, /*!< USART0 interrupt */ 141 USART1_IRQn = 28, /*!< USART1 interrupt */ 142 UART3_IRQn = 29, /*!< UART3 interrupt */ 143 UART4_IRQn = 30, /*!< UART4 interrupt */ 144 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 145 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 146 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 147 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 148 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 149 SPI1_IRQn = 36, /*!< SPI1 interrupt */ 150 DAC_IRQn = 37, /*!< DAC interrupt */ 151 I2C2_EV_IRQn = 39, /*!< I2C2 event interrupt */ 152 I2C2_ER_IRQn = 40, /*!< I2C2 error interrupt */ 153 RTC_Alarm_IRQn = 41, /*!< RTC Alarm interrupt */ 154 USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ 155 EXTI5_9_IRQn = 43, /*!< EXTI line 5 to 9 interrupts */ 156 EXTI10_15_IRQn = 47, /*!< EXTI line 10 to 15 interrupts */ 157 DMAMUX_IRQn = 55, /*!< DMAMUX interrupt */ 158 CMP0_IRQn = 56, /*!< Comparator 0 interrupt */ 159 CMP1_IRQn = 57, /*!< Comparator 1 interrupt */ 160 I2C0_WKUP_IRQn = 58, /*!< I2C0 Wakeup interrupt */ 161 I2C2_WKUP_IRQn = 59, /*!< I2C2 Wakeup interrupt */ 162 USART0_WKUP_IRQn = 60, /*!< USART0 Wakeup interrupt */ 163 LPUART_IRQn = 61, /*!< LPUART global interrupt */ 164 CAU_IRQn = 62, /*!< CAU interrupt */ 165 TRNG_IRQn = 63, /*!< TRNG interrupt */ 166 SLCD_IRQn = 64, /*!< SLCD interrupt */ 167 USART1_WKUP_IRQn = 65, /*!< USART1 Wakeup interrupt */ 168 I2C1_WKUP_IRQn = 66, /*!< I2C1 Wakeup interrupt */ 169 LPUART_WKUP_IRQn = 67, /*!< LPUART Wakeup interrupt */ 170 LPTIMER_IRQn = 68, /*!< LPTIMER interrupt */ 171 } IRQn_Type; 172 173 /* includes */ 174 #include "core_cm23.h" 175 #include "system_gd32l23x.h" 176 #include <stdint.h> 177 178 /* enum definitions */ 179 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; 180 typedef enum {RESET = 0, SET = !RESET} FlagStatus; 181 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; 182 183 /* bit operations */ 184 #define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr)) 185 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) 186 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) 187 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) 188 #ifndef BIT 189 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) 190 #endif 191 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 192 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) 193 194 /* main flash and SRAM memory map */ 195 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ 196 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ 197 /* peripheral memory map */ 198 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ 199 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ 200 #define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ 201 #define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ 202 /* advanced peripheral bus 1 memory map */ 203 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ 204 #define SLCD_BASE (APB1_BUS_BASE + 0x00002400U) /*!< LCD base address */ 205 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ 206 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ 207 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ 208 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ 209 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ 210 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ 211 #define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ 212 #define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */ 213 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ 214 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ 215 #define LPUART_BASE (APB1_BUS_BASE + 0x00008000U) /*!< LPUART base address */ 216 #define LPTIMER_BASE (APB1_BUS_BASE + 0x00009400U) /*!< LPUART base address */ 217 #define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< LPUART base address */ 218 /* advanced peripheral bus 2 memory map */ 219 #define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ 220 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ 221 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ 222 #define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */ 223 /* advanced high performance bus 1 memory map */ 224 #define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ 225 #define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ 226 #define DMAMUX_BASE (AHB1_BUS_BASE + 0x00000800U) /*!< DMA base address */ 227 #define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ 228 #define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ 229 #define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ 230 /* advanced high performance bus 2 memory map */ 231 #define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ 232 #define CAU_BASE (AHB2_BUS_BASE + 0x08060000U) /*!< CAU base address */ 233 #define TRNG_BASE (AHB2_BUS_BASE + 0x08060800U) /*!< TRNG base address */ 234 /* option byte and debug memory map */ 235 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ 236 #define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */ 237 238 #define VREF_BASE ((uint32_t)0x40010030U) /*!< VREF base address */ 239 240 #include "gd32l23x_libopt.h" 241 242 #ifdef __cplusplus 243 } 244 #endif 245 246 #endif /* GD32L23X_H */ 247
