1 /**************************************************************************//** 2 * @file lptmr_reg.h 3 * @version V1.00 4 * @brief LPTMR register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __LPTMR_REG_H__ 10 #define __LPTMR_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup LPTMR Low Power Timer Controller (LPTMR) 23 Memory Mapped Structure for LPTMR Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var LPTMR_T::CTL 32 * Offset: 0x00 LPTMR0 Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[7:0] |PSC |Prescale Counter 37 * | | |Low Power Timer input clock or event source is divided by (PSC+1) before it is fed to the low power timer up counter 38 * | | |If this field is 0 (PSC = 0), then there is no scaling. 39 * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. 40 * |[15] |FUNCSEL |Function Selection 41 * | | |0 = Low Power Timer controller is used as timer function. 42 * | | |1 = Low Power Timer controller is used as PWM function. 43 * |[16] |PDCLKEN |Power-down Engine Clock Enable 44 * | | |0 = Disable engine clock in power-down mode. 45 * | | |1 = Enable engine clock in power-down mode. 46 * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit 47 * | | |0 = The behavior selection in periodic mode is Disabled. 48 * | | |When user updates CMPDAT while timer is running in periodic mode, 49 * | | |CNT will be reset to default value. 50 * | | |1 = The behavior selection in periodic mode is Enabled. 51 * | | |When user updates CMPDAT while timer is running in periodic mode, the limitations as bellows list, 52 * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. 53 * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. 54 * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. 55 * |[21] |TGLPINSEL |Toggle-output Pin Select 56 * | | |0 = Toggle mode output to LPTMRx (Low Power Timer Event Counter Pin). 57 * | | |1 = Toggle mode output to LPTMRx_EXT (Low Power Timer External Capture Pin). 58 * |[22] |CAPSRC |Capture Pin Source Selection 59 * | | |0 = Capture Function source is from LPTMRx_EXT (x= 0~1) pin. 60 * | | |1 = Capture Function source is from internal ACMP output signal 61 * | | |Note: When CAPSRC = 1,User can set INTERCAPSEL (LPTMRx_EXTCTL[10:8]) to decide which internal ACMP output signal or which clock is as timer capture source. 62 * |[23] |WKEN |Wake-up Function Enable Bit 63 * | | |If this bit is set to 1, while timer interrupt flag TIF (LPTMRx_INTSTS[0]) is 1 and INTEN (LPTMRx_CTL[29]) is enabled, the low power timer interrupt signal will generate a wake-up trigger event to CPU. 64 * | | |0 = Wake-up function Disabled if timer interrupt signal generated. 65 * | | |1 = Wake-up function Enabled if timer interrupt signal generated. 66 * |[24] |EXTCNTEN |Event Counter Mode Enable Bit 67 * | | |This bit is for external counting pin function enabled. 68 * | | |0 = Event counter mode Disabled. 69 * | | |1 = Event counter mode Enabled. 70 * | | |Note: When timer is used as an event counter, this bit should be set to 1. 71 * |[25] |ACTSTS |Low Power Timer Active Status Bit (Read Only) 72 * | | |This bit indicates the 24-bit up counter status. 73 * | | |0 = 24-bit up counter is not active. 74 * | | |1 = 24-bit up counter is active. 75 * | | |Note: This bit may active when CNT 0 transition to CNT 1. 76 * |[28:27] |OPMODE |Low Power Timer Counting Mode Select 77 * | | |00 = The low power timer controller is operated in One-shot mode. 78 * | | |01 = The low power timer controller is operated in Periodic mode. 79 * | | |10 = The low power timer controller is operated in Toggle-output mode. 80 * | | |11 = The low power timer controller is operated in Continuous Counting mode. 81 * |[29] |INTEN |Low Power Timer Interrupt Enable Bit 82 * | | |0 = Low Power Timer time-out interrupt Disabled. 83 * | | |1 = Low Power Timer time-out interrupt Enabled. 84 * | | |Note: If this bit is enabled, when the low power timer time-out interrupt flag TIF is set to 1, the low power timer interrupt signal is generated and inform to CPU. 85 * |[30] |CNTEN |Low Power Timer Counting Enable Bit 86 * | | |0 = Stops/Suspends counting. 87 * | | |1 = Starts counting. 88 * | | |Note 1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. 89 * | | |Note 2: This bit is auto-cleared by hardware in one-shot mode (LPTMR_CTL[28:27] = 00) when the low power timer time-out interrupt flag TIF (LPTMRx_INTSTS[0]) is generated. 90 * | | |Note 3: Set enable/disable this bit needs 2 * LPTMR_CLK period to become active, user can read ACTSTS (LPTMRx_CTL[25]) to check enable/disable command is completed or not. 91 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 92 * | | |0 = ICE debug mode acknowledgement effects TIMER counting. 93 * | | |TIMER counter will be held while CPU is held by ICE. 94 * | | |1 = ICE debug mode acknowledgement Disabled. 95 * | | |TIMER counter will keep going no matter CPU is held by ICE or not. 96 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 97 * @var LPTMR_T::CMP 98 * Offset: 0x04 LPTMR0 Comparator Register 99 * --------------------------------------------------------------------------------------------------- 100 * |Bits |Field |Descriptions 101 * | :----: | :----: | :---- | 102 * |[23:0] |CMPDAT |Low Power Timer Comparator Value 103 * | | |CMPDAT is a 24-bit compared value register 104 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (LPTMRx_INTSTS[0] Low Power Timer Interrupt Flag) will set to 1. 105 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). 106 * | | |Note 1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. 107 * | | |Note 2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field 108 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the low power timer compared value while user writes a new value into CMPDAT field. 109 * @var LPTMR_T::INTSTS 110 * Offset: 0x08 LPTMR0 Interrupt Status Register 111 * --------------------------------------------------------------------------------------------------- 112 * |Bits |Field |Descriptions 113 * | :----: | :----: | :---- | 114 * |[0] |TIF |Low Power Timer Interrupt Flag 115 * | | |This bit indicates the interrupt flag status of Low Power Timer while 24-bit timer up counter CNT (LPTMRx_CNT[23:0]) value reaches to CMPDAT (LPTMRx_CMP[23:0]) value. 116 * | | |0 = No effect. 117 * | | |1 = CNT value matches the CMPDAT value. 118 * | | |Note: This bit is cleared by writing 1 to it. 119 * |[1] |TWKF |Low Power Timer Wake-up Flag 120 * | | |This bit indicates the interrupt wake-up flag status of timer. 121 * | | |0 = Low Power Timer does not cause CPU wake-up. 122 * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. 123 * | | |Note: This bit is cleared by writing 1 to it. 124 * @var LPTMR_T::CNT 125 * Offset: 0x0C LPTMR0 Data Register 126 * --------------------------------------------------------------------------------------------------- 127 * |Bits |Field |Descriptions 128 * | :----: | :----: | :---- | 129 * |[23:0] |CNT |Low Power Timer Data Register 130 * | | |Read operation. 131 * | | |Read this register to get CNT value. For example: 132 * | | |If EXTCNTEN (LPTMRx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. 133 * | | |If EXTCNTEN (LPTMRx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. 134 * | | |Write operation. 135 * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. 136 * |[31] |RSTACT |Low Power Timer Data Register Reset Active (Read Only) 137 * | | |This bit indicates if the counter reset operation active. 138 * | | |When user writes this CNT register, low power timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter 139 * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress 140 * | | |Once the counter reset operation done, low power timer clear this bit to 0 automatically. 141 * | | |0 = Reset operation is done. 142 * | | |1 = Reset operation triggered by writing LPTMRx_CNT is in progress. 143 * @var LPTMR_T::CAP 144 * Offset: 0x10 LPTMR0 Capture Data Register 145 * --------------------------------------------------------------------------------------------------- 146 * |Bits |Field |Descriptions 147 * | :----: | :----: | :---- | 148 * |[23:0] |CAPDAT |Low Power Timer Capture Data Register 149 * | | |When CAPEN (LPTMRx_EXTCTL[3]) bit is set, CAPFUNCS (LPTMRx_EXTCTL[4]) bit is 0, and a transition on LPTMRx_EXT pin matched the CAPEDGE (LPTMRx_EXTCTL[14:12]) setting, CAPIF (LPTMRx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (LPTMRx_CNT[23:0]) will be auto-loaded into this CAPDAT field. 150 * @var LPTMR_T::EXTCTL 151 * Offset: 0x14 LPTMR0 External Control Register 152 * --------------------------------------------------------------------------------------------------- 153 * |Bits |Field |Descriptions 154 * | :----: | :----: | :---- | 155 * |[0] |CNTPHASE |Low Power Timer External Count Phase 156 * | | |This bit indicates the detection phase of external counting pin LPTMRx (x= 0~1). 157 * | | |0 = A falling edge of external counting pin will be counted. 158 * | | |1 = A rising edge of external counting pin will be counted. 159 * |[3] |CAPEN |Low Power Timer Capture Enable Bit 160 * | | |This bit enables the capture input function. 161 * | | |0 =Capture source Disabled. 162 * | | |1 =Capture source Enabled. 163 * | | |Note: When CAPEN is 1, user can set INTERCAPSEL (LPTMRx_EXTCTL [10:8]) to select capture source. 164 * |[4] |CAPFUNCS |Capture Function Selection 165 * | | |0 = External Capture Mode Enabled. 166 * | | |1 = External Reset Mode Enabled. 167 * | | |Note 1: When CAPFUNCS is 0, transition on LPTMRx_EXT (x= 0~1) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. 168 * | | |Note 2: When CAPFUNCS is 1, transition on LPTMRx_EXT (x= 0~1) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. 169 * |[5] |CAPIEN |Low Power Timer External Capture Interrupt Enable Bit 170 * | | |0 = LPTMRx_EXT (x= 0~1) pin, ACMP, internal clock, or external clock detection Interrupt Disabled. 171 * | | |1 = LPTMRx_EXT (x= 0~1) pin, ACMP, internal clock, or external clock detection Interrupt Enabled. 172 * | | |Note: CAPIEN is used to enable timer external interrupt 173 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (LPTMRx_EINTSTS[0]) is 1. 174 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the LPTMRx_EXT (x= 0~1) pin, ACMP, internal clock, or external clock will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. 175 * |[6] |CAPDBEN |Low Power Timer External Capture Pin De-bounce Enable Bit 176 * | | |0 = LPTMRx_EXT (x= 0~1) pin de-bounce or ACMP output de-bounce Disabled. 177 * | | |1 = LPTMRx_EXT (x= 0~1) pin de-bounce or ACMP output de-bounce Enabled. 178 * | | |Note: If this bit is enabled, the edge detection of LPTMRx_EXT pin or ACMP output is detected with de-bounce circuit. 179 * |[7] |CNTDBEN |Low Power Timer Counter Pin De-bounce Enable Bit 180 * | | |0 = LPTMRx (x= 0~1) pin de-bounce Disabled. 181 * | | |1 = LPTMRx (x= 0~1) pin de-bounce Enabled. 182 * | | |Note: If this bit is enabled, the edge detection of LPTMRx pin is detected with de-bounce circuit. 183 * |[10:8] |INTERCAPSEL|Internal Capture Source Select 184 * | | |000 = Capture Function source is from internal ACMP0 output signal. 185 * | | |001 = Capture Function source is from internal ACMP1 output signal. 186 * | | |111 = Capture Function source is from internal ACMP2 output signal.. 187 * | | |Note: these bits only available when CAPSRC (LPTMRx_CTL[22]) is 1. 188 * |[14:12] |CAPEDGE |Low Power Timer External Capture Pin Edge Detect 189 * | | |When first capture event is generated, the CNT (LPTMRx_CNT[23:0]) will be reset to 0 and first CAPDAT (LPTMRx_CAP[23:0]) should be to 0. 190 * | | |000 = Capture event occurred when detect falling edge transfer on LPTMRx_EXT (x= 0~1) pin. 191 * | | |001 = Capture event occurred when detect rising edge transfer on LPTMRx_EXT (x= 0~1) pin. 192 * | | |010 = Capture event occurred when detect both falling and rising edge transfer on LPTMRx_EXT (x= 0~1) pin, and first capture event occurred at falling edge transfer. 193 * | | |011 = Capture event occurred when detect both rising and falling edge transfer on LPTMRx_EXT (x= 0~1) pin, and first capture event occurred at rising edge transfer. 194 * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on LPTMRx_EXT (x= 0~1) pin. 195 * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on LPTMRx_EXT (x= 0~1) pin. 196 * | | |100, 101 = Reserved. 197 * | | |Note: Set CAPSRC (LPTMRx_CTL[22]) and INTERCAPSEL (LPTMRx_EXTCTL[10:8]) to select capture source. 198 * |[18:16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function 199 * | | |000 = Event Counter input source is from external LPTMRx (x= 0~1) pin. 200 * | | |010 = Event Counter input source is from internal ACMP0 output signal. 201 * | | |011 = Event Counter input source is from internal ACMP1 output signal. 202 * | | |100 = Event Counter input source is from internal ACMP2 output signal. 203 * | | |101~111 = Reserved. 204 * |[31:28] |CAPDIVSCL |Low Power Timer Capture Source Divider Scale 205 * | | |This bits indicate the divide scale for capture source divider 206 * | | |0000 = Capture source/1. 207 * | | |0001 = Capture source/2. 208 * | | |0010 = Capture source/4. 209 * | | |0011 = Capture source/8. 210 * | | |0100 = Capture source/16. 211 * | | |0101 = Capture source/32. 212 * | | |0110 = Capture source/64. 213 * | | |0111 = Capture source/128. 214 * | | |1000 = Capture source/256. 215 * | | |1001~1111 = Reserved. 216 * | | |Note: Set INTERCAPSEL (LPTMRx_EXTCTL[10:8]) and CAPSRC (LPTMRx_CTL[22]) to select capture source. 217 * @var LPTMR_T::EINTSTS 218 * Offset: 0x18 LPTMR0 External Interrupt Status Register 219 * --------------------------------------------------------------------------------------------------- 220 * |Bits |Field |Descriptions 221 * | :----: | :----: | :---- | 222 * |[0] |CAPIF |Low Power Timer External Capture Interrupt Flag 223 * | | |This bit indicates the low power timer external capture interrupt flag status. 224 * | | |0 = LPTMRx_EXT (x= 0~1) pin, ACMP, internal clock, or external clock interrupt did not occur. 225 * | | |1 = LPTMRx_EXT (x= 0~1) pin, ACMP, internal clock, or external clock interrupt occurred. 226 * | | |Note 1: This bit is cleared by writing 1 to it. 227 * | | |Note 2: When CAPEN (LPTMRx_EXTCTL[3]) bit is set, CAPFUNCS (LPTMRx_EXTCTL[4]) bit is 0, and a transition on LPTMRx_EXT (x= 0~1) pin, ACMP, internal clock, or external clock matched the CAPEDGE (LPTMRx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. 228 * | | |Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status 229 * | | |If the above condition occurred, the Low Power Timer will keep register LPTMRx_CAP unchanged and drop the new capture value. 230 * |[1] |CAPIFOV |Capture Latch Interrupt Flag Overrun Status (Read Only) 231 * | | |0 = Capture latch happened when the corresponding CAPIF is 0. 232 * | | |1 = Capture latch happened when the corresponding CAPIF is 1. 233 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPIF. 234 * @var LPTMR_T::TRGCTL 235 * Offset: 0x1C LPTMR0 Trigger Control Register 236 * --------------------------------------------------------------------------------------------------- 237 * |Bits |Field |Descriptions 238 * | :----: | :----: | :---- | 239 * |[0] |TRGSSEL |Trigger Source Select Bit 240 * | | |This bit is used to select internal trigger source is from timer time-out interrupt signal or capture interrupt signal. 241 * | | |0 = Time-out interrupt signal is used to internal trigger LPADC0, , LPI2C0, LPSPI0, LPUART, , and LPPDMA. 242 * | | |1 = Capture interrupt signal is used to internal trigger LPADC0, LPI2C0, LPSPI0, LPUART, , and LPPDMA. 243 * |[1] |TRGEN |Trigger Low power IPs Enable Bit 244 * | | |If this bit is set to 1, each timer time-out event or capture event can trigger Low Power IPs. 245 * | | |0 = Low Power Timer interrupt trigger Low Power IPs Disabled. 246 * | | |1 = Low Power Timer interrupt trigger Low Power IPs Enabled. 247 * | | |Note: If TRGSSEL (LPTMRx_TRGCTL[0]) = 0, time-out interrupt signal will trigger Low Power IPs conversion. 248 * | | |Note: If TRGSSEL (LPTMRx_TRGCTL[0]) = 1, capture interrupt signal will trigger Low Power IPs conversion. 249 * |[4] |TRGLPPDMA |Trigger LPPDMA Enable Bit 250 * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered LPPDMA transfer. 251 * | | |0 = Low Power Timer interrupt trigger LPPDMA Disabled. 252 * | | |1 = Low Power Timer interrupt trigger LPPDMA Enabled. 253 * | | |Note: If TRGSSEL (LPTMRx_TRGCTL[0]) = 0, time-out interrupt signal will trigger LPPDMA transfer. 254 * | | |Note: If TRGSSEL (LPTMRx_TRGCTL[0]) = 1, capture interrupt signal will trigger LPPDMA transfer. 255 * @var LPTMR_T::CAPNF 256 * Offset: 0x24 LPTMR0 Capture Input Noise Filter Register 257 * --------------------------------------------------------------------------------------------------- 258 * |Bits |Field |Descriptions 259 * | :----: | :----: | :---- | 260 * |[0] |CAPNFEN |Capture Noise Filter Enable 261 * | | |0 = Capture Noise Filter function Disabled. 262 * | | |1 = Capture Noise Filter function Enabled. 263 * |[6:4] |CAPNFSEL |Capture Edge Detector Noise Filter Clock Selection 264 * | | |000 = Noise filter clock is ECLKx. 265 * | | |001 = Noise filter clock is ECLKx/2. 266 * | | |010 = Noise filter clock is ECLKx/4. 267 * | | |011 = Noise filter clock is ECLKx/8. 268 * | | |100 = Noise filter clock is ECLKx/16. 269 * | | |101 = Noise filter clock is ECLKx/32. 270 * | | |110 = Noise filter clock is ECLKx/64. 271 * | | |111 = Noise filter clock is ECLKx/128. 272 * |[10:8] |CAPNFCNT |Capture Edge Detector Noise Filter Count 273 * | | |These bits control the capture filter counter to count from 0 to CAPNFCNT. 274 * @var LPTMR_T::PWMCTL 275 * Offset: 0x40 LPTMR0 PWM Control Register 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[0] |CNTEN |PWM Counter Enable Bit 280 * | | |0 = PWM counter and clock prescale Stop Running. 281 * | | |1 = PWM counter and clock prescale Start Running. 282 * |[3] |CNTMODE |PWM Counter Mode 283 * | | |0 = Auto-reload mode. 284 * | | |1 = One-shot mode. 285 * |[12] |PWMINTWKEN|PWM Interrupt Wake-up Enable Bit 286 * | | |If PWM interrupt occurs when chip is in Power-down mode, PWMINTWKEN can determine whether chip wake-up occurs or not. 287 * | | |0 = PWM interrupt wake-up Disabled. 288 * | | |1 = PWM interrupt wake-up Enabled. 289 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 290 * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. 291 * | | |0 = ICE debug mode counter halt Disabled. 292 * | | |1 = ICE debug mode counter halt Enabled. 293 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL control register. 294 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) 295 * | | |0 = ICE debug mode acknowledgement effects PWM output. 296 * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. 297 * | | |1 = ICE debug mode acknowledgement disabled. 298 * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. 299 * | | |Note: This bit is write protected. Refer to SYS_REGLCTL control register. 300 * @var LPTMR_T::PWMCLKPSC 301 * Offset: 0x44 LPTMR0 PWM Counter Clock Pre-scale Register 302 * --------------------------------------------------------------------------------------------------- 303 * |Bits |Field |Descriptions 304 * | :----: | :----: | :---- | 305 * |[7:0] |CLKPSC |PWM Counter Clock Pre-scale 306 * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) 307 * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. 308 * @var LPTMR_T::PWMCNTCLR 309 * Offset: 0x48 LPTMR0 PWM Clear Counter Register 310 * --------------------------------------------------------------------------------------------------- 311 * |Bits |Field |Descriptions 312 * | :----: | :----: | :---- | 313 * |[0] |CNTCLR |Clear PWM Counter Control Bit 314 * | | |It is automatically cleared by hardware. 315 * | | |0 = No effect. 316 * | | |1 = Clear 16-bit PWM counter to 0x0000 in up count type. 317 * @var LPTMR_T::PWMPERIOD 318 * Offset: 0x4C LPTMR0 PWM Period Register 319 * --------------------------------------------------------------------------------------------------- 320 * |Bits |Field |Descriptions 321 * | :----: | :----: | :---- | 322 * |[15:0] |PERIOD |PWM Period Register 323 * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. 324 * | | |In up count type: 325 * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * LPTMRx_PWMCLK. 326 * @var LPTMR_T::PWMCMPDAT 327 * Offset: 0x50 LPTMR0 PWM Comparator Register 328 * --------------------------------------------------------------------------------------------------- 329 * |Bits |Field |Descriptions 330 * | :----: | :----: | :---- | 331 * |[15:0] |CMP |PWM Comparator Register 332 * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC start conversion. 333 * @var LPTMR_T::PWMCNT 334 * Offset: 0x54 LPTMR0 PWM Counter Register 335 * --------------------------------------------------------------------------------------------------- 336 * |Bits |Field |Descriptions 337 * | :----: | :----: | :---- | 338 * |[15:0] |CNT |PWM Counter Value Register (Read Only) 339 * | | |User can monitor CNT to know the current counter value in 16-bit period counter. 340 * @var LPTMR_T::PWMPOLCTL 341 * Offset: 0x58 LPTMR0 PWM Pin Output Polar Control Register 342 * --------------------------------------------------------------------------------------------------- 343 * |Bits |Field |Descriptions 344 * | :----: | :----: | :---- | 345 * |[0] |PINV |PWMx Output Pin Polar Control Bit 346 * | | |The bit is used to control polarity state of PWMx_OUT pin. 347 * | | |0 = PWMx_OUT pin polar inverse Disabled. 348 * | | |1 = PWMx_OUT polar inverse Enabled. 349 * | | |Note: Set POSEL (LPTMRx_PWMPOCTL[8]) to select LPTMRx or LPTMRx_EXT as PWMx output pin. 350 * @var LPTMR_T::PWMPOCTL 351 * Offset: 0x5C LPTMR0 PWM Pin Output Control Register 352 * --------------------------------------------------------------------------------------------------- 353 * |Bits |Field |Descriptions 354 * | :----: | :----: | :---- | 355 * |[0] |POEN |PWMx Output Pin Enable Bit 356 * | | |0 = PWMx_OUT pin at tri-state mode. 357 * | | |1 = PWMx_OUT pin in output mode. 358 * | | |Note: Set POSEL (LPTMRx_PWMPOCTL[8]) to select LPTMRx or LPTMRx_EXT as PWMx output pin. 359 * |[8] |POSEL |PWM Output Pin Select 360 * | | |0 = PWMx_OUT pin is LPTMRx. 361 * | | |1 = PWMx_OUT pin is LPTMRx_EXT. 362 * @var LPTMR_T::PWMINTEN0 363 * Offset: 0x60 LPTMR0 PWM Interrupt Enable Register 0 364 * --------------------------------------------------------------------------------------------------- 365 * |Bits |Field |Descriptions 366 * | :----: | :----: | :---- | 367 * |[1] |PIEN |PWM Period Point Interrupt Enable Bit 368 * | | |0 = Period point interrupt Disabled. 369 * | | |1 = Period point interrupt Enabled. 370 * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit 371 * | | |0 = Compare up count interrupt Disabled. 372 * | | |1 = Compare up count interrupt Enabled. 373 * @var LPTMR_T::PWMINTSTS0 374 * Offset: 0x64 LPTMR0 PWM Interrupt Status Register 0 375 * --------------------------------------------------------------------------------------------------- 376 * |Bits |Field |Descriptions 377 * | :----: | :----: | :---- | 378 * |[1] |PIF |PWM Period Point Interrupt Flag 379 * | | |This bit is set by hardware when LPTMRx_PWM counter reaches PERIOD. 380 * | | |Note: This bit is cleared by writing 1 to it. 381 * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag 382 * | | |This bit is set by hardware when LPTMRx_PWM counter in up count direction and reaches CMP. 383 * | | |Note: If CMP equal to PERIOD, there is no CMPUIF flag in up count type 384 * | | |Note 2: This bit is cleared by writing 1 to it. 385 * @var LPTMR_T::PWMTRGCTL 386 * Offset: 0x68 LPTMR0 PWM Trigger Control Register 387 * --------------------------------------------------------------------------------------------------- 388 * |Bits |Field |Descriptions 389 * | :----: | :----: | :---- | 390 * |[1:0] |TRGSEL |PWM Counter Event Source Select to Trigger Conversion 391 * | | |00 = Trigger conversion at period point (PIF). 392 * | | |01 = Trigger conversion at compare up count point (CMPUIF). 393 * | | |10 = Trigger conversion at period or compare up count point (PIF or CMPUIF). 394 * | | |11 = Reserved. 395 * |[2] |TRGEN |Trigger Low power IPs Enable Bit 396 * | | |f this bit is set to 1, each timer time-out event or capture event can trigger Low Power IP. 397 * | | |0 = Low Power Timer PWM counter event trigger Low Power IPs Disabled. 398 * | | |1 = Low Power Timer PWM counter event trigger Low Power IPs Enabled. 399 * |[9] |PWMTRGLPPDMA|PWM Counter Event Trigger LPPDMA Conversion Enable Bit 400 * | | |If this bit is set to 1, PWM can trigger LPPDMA conversion. 401 * | | |0 = PWM trigger LPPDMA Disabled. 402 * | | |1 = PWM trigger LPPDMA Enabled. 403 * | | |Note: Set TRGSEL (LPTMRx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. 404 * | | |Note: TRGEN (LPTMRx_PWMTRGCTL[2]) is needed to be set to 1. 405 * @var LPTMR_T::PWMSTATUS 406 * Offset: 0x6C LPTMR0 PWM Status Register 407 * --------------------------------------------------------------------------------------------------- 408 * |Bits |Field |Descriptions 409 * | :----: | :----: | :---- | 410 * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag 411 * | | |0 = The PWM counter value never reached its maximum value 0xFFFF. 412 * | | |1 = The PWM counter value has reached its maximum value. 413 * | | |Note: This bit is cleared by writing 1 to it. 414 * |[8] |PWMINTWKF |PWM Interrupt Wake-up Flag 415 * | | |0 = PWM interrupt wake-up has not occurred. 416 * | | |1 = PWM interrupt wake-up has occurred. 417 * | | |Note: This bit is cleared by writing 1 to it. 418 * @var LPTMR_T::PWMPBUF 419 * Offset: 0x70 LPTMR0 PWM Period Buffer Register 420 * --------------------------------------------------------------------------------------------------- 421 * |Bits |Field |Descriptions 422 * | :----: | :----: | :---- | 423 * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) 424 * | | |Used as PERIOD active register. 425 * @var LPTMR_T::PWMCMPBUF 426 * Offset: 0x74 LPTMR0 PWM Comparator Buffer Register 427 * --------------------------------------------------------------------------------------------------- 428 * |Bits |Field |Descriptions 429 * | :----: | :----: | :---- | 430 * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) 431 * | | |Used as CMP active register. 432 * @var LPTMR_T::PWMIFA 433 * Offset: 0xA8 LPTMR0 PWM Interrupt Flag Accumulator Register 434 * --------------------------------------------------------------------------------------------------- 435 * |Bits |Field |Descriptions 436 * | :----: | :----: | :---- | 437 * |[15:0] |IFACNT |PWM Interrupt Flag Accumulator Counter 438 * | | |This field sets the count number which defines (IFACNT+1) times of specify PWM interrupt occurs to set IFAIF bit to request the PWM accumulator interrupt. 439 * | | |PWM accumulator flag (IFAIF) will be set in every (IFACNT+1) times during the the PWM counter operation. 440 * |[24] |STPMOD |PWM Accumulator Stop Mode Enable Bit 441 * | | |0 = PWM interrupt accumulator event to stop counting Disabled. 442 * | | |1 = PWM interrupt accumulator event to stop counting Enabled. 443 * |[29:28] |IFASEL |PWM Interrupt Flag Accumulator Source Select 444 * | | |01 = Accumulate at each PWM period point. 445 * | | |10 = Accumulate at each PWM up-count compared point. 446 * |[31] |IFAEN |PWM Interrupt Flag Accumulator Enable Bit 447 * | | |0 = PWM interrupt flag accumulator function Disabled. 448 * | | |1 = PWM interrupt flag accumulator function Enabled. 449 * @var LPTMR_T::PWMAINTSTS 450 * Offset: 0xAC LPTMR0 PWM Accumulator Interrupt Flag Register 451 * --------------------------------------------------------------------------------------------------- 452 * |Bits |Field |Descriptions 453 * | :----: | :----: | :---- | 454 * |[0] |IFAIF |PWM Interrupt Flag Accumulator Interrupt Flag 455 * | | |This bit is set by hardware when the accumulator value reaches (IFACNT+1) 456 * | | |Note 1: This bit is cleared by writing 1 to it. 457 * | | |Note 2: If APDMAEN (LPTMRx_PWMAPDMACTL[0]) is set, this bit will be auto clear after PDMA transfer done. 458 * @var LPTMR_T::PWMAINTEN 459 * Offset: 0xB0 LPTMR0 PWM Accumulator Interrupt Enable Register 460 * --------------------------------------------------------------------------------------------------- 461 * |Bits |Field |Descriptions 462 * | :----: | :----: | :---- | 463 * |[0] |IFAIEN |PWM Interrupt Flag Accumulator Interrupt Enable Bit 464 * | | |0 = Interrupt Flag Accumulator interrupt Disabled. 465 * | | |1 = Interrupt Flag Accumulator interrupt Enabled. 466 * @var LPTMR_T::PWMAPDMACTL 467 * Offset: 0xB4 LPTMR0 PWM Accumulator LPPDMA Control Register 468 * --------------------------------------------------------------------------------------------------- 469 * |Bits |Field |Descriptions 470 * | :----: | :----: | :---- | 471 * |[0] |APDMAEN |PWM Accumulator LPPDMA Enable Bit 472 * | | |0 = PWM interrupt accumulator event to trigger LPPDMA transfer Disabled. 473 * | | |1 = PWM interrupt accumulator event to trigger LPPDMA transfer Enabled. 474 */ 475 __IO uint32_t CTL; /*!< [0x0000] LPTMR0 Control Register */ 476 __IO uint32_t CMP; /*!< [0x0004] LPTMR0 Comparator Register */ 477 __IO uint32_t INTSTS; /*!< [0x0008] LPTMR0 Interrupt Status Register */ 478 __IO uint32_t CNT; /*!< [0x000c] LPTMR0 Data Register */ 479 __I uint32_t CAP; /*!< [0x0010] LPTMR0 Capture Data Register */ 480 __IO uint32_t EXTCTL; /*!< [0x0014] LPTMR0 External Control Register */ 481 __IO uint32_t EINTSTS; /*!< [0x0018] LPTMR0 External Interrupt Status Register */ 482 __IO uint32_t TRGCTL; /*!< [0x001c] LPTMR0 Trigger Control Register */ 483 __I uint32_t RESERVE0[1]; 484 __IO uint32_t CAPNF; /*!< [0x0024] LPTMR0 Capture Input Noise Filter Register */ 485 __I uint32_t RESERVE1[6]; 486 __IO uint32_t PWMCTL; /*!< [0x0040] LPTMR0 PWM Control Register */ 487 __IO uint32_t PWMCLKPSC; /*!< [0x0044] LPTMR0 PWM Counter Clock Pre-scale Register */ 488 __IO uint32_t PWMCNTCLR; /*!< [0x0048] LPTMR0 PWM Clear Counter Register */ 489 __IO uint32_t PWMPERIOD; /*!< [0x004c] LPTMR0 PWM Period Register */ 490 __IO uint32_t PWMCMPDAT; /*!< [0x0050] LPTMR0 PWM Comparator Register */ 491 __I uint32_t PWMCNT; /*!< [0x0054] LPTMR0 PWM Counter Register */ 492 __IO uint32_t PWMPOLCTL; /*!< [0x0058] LPTMR0 PWM Pin Output Polar Control Register */ 493 __IO uint32_t PWMPOCTL; /*!< [0x005c] LPTMR0 PWM Pin Output Control Register */ 494 __IO uint32_t PWMINTEN0; /*!< [0x0060] LPTMR0 PWM Interrupt Enable Register 0 */ 495 __IO uint32_t PWMINTSTS0; /*!< [0x0064] LPTMR0 PWM Interrupt Status Register 0 */ 496 __IO uint32_t PWMTRGCTL; /*!< [0x0068] LPTMR0 PWM Trigger Control Register */ 497 __IO uint32_t PWMSTATUS; /*!< [0x006c] LPTMR0 PWM Status Register */ 498 __I uint32_t PWMPBUF; /*!< [0x0070] LPTMR0 PWM Period Buffer Register */ 499 __I uint32_t PWMCMPBUF; /*!< [0x0074] LPTMR0 PWM Comparator Buffer Register */ 500 __I uint32_t RESERVE2[12]; 501 __IO uint32_t PWMIFA; /*!< [0x00a8] LPTMR0 PWM Interrupt Flag Accumulator Register */ 502 __IO uint32_t PWMAINTSTS; /*!< [0x00ac] LPTMR0 PWM Accumulator Interrupt Flag Register */ 503 __IO uint32_t PWMAINTEN; /*!< [0x00b0] LPTMR0 PWM Accumulator Interrupt Enable Register */ 504 __IO uint32_t PWMAPDMACTL; /*!< [0x00b4] LPTMR0 PWM Accumulator LPPDMA Control Register */ 505 } LPTMR_T; 506 507 /** 508 @addtogroup LPTMR_CONST LPTMR Bit Field Definition 509 Constant Definitions for LPTMR Controller 510 @{ */ 511 512 #define LPTMR_CTL_PSC_Pos (0) /*!< LPTMR_T::CTL: PSC Position */ 513 #define LPTMR_CTL_PSC_Msk (0xfful << LPTMR_CTL_PSC_Pos) /*!< LPTMR_T::CTL: PSC Mask */ 514 515 #define LPTMR_CTL_FUNCSEL_Pos (15) /*!< LPTMR_T::CTL: FUNCSEL Position */ 516 #define LPTMR_CTL_FUNCSEL_Msk (0x1ul << LPTMR_CTL_FUNCSEL_Pos) /*!< LPTMR_T::CTL: FUNCSEL Mask */ 517 518 #define LPTMR_CTL_PDCLKEN_Pos (16) /*!< LPTMR_T::CTL: PDCLKEN Position */ 519 #define LPTMR_CTL_PDCLKEN_Msk (0x1ul << LPTMR_CTL_PDCLKEN_Pos) /*!< LPTMR_T::CTL: PDCLKEN Mask */ 520 521 #define LPTMR_CTL_PERIOSEL_Pos (20) /*!< LPTMR_T::CTL: PERIOSEL Position */ 522 #define LPTMR_CTL_PERIOSEL_Msk (0x1ul << LPTMR_CTL_PERIOSEL_Pos) /*!< LPTMR_T::CTL: PERIOSEL Mask */ 523 524 #define LPTMR_CTL_TGLPINSEL_Pos (21) /*!< LPTMR_T::CTL: TGLPINSEL Position */ 525 #define LPTMR_CTL_TGLPINSEL_Msk (0x1ul << LPTMR_CTL_TGLPINSEL_Pos) /*!< LPTMR_T::CTL: TGLPINSEL Mask */ 526 527 #define LPTMR_CTL_CAPSRC_Pos (22) /*!< LPTMR_T::CTL: CAPSRC Position */ 528 #define LPTMR_CTL_CAPSRC_Msk (0x1ul << LPTMR_CTL_CAPSRC_Pos) /*!< LPTMR_T::CTL: CAPSRC Mask */ 529 530 #define LPTMR_CTL_WKEN_Pos (23) /*!< LPTMR_T::CTL: WKEN Position */ 531 #define LPTMR_CTL_WKEN_Msk (0x1ul << LPTMR_CTL_WKEN_Pos) /*!< LPTMR_T::CTL: WKEN Mask */ 532 533 #define LPTMR_CTL_EXTCNTEN_Pos (24) /*!< LPTMR_T::CTL: EXTCNTEN Position */ 534 #define LPTMR_CTL_EXTCNTEN_Msk (0x1ul << LPTMR_CTL_EXTCNTEN_Pos) /*!< LPTMR_T::CTL: EXTCNTEN Mask */ 535 536 #define LPTMR_CTL_ACTSTS_Pos (25) /*!< LPTMR_T::CTL: ACTSTS Position */ 537 #define LPTMR_CTL_ACTSTS_Msk (0x1ul << LPTMR_CTL_ACTSTS_Pos) /*!< LPTMR_T::CTL: ACTSTS Mask */ 538 539 #define LPTMR_CTL_OPMODE_Pos (27) /*!< LPTMR_T::CTL: OPMODE Position */ 540 #define LPTMR_CTL_OPMODE_Msk (0x3ul << LPTMR_CTL_OPMODE_Pos) /*!< LPTMR_T::CTL: OPMODE Mask */ 541 542 #define LPTMR_CTL_INTEN_Pos (29) /*!< LPTMR_T::CTL: INTEN Position */ 543 #define LPTMR_CTL_INTEN_Msk (0x1ul << LPTMR_CTL_INTEN_Pos) /*!< LPTMR_T::CTL: INTEN Mask */ 544 545 #define LPTMR_CTL_CNTEN_Pos (30) /*!< LPTMR_T::CTL: CNTEN Position */ 546 #define LPTMR_CTL_CNTEN_Msk (0x1ul << LPTMR_CTL_CNTEN_Pos) /*!< LPTMR_T::CTL: CNTEN Mask */ 547 548 #define LPTMR_CTL_ICEDEBUG_Pos (31) /*!< LPTMR_T::CTL: ICEDEBUG Position */ 549 #define LPTMR_CTL_ICEDEBUG_Msk (0x1ul << LPTMR_CTL_ICEDEBUG_Pos) /*!< LPTMR_T::CTL: ICEDEBUG Mask */ 550 551 #define LPTMR_CMP_CMPDAT_Pos (0) /*!< LPTMR_T::CMP: CMPDAT Position */ 552 #define LPTMR_CMP_CMPDAT_Msk (0xfffffful << LPTMR_CMP_CMPDAT_Pos) /*!< LPTMR_T::CMP: CMPDAT Mask */ 553 554 #define LPTMR_INTSTS_TIF_Pos (0) /*!< LPTMR_T::INTSTS: TIF Position */ 555 #define LPTMR_INTSTS_TIF_Msk (0x1ul << LPTMR_INTSTS_TIF_Pos) /*!< LPTMR_T::INTSTS: TIF Mask */ 556 557 #define LPTMR_INTSTS_TWKF_Pos (1) /*!< LPTMR_T::INTSTS: TWKF Position */ 558 #define LPTMR_INTSTS_TWKF_Msk (0x1ul << LPTMR_INTSTS_TWKF_Pos) /*!< LPTMR_T::INTSTS: TWKF Mask */ 559 560 #define LPTMR_CNT_CNT_Pos (0) /*!< LPTMR_T::CNT: CNT Position */ 561 #define LPTMR_CNT_CNT_Msk (0xfffffful << LPTMR_CNT_CNT_Pos) /*!< LPTMR_T::CNT: CNT Mask */ 562 563 #define LPTMR_CNT_RSTACT_Pos (31) /*!< LPTMR_T::CNT: RSTACT Position */ 564 #define LPTMR_CNT_RSTACT_Msk (0x1ul << LPTMR_CNT_RSTACT_Pos) /*!< LPTMR_T::CNT: RSTACT Mask */ 565 566 #define LPTMR_CAP_CAPDAT_Pos (0) /*!< LPTMR_T::CAP: CAPDAT Position */ 567 #define LPTMR_CAP_CAPDAT_Msk (0xfffffful << LPTMR_CAP_CAPDAT_Pos) /*!< LPTMR_T::CAP: CAPDAT Mask */ 568 569 #define LPTMR_EXTCTL_CNTPHASE_Pos (0) /*!< LPTMR_T::EXTCTL: CNTPHASE Position */ 570 #define LPTMR_EXTCTL_CNTPHASE_Msk (0x1ul << LPTMR_EXTCTL_CNTPHASE_Pos) /*!< LPTMR_T::EXTCTL: CNTPHASE Mask */ 571 572 #define LPTMR_EXTCTL_CAPEN_Pos (3) /*!< LPTMR_T::EXTCTL: CAPEN Position */ 573 #define LPTMR_EXTCTL_CAPEN_Msk (0x1ul << LPTMR_EXTCTL_CAPEN_Pos) /*!< LPTMR_T::EXTCTL: CAPEN Mask */ 574 575 #define LPTMR_EXTCTL_CAPFUNCS_Pos (4) /*!< LPTMR_T::EXTCTL: CAPFUNCS Position */ 576 #define LPTMR_EXTCTL_CAPFUNCS_Msk (0x1ul << LPTMR_EXTCTL_CAPFUNCS_Pos) /*!< LPTMR_T::EXTCTL: CAPFUNCS Mask */ 577 578 #define LPTMR_EXTCTL_CAPIEN_Pos (5) /*!< LPTMR_T::EXTCTL: CAPIEN Position */ 579 #define LPTMR_EXTCTL_CAPIEN_Msk (0x1ul << LPTMR_EXTCTL_CAPIEN_Pos) /*!< LPTMR_T::EXTCTL: CAPIEN Mask */ 580 581 #define LPTMR_EXTCTL_CAPDBEN_Pos (6) /*!< LPTMR_T::EXTCTL: CAPDBEN Position */ 582 #define LPTMR_EXTCTL_CAPDBEN_Msk (0x1ul << LPTMR_EXTCTL_CAPDBEN_Pos) /*!< LPTMR_T::EXTCTL: CAPDBEN Mask */ 583 584 #define LPTMR_EXTCTL_CNTDBEN_Pos (7) /*!< LPTMR_T::EXTCTL: CNTDBEN Position */ 585 #define LPTMR_EXTCTL_CNTDBEN_Msk (0x1ul << LPTMR_EXTCTL_CNTDBEN_Pos) /*!< LPTMR_T::EXTCTL: CNTDBEN Mask */ 586 587 #define LPTMR_EXTCTL_INTERCAPSEL_Pos (8) /*!< LPTMR_T::EXTCTL: INTERCAPSEL Position */ 588 #define LPTMR_EXTCTL_INTERCAPSEL_Msk (0x7ul << LPTMR_EXTCTL_INTERCAPSEL_Pos) /*!< LPTMR_T::EXTCTL: INTERCAPSEL Mask */ 589 590 #define LPTMR_EXTCTL_CAPEDGE_Pos (12) /*!< LPTMR_T::EXTCTL: CAPEDGE Position */ 591 #define LPTMR_EXTCTL_CAPEDGE_Msk (0x7ul << LPTMR_EXTCTL_CAPEDGE_Pos) /*!< LPTMR_T::EXTCTL: CAPEDGE Mask */ 592 593 #define LPTMR_EXTCTL_ECNTSSEL_Pos (16) /*!< LPTMR_T::EXTCTL: ECNTSSEL Position */ 594 #define LPTMR_EXTCTL_ECNTSSEL_Msk (0x7ul << LPTMR_EXTCTL_ECNTSSEL_Pos) /*!< LPTMR_T::EXTCTL: ECNTSSEL Mask */ 595 596 #define LPTMR_EXTCTL_CAPDIVSCL_Pos (28) /*!< LPTMR_T::EXTCTL: CAPDIVSCL Position */ 597 #define LPTMR_EXTCTL_CAPDIVSCL_Msk (0xful << LPTMR_EXTCTL_CAPDIVSCL_Pos) /*!< LPTMR_T::EXTCTL: CAPDIVSCL Mask */ 598 599 #define LPTMR_EINTSTS_CAPIF_Pos (0) /*!< LPTMR_T::EINTSTS: CAPIF Position */ 600 #define LPTMR_EINTSTS_CAPIF_Msk (0x1ul << LPTMR_EINTSTS_CAPIF_Pos) /*!< LPTMR_T::EINTSTS: CAPIF Mask */ 601 602 #define LPTMR_EINTSTS_CAPIFOV_Pos (1) /*!< LPTMR_T::EINTSTS: CAPIFOV Position */ 603 #define LPTMR_EINTSTS_CAPIFOV_Msk (0x1ul << LPTMR_EINTSTS_CAPIFOV_Pos) /*!< LPTMR_T::EINTSTS: CAPIFOV Mask */ 604 605 #define LPTMR_TRGCTL_TRGSSEL_Pos (0) /*!< LPTMR_T::TRGCTL: TRGSSEL Position */ 606 #define LPTMR_TRGCTL_TRGSSEL_Msk (0x1ul << LPTMR_TRGCTL_TRGSSEL_Pos) /*!< LPTMR_T::TRGCTL: TRGSSEL Mask */ 607 608 #define LPTMR_TRGCTL_TRGEN_Pos (1) /*!< LPTMR_T::TRGCTL: TRGEN Position */ 609 #define LPTMR_TRGCTL_TRGEN_Msk (0x1ul << LPTMR_TRGCTL_TRGEN_Pos) /*!< LPTMR_T::TRGCTL: TRGEN Mask */ 610 611 #define LPTMR_TRGCTL_TRGLPPDMA_Pos (4) /*!< LPTMR_T::TRGCTL: TRGLPPDMA Position */ 612 #define LPTMR_TRGCTL_TRGLPPDMA_Msk (0x1ul << LPTMR_TRGCTL_TRGLPPDMA_Pos) /*!< LPTMR_T::TRGCTL: TRGLPPDMA Mask */ 613 614 #define LPTMR_CAPNF_CAPNFEN_Pos (0) /*!< LPTMR_T::CAPNF: CAPNFEN Position */ 615 #define LPTMR_CAPNF_CAPNFEN_Msk (0x1ul << LPTMR_CAPNF_CAPNFEN_Pos) /*!< LPTMR_T::CAPNF: CAPNFEN Mask */ 616 617 #define LPTMR_CAPNF_CAPNFSEL_Pos (4) /*!< LPTMR_T::CAPNF: CAPNFSEL Position */ 618 #define LPTMR_CAPNF_CAPNFSEL_Msk (0x7ul << LPTMR_CAPNF_CAPNFSEL_Pos) /*!< LPTMR_T::CAPNF: CAPNFSEL Mask */ 619 620 #define LPTMR_CAPNF_CAPNFCNT_Pos (8) /*!< LPTMR_T::CAPNF: CAPNFCNT Position */ 621 #define LPTMR_CAPNF_CAPNFCNT_Msk (0x7ul << LPTMR_CAPNF_CAPNFCNT_Pos) /*!< LPTMR_T::CAPNF: CAPNFCNT Mask */ 622 623 #define LPTMR_PWMCTL_CNTEN_Pos (0) /*!< LPTMR_T::PWMCTL: CNTEN Position */ 624 #define LPTMR_PWMCTL_CNTEN_Msk (0x1ul << LPTMR_PWMCTL_CNTEN_Pos) /*!< LPTMR_T::PWMCTL: CNTEN Mask */ 625 626 #define LPTMR_PWMCTL_CNTMODE_Pos (3) /*!< LPTMR_T::PWMCTL: CNTMODE Position */ 627 #define LPTMR_PWMCTL_CNTMODE_Msk (0x1ul << LPTMR_PWMCTL_CNTMODE_Pos) /*!< LPTMR_T::PWMCTL: CNTMODE Mask */ 628 629 #define LPTMR_PWMCTL_PWMINTWKEN_Pos (12) /*!< LPTMR_T::PWMCTL: PWMINTWKEN Position */ 630 #define LPTMR_PWMCTL_PWMINTWKEN_Msk (0x1ul << LPTMR_PWMCTL_PWMINTWKEN_Pos) /*!< LPTMR_T::PWMCTL: PWMINTWKEN Mask */ 631 632 #define LPTMR_PWMCTL_DBGHALT_Pos (30) /*!< LPTMR_T::PWMCTL: DBGHALT Position */ 633 #define LPTMR_PWMCTL_DBGHALT_Msk (0x1ul << LPTMR_PWMCTL_DBGHALT_Pos) /*!< LPTMR_T::PWMCTL: DBGHALT Mask */ 634 635 #define LPTMR_PWMCTL_DBGTRIOFF_Pos (31) /*!< LPTMR_T::PWMCTL: DBGTRIOFF Position */ 636 #define LPTMR_PWMCTL_DBGTRIOFF_Msk (0x1ul << LPTMR_PWMCTL_DBGTRIOFF_Pos) /*!< LPTMR_T::PWMCTL: DBGTRIOFF Mask */ 637 638 #define LPTMR_PWMCLKPSC_CLKPSC_Pos (0) /*!< LPTMR_T::PWMCLKPSC: CLKPSC Position */ 639 #define LPTMR_PWMCLKPSC_CLKPSC_Msk (0xfful << LPTMR_PWMCLKPSC_CLKPSC_Pos) /*!< LPTMR_T::PWMCLKPSC: CLKPSC Mask */ 640 641 #define LPTMR_PWMCNTCLR_CNTCLR_Pos (0) /*!< LPTMR_T::PWMCNTCLR: CNTCLR Position */ 642 #define LPTMR_PWMCNTCLR_CNTCLR_Msk (0x1ul << LPTMR_PWMCNTCLR_CNTCLR_Pos) /*!< LPTMR_T::PWMCNTCLR: CNTCLR Mask */ 643 644 #define LPTMR_PWMPERIOD_PERIOD_Pos (0) /*!< LPTMR_T::PWMPERIOD: PERIOD Position */ 645 #define LPTMR_PWMPERIOD_PERIOD_Msk (0xfffful << LPTMR_PWMPERIOD_PERIOD_Pos) /*!< LPTMR_T::PWMPERIOD: PERIOD Mask */ 646 647 #define LPTMR_PWMCMPDAT_CMP_Pos (0) /*!< LPTMR_T::PWMCMPDAT: CMP Position */ 648 #define LPTMR_PWMCMPDAT_CMP_Msk (0xfffful << LPTMR_PWMCMPDAT_CMP_Pos) /*!< LPTMR_T::PWMCMPDAT: CMP Mask */ 649 650 #define LPTMR_PWMCNT_CNT_Pos (0) /*!< LPTMR_T::PWMCNT: CNT Position */ 651 #define LPTMR_PWMCNT_CNT_Msk (0xfffful << LPTMR_PWMCNT_CNT_Pos) /*!< LPTMR_T::PWMCNT: CNT Mask */ 652 653 #define LPTMR_PWMPOLCTL_PINV_Pos (0) /*!< LPTMR_T::PWMPOLCTL: PINV Position */ 654 #define LPTMR_PWMPOLCTL_PINV_Msk (0x1ul << LPTMR_PWMPOLCTL_PINV_Pos) /*!< LPTMR_T::PWMPOLCTL: PINV Mask */ 655 656 #define LPTMR_PWMPOCTL_POEN_Pos (0) /*!< LPTMR_T::PWMPOCTL: POEN Position */ 657 #define LPTMR_PWMPOCTL_POEN_Msk (0x1ul << LPTMR_PWMPOCTL_POEN_Pos) /*!< LPTMR_T::PWMPOCTL: POEN Mask */ 658 659 #define LPTMR_PWMPOCTL_POSEL_Pos (8) /*!< LPTMR_T::PWMPOCTL: POSEL Position */ 660 #define LPTMR_PWMPOCTL_POSEL_Msk (0x1ul << LPTMR_PWMPOCTL_POSEL_Pos) /*!< LPTMR_T::PWMPOCTL: POSEL Mask */ 661 662 #define LPTMR_PWMINTEN0_PIEN_Pos (1) /*!< LPTMR_T::PWMINTEN0: PIEN Position */ 663 #define LPTMR_PWMINTEN0_PIEN_Msk (0x1ul << LPTMR_PWMINTEN0_PIEN_Pos) /*!< LPTMR_T::PWMINTEN0: PIEN Mask */ 664 665 #define LPTMR_PWMINTEN0_CMPUIEN_Pos (2) /*!< LPTMR_T::PWMINTEN0: CMPUIEN Position */ 666 #define LPTMR_PWMINTEN0_CMPUIEN_Msk (0x1ul << LPTMR_PWMINTEN0_CMPUIEN_Pos) /*!< LPTMR_T::PWMINTEN0: CMPUIEN Mask */ 667 668 #define LPTMR_PWMINTSTS0_PIF_Pos (1) /*!< LPTMR_T::PWMINTSTS0: PIF Position */ 669 #define LPTMR_PWMINTSTS0_PIF_Msk (0x1ul << LPTMR_PWMINTSTS0_PIF_Pos) /*!< LPTMR_T::PWMINTSTS0: PIF Mask */ 670 671 #define LPTMR_PWMINTSTS0_CMPUIF_Pos (2) /*!< LPTMR_T::PWMINTSTS0: CMPUIF Position */ 672 #define LPTMR_PWMINTSTS0_CMPUIF_Msk (0x1ul << LPTMR_PWMINTSTS0_CMPUIF_Pos) /*!< LPTMR_T::PWMINTSTS0: CMPUIF Mask */ 673 674 #define LPTMR_PWMTRGCTL_TRGSEL_Pos (0) /*!< LPTMR_T::PWMTRGCTL: TRGSEL Position */ 675 #define LPTMR_PWMTRGCTL_TRGSEL_Msk (0x3ul << LPTMR_PWMTRGCTL_TRGSEL_Pos) /*!< LPTMR_T::PWMTRGCTL: TRGSEL Mask */ 676 677 #define LPTMR_PWMTRGCTL_TRGEN_Pos (2) /*!< LPTMR_T::PWMTRGCTL: TRGEN Position */ 678 #define LPTMR_PWMTRGCTL_TRGEN_Msk (0x1ul << LPTMR_PWMTRGCTL_TRGEN_Pos) /*!< LPTMR_T::PWMTRGCTL: TRGEN Mask */ 679 680 #define LPTMR_PWMTRGCTL_PWMTRGLPPDMA_Pos (9) /*!< LPTMR_T::PWMTRGCTL: PWMTRGLPPDMA Position*/ 681 #define LPTMR_PWMTRGCTL_PWMTRGLPPDMA_Msk (0x1ul << LPTMR_PWMTRGCTL_PWMTRGLPPDMA_Pos) /*!< LPTMR_T::PWMTRGCTL: PWMTRGLPPDMA Mask */ 682 683 #define LPTMR_PWMSTATUS_CNTMAXF_Pos (0) /*!< LPTMR_T::PWMSTATUS: CNTMAXF Position */ 684 #define LPTMR_PWMSTATUS_CNTMAXF_Msk (0x1ul << LPTMR_PWMSTATUS_CNTMAXF_Pos) /*!< LPTMR_T::PWMSTATUS: CNTMAXF Mask */ 685 686 #define LPTMR_PWMSTATUS_PWMINTWKF_Pos (8) /*!< LPTMR_T::PWMSTATUS: PWMINTWKF Position */ 687 #define LPTMR_PWMSTATUS_PWMINTWKF_Msk (0x1ul << LPTMR_PWMSTATUS_PWMINTWKF_Pos) /*!< LPTMR_T::PWMSTATUS: PWMINTWKF Mask */ 688 689 #define LPTMR_PWMPBUF_PBUF_Pos (0) /*!< LPTMR_T::PWMPBUF: PBUF Position */ 690 #define LPTMR_PWMPBUF_PBUF_Msk (0xfffful << LPTMR_PWMPBUF_PBUF_Pos) /*!< LPTMR_T::PWMPBUF: PBUF Mask */ 691 692 #define LPTMR_PWMCMPBUF_CMPBUF_Pos (0) /*!< LPTMR_T::PWMCMPBUF: CMPBUF Position */ 693 #define LPTMR_PWMCMPBUF_CMPBUF_Msk (0xfffful << LPTMR_PWMCMPBUF_CMPBUF_Pos) /*!< LPTMR_T::PWMCMPBUF: CMPBUF Mask */ 694 695 #define LPTMR_PWMIFA_IFACNT_Pos (0) /*!< LPTMR_T::PWMIFA: IFACNT Position */ 696 #define LPTMR_PWMIFA_IFACNT_Msk (0xfffful << LPTMR_PWMIFA_IFACNT_Pos) /*!< LPTMR_T::PWMIFA: IFACNT Mask */ 697 698 #define LPTMR_PWMIFA_STPMOD_Pos (24) /*!< LPTMR_T::PWMIFA: STPMOD Position */ 699 #define LPTMR_PWMIFA_STPMOD_Msk (0x1ul << LPTMR_PWMIFA_STPMOD_Pos) /*!< LPTMR_T::PWMIFA: STPMOD Mask */ 700 701 #define LPTMR_PWMIFA_IFASEL_Pos (28) /*!< LPTMR_T::PWMIFA: IFASEL Position */ 702 #define LPTMR_PWMIFA_IFASEL_Msk (0x3ul << LPTMR_PWMIFA_IFASEL_Pos) /*!< LPTMR_T::PWMIFA: IFASEL Mask */ 703 704 #define LPTMR_PWMIFA_IFAEN_Pos (31) /*!< LPTMR_T::PWMIFA: IFAEN Position */ 705 #define LPTMR_PWMIFA_IFAEN_Msk (0x1ul << LPTMR_PWMIFA_IFAEN_Pos) /*!< LPTMR_T::PWMIFA: IFAEN Mask */ 706 707 #define LPTMR_PWMAINTSTS_IFAIF_Pos (0) /*!< LPTMR_T::PWMAINTSTS: IFAIF Position */ 708 #define LPTMR_PWMAINTSTS_IFAIF_Msk (0x1ul << LPTMR_PWMAINTSTS_IFAIF_Pos) /*!< LPTMR_T::PWMAINTSTS: IFAIF Mask */ 709 710 #define LPTMR_PWMAINTEN_IFAIEN_Pos (0) /*!< LPTMR_T::PWMAINTEN: IFAIEN Position */ 711 #define LPTMR_PWMAINTEN_IFAIEN_Msk (0x1ul << LPTMR_PWMAINTEN_IFAIEN_Pos) /*!< LPTMR_T::PWMAINTEN: IFAIEN Mask */ 712 713 #define LPTMR_PWMAPDMACTL_APDMAEN_Pos (0) /*!< LPTMR_T::PWMAPDMACTL: APDMAEN Position */ 714 #define LPTMR_PWMAPDMACTL_APDMAEN_Msk (0x1ul << LPTMR_PWMAPDMACTL_APDMAEN_Pos) /*!< LPTMR_T::PWMAPDMACTL: APDMAEN Mask */ 715 716 /**@}*/ /* LPTMR_CONST */ 717 /**@}*/ /* end of LPTMR register group */ 718 /**@}*/ /* end of REGISTER group */ 719 720 #if defined ( __CC_ARM ) 721 #pragma no_anon_unions 722 #endif 723 724 #endif /* __LPTMR_REG_H__ */ 725
