1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_LPSPI_H_
9 #define _FSL_LPSPI_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lpspi_driver
15 * @{
16 */
17
18 /**********************************************************************************************************************
19 * Definitions
20 *********************************************************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! @brief LPSPI driver version 2.0.1. */
25 #define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
26 /*@}*/
27
28 #ifndef LPSPI_DUMMY_DATA
29 /*! @brief LPSPI dummy data if no Tx data.*/
30 #define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */
31 #endif
32
33 /*! @brief Status for the LPSPI driver.*/
34 enum _lpspi_status
35 {
36 kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/
37 kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */
38 kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/
39 kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */
40 };
41
42 /*! @brief LPSPI status flags in SPIx_SR register.*/
43 enum _lpspi_flags
44 {
45 kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */
46 kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */
47 kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */
48 kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */
49 kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */
50 kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */
51 kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */
52 kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */
53 kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */
54 kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK |
55 LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK |
56 LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */
57 };
58
59 /*! @brief LPSPI interrupt source.*/
60 enum _lpspi_interrupt_enable
61 {
62 kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */
63 kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */
64 kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */
65 kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */
66 kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */
67 kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/
68 kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */
69 kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */
70 kLPSPI_AllInterruptEnable =
71 (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK |
72 LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/
73 };
74
75 /*! @brief LPSPI DMA source.*/
76 enum _lpspi_dma_enable
77 {
78 kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */
79 kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */
80 };
81
82 /*! @brief LPSPI master or slave mode configuration.*/
83 typedef enum _lpspi_master_slave_mode
84 {
85 kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/
86 kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/
87 } lpspi_master_slave_mode_t;
88
89 /*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/
90 typedef enum _lpspi_which_pcs_config
91 {
92 kLPSPI_Pcs0 = 0U, /*!< PCS[0] */
93 kLPSPI_Pcs1 = 1U, /*!< PCS[1] */
94 kLPSPI_Pcs2 = 2U, /*!< PCS[2] */
95 kLPSPI_Pcs3 = 3U /*!< PCS[3] */
96 } lpspi_which_pcs_t;
97
98 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/
99 typedef enum _lpspi_pcs_polarity_config
100 {
101 kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */
102 kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */
103 } lpspi_pcs_polarity_config_t;
104
105 /*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/
106 enum _lpspi_pcs_polarity
107 {
108 kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */
109 kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */
110 kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */
111 kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */
112 kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */
113 };
114
115 /*! @brief LPSPI clock polarity configuration.*/
116 typedef enum _lpspi_clock_polarity
117 {
118 kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/
119 kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/
120 } lpspi_clock_polarity_t;
121
122 /*! @brief LPSPI clock phase configuration.*/
123 typedef enum _lpspi_clock_phase
124 {
125 kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
126 following edge.*/
127 kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
128 following edge.*/
129 } lpspi_clock_phase_t;
130
131 /*! @brief LPSPI data shifter direction options.*/
132 typedef enum _lpspi_shift_direction
133 {
134 kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/
135 kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/
136 } lpspi_shift_direction_t;
137
138 /*! @brief LPSPI Host Request select configuration. */
139 typedef enum _lpspi_host_request_select
140 {
141 kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */
142 kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */
143 } lpspi_host_request_select_t;
144
145 /*! @brief LPSPI Match configuration options. */
146 typedef enum _lpspi_match_config
147 {
148 kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */
149 kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */
150 kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */
151 kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */
152 kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */
153 kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */
154 kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */
155 } lpspi_match_config_t;
156
157 /*! @brief LPSPI pin (SDO and SDI) configuration. */
158 typedef enum _lpspi_pin_config
159 {
160 kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */
161 kLPSPI_SdoInSdoOut = 1U, /*!< LPSPI SDO input, SDO output. */
162 kLPSPI_SdiInSdiOut = 2U, /*!< LPSPI SDI input, SDI output. */
163 kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */
164 } lpspi_pin_config_t;
165
166 /*! @brief LPSPI data output configuration. */
167 typedef enum _lpspi_data_out_config
168 {
169 kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */
170 kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */
171 } lpspi_data_out_config_t;
172
173 /*! @brief LPSPI transfer width configuration. */
174 typedef enum _lpspi_transfer_width
175 {
176 kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */
177 kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */
178 kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */
179 } lpspi_transfer_width_t;
180
181 /*! @brief LPSPI delay type selection.*/
182 typedef enum _lpspi_delay_type
183 {
184 kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */
185 kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */
186 kLPSPI_BetweenTransfer /*!< Delay between transfers. */
187 } lpspi_delay_type_t;
188
189 #define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */
190 #define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
191
192 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */
193 enum _lpspi_transfer_config_flag_for_master
194 {
195 kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */
196 kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */
197 kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */
198 kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */
199
200 kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
201
202 kLPSPI_MasterByteSwap =
203 1U << 22 /*!< Is master swap the byte.
204 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
205 * lpspi_shift_direction_t to MSB).
206 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
207 * or not, the waveform is 1 2 3 4 5 6 7 8.
208 * 2. If you set bitPerFrame = 16 :
209 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
210 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
211 * 3. If you set bitPerFrame = 32 :
212 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
213 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
214 */
215 };
216
217 #define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */
218 #define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */
219
220 /*! @brief Use this enumeration for LPSPI slave transfer configFlags. */
221 enum _lpspi_transfer_config_flag_for_slave
222 {
223 kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */
224 kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */
225 kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */
226 kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */
227
228 kLPSPI_SlaveByteSwap =
229 1U << 22 /*!< Is slave swap the byte.
230 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
231 * lpspi_shift_direction_t to MSB).
232 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
233 * or not, the waveform is 1 2 3 4 5 6 7 8.
234 * 2. If you set bitPerFrame = 16 :
235 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
236 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
237 * 3. If you set bitPerFrame = 32 :
238 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
239 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
240 */
241 };
242
243 /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */
244 enum _lpspi_transfer_state
245 {
246 kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */
247 kLPSPI_Busy, /*!< Transfer queue is not finished. */
248 kLPSPI_Error /*!< Transfer error. */
249 };
250
251 /*! @brief LPSPI master configuration structure.*/
252 typedef struct _lpspi_master_config
253 {
254 uint32_t baudRate; /*!< Baud Rate for LPSPI. */
255 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
256 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
257 lpspi_clock_phase_t cpha; /*!< Clock phase. */
258 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
259
260 uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay.
261 It sets the boundary value if out of range.*/
262 uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum
263 delay. It sets the boundary value if out of range.*/
264 uint32_t
265 betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the minimum
266 delay. It sets the boundary value if out of range.*/
267
268 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */
269 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
270
271 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
272 *during single bit transfers.*/
273
274 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
275 * between accesses (LPSPI_PCS is negated). */
276 } lpspi_master_config_t;
277
278 /*! @brief LPSPI slave configuration structure.*/
279 typedef struct _lpspi_slave_config
280 {
281 uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/
282 lpspi_clock_polarity_t cpol; /*!< Clock polarity. */
283 lpspi_clock_phase_t cpha; /*!< Clock phase. */
284 lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
285
286 lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */
287 lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */
288
289 lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
290 *during single bit transfers.*/
291
292 lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
293 * between accesses (LPSPI_PCS is negated). */
294 } lpspi_slave_config_t;
295
296 /*!
297 * @brief Forward declaration of the _lpspi_master_handle typedefs.
298 */
299 typedef struct _lpspi_master_handle lpspi_master_handle_t;
300
301 /*!
302 * @brief Forward declaration of the _lpspi_slave_handle typedefs.
303 */
304 typedef struct _lpspi_slave_handle lpspi_slave_handle_t;
305
306 /*!
307 * @brief Master completion callback function pointer type.
308 *
309 * @param base LPSPI peripheral address.
310 * @param handle Pointer to the handle for the LPSPI master.
311 * @param status Success or error code describing whether the transfer is completed.
312 * @param userData Arbitrary pointer-dataSized value passed from the application.
313 */
314 typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base,
315 lpspi_master_handle_t *handle,
316 status_t status,
317 void *userData);
318
319 /*!
320 * @brief Slave completion callback function pointer type.
321 *
322 * @param base LPSPI peripheral address.
323 * @param handle Pointer to the handle for the LPSPI slave.
324 * @param status Success or error code describing whether the transfer is completed.
325 * @param userData Arbitrary pointer-dataSized value passed from the application.
326 */
327 typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
328 lpspi_slave_handle_t *handle,
329 status_t status,
330 void *userData);
331
332 /*! @brief LPSPI master/slave transfer structure.*/
333 typedef struct _lpspi_transfer
334 {
335 uint8_t *txData; /*!< Send buffer. */
336 uint8_t *rxData; /*!< Receive buffer. */
337 volatile size_t dataSize; /*!< Transfer bytes. */
338
339 uint32_t
340 configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if the
341 transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the transfer
342 is used for slave.*/
343 } lpspi_transfer_t;
344
345 /*! @brief LPSPI master transfer handle structure used for transactional API. */
346 struct _lpspi_master_handle
347 {
348 volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */
349 volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */
350
351 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
352
353 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
354
355 volatile uint8_t rxWatermark; /*!< Rx watermark. */
356
357 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */
358 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */
359
360 uint8_t *volatile txData; /*!< Send buffer. */
361 uint8_t *volatile rxData; /*!< Receive buffer. */
362 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
363 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
364
365 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */
366 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times . */
367
368 uint32_t totalByteCount; /*!< Number of transfer bytes*/
369
370 uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */
371
372 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
373
374 lpspi_master_transfer_callback_t callback; /*!< Completion callback. */
375 void *userData; /*!< Callback user data. */
376 };
377
378 /*! @brief LPSPI slave transfer handle structure used for transactional API. */
379 struct _lpspi_slave_handle
380 {
381 volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
382
383 volatile uint8_t fifoSize; /*!< FIFO dataSize. */
384
385 volatile uint8_t rxWatermark; /*!< Rx watermark. */
386
387 volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */
388 volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR . */
389
390 uint8_t *volatile txData; /*!< Send buffer. */
391 uint8_t *volatile rxData; /*!< Receive buffer. */
392
393 volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
394 volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
395
396 volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */
397 volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times . */
398
399 uint32_t totalByteCount; /*!< Number of transfer bytes*/
400
401 volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
402
403 volatile uint32_t errorCount; /*!< Error count for slave transfer.*/
404
405 lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */
406 void *userData; /*!< Callback user data. */
407 };
408
409 /**********************************************************************************************************************
410 * API
411 *********************************************************************************************************************/
412 #if defined(__cplusplus)
413 extern "C" {
414 #endif /*_cplusplus*/
415
416 /*!
417 * @name Initialization and deinitialization
418 * @{
419 */
420
421 /*!
422 * @brief Initializes the LPSPI master.
423 *
424 * @param base LPSPI peripheral address.
425 * @param masterConfig Pointer to structure lpspi_master_config_t.
426 * @param srcClock_Hz Module source input clock in Hertz
427 */
428 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz);
429
430 /*!
431 * @brief Sets the lpspi_master_config_t structure to default values.
432 *
433 * This API initializes the configuration structure for LPSPI_MasterInit().
434 * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified
435 * before calling the LPSPI_MasterInit().
436 * Example:
437 * @code
438 * lpspi_master_config_t masterConfig;
439 * LPSPI_MasterGetDefaultConfig(&masterConfig);
440 * @endcode
441 * @param masterConfig pointer to lpspi_master_config_t structure
442 */
443 void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig);
444
445 /*!
446 * @brief LPSPI slave configuration.
447 *
448 * @param base LPSPI peripheral address.
449 * @param slaveConfig Pointer to a structure lpspi_slave_config_t.
450 */
451 void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig);
452
453 /*!
454 * @brief Sets the lpspi_slave_config_t structure to default values.
455 *
456 * This API initializes the configuration structure for LPSPI_SlaveInit().
457 * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified
458 * before calling the LPSPI_SlaveInit().
459 * Example:
460 * @code
461 * lpspi_slave_config_t slaveConfig;
462 * LPSPI_SlaveGetDefaultConfig(&slaveConfig);
463 * @endcode
464 * @param slaveConfig pointer to lpspi_slave_config_t structure.
465 */
466 void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig);
467
468 /*!
469 * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock.
470 * @param base LPSPI peripheral address.
471 */
472 void LPSPI_Deinit(LPSPI_Type *base);
473
474 /*!
475 * @brief Restores the LPSPI peripheral to reset state. Note that this function
476 * sets all registers to reset state. As a result, the LPSPI module can't work after calling
477 * this API.
478 * @param base LPSPI peripheral address.
479 */
480 void LPSPI_Reset(LPSPI_Type *base);
481
482 /*!
483 * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0.
484 *
485 * @param base LPSPI peripheral address.
486 * @param enable Pass true to enable module, false to disable module.
487 */
LPSPI_Enable(LPSPI_Type * base,bool enable)488 static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
489 {
490 if (enable)
491 {
492 base->CR |= LPSPI_CR_MEN_MASK;
493 }
494 else
495 {
496 base->CR &= ~LPSPI_CR_MEN_MASK;
497 }
498 }
499
500 /*!
501 *@}
502 */
503
504 /*!
505 * @name Status
506 * @{
507 */
508
509 /*!
510 * @brief Gets the LPSPI status flag state.
511 * @param base LPSPI peripheral address.
512 * @return The LPSPI status(in SR register).
513 */
LPSPI_GetStatusFlags(LPSPI_Type * base)514 static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base)
515 {
516 return (base->SR);
517 }
518
519 /*!
520 * @brief Gets the LPSPI Tx FIFO size.
521 * @param base LPSPI peripheral address.
522 * @return The LPSPI Tx FIFO size.
523 */
LPSPI_GetTxFifoSize(LPSPI_Type * base)524 static inline uint32_t LPSPI_GetTxFifoSize(LPSPI_Type *base)
525 {
526 return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT));
527 }
528
529 /*!
530 * @brief Gets the LPSPI Rx FIFO size.
531 * @param base LPSPI peripheral address.
532 * @return The LPSPI Rx FIFO size.
533 */
LPSPI_GetRxFifoSize(LPSPI_Type * base)534 static inline uint32_t LPSPI_GetRxFifoSize(LPSPI_Type *base)
535 {
536 return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT));
537 }
538
539 /*!
540 * @brief Gets the LPSPI Tx FIFO count.
541 * @param base LPSPI peripheral address.
542 * @return The number of words in the transmit FIFO.
543 */
LPSPI_GetTxFifoCount(LPSPI_Type * base)544 static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base)
545 {
546 return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT);
547 }
548
549 /*!
550 * @brief Gets the LPSPI Rx FIFO count.
551 * @param base LPSPI peripheral address.
552 * @return The number of words in the receive FIFO.
553 */
LPSPI_GetRxFifoCount(LPSPI_Type * base)554 static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base)
555 {
556 return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT);
557 }
558
559 /*!
560 * @brief Clears the LPSPI status flag.
561 *
562 * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
563 * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags.
564 * Example usage:
565 * @code
566 * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag);
567 * @endcode
568 *
569 * @param base LPSPI peripheral address.
570 * @param statusFlags The status flag used from type _lpspi_flags.
571 */
LPSPI_ClearStatusFlags(LPSPI_Type * base,uint32_t statusFlags)572 static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags)
573 {
574 base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/
575 }
576
577 /*!
578 *@}
579 */
580
581 /*!
582 * @name Interrupts
583 * @{
584 */
585
586 /*!
587 * @brief Enables the LPSPI interrupts.
588 *
589 * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask.
590 * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request.
591 *
592 * @code
593 * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
594 * @endcode
595 *
596 * @param base LPSPI peripheral address.
597 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
598 */
LPSPI_EnableInterrupts(LPSPI_Type * base,uint32_t mask)599 static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask)
600 {
601 base->IER |= mask;
602 }
603
604 /*!
605 * @brief Disables the LPSPI interrupts.
606 *
607 * @code
608 * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable );
609 * @endcode
610 *
611 * @param base LPSPI peripheral address.
612 * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable.
613 */
LPSPI_DisableInterrupts(LPSPI_Type * base,uint32_t mask)614 static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask)
615 {
616 base->IER &= ~mask;
617 }
618
619 /*!
620 *@}
621 */
622
623 /*!
624 * @name DMA Control
625 * @{
626 */
627
628 /*!
629 * @brief Enables the LPSPI DMA request.
630 *
631 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
632 * @code
633 * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
634 * @endcode
635 *
636 * @param base LPSPI peripheral address.
637 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
638 */
LPSPI_EnableDMA(LPSPI_Type * base,uint32_t mask)639 static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask)
640 {
641 base->DER |= mask;
642 }
643
644 /*!
645 * @brief Disables the LPSPI DMA request.
646 *
647 * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask.
648 * @code
649 * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
650 * @endcode
651 *
652 * @param base LPSPI peripheral address.
653 * @param mask The interrupt mask; Use the enum _lpspi_dma_enable.
654 */
LPSPI_DisableDMA(LPSPI_Type * base,uint32_t mask)655 static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask)
656 {
657 base->DER &= ~mask;
658 }
659
660 /*!
661 * @brief Gets the LPSPI Transmit Data Register address for a DMA operation.
662 *
663 * This function gets the LPSPI Transmit Data Register address because this value is needed
664 * for the DMA operation.
665 * This function can be used for either master or slave mode.
666 *
667 * @param base LPSPI peripheral address.
668 * @return The LPSPI Transmit Data Register address.
669 */
LPSPI_GetTxRegisterAddress(LPSPI_Type * base)670 static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base)
671 {
672 return (uint32_t) & (base->TDR);
673 }
674
675 /*!
676 * @brief Gets the LPSPI Receive Data Register address for a DMA operation.
677 *
678 * This function gets the LPSPI Receive Data Register address because this value is needed
679 * for the DMA operation.
680 * This function can be used for either master or slave mode.
681 *
682 * @param base LPSPI peripheral address.
683 * @return The LPSPI Receive Data Register address.
684 */
LPSPI_GetRxRegisterAddress(LPSPI_Type * base)685 static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
686 {
687 return (uint32_t) & (base->RDR);
688 }
689
690 /*!
691 *@}
692 */
693
694 /*!
695 * @name Bus Operations
696 * @{
697 */
698
699 /*!
700 * @brief Configures the LPSPI for either master or slave.
701 *
702 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
703 *
704 * @param base LPSPI peripheral address.
705 * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t.
706 */
LPSPI_SetMasterSlaveMode(LPSPI_Type * base,lpspi_master_slave_mode_t mode)707 static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)
708 {
709 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode);
710 }
711
712 /*!
713 * @brief Returns whether the LPSPI module is in master mode.
714 *
715 * @param base LPSPI peripheral address.
716 * @return Returns true if the module is in master mode or false if the module is in slave mode.
717 */
LPSPI_IsMaster(LPSPI_Type * base)718 static inline bool LPSPI_IsMaster(LPSPI_Type *base)
719 {
720 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK);
721 }
722
723 /*!
724 * @brief Flushes the LPSPI FIFOs.
725 *
726 * @param base LPSPI peripheral address.
727 * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO.
728 * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO.
729 */
LPSPI_FlushFifo(LPSPI_Type * base,bool flushTxFifo,bool flushRxFifo)730 static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
731 {
732 base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT);
733 }
734
735 /*!
736 * @brief Sets the transmit and receive FIFO watermark values.
737 *
738 * This function allows the user to set the receive and transmit FIFO watermarks. The function
739 * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be
740 * equal to or greater than the FIFO size. It is up to the higher level driver to make this check.
741 *
742 * @param base LPSPI peripheral address.
743 * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
744 * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated.
745 */
LPSPI_SetFifoWatermarks(LPSPI_Type * base,uint32_t txWater,uint32_t rxWater)746 static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater)
747 {
748 base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater);
749 }
750
751 /*!
752 * @brief Configures all LPSPI peripheral chip select polarities simultaneously.
753 *
754 * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0).
755 *
756 * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of
757 * PCS is device-specific.
758 * @code
759 * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow);
760 * @endcode
761 *
762 * @param base LPSPI peripheral address.
763 * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity.
764 */
LPSPI_SetAllPcsPolarity(LPSPI_Type * base,uint32_t mask)765 static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)
766 {
767 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask);
768 }
769
770 /*!
771 * @brief Configures the frame size.
772 *
773 * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal
774 * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word
775 * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not
776 * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
777 *
778 * Note 1 : The transmit command register should be initialized before enabling the LPSPI in slave mode, although
779 * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command
780 * register
781 * should only be changed if the LPSPI is idle.
782 *
783 * Note 2 : The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That
784 * means the TCR register should be written to when the Tx FIFO is not full.
785 *
786 * @param base LPSPI peripheral address.
787 * @param frameSize The frame size in number of bits.
788 */
LPSPI_SetFrameSize(LPSPI_Type * base,uint32_t frameSize)789 static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize)
790 {
791 base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1);
792 }
793
794 /*!
795 * @brief Sets the LPSPI baud rate in bits per second.
796 *
797 * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest
798 * possible baud rate without exceeding the desired baud rate and returns the
799 * calculated baud rate in bits-per-second. It requires the caller to provide
800 * the frequency of the module source clock (in Hertz). Note that the baud rate
801 * does not go into effect until the Transmit Control Register (TCR) is programmed
802 * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue
803 * parameter for later programming in the TCR. The higher level
804 * peripheral driver should alert the user of an out of range baud rate input.
805 *
806 * Note that the LPSPI module must first be disabled before configuring this.
807 * Note that the LPSPI module must be configured for master mode before configuring this.
808 *
809 * @param base LPSPI peripheral address.
810 * @param baudRate_Bps The desired baud rate in bits per second.
811 * @param srcClock_Hz Module source input clock in Hertz.
812 * @param tcrPrescaleValue The TCR prescale value needed to program the TCR.
813 * @return The actual calculated baud rate. This function may also return a "0" if the
814 * LPSPI is not configured for master mode or if the LPSPI module is not disabled.
815 */
816
817 uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base,
818 uint32_t baudRate_Bps,
819 uint32_t srcClock_Hz,
820 uint32_t *tcrPrescaleValue);
821
822 /*!
823 * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to
824 * change the delay values).
825 *
826 * This function configures the following:
827 * SCK to PCS delay, or
828 * PCS to SCK delay, or
829 * The configurations must occur between the transfer delay.
830 *
831 * The delay names are available in type lpspi_delay_type_t.
832 *
833 * The user passes the desired delay along with the delay value.
834 * This allows the user to directly set the delay values if they have
835 * pre-calculated them or if they simply wish to manually increment the value.
836 *
837 * Note that the LPSPI module must first be disabled before configuring this.
838 * Note that the LPSPI module must be configured for master mode before configuring this.
839 *
840 * @param base LPSPI peripheral address.
841 * @param scaler The 8-bit delay value 0x00 to 0xFF (255).
842 * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t.
843 */
844 void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay);
845
846 /*!
847 * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be
848 * disabled to change the delay values).
849 *
850 * This function calculates the values for the following:
851 * SCK to PCS delay, or
852 * PCS to SCK delay, or
853 * The configurations must occur between the transfer delay.
854 *
855 * The delay names are available in type lpspi_delay_type_t.
856 *
857 * The user passes the desired delay and the desired delay value in
858 * nano-seconds. The function calculates the value needed for the desired delay parameter
859 * and returns the actual calculated delay because an exact delay match may not be possible. In this
860 * case, the closest match is calculated without going below the desired delay value input.
861 * It is possible to input a very large delay value that exceeds the capability of the part, in
862 * which case the maximum supported delay is returned. It is up to the higher level
863 * peripheral driver to alert the user of an out of range delay input.
864 *
865 * Note that the LPSPI module must be configured for master mode before configuring this. And note that
866 * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler).
867 *
868 * @param base LPSPI peripheral address.
869 * @param delayTimeInNanoSec The desired delay value in nano-seconds.
870 * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t.
871 * @param srcClock_Hz Module source input clock in Hertz.
872 * @return actual Calculated delay value in nano-seconds.
873 */
874 uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base,
875 uint32_t delayTimeInNanoSec,
876 lpspi_delay_type_t whichDelay,
877 uint32_t srcClock_Hz);
878
879 /*!
880 * @brief Writes data into the transmit data buffer.
881 *
882 * This function writes data passed in by the user to the Transmit Data Register (TDR).
883 * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits,
884 * the user has to manage sending the data one 32-bit word at a time.
885 * Any writes to the TDR result in an immediate push to the transmit FIFO.
886 * This function can be used for either master or slave modes.
887 *
888 * @param base LPSPI peripheral address.
889 * @param data The data word to be sent.
890 */
LPSPI_WriteData(LPSPI_Type * base,uint32_t data)891 static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data)
892 {
893 base->TDR = data;
894 }
895
896 /*!
897 * @brief Reads data from the data buffer.
898 *
899 * This function reads the data from the Receive Data Register (RDR).
900 * This function can be used for either master or slave mode.
901 *
902 * @param base LPSPI peripheral address.
903 * @return The data read from the data buffer.
904 */
LPSPI_ReadData(LPSPI_Type * base)905 static inline uint32_t LPSPI_ReadData(LPSPI_Type *base)
906 {
907 return (base->RDR);
908 }
909
910 /*!
911 * @brief Set up the dummy data.
912 *
913 * @param base LPSPI peripheral address.
914 * @param dummyData Data to be transferred when tx buffer is NULL.
915 * Note:
916 * This API has no effect when LPSPI in slave interrupt mode, because driver
917 * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit
918 * FIFO and output pin is tristated.
919 */
920 void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData);
921
922 /*!
923 *@}
924 */
925
926 /*!
927 * @name Transactional
928 * @{
929 */
930 /*Transactional APIs*/
931
932 /*!
933 * @brief Initializes the LPSPI master handle.
934 *
935 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
936 * specified LPSPI instance, call this API once to get the initialized handle.
937
938 * @param base LPSPI peripheral address.
939 * @param handle LPSPI handle pointer to lpspi_master_handle_t.
940 * @param callback DSPI callback.
941 * @param userData callback function parameter.
942 */
943 void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
944 lpspi_master_handle_t *handle,
945 lpspi_master_transfer_callback_t callback,
946 void *userData);
947
948 /*!
949 * @brief LPSPI master transfer data using a polling method.
950 *
951 * This function transfers data using a polling method. This is a blocking function, which does not return until all
952 * transfers have been
953 * completed.
954 *
955 * Note:
956 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
957 * For bytesPerFrame greater than 4:
958 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
959 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
960 *
961 * @param base LPSPI peripheral address.
962 * @param transfer pointer to lpspi_transfer_t structure.
963 * @return status of status_t.
964 */
965 status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer);
966
967 /*!
968 * @brief LPSPI master transfer data using an interrupt method.
969 *
970 * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away.
971 * When all data
972 * is transferred, the callback function is called.
973 *
974 * Note:
975 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
976 * For bytesPerFrame greater than 4:
977 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4.
978 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
979 *
980 * @param base LPSPI peripheral address.
981 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
982 * @param transfer pointer to lpspi_transfer_t structure.
983 * @return status of status_t.
984 */
985 status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer);
986
987 /*!
988 * @brief Gets the master transfer remaining bytes.
989 *
990 * This function gets the master transfer remaining bytes.
991 *
992 * @param base LPSPI peripheral address.
993 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
994 * @param count Number of bytes transferred so far by the non-blocking transaction.
995 * @return status of status_t.
996 */
997 status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count);
998
999 /*!
1000 * @brief LPSPI master abort transfer which uses an interrupt method.
1001 *
1002 * This function aborts a transfer which uses an interrupt method.
1003 *
1004 * @param base LPSPI peripheral address.
1005 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1006 */
1007 void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle);
1008
1009 /*!
1010 * @brief LPSPI Master IRQ handler function.
1011 *
1012 * This function processes the LPSPI transmit and receive IRQ.
1013 *
1014 * @param base LPSPI peripheral address.
1015 * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state.
1016 */
1017 void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle);
1018
1019 /*!
1020 * @brief Initializes the LPSPI slave handle.
1021 *
1022 * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a
1023 * specified LPSPI instance, call this API once to get the initialized handle.
1024 *
1025 * @param base LPSPI peripheral address.
1026 * @param handle LPSPI handle pointer to lpspi_slave_handle_t.
1027 * @param callback DSPI callback.
1028 * @param userData callback function parameter.
1029 */
1030 void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
1031 lpspi_slave_handle_t *handle,
1032 lpspi_slave_transfer_callback_t callback,
1033 void *userData);
1034
1035 /*!
1036 * @brief LPSPI slave transfer data using an interrupt method.
1037 *
1038 * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away.
1039 * When all data
1040 * is transferred, the callback function is called.
1041 *
1042 * Note:
1043 * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4.
1044 * For bytesPerFrame greater than 4:
1045 * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
1046 * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
1047 *
1048 * @param base LPSPI peripheral address.
1049 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1050 * @param transfer pointer to lpspi_transfer_t structure.
1051 * @return status of status_t.
1052 */
1053 status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer);
1054
1055 /*!
1056 * @brief Gets the slave transfer remaining bytes.
1057 *
1058 * This function gets the slave transfer remaining bytes.
1059 *
1060 * @param base LPSPI peripheral address.
1061 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1062 * @param count Number of bytes transferred so far by the non-blocking transaction.
1063 * @return status of status_t.
1064 */
1065 status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count);
1066
1067 /*!
1068 * @brief LPSPI slave aborts a transfer which uses an interrupt method.
1069 *
1070 * This function aborts a transfer which uses an interrupt method.
1071 *
1072 * @param base LPSPI peripheral address.
1073 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1074 */
1075 void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1076
1077 /*!
1078 * @brief LPSPI Slave IRQ handler function.
1079 *
1080 * This function processes the LPSPI transmit and receives an IRQ.
1081 *
1082 * @param base LPSPI peripheral address.
1083 * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
1084 */
1085 void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle);
1086
1087 /*!
1088 *@}
1089 */
1090
1091 #if defined(__cplusplus)
1092 }
1093 #endif /*_cplusplus*/
1094 /*!
1095 *@}
1096 */
1097
1098 #endif /*_FSL_LPSPI_H_*/
1099
