1 /**************************************************************************//** 2 * @file lpspi_reg.h 3 * @version V1.00 4 * @brief Low power SPI register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 * 9 *****************************************************************************/ 10 #ifndef __LPSPI_REG_H__ 11 #define __LPSPI_REG_H__ 12 13 #if defined ( __CC_ARM ) 14 #pragma anon_unions 15 #endif 16 17 /** 18 @addtogroup REGISTER Control Register 19 @{ 20 */ 21 22 /** 23 @addtogroup LPSPI Low Power Serial Peripheral Interface Controller(LPSPI) 24 Memory Mapped Structure for LPSPI Controller 25 @{ */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var LPSPI_T::CTL 33 * Offset: 0x00 SPI Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |SPIEN |SPI Transfer Control Enable Bit 38 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 39 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. 40 * | | |0 = Transfer control Disabled. 41 * | | |1 = Transfer control Enabled. 42 * | | |Note: Before changing the configurations of LPSPI_CTL, LPSPI_CLKDIV, LPSPI_SSCTL and LPSPI_FIFOCTL registers, user shall clear the SPIEN (LPSPI_CTL[0]) and confirm the SPIENSTS (LPSPI_STATUS[15]) is 0. 43 * |[1] |RXNEG |Receive on Negative Edge 44 * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. 45 * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. 46 * |[2] |TXNEG |Transmit on Negative Edge 47 * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. 48 * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. 49 * |[3] |CLKPOL |Clock Polarity 50 * | | |0 = SPI bus clock is idle low. 51 * | | |1 = SPI bus clock is idle high. 52 * |[7:4] |SUSPITV |Suspend Interval 53 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer 54 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word 55 * | | |The default value is 0x3 56 * | | |The period of the suspend interval is obtained according to the following equation. 57 * | | |?(SUSPITV[3:0] + 0.5) * period of LPSPI_CLK clock cycle 58 * | | |Example: 59 * | | |SUSPITV = 0x0, it means 0.5 LPSPI_CLK clock cycle. 60 * | | |SUSPITV = 0x1, it means 1.5 LPSPI_CLK clock cycle. 61 * | | | ... 62 * | | |SUSPITV = 0xE, it means 14.5 LPSPI_CLK clock cycle. 63 * | | |SUSPITV = 0xF, it means 15.5 LPSPI_CLK clock cycle. 64 * | | |Note: These bits are for Master Mode only. 65 * |[12:8] |DWIDTH |Data Width 66 * | | |This field specifies how many bits can be transmitted/received in one transaction 67 * | | |The minimum bit length is 4 bits and can up to 32 bits. 68 * | | |DWIDTH = 0x04, it means 4 bits. 69 * | | |DWIDTH = 0x05, it means 5 bits. 70 * | | |DWIDTH = 0x06, it means 6 bits. 71 * | | |DWIDTH = 0x07, it means 7 bits. 72 * | | |DWIDTH = 0x08, it means 8 bits. 73 * | | |DWIDTH = 0x09, it means 9 bits. 74 * | | | ... 75 * | | |DWIDTH = 0x1F, it means 31 bits. 76 * | | |DWIDTH = 0x00, it means 32 bits. 77 * | | |Note: This bit field will decide the depth of TX/RX FIFO configuration in SPI mode 78 * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically. 79 * |[13] |LSB |Send LSB First 80 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. 81 * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of LPSPI_RX). 82 * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit 83 * | | |This bit is used to select full-duplex or half-duplex for SPI transfer 84 * | | |The bit field DATDIR (LPSPI_CTL[20]) can be used to set the data direction in half-duplex transfer. 85 * | | |0 = SPI operates in full-duplex transfer. 86 * | | |1 = SPI operates in half-duplex transfer. 87 * |[15] |RXONLY |Receive-only Mode Enable Bit 88 * | | |This bit field is only available in Master mode 89 * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 90 * | | |0 = Receive-only mode Disabled. 91 * | | |1 = Receive-only mode Enabled. 92 * | | |Note: This bit is for Master Mode only. 93 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit 94 * | | |0 = SPI unit transfer interrupt Disabled. 95 * | | |1 = SPI unit transfer interrupt Enabled. 96 * |[18] |SLAVE |Slave Mode Control 97 * | | |0 = Master mode. 98 * | | |1 = Slave mode. 99 * |[19] |REORDER |Byte Reorder Function Enable Bit 100 * | | |0 = Byte Reorder function Disabled. 101 * | | |1 = Byte Reorder function Enabled 102 * | | |A byte suspend interval will be inserted among each byte 103 * | | |The period of the byte suspend interval depends on the setting of SUSPITV. 104 * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 105 * |[20] |DATDIR |Data Port Direction Control 106 * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 107 * | | |0 = SPI data is input direction. 108 * | | |1 = SPI data is output direction. 109 * @var LPSPI_T::CLKDIV 110 * Offset: 0x04 SPI Clock Divider Register 111 * --------------------------------------------------------------------------------------------------- 112 * |Bits |Field |Descriptions 113 * | :----: | :----: | :---- | 114 * |[8:0] |DIVIDER |Clock Divider 115 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master 116 * | | |The frequency is obtained according to the following equation. 117 * | | | SPI_eclk = SPI_clk_src/(DIVIDER+1) 118 * | | |where 119 * | | |SPI_clk_src is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2 or CLK_CLKSEL3. 120 * | | |Note 1: The time interval must be larger than or equal to 8 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 121 * @var LPSPI_T::SSCTL 122 * Offset: 0x08 SPI Slave Select Control Register 123 * --------------------------------------------------------------------------------------------------- 124 * |Bits |Field |Descriptions 125 * | :----: | :----: | :---- | 126 * |[0] |SS |Slave Selection Control 127 * | | |If AUTOSS bit is cleared to 0, 128 * | | |0 = set the LPSPI_SS line to inactive state. 129 * | | |1 = set the LPSPI_SS line to active state. 130 * | | |If the AUTOSS bit is set to 1, 131 * | | |0 = Keep the LPSPI_SS line at inactive state. 132 * | | |1 = LPSPI_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time 133 * | | |The active state of LPSPI_SS is specified in SSACTPOL (LPSPI_SSCTL[2]). 134 * | | |Note: This bit is for Master Mode only. 135 * |[2] |SSACTPOL |Slave Selection Active Polarity 136 * | | |This bit defines the active polarity of slave selection signal (LPSPI_SS). 137 * | | |0 = The slave selection signal LPSPI_SS is active low. 138 * | | |1 = The slave selection signal LPSPI_SS is active high. 139 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit 140 * | | |0 = Automatic slave selection function Disabled 141 * | | |Slave selection signal will be asserted/de-asserted according to SS (LPSPI_SSCTL[0]). 142 * | | |1 = Automatic slave selection function Enabled. 143 * | | |Note: This bit is for Master Mode only. 144 * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit 145 * | | |In Slave 3-wire mode, the LPSPI controller can work with 3-wire interface including LPSPI_CLK, LPSPI_MISO and LPSPI_MOSI pins. 146 * | | |0 = 4-wire bi-direction interface. 147 * | | |1 = 3-wire bi-direction interface. 148 * | | |Note: This bit is for Slave Mode only. 149 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit 150 * | | |0 = Slave mode bit count error interrupt Disabled. 151 * | | |1 = Slave mode bit count error interrupt Enabled. 152 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit 153 * | | |0 = Slave mode TX under run interrupt Disabled. 154 * | | |1 = Slave mode TX under run interrupt Enabled. 155 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit 156 * | | |0 = Slave select active interrupt Disabled. 157 * | | |1 = Slave select active interrupt Enabled. 158 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit 159 * | | |0 = Slave select inactive interrupt Disabled. 160 * | | |1 = Slave select inactive interrupt Enabled. 161 * @var LPSPI_T::PDMACTL 162 * Offset: 0x0C SPI PDMA Control Register 163 * --------------------------------------------------------------------------------------------------- 164 * |Bits |Field |Descriptions 165 * | :----: | :----: | :---- | 166 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit 167 * | | |0 = Transmit PDMA function Disabled. 168 * | | |1 = Transmit PDMA function Enabled. 169 * | | |Note 1: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function 170 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. 171 * | | |Note 2: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, TX PDMA function cannot be disabled prior to RX PDMA function 172 * | | |User can disable RX PDMA function firstly or disable both functions simultaneously. 173 * |[1] |RXPDMAEN |Receive PDMA Enable Bit 174 * | | |0 = Receive PDMA function Disabled. 175 * | | |1 = Receive PDMA function Enabled. 176 * |[2] |PDMARST |PDMA Reset 177 * | | |0 = No effect. 178 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. 179 * @var LPSPI_T::FIFOCTL 180 * Offset: 0x10 SPI FIFO Control Register 181 * --------------------------------------------------------------------------------------------------- 182 * |Bits |Field |Descriptions 183 * | :----: | :----: | :---- | 184 * |[0] |RXRST |Receive Reset 185 * | | |0 = No effect. 186 * | | |1 = Reset receive FIFO pointer and receive circuit 187 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 188 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 189 * | | |User can read TXRXRST (LPSPI_STATUS[23]) to check if reset is accomplished or not. 190 * |[1] |TXRST |Transmit Reset 191 * | | |0 = No effect. 192 * | | |1 = Reset transmit FIFO pointer and transmit circuit 193 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 194 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 195 * | | |User can read TXRXRST (LPSPI_STATUS[23]) to check if reset is accomplished or not. 196 * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 197 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit 198 * | | |0 = RX FIFO threshold interrupt Disabled. 199 * | | |1 = RX FIFO threshold interrupt Enabled. 200 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit 201 * | | |0 = TX FIFO threshold interrupt Disabled. 202 * | | |1 = TX FIFO threshold interrupt Enabled. 203 * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit 204 * | | |0 = Receive time-out interrupt Disabled. 205 * | | |1 = Receive time-out interrupt Enabled. 206 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit 207 * | | |0 = Receive FIFO overrun interrupt Disabled. 208 * | | |1 = Receive FIFO overrun interrupt Enabled. 209 * |[6] |TXUFPOL |TX Underflow Data Polarity 210 * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. 211 * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. 212 * | | |Note 1: The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 213 * | | |Note 2: When TX underflow event occurs, LPSPI_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward 214 * | | |Data stored in TX FIFO will be sent through LPSPI_MISO pin in the next transfer frame. 215 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit 216 * | | |When TX underflow event occurs in Slave mode, TXUFIF (LPSPI_STATUS[19]) will be set to 1 217 * | | |This bit is used to enable the TX underflow interrupt. 218 * | | |0 = Slave TX underflow interrupt Disabled. 219 * | | |1 = Slave TX underflow interrupt Enabled. 220 * |[8] |RXFBCLR |Receive FIFO Buffer Clear 221 * | | |0 = No effect. 222 * | | |1 = Clear receive FIFO pointer 223 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 224 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 225 * | | |Note: The RX shift register will not be cleared. 226 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear 227 * | | |0 = No effect. 228 * | | |1 = Clear transmit FIFO pointer 229 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 230 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 231 * | | |Note: The TX shift register will not be cleared. 232 * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error 233 * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode. 234 * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode 235 * | | |User can read SLVBENUM (LPSPI_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. 236 * | | |Note: This bit is for Slave Mode only. 237 * |[26:24] |RXTH |Receive FIFO Threshold 238 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 239 * | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length. 240 * |[30:28] |TXTH |Transmit FIFO Threshold 241 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 242 * | | |The MSB of this bit field is only meaningful while SPI mode 4~16 bits of data length 243 * @var LPSPI_T::STATUS 244 * Offset: 0x14 SPI Status Register 245 * --------------------------------------------------------------------------------------------------- 246 * |Bits |Field |Descriptions 247 * | :----: | :----: | :---- | 248 * |[0] |BUSY |Busy Status (Read Only) 249 * | | |0 = LPSPI controller is in idle state. 250 * | | |1 = LPSPI controller is in busy state. 251 * | | |The following lists the bus busy conditions: 252 * | | |a. SPIEN (LPSPI_CTL[0]) = 1 and TXEMPTY = 0. 253 * | | |b 254 * | | |For SPI Master mode, SPIEN (LPSPI_CTL[0]) = 1 and TXEMPTY = 1 but the current transaction is not finished yet. 255 * | | |c. For SPI Master mode, SPIEN (LPSPI_CTL[0]) = 1 and RXONLY = 1. 256 * | | |d 257 * | | |For SPI Slave mode, SPIEN (LPSPI_CTL[0]) = 1 and there is serial clock input into the SPI core logic when slave select is active. 258 * | | |e 259 * | | |For SPI Slave mode, SPIEN (LPSPI_CTL[0]) = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. 260 * | | |Note: By applications, this SPI busy flag should be used with other status registers in LPSPI_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF 261 * | | |Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point. 262 * |[1] |UNITIF |Unit Transfer Interrupt Flag 263 * | | |0 = No transaction has been finished since this bit was cleared to 0. 264 * | | |1 = LPSPI controller has finished one unit transfer. 265 * | | |Note: This bit will be cleared by writing 1 to it. 266 * |[2] |SSACTIF |Slave Select Active Interrupt Flag 267 * | | |0 = Slave select active interrupt was cleared or not occurred. 268 * | | |1 = Slave select active interrupt event occurred. 269 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 270 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag 271 * | | |0 = Slave select inactive interrupt was cleared or not occurred. 272 * | | |1 = Slave select inactive interrupt event occurred. 273 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 274 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) 275 * | | |0 = The slave select line status is 0. 276 * | | |1 = The slave select line status is 1. 277 * | | |Note: This bit is only available in Slave mode 278 * | | |If SSACTPOL (LPSPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 279 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag 280 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. 281 * | | |0 = No Slave mode bit count error event. 282 * | | |1 = Slave mode bit count error event occurred. 283 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state 284 * | | |This bit will be cleared by writing 1 to it. 285 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag 286 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. 287 * | | |0 = No Slave TX under run event. 288 * | | |1 = Slave TX under run event occurred. 289 * | | |Note: This bit will be cleared by writing 1 to it. 290 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 291 * | | |0 = Receive FIFO buffer is not empty. 292 * | | |1 = Receive FIFO buffer is empty. 293 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 294 * | | |0 = Receive FIFO buffer is not full. 295 * | | |1 = Receive FIFO buffer is full. 296 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 297 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 298 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 299 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 300 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 301 * | | |0 = No FIFO is overrun. 302 * | | |1 = Receive FIFO is overrun. 303 * | | |Note: This bit will be cleared by writing 1 to it. 304 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 305 * | | |0 = No receive FIFO time-out event. 306 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode 307 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 308 * | | |Note: This bit will be cleared by writing 1 to it. 309 * |[15] |SPIENSTS |SPI Enable Status (Read Only) 310 * | | |0 = LPSPI controller Disabled. 311 * | | |1 = LPSPI controller Enabled. 312 * | | |Note: The SPI peripheral clock is asynchronous with the system clock 313 * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of LPSPI controller. 314 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 315 * | | |0 = Transmit FIFO buffer is not empty. 316 * | | |1 = Transmit FIFO buffer is empty. 317 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 318 * | | |0 = Transmit FIFO buffer is not full. 319 * | | |1 = Transmit FIFO buffer is full. 320 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 321 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 322 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 323 * |[19] |TXUFIF |TX Underflow Interrupt Flag 324 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. 325 * | | |0 = No effect. 326 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. 327 * | | |Note 1: This bit will be cleared by writing 1 to it. 328 * | | |Note 2: If reset the slave transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 329 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 330 * | | |0 = The reset function of TXRST or RXRST is done. 331 * | | |1 = Doing the reset function of TXRST or RXRST. 332 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 333 * | | |User can check the status of this bit to monitor the reset function is doing or done. 334 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) 335 * | | |This bit field indicates the valid data count of receive FIFO buffer. 336 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) 337 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 338 * @var LPSPI_T::STATUS2 339 * Offset: 0x18 SPI Status2 Register 340 * --------------------------------------------------------------------------------------------------- 341 * |Bits |Field |Descriptions 342 * | :----: | :----: | :---- | 343 * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX data 344 * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (LPSPI_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode. 345 * | | |This status register will be fixed to 0x0 when SLVBERX (LPSPI_FIFOCTL[10]) is disabled. 346 * | | |Note: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (LPSPI_STATUS[6]). 347 * | | |Note: This bit is for Slave Mode only. 348 * @var LPSPI_T::TX 349 * Offset: 0x20 SPI Data Transmit Register 350 * --------------------------------------------------------------------------------------------------- 351 * |Bits |Field |Descriptions 352 * | :----: | :----: | :---- | 353 * |[31:0] |TX |Data Transmit Register 354 * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers 355 * | | |The number of valid bits depends on the setting of DWIDTH (LPSPI_CTL[12:8]) in SPI mode. 356 * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted 357 * | | |If DWIDTH is set to 0x00, the LPSPI controller will perform a 32-bit transfer. 358 * | | |Note: In Master mode, LPSPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 359 * @var LPSPI_T::RX 360 * Offset: 0x30 SPI Data Receive Register 361 * --------------------------------------------------------------------------------------------------- 362 * |Bits |Field |Descriptions 363 * | :----: | :----: | :---- | 364 * |[31:0] |RX |Data Receive Register (Read Only) 365 * | | |There are 4-level FIFO buffers in this controller 366 * | | |The data receive register holds the data received from SPI data input pin 367 * | | |If the RXEMPTY (LPSPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 368 * @var LPSPI_T::AUTOCTL 369 * Offset: 0x50 LPSPI Automatic Operation Control Register 370 * --------------------------------------------------------------------------------------------------- 371 * |Bits |Field |Descriptions 372 * | :----: | :----: | :---- | 373 * |[3:0] |TRIGSEL |Automatic Operation Trigger Source Select 374 * | | |0000 = Low Power Auto-operation Trigger Source from LPTMR0. 375 * | | |0001 = Low Power Auto-operation Trigger Source from LPTMR1. 376 * | | |0010 = Low Power Auto-operation Trigger Source from TTMR0. 377 * | | |0011 = Low Power Auto-operation Trigger Source from TTMR1. 378 * | | |0100 = Low Power Auto-operation Trigger Source from LPGPIO0 (PA.0). 379 * | | |0101 = Low Power Auto-operation Trigger Source from LPGPIO1 (PB.0). 380 * | | |0110 = Low Power Auto-operation Trigger Source from LPGPIO2 (PC.0). 381 * | | |0111 = Low Power Auto-operation Trigger Source from LPGPIO3 (PD.0). 382 * | | |1000~1111 = Reserved. 383 * |[4] |TRIGEN |Automatic Operation Trigger Enable Bit 384 * | | |In Auomatic Operation Master mode, the automatic operation of LPSPI will be triggered by an event sent from the trigger source selected by TRIGSEL[3:0] after this bit is set to 1. 385 * | | |0 = LPSPI Automatic Operation Trigger disabled. 386 * | | |1 = LPSPI Automatic Operation Trigger enabled. 387 * |[5] |CNTIEN |TCNT Count Match Interrupt Enable 388 * | | |0 = TCNT count match interrupt disabled. 389 * | | |1 = TCNT count match interrupt enabled. 390 * |[6] |FULLRXEN |Full RX Data Acception Enable Bit 391 * | | |In Auomatic Operation Master mode and LPSPI operates in full-duplex mode, the RX data will be saved from RX buffer by LPPDMA while in TX Phase after this bit is set to 1. 392 * |[7] |SSWKEN |Slave Select Wake Up Enable Bit 393 * | | |In Slave mode, the CPU will be woken up by SS falling or rising edge in NPDx mode after this bit is set to 1. 394 * | | |0 = LPSPI SS wake-up function disabled. 395 * | | |1 = LPSPI SS wake-up function enabled. 396 * |[8] |AUTOEN |Automatic Operation Mode Enable Bit 397 * | | |0 = Automatic operation master mode disabled. 398 * | | |1 = Automatic operation master mode enabled. 399 * |[9] |SWTRIG |Software Trigger (Write Only) 400 * | | |After AUTOEN set to 1, software can manually trigger the Automatic Operation Master mode by writing 1 to this bit. 401 * |[10] |CNTWKEN |TCNT Count Match Wake Up Enable Bit 402 * | | |0 = TCNT count match wake-up function disabled. 403 * | | |1 = TCNT count match wake-up function enabled. 404 * |[23:16] |TCNT |Auomatic Operation RX Transfer Count 405 * | | |In Auomatic Operation Master mode, TCNT represents the required number of RX data received from external SPI slave device while in RX Phase 406 * | | |The maximum transfer count is 255. 407 * @var LPSPI_T::AUTOSTS 408 * Offset: 0x54 LPSPI Automatic Operation Status Register 409 * --------------------------------------------------------------------------------------------------- 410 * |Bits |Field |Descriptions 411 * | :----: | :----: | :---- | 412 * |[0] |CNTIF |TCNT Count Match Interrupt Flag 413 * | | |When the received data count matchs the setting value of TCNT, this bit will be set to 1. 414 * | | |0 = The received data count is less than the setting value of TCNT. 415 * | | |1 = The received data count is equal than the setting value of TCNT. 416 * |[1] |SSWKF |Slave Select Wake Up Flag 417 * | | |In Slave mode, when chip is woken up from NPDx mode by LPSPI, this bit is set to 1 418 * | | |Software can write 1 to clear this bit. 419 * |[2] |AOBUSY |Automatic Operation Busy Flag 420 * | | |When there were one or more requests from trigger sources during auto operation, this bit will be set to 1 421 * | | |Software can write 1 to clear this bit. 422 * |[3] |CNTWKF |TCNT Count Match Wake Up Flag 423 * | | |When chip is woken up due to the received data count matching the setting value of TCNT, this bit will be set to 1. 424 * | | |Software can write 1 to clear this bit. 425 */ 426 __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ 427 __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ 428 __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ 429 __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ 430 __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ 431 __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ 432 __IO uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */ 433 __I uint32_t RESERVE0[1]; 434 __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ 435 __I uint32_t RESERVE1[3]; 436 __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ 437 __I uint32_t RESERVE2[7]; 438 __IO uint32_t AUTOCTL; /*!< [0x0050] LPSPI Automatic Operation Control Register */ 439 __IO uint32_t AUTOSTS; /*!< [0x0054] LPSPI Automatic Operation Status Register */ 440 441 } LPSPI_T; 442 443 /** 444 @addtogroup LPSPI_CONST LPSPI Bit Field Definition 445 Constant Definitions for LPSPI Controller 446 @{ */ 447 448 #define LPSPI_CTL_SPIEN_Pos (0) /*!< LPSPI_T::CTL: SPIEN Position */ 449 #define LPSPI_CTL_SPIEN_Msk (0x1ul << LPSPI_CTL_SPIEN_Pos) /*!< LPSPI_T::CTL: SPIEN Mask */ 450 451 #define LPSPI_CTL_RXNEG_Pos (1) /*!< LPSPI_T::CTL: RXNEG Position */ 452 #define LPSPI_CTL_RXNEG_Msk (0x1ul << LPSPI_CTL_RXNEG_Pos) /*!< LPSPI_T::CTL: RXNEG Mask */ 453 454 #define LPSPI_CTL_TXNEG_Pos (2) /*!< LPSPI_T::CTL: TXNEG Position */ 455 #define LPSPI_CTL_TXNEG_Msk (0x1ul << LPSPI_CTL_TXNEG_Pos) /*!< LPSPI_T::CTL: TXNEG Mask */ 456 457 #define LPSPI_CTL_CLKPOL_Pos (3) /*!< LPSPI_T::CTL: CLKPOL Position */ 458 #define LPSPI_CTL_CLKPOL_Msk (0x1ul << LPSPI_CTL_CLKPOL_Pos) /*!< LPSPI_T::CTL: CLKPOL Mask */ 459 460 #define LPSPI_CTL_SUSPITV_Pos (4) /*!< LPSPI_T::CTL: SUSPITV Position */ 461 #define LPSPI_CTL_SUSPITV_Msk (0xful << LPSPI_CTL_SUSPITV_Pos) /*!< LPSPI_T::CTL: SUSPITV Mask */ 462 463 #define LPSPI_CTL_DWIDTH_Pos (8) /*!< LPSPI_T::CTL: DWIDTH Position */ 464 #define LPSPI_CTL_DWIDTH_Msk (0x1ful << LPSPI_CTL_DWIDTH_Pos) /*!< LPSPI_T::CTL: DWIDTH Mask */ 465 466 #define LPSPI_CTL_LSB_Pos (13) /*!< LPSPI_T::CTL: LSB Position */ 467 #define LPSPI_CTL_LSB_Msk (0x1ul << LPSPI_CTL_LSB_Pos) /*!< LPSPI_T::CTL: LSB Mask */ 468 469 #define LPSPI_CTL_HALFDPX_Pos (14) /*!< LPSPI_T::CTL: HALFDPX Position */ 470 #define LPSPI_CTL_HALFDPX_Msk (0x1ul << LPSPI_CTL_HALFDPX_Pos) /*!< LPSPI_T::CTL: HALFDPX Mask */ 471 472 #define LPSPI_CTL_RXONLY_Pos (15) /*!< LPSPI_T::CTL: RXONLY Position */ 473 #define LPSPI_CTL_RXONLY_Msk (0x1ul << LPSPI_CTL_RXONLY_Pos) /*!< LPSPI_T::CTL: RXONLY Mask */ 474 475 #define LPSPI_CTL_UNITIEN_Pos (17) /*!< LPSPI_T::CTL: UNITIEN Position */ 476 #define LPSPI_CTL_UNITIEN_Msk (0x1ul << LPSPI_CTL_UNITIEN_Pos) /*!< LPSPI_T::CTL: UNITIEN Mask */ 477 478 #define LPSPI_CTL_SLAVE_Pos (18) /*!< LPSPI_T::CTL: SLAVE Position */ 479 #define LPSPI_CTL_SLAVE_Msk (0x1ul << LPSPI_CTL_SLAVE_Pos) /*!< LPSPI_T::CTL: SLAVE Mask */ 480 481 #define LPSPI_CTL_REORDER_Pos (19) /*!< LPSPI_T::CTL: REORDER Position */ 482 #define LPSPI_CTL_REORDER_Msk (0x1ul << LPSPI_CTL_REORDER_Pos) /*!< LPSPI_T::CTL: REORDER Mask */ 483 484 #define LPSPI_CTL_DATDIR_Pos (20) /*!< LPSPI_T::CTL: DATDIR Position */ 485 #define LPSPI_CTL_DATDIR_Msk (0x1ul << LPSPI_CTL_DATDIR_Pos) /*!< LPSPI_T::CTL: DATDIR Mask */ 486 487 #define LPSPI_CLKDIV_DIVIDER_Pos (0) /*!< LPSPI_T::CLKDIV: DIVIDER Position */ 488 #define LPSPI_CLKDIV_DIVIDER_Msk (0x1fful << LPSPI_CLKDIV_DIVIDER_Pos) /*!< LPSPI_T::CLKDIV: DIVIDER Mask */ 489 490 #define LPSPI_SSCTL_SS_Pos (0) /*!< LPSPI_T::SSCTL: SS Position */ 491 #define LPSPI_SSCTL_SS_Msk (0x1ul << LPSPI_SSCTL_SS_Pos) /*!< LPSPI_T::SSCTL: SS Mask */ 492 493 #define LPSPI_SSCTL_SSACTPOL_Pos (2) /*!< LPSPI_T::SSCTL: SSACTPOL Position */ 494 #define LPSPI_SSCTL_SSACTPOL_Msk (0x1ul << LPSPI_SSCTL_SSACTPOL_Pos) /*!< LPSPI_T::SSCTL: SSACTPOL Mask */ 495 496 #define LPSPI_SSCTL_AUTOSS_Pos (3) /*!< LPSPI_T::SSCTL: AUTOSS Position */ 497 #define LPSPI_SSCTL_AUTOSS_Msk (0x1ul << LPSPI_SSCTL_AUTOSS_Pos) /*!< LPSPI_T::SSCTL: AUTOSS Mask */ 498 499 #define LPSPI_SSCTL_SLV3WIRE_Pos (4) /*!< LPSPI_T::SSCTL: SLV3WIRE Position */ 500 #define LPSPI_SSCTL_SLV3WIRE_Msk (0x1ul << LPSPI_SSCTL_SLV3WIRE_Pos) /*!< LPSPI_T::SSCTL: SLV3WIRE Mask */ 501 502 #define LPSPI_SSCTL_SLVBEIEN_Pos (8) /*!< LPSPI_T::SSCTL: SLVBEIEN Position */ 503 #define LPSPI_SSCTL_SLVBEIEN_Msk (0x1ul << LPSPI_SSCTL_SLVBEIEN_Pos) /*!< LPSPI_T::SSCTL: SLVBEIEN Mask */ 504 505 #define LPSPI_SSCTL_SLVURIEN_Pos (9) /*!< LPSPI_T::SSCTL: SLVURIEN Position */ 506 #define LPSPI_SSCTL_SLVURIEN_Msk (0x1ul << LPSPI_SSCTL_SLVURIEN_Pos) /*!< LPSPI_T::SSCTL: SLVURIEN Mask */ 507 508 #define LPSPI_SSCTL_SSACTIEN_Pos (12) /*!< LPSPI_T::SSCTL: SSACTIEN Position */ 509 #define LPSPI_SSCTL_SSACTIEN_Msk (0x1ul << LPSPI_SSCTL_SSACTIEN_Pos) /*!< LPSPI_T::SSCTL: SSACTIEN Mask */ 510 511 #define LPSPI_SSCTL_SSINAIEN_Pos (13) /*!< LPSPI_T::SSCTL: SSINAIEN Position */ 512 #define LPSPI_SSCTL_SSINAIEN_Msk (0x1ul << LPSPI_SSCTL_SSINAIEN_Pos) /*!< LPSPI_T::SSCTL: SSINAIEN Mask */ 513 514 #define LPSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< LPSPI_T::PDMACTL: TXPDMAEN Position */ 515 #define LPSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << LPSPI_PDMACTL_TXPDMAEN_Pos) /*!< LPSPI_T::PDMACTL: TXPDMAEN Mask */ 516 517 #define LPSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< LPSPI_T::PDMACTL: RXPDMAEN Position */ 518 #define LPSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << LPSPI_PDMACTL_RXPDMAEN_Pos) /*!< LPSPI_T::PDMACTL: RXPDMAEN Mask */ 519 520 #define LPSPI_PDMACTL_PDMARST_Pos (2) /*!< LPSPI_T::PDMACTL: PDMARST Position */ 521 #define LPSPI_PDMACTL_PDMARST_Msk (0x1ul << LPSPI_PDMACTL_PDMARST_Pos) /*!< LPSPI_T::PDMACTL: PDMARST Mask */ 522 523 #define LPSPI_FIFOCTL_RXRST_Pos (0) /*!< LPSPI_T::FIFOCTL: RXRST Position */ 524 #define LPSPI_FIFOCTL_RXRST_Msk (0x1ul << LPSPI_FIFOCTL_RXRST_Pos) /*!< LPSPI_T::FIFOCTL: RXRST Mask */ 525 526 #define LPSPI_FIFOCTL_TXRST_Pos (1) /*!< LPSPI_T::FIFOCTL: TXRST Position */ 527 #define LPSPI_FIFOCTL_TXRST_Msk (0x1ul << LPSPI_FIFOCTL_TXRST_Pos) /*!< LPSPI_T::FIFOCTL: TXRST Mask */ 528 529 #define LPSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< LPSPI_T::FIFOCTL: RXTHIEN Position */ 530 #define LPSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << LPSPI_FIFOCTL_RXTHIEN_Pos) /*!< LPSPI_T::FIFOCTL: RXTHIEN Mask */ 531 532 #define LPSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< LPSPI_T::FIFOCTL: TXTHIEN Position */ 533 #define LPSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << LPSPI_FIFOCTL_TXTHIEN_Pos) /*!< LPSPI_T::FIFOCTL: TXTHIEN Mask */ 534 535 #define LPSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< LPSPI_T::FIFOCTL: RXTOIEN Position */ 536 #define LPSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << LPSPI_FIFOCTL_RXTOIEN_Pos) /*!< LPSPI_T::FIFOCTL: RXTOIEN Mask */ 537 538 #define LPSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< LPSPI_T::FIFOCTL: RXOVIEN Position */ 539 #define LPSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << LPSPI_FIFOCTL_RXOVIEN_Pos) /*!< LPSPI_T::FIFOCTL: RXOVIEN Mask */ 540 541 #define LPSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< LPSPI_T::FIFOCTL: TXUFPOL Position */ 542 #define LPSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << LPSPI_FIFOCTL_TXUFPOL_Pos) /*!< LPSPI_T::FIFOCTL: TXUFPOL Mask */ 543 544 #define LPSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< LPSPI_T::FIFOCTL: TXUFIEN Position */ 545 #define LPSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << LPSPI_FIFOCTL_TXUFIEN_Pos) /*!< LPSPI_T::FIFOCTL: TXUFIEN Mask */ 546 547 #define LPSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< LPSPI_T::FIFOCTL: RXFBCLR Position */ 548 #define LPSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << LPSPI_FIFOCTL_RXFBCLR_Pos) /*!< LPSPI_T::FIFOCTL: RXFBCLR Mask */ 549 550 #define LPSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< LPSPI_T::FIFOCTL: TXFBCLR Position */ 551 #define LPSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << LPSPI_FIFOCTL_TXFBCLR_Pos) /*!< LPSPI_T::FIFOCTL: TXFBCLR Mask */ 552 553 #define LPSPI_FIFOCTL_SLVBERX_Pos (10) /*!< LPSPI_T::FIFOCTL: SLVBERX Position */ 554 #define LPSPI_FIFOCTL_SLVBERX_Msk (0x1ul << LPSPI_FIFOCTL_SLVBERX_Pos) /*!< LPSPI_T::FIFOCTL: SLVBERX Mask */ 555 556 #define LPSPI_FIFOCTL_RXTH_Pos (24) /*!< LPSPI_T::FIFOCTL: RXTH Position */ 557 #define LPSPI_FIFOCTL_RXTH_Msk (0x7ul << LPSPI_FIFOCTL_RXTH_Pos) /*!< LPSPI_T::FIFOCTL: RXTH Mask */ 558 559 #define LPSPI_FIFOCTL_TXTH_Pos (28) /*!< LPSPI_T::FIFOCTL: TXTH Position */ 560 #define LPSPI_FIFOCTL_TXTH_Msk (0x7ul << LPSPI_FIFOCTL_TXTH_Pos) /*!< LPSPI_T::FIFOCTL: TXTH Mask */ 561 562 #define LPSPI_STATUS_BUSY_Pos (0) /*!< LPSPI_T::STATUS: BUSY Position */ 563 #define LPSPI_STATUS_BUSY_Msk (0x1ul << LPSPI_STATUS_BUSY_Pos) /*!< LPSPI_T::STATUS: BUSY Mask */ 564 565 #define LPSPI_STATUS_UNITIF_Pos (1) /*!< LPSPI_T::STATUS: UNITIF Position */ 566 #define LPSPI_STATUS_UNITIF_Msk (0x1ul << LPSPI_STATUS_UNITIF_Pos) /*!< LPSPI_T::STATUS: UNITIF Mask */ 567 568 #define LPSPI_STATUS_SSACTIF_Pos (2) /*!< LPSPI_T::STATUS: SSACTIF Position */ 569 #define LPSPI_STATUS_SSACTIF_Msk (0x1ul << LPSPI_STATUS_SSACTIF_Pos) /*!< LPSPI_T::STATUS: SSACTIF Mask */ 570 571 #define LPSPI_STATUS_SSINAIF_Pos (3) /*!< LPSPI_T::STATUS: SSINAIF Position */ 572 #define LPSPI_STATUS_SSINAIF_Msk (0x1ul << LPSPI_STATUS_SSINAIF_Pos) /*!< LPSPI_T::STATUS: SSINAIF Mask */ 573 574 #define LPSPI_STATUS_SSLINE_Pos (4) /*!< LPSPI_T::STATUS: SSLINE Position */ 575 #define LPSPI_STATUS_SSLINE_Msk (0x1ul << LPSPI_STATUS_SSLINE_Pos) /*!< LPSPI_T::STATUS: SSLINE Mask */ 576 577 #define LPSPI_STATUS_SLVBEIF_Pos (6) /*!< LPSPI_T::STATUS: SLVBEIF Position */ 578 #define LPSPI_STATUS_SLVBEIF_Msk (0x1ul << LPSPI_STATUS_SLVBEIF_Pos) /*!< LPSPI_T::STATUS: SLVBEIF Mask */ 579 580 #define LPSPI_STATUS_SLVURIF_Pos (7) /*!< LPSPI_T::STATUS: SLVURIF Position */ 581 #define LPSPI_STATUS_SLVURIF_Msk (0x1ul << LPSPI_STATUS_SLVURIF_Pos) /*!< LPSPI_T::STATUS: SLVURIF Mask */ 582 583 #define LPSPI_STATUS_RXEMPTY_Pos (8) /*!< LPSPI_T::STATUS: RXEMPTY Position */ 584 #define LPSPI_STATUS_RXEMPTY_Msk (0x1ul << LPSPI_STATUS_RXEMPTY_Pos) /*!< LPSPI_T::STATUS: RXEMPTY Mask */ 585 586 #define LPSPI_STATUS_RXFULL_Pos (9) /*!< LPSPI_T::STATUS: RXFULL Position */ 587 #define LPSPI_STATUS_RXFULL_Msk (0x1ul << LPSPI_STATUS_RXFULL_Pos) /*!< LPSPI_T::STATUS: RXFULL Mask */ 588 589 #define LPSPI_STATUS_RXTHIF_Pos (10) /*!< LPSPI_T::STATUS: RXTHIF Position */ 590 #define LPSPI_STATUS_RXTHIF_Msk (0x1ul << LPSPI_STATUS_RXTHIF_Pos) /*!< LPSPI_T::STATUS: RXTHIF Mask */ 591 592 #define LPSPI_STATUS_RXOVIF_Pos (11) /*!< LPSPI_T::STATUS: RXOVIF Position */ 593 #define LPSPI_STATUS_RXOVIF_Msk (0x1ul << LPSPI_STATUS_RXOVIF_Pos) /*!< LPSPI_T::STATUS: RXOVIF Mask */ 594 595 #define LPSPI_STATUS_RXTOIF_Pos (12) /*!< LPSPI_T::STATUS: RXTOIF Position */ 596 #define LPSPI_STATUS_RXTOIF_Msk (0x1ul << LPSPI_STATUS_RXTOIF_Pos) /*!< LPSPI_T::STATUS: RXTOIF Mask */ 597 598 #define LPSPI_STATUS_SPIENSTS_Pos (15) /*!< LPSPI_T::STATUS: SPIENSTS Position */ 599 #define LPSPI_STATUS_SPIENSTS_Msk (0x1ul << LPSPI_STATUS_SPIENSTS_Pos) /*!< LPSPI_T::STATUS: SPIENSTS Mask */ 600 601 #define LPSPI_STATUS_TXEMPTY_Pos (16) /*!< LPSPI_T::STATUS: TXEMPTY Position */ 602 #define LPSPI_STATUS_TXEMPTY_Msk (0x1ul << LPSPI_STATUS_TXEMPTY_Pos) /*!< LPSPI_T::STATUS: TXEMPTY Mask */ 603 604 #define LPSPI_STATUS_TXFULL_Pos (17) /*!< LPSPI_T::STATUS: TXFULL Position */ 605 #define LPSPI_STATUS_TXFULL_Msk (0x1ul << LPSPI_STATUS_TXFULL_Pos) /*!< LPSPI_T::STATUS: TXFULL Mask */ 606 607 #define LPSPI_STATUS_TXTHIF_Pos (18) /*!< LPSPI_T::STATUS: TXTHIF Position */ 608 #define LPSPI_STATUS_TXTHIF_Msk (0x1ul << LPSPI_STATUS_TXTHIF_Pos) /*!< LPSPI_T::STATUS: TXTHIF Mask */ 609 610 #define LPSPI_STATUS_TXUFIF_Pos (19) /*!< LPSPI_T::STATUS: TXUFIF Position */ 611 #define LPSPI_STATUS_TXUFIF_Msk (0x1ul << LPSPI_STATUS_TXUFIF_Pos) /*!< LPSPI_T::STATUS: TXUFIF Mask */ 612 613 #define LPSPI_STATUS_TXRXRST_Pos (23) /*!< LPSPI_T::STATUS: TXRXRST Position */ 614 #define LPSPI_STATUS_TXRXRST_Msk (0x1ul << LPSPI_STATUS_TXRXRST_Pos) /*!< LPSPI_T::STATUS: TXRXRST Mask */ 615 616 #define LPSPI_STATUS_RXCNT_Pos (24) /*!< LPSPI_T::STATUS: RXCNT Position */ 617 #define LPSPI_STATUS_RXCNT_Msk (0xful << LPSPI_STATUS_RXCNT_Pos) /*!< LPSPI_T::STATUS: RXCNT Mask */ 618 619 #define LPSPI_STATUS_TXCNT_Pos (28) /*!< LPSPI_T::STATUS: TXCNT Position */ 620 #define LPSPI_STATUS_TXCNT_Msk (0xful << LPSPI_STATUS_TXCNT_Pos) /*!< LPSPI_T::STATUS: TXCNT Mask */ 621 622 #define LPSPI_STATUS2_SLVBENUM_Pos (24) /*!< LPSPI_T::STATUS2: SLVBENUM Position */ 623 #define LPSPI_STATUS2_SLVBENUM_Msk (0x3ful << LPSPI_STATUS2_SLVBENUM_Pos) /*!< LPSPI_T::STATUS2: SLVBENUM Mask */ 624 625 #define LPSPI_TX_TX_Pos (0) /*!< LPSPI_T::TX: TX Position */ 626 #define LPSPI_TX_TX_Msk (0xfffffffful << LPSPI_TX_TX_Pos) /*!< LPSPI_T::TX: TX Mask */ 627 628 #define LPSPI_RX_RX_Pos (0) /*!< LPSPI_T::RX: RX Position */ 629 #define LPSPI_RX_RX_Msk (0xfffffffful << LPSPI_RX_RX_Pos) /*!< LPSPI_T::RX: RX Mask */ 630 631 #define LPSPI_AUTOCTL_TRIGSEL_Pos (0) /*!< LPSPI_T::AUTOCTL: TRIGSEL Position */ 632 #define LPSPI_AUTOCTL_TRIGSEL_Msk (0xful << LPSPI_AUTOCTL_TRIGSEL_Pos) /*!< LPSPI_T::AUTOCTL: TRIGSEL Mask */ 633 634 #define LPSPI_AUTOCTL_TRIGEN_Pos (4) /*!< LPSPI_T::AUTOCTL: TRIGEN Position */ 635 #define LPSPI_AUTOCTL_TRIGEN_Msk (0x1ul << LPSPI_AUTOCTL_TRIGEN_Pos) /*!< LPSPI_T::AUTOCTL: TRIGEN Mask */ 636 637 #define LPSPI_AUTOCTL_CNTIEN_Pos (5) /*!< LPSPI_T::AUTOCTL: CNTIEN Position */ 638 #define LPSPI_AUTOCTL_CNTIEN_Msk (0x1ul << LPSPI_AUTOCTL_CNTIEN_Pos) /*!< LPSPI_T::AUTOCTL: CNTIEN Mask */ 639 640 #define LPSPI_AUTOCTL_FULLRXEN_Pos (6) /*!< LPSPI_T::AUTOCTL: FULLRXEN Position */ 641 #define LPSPI_AUTOCTL_FULLRXEN_Msk (0x1ul << LPSPI_AUTOCTL_FULLRXEN_Pos) /*!< LPSPI_T::AUTOCTL: FULLRXEN Mask */ 642 643 #define LPSPI_AUTOCTL_SSWKEN_Pos (7) /*!< LPSPI_T::AUTOCTL: SSWKEN Position */ 644 #define LPSPI_AUTOCTL_SSWKEN_Msk (0x1ul << LPSPI_AUTOCTL_SSWKEN_Pos) /*!< LPSPI_T::AUTOCTL: SSWKEN Mask */ 645 646 #define LPSPI_AUTOCTL_AUTOEN_Pos (8) /*!< LPSPI_T::AUTOCTL: AUTOEN Position */ 647 #define LPSPI_AUTOCTL_AUTOEN_Msk (0x1ul << LPSPI_AUTOCTL_AUTOEN_Pos) /*!< LPSPI_T::AUTOCTL: AUTOEN Mask */ 648 649 #define LPSPI_AUTOCTL_SWTRIG_Pos (9) /*!< LPSPI_T::AUTOCTL: SWTRIG Position */ 650 #define LPSPI_AUTOCTL_SWTRIG_Msk (0x1ul << LPSPI_AUTOCTL_SWTRIG_Pos) /*!< LPSPI_T::AUTOCTL: SWTRIG Mask */ 651 652 #define LPSPI_AUTOCTL_CNTWKEN_Pos (10) /*!< LPSPI_T::AUTOCTL: CNTWKEN Position */ 653 #define LPSPI_AUTOCTL_CNTWKEN_Msk (0x1ul << LPSPI_AUTOCTL_CNTWKEN_Pos) /*!< LPSPI_T::AUTOCTL: CNTWKEN Mask */ 654 655 #define LPSPI_AUTOCTL_TCNT_Pos (16) /*!< LPSPI_T::AUTOCTL: TCNT Position */ 656 #define LPSPI_AUTOCTL_TCNT_Msk (0xfful << LPSPI_AUTOCTL_TCNT_Pos) /*!< LPSPI_T::AUTOCTL: TCNT Mask */ 657 658 #define LPSPI_AUTOSTS_CNTIF_Pos (0) /*!< LPSPI_T::AUTOSTS: CNTIF Position */ 659 #define LPSPI_AUTOSTS_CNTIF_Msk (0x1ul << LPSPI_AUTOSTS_CNTIF_Pos) /*!< LPSPI_T::AUTOSTS: CNTIF Mask */ 660 661 #define LPSPI_AUTOSTS_SSWKF_Pos (1) /*!< LPSPI_T::AUTOSTS: SSWKF Position */ 662 #define LPSPI_AUTOSTS_SSWKF_Msk (0x1ul << LPSPI_AUTOSTS_SSWKF_Pos) /*!< LPSPI_T::AUTOSTS: SSWKF Mask */ 663 664 #define LPSPI_AUTOSTS_AOBUSY_Pos (2) /*!< LPSPI_T::AUTOSTS: AOBUSY Position */ 665 #define LPSPI_AUTOSTS_AOBUSY_Msk (0x1ul << LPSPI_AUTOSTS_AOBUSY_Pos) /*!< LPSPI_T::AUTOSTS: AOBUSY Mask */ 666 667 #define LPSPI_AUTOSTS_CNTWKF_Pos (3) /*!< LPSPI_T::AUTOSTS: CNTWKF Position */ 668 #define LPSPI_AUTOSTS_CNTWKF_Msk (0x1ul << LPSPI_AUTOSTS_CNTWKF_Pos) /*!< LPSPI_T::AUTOSTS: CNTWKF Mask */ 669 670 /**@}*/ /* LPSPI_CONST */ 671 /**@}*/ /* end of LPSPI register group */ 672 /**@}*/ /* end of REGISTER group */ 673 #if defined ( __CC_ARM ) 674 #pragma no_anon_unions 675 #endif 676 677 #endif /* __LPSPI_REG_H__ */ 678
