1 /**************************************************************************//** 2 * @file sys_reg.h 3 * @version V1.00 4 * @brief SYS register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SYS_REG_H__ 10 #define __SYS_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup LPSCC Low Power System and Clock Controller (LPSCC) 23 Memory Mapped Structure for LPSCC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var LPSCC_T::IPRST0 32 * Offset: 0x04 Peripheral Reset Control Register 0 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |LPPDMA0RST|LPPDMA0 Controller Reset 37 * | | |0 = LPPDMA0 controller normal operation. 38 * | | |1 = LPPDMA0 controller reset. 39 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 40 * |[1] |LPGPIORST |LPGPIO Controller Reset 41 * | | |0 = LPGPIO controller normal operation. 42 * | | |1 = LPGPIO controller reset. 43 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 44 * |[2] |LPSRAMRST |LPSRAM Controller Reset 45 * | | |0 = LPSRAM controller normal operation. 46 * | | |1 = LPSRAM controller reset. 47 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 48 * |[16] |WDTRST |WDT Controller Reset 49 * | | |0 = WDT controller normal operation. 50 * | | |1 = WDT controller reset. 51 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 52 * |[17] |LPSPI0RST |LPSPI0 Controller Reset 53 * | | |0 = LPSPI0 controller normal operation. 54 * | | |1 = LPSPI0 controller reset. 55 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 56 * |[18] |LPI2C0RST |LPI2C0 Controller Reset 57 * | | |0 = LPI2C0 controller normal operation. 58 * | | |1 = LPI2C0 controller reset. 59 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 60 * |[19] |LPUART0RST|LPUART0 Controller Reset 61 * | | |0 = LPUART0 controller normal operation. 62 * | | |1 = LPUART0 controller reset. 63 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 64 * |[20] |LPTMR0RST |LPTMR0 Controller Reset 65 * | | |0 = LPTMR0 controller normal operation. 66 * | | |1 = LPTMR0 controller reset. 67 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 68 * |[21] |LPTMR1RST |LPTMR1 Controller Reset 69 * | | |0 = LPTMR1 controller normal operation. 70 * | | |1 = LPTMR1 controller reset. 71 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 72 * |[22] |TTMR0RST |TTMR0 Controller Reset 73 * | | |0 = TTMR0 controller normal operation. 74 * | | |1 = TTMR0 controller reset. 75 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 76 * |[23] |TTMR1RST |TTMR1 Controller Reset 77 * | | |0 = TTMR1 controller normal operation. 78 * | | |1 = TTMR1 controller reset. 79 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 80 * |[24] |LPADC0RST |LPADC0 Controller Reset 81 * | | |0 = LPADC0 controller normal operation. 82 * | | |1 = LPADC0 controller reset. 83 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 84 * |[27] |OPARST |OP Amplifier Controller Reset 85 * | | |0 = OPA controller normal operation. 86 * | | |1 = OPA controller reset. 87 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 88 * @var LPSCC_T::CLKEN0 89 * Offset: 0x40 Peripheral Clock Enable Control Register 0 90 * --------------------------------------------------------------------------------------------------- 91 * |Bits |Field |Descriptions 92 * | :----: | :----: | :---- | 93 * |[0] |LPPDMA0CKEN|LPPDMA0 Clock Enable Bit 94 * | | |0 = LPPDMA0 clock Disabled. 95 * | | |1 = LPPDMA0 clock Enabled. 96 * |[1] |LPGPIOCKEN|LPGPIO Clock Enable Bit 97 * | | |0 = LPGPIO clock Disabled. 98 * | | |1 = LPGPIO clock Enabled. 99 * |[2] |LPSRAMCKEN|LPSRAM Clock Enable Bit 100 * | | |0 = LPSRAM clock Disabled. 101 * | | |1 = LPSRAM clock Enabled. 102 * |[16] |WDTCKEN |WDT Clock Enable Bit 103 * | | |0 = WDT clock Disabled. 104 * | | |1 = WDT clock Enabled. 105 * |[17] |LPSPI0CKEN|LPSPI0 Clock Enable Bit 106 * | | |0 = LPSPI0 clock Disabled. 107 * | | |1 = LPSPI0 clock Enabled. 108 * |[18] |LPI2C0CKEN|LPI2C0 Clock Enable Bit 109 * | | |0 = LPI2C0 clock Disabled. 110 * | | |1 = LPI2C0 clock Enabled. 111 * |[19] |LPUART0CKEN|LPUART0 Clock Enable Bit 112 * | | |0 = LPUART0 clock Disabled. 113 * | | |1 = LPUART0 clock Enabled. 114 * |[20] |LPTMR0CKEN|LPTMR0 Clock Enable Bit 115 * | | |0 = LPTMR0 clock Disabled. 116 * | | |1 = LPTMR0 clock Enabled. 117 * |[21] |LPTMR1CKEN|LPTMR1 Clock Enable Bit 118 * | | |0 = LPTMR1 clock Disabled. 119 * | | |1 = LPTMR1 clock Enabled. 120 * |[22] |TTMR0CKEN |TTMR0 Clock Enable Bit 121 * | | |0 = TTMR0 clock Disabled. 122 * | | |1 = TTMR0 clock Enabled. 123 * |[23] |TTMR1CKEN |TTMR1 Clock Enable Bit 124 * | | |0 = TTMR1 clock Disabled. 125 * | | |1 = TTMR1 clock Enabled. 126 * |[24] |LPADC0CKEN|LPADC0 Clock Enable Bit 127 * | | |0 = LPADC0 clock Disabled. 128 * | | |1 = LPADC0 clock Enabled. 129 * |[27] |OPACKEN |OP Amplifier Clock Enable Bit 130 * | | |0 = OPA clock Disabled. 131 * | | |1 = OPA clock Enabled. 132 * @var LPSCC_T::CLKKEEP0 133 * Offset: 0x44 Peripheral Clock Keep Control Register 0 134 * --------------------------------------------------------------------------------------------------- 135 * |Bits |Field |Descriptions 136 * | :----: | :----: | :---- | 137 * |[0] |LPPDMA0KEEP|LPPDMA0 Clock Keep Bit 138 * | | |0 = LPPDMA0 clock Disabled when enter NPD0~5/SPD0~2 mode. 139 * | | |1 = LPPDMA0 clock Enabled when enter NPD0~5/SPD0~2 mode. 140 * |[1] |LPGPIOKEEP|LPGPIO Clock Keep Bit 141 * | | |0 = LPGPIO clock Disabled when enter NPD0~5/SPD0~2 mode. 142 * | | |1 = LPGPIO clock Enabled when enter NPD0~5/SPD0~2 mode. 143 * |[2] |LPSRAMKEEP|LPSRAM Clock Keep Bit 144 * | | |0 = LPSRAM clock Disabled when enter NPD0~5/SPD0~2 mode. 145 * | | |1 = LPSRAM clock Enabled when enter NPD0~5/SPD0~2 mode. 146 * |[16] |WDTKEEP |WDT Clock Keep Bit 147 * | | |0 = WDT clock Disabled when enter NPD0~5/SPD0~2 mode. 148 * | | |1 = WDT clock Enabled when enter NPD0~5/SPD0~2 mode. 149 * |[17] |LPSPI0KEEP|LPSPI0 Clock Keep Bit 150 * | | |0 = LPSPI0 clock Disabled when enter NPD0~5/SPD0~2 mode. 151 * | | |1 = LPSPI0 clock Enabled when enter NPD0~5/SPD0~2 mode. 152 * |[18] |LPI2C0KEEP|LPI2C0 Clock Keep Bit 153 * | | |0 = LPI2C0 clock Disabled when enter NPD0~5/SPD0~2 mode. 154 * | | |1 = LPI2C0 clock Enabled when enter NPD0~5/SPD0~2 mode. 155 * |[19] |LPUART0KEEP|LPUART0 Clock Keep Bit 156 * | | |0 = LPUART0 clock Disabled when enter NPD0~5/SPD0~2 mode. 157 * | | |1 = LPUART0 clock Enabled when enter NPD0~5/SPD0~2 mode. 158 * |[20] |LPTMR0KEEP|LPTMR0 Clock Keep Bit 159 * | | |0 = LPTMR0 clock Disabled when enter NPD0~5/SPD0~2 mode. 160 * | | |1 = LPTMR0 clock Enabled when enter NPD0~5/SPD0~2 mode. 161 * |[21] |LPTMR1KEEP|LPTMR1 Clock Keep Bit 162 * | | |0 = LPTMR1 clock Disabled when enter NPD0~5/SPD0~2 mode. 163 * | | |1 = LPTMR1 clock Enabled when enter NPD0~5/SPD0~2 mode. 164 * |[22] |TTMR0KEEP |TTMR0 Clock Keep Bit 165 * | | |0 = TTMR0 clock Disabled when enter NPD0~5/SPD0~2 mode. 166 * | | |1 = TTMR0 clock Enabled when enter NPD0~5/SPD0~2 mode. 167 * |[23] |TTMR1KEEP |TTMR1 Clock Keep Bit 168 * | | |0 = TTMR1 clock Disabled when enter NPD0~5/SPD0~2 mode. 169 * | | |1 = TTMR1 clock Enabled when enter NPD0~5/SPD0~2 mode. 170 * |[24] |LPADC0KEEP|LPADC0 Clock Keep Bit 171 * | | |0 = LPADC0 clock Disabled when enter NPD0~5/SPD0~2 mode. 172 * | | |1 = LPADC0 clock Enabled when enter NPD0~5/SPD0~2 mode. 173 * |[27] |OPAKEEP |OP Amplifier Clock Keep Bit 174 * | | |0 = OPA clock Disabled when enter NPD0~5/SPD0~2 mode. 175 * | | |1 = OPA clock Enabled when enter NPD0~5/SPD0~2 mode. 176 * @var LPSCC_T::CLKSEL0 177 * Offset: 0x50 Peripheral Clock Source Select Control Register 0 178 * --------------------------------------------------------------------------------------------------- 179 * |Bits |Field |Descriptions 180 * | :----: | :----: | :---- | 181 * |[1:0] |LPUART0SEL|LPUART0 Clock Source Selection 182 * | | |00 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 183 * | | |01 = Clock source from 1~24 MHz internal middle speed RC oscillator (MIRC). 184 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 185 * | | |11 = Reserved. 186 * | | |Note: The LPUART0SEL cannot be changed when LPUART0 is operating 187 * | | |Used should make LPUART0 disable before change LPUART0SEL, and reset LPUART0 after change LPUART0SEL. 188 * |[3:2] |LPSPI0SEL |LPSPI0 Clock Source Selection 189 * | | |00 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 190 * | | |01 = Clock source from 1~24 MHz internal middle speed RC oscillator (MIRC). 191 * | | |10 = Reserved. 192 * | | |11 = Reserved. 193 * | | |Note: The LPSPI0SEL cannot be changed when LPSPI0 is operating 194 * | | |Used should make LPSPI0 disable before change LPSPI0SEL, and reset LPSPI0 after change LPSPI0SEL. 195 * |[5:4] |TTMR0SEL |TTMR0 Clock Source Selection 196 * | | |00 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 197 * | | |01 = Clock source from 1~24 MHz internal middle speed RC oscillator (MIRC). 198 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 199 * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 200 * | | |Note: The TTMR0SEL cannot be changed when TTMR0 is operating 201 * | | |Used should make TTMR0 disable before change TTMR0SEL, and reset TTMR0 after change TTMR0SEL. 202 * |[7:6] |TTMR1SEL |TTMR1 Clock Source Selection 203 * | | |00 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 204 * | | |01 = Clock source from 1~24 MHz internal middle speed RC oscillator (MIRC). 205 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 206 * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 207 * | | |Note: The TTMR1SEL cannot be changed when TTMR1 is operating 208 * | | |Used should make TTMR1 disable before change TTMR1SEL, and reset TTMR1 after change TTMR1SEL. 209 * |[10:8] |LPTMR0SEL |LPTMR0 Clock Source Selection 210 * | | |000 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 211 * | | |001 = Clock source from 1~24 MHz internal middle speed RC oscillator (MIRC). 212 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 213 * | | |011 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 214 * | | |100 = Clock source from external clock LPTM0 pin. 215 * | | |Others = Reserved. 216 * | | |Note: The LPTMR0SEL cannot be changed when LPTMR0 is operating 217 * | | |Used should make LPTMR0 disable before change LPTMR0SEL, and reset LPTMR0 after change LPTMR0SEL. 218 * |[14:12] |LPTMR1SEL |LPTMR1 Clock Source Selection 219 * | | |000 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 220 * | | |001 = Clock source from 1~24 MHz internal middle speed RC oscillator (MIRC). 221 * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 222 * | | |011 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 223 * | | |100 = Clock source from external clock LPTM1 pin. 224 * | | |Others = Reserved. 225 * | | |Note: The LPTMR1SEL cannot be changed when LPTMR1 is operating 226 * | | |Used should make LPTMR1 disable before change LPTMR1SEL, and reset LPTMR1 after change LPTMR1SEL. 227 * |[17:16] |LPADC0SEL |LPADC0 Clock Source Selection 228 * | | |00 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 229 * | | |01 = Clock source from 1~24 MHz internal middle speed RC oscillator (MIRC). 230 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 231 * | | |11 = Clock source from PCLK2. 232 * | | |Note: The LPADC0SEL cannot be changed when LPADC0 is operating 233 * | | |Used should make LPADC0 disable before change LPADC0SEL, and reset LPADC0 after change LPADC0SEL. 234 * |[25:24] |WDTSEL |WDT Clock Source Selection 235 * | | |00 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). 236 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 237 * | | |10 = Clock source from HCLK1/2048. 238 * | | |11 = Reserved. 239 * | | |Note: The WDTSEL cannot be changed when WDT is operating 240 * | | |Used should make WDT disable before change WDTSEL, and reset WDT after change WDTSEL. 241 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 242 * @var LPSCC_T::CLKDIV0 243 * Offset: 0x60 Peripheral Clock Divider Number Register 0 244 * --------------------------------------------------------------------------------------------------- 245 * |Bits |Field |Descriptions 246 * | :----: | :----: | :---- | 247 * |[3:0] |HCLK1DIV |HCLK1 Clock Divide Number from HCLK1 Clock Source 248 * | | |HCLK1 clock frequency = (HCLK1 clock source frequency) / (HCLK1DIV + 1). 249 * |[6:4] |APB2DIV |APB2 Clock Divider 250 * | | |APB2 clock can be divided from HCLK1. 251 * | | |000 = PCLK2 frequency is HCLK1. 252 * | | |001 = PCLK2 frequency is 1/2 HCLK1. 253 * | | |010 = PCLK2 frequency is 1/4 HCLK1. 254 * | | |011 = PCLK2 frequency is 1/8 HCLK1. 255 * | | |100 = PCLK2 frequency is 1/16 HCLK1. 256 * | | |Others = Reserved. 257 * |[11:8] |LPUART0DIV|LPUART0 Clock Divide Number from LPUART0 Clock Source 258 * | | |LPUART0 clock frequency = (LPUART0 clock source frequency) / (LPUART0DIV + 1). 259 * |[19:16] |LPADC0DIV |LPADC0 Clock Divide Number from CANFD1 Clock Source 260 * | | |LPADC0 clock frequency = (LPADC0 clock source frequency) / (LPADC0DIV + 1). 261 * @var LPSCC_T::CLKMCTL 262 * Offset: 0x80 Clock Monitor Control Register 263 * --------------------------------------------------------------------------------------------------- 264 * |Bits |Field |Descriptions 265 * | :----: | :----: | :---- | 266 * |[1:0] |CLKM0SEL |Clock Monitor 0 Source Select 267 * | | |00 = Clock monitor source is HCLK1. 268 * | | |01 = Clock monitor source is HIRC12M. 269 * | | |10 = Clock monitor source is MIRC1TO24M. 270 * | | |Others = Reserved. 271 * | | |The CLKM0 output high means clock source is enabled, else clock source is disabled 272 * |[9:8] |CLKM1SEL |Clock Monitor 1 Source Select 273 * | | |00 = Clock monitor source is HCLK1. 274 * | | |01 = Clock monitor source is HIRC12M. 275 * | | |10 = Clock monitor source is MIRC1TO24M. 276 * | | |Others = Reserved. 277 * | | |The CLKM1 output high means clock source is enabled, else clock source is disabled 278 * |[24] |AOCMEN1 |Auto-operation Clock Monitor Enable 1 279 * | | |0 = No auto-operation clock monitor function. 280 * | | |1 = PF.0 will output AOCM0 (controlled by CLKM0SEL (LPSCC_CLKMCTL[1:0]) 281 * | | |PF.1 will output AOCM1 (controlled by CLKM1SEL (LPSCC_CLKMCTL[9:8]). 282 * | | |Note: when ICE connect to chip, DO NOT set this register or may cause chip damage by I/O conflict 283 * |[25] |AOCMEN2 |Auto-operation Clock Monitor Enable 2 284 * | | |0 = No auto-operation clock monitor function. 285 * | | |1 = PF.2 will output AOCM0 (controlled by CLKM0SEL (LPSCC_CLKMCTL[1:0]) 286 * | | |PF.3 will output AOCM1 (controlled by CLKM1SEL (LPSCC_CLKMCTL[9:8]). 287 * | | |Note: when crystal connect to chip, DO NOT set this register or may cause chip damage by I/O conflict 288 * @var LPSCC_T::SRAMCTL 289 * Offset: 0xA0 Low Power SRAM Control Register 290 * --------------------------------------------------------------------------------------------------- 291 * |Bits |Field |Descriptions 292 * | :----: | :----: | :---- | 293 * |[0] |LPSRAMEN |Force LPSRAM Enable Bit 294 * | | |0 = LPSRAM will be auto-enable when SRAM needed suting suto-operating mode 295 * | | |If auto-operating mode is not enabled, the LPSRAM power mode is controlled by CLK_PMUCTL 296 * | | |1 = Force LPSRAM enable for auto-operating mode usage. 297 * |[4] |LPSRAMDR |LPSRAM Retention at idle Enabled 298 * | | |0 = LPSRAM retention at idel when cpu in run mode/NPD0/NPD1/NPD2 Disabled. 299 * | | |1 = LPSRAM retention at idel when cpu in run mode/NPD0/NPD1/NPD2 Enabled.(.default) 300 * | | |When LPSRAMDR = 1, the LPSRAM will auto change to active mode when LPPDMA need to access LPSRAM, else enter power mode which controlled by CLK_PMUCTL. 301 * |[5] |LPSRAMDRL |LPSRAM low power Retention at idle Enabled 302 * | | |0 = LPSRAM retention at idle only.(default) 303 * | | |1 = LPSRAM retention at idle with low power mode. 304 * | | |Note : This control works when LPSRAMDR=1. 305 * @var LPSCC_T::IOHCTL 306 * Offset: 0x100 I/O Hold Control Register 307 * --------------------------------------------------------------------------------------------------- 308 * |Bits |Field |Descriptions 309 * | :----: | :----: | :---- | 310 * |[0] |SCHDIS |I/O Schmitt-Trigger Disable Bit 311 * | | |When chip enter NPD3/NPD4/NPD5, the I/O will be hold and the input mode is default at Schmitt-Trigger mode 312 * | | |Setting this bit can change all I/O input mode to TTL mode 313 * | | |0 = I/O hold with Schmitt-Trigger iput mode. 314 * | | |1 = I/O hold with TTL input mode. 315 */ 316 __I uint32_t RESERVE0[1]; 317 __IO uint32_t IPRST0; /*!< [0x0004] Peripheral Reset Control Register 0 */ 318 __I uint32_t RESERVE1[14]; 319 __IO uint32_t CLKEN0; /*!< [0x0040] Peripheral Clock Enable Control Register 0 */ 320 __IO uint32_t CLKKEEP0; /*!< [0x0044] Peripheral Clock Keep Control Register 0 */ 321 __I uint32_t RESERVE2[2]; 322 __IO uint32_t CLKSEL0; /*!< [0x0050] Peripheral Clock Source Select Control Register 0 */ 323 __I uint32_t RESERVE3[3]; 324 __IO uint32_t CLKDIV0; /*!< [0x0060] Peripheral Clock Divider Number Register 0 */ 325 __I uint32_t RESERVE4[7]; 326 __IO uint32_t CLKMCTL; /*!< [0x0080] Clock Monitor Control Register */ 327 __I uint32_t RESERVE5[7]; 328 __IO uint32_t SRAMCTL; /*!< [0x00a0] Low Power SRAM Control Register */ 329 __I uint32_t RESERVE6[23]; 330 __IO uint32_t IOHCTL; /*!< [0x0100] I/O Hold Control Register */ 331 } LPSCC_T; 332 333 /** 334 @addtogroup LPSCC_CONST LPSCC Bit Field Definition 335 Constant Definitions for LPSCC Controller 336 @{ */ 337 338 #define LPSCC_IPRST0_LPPDMA0RST_Pos (0) /*!< LPSCC_T::IPRST0: LPPDMA0RST Position */ 339 #define LPSCC_IPRST0_LPPDMA0RST_Msk (0x1ul << LPSCC_IPRST0_LPPDMA0RST_Pos) /*!< LPSCC_T::IPRST0: LPPDMA0RST Mask */ 340 341 #define LPSCC_IPRST0_LPGPIORST_Pos (1) /*!< LPSCC_T::IPRST0: LPGPIORST Position */ 342 #define LPSCC_IPRST0_LPGPIORST_Msk (0x1ul << LPSCC_IPRST0_LPGPIORST_Pos) /*!< LPSCC_T::IPRST0: LPGPIORST Mask */ 343 344 #define LPSCC_IPRST0_LPSRAMRST_Pos (2) /*!< LPSCC_T::IPRST0: LPSRAMRST Position */ 345 #define LPSCC_IPRST0_LPSRAMRST_Msk (0x1ul << LPSCC_IPRST0_LPSRAMRST_Pos) /*!< LPSCC_T::IPRST0: LPSRAMRST Mask */ 346 347 #define LPSCC_IPRST0_WDTRST_Pos (16) /*!< LPSCC_T::IPRST0: WDTRST Position */ 348 #define LPSCC_IPRST0_WDTRST_Msk (0x1ul << LPSCC_IPRST0_WDTRST_Pos) /*!< LPSCC_T::IPRST0: WDTRST Mask */ 349 350 #define LPSCC_IPRST0_LPSPI0RST_Pos (17) /*!< LPSCC_T::IPRST0: LPSPI0RST Position */ 351 #define LPSCC_IPRST0_LPSPI0RST_Msk (0x1ul << LPSCC_IPRST0_LPSPI0RST_Pos) /*!< LPSCC_T::IPRST0: LPSPI0RST Mask */ 352 353 #define LPSCC_IPRST0_LPI2C0RST_Pos (18) /*!< LPSCC_T::IPRST0: LPI2C0RST Position */ 354 #define LPSCC_IPRST0_LPI2C0RST_Msk (0x1ul << LPSCC_IPRST0_LPI2C0RST_Pos) /*!< LPSCC_T::IPRST0: LPI2C0RST Mask */ 355 356 #define LPSCC_IPRST0_LPUART0RST_Pos (19) /*!< LPSCC_T::IPRST0: LPUART0RST Position */ 357 #define LPSCC_IPRST0_LPUART0RST_Msk (0x1ul << LPSCC_IPRST0_LPUART0RST_Pos) /*!< LPSCC_T::IPRST0: LPUART0RST Mask */ 358 359 #define LPSCC_IPRST0_LPTMR0RST_Pos (20) /*!< LPSCC_T::IPRST0: LPTMR0RST Position */ 360 #define LPSCC_IPRST0_LPTMR0RST_Msk (0x1ul << LPSCC_IPRST0_LPTMR0RST_Pos) /*!< LPSCC_T::IPRST0: LPTMR0RST Mask */ 361 362 #define LPSCC_IPRST0_LPTMR1RST_Pos (21) /*!< LPSCC_T::IPRST0: LPTMR1RST Position */ 363 #define LPSCC_IPRST0_LPTMR1RST_Msk (0x1ul << LPSCC_IPRST0_LPTMR1RST_Pos) /*!< LPSCC_T::IPRST0: LPTMR1RST Mask */ 364 365 #define LPSCC_IPRST0_TTMR0RST_Pos (22) /*!< LPSCC_T::IPRST0: TTMR0RST Position */ 366 #define LPSCC_IPRST0_TTMR0RST_Msk (0x1ul << LPSCC_IPRST0_TTMR0RST_Pos) /*!< LPSCC_T::IPRST0: TTMR0RST Mask */ 367 368 #define LPSCC_IPRST0_TTMR1RST_Pos (23) /*!< LPSCC_T::IPRST0: TTMR1RST Position */ 369 #define LPSCC_IPRST0_TTMR1RST_Msk (0x1ul << LPSCC_IPRST0_TTMR1RST_Pos) /*!< LPSCC_T::IPRST0: TTMR1RST Mask */ 370 371 #define LPSCC_IPRST0_LPADC0RST_Pos (24) /*!< LPSCC_T::IPRST0: LPADC0RST Position */ 372 #define LPSCC_IPRST0_LPADC0RST_Msk (0x1ul << LPSCC_IPRST0_LPADC0RST_Pos) /*!< LPSCC_T::IPRST0: LPADC0RST Mask */ 373 374 #define LPSCC_IPRST0_OPARST_Pos (27) /*!< LPSCC_T::IPRST0: OPARST Position */ 375 #define LPSCC_IPRST0_OPARST_Msk (0x1ul << LPSCC_IPRST0_OPARST_Pos) /*!< LPSCC_T::IPRST0: OPARST Mask */ 376 377 #define LPSCC_CLKEN0_LPPDMA0CKEN_Pos (0) /*!< LPSCC_T::CLKEN0: LPPDMA0CKEN Position */ 378 #define LPSCC_CLKEN0_LPPDMA0CKEN_Msk (0x1ul << LPSCC_CLKEN0_LPPDMA0CKEN_Pos) /*!< LPSCC_T::CLKEN0: LPPDMA0CKEN Mask */ 379 380 #define LPSCC_CLKEN0_LPGPIOCKEN_Pos (1) /*!< LPSCC_T::CLKEN0: LPGPIOCKEN Position */ 381 #define LPSCC_CLKEN0_LPGPIOCKEN_Msk (0x1ul << LPSCC_CLKEN0_LPGPIOCKEN_Pos) /*!< LPSCC_T::CLKEN0: LPGPIOCKEN Mask */ 382 383 #define LPSCC_CLKEN0_LPSRAMCKEN_Pos (2) /*!< LPSCC_T::CLKEN0: LPSRAMCKEN Position */ 384 #define LPSCC_CLKEN0_LPSRAMCKEN_Msk (0x1ul << LPSCC_CLKEN0_LPSRAMCKEN_Pos) /*!< LPSCC_T::CLKEN0: LPSRAMCKEN Mask */ 385 386 #define LPSCC_CLKEN0_WDTCKEN_Pos (16) /*!< LPSCC_T::CLKEN0: WDTCKEN Position */ 387 #define LPSCC_CLKEN0_WDTCKEN_Msk (0x1ul << LPSCC_CLKEN0_WDTCKEN_Pos) /*!< LPSCC_T::CLKEN0: WDTCKEN Mask */ 388 389 #define LPSCC_CLKEN0_LPSPI0CKEN_Pos (17) /*!< LPSCC_T::CLKEN0: LPSPI0CKEN Position */ 390 #define LPSCC_CLKEN0_LPSPI0CKEN_Msk (0x1ul << LPSCC_CLKEN0_LPSPI0CKEN_Pos) /*!< LPSCC_T::CLKEN0: LPSPI0CKEN Mask */ 391 392 #define LPSCC_CLKEN0_LPI2C0CKEN_Pos (18) /*!< LPSCC_T::CLKEN0: LPI2C0CKEN Position */ 393 #define LPSCC_CLKEN0_LPI2C0CKEN_Msk (0x1ul << LPSCC_CLKEN0_LPI2C0CKEN_Pos) /*!< LPSCC_T::CLKEN0: LPI2C0CKEN Mask */ 394 395 #define LPSCC_CLKEN0_LPUART0CKEN_Pos (19) /*!< LPSCC_T::CLKEN0: LPUART0CKEN Position */ 396 #define LPSCC_CLKEN0_LPUART0CKEN_Msk (0x1ul << LPSCC_CLKEN0_LPUART0CKEN_Pos) /*!< LPSCC_T::CLKEN0: LPUART0CKEN Mask */ 397 398 #define LPSCC_CLKEN0_LPTMR0CKEN_Pos (20) /*!< LPSCC_T::CLKEN0: LPTMR0CKEN Position */ 399 #define LPSCC_CLKEN0_LPTMR0CKEN_Msk (0x1ul << LPSCC_CLKEN0_LPTMR0CKEN_Pos) /*!< LPSCC_T::CLKEN0: LPTMR0CKEN Mask */ 400 401 #define LPSCC_CLKEN0_LPTMR1CKEN_Pos (21) /*!< LPSCC_T::CLKEN0: LPTMR1CKEN Position */ 402 #define LPSCC_CLKEN0_LPTMR1CKEN_Msk (0x1ul << LPSCC_CLKEN0_LPTMR1CKEN_Pos) /*!< LPSCC_T::CLKEN0: LPTMR1CKEN Mask */ 403 404 #define LPSCC_CLKEN0_TTMR0CKEN_Pos (22) /*!< LPSCC_T::CLKEN0: TTMR0CKEN Position */ 405 #define LPSCC_CLKEN0_TTMR0CKEN_Msk (0x1ul << LPSCC_CLKEN0_TTMR0CKEN_Pos) /*!< LPSCC_T::CLKEN0: TTMR0CKEN Mask */ 406 407 #define LPSCC_CLKEN0_TTMR1CKEN_Pos (23) /*!< LPSCC_T::CLKEN0: TTMR1CKEN Position */ 408 #define LPSCC_CLKEN0_TTMR1CKEN_Msk (0x1ul << LPSCC_CLKEN0_TTMR1CKEN_Pos) /*!< LPSCC_T::CLKEN0: TTMR1CKEN Mask */ 409 410 #define LPSCC_CLKEN0_LPADC0CKEN_Pos (24) /*!< LPSCC_T::CLKEN0: LPADC0CKEN Position */ 411 #define LPSCC_CLKEN0_LPADC0CKEN_Msk (0x1ul << LPSCC_CLKEN0_LPADC0CKEN_Pos) /*!< LPSCC_T::CLKEN0: LPADC0CKEN Mask */ 412 413 #define LPSCC_CLKEN0_OPACKEN_Pos (27) /*!< LPSCC_T::CLKEN0: OPACKEN Position */ 414 #define LPSCC_CLKEN0_OPACKEN_Msk (0x1ul << LPSCC_CLKEN0_OPACKEN_Pos) /*!< LPSCC_T::CLKEN0: OPACKEN Mask */ 415 416 #define LPSCC_CLKKEEP0_LPPDMA0KEEP_Pos (0) /*!< LPSCC_T::CLKKEEP0: LPPDMA0KEEP Position*/ 417 #define LPSCC_CLKKEEP0_LPPDMA0KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPPDMA0KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPPDMA0KEEP Mask */ 418 419 #define LPSCC_CLKKEEP0_LPGPIOKEEP_Pos (1) /*!< LPSCC_T::CLKKEEP0: LPGPIOKEEP Position */ 420 #define LPSCC_CLKKEEP0_LPGPIOKEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPGPIOKEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPGPIOKEEP Mask */ 421 422 #define LPSCC_CLKKEEP0_LPSRAMKEEP_Pos (2) /*!< LPSCC_T::CLKKEEP0: LPSRAMKEEP Position */ 423 #define LPSCC_CLKKEEP0_LPSRAMKEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPSRAMKEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPSRAMKEEP Mask */ 424 425 #define LPSCC_CLKKEEP0_WDTKEEP_Pos (16) /*!< LPSCC_T::CLKKEEP0: WDTKEEP Position */ 426 #define LPSCC_CLKKEEP0_WDTKEEP_Msk (0x1ul << LPSCC_CLKKEEP0_WDTKEEP_Pos) /*!< LPSCC_T::CLKKEEP0: WDTKEEP Mask */ 427 428 #define LPSCC_CLKKEEP0_LPSPI0KEEP_Pos (17) /*!< LPSCC_T::CLKKEEP0: LPSPI0KEEP Position */ 429 #define LPSCC_CLKKEEP0_LPSPI0KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPSPI0KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPSPI0KEEP Mask */ 430 431 #define LPSCC_CLKKEEP0_LPI2C0KEEP_Pos (18) /*!< LPSCC_T::CLKKEEP0: LPI2C0KEEP Position */ 432 #define LPSCC_CLKKEEP0_LPI2C0KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPI2C0KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPI2C0KEEP Mask */ 433 434 #define LPSCC_CLKKEEP0_LPUART0KEEP_Pos (19) /*!< LPSCC_T::CLKKEEP0: LPUART0KEEP Position*/ 435 #define LPSCC_CLKKEEP0_LPUART0KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPUART0KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPUART0KEEP Mask */ 436 437 #define LPSCC_CLKKEEP0_LPTMR0KEEP_Pos (20) /*!< LPSCC_T::CLKKEEP0: LPTMR0KEEP Position */ 438 #define LPSCC_CLKKEEP0_LPTMR0KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPTMR0KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPTMR0KEEP Mask */ 439 440 #define LPSCC_CLKKEEP0_LPTMR1KEEP_Pos (21) /*!< LPSCC_T::CLKKEEP0: LPTMR1KEEP Position */ 441 #define LPSCC_CLKKEEP0_LPTMR1KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPTMR1KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPTMR1KEEP Mask */ 442 443 #define LPSCC_CLKKEEP0_TTMR0KEEP_Pos (22) /*!< LPSCC_T::CLKKEEP0: TTMR0KEEP Position */ 444 #define LPSCC_CLKKEEP0_TTMR0KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_TTMR0KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: TTMR0KEEP Mask */ 445 446 #define LPSCC_CLKKEEP0_TTMR1KEEP_Pos (23) /*!< LPSCC_T::CLKKEEP0: TTMR1KEEP Position */ 447 #define LPSCC_CLKKEEP0_TTMR1KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_TTMR1KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: TTMR1KEEP Mask */ 448 449 #define LPSCC_CLKKEEP0_LPADC0KEEP_Pos (24) /*!< LPSCC_T::CLKKEEP0: LPADC0KEEP Position */ 450 #define LPSCC_CLKKEEP0_LPADC0KEEP_Msk (0x1ul << LPSCC_CLKKEEP0_LPADC0KEEP_Pos) /*!< LPSCC_T::CLKKEEP0: LPADC0KEEP Mask */ 451 452 #define LPSCC_CLKKEEP0_OPAKEEP_Pos (27) /*!< LPSCC_T::CLKKEEP0: OPAKEEP Position */ 453 #define LPSCC_CLKKEEP0_OPAKEEP_Msk (0x1ul << LPSCC_CLKKEEP0_OPAKEEP_Pos) /*!< LPSCC_T::CLKKEEP0: OPAKEEP Mask */ 454 455 #define LPSCC_CLKSEL0_LPUART0SEL_Pos (0) /*!< LPSCC_T::CLKSEL0: LPUART0SEL Position */ 456 #define LPSCC_CLKSEL0_LPUART0SEL_Msk (0x3ul << LPSCC_CLKSEL0_LPUART0SEL_Pos) /*!< LPSCC_T::CLKSEL0: LPUART0SEL Mask */ 457 458 #define LPSCC_CLKSEL0_LPSPI0SEL_Pos (2) /*!< LPSCC_T::CLKSEL0: LPSPI0SEL Position */ 459 #define LPSCC_CLKSEL0_LPSPI0SEL_Msk (0x3ul << LPSCC_CLKSEL0_LPSPI0SEL_Pos) /*!< LPSCC_T::CLKSEL0: LPSPI0SEL Mask */ 460 461 #define LPSCC_CLKSEL0_TTMR0SEL_Pos (4) /*!< LPSCC_T::CLKSEL0: TTMR0SEL Position */ 462 #define LPSCC_CLKSEL0_TTMR0SEL_Msk (0x3ul << LPSCC_CLKSEL0_TTMR0SEL_Pos) /*!< LPSCC_T::CLKSEL0: TTMR0SEL Mask */ 463 464 #define LPSCC_CLKSEL0_TTMR1SEL_Pos (6) /*!< LPSCC_T::CLKSEL0: TTMR1SEL Position */ 465 #define LPSCC_CLKSEL0_TTMR1SEL_Msk (0x3ul << LPSCC_CLKSEL0_TTMR1SEL_Pos) /*!< LPSCC_T::CLKSEL0: TTMR1SEL Mask */ 466 467 #define LPSCC_CLKSEL0_LPTMR0SEL_Pos (8) /*!< LPSCC_T::CLKSEL0: LPTMR0SEL Position */ 468 #define LPSCC_CLKSEL0_LPTMR0SEL_Msk (0x7ul << LPSCC_CLKSEL0_LPTMR0SEL_Pos) /*!< LPSCC_T::CLKSEL0: LPTMR0SEL Mask */ 469 470 #define LPSCC_CLKSEL0_LPTMR1SEL_Pos (12) /*!< LPSCC_T::CLKSEL0: LPTMR1SEL Position */ 471 #define LPSCC_CLKSEL0_LPTMR1SEL_Msk (0x7ul << LPSCC_CLKSEL0_LPTMR1SEL_Pos) /*!< LPSCC_T::CLKSEL0: LPTMR1SEL Mask */ 472 473 #define LPSCC_CLKSEL0_LPADC0SEL_Pos (16) /*!< LPSCC_T::CLKSEL0: LPADC0SEL Position */ 474 #define LPSCC_CLKSEL0_LPADC0SEL_Msk (0x3ul << LPSCC_CLKSEL0_LPADC0SEL_Pos) /*!< LPSCC_T::CLKSEL0: LPADC0SEL Mask */ 475 476 #define LPSCC_CLKSEL0_WDTSEL_Pos (24) /*!< LPSCC_T::CLKSEL0: WDTSEL Position */ 477 #define LPSCC_CLKSEL0_WDTSEL_Msk (0x3ul << LPSCC_CLKSEL0_WDTSEL_Pos) /*!< LPSCC_T::CLKSEL0: WDTSEL Mask */ 478 479 #define LPSCC_CLKDIV0_HCLK1DIV_Pos (0) /*!< LPSCC_T::CLKDIV0: HCLK1DIV Position */ 480 #define LPSCC_CLKDIV0_HCLK1DIV_Msk (0xful << LPSCC_CLKDIV0_HCLK1DIV_Pos) /*!< LPSCC_T::CLKDIV0: HCLK1DIV Mask */ 481 482 #define LPSCC_CLKDIV0_APB2DIV_Pos (4) /*!< LPSCC_T::CLKDIV0: APB2DIV Position */ 483 #define LPSCC_CLKDIV0_APB2DIV_Msk (0x7ul << LPSCC_CLKDIV0_APB2DIV_Pos) /*!< LPSCC_T::CLKDIV0: APB2DIV Mask */ 484 485 #define LPSCC_CLKDIV0_LPUART0DIV_Pos (8) /*!< LPSCC_T::CLKDIV0: LPUART0DIV Position */ 486 #define LPSCC_CLKDIV0_LPUART0DIV_Msk (0xful << LPSCC_CLKDIV0_LPUART0DIV_Pos) /*!< LPSCC_T::CLKDIV0: LPUART0DIV Mask */ 487 488 #define LPSCC_CLKDIV0_LPADC0DIV_Pos (16) /*!< LPSCC_T::CLKDIV0: LPADC0DIV Position */ 489 #define LPSCC_CLKDIV0_LPADC0DIV_Msk (0xful << LPSCC_CLKDIV0_LPADC0DIV_Pos) /*!< LPSCC_T::CLKDIV0: LPADC0DIV Mask */ 490 491 #define LPSCC_CLKMCTL_CLKM0SEL_Pos (0) /*!< LPSCC_T::CLKMCTL: CLKM0SEL Position */ 492 #define LPSCC_CLKMCTL_CLKM0SEL_Msk (0x3ul << LPSCC_CLKMCTL_CLKM0SEL_Pos) /*!< LPSCC_T::CLKMCTL: CLKM0SEL Mask */ 493 494 #define LPSCC_CLKMCTL_CLKM1SEL_Pos (8) /*!< LPSCC_T::CLKMCTL: CLKM1SEL Position */ 495 #define LPSCC_CLKMCTL_CLKM1SEL_Msk (0x3ul << LPSCC_CLKMCTL_CLKM1SEL_Pos) /*!< LPSCC_T::CLKMCTL: CLKM1SEL Mask */ 496 497 #define LPSCC_CLKMCTL_AOCMEN1_Pos (24) /*!< LPSCC_T::CLKMCTL: AOCMEN1 Position */ 498 #define LPSCC_CLKMCTL_AOCMEN1_Msk (0x1ul << LPSCC_CLKMCTL_AOCMEN1_Pos) /*!< LPSCC_T::CLKMCTL: AOCMEN1 Mask */ 499 500 #define LPSCC_CLKMCTL_AOCMEN2_Pos (25) /*!< LPSCC_T::CLKMCTL: AOCMEN2 Position */ 501 #define LPSCC_CLKMCTL_AOCMEN2_Msk (0x1ul << LPSCC_CLKMCTL_AOCMEN2_Pos) /*!< LPSCC_T::CLKMCTL: AOCMEN2 Mask */ 502 503 #define LPSCC_SRAMCTL_LPSRAMEN_Pos (0) /*!< LPSCC_T::SRAMCTL: LPSRAMEN Position */ 504 #define LPSCC_SRAMCTL_LPSRAMEN_Msk (0x1ul << LPSCC_SRAMCTL_LPSRAMEN_Pos) /*!< LPSCC_T::SRAMCTL: LPSRAMEN Mask */ 505 506 #define LPSCC_SRAMCTL_LPSRAMDR_Pos (4) /*!< LPSCC_T::SRAMCTL: LPSRAMDR Position */ 507 #define LPSCC_SRAMCTL_LPSRAMDR_Msk (0x1ul << LPSCC_SRAMCTL_LPSRAMDR_Pos) /*!< LPSCC_T::SRAMCTL: LPSRAMDR Mask */ 508 509 #define LPSCC_SRAMCTL_LPSRAMDRL_Pos (5) /*!< LPSCC_T::SRAMCTL: LPSRAMDRL Position */ 510 #define LPSCC_SRAMCTL_LPSRAMDRL_Msk (0x1ul << LPSCC_SRAMCTL_LPSRAMDRL_Pos) /*!< LPSCC_T::SRAMCTL: LPSRAMDRL Mask */ 511 512 #define LPSCC_IOHCTL_SCHDIS_Pos (0) /*!< LPSCC_T::IOHCTL: SCHDIS Position */ 513 #define LPSCC_IOHCTL_SCHDIS_Msk (0x1ul << LPSCC_IOHCTL_SCHDIS_Pos) /*!< LPSCC_T::IOHCTL: SCHDIS Mask */ 514 515 /**@}*/ /* LPSCC_CONST */ 516 /**@}*/ /* end of LPSCC register group */ 517 518 519 /*---------------------- NMI Controller -------------------------*/ 520 /** 521 @addtogroup NMI NMI Controller(NMI) 522 Memory Mapped Structure for NMI Controller 523 @{ */ 524 525 typedef struct 526 { 527 528 529 /** 530 * @var NMI_T::NMIEN 531 * Offset: 0x00 NMI Source Interrupt Enable Register 532 * --------------------------------------------------------------------------------------------------- 533 * |Bits |Field |Descriptions 534 * | :----: | :----: | :---- | 535 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) 536 * | | |0 = BOD NMI source Disabled. 537 * | | |1 = BOD NMI source Enabled. 538 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 539 * |[1] |IRC_INT |IRC TRIM NMI Source Enable (Write Protect) 540 * | | |0 = IRC TRIM NMI source Disabled. 541 * | | |1 = IRC TRIM NMI source Enabled. 542 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 543 * |[2] |PWRWU_INT |Power-down Mode Wake-up NMI Source Enable (Write Protect) 544 * | | |0 = Power-down mode wake-up NMI source Disabled. 545 * | | |1 = Power-down mode wake-up NMI source Enabled. 546 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 547 * |[3] |SRAM_PERR |SRAM ParityCheck Error NMI Source Enable (Write Protect) 548 * | | |0 = SRAM parity check error NMI source Disabled. 549 * | | |1 = SRAM parity check error NMI source Enabled. 550 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 551 * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect) 552 * | | |0 = Clock fail detected interrupt NMI source Disabled. 553 * | | |1 = Clock fail detected interrupt NMI source Enabled. 554 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 555 * |[6] |RTC_INT |RTC NMI Source Enable (Write Protect) 556 * | | |0 = RTC NMI source Disabled. 557 * | | |1 = RTC NMI source Enabled. 558 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 559 * |[7] |TAMPER_INT|TAMPER_INT NMI Source Enable (Write Protect) 560 * | | |0 = Backup register tamper detected interrupt.NMI source Disabled. 561 * | | |1 = Backup register tamper detected interrupt.NMI source Enabled. 562 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 563 * |[8] |EINT0 |External Interrupt From INT0 Pin NMI Source Enable (Write Protect) 564 * | | |0 = External interrupt from INT0 pin NMI source Disabled. 565 * | | |1 = External interrupt from INT0 pin NMI source Enabled. 566 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 567 * |[9] |EINT1 |External Interrupt From INT1 Pin NMI Source Enable (Write Protect) 568 * | | |0 = External interrupt from INT1 pin NMI source Disabled. 569 * | | |1 = External interrupt from INT1 pin NMI source Enabled. 570 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 571 * |[10] |EINT2 |External Interrupt From INT2 Pin NMI Source Enable (Write Protect) 572 * | | |0 = External interrupt from INT2 pin NMI source Disabled. 573 * | | |1 = External interrupt from INT2 pin NMI source Enabled. 574 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 575 * |[11] |EINT3 |External Interrupt From INT3 Pin NMI Source Enable (Write Protect) 576 * | | |0 = External interrupt from INT3 pin NMI source Disabled. 577 * | | |1 = External interrupt from INT3 pin NMI source Enabled. 578 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 579 * |[12] |EINT4 |External Interrupt From INT4 Pin NMI Source Enable (Write Protect) 580 * | | |0 = External interrupt from INT4 pin NMI source Disabled. 581 * | | |1 = External interrupt from INT4 pin NMI source Enabled. 582 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 583 * |[13] |EINT5 |External Interrupt From INT5 Pin NMI Source Enable (Write Protect) 584 * | | |0 = External interrupt from INT5 pin NMI source Disabled. 585 * | | |1 = External interrupt from INT5 pin NMI source Enabled. 586 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 587 * |[14] |UART0_INT |UART0 NMI Source Enable (Write Protect) 588 * | | |0 = UART0 NMI source Disabled. 589 * | | |1 = UART0 NMI source Enabled. 590 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 591 * |[15] |UART1_INT |UART1 NMI Source Enable (Write Protect) 592 * | | |0 = UART1 NMI source Disabled. 593 * | | |1 = UART1 NMI source Enabled. 594 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 595 * @var NMI_T::NMISTS 596 * Offset: 0x04 NMI Source Interrupt Status Register 597 * --------------------------------------------------------------------------------------------------- 598 * |Bits |Field |Descriptions 599 * | :----: | :----: | :---- | 600 * |[0] |BODOUT |BOD Interrupt Flag (Read Only) 601 * | | |0 = BOD interrupt is deasserted. 602 * | | |1 = BOD interrupt is asserted. 603 * |[1] |IRC_INT |IRC TRIM Interrupt Flag (Read Only) 604 * | | |0 = HIRC TRIM interrupt is deasserted. 605 * | | |1 = HIRC TRIM interrupt is asserted. 606 * |[2] |PWRWU_INT |Power-down Mode Wake-up Interrupt Flag (Read Only) 607 * | | |0 = Power-down mode wake-up interrupt is deasserted. 608 * | | |1 = Power-down mode wake-up interrupt is asserted. 609 * |[3] |SRAM_PERR |SRAM ParityCheck Error Interrupt Flag (Read Only) 610 * | | |0 = SRAM parity check error interrupt is deasserted. 611 * | | |1 = SRAM parity check error interrupt is asserted. 612 * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only) 613 * | | |0 = Clock fail detected interrupt is deasserted. 614 * | | |1 = Clock fail detected interrupt is asserted. 615 * |[6] |RTC_INT |RTC Interrupt Flag (Read Only) 616 * | | |0 = RTC interrupt is deasserted. 617 * | | |1 = RTC interrupt is asserted. 618 * |[7] |TAMPER_INT|TAMPER_INT Interrupt Flag (Read Only) 619 * | | |0 = Backup register tamper detected interrupt is deasserted. 620 * | | |1 = Backup register tamper detected interrupt is asserted. 621 * |[8] |EINT0 |External Interrupt From INT0 Pin Interrupt Flag (Read Only) 622 * | | |0 = External Interrupt from INT0 interrupt is deasserted. 623 * | | |1 = External Interrupt from INT0 interrupt is asserted. 624 * |[9] |EINT1 |External Interrupt From INT1 Pin Interrupt Flag (Read Only) 625 * | | |0 = External Interrupt from INT1 interrupt is deasserted. 626 * | | |1 = External Interrupt from INT1 interrupt is asserted. 627 * |[10] |EINT2 |External Interrupt From INT2 Pin Interrupt Flag (Read Only) 628 * | | |0 = External Interrupt from INT2 interrupt is deasserted. 629 * | | |1 = External Interrupt from INT2 interrupt is asserted. 630 * |[11] |EINT3 |External Interrupt From INT3 Pin Interrupt Flag (Read Only) 631 * | | |0 = External Interrupt from INT3 interrupt is deasserted. 632 * | | |1 = External Interrupt from INT3 interrupt is asserted. 633 * |[12] |EINT4 |External Interrupt From INT4 Pin Interrupt Flag (Read Only) 634 * | | |0 = External Interrupt from INT4 interrupt is deasserted. 635 * | | |1 = External Interrupt from INT4 interrupt is asserted. 636 * |[13] |EINT5 |External Interrupt From INT5 Pin Interrupt Flag (Read Only) 637 * | | |0 = External Interrupt from INT5 interrupt is deasserted. 638 * | | |1 = External Interrupt from INT5 interrupt is asserted. 639 * |[14] |UART0_INT |UART0 Interrupt Flag (Read Only) 640 * | | |0 = UART1 interrupt is deasserted. 641 * | | |1 = UART1 interrupt is asserted. 642 * |[15] |UART1_INT |UART1 Interrupt Flag (Read Only) 643 * | | |0 = UART1 interrupt is deasserted. 644 * | | |1 = UART1 interrupt is asserted. 645 */ 646 __IO uint32_t NMIEN; /*!< [0x0000] NMI Source Interrupt Enable Register */ 647 __I uint32_t NMISTS; /*!< [0x0004] NMI Source Interrupt Status Register */ 648 649 } NMI_T; 650 651 /** 652 @addtogroup NMI_CONST NMI Bit Field Definition 653 Constant Definitions for NMI Controller 654 @{ */ 655 656 #define NMI_NMIEN_BODOUT_Pos (0) /*!< NMI_T::NMIEN: BODOUT Position */ 657 #define NMI_NMIEN_BODOUT_Msk (0x1ul << NMI_NMIEN_BODOUT_Pos) /*!< NMI_T::NMIEN: BODOUT Mask */ 658 659 #define NMI_NMIEN_IRC_INT_Pos (1) /*!< NMI_T::NMIEN: IRC_INT Position */ 660 #define NMI_NMIEN_IRC_INT_Msk (0x1ul << NMI_NMIEN_IRC_INT_Pos) /*!< NMI_T::NMIEN: IRC_INT Mask */ 661 662 #define NMI_NMIEN_PWRWU_INT_Pos (2) /*!< NMI_T::NMIEN: PWRWU_INT Position */ 663 #define NMI_NMIEN_PWRWU_INT_Msk (0x1ul << NMI_NMIEN_PWRWU_INT_Pos) /*!< NMI_T::NMIEN: PWRWU_INT Mask */ 664 665 #define NMI_NMIEN_SRAM_PERR_Pos (3) /*!< NMI_T::NMIEN: SRAM_PERR Position */ 666 #define NMI_NMIEN_SRAM_PERR_Msk (0x1ul << NMI_NMIEN_SRAM_PERR_Pos) /*!< NMI_T::NMIEN: SRAM_PERR Mask */ 667 668 #define NMI_NMIEN_CLKFAIL_Pos (4) /*!< NMI_T::NMIEN: CLKFAIL Position */ 669 #define NMI_NMIEN_CLKFAIL_Msk (0x1ul << NMI_NMIEN_CLKFAIL_Pos) /*!< NMI_T::NMIEN: CLKFAIL Mask */ 670 671 #define NMI_NMIEN_RTC_INT_Pos (6) /*!< NMI_T::NMIEN: RTC_INT Position */ 672 #define NMI_NMIEN_RTC_INT_Msk (0x1ul << NMI_NMIEN_RTC_INT_Pos) /*!< NMI_T::NMIEN: RTC_INT Mask */ 673 674 #define NMI_NMIEN_TAMPER_INT_Pos (7) /*!< NMI_T::NMIEN: TAMPER_INT Position */ 675 #define NMI_NMIEN_TAMPER_INT_Msk (0x1ul << NMI_NMIEN_TAMPER_INT_Pos) /*!< NMI_T::NMIEN: TAMPER_INT Mask */ 676 677 #define NMI_NMIEN_EINT0_Pos (8) /*!< NMI_T::NMIEN: EINT0 Position */ 678 #define NMI_NMIEN_EINT0_Msk (0x1ul << NMI_NMIEN_EINT0_Pos) /*!< NMI_T::NMIEN: EINT0 Mask */ 679 680 #define NMI_NMIEN_EINT1_Pos (9) /*!< NMI_T::NMIEN: EINT1 Position */ 681 #define NMI_NMIEN_EINT1_Msk (0x1ul << NMI_NMIEN_EINT1_Pos) /*!< NMI_T::NMIEN: EINT1 Mask */ 682 683 #define NMI_NMIEN_EINT2_Pos (10) /*!< NMI_T::NMIEN: EINT2 Position */ 684 #define NMI_NMIEN_EINT2_Msk (0x1ul << NMI_NMIEN_EINT2_Pos) /*!< NMI_T::NMIEN: EINT2 Mask */ 685 686 #define NMI_NMIEN_EINT3_Pos (11) /*!< NMI_T::NMIEN: EINT3 Position */ 687 #define NMI_NMIEN_EINT3_Msk (0x1ul << NMI_NMIEN_EINT3_Pos) /*!< NMI_T::NMIEN: EINT3 Mask */ 688 689 #define NMI_NMIEN_EINT4_Pos (12) /*!< NMI_T::NMIEN: EINT4 Position */ 690 #define NMI_NMIEN_EINT4_Msk (0x1ul << NMI_NMIEN_EINT4_Pos) /*!< NMI_T::NMIEN: EINT4 Mask */ 691 692 #define NMI_NMIEN_EINT5_Pos (13) /*!< NMI_T::NMIEN: EINT5 Position */ 693 #define NMI_NMIEN_EINT5_Msk (0x1ul << NMI_NMIEN_EINT5_Pos) /*!< NMI_T::NMIEN: EINT5 Mask */ 694 695 #define NMI_NMIEN_UART0_INT_Pos (14) /*!< NMI_T::NMIEN: UART0_INT Position */ 696 #define NMI_NMIEN_UART0_INT_Msk (0x1ul << NMI_NMIEN_UART0_INT_Pos) /*!< NMI_T::NMIEN: UART0_INT Mask */ 697 698 #define NMI_NMIEN_UART1_INT_Pos (15) /*!< NMI_T::NMIEN: UART1_INT Position */ 699 #define NMI_NMIEN_UART1_INT_Msk (0x1ul << NMI_NMIEN_UART1_INT_Pos) /*!< NMI_T::NMIEN: UART1_INT Mask */ 700 701 #define NMI_NMISTS_BODOUT_Pos (0) /*!< NMI_T::NMISTS: BODOUT Position */ 702 #define NMI_NMISTS_BODOUT_Msk (0x1ul << NMI_NMISTS_BODOUT_Pos) /*!< NMI_T::NMISTS: BODOUT Mask */ 703 704 #define NMI_NMISTS_IRC_INT_Pos (1) /*!< NMI_T::NMISTS: IRC_INT Position */ 705 #define NMI_NMISTS_IRC_INT_Msk (0x1ul << NMI_NMISTS_IRC_INT_Pos) /*!< NMI_T::NMISTS: IRC_INT Mask */ 706 707 #define NMI_NMISTS_PWRWU_INT_Pos (2) /*!< NMI_T::NMISTS: PWRWU_INT Position */ 708 #define NMI_NMISTS_PWRWU_INT_Msk (0x1ul << NMI_NMISTS_PWRWU_INT_Pos) /*!< NMI_T::NMISTS: PWRWU_INT Mask */ 709 710 #define NMI_NMISTS_SRAM_PERR_Pos (3) /*!< NMI_T::NMISTS: SRAM_PERR Position */ 711 #define NMI_NMISTS_SRAM_PERR_Msk (0x1ul << NMI_NMISTS_SRAM_PERR_Pos) /*!< NMI_T::NMISTS: SRAM_PERR Mask */ 712 713 #define NMI_NMISTS_CLKFAIL_Pos (4) /*!< NMI_T::NMISTS: CLKFAIL Position */ 714 #define NMI_NMISTS_CLKFAIL_Msk (0x1ul << NMI_NMISTS_CLKFAIL_Pos) /*!< NMI_T::NMISTS: CLKFAIL Mask */ 715 716 #define NMI_NMISTS_RTC_INT_Pos (6) /*!< NMI_T::NMISTS: RTC_INT Position */ 717 #define NMI_NMISTS_RTC_INT_Msk (0x1ul << NMI_NMISTS_RTC_INT_Pos) /*!< NMI_T::NMISTS: RTC_INT Mask */ 718 719 #define NMI_NMISTS_TAMPER_INT_Pos (7) /*!< NMI_T::NMISTS: TAMPER_INT Position */ 720 #define NMI_NMISTS_TAMPER_INT_Msk (0x1ul << NMI_NMISTS_TAMPER_INT_Pos) /*!< NMI_T::NMISTS: TAMPER_INT Mask */ 721 722 #define NMI_NMISTS_EINT0_Pos (8) /*!< NMI_T::NMISTS: EINT0 Position */ 723 #define NMI_NMISTS_EINT0_Msk (0x1ul << NMI_NMISTS_EINT0_Pos) /*!< NMI_T::NMISTS: EINT0 Mask */ 724 725 #define NMI_NMISTS_EINT1_Pos (9) /*!< NMI_T::NMISTS: EINT1 Position */ 726 #define NMI_NMISTS_EINT1_Msk (0x1ul << NMI_NMISTS_EINT1_Pos) /*!< NMI_T::NMISTS: EINT1 Mask */ 727 728 #define NMI_NMISTS_EINT2_Pos (10) /*!< NMI_T::NMISTS: EINT2 Position */ 729 #define NMI_NMISTS_EINT2_Msk (0x1ul << NMI_NMISTS_EINT2_Pos) /*!< NMI_T::NMISTS: EINT2 Mask */ 730 731 #define NMI_NMISTS_EINT3_Pos (11) /*!< NMI_T::NMISTS: EINT3 Position */ 732 #define NMI_NMISTS_EINT3_Msk (0x1ul << NMI_NMISTS_EINT3_Pos) /*!< NMI_T::NMISTS: EINT3 Mask */ 733 734 #define NMI_NMISTS_EINT4_Pos (12) /*!< NMI_T::NMISTS: EINT4 Position */ 735 #define NMI_NMISTS_EINT4_Msk (0x1ul << NMI_NMISTS_EINT4_Pos) /*!< NMI_T::NMISTS: EINT4 Mask */ 736 737 #define NMI_NMISTS_EINT5_Pos (13) /*!< NMI_T::NMISTS: EINT5 Position */ 738 #define NMI_NMISTS_EINT5_Msk (0x1ul << NMI_NMISTS_EINT5_Pos) /*!< NMI_T::NMISTS: EINT5 Mask */ 739 740 #define NMI_NMISTS_UART0_INT_Pos (14) /*!< NMI_T::NMISTS: UART0_INT Position */ 741 #define NMI_NMISTS_UART0_INT_Msk (0x1ul << NMI_NMISTS_UART0_INT_Pos) /*!< NMI_T::NMISTS: UART0_INT Mask */ 742 743 #define NMI_NMISTS_UART1_INT_Pos (15) /*!< NMI_T::NMISTS: UART1_INT Position */ 744 #define NMI_NMISTS_UART1_INT_Msk (0x1ul << NMI_NMISTS_UART1_INT_Pos) /*!< NMI_T::NMISTS: UART1_INT Mask */ 745 746 /**@}*/ /* NMI_CONST */ 747 /**@}*/ /* end of NMI register group */ 748 749 750 751 /*---------------------- System Manger Controller -------------------------*/ 752 /** 753 @addtogroup SYS System Manger Controller(SYS) 754 Memory Mapped Structure for SYS Controller 755 @{ */ 756 757 typedef struct 758 { 759 /** 760 * @var SYS_T::PDID 761 * Offset: 0x00 Part Device Identification Number Register 762 * --------------------------------------------------------------------------------------------------- 763 * |Bits |Field |Descriptions 764 * | :----: | :----: | :---- | 765 * |[31:0] |PDID |Part Device Identification Number (Read Only) 766 * | | |This register reflects device part number code 767 * | | |Software can read this register to identify which device is used. 768 * @var SYS_T::RSTSTS 769 * Offset: 0x04 System Reset Status Register 770 * --------------------------------------------------------------------------------------------------- 771 * |Bits |Field |Descriptions 772 * | :----: | :----: | :---- | 773 * |[0] |PORF |POR Reset Flag 774 * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 775 * | | |0 = No reset from POR or CHIPRST. 776 * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. 777 * | | |Note: Write 1 to clear this bit to 0. 778 * |[1] |PINRF |NRESET Pin Reset Flag 779 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. 780 * | | |0 = No reset from nRESET pin. 781 * | | |1 = Pin nRESET had issued the reset signal to reset the system. 782 * | | |Note: Write 1 to clear this bit to 0. 783 * |[2] |WDTRF |WDT Reset Flag 784 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. 785 * | | |0 = No reset from watchdog timer or window watchdog timer. 786 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. 787 * | | |Note 1: Write 1 to clear this bit to 0. 788 * | | |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset 789 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 790 * |[3] |LVRF |LVR Reset Flag 791 * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. 792 * | | |0 = No reset from LVR. 793 * | | |1 = LVR controller had issued the reset signal to reset the system. 794 * | | |Note: Write 1 to clear this bit to 0. 795 * |[4] |BODRF |BOD Reset Flag 796 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. 797 * | | |0 = No reset from BOD. 798 * | | |1 = The BOD had issued the reset signal to reset the system. 799 * | | |Note: Write 1 to clear this bit to 0. 800 * |[5] |SYSRF |System Reset Flag 801 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M23 core to indicate the previous reset source. 802 * | | |0 = No reset from Cortex-M23. 803 * | | |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core. 804 * | | |Note: Write 1 to clear this bit to 0. 805 * |[6] |HRESETRF |HRESET Reset Flag 806 * | | |The HRESET reset flag is set by the "Reset Signal" from the HRESET. 807 * | | |0 = No reset from HRESET. 808 * | | |1 = Reset from HRESET. 809 * | | |Note: Write 1 to clear this bit to 0. 810 * |[7] |CPURF |CPU Reset Flag 811 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 core and RRAM Memory Controller (RMC). 812 * | | |0 = No reset from CPU. 813 * | | |1 = The Cortex-M23 core and RMC are reset by software setting CPURST to 1. 814 * | | |Note: Write 1 to clear this bit to 0. 815 * |[8] |CPULKRF |CPU Lockup Reset Flag 816 * | | |0 = No reset from CPU lockup happened. 817 * | | |1 = The Cortex-M23 lockup happened and chip is reset. 818 * | | |Note 1: Write 1 to clear this bit to 0. 819 * | | |Note 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset. 820 * @var SYS_T::IPRST0 821 * Offset: 0x08 Peripheral Reset Control Register 0 822 * --------------------------------------------------------------------------------------------------- 823 * |Bits |Field |Descriptions 824 * | :----: | :----: | :---- | 825 * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) 826 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. 827 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from RRAM are also reload. 828 * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 7.2.2 829 * | | |0 = Chip normal operation. 830 * | | |1 = Chip one-shot reset. 831 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 832 * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) 833 * | | |Setting this bit will only reset the processor core and RRAM Memory Controller (RMC), and this bit will automatically return to 0 after the 2 clock cycles. 834 * | | |0 = Processor core normal operation. 835 * | | |1 = Processor core one-shot reset. 836 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 837 * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect) 838 * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 839 * | | |User needs to set this bit to 0 to release from reset state. 840 * | | |0 = PDMA0 controller normal operation. 841 * | | |1 = PDMA0 controller reset. 842 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 843 * |[3] |EBIRST |EBI Controller Reset (Write Protect) 844 * | | |Set this bit to 1 will generate a reset signal to the EBI 845 * | | |User needs to set this bit to 0 to release from the reset state. 846 * | | |0 = EBI controller normal operation. 847 * | | |1 = EBI controller reset. 848 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 849 * |[4] |USBHRST |USBH Controller Reset (Write Protect) 850 * | | |Set this bit to 1 will generate a reset signal to the USBH 851 * | | |User needs to set this bit to 0 to release from the reset state. 852 * | | |0 = USBH controller normal operation. 853 * | | |1 = USBH controller reset. 854 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 855 * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) 856 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller 857 * | | |User needs to set this bit to 0 to release from the reset state. 858 * | | |0 = CRC calculation controller normal operation. 859 * | | |1 = CRC calculation controller reset. 860 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 861 * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) 862 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller 863 * | | |User needs to set this bit to 0 to release from the reset state. 864 * | | |0 = CRYPTO controller normal operation. 865 * | | |1 = CRYPTO controller reset. 866 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 867 * |[20] |CANFD0RST |CANFD0 Controller Reset 868 * | | |Setting this bit to 1 will generate a reset signal to the CANFD0 controller 869 * | | |User needs to set this bit to 0 to release from the reset state. 870 * | | |0 = CANFD0 controller normal operation. 871 * | | |1 = CANFD0 controller reset. 872 * |[21] |CANFD1RST |CANFD1 Controller Reset 873 * | | |Setting this bit to 1 will generate a reset signal to the CANFD1 controller 874 * | | |User needs to set this bit to 0 to release from the reset state. 875 * | | |0 = CANFD1 controller normal operation. 876 * | | |1 = CANFD1 controller reset. 877 * @var SYS_T::IPRST1 878 * Offset: 0x0C Peripheral Reset Control Register 1 879 * --------------------------------------------------------------------------------------------------- 880 * |Bits |Field |Descriptions 881 * | :----: | :----: | :---- | 882 * |[1] |GPIORST |GPIO Controller Reset 883 * | | |0 = GPIO controller normal operation. 884 * | | |1 = GPIO controller reset. 885 * |[2] |TMR0RST |Timer0 Controller Reset 886 * | | |0 = Timer0 controller normal operation. 887 * | | |1 = Timer0 controller reset. 888 * |[3] |TMR1RST |Timer1 Controller Reset 889 * | | |0 = Timer1 controller normal operation. 890 * | | |1 = Timer1 controller reset. 891 * |[4] |TMR2RST |Timer2 Controller Reset 892 * | | |0 = Timer2 controller normal operation. 893 * | | |1 = Timer2 controller reset. 894 * |[5] |TMR3RST |Timer3 Controller Reset 895 * | | |0 = Timer3 controller normal operation. 896 * | | |1 = Timer3 controller reset. 897 * |[7] |ACMP01RST |ACMP01 Controller Reset 898 * | | |0 = ACMP01 controller normal operation. 899 * | | |1 = ACMP01 controller reset. 900 * |[8] |I2C0RST |I2C0 Controller Reset 901 * | | |0 = I2C0 controller normal operation. 902 * | | |1 = I2C0 controller reset. 903 * |[9] |I2C1RST |I2C1 Controller Reset 904 * | | |0 = I2C1 controller normal operation. 905 * | | |1 = I2C1 controller reset. 906 * |[10] |I2C2RST |I2C2 Controller Reset 907 * | | |0 = I2C2 controller normal operation. 908 * | | |1 = I2C2 controller reset.`. 909 * |[11] |I2C3RST |I2C3 Controller Reset 910 * | | |0 = I2C3 controller normal operation. 911 * | | |1 = I2C3 controller reset. 912 * |[12] |QSPI0RST |Qual SPI0 Controller Reset 913 * | | |0 = Qual SPI0 controller normal operation. 914 * | | |1 = Qual SPI0 controller reset. 915 * |[13] |SPI0RST |SPI0 Controller Reset 916 * | | |0 = SPI0 controller normal operation. 917 * | | |1 = SPI0 controller reset. 918 * |[14] |SPI1RST |SPI1 Controller Reset 919 * | | |0 = SPI1 controller normal operation. 920 * | | |1 = SPI1 controller reset. 921 * |[15] |SPI2RST |SPI2 Controller Reset 922 * | | |0 = SPI2 controller normal operation. 923 * | | |1 = SPI2 controller reset. 924 * |[16] |UART0RST |UART0 Controller Reset 925 * | | |0 = UART0 controller normal operation. 926 * | | |1 = UART0 controller reset. 927 * |[17] |UART1RST |UART1 Controller Reset 928 * | | |0 = UART1 controller normal operation. 929 * | | |1 = UART1 controller reset. 930 * |[18] |UART2RST |UART2 Controller Reset 931 * | | |0 = UART2 controller normal operation. 932 * | | |1 = UART2 controller reset. 933 * |[19] |UART3RST |UART3 Controller Reset 934 * | | |0 = UART3 controller normal operation. 935 * | | |1 = UART3 controller reset. 936 * |[20] |UART4RST |UART4 Controller Reset 937 * | | |0 = UART4 controller normal operation. 938 * | | |1 = UART4 controller reset. 939 * |[21] |UART5RST |UART5 Controller Reset 940 * | | |0 = UART5 controller normal operation. 941 * | | |1 = UART5 controller reset. 942 * |[22] |UART6RST |UART6 Controller Reset 943 * | | |0 = UART6 controller normal operation. 944 * | | |1 = UART6 controller reset. 945 * |[23] |UART7RST |UART7 Controller Reset 946 * | | |0 = UART7 controller normal operation. 947 * | | |1 = UART7 controller reset. 948 * |[26] |OTGRST |OTG Controller Reset 949 * | | |0 = OTG controller normal operation. 950 * | | |1 = OTG controller reset. 951 * |[27] |USBDRST |USBD Controller Reset 952 * | | |0 = USBD controller normal operation. 953 * | | |1 = USBD controller reset. 954 * |[28] |EADC0RST |EADC0 Controller Reset 955 * | | |0 = EADC0 controller normal operation. 956 * | | |1 = EADC0 controller reset. 957 * |[31] |TRNGRST |TRNG Controller Reset 958 * | | |0 = TRNG controller normal operation. 959 * | | |1 = TRNG controller reset. 960 * @var SYS_T::IPRST2 961 * Offset: 0x10 Peripheral Reset Control Register 2 962 * --------------------------------------------------------------------------------------------------- 963 * |Bits |Field |Descriptions 964 * | :----: | :----: | :---- | 965 * |[6] |SPI3RST |SPI3 Controller Reset 966 * | | |0 = SPI3 controller normal operation. 967 * | | |1 = SPI3 controller reset. 968 * |[8] |USCI0RST |USCI0 Controller Reset 969 * | | |0 = USCI0 controller normal operation. 970 * | | |1 = USCI0 controller reset. 971 * |[9] |USCI1RST |USCI1 Controller Reset 972 * | | |0 = USCI1 controller normal operation. 973 * | | |1 = USCI1 controller reset. 974 * |[11] |WWDTRST |WWDT Controller Reset 975 * | | |0 = WWDT controller normal operation. 976 * | | |1 = WWDT controller reset. 977 * |[12] |DACRST |DAC Controller Reset 978 * | | |0 = DAC controller normal operation. 979 * | | |1 = DAC controller reset. 980 * |[16] |EPWM0RST |EPWM0 Controller Reset 981 * | | |0 = EPWM0 controller normal operation. 982 * | | |1 = EPWM0 controller reset. 983 * |[17] |EPWM1RST |EPWM1 Controller Reset 984 * | | |0 = EPWM1 controller normal operation. 985 * | | |1 = EPWM1 controller reset. 986 * |[22] |EQEI0RST |EQEI0 Controller Reset 987 * | | |0 = EQEI0 controller normal operation. 988 * | | |1 = EQEI0 controller reset. 989 * |[23] |EQEI1RST |EQEI1 Controller Reset 990 * | | |0 = EQEI1 controller normal operation. 991 * | | |1 = EQEI1 controller reset. 992 * |[25] |TKRST |TK Controller Reset 993 * | | |0 = TK controller normal operation. 994 * | | |1 = TK controller reset. 995 * |[26] |ECAP0RST |ECAP0 Controller Reset 996 * | | |0 = ECAP0 controller normal operation. 997 * | | |1 = ECAP0 controller reset. 998 * |[27] |ECAP1RST |ECAP1 Controller Reset 999 * | | |0 = ECAP1 controller normal operation. 1000 * | | |1 = ECAP1 controller reset. 1001 * @var SYS_T::BODCTL 1002 * Offset: 0x18 Brown-out Detector Control Register 1003 * --------------------------------------------------------------------------------------------------- 1004 * |Bits |Field |Descriptions 1005 * | :----: | :----: | :---- | 1006 * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) 1007 * | | |The default value is set by RRAM controller user configuration register CBODEN (CONFIG0 [19]). 1008 * | | |0 = Brown-out Detector function Disabled. 1009 * | | |1 = Brown-out Detector function Enabled. 1010 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1011 * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) 1012 * | | |The default value is set by RRAM controller user configuration register CBORST(CONFIG0[20]) bit. 1013 * | | |0 = Brown-out "INTERRUPT" function Enabled. 1014 * | | |1 = Brown-out "RESET" function Enabled. 1015 * | | |Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). 1016 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high 1017 * | | |BOD interrupt will keep till to the BODEN set to 0 1018 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). 1019 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1020 * |[4] |BODIF |Brown-out Detector Interrupt Flag 1021 * | | |0 = Brown-out Detector does not detect any voltage draft at AVDD down through or up through the voltage of BODVL setting. 1022 * | | |1 = When Brown-out Detector detects the AVDD is dropped down through the voltage of BODVL setting or the AVDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. 1023 * | | |Note: Write 1 to clear this bit to 0. 1024 * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) 1025 * | | |0 = BOD operate in normal mode (default). 1026 * | | |1 = BOD Low Power mode Enabled. 1027 * | | |Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. 1028 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1029 * |[6] |BODOUT |Brown-out Detector Output Status 1030 * | | |0 = Brown-out Detector output status is 0. 1031 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. 1032 * | | |1 = Brown-out Detector output status is 1. 1033 * | | |It means the detected voltage is lower than BODVL setting 1034 * | | |If the BODEN is 0, BOD function disabled, this bit always responds 0000. 1035 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) 1036 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting 1037 * | | |LVR function is enabled by default. 1038 * | | |0 = Low Voltage Reset function Disabled. 1039 * | | |1 = Low Voltage Reset function Enabled. 1040 * | | |Note 1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). 1041 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1042 * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) 1043 * | | |000 = BOD output is sampled by RC10K clock. 1044 * | | |001 = 3~4 system clock (HCLK). 1045 * | | |010 = 7~8 system clock (HCLK). 1046 * | | |011 = 15~16 system clock (HCLK). 1047 * | | |100 = 31~32 system clock (HCLK). 1048 * | | |101 = 63~64 system clock (HCLK). 1049 * | | |110 = 127~128 system clock (HCLK). 1050 * | | |111 = 255~256 system clock (HCLK). 1051 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 1052 * | | |Note 2: In NPD3/NPD4/NPD5/SPD0~2 mode, BOD output is sampled by RC10K clock. 1053 * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) 1054 * | | |000 = Without de-glitch function. 1055 * | | |001 = 4 system clock (HCLK). 1056 * | | |010 = 8 system clock (HCLK). 1057 * | | |011 = 16 system clock (HCLK). 1058 * | | |100 = 32 system clock (HCLK). 1059 * | | |101 = 64 system clock (HCLK). 1060 * | | |110 = 128 system clock (HCLK). 1061 * | | |111 = 256 system clock (HCLK). 1062 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 1063 * | | |Note 2: In NPD3/NPD4/NPD5/SPD0~2 mode, LVR output is sampled by RC10K clock. 1064 * |[15] |LVRRDY |LVR Enable Ready Flag (Read Only) 1065 * | | |0 = LVR disabled and not ready. 1066 * | | |1 = LVR enabled and ready. 1067 * |[19:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) 1068 * | | |The default value is set by RRAM controller user configuration register CBOV ({1'b1, CONFIG0 [23:21]}). 1069 * | | |0000 = Brown-Out Detector threshold voltage is 1.5V. 1070 * | | |1000 = Brown-Out Detector threshold voltage is 1.6V. 1071 * | | |1001 = Brown-Out Detector threshold voltage is 1.8V. 1072 * | | |1010 = Brown-Out Detector threshold voltage is 2.0V. 1073 * | | |1011 = Brown-Out Detector threshold voltage is 2.2V. 1074 * | | |1100 = Brown-Out Detector threshold voltage is 2.4V. 1075 * | | |1101 = Brown-Out Detector threshold voltage is 2.6V. 1076 * | | |1110 = Brown-Out Detector threshold voltage is 2.8V. 1077 * | | |1111 = Brown-Out Detector threshold voltage is 3.0V. 1078 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1079 * @var SYS_T::IVSCTL 1080 * Offset: 0x1C Internal Voltage Source Control Register 1081 * --------------------------------------------------------------------------------------------------- 1082 * |Bits |Field |Descriptions 1083 * | :----: | :----: | :---- | 1084 * |[0] |VTEMPEN |Temperature Sensor Enable Bit 1085 * | | |This bit is used to enable/disable temperature sensor function. 1086 * | | |0 = Temperature sensor function Disabled (default). 1087 * | | |1 = Temperature sensor function Enabled. 1088 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit 1089 * | | |This bit is used to enable/disable VBAT unity gain buffer function. 1090 * | | |0 = VBAT unity gain buffer function Disabled (default). 1091 * | | |1 = VBAT unity gain buffer function Enabled. 1092 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result 1093 * |[2] |AVDDDIV4EN|AVDD divide 4 Enable Bit 1094 * | | |This bit is used to enable/disable AVDD divide 4 function. 1095 * | | |0 = AVDD divide 4 function Disabled (default). 1096 * | | |1 = AVDD divide 4 function Enabled. 1097 * | | |Note: After this bit is set to 1, the value of AVDD divide 4 output voltage can be obtained from ADC conversion result 1098 * |[4] |VTEMPSEL |Temperature Sensor Slope Select Bit 1099 * | | |This bit is used to select temperature sensor slope trend. 1100 * | | |0 = Temperature sensor negative temperature coefficient slope. 1101 * | | |1 = Temperature sensor positive temperature coefficient slope. 1102 * |[7] |ADCCSEL |ADC Controller Select Bit 1103 * | | |This bit is used to select ADC controller. 1104 * | | |0 = EADC0 controlled is active. 1105 * | | |1 = LPADC0 controller is active. 1106 * @var SYS_T::IPRST3 1107 * Offset: 0x20 Peripheral Reset Control Register 3 1108 * --------------------------------------------------------------------------------------------------- 1109 * |Bits |Field |Descriptions 1110 * | :----: | :----: | :---- | 1111 * |[7] |ACMP2RST |ACMP2 Controller Reset 1112 * | | |0 = ACMP2 controller normal operation. 1113 * | | |1 = ACMP2 controller reset. 1114 * |[8] |PWM0RST |PWM0 Controller Reset 1115 * | | |0 = PWM0 controller normal operation. 1116 * | | |1 = PWM0 controller reset. 1117 * |[9] |PWM1RST |PWM1 Controller Reset 1118 * | | |0 = PWM1 controller normal operation. 1119 * | | |1 = PWM1 controller reset. 1120 * |[15] |UTCPD0RST |UTCPD0 Controller Reset 1121 * | | |0 = UTCPD0 controller normal operation. 1122 * | | |1 = UTCPD0 controller reset. 1123 * @var SYS_T::VREFCTL 1124 * Offset: 0x28 VREF Control Register 1125 * --------------------------------------------------------------------------------------------------- 1126 * |Bits |Field |Descriptions 1127 * | :----: | :----: | :---- | 1128 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) 1129 * | | |00000 = VREF is from external pin. 1130 * | | |00011 = VREF is internal 1.6V. 1131 * | | |00111 = VREF is internal 2.0V. 1132 * | | |01011 = VREF is internal 2.5V. 1133 * | | |01111 = VREF is internal 3.0V. 1134 * | | |Others = Reserved. 1135 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1136 * |[7:6] |PRELOAD_SEL|Pre-load Timing Selection (Write Protect) 1137 * | | |00 = pre-load time is 60us for 0.1uF Capacitor. 1138 * | | |01 = pre-load time is 310us for 1uF Capacitor. 1139 * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. 1140 * | | |11 = pre-load time is 2650us for 10uF Capacitor. 1141 * |[24] |VBGFEN |Chip Internal Voltage Band-gap Force Enable Bit (Write Only) 1142 * | | |0 = Chip internal voltage band-gap controlled by ADC/ACMP/USB PHY if source selected. 1143 * | | |1 = Chip internal voltage band-gap force enable. 1144 * @var SYS_T::USBPHY 1145 * Offset: 0x2C USB PHY Control Register 1146 * --------------------------------------------------------------------------------------------------- 1147 * |Bits |Field |Descriptions 1148 * | :----: | :----: | :---- | 1149 * |[1:0] |USBROLE |USB Role Option (Write Protect) 1150 * | | |These two bits are used to select the role of USB. 1151 * | | |00 = Standard USB Device mode. 1152 * | | |01 = Standard USB Host mode. 1153 * | | |10 = ID dependent mode. 1154 * | | |11 = On-The-Go device mode. 1155 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1156 * |[2] |SBO |Note: This bit must always be kept 1 If set to 0, the result is unpredictable 1157 * |[8] |USBEN |USB PHY Enable Bit 1158 * | | |This bit is used to enable/disable USB PHY. 1159 * | | |0 = USB PHY Disabled. 1160 * | | |1 = USB PHY Enabled. 1161 * @var SYS_T::UTCPDCTL 1162 * Offset: 0x30 UTCPD Control Register 1163 * --------------------------------------------------------------------------------------------------- 1164 * |Bits |Field |Descriptions 1165 * | :----: | :----: | :---- | 1166 * |[0] |IOMODE |UTCPD0 as I/O mode 1167 * | | |This bit is used to define UTCPD0 CCx and CCDBx function 1168 * | | |0 = Pin as UTCPD0 CCx and CCDBx function. 1169 * | | |1 = Pin as general I/O function. 1170 * |[1] |POREN0 |UTCPD0 Power-on Enable Bit 1171 * | | |0 = UTCPD0 PHY in reset mode. 1172 * | | |1 = UTCPD0 PHY in normal mode. 1173 * | | |Note: user should set POREN0 to 1 after IOMODE is setting down. 1174 * |[10:8] |PD0VBDSS |UTCPD0 VBUS Detect Source Select 1175 * | | |UTCPD0 controller need a VBUS detect result to note if VBUS is connected 1176 * | | |For SPD0~2/NPD3/NPD4/NPD5 usage, ACMP can be another voltage detect method to detect VBUS pulg in or out 1177 * | | |This bit field is used to select UTCPD0 VBUS detect source 1178 * | | |And the selected result is VBDETSW0 1179 * | | |000 = UTCPD0 VBUS detect source from UTCPD0 PHY. 1180 * | | |001 = UTCPD0 VBUS detect source from ACMP0 output. 1181 * | | |010 = UTCPD0 VBUS detect source from ACMP1 output. 1182 * | | |011 = UTCPD0 VBUS detect source from ACMP2 output. 1183 * | | |Others = Reserved. 1184 * | | |Note: Before use UTCPD0 function, PDVBDETS should be set and cannot change during UTCPD0 operating. 1185 * |[12] |UDVBDETS |UDC11 VBUS Detect Source Select 1186 * | | |0 = UDC11 VBUS detect source from OTGPHY. 1187 * | | |1 = UDC11 VBUS detect source from VBDETSW0. 1188 * | | |Note: Before use UDC11 function, UDVBDETS should be set and cannot change during UDC11 operating. 1189 * @var SYS_T::GPA_MFOS 1190 * Offset: 0x80 GPIOA Multiple Function Output Select Register 1191 * --------------------------------------------------------------------------------------------------- 1192 * |Bits |Field |Descriptions 1193 * | :----: | :----: | :---- | 1194 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1195 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1196 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1197 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1198 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1199 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1200 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1201 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1202 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1203 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1204 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1205 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1206 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1207 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1208 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1209 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1210 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1211 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1212 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1213 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1214 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1215 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1216 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1217 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1218 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1219 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1220 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1221 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1222 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1223 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1224 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1225 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1226 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1227 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1228 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1229 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1230 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1231 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1232 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1233 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1234 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1235 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1236 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1237 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1238 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1239 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1240 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1241 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1242 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1243 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1244 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1245 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1246 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1247 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1248 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1249 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1250 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1251 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1252 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1253 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1254 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1255 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1256 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1257 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1258 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1259 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1260 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1261 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1262 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1263 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1264 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1265 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1266 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1267 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1268 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1269 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1270 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1271 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1272 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1273 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1274 * @var SYS_T::GPB_MFOS 1275 * Offset: 0x84 GPIOB Multiple Function Output Select Register 1276 * --------------------------------------------------------------------------------------------------- 1277 * |Bits |Field |Descriptions 1278 * | :----: | :----: | :---- | 1279 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1280 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1281 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1282 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1283 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1284 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1285 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1286 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1287 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1288 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1289 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1290 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1291 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1292 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1293 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1294 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1295 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1296 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1297 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1298 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1299 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1300 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1301 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1302 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1303 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1304 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1305 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1306 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1307 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1308 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1309 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1310 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1311 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1312 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1313 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1314 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1315 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1316 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1317 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1318 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1319 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1320 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1321 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1322 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1323 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1324 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1325 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1326 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1327 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1328 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1329 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1330 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1331 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1332 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1333 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1334 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1335 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1336 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1337 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1338 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1339 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1340 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1341 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1342 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1343 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1344 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1345 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1346 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1347 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1348 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1349 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1350 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1351 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1352 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1353 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1354 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1355 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1356 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1357 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1358 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1359 * @var SYS_T::GPC_MFOS 1360 * Offset: 0x88 GPIOC Multiple Function Output Select Register 1361 * --------------------------------------------------------------------------------------------------- 1362 * |Bits |Field |Descriptions 1363 * | :----: | :----: | :---- | 1364 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1365 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1366 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1367 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1368 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1369 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1370 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1371 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1372 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1373 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1374 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1375 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1376 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1377 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1378 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1379 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1380 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1381 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1382 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1383 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1384 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1385 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1386 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1387 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1388 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1389 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1390 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1391 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1392 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1393 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1394 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1395 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1396 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1397 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1398 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1399 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1400 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1401 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1402 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1403 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1404 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1405 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1406 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1407 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1408 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1409 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1410 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1411 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1412 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1413 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1414 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1415 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1416 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1417 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1418 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1419 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1420 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1421 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1422 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1423 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1424 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1425 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1426 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1427 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1428 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1429 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1430 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1431 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1432 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1433 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1434 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1435 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1436 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1437 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1438 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1439 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1440 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1441 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1442 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1443 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1444 * @var SYS_T::GPD_MFOS 1445 * Offset: 0x8C GPIOD Multiple Function Output Select Register 1446 * --------------------------------------------------------------------------------------------------- 1447 * |Bits |Field |Descriptions 1448 * | :----: | :----: | :---- | 1449 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1450 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1451 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1452 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1453 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1454 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1455 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1456 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1457 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1458 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1459 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1460 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1461 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1462 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1463 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1464 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1465 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1466 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1467 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1468 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1469 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1470 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1471 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1472 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1473 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1474 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1475 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1476 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1477 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1478 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1479 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1480 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1481 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1482 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1483 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1484 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1485 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1486 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1487 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1488 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1489 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1490 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1491 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1492 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1493 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1494 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1495 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1496 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1497 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1498 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1499 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1500 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1501 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1502 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1503 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1504 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1505 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1506 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1507 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1508 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1509 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1510 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1511 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1512 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1513 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1514 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1515 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1516 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1517 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1518 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1519 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1520 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1521 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1522 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1523 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1524 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1525 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1526 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1527 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1528 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1529 * @var SYS_T::GPE_MFOS 1530 * Offset: 0x90 GPIOE Multiple Function Output Select Register 1531 * --------------------------------------------------------------------------------------------------- 1532 * |Bits |Field |Descriptions 1533 * | :----: | :----: | :---- | 1534 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1535 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1536 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1537 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1538 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1539 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1540 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1541 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1542 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1543 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1544 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1545 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1546 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1547 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1548 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1549 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1550 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1551 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1552 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1553 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1554 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1555 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1556 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1557 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1558 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1559 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1560 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1561 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1562 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1563 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1564 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1565 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1566 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1567 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1568 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1569 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1570 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1571 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1572 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1573 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1574 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1575 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1576 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1577 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1578 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1579 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1580 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1581 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1582 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1583 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1584 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1585 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1586 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1587 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1588 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1589 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1590 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1591 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1592 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1593 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1594 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1595 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1596 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1597 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1598 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1599 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1600 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1601 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1602 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1603 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1604 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1605 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1606 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1607 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1608 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1609 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1610 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1611 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1612 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1613 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1614 * @var SYS_T::GPF_MFOS 1615 * Offset: 0x94 GPIOF Multiple Function Output Select Register 1616 * --------------------------------------------------------------------------------------------------- 1617 * |Bits |Field |Descriptions 1618 * | :----: | :----: | :---- | 1619 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1620 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1621 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1622 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1623 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1624 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1625 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1626 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1627 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1628 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1629 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1630 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1631 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1632 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1633 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1634 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1635 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1636 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1637 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1638 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1639 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1640 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1641 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1642 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1643 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1644 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1645 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1646 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1647 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1648 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1649 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1650 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1651 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1652 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1653 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1654 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1655 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1656 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1657 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1658 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1659 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1660 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1661 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1662 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1663 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1664 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1665 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1666 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1667 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1668 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1669 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1670 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1671 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1672 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1673 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1674 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1675 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1676 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1677 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1678 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1679 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1680 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1681 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1682 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1683 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1684 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1685 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1686 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1687 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1688 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1689 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1690 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1691 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1692 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1693 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1694 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1695 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1696 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1697 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1698 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1699 * @var SYS_T::GPG_MFOS 1700 * Offset: 0x98 GPIOG Multiple Function Output Select Register 1701 * --------------------------------------------------------------------------------------------------- 1702 * |Bits |Field |Descriptions 1703 * | :----: | :----: | :---- | 1704 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1705 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1706 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1707 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1708 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1709 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1710 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1711 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1712 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1713 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1714 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1715 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1716 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1717 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1718 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1719 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1720 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1721 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1722 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1723 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1724 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1725 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1726 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1727 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1728 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1729 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1730 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1731 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1732 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1733 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1734 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1735 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1736 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1737 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1738 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1739 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1740 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1741 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1742 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1743 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1744 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1745 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1746 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1747 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1748 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1749 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1750 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1751 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1752 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1753 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1754 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1755 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1756 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1757 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1758 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1759 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1760 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1761 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1762 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1763 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1764 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1765 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1766 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1767 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1768 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1769 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1770 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1771 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1772 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1773 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1774 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1775 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1776 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1777 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1778 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1779 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1780 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1781 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1782 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1783 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1784 * @var SYS_T::GPH_MFOS 1785 * Offset: 0x9C GPIOH Multiple Function Output Select Register 1786 * --------------------------------------------------------------------------------------------------- 1787 * |Bits |Field |Descriptions 1788 * | :----: | :----: | :---- | 1789 * |[0] |MFOS0 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1790 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1791 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1792 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1793 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1794 * |[1] |MFOS1 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1795 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1796 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1797 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1798 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1799 * |[2] |MFOS2 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1800 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1801 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1802 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1803 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1804 * |[3] |MFOS3 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1805 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1806 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1807 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1808 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1809 * |[4] |MFOS4 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1810 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1811 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1812 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1813 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1814 * |[5] |MFOS5 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1815 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1816 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1817 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1818 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1819 * |[6] |MFOS6 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1820 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1821 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1822 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1823 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1824 * |[7] |MFOS7 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1825 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1826 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1827 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1828 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1829 * |[8] |MFOS8 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1830 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1831 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1832 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1833 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1834 * |[9] |MFOS9 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1835 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1836 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1837 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1838 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1839 * |[10] |MFOS10 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1840 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1841 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1842 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1843 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1844 * |[11] |MFOS11 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1845 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1846 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1847 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1848 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1849 * |[12] |MFOS12 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1850 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1851 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1852 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1853 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1854 * |[13] |MFOS13 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1855 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1856 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1857 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1858 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1859 * |[14] |MFOS14 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1860 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1861 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1862 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1863 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1864 * |[15] |MFOS15 |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 1865 * | | |This bit used to select multiple function pin output mode type for Px.n pin 1866 * | | |0 = Multiple function pin output mode type is Push-pull mode. 1867 * | | |1 = Multiple function pin output mode type is Open-drain mode. 1868 * | | |Note: For more information about Px.n, please refer to the "PIN CONFIGURATION" chapter. 1869 * @var SYS_T::MIRCTCTL 1870 * Offset: 0xB0 MIRC1M Trim Control Register 1871 * --------------------------------------------------------------------------------------------------- 1872 * |Bits |Field |Descriptions 1873 * | :----: | :----: | :---- | 1874 * |[1:0] |FREQSEL |Trim Frequency Selection 1875 * | | |This field indicates the target frequency of 1 MHz internal high speed RC oscillator (MIRC) auto trim. 1876 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 1877 * | | |00 = Disable MIRC auto trim function. 1878 * | | |01 = Enable MIRC auto trim function and trim MIRC to 1 MHz. 1879 * | | |10 = Reserved. 1880 * | | |11 = Reserved. 1881 * |[3:2] |ACCURSEL |Trim Accuracy Selection 1882 * | | |This field indicates the target frequency accuracy of 1 MHz internal high speed RC oscillator (MIRC) auto trim. 1883 * | | |00 = Accuracy is +-0.25% deviation within all temperature ranges. 1884 * | | |01 = Accuracy is +-0.50% deviation within all temperature ranges. 1885 * | | |10 = Accuracy is +-0.75% deviation within all temperature ranges. 1886 * | | |11 = Accuracy is +-1% deviation within all temperature ranges. 1887 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 1888 * | | |This field defines that trim value calculation is based on how many reference clocks. 1889 * | | |00 = Trim value calculation is based on average difference in 32 clocks of reference clock. 1890 * | | |01 = Trim value calculation is based on average difference in 64 clocks of reference clock. 1891 * | | |10 = Trim value calculation is based on average difference in 96 clocks of reference clock. 1892 * | | |11 = Trim value calculation is based on average difference in 128 clocks of reference clock. 1893 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 1894 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 1895 * | | |This field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked. 1896 * | | |Once the MIRC locked, the internal trim value update counter will be reset. 1897 * | | |If the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 1898 * | | |00 = Trim retry count limitation is 64 loops. 1899 * | | |01 = Trim retry count limitation is 128 loops. 1900 * | | |10 = Trim retry count limitation is 256 loops. 1901 * | | |11 = Trim retry count limitation is 512 loops. 1902 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 1903 * | | |0 = The trim operation is keep going if clock is inaccuracy. 1904 * | | |1 = The trim operation is stopped if clock is inaccuracy. 1905 * |[9] |BOUNDEN |Boundary Enable Bit 1906 * | | |0 = Boundary function Disabled. 1907 * | | |1 = Boundary function Enabled. 1908 * |[10] |REFCKSEL |Reference Clock Selection 1909 * | | |0 = MIRC trim reference clock is from LXT (32.768 kHz). 1910 * | | |1 = Reserved. 1911 * | | |Note: MIRC trim reference clock is 20 kHz in test mode. 1912 * |[20:16] |BOUNDARY |Boundary Selection 1913 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 1914 * | | |Note: This field is effective only when the BOUNDEN(SYS_MIRCTRIMCTL[9]) is enabled. 1915 * @var SYS_T::MIRCTIEN 1916 * Offset: 0xB4 MIRC1M Trim Interrupt Enable Register 1917 * --------------------------------------------------------------------------------------------------- 1918 * |Bits |Field |Descriptions 1919 * | :----: | :----: | :---- | 1920 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 1921 * | | |This bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_MIRCTCTL[1:0]). 1922 * | | |If this bit is high and TFAILIF(SYS_MIRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. 1923 * | | |0 = Disable TFAILIF(SYS_MIRCTISTS[1]) status to trigger an interrupt to CPU. 1924 * | | |1 = Enable TFAILIF(SYS_MIRCTISTS[1]) status to trigger an interrupt to CPU. 1925 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 1926 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 1927 * | | |If this bit is set to1, and CLKERRIF(SYS_MIRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 1928 * | | |0 = Disable CLKERRIF(SYS_MIRCTISTS[2]) status to trigger an interrupt to CPU. 1929 * | | |1 = Enable CLKERRIF(SYS_MIRCTISTS[2]) status to trigger an interrupt to CPU. 1930 * @var SYS_T::MIRCTISTS 1931 * Offset: 0xB8 MIRC1M Trim Interrupt Status Register 1932 * --------------------------------------------------------------------------------------------------- 1933 * |Bits |Field |Descriptions 1934 * | :----: | :----: | :---- | 1935 * |[0] |FREQLOCK |MIRC Frequency Lock Status 1936 * | | |This bit indicates the MIRC frequency is locked. 1937 * | | |This is a status bit and doesn't trigger any interrupt 1938 * | | |Write 1 to clear this to 0 1939 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 1940 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 1 MHz yet. 1941 * | | |1 = The internal high-speed oscillator frequency locked at 1 MHz. 1942 * |[1] |TFAILIF |Trim Failure Interrupt Status 1943 * | | |This bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked 1944 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 1945 * | | |If this bit is set and TFAILIEN(SYS_MIRCTIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached 1946 * | | |Write 1 to clear this to 0. 1947 * | | |0 = Trim value update limitation count does not reach. 1948 * | | |1 = Trim value update limitation count reached and MIRC frequency still not locked. 1949 * |[2] |CLKERRIF |Clock Error Interrupt Status 1950 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 1 MHz internal high speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy 1951 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCTCTL[8]) is set to 1. 1952 * | | |If this bit is set and CLKEIEN(SYS_MIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy 1953 * | | |Write 1 to clear this to 0. 1954 * | | |0 = Clock frequency is accuracy. 1955 * | | |1 = Clock frequency is inaccuracy. 1956 * |[3] |OVBDIF |Over Boundary Status 1957 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 1958 * | | |0 = Over boundary coundition did not occur. 1959 * | | |1 = Over boundary coundition occurred. 1960 * | | |Note 1: Write 1 to clear this flag. 1961 * @var SYS_T::SRAM_INTCTL 1962 * Offset: 0xC0 System SRAM Interrupt Enable Control Register 1963 * --------------------------------------------------------------------------------------------------- 1964 * |Bits |Field |Descriptions 1965 * | :----: | :----: | :---- | 1966 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit 1967 * | | |0 = SRAM parity check error interrupt Disabled. 1968 * | | |1 = SRAM parity check error interrupt Enabled. 1969 * @var SYS_T::SRAM_STATUS 1970 * Offset: 0xC4 System SRAM Parity Error Status Register 1971 * --------------------------------------------------------------------------------------------------- 1972 * |Bits |Field |Descriptions 1973 * | :----: | :----: | :---- | 1974 * |[0] |PERRIF |SRAM Parity Check Error Flag 1975 * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 1976 * | | |0 = No System SRAM parity error. 1977 * | | |1 = System SRAM parity error occur. 1978 * @var SYS_T::SRAM_ERRADDR 1979 * Offset: 0xC8 System SRAM Parity Check Error Address Register 1980 * --------------------------------------------------------------------------------------------------- 1981 * |Bits |Field |Descriptions 1982 * | :----: | :----: | :---- | 1983 * |[31:0] |ERRADDR |System SRAM Parity Error Address 1984 * | | |This register shows system SRAM parity error byte address. 1985 * @var SYS_T::SRAM_BISTCTL 1986 * Offset: 0xD0 System SRAM BIST Test Control Register 1987 * --------------------------------------------------------------------------------------------------- 1988 * |Bits |Field |Descriptions 1989 * | :----: | :----: | :---- | 1990 * |[0] |SRBIST0 |SRAM Bank0 BIST Enable Bit (Write Protect) 1991 * | | |This bit enables BIST test for SRAM bank0. 1992 * | | |0 = system SRAM bank0 BIST Disabled. 1993 * | | |1 = system SRAM bank0 BIST Enabled. 1994 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1995 * |[1] |SRBIST1 |SRAM Bank1 BIST Enable Bit (Write Protect) 1996 * | | |This bit enables BIST test for SRAM bank1. 1997 * | | |0 = system SRAM bank1 BIST Disabled. 1998 * | | |1 = system SRAM bank1 BIST Enabled. 1999 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2000 * |[2] |CRBIST |CACHE BIST Enable Bit (Write Protect) 2001 * | | |This bit enables BIST test for CACHE RAM. 2002 * | | |0 = system CACHE BIST Disabled. 2003 * | | |1 = system CACHE BIST Enabled. 2004 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2005 * |[3] |CANFDBIST |CANFDx BIST Enable Bit (Write Protect) 2006 * | | |This bit enables BIST test for CANFDx RAM. 2007 * | | |0 = system CANFDx BIST Disabled. 2008 * | | |1 = system CANFDx BIST Enabled. 2009 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2010 * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) 2011 * | | |This bit enables BIST test for USB RAM. 2012 * | | |0 = system USB BIST Disabled. 2013 * | | |1 = system USB BIST Enabled. 2014 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2015 * |[11] |LPSRBIST |Low Power SRAM BIST Enable Bit (Write Protect) 2016 * | | |This bit enables BIST test for LPSRAM. 2017 * | | |0 = system LPSRAM BIST Disabled. 2018 * | | |1 = system LPSRAM BIST Enabled. 2019 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2020 * @var SYS_T::SRAM_BISTSTS 2021 * Offset: 0xD4 System SRAM BIST Test Status Register 2022 * --------------------------------------------------------------------------------------------------- 2023 * |Bits |Field |Descriptions 2024 * | :----: | :----: | :---- | 2025 * |[0] |SRBISTEF0 |1st System SRAM BIST Fail Flag 2026 * | | |0 = 1st system SRAM BIST test pass. 2027 * | | |1 = 1st system SRAM BIST test fail. 2028 * |[1] |SRBISTEF1 |2nd System SRAM BIST Fail Flag 2029 * | | |0 = 2nd system SRAM BIST test pass. 2030 * | | |1 = 2nd system SRAM BIST test fail. 2031 * |[2] |CRBISTEF |CACHE SRAM BIST Fail Flag 2032 * | | |0 = System CACHE RAM BIST test pass. 2033 * | | |1 = System CACHE RAM BIST test fail. 2034 * |[3] |CANBEF |CAN SRAM BIST Fail Flag 2035 * | | |0 = CAN SRAM BIST test pass. 2036 * | | |1 = CAN SRAM BIST test fail. 2037 * |[4] |USBBEF |USB SRAM BIST Fail Flag 2038 * | | |0 = USB SRAM BIST test pass. 2039 * | | |1 = USB SRAM BIST test fail. 2040 * |[11] |LPSRBEF |Low Power SRAM BIST Fail Flag 2041 * | | |0 = LPSRAM BIST test pass. 2042 * | | |1 = LPSRAM BIST test fail. 2043 * |[16] |SRBEND0 |1st SRAM BIST Test Finish 2044 * | | |0 = 1st system SRAM BIST active. 2045 * | | |1 =1st system SRAM BIST finish. 2046 * |[17] |SRBEND1 |2nd SRAM BIST Test Finish 2047 * | | |0 = 2nd system SRAM BIST is active. 2048 * | | |1 = 2nd system SRAM BIST finish. 2049 * |[18] |CRBEND |CACHE SRAM BIST Test Finish 2050 * | | |0 = System CACHE RAM BIST is active. 2051 * | | |1 = System CACHE RAM BIST test finish. 2052 * |[19] |CANBEND |CAN SRAM BIST Test Finish 2053 * | | |0 = CAN SRAM BIST is active. 2054 * | | |1 = CAN SRAM BIST test finish. 2055 * |[20] |USBBEND |USB SRAM BIST Test Finish 2056 * | | |0 = USB SRAM BIST is active. 2057 * | | |1 = USB SRAM BIST test finish. 2058 * |[27] |LPSRBEND |Low Power SRAM BIST Test Finish 2059 * | | |0 = LPSRAM BIST is active. 2060 * | | |1 = LPSRAM BIST test finish. 2061 * @var SYS_T::SRAMPC0 2062 * Offset: 0xDC SRAM Power Mode Control Register 0 2063 * --------------------------------------------------------------------------------------------------- 2064 * |Bits |Field |Descriptions 2065 * | :----: | :----: | :---- | 2066 * |[2:0] |SRAM0PM |SRAM Group 0 Power Mode Select (Write Protect) 2067 * | | |This field can control SRAM group0 in bank0 (8k) power mode for range 0x2000_0000 - 0x2000_1FFF. 2068 * | | |000 = Normal mode. 2069 * | | |010 = Retention mode. 2070 * | | |011 = Shut down mode (No Retention). 2071 * | | |Other = Reserved. 2072 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 2073 * | | |Note 2: Mode change need to wait PCBUSY=0. 2074 * | | |Note 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal mode, not mode change between Power-down mode. 2075 * | | |Note 4: Power saving priority first 2076 * | | |If CLK_PMUCTL setting SRAM at retention mode but SYS_SRAMPC0 setting to shut mode, SRAM go to shut down mode. 2077 * |[6:4] |SRAM1PM |SRAM Group 1 Power Mode Select (Write Protect) 2078 * | | |This field can control SRAM group1 in bank0 (16k) power mode for range 0x2000_2000 - 0x2000_5FFF. 2079 * | | |000 = Normal mode. 2080 * | | |010 = Retention mode. 2081 * | | |011 = Shut down mode (No Retention). 2082 * | | |Other = Reserved. 2083 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 2084 * | | |Note 2: Mode change need to wait PCBUSY=0. 2085 * | | |Note 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal mode, not mode change between Power-down mode. 2086 * | | |Note 4: Power saving priority first 2087 * | | |If CLK_PMUCTL setting SRAM at retention mode but SYS_SRAMPC0 setting to shut mode, SRAM go to shut down mode. 2088 * |[10:8] |SRAM2PM |SRAM Group 2 Power Mode Select (Write Protect) 2089 * | | |This field can control SRAM group2 in bank0 (16k) power mode for range 0x2000_6000 - 0x2000_9FFF. 2090 * | | |000 = Normal mode. 2091 * | | |010 = Retention mode. 2092 * | | |011 = Shut down mode (No Retention). 2093 * | | |Other = Reserved. 2094 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 2095 * | | |Note 2: Mode change need to wait PCBUSY=0. 2096 * | | |Note 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal mode, not mode change between Power-down mode. 2097 * | | |Note 4: Power saving priority first 2098 * | | |If CLK_PMUCTL setting SRAM at retention mode but SYS_SRAMPC0 setting to shut mode, SRAM go to shut down mode. 2099 * |[14:12] |SRAM3PM |SRAM Group 3 Power Mode Select (Write Protect) 2100 * | | |This field can control SRAM group 3 in bank1 (32k) power mode for range 0x2000_A000 - 0x2001_1FFF. 2101 * | | |000 = Normal mode. 2102 * | | |010 = Retention mode. 2103 * | | |011 = Shut down mode (No Retention). 2104 * | | |Other = Reserved. 2105 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 2106 * | | |Note 2: Mode change need to wait PCBUSY=0. 2107 * | | |Note 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal mode, not mode change between Power-down mode. 2108 * | | |Note 4: Power saving priority first 2109 * | | |If CLK_PMUCTL setting SRAM at retention mode but SYS_SRAMPC0 setting to shut mode, SRAM go to shut down mode. 2110 * |[18:16] |SRAM4PM |SRAM Group 4 Power Mode Select (Write Protect) 2111 * | | |This field can control SRAM group 4 in bank1 (32k) power mode for range 0x2001_2000 - 0x2001_9FFF. 2112 * | | |000 = Normal mode. 2113 * | | |010 = Retention mode. 2114 * | | |011 = Shut down mode (No Retention). 2115 * | | |Other = Reserved. 2116 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 2117 * | | |Note 2: Mode change need to wait PCBUSY=0. 2118 * | | |Note 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal mode, not mode change between Power-down mode. 2119 * | | |Note 4: Power saving priority first 2120 * | | |If CLK_PMUCTL setting SRAM at retention mode but SYS_SRAMPC0 setting to shut mode, SRAM go to shut down mode. 2121 * |[22:20] |SRAM5PM |SRAM Group 5 Power Mode Select (Write Protect) 2122 * | | |This field can control SRAM group 5 in bank1 (64k) power mode for range 0x2001_A000 - 0x2002_9FFF. 2123 * | | |000 = Normal mode. 2124 * | | |010 = Retention mode. 2125 * | | |011 = Shut down mode (No Retention). 2126 * | | |Other = Reserved. 2127 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 2128 * | | |Note 2: Mode change need to wait PCBUSY=0. 2129 * | | |Note 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal mode, not mode change between Power-down mode. 2130 * | | |Note 4: Power saving priority first 2131 * | | |If CLK_PMUCTL setting SRAM at retention mode but SYS_SRAMPC0 setting to shut mode, SRAM go to shut down mode. 2132 * |[26:24] |SRAM6PM |SRAM Group 6 Power Mode Select (Write Protect) 2133 * | | |This field can control SRAM group 6 in bank2 (8k) power mode for range 0x2800_0000 - 0x2800_1FFF. 2134 * | | |000 = Normal mode. 2135 * | | |010 = Retention mode. 2136 * | | |011 = Shut down mode (No Retention). 2137 * | | |Other = Reserved. 2138 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 2139 * | | |Note 2: Mode change need to wait PCBUSY=0. 2140 * | | |Note 3: Only support from normal mode to each Power-down mode and each Power-down mode to normal mode, not mode change between Power-down mode. 2141 * | | |Note 4: Power saving priority first 2142 * | | |If CLK_PMUCTL setting SRAM at retention mode but SYS_SRAMPC0 setting to shut mode, SRAM go to shut down mode. 2143 * | | |Note 5: Beforce setting SRAM6PM, set LPSRAMDR(LPSCC_SRAMCTL[4])=0 firstly. 2144 * |[31] |PCBUSY |Power Changing Busy Flag (Read Only) 2145 * | | |This bit indicate SRAM power changing. 2146 * | | |0 = SRAM power change finish. 2147 * | | |1 = SRAM power changing. 2148 * @var SYS_T::HIRCTCTL 2149 * Offset: 0xE4 HIRC48M Trim Control Register 2150 * --------------------------------------------------------------------------------------------------- 2151 * |Bits |Field |Descriptions 2152 * | :----: | :----: | :---- | 2153 * |[1:0] |FREQSEL |Trim Frequency Selection 2154 * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. 2155 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 2156 * | | |00 = Disable HIRC auto trim function. 2157 * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. 2158 * | | |10 = Reserved. 2159 * | | |11 = Reserved. 2160 * |[3:2] |ACCURSEL |Trim Accuracy Selection 2161 * | | |This field indicates the target frequency accuracy of 48 MHz internal high speed RC oscillator (HIRC) auto trim. 2162 * | | |00 = Accuracy is +-0.25% deviation within all temperature ranges. 2163 * | | |01 = Accuracy is +-0.50% deviation within all temperature ranges. 2164 * | | |10 = Accuracy is +-0.75% deviation within all temperature ranges. 2165 * | | |11 = Accuracy is +-1% deviation within all temperature ranges. 2166 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 2167 * | | |This field defines that trim value calculation is based on how many reference clocks. 2168 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 2169 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 2170 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 2171 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 2172 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 2173 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 2174 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 2175 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 2176 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 2177 * | | |00 = Trim retry count limitation is 64 loops. 2178 * | | |01 = Trim retry count limitation is 128 loops. 2179 * | | |10 = Trim retry count limitation is 256 loops. 2180 * | | |11 = Trim retry count limitation is 512 loops. 2181 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 2182 * | | |0 = The trim operation is keep going if clock is inaccuracy. 2183 * | | |1 = The trim operation is stopped if clock is inaccuracy. 2184 * |[9] |BOUNDEN |Boundary Enable Bit 2185 * | | |0 = Boundary function Disabled. 2186 * | | |1 = Boundary function Enabled. 2187 * |[10] |REFCKSEL |Reference Clock Selection 2188 * | | |0 = HIRC trim reference clock is from LXT (32.768 kHz). 2189 * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. 2190 * | | |Note: HIRC trim reference clock is 20 kHz in test mode. 2191 * |[20:16] |BOUNDARY |Boundary Selection 2192 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 2193 * | | |Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled. 2194 * @var SYS_T::HIRCTIEN 2195 * Offset: 0xE8 HIRC48M Trim Interrupt Enable Register 2196 * --------------------------------------------------------------------------------------------------- 2197 * |Bits |Field |Descriptions 2198 * | :----: | :----: | :---- | 2199 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 2200 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). 2201 * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 2202 * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 2203 * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 2204 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 2205 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 2206 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2207 * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 2208 * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 2209 * @var SYS_T::HIRCTISTS 2210 * Offset: 0xEC HIRC48M Trim Interrupt Status Register 2211 * --------------------------------------------------------------------------------------------------- 2212 * |Bits |Field |Descriptions 2213 * | :----: | :----: | :---- | 2214 * |[0] |FREQLOCK |HIRC Frequency Lock Status 2215 * | | |This bit indicates the HIRC frequency is locked. 2216 * | | |This is a status bit and doesn't trigger any interrupt 2217 * | | |Write 1 to clear this to 0 2218 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 2219 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. 2220 * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. 2221 * |[1] |TFAILIF |Trim Failure Interrupt Status 2222 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked 2223 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 2224 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached 2225 * | | |Write 1 to clear this to 0. 2226 * | | |0 = Trim value update limitation count does not reach. 2227 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 2228 * |[2] |CLKERRIF |Clock Error Interrupt Status 2229 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy 2230 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. 2231 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy 2232 * | | |Write 1 to clear this to 0. 2233 * | | |0 = Clock frequency is accuracy. 2234 * | | |1 = Clock frequency is inaccuracy. 2235 * |[3] |OVBDIF |Over Boundary Status 2236 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 2237 * | | |0 = Over boundary coundition did not occur. 2238 * | | |1 = Over boundary coundition occurred. 2239 * | | |Note: Write 1 to clear this flag. 2240 * @var SYS_T::IRCTCTL 2241 * Offset: 0xF0 HIRC Trim Control Register 2242 * --------------------------------------------------------------------------------------------------- 2243 * |Bits |Field |Descriptions 2244 * | :----: | :----: | :---- | 2245 * |[1:0] |FREQSEL |Trim Frequency Selection 2246 * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. 2247 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 2248 * | | |00 = Disable HIRC auto trim function. 2249 * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. 2250 * | | |10 = Reserved. 2251 * | | |11 = Reserved. 2252 * |[3:2] |ACCURSEL |Trim Accuracy Selection 2253 * | | |This field indicates the target frequency accuracy of 12 MHz internal high speed RC oscillator (IRC) auto trim. 2254 * | | |00 = Accuracy is +-0.25% deviation within all temperature ranges. 2255 * | | |01 = Accuracy is +-0.50% deviation within all temperature ranges. 2256 * | | |10 = Accuracy is +-0.75% deviation within all temperature ranges. 2257 * | | |11 = Accuracy is +-1% deviation within all temperature ranges. 2258 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 2259 * | | |This field defines that trim value calculation is based on how many reference clocks. 2260 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 2261 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 2262 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 2263 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 2264 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 2265 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 2266 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 2267 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 2268 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 2269 * | | |00 = Trim retry count limitation is 64 loops. 2270 * | | |01 = Trim retry count limitation is 128 loops. 2271 * | | |10 = Trim retry count limitation is 256 loops. 2272 * | | |11 = Trim retry count limitation is 512 loops. 2273 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 2274 * | | |0 = The trim operation is keep going if clock is inaccuracy. 2275 * | | |1 = The trim operation is stopped if clock is inaccuracy. 2276 * |[9] |BOUNDEN |Boundary Enable Bit 2277 * | | |0 = Boundary function Disabled. 2278 * | | |1 = Boundary function Enabled. 2279 * |[10] |REFCKSEL |Reference Clock Selection 2280 * | | |0 = HIRC trim reference clock is from LXT (32.768 kHz). 2281 * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. 2282 * | | |Note: HIRC trim reference clock is 20 kHz in test mode. 2283 * |[20:16] |BOUNDARY |Boundary Selection 2284 * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. 2285 * | | |Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled. 2286 * @var SYS_T::IRCTIEN 2287 * Offset: 0xF4 HIRC Trim Interrupt Enable Register 2288 * --------------------------------------------------------------------------------------------------- 2289 * |Bits |Field |Descriptions 2290 * | :----: | :----: | :---- | 2291 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 2292 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). 2293 * | | |If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 2294 * | | |0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 2295 * | | |1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 2296 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 2297 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 2298 * | | |If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 2299 * | | |0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 2300 * | | |1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 2301 * @var SYS_T::IRCTISTS 2302 * Offset: 0xF8 HIRC Trim Interrupt Status Register 2303 * --------------------------------------------------------------------------------------------------- 2304 * |Bits |Field |Descriptions 2305 * | :----: | :----: | :---- | 2306 * |[0] |FREQLOCK |HIRC Frequency Lock Status 2307 * | | |This bit indicates the HIRC frequency is locked. 2308 * | | |This is a status bit and doesn't trigger any interrupt 2309 * | | |Write 1 to clear this to 0 2310 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 2311 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. 2312 * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. 2313 * |[1] |TFAILIF |Trim Failure Interrupt Status 2314 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked 2315 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. 2316 * | | |If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached 2317 * | | |Write 1 to clear this to 0. 2318 * | | |0 = Trim value update limitation count does not reach. 2319 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 2320 * |[2] |CLKERRIF |Clock Error Interrupt Status 2321 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy 2322 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. 2323 * | | |If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy 2324 * | | |Write 1 to clear this to 0. 2325 * | | |0 = Clock frequency is accuracy. 2326 * | | |1 = Clock frequency is inaccuracy. 2327 * |[3] |OVBDIF |Over Boundary Status 2328 * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. 2329 * | | |0 = Over boundary coundition did not occur. 2330 * | | |1 = Over boundary coundition occurred. 2331 * | | |Note: Write 1 to clear this flag. 2332 * @var SYS_T::RAMPGCTL 2333 * Offset: 0xFC RRAM Power Gating Contol Register 2334 * --------------------------------------------------------------------------------------------------- 2335 * |Bits |Field |Descriptions 2336 * | :----: | :----: | :---- | 2337 * |[0] |RRAMPGEN0 |RRAM Bank0 Power Gating Enable Bit 2338 * | | |0 = RRAM bank0 power gating disabled. 2339 * | | |1 = RRAM bank0 power gating enabled. 2340 * |[1] |RRAMPGDN0 |RRAM Bank0 Power Gating Done Flag(Read Only) 2341 * | | |0 = RRAM bank0 power switch is openoing. 2342 * | | |1 = RRAM bank0 power gating done. 2343 * |[2] |RRAMBUSY0 |RRAM Bank0 Busy Flag (Read Only) 2344 * | | |0 = RRAM bank0 in stand by mode. 2345 * | | |1 = RRAM bank0 is busy. 2346 * |[4] |RRAMPGEN1 |RRAM Bank1 Power Gating Enable Bit 2347 * | | |0 = RRAM bank1 power gating disabled. 2348 * | | |1 = RRAM bank1 power gating enabled. 2349 * |[5] |RRAMPGDN1 |RRAM Bank1 Power Gating Done Flag(Read Only) 2350 * | | |0 = RRAM bank1 power switch is openoing. 2351 * | | |1 = RRAM bank1 power gating done. 2352 * |[6] |RRAMBUSY1 |RRAM Bank1 Busy Flag(Read Only) 2353 * | | |0 = RRAM bank1 in stand by mode. 2354 * | | |1 = RRAM bank1 is busy. 2355 * @var SYS_T::REGLCTL 2356 * Offset: 0x100 Register Lock Control Register 2357 * --------------------------------------------------------------------------------------------------- 2358 * |Bits |Field |Descriptions 2359 * | :----: | :----: | :---- | 2360 * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) 2361 * | | |Some registers have write-protection function 2362 * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field. 2363 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 2364 * | | |REGLCTL[0] 2365 * | | |Register Lock Control Disable Index (Read Only) 2366 * | | |0 = Write-protection Enabled for writing protected registers. 2367 * | | |Any write to the protected register is ignored. 2368 * | | |1 = Write-protection Disabled for writing protected registers. 2369 * @var SYS_T::PORDISAN 2370 * Offset: 0x1EC Analog POR Disable Control Register 2371 * --------------------------------------------------------------------------------------------------- 2372 * |Bits |Field |Descriptions 2373 * | :----: | :----: | :---- | 2374 * |[15:0] |POROFFAN |Power-on Reset Enable Bit (Write Protect) 2375 * | | |After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. 2376 * | | |The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: 2377 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 2378 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 2379 * @var SYS_T::CSERVER 2380 * Offset: 0x1F4 Chip Series Version Register 2381 * --------------------------------------------------------------------------------------------------- 2382 * |Bits |Field |Descriptions 2383 * | :----: | :----: | :---- | 2384 * |[7:0] |VERSION |Chip Series Version 2385 * | | |These bits indicate the series version of chip. 2386 * | | |00 = M2L31xxDAE. 2387 * | | |01 = M2L31xx4AE. 2388 * | | |Others = Reserved. 2389 * @var SYS_T::PLCTL 2390 * Offset: 0x1F8 Power Level Control Register 2391 * --------------------------------------------------------------------------------------------------- 2392 * |Bits |Field |Descriptions 2393 * | :----: | :----: | :---- | 2394 * |[2:0] |PLSEL |Power Level Select (Write Protect) 2395 * | | |These bits indicate the status of power level. 2396 * | | |001 = Power level is PL1. 2397 * | | |010 = Power level is PL2. 2398 * | | |011 = Power level is PL3. 2399 * | | |Others = Reserved. 2400 * | | |Note : Write ignore when wtire reserved setting. 2401 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 2402 * |[3] |PLKEEP |Power Level keep for wakeup(Write Protect) 2403 * | | |0 = Power level back to default PL1 when SPD0~2 wakeup. 2404 * | | |1 = Power level back to normal run voltage when SPD0~2 wakeup. 2405 * | | |Note : SPD reset type wakeup, power level back to default PL1 even if PLKEEP=1. 2406 * @var SYS_T::PLSTS 2407 * Offset: 0x1FC Power Level Status Register 2408 * --------------------------------------------------------------------------------------------------- 2409 * |Bits |Field |Descriptions 2410 * | :----: | :----: | :---- | 2411 * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) 2412 * | | |This bit is set by hardware when power level is changing 2413 * | | |After power level change is completed, this bit will be cleared automatically by hardware. 2414 * | | |0 = Core voltage change is completed. 2415 * | | |1 = Core voltage change is ongoing. 2416 * |[10:8] |PLSTATUS |Power Level Status (Read Only) 2417 * | | |This bit indicates the status of power level. 2418 * | | |001 = Power level is PL1. 2419 * | | |010 = Power level is PL2. 2420 * | | |011 = Power level is PL3. 2421 * | | |Others = Reserved. 2422 * @var SYS_T::INIVTOR 2423 * Offset: 0x310 Initial VTOR Control Register 2424 * --------------------------------------------------------------------------------------------------- 2425 * |Bits |Field |Descriptions 2426 * | :----: | :----: | :---- | 2427 * |[31:10] |INIVTOR |Initial VTOR Control Register 2428 * | | |This is the register to set the address of vector table after CPU reseted or chip waked up from SPD0~2 mode. 2429 * | | |The value will be loaded to Vector Table Offset Register, which is at the address 0xE000ED08, when CPU reseted or chip wake up from SPD0~2 mode. 2430 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 2431 * @var SYS_T::GPA_MFP0 2432 * Offset: 0x500 GPIOA Multiple Function Control Register 0 2433 * --------------------------------------------------------------------------------------------------- 2434 * |Bits |Field |Descriptions 2435 * | :----: | :----: | :---- | 2436 * |[4:0] |PA0MFP |PA.0 Multi-function Pin Selection 2437 * | | |03 = QSPI0_MOSI0 2438 * | | |04 = SPI0_MOSI 2439 * | | |07 = UART0_RXD 2440 * | | |08 = UART1_nRTS 2441 * | | |09 = I2C2_SDA 2442 * | | |10 = CANFD1_RXD 2443 * | | |11 = EPWM0_BRAKE0 2444 * | | |12 = PWM0_CH0 2445 * | | |13 = EPWM0_CH5 2446 * | | |14 = ACMP2_WLAT 2447 * | | |15 = DAC0_ST 2448 * | | |16 = TK_TK8 2449 * | | |17 = UTCPD0_VCNEN1 2450 * | | |20 = LPSPI0_MOSI 2451 * | | |21 = LPUART0_RXD 2452 * | | |23 = LPIO0 2453 * |[12:8] |PA1MFP |PA.1 Multi-function Pin Selection 2454 * | | |03 = QSPI0_MISO0 2455 * | | |04 = SPI0_MISO 2456 * | | |07 = UART0_TXD 2457 * | | |08 = UART1_nCTS 2458 * | | |09 = I2C2_SCL 2459 * | | |10 = CANFD1_TXD 2460 * | | |11 = EQEI0_INDEX 2461 * | | |12 = PWM0_CH1 2462 * | | |13 = EPWM0_CH4 2463 * | | |14 = ACMP2_O 2464 * | | |15 = DAC1_ST 2465 * | | |16 = TK_TK7 2466 * | | |17 = UTCPD0_FRSTX1 2467 * | | |18 = UTCPD0_DISCHG 2468 * | | |20 = LPSPI0_MISO 2469 * | | |21 = LPUART0_TXD 2470 * | | |23 = LPIO1 2471 * |[20:16] |PA2MFP |PA.2 Multi-function Pin Selection 2472 * | | |03 = QSPI0_CLK 2473 * | | |04 = SPI0_CLK 2474 * | | |05 = UART4_RXD 2475 * | | |07 = I2C0_SMBSUS 2476 * | | |08 = UART1_RXD 2477 * | | |09 = I2C1_SDA 2478 * | | |11 = EQEI0_A 2479 * | | |12 = PWM0_CH2 2480 * | | |13 = EPWM0_CH3 2481 * | | |16 = TK_TK6 2482 * | | |17 = UTCPD0_VBSRCEN 2483 * | | |20 = LPSPI0_CLK 2484 * |[28:24] |PA3MFP |PA.3 Multi-function Pin Selection 2485 * | | |03 = QSPI0_SS 2486 * | | |04 = SPI0_SS 2487 * | | |05 = UART4_TXD 2488 * | | |06 = TK_SE 2489 * | | |07 = I2C0_SMBAL 2490 * | | |08 = UART1_TXD 2491 * | | |09 = I2C1_SCL 2492 * | | |10 = PWM1_BRAKE1 2493 * | | |11 = EQEI0_B 2494 * | | |12 = PWM0_CH3 2495 * | | |13 = EPWM0_CH2 2496 * | | |14 = CLKO 2497 * | | |15 = EPWM1_BRAKE1 2498 * | | |16 = TK_TK5 2499 * | | |17 = UTCPD0_VBSNKEN 2500 * | | |20 = LPSPI0_SS 2501 * @var SYS_T::GPA_MFP1 2502 * Offset: 0x504 GPIOA Multiple Function Control Register 1 2503 * --------------------------------------------------------------------------------------------------- 2504 * |Bits |Field |Descriptions 2505 * | :----: | :----: | :---- | 2506 * |[4:0] |PA4MFP |PA.4 Multi-function Pin Selection 2507 * | | |03 = QSPI0_MOSI1 2508 * | | |04 = SPI0_I2SMCLK 2509 * | | |07 = UART0_nRTS 2510 * | | |08 = UART0_RXD 2511 * | | |09 = I2C0_SDA 2512 * | | |10 = CANFD0_RXD 2513 * | | |11 = UART5_RXD 2514 * | | |12 = PWM0_CH4 2515 * | | |13 = EPWM0_CH1 2516 * | | |14 = EQEI0_A 2517 * | | |16 = TK_TK4 2518 * | | |17 = UTCPD0_VBSRCEN 2519 * | | |20 = LPUART0_RXD 2520 * | | |21 = LPUART0_nRTS 2521 * | | |22 = LPI2C0_SDA 2522 * |[12:8] |PA5MFP |PA.5 Multi-function Pin Selection 2523 * | | |03 = QSPI0_MISO1 2524 * | | |04 = SPI1_I2SMCLK 2525 * | | |07 = UART0_nCTS 2526 * | | |08 = UART0_TXD 2527 * | | |09 = I2C0_SCL 2528 * | | |10 = CANFD0_TXD 2529 * | | |11 = UART5_TXD 2530 * | | |12 = PWM0_CH5 2531 * | | |13 = EPWM0_CH0 2532 * | | |14 = EQEI0_INDEX 2533 * | | |16 = TK_TK3 2534 * | | |17 = UTCPD0_VBSNKEN 2535 * | | |20 = LPUART0_TXD 2536 * | | |21 = LPUART0_nCTS 2537 * | | |22 = LPI2C0_SCL 2538 * |[20:16] |PA6MFP |PA.6 Multi-function Pin Selection 2539 * | | |02 = EBI_AD6 2540 * | | |04 = SPI1_SS 2541 * | | |07 = UART0_RXD 2542 * | | |08 = I2C1_SDA 2543 * | | |11 = EPWM1_CH5 2544 * | | |12 = PWM1_CH3 2545 * | | |13 = ACMP1_WLAT 2546 * | | |14 = TM3 2547 * | | |15 = INT0 2548 * | | |16 = TK_TK1 2549 * | | |17 = UTCPD0_VBSRCEN 2550 * | | |21 = LPUART0_RXD 2551 * | | |23 = LPIO4 2552 * |[28:24] |PA7MFP |PA.7 Multi-function Pin Selection 2553 * | | |02 = EBI_AD7 2554 * | | |04 = SPI1_CLK 2555 * | | |07 = UART0_TXD 2556 * | | |08 = I2C1_SCL 2557 * | | |11 = EPWM1_CH4 2558 * | | |12 = PWM1_CH2 2559 * | | |13 = ACMP0_WLAT 2560 * | | |14 = TM2 2561 * | | |15 = INT1 2562 * | | |16 = TK_TK0 2563 * | | |17 = UTCPD0_VBSNKEN 2564 * | | |21 = LPUART0_TXD 2565 * | | |23 = LPIO5 2566 * @var SYS_T::GPA_MFP2 2567 * Offset: 0x508 GPIOA Multiple Function Control Register 2 2568 * --------------------------------------------------------------------------------------------------- 2569 * |Bits |Field |Descriptions 2570 * | :----: | :----: | :---- | 2571 * |[4:0] |PA8MFP |PA.8 Multi-function Pin Selection 2572 * | | |01 = EADC0_CH20, OPA1_P0 2573 * | | |02 = EBI_ALE 2574 * | | |05 = SPI3_MOSI 2575 * | | |06 = USCI0_CTL1 2576 * | | |07 = UART1_RXD 2577 * | | |08 = UART7_RXD 2578 * | | |09 = PWM0_CH3 2579 * | | |10 = EQEI1_B 2580 * | | |11 = ECAP0_IC2 2581 * | | |13 = TM3_EXT 2582 * | | |14 = I2C2_SMBSUS 2583 * | | |15 = INT4 2584 * |[12:8] |PA9MFP |PA.9 Multi-function Pin Selection 2585 * | | |01 = EADC0_CH21, ACMP2_P0, OPA1_N0 2586 * | | |02 = EBI_MCLK 2587 * | | |05 = SPI3_MISO 2588 * | | |06 = USCI0_DAT1 2589 * | | |07 = UART1_TXD 2590 * | | |08 = UART7_TXD 2591 * | | |09 = PWM0_CH2 2592 * | | |10 = EQEI1_A 2593 * | | |11 = ECAP0_IC1 2594 * | | |13 = TM2_EXT 2595 * | | |14 = I2C2_SMBAL 2596 * |[20:16] |PA10MFP |PA.10 Multi-function Pin Selection 2597 * | | |01 = EADC0_CH22, ACMP1_P0, OPA1_O 2598 * | | |02 = EBI_nWR 2599 * | | |05 = SPI3_CLK 2600 * | | |06 = USCI0_DAT0 2601 * | | |07 = I2C2_SDA 2602 * | | |08 = UART6_RXD 2603 * | | |09 = PWM0_CH1 2604 * | | |10 = EQEI1_INDEX 2605 * | | |11 = ECAP0_IC0 2606 * | | |13 = TM1_EXT 2607 * | | |14 = DAC0_ST 2608 * | | |23 = LPTM1_EXT 2609 * |[28:24] |PA11MFP |PA.11 Multi-function Pin Selection 2610 * | | |01 = EADC0_CH23, ACMP0_P0, OPA2_O 2611 * | | |02 = EBI_nRD 2612 * | | |05 = SPI3_SS 2613 * | | |06 = USCI0_CLK 2614 * | | |07 = I2C2_SCL 2615 * | | |08 = UART6_TXD 2616 * | | |09 = PWM0_CH0 2617 * | | |10 = EPWM0_SYNC_OUT 2618 * | | |13 = TM0_EXT 2619 * | | |14 = DAC1_ST 2620 * | | |23 = LPTM0_EXT 2621 * @var SYS_T::GPA_MFP3 2622 * Offset: 0x50C GPIOA Multiple Function Control Register 3 2623 * --------------------------------------------------------------------------------------------------- 2624 * |Bits |Field |Descriptions 2625 * | :----: | :----: | :---- | 2626 * |[4:0] |PA12MFP |PA.12 Multi-function Pin Selection 2627 * | | |03 = UART4_TXD 2628 * | | |04 = I2C1_SCL 2629 * | | |05 = SPI2_SS 2630 * | | |06 = CANFD1_TXD 2631 * | | |08 = SPI0_SS 2632 * | | |11 = PWM1_CH2 2633 * | | |12 = EQEI1_INDEX 2634 * | | |13 = ECAP1_IC0 2635 * | | |14 = USB_VBUS 2636 * | | |20 = LPSPI0_SS 2637 * |[12:8] |PA13MFP |PA.13 Multi-function Pin Selection 2638 * | | |03 = UART4_RXD 2639 * | | |04 = I2C1_SDA 2640 * | | |05 = SPI2_CLK 2641 * | | |06 = CANFD1_RXD 2642 * | | |08 = SPI0_CLK 2643 * | | |11 = PWM1_CH3 2644 * | | |12 = EQEI1_A 2645 * | | |13 = ECAP1_IC1 2646 * | | |14 = USB_D- 2647 * | | |20 = LPSPI0_CLK 2648 * |[20:16] |PA14MFP |PA.14 Multi-function Pin Selection 2649 * | | |03 = UART0_TXD 2650 * | | |04 = EBI_AD5 2651 * | | |05 = SPI2_MISO 2652 * | | |06 = I2C2_SCL 2653 * | | |08 = SPI0_MISO 2654 * | | |11 = PWM1_CH4 2655 * | | |12 = EQEI1_B 2656 * | | |13 = ECAP1_IC2 2657 * | | |14 = USB_D+ 2658 * | | |20 = LPSPI0_MISO 2659 * |[28:24] |PA15MFP |PA.15 Multi-function Pin Selection 2660 * | | |03 = UART0_RXD 2661 * | | |05 = SPI2_MOSI 2662 * | | |06 = I2C2_SDA 2663 * | | |08 = SPI0_MOSI 2664 * | | |11 = PWM1_CH5 2665 * | | |12 = EPWM0_SYNC_IN 2666 * | | |14 = USB_OTG_ID 2667 * | | |20 = LPSPI0_MOSI 2668 * @var SYS_T::GPB_MFP0 2669 * Offset: 0x510 GPIOB Multiple Function Control Register 0 2670 * --------------------------------------------------------------------------------------------------- 2671 * |Bits |Field |Descriptions 2672 * | :----: | :----: | :---- | 2673 * |[4:0] |PB0MFP |PB.0 Multi-function Pin Selection 2674 * | | |01 = EADC0_CH0, LPADC0_CH0, ACMP2_P1, OPA0_P0 2675 * | | |02 = EBI_ADR9 2676 * | | |05 = SPI3_I2SMCLK 2677 * | | |06 = USCI0_CTL0 2678 * | | |07 = UART2_RXD 2679 * | | |08 = SPI0_I2SMCLK 2680 * | | |09 = I2C1_SDA 2681 * | | |10 = QSPI0_MOSI1 2682 * | | |11 = EPWM0_CH5 2683 * | | |12 = EPWM1_CH5 2684 * | | |13 = EPWM0_BRAKE1 2685 * | | |14 = PWM0_BRAKE1 2686 * | | |17 = UTCPD0_VCNEN2 2687 * | | |23 = LPIO2 2688 * |[12:8] |PB1MFP |PB.1 Multi-function Pin Selection 2689 * | | |01 = EADC0_CH1, LPADC0_CH1, ACMP2_N, OPA0_N0 2690 * | | |02 = EBI_ADR8 2691 * | | |07 = UART2_TXD 2692 * | | |08 = USCI1_CLK 2693 * | | |09 = I2C1_SCL 2694 * | | |10 = QSPI0_MISO1 2695 * | | |11 = EPWM0_CH4 2696 * | | |12 = EPWM1_CH4 2697 * | | |13 = EPWM0_BRAKE0 2698 * | | |14 = PWM0_BRAKE0 2699 * | | |17 = UTCPD0_VBDCHG 2700 * | | |23 = LPIO3 2701 * |[20:16] |PB2MFP |PB.2 Multi-function Pin Selection 2702 * | | |01 = EADC0_CH2, LPADC0_CH2, ACMP0_P1, OPA0_O 2703 * | | |02 = EBI_ADR3 2704 * | | |04 = I2C1_SDA 2705 * | | |05 = SPI1_SS 2706 * | | |06 = UART1_RXD 2707 * | | |07 = UART5_nCTS 2708 * | | |08 = USCI1_DAT0 2709 * | | |11 = EPWM0_CH3 2710 * | | |14 = TM3 2711 * | | |15 = INT3 2712 * | | |23 = LPIO6 2713 * |[28:24] |PB3MFP |PB.3 Multi-function Pin Selection 2714 * | | |01 = EADC0_CH3, LPADC0_CH3, ACMP0_N, OPA2_P0 2715 * | | |02 = EBI_ADR2 2716 * | | |04 = I2C1_SCL 2717 * | | |05 = SPI1_CLK 2718 * | | |06 = UART1_TXD 2719 * | | |07 = UART5_nRTS 2720 * | | |08 = USCI1_DAT1 2721 * | | |11 = EPWM0_CH2 2722 * | | |13 = PWM0_BRAKE0 2723 * | | |14 = TM2 2724 * | | |15 = INT2 2725 * | | |23 = LPIO7 2726 * @var SYS_T::GPB_MFP1 2727 * Offset: 0x514 GPIOB Multiple Function Control Register 1 2728 * --------------------------------------------------------------------------------------------------- 2729 * |Bits |Field |Descriptions 2730 * | :----: | :----: | :---- | 2731 * |[4:0] |PB4MFP |PB.4 Multi-function Pin Selection 2732 * | | |01 = EADC0_CH4, LPADC0_CH4, ACMP1_P1, OPA2_N0 2733 * | | |02 = EBI_ADR1 2734 * | | |05 = SPI1_MOSI 2735 * | | |06 = I2C0_SDA 2736 * | | |07 = UART5_RXD 2737 * | | |08 = USCI1_CTL1 2738 * | | |11 = EPWM0_CH1 2739 * | | |13 = UART2_RXD 2740 * | | |14 = TM1 2741 * | | |15 = INT1 2742 * | | |22 = LPI2C0_SDA 2743 * | | |23 = LPTM1 2744 * |[12:8] |PB5MFP |PB.5 Multi-function Pin Selection 2745 * | | |01 = EADC0_CH5, LPADC0_CH5, ACMP1_N, OPA1_P1 2746 * | | |02 = EBI_ADR0 2747 * | | |05 = SPI1_MISO 2748 * | | |06 = I2C0_SCL 2749 * | | |07 = UART5_TXD 2750 * | | |08 = USCI1_CTL0 2751 * | | |11 = EPWM0_CH0 2752 * | | |13 = UART2_TXD 2753 * | | |14 = TM0 2754 * | | |15 = INT0 2755 * | | |22 = LPI2C0_SCL 2756 * | | |23 = LPTM0 2757 * |[20:16] |PB6MFP |PB.6 Multi-function Pin Selection 2758 * | | |01 = EADC0_CH6, LPADC0_CH6, ACMP2_P2, OPA2_P1 2759 * | | |02 = EBI_nWRH 2760 * | | |04 = USCI1_DAT1 2761 * | | |06 = UART1_RXD 2762 * | | |08 = EBI_nCS1 2763 * | | |10 = PWM1_CH5 2764 * | | |11 = EPWM1_BRAKE1 2765 * | | |12 = EPWM1_CH5 2766 * | | |13 = INT4 2767 * | | |14 = PWM1_BRAKE1 2768 * | | |15 = ACMP1_O 2769 * |[28:24] |PB7MFP |PB.7 Multi-function Pin Selection 2770 * | | |01 = EADC0_CH7, LPADC0_CH7, ACMP2_P3, OPA2_N1 2771 * | | |02 = EBI_nWRL 2772 * | | |04 = USCI1_DAT0 2773 * | | |06 = UART1_TXD 2774 * | | |08 = EBI_nCS0 2775 * | | |10 = PWM1_CH4 2776 * | | |11 = EPWM1_BRAKE0 2777 * | | |12 = EPWM1_CH4 2778 * | | |13 = INT5 2779 * | | |14 = PWM1_BRAKE0 2780 * | | |15 = ACMP0_O 2781 * @var SYS_T::GPB_MFP2 2782 * Offset: 0x518 GPIOB Multiple Function Control Register 2 2783 * --------------------------------------------------------------------------------------------------- 2784 * |Bits |Field |Descriptions 2785 * | :----: | :----: | :---- | 2786 * |[4:0] |PB8MFP |PB.8 Multi-function Pin Selection 2787 * | | |01 = EADC0_CH8, LPADC0_CH8 2788 * | | |02 = EBI_ADR19 2789 * | | |04 = USCI1_CLK 2790 * | | |05 = UART0_RXD 2791 * | | |06 = UART1_nRTS 2792 * | | |08 = UART7_RXD 2793 * | | |10 = PWM1_CH3 2794 * | | |21 = LPUART0_RXD 2795 * |[12:8] |PB9MFP |PB.9 Multi-function Pin Selection 2796 * | | |01 = EADC0_CH9, LPADC0_CH9 2797 * | | |02 = EBI_ADR18 2798 * | | |04 = USCI1_CTL1 2799 * | | |05 = UART0_TXD 2800 * | | |06 = UART1_nCTS 2801 * | | |08 = UART7_TXD 2802 * | | |10 = PWM1_CH2 2803 * | | |21 = LPUART0_TXD 2804 * |[20:16] |PB10MFP |PB.10 Multi-function Pin Selection 2805 * | | |01 = EADC0_CH10, LPADC0_CH10 2806 * | | |02 = EBI_ADR17 2807 * | | |04 = USCI1_CTL0 2808 * | | |05 = UART0_nRTS 2809 * | | |06 = UART4_RXD 2810 * | | |07 = I2C1_SDA 2811 * | | |08 = CANFD1_RXD 2812 * | | |10 = PWM1_CH1 2813 * | | |21 = LPUART0_nRTS 2814 * |[28:24] |PB11MFP |PB.11 Multi-function Pin Selection 2815 * | | |01 = EADC0_CH11, LPADC0_CH11 2816 * | | |02 = EBI_ADR16 2817 * | | |05 = UART0_nCTS 2818 * | | |06 = UART4_TXD 2819 * | | |07 = I2C1_SCL 2820 * | | |08 = CANFD1_TXD 2821 * | | |09 = SPI0_I2SMCLK 2822 * | | |10 = PWM1_CH0 2823 * | | |21 = LPUART0_nCTS 2824 * @var SYS_T::GPB_MFP3 2825 * Offset: 0x51C GPIOB Multiple Function Control Register 3 2826 * --------------------------------------------------------------------------------------------------- 2827 * |Bits |Field |Descriptions 2828 * | :----: | :----: | :---- | 2829 * |[4:0] |PB12MFP |PB.12 Multi-function Pin Selection 2830 * | | |01 = EADC0_CH12, LPADC0_CH12, DAC0_OUT, ACMP0_P2, ACMP1_P2 2831 * | | |02 = EBI_AD15 2832 * | | |04 = SPI0_MOSI 2833 * | | |05 = USCI0_CLK 2834 * | | |06 = UART0_RXD 2835 * | | |07 = UART3_nCTS 2836 * | | |08 = I2C2_SDA 2837 * | | |10 = CANFD0_RXD 2838 * | | |11 = EPWM1_CH3 2839 * | | |13 = TM3_EXT 2840 * | | |20 = LPSPI0_MOSI 2841 * | | |21 = LPUART0_RXD 2842 * |[12:8] |PB13MFP |PB.13 Multi-function Pin Selection 2843 * | | |01 = EADC0_CH13, LPADC0_CH13, DAC1_OUT, ACMP0_P3, ACMP1_P3, OPA1_N1 2844 * | | |02 = EBI_AD14 2845 * | | |04 = SPI0_MISO 2846 * | | |05 = USCI0_DAT0 2847 * | | |06 = UART0_TXD 2848 * | | |07 = UART3_nRTS 2849 * | | |08 = I2C2_SCL 2850 * | | |10 = CANFD0_TXD 2851 * | | |11 = EPWM1_CH2 2852 * | | |13 = TM2_EXT 2853 * | | |20 = LPSPI0_MISO 2854 * | | |21 = LPUART0_TXD 2855 * |[20:16] |PB14MFP |PB.14 Multi-function Pin Selection 2856 * | | |01 = EADC0_CH14, LPADC0_CH14, OPA0_N1 2857 * | | |02 = EBI_AD13 2858 * | | |04 = SPI0_CLK 2859 * | | |05 = USCI0_DAT1 2860 * | | |06 = UART0_nRTS 2861 * | | |07 = UART3_RXD 2862 * | | |08 = I2C2_SMBSUS 2863 * | | |10 = EQEI0_INDEX 2864 * | | |11 = EPWM1_CH1 2865 * | | |12 = ECAP0_IC0 2866 * | | |13 = TM1_EXT 2867 * | | |14 = CLKO 2868 * | | |16 = TK_SE 2869 * | | |17 = UTCPD0_VBSRCEN 2870 * | | |20 = LPSPI0_CLK 2871 * | | |21 = LPUART0_nRTS 2872 * | | |23 = LPTM1_EXT 2873 * |[28:24] |PB15MFP |PB.15 Multi-function Pin Selection 2874 * | | |01 = EADC0_CH15, LPADC0_CH15, OPA0_P1 2875 * | | |02 = EBI_AD12 2876 * | | |04 = SPI0_SS 2877 * | | |05 = USCI0_CTL1 2878 * | | |06 = UART0_nCTS 2879 * | | |07 = UART3_TXD 2880 * | | |08 = I2C2_SMBAL 2881 * | | |10 = EPWM0_BRAKE1 2882 * | | |11 = EPWM1_CH0 2883 * | | |13 = TM0_EXT 2884 * | | |14 = USB_VBUS_EN 2885 * | | |17 = UTCPD0_VBSNKEN 2886 * | | |20 = LPSPI0_SS 2887 * | | |21 = LPUART0_nCTS 2888 * | | |23 = LPTM0_EXT 2889 * @var SYS_T::GPC_MFP0 2890 * Offset: 0x520 GPIOC Multiple Function Control Register 0 2891 * --------------------------------------------------------------------------------------------------- 2892 * |Bits |Field |Descriptions 2893 * | :----: | :----: | :---- | 2894 * |[4:0] |PC0MFP |PC.0 Multi-function Pin Selection 2895 * | | |02 = EBI_AD0 2896 * | | |04 = QSPI0_MOSI0 2897 * | | |07 = SPI1_SS 2898 * | | |08 = UART2_RXD 2899 * | | |09 = I2C0_SDA 2900 * | | |10 = EQEI0_B 2901 * | | |12 = EPWM1_CH5 2902 * | | |13 = ECAP0_IC2 2903 * | | |14 = ACMP1_O 2904 * | | |17 = UTCPD0_CC1 2905 * | | |22 = LPI2C0_SDA 2906 * | | |23 = LPIO4 2907 * |[12:8] |PC1MFP |PC.1 Multi-function Pin Selection 2908 * | | |02 = EBI_AD1 2909 * | | |04 = QSPI0_MISO0 2910 * | | |07 = SPI1_CLK 2911 * | | |08 = UART2_TXD 2912 * | | |09 = I2C0_SCL 2913 * | | |10 = EQEI0_A 2914 * | | |12 = EPWM1_CH4 2915 * | | |13 = ECAP0_IC1 2916 * | | |14 = ACMP0_O 2917 * | | |15 = EADC0_ST 2918 * | | |17 = UTCPD0_CC2 2919 * | | |22 = LPI2C0_SCL 2920 * | | |23 = LPIO5 2921 * |[20:16] |PC2MFP |PC.2 Multi-function Pin Selection 2922 * | | |02 = EBI_AD2 2923 * | | |04 = QSPI0_CLK 2924 * | | |06 = SPI3_MOSI 2925 * | | |07 = SPI1_MOSI 2926 * | | |08 = UART2_nCTS 2927 * | | |09 = I2C0_SMBSUS 2928 * | | |10 = EQEI0_INDEX 2929 * | | |11 = UART3_RXD 2930 * | | |12 = EPWM1_CH3 2931 * | | |13 = ECAP0_IC0 2932 * | | |15 = I2C3_SDA 2933 * | | |16 = TK_TK13 2934 * | | |17 = UTCPD0_CCDB1 2935 * |[28:24] |PC3MFP |PC.3 Multi-function Pin Selection 2936 * | | |02 = EBI_AD3 2937 * | | |04 = QSPI0_SS 2938 * | | |06 = SPI3_MISO 2939 * | | |07 = SPI1_MISO 2940 * | | |08 = UART2_nRTS 2941 * | | |09 = I2C0_SMBAL 2942 * | | |11 = UART3_TXD 2943 * | | |12 = EPWM1_CH2 2944 * | | |15 = I2C3_SCL 2945 * | | |16 = TK_TK12 2946 * | | |17 = UTCPD0_CCDB2 2947 * @var SYS_T::GPC_MFP1 2948 * Offset: 0x524 GPIOC Multiple Function Control Register 1 2949 * --------------------------------------------------------------------------------------------------- 2950 * |Bits |Field |Descriptions 2951 * | :----: | :----: | :---- | 2952 * |[4:0] |PC4MFP |PC.4 Multi-function Pin Selection 2953 * | | |02 = EBI_AD4 2954 * | | |04 = QSPI0_MOSI1 2955 * | | |06 = SPI3_CLK 2956 * | | |07 = SPI1_I2SMCLK 2957 * | | |08 = UART2_RXD 2958 * | | |09 = I2C1_SDA 2959 * | | |10 = CANFD0_RXD 2960 * | | |11 = UART4_RXD 2961 * | | |12 = EPWM1_CH1 2962 * | | |15 = I2C3_SMBSUS 2963 * | | |16 = TK_TK11 2964 * | | |17 = UTCPD0_FRSTX1 2965 * | | |18 = UTCPD0_DISCHG 2966 * |[12:8] |PC5MFP |PC.5 Multi-function Pin Selection 2967 * | | |02 = EBI_AD5 2968 * | | |04 = QSPI0_MISO1 2969 * | | |06 = SPI3_SS 2970 * | | |08 = UART2_TXD 2971 * | | |09 = I2C1_SCL 2972 * | | |10 = CANFD0_TXD 2973 * | | |11 = UART4_TXD 2974 * | | |12 = EPWM1_CH0 2975 * | | |15 = I2C3_SMBAL 2976 * | | |16 = TK_TK10 2977 * | | |17 = UTCPD0_FRSTX2 2978 * | | |18 = UTCPD0_DISCHG 2979 * |[20:16] |PC6MFP |PC.6 Multi-function Pin Selection 2980 * | | |02 = EBI_AD8 2981 * | | |04 = SPI1_MOSI 2982 * | | |05 = UART4_RXD 2983 * | | |07 = UART0_nRTS 2984 * | | |09 = UART6_RXD 2985 * | | |11 = EPWM1_CH3 2986 * | | |12 = PWM1_CH1 2987 * | | |14 = TM1 2988 * | | |15 = INT2 2989 * | | |21 = LPUART0_nRTS 2990 * | | |23 = LPTM1 2991 * |[28:24] |PC7MFP |PC.7 Multi-function Pin Selection 2992 * | | |02 = EBI_AD9 2993 * | | |04 = SPI1_MISO 2994 * | | |05 = UART4_TXD 2995 * | | |07 = UART0_nCTS 2996 * | | |09 = UART6_TXD 2997 * | | |11 = EPWM1_CH2 2998 * | | |12 = PWM1_CH0 2999 * | | |14 = TM0 3000 * | | |15 = INT3 3001 * | | |21 = LPUART0_nCTS 3002 * | | |23 = LPTM0 3003 * @var SYS_T::GPC_MFP2 3004 * Offset: 0x528 GPIOC Multiple Function Control Register 2 3005 * --------------------------------------------------------------------------------------------------- 3006 * |Bits |Field |Descriptions 3007 * | :----: | :----: | :---- | 3008 * |[4:0] |PC8MFP |PC.8 Multi-function Pin Selection 3009 * | | |02 = EBI_ADR16 3010 * | | |04 = I2C0_SDA 3011 * | | |05 = UART4_nCTS 3012 * | | |08 = UART1_RXD 3013 * | | |11 = EPWM1_CH1 3014 * | | |12 = PWM1_CH4 3015 * | | |22 = LPI2C0_SDA 3016 * |[12:8] |PC9MFP |PC.9 Multi-function Pin Selection 3017 * | | |02 = EBI_ADR7 3018 * | | |05 = UART6_nCTS 3019 * | | |06 = SPI3_SS 3020 * | | |07 = UART3_RXD 3021 * | | |09 = CANFD1_RXD 3022 * | | |12 = EPWM1_CH3 3023 * |[20:16] |PC10MFP |PC.10 Multi-function Pin Selection 3024 * | | |02 = EBI_ADR6 3025 * | | |05 = UART6_nRTS 3026 * | | |06 = SPI3_CLK 3027 * | | |07 = UART3_TXD 3028 * | | |09 = CANFD1_TXD 3029 * | | |11 = ECAP1_IC0 3030 * | | |12 = EPWM1_CH2 3031 * |[28:24] |PC11MFP |PC.11 Multi-function Pin Selection 3032 * | | |02 = EBI_ADR5 3033 * | | |03 = UART0_RXD 3034 * | | |04 = I2C0_SDA 3035 * | | |05 = UART6_RXD 3036 * | | |06 = SPI3_MOSI 3037 * | | |11 = ECAP1_IC1 3038 * | | |12 = EPWM1_CH1 3039 * | | |14 = ACMP1_O 3040 * | | |21 = LPUART0_RXD 3041 * | | |22 = LPI2C0_SDA 3042 * @var SYS_T::GPC_MFP3 3043 * Offset: 0x52C GPIOC Multiple Function Control Register 3 3044 * --------------------------------------------------------------------------------------------------- 3045 * |Bits |Field |Descriptions 3046 * | :----: | :----: | :---- | 3047 * |[4:0] |PC12MFP |PC.12 Multi-function Pin Selection 3048 * | | |02 = EBI_ADR4 3049 * | | |03 = UART0_TXD 3050 * | | |04 = I2C0_SCL 3051 * | | |05 = UART6_TXD 3052 * | | |06 = SPI3_MISO 3053 * | | |11 = ECAP1_IC2 3054 * | | |12 = EPWM1_CH0 3055 * | | |14 = ACMP0_O 3056 * | | |21 = LPUART0_TXD 3057 * | | |22 = LPI2C0_SCL 3058 * |[12:8] |PC13MFP |PC.13 Multi-function Pin Selection 3059 * | | |01 = EADC0_CH19 3060 * | | |02 = EBI_ADR10 3061 * | | |04 = SPI2_I2SMCLK 3062 * | | |05 = CANFD1_TXD 3063 * | | |06 = USCI0_CTL0 3064 * | | |07 = UART2_TXD 3065 * | | |09 = PWM0_CH4 3066 * | | |13 = CLKO 3067 * | | |14 = EADC0_ST 3068 * | | |16 = TK_SE 3069 * | | |23 = LPADC0_ST 3070 * |[20:16] |PC14MFP |PC.14 Multi-function Pin Selection 3071 * | | |02 = EBI_AD11 3072 * | | |04 = SPI0_I2SMCLK 3073 * | | |05 = USCI0_CTL0 3074 * | | |06 = QSPI0_CLK 3075 * | | |08 = EBI_nCS2 3076 * | | |11 = EPWM0_SYNC_IN 3077 * | | |13 = TM1 3078 * | | |14 = USB_VBUS_ST 3079 * | | |15 = ACMP2_O 3080 * | | |23 = LPTM1 3081 * @var SYS_T::GPD_MFP0 3082 * Offset: 0x530 GPIOD Multiple Function Control Register 0 3083 * --------------------------------------------------------------------------------------------------- 3084 * |Bits |Field |Descriptions 3085 * | :----: | :----: | :---- | 3086 * |[4:0] |PD0MFP |PD.0 Multi-function Pin Selection 3087 * | | |02 = EBI_AD13 3088 * | | |03 = USCI0_CLK 3089 * | | |04 = SPI0_MOSI 3090 * | | |05 = UART3_RXD 3091 * | | |14 = TM2 3092 * | | |16 = TK_TK17 3093 * | | |20 = LPSPI0_MOSI 3094 * | | |23 = LPIO6 3095 * |[12:8] |PD1MFP |PD.1 Multi-function Pin Selection 3096 * | | |02 = EBI_AD12 3097 * | | |03 = USCI0_DAT0 3098 * | | |04 = SPI0_MISO 3099 * | | |05 = UART3_TXD 3100 * | | |16 = TK_TK16 3101 * | | |20 = LPSPI0_MISO 3102 * | | |23 = LPIO7 3103 * |[20:16] |PD2MFP |PD.2 Multi-function Pin Selection 3104 * | | |02 = EBI_AD11 3105 * | | |03 = USCI0_DAT1 3106 * | | |04 = SPI0_CLK 3107 * | | |05 = UART3_nCTS 3108 * | | |09 = UART0_RXD 3109 * | | |16 = TK_TK15 3110 * | | |20 = LPSPI0_CLK 3111 * | | |21 = LPUART0_RXD 3112 * |[28:24] |PD3MFP |PD.3 Multi-function Pin Selection 3113 * | | |02 = EBI_AD10 3114 * | | |03 = USCI0_CTL1 3115 * | | |04 = SPI0_SS 3116 * | | |05 = UART3_nRTS 3117 * | | |06 = USCI1_CTL0 3118 * | | |09 = UART0_TXD 3119 * | | |16 = TK_TK14 3120 * | | |20 = LPSPI0_SS 3121 * | | |21 = LPUART0_TXD 3122 * @var SYS_T::GPD_MFP1 3123 * Offset: 0x534 GPIOD Multiple Function Control Register 1 3124 * --------------------------------------------------------------------------------------------------- 3125 * |Bits |Field |Descriptions 3126 * | :----: | :----: | :---- | 3127 * |[4:0] |PD4MFP |PD.4 Multi-function Pin Selection 3128 * | | |03 = USCI0_CTL0 3129 * | | |04 = I2C1_SDA 3130 * | | |06 = USCI1_CTL1 3131 * | | |16 = TK_TK17 3132 * |[12:8] |PD5MFP |PD.5 Multi-function Pin Selection 3133 * | | |04 = I2C1_SCL 3134 * | | |06 = USCI1_DAT0 3135 * | | |16 = TK_TK16 3136 * |[20:16] |PD6MFP |PD.6 Multi-function Pin Selection 3137 * | | |03 = UART1_RXD 3138 * | | |04 = I2C0_SDA 3139 * | | |06 = USCI1_DAT1 3140 * | | |16 = TK_TK15 3141 * | | |22 = LPI2C0_SDA 3142 * |[28:24] |PD7MFP |PD.7 Multi-function Pin Selection 3143 * | | |03 = UART1_TXD 3144 * | | |04 = I2C0_SCL 3145 * | | |06 = USCI1_CLK 3146 * | | |16 = TK_TK14 3147 * | | |22 = LPI2C0_SCL 3148 * @var SYS_T::GPD_MFP2 3149 * Offset: 0x538 GPIOD Multiple Function Control Register 2 3150 * --------------------------------------------------------------------------------------------------- 3151 * |Bits |Field |Descriptions 3152 * | :----: | :----: | :---- | 3153 * |[4:0] |PD8MFP |PD.8 Multi-function Pin Selection 3154 * | | |02 = EBI_AD6 3155 * | | |03 = I2C2_SDA 3156 * | | |04 = UART2_nRTS 3157 * | | |05 = UART7_RXD 3158 * |[12:8] |PD9MFP |PD.9 Multi-function Pin Selection 3159 * | | |02 = EBI_AD7 3160 * | | |03 = I2C2_SCL 3161 * | | |04 = UART2_nCTS 3162 * | | |05 = UART7_TXD 3163 * |[20:16] |PD10MFP |PD.10 Multi-function Pin Selection 3164 * | | |01 = EADC0_CH16 3165 * | | |02 = EBI_nCS2 3166 * | | |03 = UART1_RXD 3167 * | | |04 = CANFD0_RXD 3168 * | | |10 = EQEI0_B 3169 * | | |15 = INT7 3170 * |[28:24] |PD11MFP |PD.11 Multi-function Pin Selection 3171 * | | |01 = EADC0_CH17 3172 * | | |02 = EBI_nCS1 3173 * | | |03 = UART1_TXD 3174 * | | |04 = CANFD0_TXD 3175 * | | |10 = EQEI0_A 3176 * | | |15 = INT6 3177 * @var SYS_T::GPD_MFP3 3178 * Offset: 0x53C GPIOD Multiple Function Control Register 3 3179 * --------------------------------------------------------------------------------------------------- 3180 * |Bits |Field |Descriptions 3181 * | :----: | :----: | :---- | 3182 * |[4:0] |PD12MFP |PD.12 Multi-function Pin Selection 3183 * | | |01 = EADC0_CH18 3184 * | | |02 = EBI_nCS0 3185 * | | |05 = CANFD1_RXD 3186 * | | |07 = UART2_RXD 3187 * | | |09 = PWM0_CH5 3188 * | | |10 = EQEI0_INDEX 3189 * | | |13 = CLKO 3190 * | | |14 = EADC0_ST 3191 * | | |15 = INT5 3192 * | | |16 = TK_SE 3193 * | | |23 = LPADC0_ST 3194 * |[12:8] |PD13MFP |PD.13 Multi-function Pin Selection 3195 * | | |02 = EBI_AD10 3196 * | | |04 = SPI0_I2SMCLK 3197 * | | |05 = SPI1_I2SMCLK 3198 * | | |11 = PWM0_CH0 3199 * | | |14 = CLKO 3200 * | | |15 = EADC0_ST 3201 * | | |16 = TK_SE 3202 * | | |23 = LPADC0_ST 3203 * |[20:16] |PD14MFP |PD.14 Multi-function Pin Selection 3204 * | | |02 = EBI_nCS0 3205 * | | |03 = SPI3_I2SMCLK 3206 * | | |05 = SPI0_I2SMCLK 3207 * | | |11 = EPWM0_CH4 3208 * |[28:24] |PD15MFP |PD.15 Multi-function Pin Selection 3209 * | | |12 = EPWM0_CH5 3210 * | | |13 = ACMP2_WLAT 3211 * | | |14 = TM3 3212 * | | |15 = INT1 3213 * | | |16 = TK_TK2 3214 * | | |17 = UTCPD0_FRSTX2 3215 * | | |18 = UTCPD0_DISCHG 3216 * @var SYS_T::GPE_MFP0 3217 * Offset: 0x540 GPIOE Multiple Function Control Register 0 3218 * --------------------------------------------------------------------------------------------------- 3219 * |Bits |Field |Descriptions 3220 * | :----: | :----: | :---- | 3221 * |[4:0] |PE0MFP |PE.0 Multi-function Pin Selection 3222 * | | |02 = EBI_AD11 3223 * | | |03 = QSPI0_MOSI0 3224 * | | |06 = SPI1_MOSI 3225 * | | |07 = UART3_RXD 3226 * | | |08 = I2C1_SDA 3227 * | | |09 = UART4_nRTS 3228 * | | |23 = LPIO0 3229 * |[12:8] |PE1MFP |PE.1 Multi-function Pin Selection 3230 * | | |02 = EBI_AD10 3231 * | | |03 = QSPI0_MISO0 3232 * | | |06 = SPI1_MISO 3233 * | | |07 = UART3_TXD 3234 * | | |08 = I2C1_SCL 3235 * | | |09 = UART4_nCTS 3236 * | | |23 = LPIO1 3237 * |[20:16] |PE2MFP |PE.2 Multi-function Pin Selection 3238 * | | |02 = EBI_ALE 3239 * | | |05 = SPI3_MOSI 3240 * | | |07 = USCI0_CLK 3241 * | | |08 = UART6_nCTS 3242 * | | |09 = UART7_RXD 3243 * | | |11 = EQEI0_B 3244 * | | |12 = EPWM0_CH5 3245 * | | |13 = PWM0_CH0 3246 * |[28:24] |PE3MFP |PE.3 Multi-function Pin Selection 3247 * | | |02 = EBI_MCLK 3248 * | | |05 = SPI3_MISO 3249 * | | |07 = USCI0_DAT0 3250 * | | |08 = UART6_nRTS 3251 * | | |09 = UART7_TXD 3252 * | | |11 = EQEI0_A 3253 * | | |12 = EPWM0_CH4 3254 * | | |13 = PWM0_CH1 3255 * @var SYS_T::GPE_MFP1 3256 * Offset: 0x544 GPIOE Multiple Function Control Register 1 3257 * --------------------------------------------------------------------------------------------------- 3258 * |Bits |Field |Descriptions 3259 * | :----: | :----: | :---- | 3260 * |[4:0] |PE4MFP |PE.4 Multi-function Pin Selection 3261 * | | |02 = EBI_nWR 3262 * | | |05 = SPI3_CLK 3263 * | | |07 = USCI0_DAT1 3264 * | | |08 = UART6_RXD 3265 * | | |09 = UART7_nCTS 3266 * | | |11 = EQEI0_INDEX 3267 * | | |12 = EPWM0_CH3 3268 * | | |13 = PWM0_CH2 3269 * |[12:8] |PE5MFP |PE.5 Multi-function Pin Selection 3270 * | | |02 = EBI_nRD 3271 * | | |05 = SPI3_SS 3272 * | | |07 = USCI0_CTL1 3273 * | | |08 = UART6_TXD 3274 * | | |09 = UART7_nRTS 3275 * | | |11 = EQEI1_B 3276 * | | |12 = EPWM0_CH2 3277 * | | |13 = PWM0_CH3 3278 * |[20:16] |PE6MFP |PE.6 Multi-function Pin Selection 3279 * | | |05 = SPI3_I2SMCLK 3280 * | | |07 = USCI0_CTL0 3281 * | | |08 = UART5_RXD 3282 * | | |09 = CANFD1_RXD 3283 * | | |11 = EQEI1_A 3284 * | | |12 = EPWM0_CH1 3285 * | | |13 = PWM0_CH4 3286 * |[28:24] |PE7MFP |PE.7 Multi-function Pin Selection 3287 * | | |08 = UART5_TXD 3288 * | | |09 = CANFD1_TXD 3289 * | | |11 = EQEI1_INDEX 3290 * | | |12 = EPWM0_CH0 3291 * | | |13 = PWM0_CH5 3292 * @var SYS_T::GPE_MFP2 3293 * Offset: 0x548 GPIOE Multiple Function Control Register 2 3294 * --------------------------------------------------------------------------------------------------- 3295 * |Bits |Field |Descriptions 3296 * | :----: | :----: | :---- | 3297 * |[4:0] |PE8MFP |PE.8 Multi-function Pin Selection 3298 * | | |02 = EBI_ADR10 3299 * | | |05 = SPI2_CLK 3300 * | | |06 = USCI1_CTL1 3301 * | | |07 = UART2_TXD 3302 * | | |09 = PWM0_BRAKE0 3303 * | | |10 = EPWM0_CH0 3304 * | | |11 = EPWM0_BRAKE0 3305 * | | |12 = ECAP0_IC0 3306 * |[12:8] |PE9MFP |PE.9 Multi-function Pin Selection 3307 * | | |02 = EBI_ADR11 3308 * | | |05 = SPI2_MISO 3309 * | | |06 = USCI1_CTL0 3310 * | | |07 = UART2_RXD 3311 * | | |09 = PWM0_BRAKE1 3312 * | | |10 = EPWM0_CH1 3313 * | | |11 = EPWM0_BRAKE1 3314 * | | |12 = ECAP0_IC1 3315 * |[20:16] |PE10MFP |PE.10 Multi-function Pin Selection 3316 * | | |02 = EBI_ADR12 3317 * | | |05 = SPI2_MOSI 3318 * | | |06 = USCI1_DAT0 3319 * | | |07 = UART3_TXD 3320 * | | |09 = PWM1_BRAKE0 3321 * | | |10 = EPWM0_CH2 3322 * | | |11 = EPWM1_BRAKE0 3323 * | | |12 = ECAP0_IC2 3324 * |[28:24] |PE11MFP |PE.11 Multi-function Pin Selection 3325 * | | |02 = EBI_ADR13 3326 * | | |05 = SPI2_SS 3327 * | | |06 = USCI1_DAT1 3328 * | | |07 = UART3_RXD 3329 * | | |08 = UART1_nCTS 3330 * | | |09 = PWM1_BRAKE1 3331 * | | |10 = EPWM0_CH3 3332 * | | |11 = EPWM1_BRAKE1 3333 * | | |13 = ECAP1_IC2 3334 * @var SYS_T::GPE_MFP3 3335 * Offset: 0x54C GPIOE Multiple Function Control Register 3 3336 * --------------------------------------------------------------------------------------------------- 3337 * |Bits |Field |Descriptions 3338 * | :----: | :----: | :---- | 3339 * |[4:0] |PE12MFP |PE.12 Multi-function Pin Selection 3340 * | | |02 = EBI_ADR14 3341 * | | |05 = SPI2_I2SMCLK 3342 * | | |06 = USCI1_CLK 3343 * | | |08 = UART1_nRTS 3344 * | | |10 = EPWM0_CH4 3345 * | | |13 = ECAP1_IC1 3346 * |[12:8] |PE13MFP |PE.13 Multi-function Pin Selection 3347 * | | |02 = EBI_ADR15 3348 * | | |04 = I2C0_SCL 3349 * | | |05 = UART4_nRTS 3350 * | | |08 = UART1_TXD 3351 * | | |10 = EPWM0_CH5 3352 * | | |11 = EPWM1_CH0 3353 * | | |12 = PWM1_CH5 3354 * | | |13 = ECAP1_IC0 3355 * | | |22 = LPI2C0_SCL 3356 * |[20:16] |PE14MFP |PE.14 Multi-function Pin Selection 3357 * | | |02 = EBI_AD8 3358 * | | |03 = UART2_TXD 3359 * | | |04 = CANFD0_TXD 3360 * | | |06 = UART6_TXD 3361 * | | |12 = EPWM0_CH1 3362 * | | |13 = TM2 3363 * | | |14 = CLKO 3364 * | | |15 = INT4 3365 * | | |16 = TK_TK9 3366 * |[28:24] |PE15MFP |PE.15 Multi-function Pin Selection 3367 * | | |02 = EBI_AD9 3368 * | | |03 = UART2_RXD 3369 * | | |04 = CANFD0_RXD 3370 * | | |06 = UART6_RXD 3371 * @var SYS_T::GPF_MFP0 3372 * Offset: 0x550 GPIOF Multiple Function Control Register 0 3373 * --------------------------------------------------------------------------------------------------- 3374 * |Bits |Field |Descriptions 3375 * | :----: | :----: | :---- | 3376 * |[4:0] |PF0MFP |PF.0 Multi-function Pin Selection 3377 * | | |02 = UART1_TXD 3378 * | | |03 = I2C1_SCL 3379 * | | |04 = UART0_TXD 3380 * | | |11 = EPWM1_CH4 3381 * | | |12 = PWM1_CH0 3382 * | | |14 = ICE_DAT 3383 * | | |17 = UTCPD0_FRSTX2 3384 * | | |18 = UTCPD0_DISCHG 3385 * | | |21 = LPUART0_TXD 3386 * | | |23 = LPIO2 3387 * |[12:8] |PF1MFP |PF.1 Multi-function Pin Selection 3388 * | | |02 = UART1_RXD 3389 * | | |03 = I2C1_SDA 3390 * | | |04 = UART0_RXD 3391 * | | |06 = SPI3_I2SMCLK 3392 * | | |11 = EPWM1_CH5 3393 * | | |12 = PWM1_CH1 3394 * | | |14 = ICE_CLK 3395 * | | |17 = UTCPD0_FRSTX1 3396 * | | |18 = UTCPD0_DISCHG 3397 * | | |21 = LPUART0_RXD 3398 * | | |23 = LPIO3 3399 * |[20:16] |PF2MFP |PF.2 Multi-function Pin Selection 3400 * | | |02 = EBI_nCS1 3401 * | | |03 = UART0_RXD 3402 * | | |04 = I2C0_SDA 3403 * | | |05 = QSPI0_CLK 3404 * | | |10 = XT1_OUT 3405 * | | |11 = PWM1_CH1 3406 * | | |12 = EQEI1_B 3407 * | | |13 = ECAP1_IC2 3408 * | | |21 = LPUART0_RXD 3409 * | | |22 = LPI2C0_SDA 3410 * |[28:24] |PF3MFP |PF.3 Multi-function Pin Selection 3411 * | | |02 = EBI_nCS0 3412 * | | |03 = UART0_TXD 3413 * | | |04 = I2C0_SCL 3414 * | | |10 = XT1_IN 3415 * | | |11 = PWM1_CH0 3416 * | | |12 = EQEI1_A 3417 * | | |13 = ECAP1_IC1 3418 * | | |21 = LPUART0_TXD 3419 * | | |22 = LPI2C0_SCL 3420 * @var SYS_T::GPF_MFP1 3421 * Offset: 0x554 GPIOF Multiple Function Control Register 1 3422 * --------------------------------------------------------------------------------------------------- 3423 * |Bits |Field |Descriptions 3424 * | :----: | :----: | :---- | 3425 * |[4:0] |PF4MFP |PF.4 Multi-function Pin Selection 3426 * | | |02 = UART2_TXD 3427 * | | |04 = UART2_nRTS 3428 * | | |07 = EPWM0_CH1 3429 * | | |08 = PWM0_CH5 3430 * | | |10 = X32_OUT 3431 * | | |12 = EQEI1_INDEX 3432 * | | |13 = ECAP1_IC0 3433 * | | |17 = UTCPD0_VBSRCEN 3434 * |[12:8] |PF5MFP |PF.5 Multi-function Pin Selection 3435 * | | |02 = UART2_RXD 3436 * | | |04 = UART2_nCTS 3437 * | | |07 = EPWM0_CH0 3438 * | | |08 = PWM0_CH4 3439 * | | |09 = EPWM0_SYNC_OUT 3440 * | | |10 = X32_IN 3441 * | | |11 = EADC0_ST 3442 * | | |17 = UTCPD0_VBSNKEN 3443 * |[20:16] |PF6MFP |PF.6 Multi-function Pin Selection 3444 * | | |02 = EBI_ADR19 3445 * | | |05 = SPI0_MOSI 3446 * | | |06 = UART4_RXD 3447 * | | |07 = EBI_nCS0 3448 * | | |09 = EPWM1_BRAKE0 3449 * | | |10 = TAMPER0 3450 * | | |11 = EPWM0_BRAKE0 3451 * | | |12 = EPWM0_CH4 3452 * | | |13 = PWM1_BRAKE0 3453 * | | |14 = PWM0_BRAKE0 3454 * | | |15 = CLKO 3455 * | | |20 = LPSPI0_MOSI 3456 * |[28:24] |PF7MFP |PF.7 Multi-function Pin Selection 3457 * | | |02 = EBI_ADR18 3458 * | | |05 = SPI0_MISO 3459 * | | |06 = UART4_TXD 3460 * | | |10 = TAMPER1 3461 * | | |14 = TM3 3462 * | | |15 = INT5 3463 * | | |20 = LPSPI0_MISO 3464 * @var SYS_T::GPF_MFP2 3465 * Offset: 0x558 GPIOF Multiple Function Control Register 2 3466 * --------------------------------------------------------------------------------------------------- 3467 * |Bits |Field |Descriptions 3468 * | :----: | :----: | :---- | 3469 * |[4:0] |PF8MFP |PF.8 Multi-function Pin Selection 3470 * | | |02 = EBI_ADR17 3471 * | | |05 = SPI0_CLK 3472 * | | |06 = UART5_nCTS 3473 * | | |08 = CANFD1_RXD 3474 * | | |10 = TAMPER2 3475 * | | |20 = LPSPI0_CLK 3476 * |[12:8] |PF9MFP |PF.9 Multi-function Pin Selection 3477 * | | |02 = EBI_ADR16 3478 * | | |05 = SPI0_SS 3479 * | | |06 = UART5_nRTS 3480 * | | |08 = CANFD1_TXD 3481 * | | |20 = LPSPI0_SS 3482 * |[20:16] |PF10MFP |PF.10 Multi-function Pin Selection 3483 * | | |02 = EBI_ADR15 3484 * | | |05 = SPI0_I2SMCLK 3485 * | | |06 = UART5_RXD 3486 * |[28:24] |PF11MFP |PF.11 Multi-function Pin Selection 3487 * | | |02 = EBI_ADR14 3488 * | | |03 = SPI2_MOSI 3489 * | | |06 = UART5_TXD 3490 * | | |13 = TM3 3491 * @var SYS_T::GPG_MFP0 3492 * Offset: 0x560 GPIOG Multiple Function Control Register 0 3493 * --------------------------------------------------------------------------------------------------- 3494 * |Bits |Field |Descriptions 3495 * | :----: | :----: | :---- | 3496 * |[20:16] |PG2MFP |PG.2 Multi-function Pin Selection 3497 * | | |02 = EBI_ADR11 3498 * | | |03 = SPI2_SS 3499 * | | |04 = I2C0_SMBAL 3500 * | | |05 = I2C1_SCL 3501 * | | |09 = I2C3_SMBAL 3502 * | | |13 = TM0 3503 * | | |23 = LPTM0 3504 * |[28:24] |PG3MFP |PG.3 Multi-function Pin Selection 3505 * | | |02 = EBI_ADR12 3506 * | | |03 = SPI2_CLK 3507 * | | |04 = I2C0_SMBSUS 3508 * | | |05 = I2C1_SDA 3509 * | | |09 = I2C3_SMBSUS 3510 * | | |13 = TM1 3511 * | | |23 = LPTM1 3512 * @var SYS_T::GPG_MFP1 3513 * Offset: 0x564 GPIOG Multiple Function Control Register 1 3514 * --------------------------------------------------------------------------------------------------- 3515 * |Bits |Field |Descriptions 3516 * | :----: | :----: | :---- | 3517 * |[4:0] |PG4MFP |PG.4 Multi-function Pin Selection 3518 * | | |02 = EBI_ADR13 3519 * | | |03 = SPI2_MISO 3520 * | | |13 = TM2 3521 * @var SYS_T::GPG_MFP2 3522 * Offset: 0x568 GPIOG Multiple Function Control Register 2 3523 * --------------------------------------------------------------------------------------------------- 3524 * |Bits |Field |Descriptions 3525 * | :----: | :----: | :---- | 3526 * |[12:8] |PG9MFP |PG.9 Multi-function Pin Selection 3527 * | | |02 = EBI_AD0 3528 * | | |12 = PWM0_CH5 3529 * |[20:16] |PG10MFP |PG.10 Multi-function Pin Selection 3530 * | | |02 = EBI_AD1 3531 * | | |12 = PWM0_CH4 3532 * |[28:24] |PG11MFP |PG.11 Multi-function Pin Selection 3533 * | | |02 = EBI_AD2 3534 * | | |06 = UART7_TXD 3535 * | | |12 = PWM0_CH3 3536 * @var SYS_T::GPG_MFP3 3537 * Offset: 0x56C GPIOG Multiple Function Control Register 3 3538 * --------------------------------------------------------------------------------------------------- 3539 * |Bits |Field |Descriptions 3540 * | :----: | :----: | :---- | 3541 * |[4:0] |PG12MFP |PG.12 Multi-function Pin Selection 3542 * | | |02 = EBI_AD3 3543 * | | |06 = UART7_RXD 3544 * | | |12 = PWM0_CH2 3545 * |[12:8] |PG13MFP |PG.13 Multi-function Pin Selection 3546 * | | |02 = EBI_AD4 3547 * | | |06 = UART6_TXD 3548 * | | |12 = PWM0_CH1 3549 * |[20:16] |PG14MFP |PG.14 Multi-function Pin Selection 3550 * | | |02 = EBI_AD5 3551 * | | |06 = UART6_RXD 3552 * | | |12 = PWM0_CH0 3553 * |[28:24] |PG15MFP |PG.15 Multi-function Pin Selection 3554 * | | |14 = CLKO 3555 * | | |15 = EADC0_ST 3556 * | | |16 = TK_SE 3557 * | | |23 = LPADC0_ST 3558 * @var SYS_T::GPH_MFP1 3559 * Offset: 0x574 GPIOH Multiple Function Control Register 1 3560 * --------------------------------------------------------------------------------------------------- 3561 * |Bits |Field |Descriptions 3562 * | :----: | :----: | :---- | 3563 * |[4:0] |PH4MFP |PH.4 Multi-function Pin Selection 3564 * | | |02 = EBI_ADR3 3565 * | | |03 = SPI1_MISO 3566 * | | |04 = UART7_nRTS 3567 * | | |05 = UART6_TXD 3568 * |[12:8] |PH5MFP |PH.5 Multi-function Pin Selection 3569 * | | |02 = EBI_ADR2 3570 * | | |03 = SPI1_MOSI 3571 * | | |04 = UART7_nCTS 3572 * | | |05 = UART6_RXD 3573 * |[20:16] |PH6MFP |PH.6 Multi-function Pin Selection 3574 * | | |02 = EBI_ADR1 3575 * | | |03 = SPI1_CLK 3576 * | | |04 = UART7_TXD 3577 * |[28:24] |PH7MFP |PH.7 Multi-function Pin Selection 3578 * | | |02 = EBI_ADR0 3579 * | | |03 = SPI1_SS 3580 * | | |04 = UART7_RXD 3581 * @var SYS_T::GPH_MFP2 3582 * Offset: 0x578 GPIOH Multiple Function Control Register 2 3583 * --------------------------------------------------------------------------------------------------- 3584 * |Bits |Field |Descriptions 3585 * | :----: | :----: | :---- | 3586 * |[4:0] |PH8MFP |PH.8 Multi-function Pin Selection 3587 * | | |02 = EBI_AD12 3588 * | | |03 = QSPI0_CLK 3589 * | | |06 = SPI1_CLK 3590 * | | |07 = UART3_nRTS 3591 * | | |08 = I2C1_SMBAL 3592 * | | |09 = I2C2_SCL 3593 * | | |10 = UART1_TXD 3594 * |[12:8] |PH9MFP |PH.9 Multi-function Pin Selection 3595 * | | |02 = EBI_AD13 3596 * | | |03 = QSPI0_SS 3597 * | | |06 = SPI1_SS 3598 * | | |07 = UART3_nCTS 3599 * | | |08 = I2C1_SMBSUS 3600 * | | |09 = I2C2_SDA 3601 * | | |10 = UART1_RXD 3602 * |[20:16] |PH10MFP |PH.10 Multi-function Pin Selection 3603 * | | |02 = EBI_AD14 3604 * | | |03 = QSPI0_MISO1 3605 * | | |06 = SPI1_I2SMCLK 3606 * | | |07 = UART4_TXD 3607 * | | |08 = UART0_TXD 3608 * | | |21 = LPUART0_TXD 3609 * |[28:24] |PH11MFP |PH.11 Multi-function Pin Selection 3610 * | | |02 = EBI_AD15 3611 * | | |03 = QSPI0_MOSI1 3612 * | | |07 = UART4_RXD 3613 * | | |08 = UART0_RXD 3614 * | | |11 = EPWM0_CH5 3615 * | | |21 = LPUART0_RXD 3616 */ 3617 __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ 3618 __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ 3619 __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ 3620 __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ 3621 __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ 3622 __I uint32_t RESERVE0[1]; 3623 __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ 3624 __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ 3625 __IO uint32_t IPRST3; /*!< [0x0020] Peripheral Reset Control Register 3 */ 3626 __I uint32_t RESERVE1[1]; 3627 __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ 3628 __IO uint32_t USBPHY; /*!< [0x002c] USB PHY Control Register */ 3629 __IO uint32_t UTCPDCTL; /*!< [0x0030] UTCPD Control Register */ 3630 __I uint32_t RESERVE2[19]; 3631 __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ 3632 __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ 3633 __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ 3634 __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ 3635 __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ 3636 __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ 3637 __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ 3638 __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ 3639 __I uint32_t RESERVE3[4]; 3640 __IO uint32_t MIRCTCTL; /*!< [0x00b0] MIRC1M Trim Control Register */ 3641 __IO uint32_t MIRCTIEN; /*!< [0x00b4] MIRC1M Trim Interrupt Enable Register */ 3642 __IO uint32_t MIRCTISTS; /*!< [0x00b8] MIRC1M Trim Interrupt Status Register */ 3643 __I uint32_t RESERVE4[1]; 3644 __IO uint32_t SRAM_INTCTL; /*!< [0x00c0] System SRAM Interrupt Enable Control Register */ 3645 __IO uint32_t SRAM_STATUS; /*!< [0x00c4] System SRAM Parity Error Status Register */ 3646 __I uint32_t SRAM_ERRADDR; /*!< [0x00c8] System SRAM Parity Check Error Address Register */ 3647 __I uint32_t RESERVE5[1]; 3648 __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ 3649 __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ 3650 __I uint32_t RESERVE6[1]; 3651 __IO uint32_t SRAMPC0; /*!< [0x00dc] SRAM Power Mode Control Register 0 */ 3652 __I uint32_t RESERVE7[1]; 3653 __IO uint32_t HIRCTCTL; /*!< [0x00e4] HIRC48M Trim Control Register */ 3654 __IO uint32_t HIRCTIEN; /*!< [0x00e8] HIRC48M Trim Interrupt Enable Register */ 3655 __IO uint32_t HIRCTISTS; /*!< [0x00ec] HIRC48M Trim Interrupt Status Register */ 3656 __IO uint32_t IRCTCTL; /*!< [0x00f0] HIRC Trim Control Register */ 3657 __IO uint32_t IRCTIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ 3658 __IO uint32_t IRCTISTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ 3659 __IO uint32_t RAMPGCTL; /*!< [0x00fc] RRAM Power Gating Contol Register */ 3660 __O uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ 3661 __I uint32_t RESERVE8[58]; 3662 __IO uint32_t PORDISAN; /*!< [0x01ec] Analog POR Disable Control Register */ 3663 __I uint32_t RESERVE9[1]; 3664 __I uint32_t CSERVER; /*!< [0x01f4] Chip Series Version Register */ 3665 __IO uint32_t PLCTL; /*!< [0x01f8] Power Level Control Register */ 3666 __IO uint32_t PLSTS; /*!< [0x01fc] Power Level Status Register */ 3667 __I uint32_t RESERVE10[68]; 3668 __IO uint32_t INIVTOR; /*!< [0x0310] Initial VTOR Control Register */ 3669 __I uint32_t RESERVE11[123]; 3670 __IO uint32_t GPA_MFP0; /*!< [0x0500] GPIOA Multiple Function Control Register 0 */ 3671 __IO uint32_t GPA_MFP1; /*!< [0x0504] GPIOA Multiple Function Control Register 1 */ 3672 __IO uint32_t GPA_MFP2; /*!< [0x0508] GPIOA Multiple Function Control Register 2 */ 3673 __IO uint32_t GPA_MFP3; /*!< [0x050c] GPIOA Multiple Function Control Register 3 */ 3674 __IO uint32_t GPB_MFP0; /*!< [0x0510] GPIOB Multiple Function Control Register 0 */ 3675 __IO uint32_t GPB_MFP1; /*!< [0x0514] GPIOB Multiple Function Control Register 1 */ 3676 __IO uint32_t GPB_MFP2; /*!< [0x0518] GPIOB Multiple Function Control Register 2 */ 3677 __IO uint32_t GPB_MFP3; /*!< [0x051c] GPIOB Multiple Function Control Register 3 */ 3678 __IO uint32_t GPC_MFP0; /*!< [0x0520] GPIOC Multiple Function Control Register 0 */ 3679 __IO uint32_t GPC_MFP1; /*!< [0x0524] GPIOC Multiple Function Control Register 1 */ 3680 __IO uint32_t GPC_MFP2; /*!< [0x0528] GPIOC Multiple Function Control Register 2 */ 3681 __IO uint32_t GPC_MFP3; /*!< [0x052c] GPIOC Multiple Function Control Register 3 */ 3682 __IO uint32_t GPD_MFP0; /*!< [0x0530] GPIOD Multiple Function Control Register 0 */ 3683 __IO uint32_t GPD_MFP1; /*!< [0x0534] GPIOD Multiple Function Control Register 1 */ 3684 __IO uint32_t GPD_MFP2; /*!< [0x0538] GPIOD Multiple Function Control Register 2 */ 3685 __IO uint32_t GPD_MFP3; /*!< [0x053c] GPIOD Multiple Function Control Register 3 */ 3686 __IO uint32_t GPE_MFP0; /*!< [0x0540] GPIOE Multiple Function Control Register 0 */ 3687 __IO uint32_t GPE_MFP1; /*!< [0x0544] GPIOE Multiple Function Control Register 1 */ 3688 __IO uint32_t GPE_MFP2; /*!< [0x0548] GPIOE Multiple Function Control Register 2 */ 3689 __IO uint32_t GPE_MFP3; /*!< [0x054c] GPIOE Multiple Function Control Register 3 */ 3690 __IO uint32_t GPF_MFP0; /*!< [0x0550] GPIOF Multiple Function Control Register 0 */ 3691 __IO uint32_t GPF_MFP1; /*!< [0x0554] GPIOF Multiple Function Control Register 1 */ 3692 __IO uint32_t GPF_MFP2; /*!< [0x0558] GPIOF Multiple Function Control Register 2 */ 3693 __I uint32_t RESERVE12[1]; 3694 __IO uint32_t GPG_MFP0; /*!< [0x0560] GPIOG Multiple Function Control Register 0 */ 3695 __IO uint32_t GPG_MFP1; /*!< [0x0564] GPIOG Multiple Function Control Register 1 */ 3696 __IO uint32_t GPG_MFP2; /*!< [0x0568] GPIOG Multiple Function Control Register 2 */ 3697 __IO uint32_t GPG_MFP3; /*!< [0x056c] GPIOG Multiple Function Control Register 3 */ 3698 __I uint32_t RESERVE13[1]; 3699 __IO uint32_t GPH_MFP1; /*!< [0x0574] GPIOH Multiple Function Control Register 1 */ 3700 __IO uint32_t GPH_MFP2; /*!< [0x0578] GPIOH Multiple Function Control Register 2 */ 3701 3702 } SYS_T; 3703 3704 /** 3705 @addtogroup SYS_CONST SYS Bit Field Definition 3706 Constant Definitions for SYS Controller 3707 @{ */ 3708 3709 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ 3710 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ 3711 3712 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ 3713 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ 3714 3715 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ 3716 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ 3717 3718 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ 3719 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ 3720 3721 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ 3722 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ 3723 3724 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ 3725 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ 3726 3727 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ 3728 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ 3729 3730 #define SYS_RSTSTS_HRESETRF_Pos (6) /*!< SYS_T::RSTSTS: HRESETRF Position */ 3731 #define SYS_RSTSTS_HRESETRF_Msk (0x1ul << SYS_RSTSTS_HRESETRF_Pos) /*!< SYS_T::RSTSTS: HRESETRF Mask */ 3732 3733 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ 3734 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ 3735 3736 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ 3737 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ 3738 3739 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ 3740 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ 3741 3742 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ 3743 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ 3744 3745 #define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */ 3746 #define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ 3747 3748 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ 3749 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ 3750 3751 #define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */ 3752 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ 3753 3754 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ 3755 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ 3756 3757 #define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ 3758 #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ 3759 3760 #define SYS_IPRST0_CANFD0RST_Pos (20) /*!< SYS_T::IPRST0: CANFD0RST Position */ 3761 #define SYS_IPRST0_CANFD0RST_Msk (0x1ul << SYS_IPRST0_CANFD0RST_Pos) /*!< SYS_T::IPRST0: CANFD0RST Mask */ 3762 3763 #define SYS_IPRST0_CANFD1RST_Pos (21) /*!< SYS_T::IPRST0: CANFD1RST Position */ 3764 #define SYS_IPRST0_CANFD1RST_Msk (0x1ul << SYS_IPRST0_CANFD1RST_Pos) /*!< SYS_T::IPRST0: CANFD1RST Mask */ 3765 3766 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ 3767 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ 3768 3769 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ 3770 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ 3771 3772 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ 3773 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ 3774 3775 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ 3776 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ 3777 3778 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ 3779 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ 3780 3781 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ 3782 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ 3783 3784 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ 3785 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ 3786 3787 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ 3788 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ 3789 3790 #define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ 3791 #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ 3792 3793 #define SYS_IPRST1_I2C3RST_Pos (11) /*!< SYS_T::IPRST1: I2C3RST Position */ 3794 #define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) /*!< SYS_T::IPRST1: I2C3RST Mask */ 3795 3796 #define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ 3797 #define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ 3798 3799 #define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ 3800 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ 3801 3802 #define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ 3803 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ 3804 3805 #define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ 3806 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ 3807 3808 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ 3809 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ 3810 3811 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ 3812 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ 3813 3814 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ 3815 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ 3816 3817 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ 3818 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ 3819 3820 #define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ 3821 #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ 3822 3823 #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ 3824 #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ 3825 3826 #define SYS_IPRST1_UART6RST_Pos (22) /*!< SYS_T::IPRST1: UART6RST Position */ 3827 #define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) /*!< SYS_T::IPRST1: UART6RST Mask */ 3828 3829 #define SYS_IPRST1_UART7RST_Pos (23) /*!< SYS_T::IPRST1: UART7RST Position */ 3830 #define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) /*!< SYS_T::IPRST1: UART7RST Mask */ 3831 3832 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ 3833 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ 3834 3835 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ 3836 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ 3837 3838 #define SYS_IPRST1_EADC0RST_Pos (28) /*!< SYS_T::IPRST1: EADC0RST Position */ 3839 #define SYS_IPRST1_EADC0RST_Msk (0x1ul << SYS_IPRST1_EADC0RST_Pos) /*!< SYS_T::IPRST1: EADC0RST Mask */ 3840 3841 #define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ 3842 #define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ 3843 3844 #define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ 3845 #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ 3846 3847 #define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ 3848 #define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ 3849 3850 #define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ 3851 #define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ 3852 3853 #define SYS_IPRST2_WWDTRST_Pos (11) /*!< SYS_T::IPRST2: WWDTRST Position */ 3854 #define SYS_IPRST2_WWDTRST_Msk (0x1ul << SYS_IPRST2_WWDTRST_Pos) /*!< SYS_T::IPRST2: WWDTRST Mask */ 3855 3856 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ 3857 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ 3858 3859 #define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ 3860 #define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ 3861 3862 #define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ 3863 #define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ 3864 3865 #define SYS_IPRST2_EQEI0RST_Pos (22) /*!< SYS_T::IPRST2: EQEI0RST Position */ 3866 #define SYS_IPRST2_EQEI0RST_Msk (0x1ul << SYS_IPRST2_EQEI0RST_Pos) /*!< SYS_T::IPRST2: EQEI0RST Mask */ 3867 3868 #define SYS_IPRST2_EQEI1RST_Pos (23) /*!< SYS_T::IPRST2: EQEI1RST Position */ 3869 #define SYS_IPRST2_EQEI1RST_Msk (0x1ul << SYS_IPRST2_EQEI1RST_Pos) /*!< SYS_T::IPRST2: EQEI1RST Mask */ 3870 3871 #define SYS_IPRST2_TKRST_Pos (25) /*!< SYS_T::IPRST2: TKRST Position */ 3872 #define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos) /*!< SYS_T::IPRST2: TKRST Mask */ 3873 3874 #define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ 3875 #define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ 3876 3877 #define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ 3878 #define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ 3879 3880 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ 3881 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ 3882 3883 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ 3884 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ 3885 3886 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ 3887 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ 3888 3889 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ 3890 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ 3891 3892 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ 3893 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ 3894 3895 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ 3896 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ 3897 3898 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ 3899 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ 3900 3901 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ 3902 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ 3903 3904 #define SYS_BODCTL_LVRRDY_Pos (15) /*!< SYS_T::BODCTL: LVRRDY Position */ 3905 #define SYS_BODCTL_LVRRDY_Msk (0x1ul << SYS_BODCTL_LVRRDY_Pos) /*!< SYS_T::BODCTL: LVRRDY Mask */ 3906 3907 #define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ 3908 #define SYS_BODCTL_BODVL_Msk (0xful << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ 3909 3910 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ 3911 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ 3912 3913 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ 3914 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ 3915 3916 #define SYS_IVSCTL_AVDDDIV4EN_Pos (2) /*!< SYS_T::IVSCTL: AVDDDIV4EN Position */ 3917 #define SYS_IVSCTL_AVDDDIV4EN_Msk (0x1ul << SYS_IVSCTL_AVDDDIV4EN_Pos) /*!< SYS_T::IVSCTL: AVDDDIV4EN Mask */ 3918 3919 #define SYS_IVSCTL_VTEMPSEL_Pos (4) /*!< SYS_T::IVSCTL: VTEMPSEL Position */ 3920 #define SYS_IVSCTL_VTEMPSEL_Msk (0x1ul << SYS_IVSCTL_VTEMPSEL_Pos) /*!< SYS_T::IVSCTL: VTEMPSEL Mask */ 3921 3922 #define SYS_IVSCTL_ADCCSEL_Pos (7) /*!< SYS_T::IVSCTL: ADCCSEL Position */ 3923 #define SYS_IVSCTL_ADCCSEL_Msk (0x1ul << SYS_IVSCTL_ADCCSEL_Pos) /*!< SYS_T::IVSCTL: ADCCSEL Mask */ 3924 3925 #define SYS_IPRST3_ACMP2RST_Pos (7) /*!< SYS_T::IPRST3: ACMP2RST Position */ 3926 #define SYS_IPRST3_ACMP2RST_Msk (0x1ul << SYS_IPRST3_ACMP2RST_Pos) /*!< SYS_T::IPRST3: ACMP2RST Mask */ 3927 3928 #define SYS_IPRST3_PWM0RST_Pos (8) /*!< SYS_T::IPRST3: PWM0RST Position */ 3929 #define SYS_IPRST3_PWM0RST_Msk (0x1ul << SYS_IPRST3_PWM0RST_Pos) /*!< SYS_T::IPRST3: PWM0RST Mask */ 3930 3931 #define SYS_IPRST3_PWM1RST_Pos (9) /*!< SYS_T::IPRST3: PWM1RST Position */ 3932 #define SYS_IPRST3_PWM1RST_Msk (0x1ul << SYS_IPRST3_PWM1RST_Pos) /*!< SYS_T::IPRST3: PWM1RST Mask */ 3933 3934 #define SYS_IPRST3_UTCPD0RST_Pos (15) /*!< SYS_T::IPRST3: UTCPD0RST Position */ 3935 #define SYS_IPRST3_UTCPD0RST_Msk (0x1ul << SYS_IPRST3_UTCPD0RST_Pos) /*!< SYS_T::IPRST3: UTCPD0RST Mask */ 3936 3937 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ 3938 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ 3939 3940 #define SYS_VREFCTL_PRELOAD_SEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOAD_SEL Position */ 3941 #define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) /*!< SYS_T::VREFCTL: PRELOAD_SEL Mask */ 3942 3943 #define SYS_VREFCTL_VBGFEN_Pos (24) /*!< SYS_T::VREFCTL: VBGFEN Position */ 3944 #define SYS_VREFCTL_VBGFEN_Msk (0x1ul << SYS_VREFCTL_VBGFEN_Pos) /*!< SYS_T::VREFCTL: VBGFEN Mask */ 3945 3946 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ 3947 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ 3948 3949 #define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ 3950 #define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ 3951 3952 #define SYS_USBPHY_USBEN_Pos (8) /*!< SYS_T::USBPHY: USBEN Position */ 3953 #define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) /*!< SYS_T::USBPHY: USBEN Mask */ 3954 3955 #define SYS_UTCPDCTL_IOMODE_Pos (0) /*!< SYS_T::UTCPDCTL: IOMODE Position */ 3956 #define SYS_UTCPDCTL_IOMODE_Msk (0x1ul << SYS_UTCPDCTL_IOMODE_Pos) /*!< SYS_T::UTCPDCTL: IOMODE Mask */ 3957 3958 #define SYS_UTCPDCTL_POREN0_Pos (1) /*!< SYS_T::UTCPDCTL: POREN0 Position */ 3959 #define SYS_UTCPDCTL_POREN0_Msk (0x1ul << SYS_UTCPDCTL_POREN0_Pos) /*!< SYS_T::UTCPDCTL: POREN0 Mask */ 3960 3961 #define SYS_UTCPDCTL_PD0VBDSS_Pos (8) /*!< SYS_T::UTCPDCTL: PD0VBDSS Position */ 3962 #define SYS_UTCPDCTL_PD0VBDSS_Msk (0x7ul << SYS_UTCPDCTL_PD0VBDSS_Pos) /*!< SYS_T::UTCPDCTL: PD0VBDSS Mask */ 3963 3964 #define SYS_UTCPDCTL_UDVBDETS_Pos (12) /*!< SYS_T::UTCPDCTL: UDVBDETS Position */ 3965 #define SYS_UTCPDCTL_UDVBDETS_Msk (0x1ul << SYS_UTCPDCTL_UDVBDETS_Pos) /*!< SYS_T::UTCPDCTL: UDVBDETS Mask */ 3966 3967 #define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ 3968 #define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ 3969 3970 #define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ 3971 #define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ 3972 3973 #define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ 3974 #define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ 3975 3976 #define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ 3977 #define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ 3978 3979 #define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ 3980 #define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ 3981 3982 #define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ 3983 #define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ 3984 3985 #define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ 3986 #define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ 3987 3988 #define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ 3989 #define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ 3990 3991 #define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ 3992 #define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ 3993 3994 #define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ 3995 #define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ 3996 3997 #define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ 3998 #define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ 3999 4000 #define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ 4001 #define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ 4002 4003 #define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ 4004 #define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ 4005 4006 #define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ 4007 #define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ 4008 4009 #define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ 4010 #define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ 4011 4012 #define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ 4013 #define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ 4014 4015 #define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ 4016 #define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ 4017 4018 #define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ 4019 #define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ 4020 4021 #define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ 4022 #define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ 4023 4024 #define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ 4025 #define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ 4026 4027 #define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ 4028 #define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ 4029 4030 #define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ 4031 #define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ 4032 4033 #define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ 4034 #define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ 4035 4036 #define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ 4037 #define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ 4038 4039 #define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ 4040 #define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ 4041 4042 #define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ 4043 #define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ 4044 4045 #define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ 4046 #define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ 4047 4048 #define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ 4049 #define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ 4050 4051 #define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ 4052 #define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ 4053 4054 #define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ 4055 #define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ 4056 4057 #define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ 4058 #define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ 4059 4060 #define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ 4061 #define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ 4062 4063 #define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ 4064 #define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ 4065 4066 #define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ 4067 #define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ 4068 4069 #define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ 4070 #define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ 4071 4072 #define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ 4073 #define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ 4074 4075 #define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ 4076 #define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ 4077 4078 #define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ 4079 #define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ 4080 4081 #define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ 4082 #define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ 4083 4084 #define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ 4085 #define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ 4086 4087 #define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ 4088 #define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ 4089 4090 #define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ 4091 #define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ 4092 4093 #define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ 4094 #define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ 4095 4096 #define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ 4097 #define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ 4098 4099 #define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ 4100 #define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ 4101 4102 #define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ 4103 #define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ 4104 4105 #define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ 4106 #define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ 4107 4108 #define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */ 4109 #define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */ 4110 4111 #define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ 4112 #define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ 4113 4114 #define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ 4115 #define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ 4116 4117 #define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ 4118 #define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ 4119 4120 #define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ 4121 #define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ 4122 4123 #define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ 4124 #define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ 4125 4126 #define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ 4127 #define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ 4128 4129 #define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ 4130 #define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ 4131 4132 #define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ 4133 #define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ 4134 4135 #define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ 4136 #define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ 4137 4138 #define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ 4139 #define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ 4140 4141 #define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ 4142 #define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ 4143 4144 #define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ 4145 #define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ 4146 4147 #define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ 4148 #define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ 4149 4150 #define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ 4151 #define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ 4152 4153 #define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ 4154 #define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ 4155 4156 #define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */ 4157 #define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */ 4158 4159 #define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ 4160 #define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ 4161 4162 #define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ 4163 #define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ 4164 4165 #define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ 4166 #define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ 4167 4168 #define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ 4169 #define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ 4170 4171 #define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ 4172 #define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ 4173 4174 #define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ 4175 #define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ 4176 4177 #define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ 4178 #define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ 4179 4180 #define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ 4181 #define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ 4182 4183 #define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ 4184 #define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ 4185 4186 #define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ 4187 #define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ 4188 4189 #define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ 4190 #define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ 4191 4192 #define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ 4193 #define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ 4194 4195 #define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ 4196 #define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ 4197 4198 #define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ 4199 #define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ 4200 4201 #define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ 4202 #define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ 4203 4204 #define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ 4205 #define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ 4206 4207 #define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ 4208 #define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ 4209 4210 #define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ 4211 #define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ 4212 4213 #define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ 4214 #define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ 4215 4216 #define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ 4217 #define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ 4218 4219 #define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ 4220 #define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ 4221 4222 #define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ 4223 #define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ 4224 4225 #define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ 4226 #define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ 4227 4228 #define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ 4229 #define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ 4230 4231 #define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ 4232 #define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ 4233 4234 #define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ 4235 #define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ 4236 4237 #define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ 4238 #define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ 4239 4240 #define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ 4241 #define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ 4242 4243 #define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */ 4244 #define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */ 4245 4246 #define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */ 4247 #define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */ 4248 4249 #define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */ 4250 #define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */ 4251 4252 #define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */ 4253 #define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */ 4254 4255 #define SYS_GPG_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPG_MFOS: MFOS0 Position */ 4256 #define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) /*!< SYS_T::GPG_MFOS: MFOS0 Mask */ 4257 4258 #define SYS_GPG_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPG_MFOS: MFOS1 Position */ 4259 #define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) /*!< SYS_T::GPG_MFOS: MFOS1 Mask */ 4260 4261 #define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ 4262 #define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ 4263 4264 #define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ 4265 #define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ 4266 4267 #define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ 4268 #define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ 4269 4270 #define SYS_GPG_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPG_MFOS: MFOS5 Position */ 4271 #define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) /*!< SYS_T::GPG_MFOS: MFOS5 Mask */ 4272 4273 #define SYS_GPG_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPG_MFOS: MFOS6 Position */ 4274 #define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) /*!< SYS_T::GPG_MFOS: MFOS6 Mask */ 4275 4276 #define SYS_GPG_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPG_MFOS: MFOS7 Position */ 4277 #define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) /*!< SYS_T::GPG_MFOS: MFOS7 Mask */ 4278 4279 #define SYS_GPG_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPG_MFOS: MFOS8 Position */ 4280 #define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) /*!< SYS_T::GPG_MFOS: MFOS8 Mask */ 4281 4282 #define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ 4283 #define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ 4284 4285 #define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ 4286 #define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ 4287 4288 #define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ 4289 #define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ 4290 4291 #define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ 4292 #define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ 4293 4294 #define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ 4295 #define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ 4296 4297 #define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ 4298 #define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ 4299 4300 #define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ 4301 #define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ 4302 4303 #define SYS_GPH_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPH_MFOS: MFOS0 Position */ 4304 #define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) /*!< SYS_T::GPH_MFOS: MFOS0 Mask */ 4305 4306 #define SYS_GPH_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPH_MFOS: MFOS1 Position */ 4307 #define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) /*!< SYS_T::GPH_MFOS: MFOS1 Mask */ 4308 4309 #define SYS_GPH_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPH_MFOS: MFOS2 Position */ 4310 #define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) /*!< SYS_T::GPH_MFOS: MFOS2 Mask */ 4311 4312 #define SYS_GPH_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPH_MFOS: MFOS3 Position */ 4313 #define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) /*!< SYS_T::GPH_MFOS: MFOS3 Mask */ 4314 4315 #define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ 4316 #define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ 4317 4318 #define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ 4319 #define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ 4320 4321 #define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ 4322 #define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ 4323 4324 #define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ 4325 #define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ 4326 4327 #define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ 4328 #define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ 4329 4330 #define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ 4331 #define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ 4332 4333 #define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ 4334 #define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ 4335 4336 #define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ 4337 #define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ 4338 4339 #define SYS_GPH_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPH_MFOS: MFOS12 Position */ 4340 #define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) /*!< SYS_T::GPH_MFOS: MFOS12 Mask */ 4341 4342 #define SYS_GPH_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPH_MFOS: MFOS13 Position */ 4343 #define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) /*!< SYS_T::GPH_MFOS: MFOS13 Mask */ 4344 4345 #define SYS_GPH_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPH_MFOS: MFOS14 Position */ 4346 #define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) /*!< SYS_T::GPH_MFOS: MFOS14 Mask */ 4347 4348 #define SYS_GPH_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPH_MFOS: MFOS15 Position */ 4349 #define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) /*!< SYS_T::GPH_MFOS: MFOS15 Mask */ 4350 4351 #define SYS_MIRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::MIRCTCTL: FREQSEL Position */ 4352 #define SYS_MIRCTCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTCTL_FREQSEL_Pos) /*!< SYS_T::MIRCTCTL: FREQSEL Mask */ 4353 4354 #define SYS_MIRCTCTL_ACCURSEL_Pos (2) /*!< SYS_T::MIRCTCTL: ACCURSEL Position */ 4355 #define SYS_MIRCTCTL_ACCURSEL_Msk (0x3ul << SYS_MIRCTCTL_ACCURSEL_Pos) /*!< SYS_T::MIRCTCTL: ACCURSEL Mask */ 4356 4357 #define SYS_MIRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::MIRCTCTL: LOOPSEL Position */ 4358 #define SYS_MIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTCTL_LOOPSEL_Pos) /*!< SYS_T::MIRCTCTL: LOOPSEL Mask */ 4359 4360 #define SYS_MIRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::MIRCTCTL: RETRYCNT Position */ 4361 #define SYS_MIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTCTL_RETRYCNT_Pos) /*!< SYS_T::MIRCTCTL: RETRYCNT Mask */ 4362 4363 #define SYS_MIRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::MIRCTCTL: CESTOPEN Position */ 4364 #define SYS_MIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::MIRCTCTL: CESTOPEN Mask */ 4365 4366 #define SYS_MIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::MIRCTCTL: BOUNDEN Position */ 4367 #define SYS_MIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_MIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::MIRCTCTL: BOUNDEN Mask */ 4368 4369 #define SYS_MIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::MIRCTCTL: REFCKSEL Position */ 4370 #define SYS_MIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_MIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::MIRCTCTL: REFCKSEL Mask */ 4371 4372 #define SYS_MIRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::MIRCTCTL: BOUNDARY Position */ 4373 #define SYS_MIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_MIRCTCTL_BOUNDARY_Pos) /*!< SYS_T::MIRCTCTL: BOUNDARY Mask */ 4374 4375 #define SYS_MIRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::MIRCTIEN: TFAILIEN Position */ 4376 #define SYS_MIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_MIRCTIEN_TFAILIEN_Pos) /*!< SYS_T::MIRCTIEN: TFAILIEN Mask */ 4377 4378 #define SYS_MIRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::MIRCTIEN: CLKEIEN Position */ 4379 #define SYS_MIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTIEN_CLKEIEN_Pos) /*!< SYS_T::MIRCTIEN: CLKEIEN Mask */ 4380 4381 #define SYS_MIRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::MIRCTISTS: FREQLOCK Position */ 4382 #define SYS_MIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTISTS_FREQLOCK_Pos) /*!< SYS_T::MIRCTISTS: FREQLOCK Mask */ 4383 4384 #define SYS_MIRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::MIRCTISTS: TFAILIF Position */ 4385 #define SYS_MIRCTISTS_TFAILIF_Msk (0x1ul << SYS_MIRCTISTS_TFAILIF_Pos) /*!< SYS_T::MIRCTISTS: TFAILIF Mask */ 4386 4387 #define SYS_MIRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::MIRCTISTS: CLKERRIF Position */ 4388 #define SYS_MIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_MIRCTISTS_CLKERRIF_Pos) /*!< SYS_T::MIRCTISTS: CLKERRIF Mask */ 4389 4390 #define SYS_MIRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::MIRCTISTS: OVBDIF Position */ 4391 #define SYS_MIRCTISTS_OVBDIF_Msk (0x1ul << SYS_MIRCTISTS_OVBDIF_Pos) /*!< SYS_T::MIRCTISTS: OVBDIF Mask */ 4392 4393 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS_T::SRAM_INTCTL: PERRIEN Position */ 4394 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS_T::SRAM_INTCTL: PERRIEN Mask */ 4395 4396 #define SYS_SRAM_STATUS_PERRIF_Pos (0) /*!< SYS_T::SRAM_STATUS: PERRIF Position */ 4397 #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) /*!< SYS_T::SRAM_STATUS: PERRIF Mask */ 4398 4399 #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Position */ 4400 #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) /*!< SYS_T::SRAM_ERRADDR: ERRADDR Mask */ 4401 4402 #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Position */ 4403 #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST0 Mask */ 4404 4405 #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Position */ 4406 #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST1 Mask */ 4407 4408 #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: CRBIST Position */ 4409 #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CRBIST Mask */ 4410 4411 #define SYS_SRAM_BISTCTL_CANFDBIST_Pos (3) /*!< SYS_T::SRAM_BISTCTL: CANFDBIST Position*/ 4412 #define SYS_SRAM_BISTCTL_CANFDBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANFDBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: CANFDBIST Mask */ 4413 4414 #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ 4415 #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ 4416 4417 #define SYS_SRAM_BISTCTL_LPSRBIST_Pos (11) /*!< SYS_T::SRAM_BISTCTL: LPSRBIST Position */ 4418 #define SYS_SRAM_BISTCTL_LPSRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_LPSRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: LPSRBIST Mask */ 4419 4420 #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Position*/ 4421 #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask */ 4422 4423 #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Position*/ 4424 #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask */ 4425 4426 #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Position */ 4427 #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBISTEF Mask */ 4428 4429 #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) /*!< SYS_T::SRAM_BISTSTS: CANBEF Position */ 4430 #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEF Mask */ 4431 4432 #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ 4433 #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ 4434 4435 #define SYS_SRAM_BISTSTS_LPSRBEF_Pos (11) /*!< SYS_T::SRAM_BISTSTS: LPSRBEF Position */ 4436 #define SYS_SRAM_BISTSTS_LPSRBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_LPSRBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: LPSRBEF Mask */ 4437 4438 #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Position */ 4439 #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND0 Mask */ 4440 4441 #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Position */ 4442 #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND1 Mask */ 4443 4444 #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CRBEND Position */ 4445 #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CRBEND Mask */ 4446 4447 #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) /*!< SYS_T::SRAM_BISTSTS: CANBEND Position */ 4448 #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CANBEND Mask */ 4449 4450 #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ 4451 #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ 4452 4453 #define SYS_SRAM_BISTSTS_LPSRBEND_Pos (27) /*!< SYS_T::SRAM_BISTSTS: LPSRBEND Position */ 4454 #define SYS_SRAM_BISTSTS_LPSRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_LPSRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: LPSRBEND Mask */ 4455 4456 #define SYS_SRAMPC0_SRAM0PM_Pos (0) /*!< SYS_T::SRAMPC0: SRAM0PM Position */ 4457 #define SYS_SRAMPC0_SRAM0PM_Msk (0x7ul << SYS_SRAMPC0_SRAM0PM_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM Mask */ 4458 4459 #define SYS_SRAMPC0_SRAM1PM_Pos (4) /*!< SYS_T::SRAMPC0: SRAM1PM Position */ 4460 #define SYS_SRAMPC0_SRAM1PM_Msk (0x7ul << SYS_SRAMPC0_SRAM1PM_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM Mask */ 4461 4462 #define SYS_SRAMPC0_SRAM2PM_Pos (8) /*!< SYS_T::SRAMPC0: SRAM2PM Position */ 4463 #define SYS_SRAMPC0_SRAM2PM_Msk (0x7ul << SYS_SRAMPC0_SRAM2PM_Pos) /*!< SYS_T::SRAMPC0: SRAM2PM Mask */ 4464 4465 #define SYS_SRAMPC0_SRAM3PM_Pos (12) /*!< SYS_T::SRAMPC0: SRAM3PM Position */ 4466 #define SYS_SRAMPC0_SRAM3PM_Msk (0x7ul << SYS_SRAMPC0_SRAM3PM_Pos) /*!< SYS_T::SRAMPC0: SRAM3PM Mask */ 4467 4468 #define SYS_SRAMPC0_SRAM4PM_Pos (16) /*!< SYS_T::SRAMPC0: SRAM4PM Position */ 4469 #define SYS_SRAMPC0_SRAM4PM_Msk (0x7ul << SYS_SRAMPC0_SRAM4PM_Pos) /*!< SYS_T::SRAMPC0: SRAM4PM Mask */ 4470 4471 #define SYS_SRAMPC0_SRAM5PM_Pos (20) /*!< SYS_T::SRAMPC0: SRAM5PM Position */ 4472 #define SYS_SRAMPC0_SRAM5PM_Msk (0x7ul << SYS_SRAMPC0_SRAM5PM_Pos) /*!< SYS_T::SRAMPC0: SRAM5PM Mask */ 4473 4474 #define SYS_SRAMPC0_SRAM6PM_Pos (24) /*!< SYS_T::SRAMPC0: SRAM6PM Position */ 4475 #define SYS_SRAMPC0_SRAM6PM_Msk (0x7ul << SYS_SRAMPC0_SRAM6PM_Pos) /*!< SYS_T::SRAMPC0: SRAM6PM Mask */ 4476 4477 #define SYS_SRAMPC0_PCBUSY_Pos (31) /*!< SYS_T::SRAMPC0: PCBUSY Position */ 4478 #define SYS_SRAMPC0_PCBUSY_Msk (0x1ul << SYS_SRAMPC0_PCBUSY_Pos) /*!< SYS_T::SRAMPC0: PCBUSY Mask */ 4479 4480 #define SYS_HIRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::HIRCTCTL: FREQSEL Position */ 4481 #define SYS_HIRCTCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTCTL_FREQSEL_Pos) /*!< SYS_T::HIRCTCTL: FREQSEL Mask */ 4482 4483 #define SYS_HIRCTCTL_ACCURSEL_Pos (2) /*!< SYS_T::HIRCTCTL: ACCURSEL Position */ 4484 #define SYS_HIRCTCTL_ACCURSEL_Msk (0x3ul << SYS_HIRCTCTL_ACCURSEL_Pos) /*!< SYS_T::HIRCTCTL: ACCURSEL Mask */ 4485 4486 #define SYS_HIRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::HIRCTCTL: LOOPSEL Position */ 4487 #define SYS_HIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTCTL_LOOPSEL_Pos) /*!< SYS_T::HIRCTCTL: LOOPSEL Mask */ 4488 4489 #define SYS_HIRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::HIRCTCTL: RETRYCNT Position */ 4490 #define SYS_HIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTCTL_RETRYCNT_Pos) /*!< SYS_T::HIRCTCTL: RETRYCNT Mask */ 4491 4492 #define SYS_HIRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::HIRCTCTL: CESTOPEN Position */ 4493 #define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTCTL: CESTOPEN Mask */ 4494 4495 #define SYS_HIRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTCTL: BOUNDEN Position */ 4496 #define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTCTL: BOUNDEN Mask */ 4497 4498 #define SYS_HIRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTCTL: REFCKSEL Position */ 4499 #define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTCTL: REFCKSEL Mask */ 4500 4501 #define SYS_HIRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::HIRCTCTL: BOUNDARY Position */ 4502 #define SYS_HIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTCTL_BOUNDARY_Pos) /*!< SYS_T::HIRCTCTL: BOUNDARY Mask */ 4503 4504 #define SYS_HIRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::HIRCTIEN: TFAILIEN Position */ 4505 #define SYS_HIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_HIRCTIEN_TFAILIEN_Pos) /*!< SYS_T::HIRCTIEN: TFAILIEN Mask */ 4506 4507 #define SYS_HIRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::HIRCTIEN: CLKEIEN Position */ 4508 #define SYS_HIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTIEN_CLKEIEN_Pos) /*!< SYS_T::HIRCTIEN: CLKEIEN Mask */ 4509 4510 #define SYS_HIRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::HIRCTISTS: FREQLOCK Position */ 4511 #define SYS_HIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTISTS_FREQLOCK_Pos) /*!< SYS_T::HIRCTISTS: FREQLOCK Mask */ 4512 4513 #define SYS_HIRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::HIRCTISTS: TFAILIF Position */ 4514 #define SYS_HIRCTISTS_TFAILIF_Msk (0x1ul << SYS_HIRCTISTS_TFAILIF_Pos) /*!< SYS_T::HIRCTISTS: TFAILIF Mask */ 4515 4516 #define SYS_HIRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::HIRCTISTS: CLKERRIF Position */ 4517 #define SYS_HIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_HIRCTISTS_CLKERRIF_Pos) /*!< SYS_T::HIRCTISTS: CLKERRIF Mask */ 4518 4519 #define SYS_HIRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::HIRCTISTS: OVBDIF Position */ 4520 #define SYS_HIRCTISTS_OVBDIF_Msk (0x1ul << SYS_HIRCTISTS_OVBDIF_Pos) /*!< SYS_T::HIRCTISTS: OVBDIF Mask */ 4521 4522 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS_T::IRCTCTL: FREQSEL Position */ 4523 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS_T::IRCTCTL: FREQSEL Mask */ 4524 4525 #define SYS_IRCTCTL_ACCURSEL_Pos (2) /*!< SYS_T::IRCTCTL: ACCURSEL Position */ 4526 #define SYS_IRCTCTL_ACCURSEL_Msk (0x3ul << SYS_IRCTCTL_ACCURSEL_Pos) /*!< SYS_T::IRCTCTL: ACCURSEL Mask */ 4527 4528 #define SYS_IRCTCTL_LOOPSEL_Pos (4) /*!< SYS_T::IRCTCTL: LOOPSEL Position */ 4529 #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) /*!< SYS_T::IRCTCTL: LOOPSEL Mask */ 4530 4531 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS_T::IRCTCTL: RETRYCNT Position */ 4532 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS_T::IRCTCTL: RETRYCNT Mask */ 4533 4534 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS_T::IRCTCTL: CESTOPEN Position */ 4535 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS_T::IRCTCTL: CESTOPEN Mask */ 4536 4537 #define SYS_IRCTCTL_BOUNDEN_Pos (9) /*!< SYS_T::IRCTCTL: BOUNDEN Position */ 4538 #define SYS_IRCTCTL_BOUNDEN_Msk (0x1ul << SYS_IRCTCTL_BOUNDEN_Pos) /*!< SYS_T::IRCTCTL: BOUNDEN Mask */ 4539 4540 #define SYS_IRCTCTL_REFCKSEL_Pos (10) /*!< SYS_T::IRCTCTL: REFCKSEL Position */ 4541 #define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) /*!< SYS_T::IRCTCTL: REFCKSEL Mask */ 4542 4543 #define SYS_IRCTCTL_BOUNDARY_Pos (16) /*!< SYS_T::IRCTCTL: BOUNDARY Position */ 4544 #define SYS_IRCTCTL_BOUNDARY_Msk (0x1ful << SYS_IRCTCTL_BOUNDARY_Pos) /*!< SYS_T::IRCTCTL: BOUNDARY Mask */ 4545 4546 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS_T::IRCTIEN: TFAILIEN Position */ 4547 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS_T::IRCTIEN: TFAILIEN Mask */ 4548 4549 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS_T::IRCTIEN: CLKEIEN Position */ 4550 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS_T::IRCTIEN: CLKEIEN Mask */ 4551 4552 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS_T::IRCTISTS: FREQLOCK Position */ 4553 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS_T::IRCTISTS: FREQLOCK Mask */ 4554 4555 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS_T::IRCTISTS: TFAILIF Position */ 4556 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS_T::IRCTISTS: TFAILIF Mask */ 4557 4558 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS_T::IRCTISTS: CLKERRIF Position */ 4559 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS_T::IRCTISTS: CLKERRIF Mask */ 4560 4561 #define SYS_IRCTISTS_OVBDIF_Pos (3) /*!< SYS_T::IRCTISTS: OVBDIF Position */ 4562 #define SYS_IRCTISTS_OVBDIF_Msk (0x1ul << SYS_IRCTISTS_OVBDIF_Pos) /*!< SYS_T::IRCTISTS: OVBDIF Mask */ 4563 4564 #define SYS_RAMPGCTL_RRAMPGEN0_Pos (0) /*!< SYS_T::RAMPGCTL: RRAMPGEN0 Position */ 4565 #define SYS_RAMPGCTL_RRAMPGEN0_Msk (0x1ul << SYS_RAMPGCTL_RRAMPGEN0_Pos) /*!< SYS_T::RAMPGCTL: RRAMPGEN0 Mask */ 4566 4567 #define SYS_RAMPGCTL_RRAMPGDN0_Pos (1) /*!< SYS_T::RAMPGCTL: RRAMPGDN0 Position */ 4568 #define SYS_RAMPGCTL_RRAMPGDN0_Msk (0x1ul << SYS_RAMPGCTL_RRAMPGDN0_Pos) /*!< SYS_T::RAMPGCTL: RRAMPGDN0 Mask */ 4569 4570 #define SYS_RAMPGCTL_RRAMBUSY0_Pos (2) /*!< SYS_T::RAMPGCTL: RRAMBUSY0 Position */ 4571 #define SYS_RAMPGCTL_RRAMBUSY0_Msk (0x1ul << SYS_RAMPGCTL_RRAMBUSY0_Pos) /*!< SYS_T::RAMPGCTL: RRAMBUSY0 Mask */ 4572 4573 #define SYS_RAMPGCTL_RRAMPGEN1_Pos (4) /*!< SYS_T::RAMPGCTL: RRAMPGEN1 Position */ 4574 #define SYS_RAMPGCTL_RRAMPGEN1_Msk (0x1ul << SYS_RAMPGCTL_RRAMPGEN1_Pos) /*!< SYS_T::RAMPGCTL: RRAMPGEN1 Mask */ 4575 4576 #define SYS_RAMPGCTL_RRAMPGDN1_Pos (5) /*!< SYS_T::RAMPGCTL: RRAMPGDN1 Position */ 4577 #define SYS_RAMPGCTL_RRAMPGDN1_Msk (0x1ul << SYS_RAMPGCTL_RRAMPGDN1_Pos) /*!< SYS_T::RAMPGCTL: RRAMPGDN1 Mask */ 4578 4579 #define SYS_RAMPGCTL_RRAMBUSY1_Pos (6) /*!< SYS_T::RAMPGCTL: RRAMBUSY1 Position */ 4580 #define SYS_RAMPGCTL_RRAMBUSY1_Msk (0x1ul << SYS_RAMPGCTL_RRAMBUSY1_Pos) /*!< SYS_T::RAMPGCTL: RRAMBUSY1 Mask */ 4581 4582 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ 4583 #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ 4584 4585 #define SYS_PORDISAN_POROFFAN_Pos (0) /*!< SYS_T::PORDISAN: POROFFAN Position */ 4586 #define SYS_PORDISAN_POROFFAN_Msk (0xfffful << SYS_PORDISAN_POROFFAN_Pos) /*!< SYS_T::PORDISAN: POROFFAN Mask */ 4587 4588 #define SYS_CSERVER_VERSION_Pos (0) /*!< SYS_T::CSERVER: VERSION Position */ 4589 #define SYS_CSERVER_VERSION_Msk (0xfful << SYS_CSERVER_VERSION_Pos) /*!< SYS_T::CSERVER: VERSION Mask */ 4590 4591 #define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ 4592 #define SYS_PLCTL_PLSEL_Msk (0x7ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ 4593 4594 #define SYS_PLCTL_PLKEEP_Pos (3) /*!< SYS_T::PLCTL: PLKEEP Position */ 4595 #define SYS_PLCTL_PLKEEP_Msk (0x1ul << SYS_PLCTL_PLKEEP_Pos) /*!< SYS_T::PLCTL: PLKEEP Mask */ 4596 4597 #define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ 4598 #define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ 4599 4600 #define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ 4601 #define SYS_PLSTS_PLSTATUS_Msk (0x7ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ 4602 4603 #define SYS_INIVTOR_INIVTOR_Pos (10) /*!< SYS_T::INIVTOR: INIVTOR Position */ 4604 #define SYS_INIVTOR_INIVTOR_Msk (0x3ffffful << SYS_INIVTOR_INIVTOR_Pos) /*!< SYS_T::INIVTOR: INIVTOR Mask */ 4605 4606 #define SYS_GPA_MFP0_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFP0: PA0MFP Position */ 4607 #define SYS_GPA_MFP0_PA0MFP_Msk (0x1ful << SYS_GPA_MFP0_PA0MFP_Pos) /*!< SYS_T::GPA_MFP0: PA0MFP Mask */ 4608 4609 #define SYS_GPA_MFP0_PA1MFP_Pos (8) /*!< SYS_T::GPA_MFP0: PA1MFP Position */ 4610 #define SYS_GPA_MFP0_PA1MFP_Msk (0x1ful << SYS_GPA_MFP0_PA1MFP_Pos) /*!< SYS_T::GPA_MFP0: PA1MFP Mask */ 4611 4612 #define SYS_GPA_MFP0_PA2MFP_Pos (16) /*!< SYS_T::GPA_MFP0: PA2MFP Position */ 4613 #define SYS_GPA_MFP0_PA2MFP_Msk (0x1ful << SYS_GPA_MFP0_PA2MFP_Pos) /*!< SYS_T::GPA_MFP0: PA2MFP Mask */ 4614 4615 #define SYS_GPA_MFP0_PA3MFP_Pos (24) /*!< SYS_T::GPA_MFP0: PA3MFP Position */ 4616 #define SYS_GPA_MFP0_PA3MFP_Msk (0x1ful << SYS_GPA_MFP0_PA3MFP_Pos) /*!< SYS_T::GPA_MFP0: PA3MFP Mask */ 4617 4618 #define SYS_GPA_MFP1_PA4MFP_Pos (0) /*!< SYS_T::GPA_MFP1: PA4MFP Position */ 4619 #define SYS_GPA_MFP1_PA4MFP_Msk (0x1ful << SYS_GPA_MFP1_PA4MFP_Pos) /*!< SYS_T::GPA_MFP1: PA4MFP Mask */ 4620 4621 #define SYS_GPA_MFP1_PA5MFP_Pos (8) /*!< SYS_T::GPA_MFP1: PA5MFP Position */ 4622 #define SYS_GPA_MFP1_PA5MFP_Msk (0x1ful << SYS_GPA_MFP1_PA5MFP_Pos) /*!< SYS_T::GPA_MFP1: PA5MFP Mask */ 4623 4624 #define SYS_GPA_MFP1_PA6MFP_Pos (16) /*!< SYS_T::GPA_MFP1: PA6MFP Position */ 4625 #define SYS_GPA_MFP1_PA6MFP_Msk (0x1ful << SYS_GPA_MFP1_PA6MFP_Pos) /*!< SYS_T::GPA_MFP1: PA6MFP Mask */ 4626 4627 #define SYS_GPA_MFP1_PA7MFP_Pos (24) /*!< SYS_T::GPA_MFP1: PA7MFP Position */ 4628 #define SYS_GPA_MFP1_PA7MFP_Msk (0x1ful << SYS_GPA_MFP1_PA7MFP_Pos) /*!< SYS_T::GPA_MFP1: PA7MFP Mask */ 4629 4630 #define SYS_GPA_MFP2_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFP2: PA8MFP Position */ 4631 #define SYS_GPA_MFP2_PA8MFP_Msk (0x1ful << SYS_GPA_MFP2_PA8MFP_Pos) /*!< SYS_T::GPA_MFP2: PA8MFP Mask */ 4632 4633 #define SYS_GPA_MFP2_PA9MFP_Pos (8) /*!< SYS_T::GPA_MFP2: PA9MFP Position */ 4634 #define SYS_GPA_MFP2_PA9MFP_Msk (0x1ful << SYS_GPA_MFP2_PA9MFP_Pos) /*!< SYS_T::GPA_MFP2: PA9MFP Mask */ 4635 4636 #define SYS_GPA_MFP2_PA10MFP_Pos (16) /*!< SYS_T::GPA_MFP2: PA10MFP Position */ 4637 #define SYS_GPA_MFP2_PA10MFP_Msk (0x1ful << SYS_GPA_MFP2_PA10MFP_Pos) /*!< SYS_T::GPA_MFP2: PA10MFP Mask */ 4638 4639 #define SYS_GPA_MFP2_PA11MFP_Pos (24) /*!< SYS_T::GPA_MFP2: PA11MFP Position */ 4640 #define SYS_GPA_MFP2_PA11MFP_Msk (0x1ful << SYS_GPA_MFP2_PA11MFP_Pos) /*!< SYS_T::GPA_MFP2: PA11MFP Mask */ 4641 4642 #define SYS_GPA_MFP3_PA12MFP_Pos (0) /*!< SYS_T::GPA_MFP3: PA12MFP Position */ 4643 #define SYS_GPA_MFP3_PA12MFP_Msk (0x1ful << SYS_GPA_MFP3_PA12MFP_Pos) /*!< SYS_T::GPA_MFP3: PA12MFP Mask */ 4644 4645 #define SYS_GPA_MFP3_PA13MFP_Pos (8) /*!< SYS_T::GPA_MFP3: PA13MFP Position */ 4646 #define SYS_GPA_MFP3_PA13MFP_Msk (0x1ful << SYS_GPA_MFP3_PA13MFP_Pos) /*!< SYS_T::GPA_MFP3: PA13MFP Mask */ 4647 4648 #define SYS_GPA_MFP3_PA14MFP_Pos (16) /*!< SYS_T::GPA_MFP3: PA14MFP Position */ 4649 #define SYS_GPA_MFP3_PA14MFP_Msk (0x1ful << SYS_GPA_MFP3_PA14MFP_Pos) /*!< SYS_T::GPA_MFP3: PA14MFP Mask */ 4650 4651 #define SYS_GPA_MFP3_PA15MFP_Pos (24) /*!< SYS_T::GPA_MFP3: PA15MFP Position */ 4652 #define SYS_GPA_MFP3_PA15MFP_Msk (0x1ful << SYS_GPA_MFP3_PA15MFP_Pos) /*!< SYS_T::GPA_MFP3: PA15MFP Mask */ 4653 4654 #define SYS_GPB_MFP0_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFP0: PB0MFP Position */ 4655 #define SYS_GPB_MFP0_PB0MFP_Msk (0x1ful << SYS_GPB_MFP0_PB0MFP_Pos) /*!< SYS_T::GPB_MFP0: PB0MFP Mask */ 4656 4657 #define SYS_GPB_MFP0_PB1MFP_Pos (8) /*!< SYS_T::GPB_MFP0: PB1MFP Position */ 4658 #define SYS_GPB_MFP0_PB1MFP_Msk (0x1ful << SYS_GPB_MFP0_PB1MFP_Pos) /*!< SYS_T::GPB_MFP0: PB1MFP Mask */ 4659 4660 #define SYS_GPB_MFP0_PB2MFP_Pos (16) /*!< SYS_T::GPB_MFP0: PB2MFP Position */ 4661 #define SYS_GPB_MFP0_PB2MFP_Msk (0x1ful << SYS_GPB_MFP0_PB2MFP_Pos) /*!< SYS_T::GPB_MFP0: PB2MFP Mask */ 4662 4663 #define SYS_GPB_MFP0_PB3MFP_Pos (24) /*!< SYS_T::GPB_MFP0: PB3MFP Position */ 4664 #define SYS_GPB_MFP0_PB3MFP_Msk (0x1ful << SYS_GPB_MFP0_PB3MFP_Pos) /*!< SYS_T::GPB_MFP0: PB3MFP Mask */ 4665 4666 #define SYS_GPB_MFP1_PB4MFP_Pos (0) /*!< SYS_T::GPB_MFP1: PB4MFP Position */ 4667 #define SYS_GPB_MFP1_PB4MFP_Msk (0x1ful << SYS_GPB_MFP1_PB4MFP_Pos) /*!< SYS_T::GPB_MFP1: PB4MFP Mask */ 4668 4669 #define SYS_GPB_MFP1_PB5MFP_Pos (8) /*!< SYS_T::GPB_MFP1: PB5MFP Position */ 4670 #define SYS_GPB_MFP1_PB5MFP_Msk (0x1ful << SYS_GPB_MFP1_PB5MFP_Pos) /*!< SYS_T::GPB_MFP1: PB5MFP Mask */ 4671 4672 #define SYS_GPB_MFP1_PB6MFP_Pos (16) /*!< SYS_T::GPB_MFP1: PB6MFP Position */ 4673 #define SYS_GPB_MFP1_PB6MFP_Msk (0x1ful << SYS_GPB_MFP1_PB6MFP_Pos) /*!< SYS_T::GPB_MFP1: PB6MFP Mask */ 4674 4675 #define SYS_GPB_MFP1_PB7MFP_Pos (24) /*!< SYS_T::GPB_MFP1: PB7MFP Position */ 4676 #define SYS_GPB_MFP1_PB7MFP_Msk (0x1ful << SYS_GPB_MFP1_PB7MFP_Pos) /*!< SYS_T::GPB_MFP1: PB7MFP Mask */ 4677 4678 #define SYS_GPB_MFP2_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFP2: PB8MFP Position */ 4679 #define SYS_GPB_MFP2_PB8MFP_Msk (0x1ful << SYS_GPB_MFP2_PB8MFP_Pos) /*!< SYS_T::GPB_MFP2: PB8MFP Mask */ 4680 4681 #define SYS_GPB_MFP2_PB9MFP_Pos (8) /*!< SYS_T::GPB_MFP2: PB9MFP Position */ 4682 #define SYS_GPB_MFP2_PB9MFP_Msk (0x1ful << SYS_GPB_MFP2_PB9MFP_Pos) /*!< SYS_T::GPB_MFP2: PB9MFP Mask */ 4683 4684 #define SYS_GPB_MFP2_PB10MFP_Pos (16) /*!< SYS_T::GPB_MFP2: PB10MFP Position */ 4685 #define SYS_GPB_MFP2_PB10MFP_Msk (0x1ful << SYS_GPB_MFP2_PB10MFP_Pos) /*!< SYS_T::GPB_MFP2: PB10MFP Mask */ 4686 4687 #define SYS_GPB_MFP2_PB11MFP_Pos (24) /*!< SYS_T::GPB_MFP2: PB11MFP Position */ 4688 #define SYS_GPB_MFP2_PB11MFP_Msk (0x1ful << SYS_GPB_MFP2_PB11MFP_Pos) /*!< SYS_T::GPB_MFP2: PB11MFP Mask */ 4689 4690 #define SYS_GPB_MFP3_PB12MFP_Pos (0) /*!< SYS_T::GPB_MFP3: PB12MFP Position */ 4691 #define SYS_GPB_MFP3_PB12MFP_Msk (0x1ful << SYS_GPB_MFP3_PB12MFP_Pos) /*!< SYS_T::GPB_MFP3: PB12MFP Mask */ 4692 4693 #define SYS_GPB_MFP3_PB13MFP_Pos (8) /*!< SYS_T::GPB_MFP3: PB13MFP Position */ 4694 #define SYS_GPB_MFP3_PB13MFP_Msk (0x1ful << SYS_GPB_MFP3_PB13MFP_Pos) /*!< SYS_T::GPB_MFP3: PB13MFP Mask */ 4695 4696 #define SYS_GPB_MFP3_PB14MFP_Pos (16) /*!< SYS_T::GPB_MFP3: PB14MFP Position */ 4697 #define SYS_GPB_MFP3_PB14MFP_Msk (0x1ful << SYS_GPB_MFP3_PB14MFP_Pos) /*!< SYS_T::GPB_MFP3: PB14MFP Mask */ 4698 4699 #define SYS_GPB_MFP3_PB15MFP_Pos (24) /*!< SYS_T::GPB_MFP3: PB15MFP Position */ 4700 #define SYS_GPB_MFP3_PB15MFP_Msk (0x1ful << SYS_GPB_MFP3_PB15MFP_Pos) /*!< SYS_T::GPB_MFP3: PB15MFP Mask */ 4701 4702 #define SYS_GPC_MFP0_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFP0: PC0MFP Position */ 4703 #define SYS_GPC_MFP0_PC0MFP_Msk (0x1ful << SYS_GPC_MFP0_PC0MFP_Pos) /*!< SYS_T::GPC_MFP0: PC0MFP Mask */ 4704 4705 #define SYS_GPC_MFP0_PC1MFP_Pos (8) /*!< SYS_T::GPC_MFP0: PC1MFP Position */ 4706 #define SYS_GPC_MFP0_PC1MFP_Msk (0x1ful << SYS_GPC_MFP0_PC1MFP_Pos) /*!< SYS_T::GPC_MFP0: PC1MFP Mask */ 4707 4708 #define SYS_GPC_MFP0_PC2MFP_Pos (16) /*!< SYS_T::GPC_MFP0: PC2MFP Position */ 4709 #define SYS_GPC_MFP0_PC2MFP_Msk (0x1ful << SYS_GPC_MFP0_PC2MFP_Pos) /*!< SYS_T::GPC_MFP0: PC2MFP Mask */ 4710 4711 #define SYS_GPC_MFP0_PC3MFP_Pos (24) /*!< SYS_T::GPC_MFP0: PC3MFP Position */ 4712 #define SYS_GPC_MFP0_PC3MFP_Msk (0x1ful << SYS_GPC_MFP0_PC3MFP_Pos) /*!< SYS_T::GPC_MFP0: PC3MFP Mask */ 4713 4714 #define SYS_GPC_MFP1_PC4MFP_Pos (0) /*!< SYS_T::GPC_MFP1: PC4MFP Position */ 4715 #define SYS_GPC_MFP1_PC4MFP_Msk (0x1ful << SYS_GPC_MFP1_PC4MFP_Pos) /*!< SYS_T::GPC_MFP1: PC4MFP Mask */ 4716 4717 #define SYS_GPC_MFP1_PC5MFP_Pos (8) /*!< SYS_T::GPC_MFP1: PC5MFP Position */ 4718 #define SYS_GPC_MFP1_PC5MFP_Msk (0x1ful << SYS_GPC_MFP1_PC5MFP_Pos) /*!< SYS_T::GPC_MFP1: PC5MFP Mask */ 4719 4720 #define SYS_GPC_MFP1_PC6MFP_Pos (16) /*!< SYS_T::GPC_MFP1: PC6MFP Position */ 4721 #define SYS_GPC_MFP1_PC6MFP_Msk (0x1ful << SYS_GPC_MFP1_PC6MFP_Pos) /*!< SYS_T::GPC_MFP1: PC6MFP Mask */ 4722 4723 #define SYS_GPC_MFP1_PC7MFP_Pos (24) /*!< SYS_T::GPC_MFP1: PC7MFP Position */ 4724 #define SYS_GPC_MFP1_PC7MFP_Msk (0x1ful << SYS_GPC_MFP1_PC7MFP_Pos) /*!< SYS_T::GPC_MFP1: PC7MFP Mask */ 4725 4726 #define SYS_GPC_MFP2_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFP2: PC8MFP Position */ 4727 #define SYS_GPC_MFP2_PC8MFP_Msk (0x1ful << SYS_GPC_MFP2_PC8MFP_Pos) /*!< SYS_T::GPC_MFP2: PC8MFP Mask */ 4728 4729 #define SYS_GPC_MFP2_PC9MFP_Pos (8) /*!< SYS_T::GPC_MFP2: PC9MFP Position */ 4730 #define SYS_GPC_MFP2_PC9MFP_Msk (0x1ful << SYS_GPC_MFP2_PC9MFP_Pos) /*!< SYS_T::GPC_MFP2: PC9MFP Mask */ 4731 4732 #define SYS_GPC_MFP2_PC10MFP_Pos (16) /*!< SYS_T::GPC_MFP2: PC10MFP Position */ 4733 #define SYS_GPC_MFP2_PC10MFP_Msk (0x1ful << SYS_GPC_MFP2_PC10MFP_Pos) /*!< SYS_T::GPC_MFP2: PC10MFP Mask */ 4734 4735 #define SYS_GPC_MFP2_PC11MFP_Pos (24) /*!< SYS_T::GPC_MFP2: PC11MFP Position */ 4736 #define SYS_GPC_MFP2_PC11MFP_Msk (0x1ful << SYS_GPC_MFP2_PC11MFP_Pos) /*!< SYS_T::GPC_MFP2: PC11MFP Mask */ 4737 4738 #define SYS_GPC_MFP3_PC12MFP_Pos (0) /*!< SYS_T::GPC_MFP3: PC12MFP Position */ 4739 #define SYS_GPC_MFP3_PC12MFP_Msk (0x1ful << SYS_GPC_MFP3_PC12MFP_Pos) /*!< SYS_T::GPC_MFP3: PC12MFP Mask */ 4740 4741 #define SYS_GPC_MFP3_PC13MFP_Pos (8) /*!< SYS_T::GPC_MFP3: PC13MFP Position */ 4742 #define SYS_GPC_MFP3_PC13MFP_Msk (0x1ful << SYS_GPC_MFP3_PC13MFP_Pos) /*!< SYS_T::GPC_MFP3: PC13MFP Mask */ 4743 4744 #define SYS_GPC_MFP3_PC14MFP_Pos (16) /*!< SYS_T::GPC_MFP3: PC14MFP Position */ 4745 #define SYS_GPC_MFP3_PC14MFP_Msk (0x1ful << SYS_GPC_MFP3_PC14MFP_Pos) /*!< SYS_T::GPC_MFP3: PC14MFP Mask */ 4746 4747 #define SYS_GPD_MFP0_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFP0: PD0MFP Position */ 4748 #define SYS_GPD_MFP0_PD0MFP_Msk (0x1ful << SYS_GPD_MFP0_PD0MFP_Pos) /*!< SYS_T::GPD_MFP0: PD0MFP Mask */ 4749 4750 #define SYS_GPD_MFP0_PD1MFP_Pos (8) /*!< SYS_T::GPD_MFP0: PD1MFP Position */ 4751 #define SYS_GPD_MFP0_PD1MFP_Msk (0x1ful << SYS_GPD_MFP0_PD1MFP_Pos) /*!< SYS_T::GPD_MFP0: PD1MFP Mask */ 4752 4753 #define SYS_GPD_MFP0_PD2MFP_Pos (16) /*!< SYS_T::GPD_MFP0: PD2MFP Position */ 4754 #define SYS_GPD_MFP0_PD2MFP_Msk (0x1ful << SYS_GPD_MFP0_PD2MFP_Pos) /*!< SYS_T::GPD_MFP0: PD2MFP Mask */ 4755 4756 #define SYS_GPD_MFP0_PD3MFP_Pos (24) /*!< SYS_T::GPD_MFP0: PD3MFP Position */ 4757 #define SYS_GPD_MFP0_PD3MFP_Msk (0x1ful << SYS_GPD_MFP0_PD3MFP_Pos) /*!< SYS_T::GPD_MFP0: PD3MFP Mask */ 4758 4759 #define SYS_GPD_MFP1_PD4MFP_Pos (0) /*!< SYS_T::GPD_MFP1: PD4MFP Position */ 4760 #define SYS_GPD_MFP1_PD4MFP_Msk (0x1ful << SYS_GPD_MFP1_PD4MFP_Pos) /*!< SYS_T::GPD_MFP1: PD4MFP Mask */ 4761 4762 #define SYS_GPD_MFP1_PD5MFP_Pos (8) /*!< SYS_T::GPD_MFP1: PD5MFP Position */ 4763 #define SYS_GPD_MFP1_PD5MFP_Msk (0x1ful << SYS_GPD_MFP1_PD5MFP_Pos) /*!< SYS_T::GPD_MFP1: PD5MFP Mask */ 4764 4765 #define SYS_GPD_MFP1_PD6MFP_Pos (16) /*!< SYS_T::GPD_MFP1: PD6MFP Position */ 4766 #define SYS_GPD_MFP1_PD6MFP_Msk (0x1ful << SYS_GPD_MFP1_PD6MFP_Pos) /*!< SYS_T::GPD_MFP1: PD6MFP Mask */ 4767 4768 #define SYS_GPD_MFP1_PD7MFP_Pos (24) /*!< SYS_T::GPD_MFP1: PD7MFP Position */ 4769 #define SYS_GPD_MFP1_PD7MFP_Msk (0x1ful << SYS_GPD_MFP1_PD7MFP_Pos) /*!< SYS_T::GPD_MFP1: PD7MFP Mask */ 4770 4771 #define SYS_GPD_MFP2_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFP2: PD8MFP Position */ 4772 #define SYS_GPD_MFP2_PD8MFP_Msk (0x1ful << SYS_GPD_MFP2_PD8MFP_Pos) /*!< SYS_T::GPD_MFP2: PD8MFP Mask */ 4773 4774 #define SYS_GPD_MFP2_PD9MFP_Pos (8) /*!< SYS_T::GPD_MFP2: PD9MFP Position */ 4775 #define SYS_GPD_MFP2_PD9MFP_Msk (0x1ful << SYS_GPD_MFP2_PD9MFP_Pos) /*!< SYS_T::GPD_MFP2: PD9MFP Mask */ 4776 4777 #define SYS_GPD_MFP2_PD10MFP_Pos (16) /*!< SYS_T::GPD_MFP2: PD10MFP Position */ 4778 #define SYS_GPD_MFP2_PD10MFP_Msk (0x1ful << SYS_GPD_MFP2_PD10MFP_Pos) /*!< SYS_T::GPD_MFP2: PD10MFP Mask */ 4779 4780 #define SYS_GPD_MFP2_PD11MFP_Pos (24) /*!< SYS_T::GPD_MFP2: PD11MFP Position */ 4781 #define SYS_GPD_MFP2_PD11MFP_Msk (0x1ful << SYS_GPD_MFP2_PD11MFP_Pos) /*!< SYS_T::GPD_MFP2: PD11MFP Mask */ 4782 4783 #define SYS_GPD_MFP3_PD12MFP_Pos (0) /*!< SYS_T::GPD_MFP3: PD12MFP Position */ 4784 #define SYS_GPD_MFP3_PD12MFP_Msk (0x1ful << SYS_GPD_MFP3_PD12MFP_Pos) /*!< SYS_T::GPD_MFP3: PD12MFP Mask */ 4785 4786 #define SYS_GPD_MFP3_PD13MFP_Pos (8) /*!< SYS_T::GPD_MFP3: PD13MFP Position */ 4787 #define SYS_GPD_MFP3_PD13MFP_Msk (0x1ful << SYS_GPD_MFP3_PD13MFP_Pos) /*!< SYS_T::GPD_MFP3: PD13MFP Mask */ 4788 4789 #define SYS_GPD_MFP3_PD14MFP_Pos (16) /*!< SYS_T::GPD_MFP3: PD14MFP Position */ 4790 #define SYS_GPD_MFP3_PD14MFP_Msk (0x1ful << SYS_GPD_MFP3_PD14MFP_Pos) /*!< SYS_T::GPD_MFP3: PD14MFP Mask */ 4791 4792 #define SYS_GPD_MFP3_PD15MFP_Pos (24) /*!< SYS_T::GPD_MFP3: PD15MFP Position */ 4793 #define SYS_GPD_MFP3_PD15MFP_Msk (0x1ful << SYS_GPD_MFP3_PD15MFP_Pos) /*!< SYS_T::GPD_MFP3: PD15MFP Mask */ 4794 4795 #define SYS_GPE_MFP0_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFP0: PE0MFP Position */ 4796 #define SYS_GPE_MFP0_PE0MFP_Msk (0x1ful << SYS_GPE_MFP0_PE0MFP_Pos) /*!< SYS_T::GPE_MFP0: PE0MFP Mask */ 4797 4798 #define SYS_GPE_MFP0_PE1MFP_Pos (8) /*!< SYS_T::GPE_MFP0: PE1MFP Position */ 4799 #define SYS_GPE_MFP0_PE1MFP_Msk (0x1ful << SYS_GPE_MFP0_PE1MFP_Pos) /*!< SYS_T::GPE_MFP0: PE1MFP Mask */ 4800 4801 #define SYS_GPE_MFP0_PE2MFP_Pos (16) /*!< SYS_T::GPE_MFP0: PE2MFP Position */ 4802 #define SYS_GPE_MFP0_PE2MFP_Msk (0x1ful << SYS_GPE_MFP0_PE2MFP_Pos) /*!< SYS_T::GPE_MFP0: PE2MFP Mask */ 4803 4804 #define SYS_GPE_MFP0_PE3MFP_Pos (24) /*!< SYS_T::GPE_MFP0: PE3MFP Position */ 4805 #define SYS_GPE_MFP0_PE3MFP_Msk (0x1ful << SYS_GPE_MFP0_PE3MFP_Pos) /*!< SYS_T::GPE_MFP0: PE3MFP Mask */ 4806 4807 #define SYS_GPE_MFP1_PE4MFP_Pos (0) /*!< SYS_T::GPE_MFP1: PE4MFP Position */ 4808 #define SYS_GPE_MFP1_PE4MFP_Msk (0x1ful << SYS_GPE_MFP1_PE4MFP_Pos) /*!< SYS_T::GPE_MFP1: PE4MFP Mask */ 4809 4810 #define SYS_GPE_MFP1_PE5MFP_Pos (8) /*!< SYS_T::GPE_MFP1: PE5MFP Position */ 4811 #define SYS_GPE_MFP1_PE5MFP_Msk (0x1ful << SYS_GPE_MFP1_PE5MFP_Pos) /*!< SYS_T::GPE_MFP1: PE5MFP Mask */ 4812 4813 #define SYS_GPE_MFP1_PE6MFP_Pos (16) /*!< SYS_T::GPE_MFP1: PE6MFP Position */ 4814 #define SYS_GPE_MFP1_PE6MFP_Msk (0x1ful << SYS_GPE_MFP1_PE6MFP_Pos) /*!< SYS_T::GPE_MFP1: PE6MFP Mask */ 4815 4816 #define SYS_GPE_MFP1_PE7MFP_Pos (24) /*!< SYS_T::GPE_MFP1: PE7MFP Position */ 4817 #define SYS_GPE_MFP1_PE7MFP_Msk (0x1ful << SYS_GPE_MFP1_PE7MFP_Pos) /*!< SYS_T::GPE_MFP1: PE7MFP Mask */ 4818 4819 #define SYS_GPE_MFP2_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFP2: PE8MFP Position */ 4820 #define SYS_GPE_MFP2_PE8MFP_Msk (0x1ful << SYS_GPE_MFP2_PE8MFP_Pos) /*!< SYS_T::GPE_MFP2: PE8MFP Mask */ 4821 4822 #define SYS_GPE_MFP2_PE9MFP_Pos (8) /*!< SYS_T::GPE_MFP2: PE9MFP Position */ 4823 #define SYS_GPE_MFP2_PE9MFP_Msk (0x1ful << SYS_GPE_MFP2_PE9MFP_Pos) /*!< SYS_T::GPE_MFP2: PE9MFP Mask */ 4824 4825 #define SYS_GPE_MFP2_PE10MFP_Pos (16) /*!< SYS_T::GPE_MFP2: PE10MFP Position */ 4826 #define SYS_GPE_MFP2_PE10MFP_Msk (0x1ful << SYS_GPE_MFP2_PE10MFP_Pos) /*!< SYS_T::GPE_MFP2: PE10MFP Mask */ 4827 4828 #define SYS_GPE_MFP2_PE11MFP_Pos (24) /*!< SYS_T::GPE_MFP2: PE11MFP Position */ 4829 #define SYS_GPE_MFP2_PE11MFP_Msk (0x1ful << SYS_GPE_MFP2_PE11MFP_Pos) /*!< SYS_T::GPE_MFP2: PE11MFP Mask */ 4830 4831 #define SYS_GPE_MFP3_PE12MFP_Pos (0) /*!< SYS_T::GPE_MFP3: PE12MFP Position */ 4832 #define SYS_GPE_MFP3_PE12MFP_Msk (0x1ful << SYS_GPE_MFP3_PE12MFP_Pos) /*!< SYS_T::GPE_MFP3: PE12MFP Mask */ 4833 4834 #define SYS_GPE_MFP3_PE13MFP_Pos (8) /*!< SYS_T::GPE_MFP3: PE13MFP Position */ 4835 #define SYS_GPE_MFP3_PE13MFP_Msk (0x1ful << SYS_GPE_MFP3_PE13MFP_Pos) /*!< SYS_T::GPE_MFP3: PE13MFP Mask */ 4836 4837 #define SYS_GPE_MFP3_PE14MFP_Pos (16) /*!< SYS_T::GPE_MFP3: PE14MFP Position */ 4838 #define SYS_GPE_MFP3_PE14MFP_Msk (0x1ful << SYS_GPE_MFP3_PE14MFP_Pos) /*!< SYS_T::GPE_MFP3: PE14MFP Mask */ 4839 4840 #define SYS_GPE_MFP3_PE15MFP_Pos (24) /*!< SYS_T::GPE_MFP3: PE15MFP Position */ 4841 #define SYS_GPE_MFP3_PE15MFP_Msk (0x1ful << SYS_GPE_MFP3_PE15MFP_Pos) /*!< SYS_T::GPE_MFP3: PE15MFP Mask */ 4842 4843 #define SYS_GPF_MFP0_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFP0: PF0MFP Position */ 4844 #define SYS_GPF_MFP0_PF0MFP_Msk (0x1ful << SYS_GPF_MFP0_PF0MFP_Pos) /*!< SYS_T::GPF_MFP0: PF0MFP Mask */ 4845 4846 #define SYS_GPF_MFP0_PF1MFP_Pos (8) /*!< SYS_T::GPF_MFP0: PF1MFP Position */ 4847 #define SYS_GPF_MFP0_PF1MFP_Msk (0x1ful << SYS_GPF_MFP0_PF1MFP_Pos) /*!< SYS_T::GPF_MFP0: PF1MFP Mask */ 4848 4849 #define SYS_GPF_MFP0_PF2MFP_Pos (16) /*!< SYS_T::GPF_MFP0: PF2MFP Position */ 4850 #define SYS_GPF_MFP0_PF2MFP_Msk (0x1ful << SYS_GPF_MFP0_PF2MFP_Pos) /*!< SYS_T::GPF_MFP0: PF2MFP Mask */ 4851 4852 #define SYS_GPF_MFP0_PF3MFP_Pos (24) /*!< SYS_T::GPF_MFP0: PF3MFP Position */ 4853 #define SYS_GPF_MFP0_PF3MFP_Msk (0x1ful << SYS_GPF_MFP0_PF3MFP_Pos) /*!< SYS_T::GPF_MFP0: PF3MFP Mask */ 4854 4855 #define SYS_GPF_MFP1_PF4MFP_Pos (0) /*!< SYS_T::GPF_MFP1: PF4MFP Position */ 4856 #define SYS_GPF_MFP1_PF4MFP_Msk (0x1ful << SYS_GPF_MFP1_PF4MFP_Pos) /*!< SYS_T::GPF_MFP1: PF4MFP Mask */ 4857 4858 #define SYS_GPF_MFP1_PF5MFP_Pos (8) /*!< SYS_T::GPF_MFP1: PF5MFP Position */ 4859 #define SYS_GPF_MFP1_PF5MFP_Msk (0x1ful << SYS_GPF_MFP1_PF5MFP_Pos) /*!< SYS_T::GPF_MFP1: PF5MFP Mask */ 4860 4861 #define SYS_GPF_MFP1_PF6MFP_Pos (16) /*!< SYS_T::GPF_MFP1: PF6MFP Position */ 4862 #define SYS_GPF_MFP1_PF6MFP_Msk (0x1ful << SYS_GPF_MFP1_PF6MFP_Pos) /*!< SYS_T::GPF_MFP1: PF6MFP Mask */ 4863 4864 #define SYS_GPF_MFP1_PF7MFP_Pos (24) /*!< SYS_T::GPF_MFP1: PF7MFP Position */ 4865 #define SYS_GPF_MFP1_PF7MFP_Msk (0x1ful << SYS_GPF_MFP1_PF7MFP_Pos) /*!< SYS_T::GPF_MFP1: PF7MFP Mask */ 4866 4867 #define SYS_GPF_MFP2_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFP2: PF8MFP Position */ 4868 #define SYS_GPF_MFP2_PF8MFP_Msk (0x1ful << SYS_GPF_MFP2_PF8MFP_Pos) /*!< SYS_T::GPF_MFP2: PF8MFP Mask */ 4869 4870 #define SYS_GPF_MFP2_PF9MFP_Pos (8) /*!< SYS_T::GPF_MFP2: PF9MFP Position */ 4871 #define SYS_GPF_MFP2_PF9MFP_Msk (0x1ful << SYS_GPF_MFP2_PF9MFP_Pos) /*!< SYS_T::GPF_MFP2: PF9MFP Mask */ 4872 4873 #define SYS_GPF_MFP2_PF10MFP_Pos (16) /*!< SYS_T::GPF_MFP2: PF10MFP Position */ 4874 #define SYS_GPF_MFP2_PF10MFP_Msk (0x1ful << SYS_GPF_MFP2_PF10MFP_Pos) /*!< SYS_T::GPF_MFP2: PF10MFP Mask */ 4875 4876 #define SYS_GPF_MFP2_PF11MFP_Pos (24) /*!< SYS_T::GPF_MFP2: PF11MFP Position */ 4877 #define SYS_GPF_MFP2_PF11MFP_Msk (0x1ful << SYS_GPF_MFP2_PF11MFP_Pos) /*!< SYS_T::GPF_MFP2: PF11MFP Mask */ 4878 4879 #define SYS_GPG_MFP0_PG2MFP_Pos (16) /*!< SYS_T::GPG_MFP0: PG2MFP Position */ 4880 #define SYS_GPG_MFP0_PG2MFP_Msk (0x1ful << SYS_GPG_MFP0_PG2MFP_Pos) /*!< SYS_T::GPG_MFP0: PG2MFP Mask */ 4881 4882 #define SYS_GPG_MFP0_PG3MFP_Pos (24) /*!< SYS_T::GPG_MFP0: PG3MFP Position */ 4883 #define SYS_GPG_MFP0_PG3MFP_Msk (0x1ful << SYS_GPG_MFP0_PG3MFP_Pos) /*!< SYS_T::GPG_MFP0: PG3MFP Mask */ 4884 4885 #define SYS_GPG_MFP1_PG4MFP_Pos (0) /*!< SYS_T::GPG_MFP1: PG4MFP Position */ 4886 #define SYS_GPG_MFP1_PG4MFP_Msk (0x1ful << SYS_GPG_MFP1_PG4MFP_Pos) /*!< SYS_T::GPG_MFP1: PG4MFP Mask */ 4887 4888 #define SYS_GPG_MFP2_PG9MFP_Pos (8) /*!< SYS_T::GPG_MFP2: PG9MFP Position */ 4889 #define SYS_GPG_MFP2_PG9MFP_Msk (0x1ful << SYS_GPG_MFP2_PG9MFP_Pos) /*!< SYS_T::GPG_MFP2: PG9MFP Mask */ 4890 4891 #define SYS_GPG_MFP2_PG10MFP_Pos (16) /*!< SYS_T::GPG_MFP2: PG10MFP Position */ 4892 #define SYS_GPG_MFP2_PG10MFP_Msk (0x1ful << SYS_GPG_MFP2_PG10MFP_Pos) /*!< SYS_T::GPG_MFP2: PG10MFP Mask */ 4893 4894 #define SYS_GPG_MFP2_PG11MFP_Pos (24) /*!< SYS_T::GPG_MFP2: PG11MFP Position */ 4895 #define SYS_GPG_MFP2_PG11MFP_Msk (0x1ful << SYS_GPG_MFP2_PG11MFP_Pos) /*!< SYS_T::GPG_MFP2: PG11MFP Mask */ 4896 4897 #define SYS_GPG_MFP3_PG12MFP_Pos (0) /*!< SYS_T::GPG_MFP3: PG12MFP Position */ 4898 #define SYS_GPG_MFP3_PG12MFP_Msk (0x1ful << SYS_GPG_MFP3_PG12MFP_Pos) /*!< SYS_T::GPG_MFP3: PG12MFP Mask */ 4899 4900 #define SYS_GPG_MFP3_PG13MFP_Pos (8) /*!< SYS_T::GPG_MFP3: PG13MFP Position */ 4901 #define SYS_GPG_MFP3_PG13MFP_Msk (0x1ful << SYS_GPG_MFP3_PG13MFP_Pos) /*!< SYS_T::GPG_MFP3: PG13MFP Mask */ 4902 4903 #define SYS_GPG_MFP3_PG14MFP_Pos (16) /*!< SYS_T::GPG_MFP3: PG14MFP Position */ 4904 #define SYS_GPG_MFP3_PG14MFP_Msk (0x1ful << SYS_GPG_MFP3_PG14MFP_Pos) /*!< SYS_T::GPG_MFP3: PG14MFP Mask */ 4905 4906 #define SYS_GPG_MFP3_PG15MFP_Pos (24) /*!< SYS_T::GPG_MFP3: PG15MFP Position */ 4907 #define SYS_GPG_MFP3_PG15MFP_Msk (0x1ful << SYS_GPG_MFP3_PG15MFP_Pos) /*!< SYS_T::GPG_MFP3: PG15MFP Mask */ 4908 4909 #define SYS_GPH_MFP1_PH4MFP_Pos (0) /*!< SYS_T::GPH_MFP1: PH4MFP Position */ 4910 #define SYS_GPH_MFP1_PH4MFP_Msk (0x1ful << SYS_GPH_MFP1_PH4MFP_Pos) /*!< SYS_T::GPH_MFP1: PH4MFP Mask */ 4911 4912 #define SYS_GPH_MFP1_PH5MFP_Pos (8) /*!< SYS_T::GPH_MFP1: PH5MFP Position */ 4913 #define SYS_GPH_MFP1_PH5MFP_Msk (0x1ful << SYS_GPH_MFP1_PH5MFP_Pos) /*!< SYS_T::GPH_MFP1: PH5MFP Mask */ 4914 4915 #define SYS_GPH_MFP1_PH6MFP_Pos (16) /*!< SYS_T::GPH_MFP1: PH6MFP Position */ 4916 #define SYS_GPH_MFP1_PH6MFP_Msk (0x1ful << SYS_GPH_MFP1_PH6MFP_Pos) /*!< SYS_T::GPH_MFP1: PH6MFP Mask */ 4917 4918 #define SYS_GPH_MFP1_PH7MFP_Pos (24) /*!< SYS_T::GPH_MFP1: PH7MFP Position */ 4919 #define SYS_GPH_MFP1_PH7MFP_Msk (0x1ful << SYS_GPH_MFP1_PH7MFP_Pos) /*!< SYS_T::GPH_MFP1: PH7MFP Mask */ 4920 4921 #define SYS_GPH_MFP2_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFP2: PH8MFP Position */ 4922 #define SYS_GPH_MFP2_PH8MFP_Msk (0x1ful << SYS_GPH_MFP2_PH8MFP_Pos) /*!< SYS_T::GPH_MFP2: PH8MFP Mask */ 4923 4924 #define SYS_GPH_MFP2_PH9MFP_Pos (8) /*!< SYS_T::GPH_MFP2: PH9MFP Position */ 4925 #define SYS_GPH_MFP2_PH9MFP_Msk (0x1ful << SYS_GPH_MFP2_PH9MFP_Pos) /*!< SYS_T::GPH_MFP2: PH9MFP Mask */ 4926 4927 #define SYS_GPH_MFP2_PH10MFP_Pos (16) /*!< SYS_T::GPH_MFP2: PH10MFP Position */ 4928 #define SYS_GPH_MFP2_PH10MFP_Msk (0x1ful << SYS_GPH_MFP2_PH10MFP_Pos) /*!< SYS_T::GPH_MFP2: PH10MFP Mask */ 4929 4930 #define SYS_GPH_MFP2_PH11MFP_Pos (24) /*!< SYS_T::GPH_MFP2: PH11MFP Position */ 4931 #define SYS_GPH_MFP2_PH11MFP_Msk (0x1ful << SYS_GPH_MFP2_PH11MFP_Pos) /*!< SYS_T::GPH_MFP2: PH11MFP Mask */ 4932 4933 /**@}*/ /* SYS_CONST */ 4934 /**@}*/ /* end of SYS register group */ 4935 /**@}*/ /* end of REGISTER group */ 4936 4937 #if defined ( __CC_ARM ) 4938 #pragma no_anon_unions 4939 #endif 4940 4941 #endif /* __SYS_REG_H__ */ 4942
